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Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_95 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_95( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_48 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_48( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_134 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_148 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_134( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_148 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_19 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[12] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 node _source_ok_T_32 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[2]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[3]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[4]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[5]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[6]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[7]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[8]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[9]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[10]) node source_ok = or(_source_ok_T_41, _source_ok_WIRE[11]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = and(_T_11, _T_24) node _T_121 = and(_T_120, _T_37) node _T_122 = and(_T_121, _T_50) node _T_123 = and(_T_122, _T_63) node _T_124 = and(_T_123, _T_71) node _T_125 = and(_T_124, _T_79) node _T_126 = and(_T_125, _T_87) node _T_127 = and(_T_126, _T_95) node _T_128 = and(_T_127, _T_103) node _T_129 = and(_T_128, _T_111) node _T_130 = and(_T_129, _T_119) node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(_T_130, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_130, UInt<1>(0h1), "") : assert_1 node _T_134 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_134 : node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_136 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_139 = shr(io.in.a.bits.source, 2) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = leq(UInt<1>(0h0), uncommonBits_4) node _T_142 = and(_T_140, _T_141) node _T_143 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_144 = and(_T_142, _T_143) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_145 = shr(io.in.a.bits.source, 2) node _T_146 = eq(_T_145, UInt<1>(0h1)) node _T_147 = leq(UInt<1>(0h0), uncommonBits_5) node _T_148 = and(_T_146, _T_147) node _T_149 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_150 = and(_T_148, _T_149) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_151 = shr(io.in.a.bits.source, 2) node _T_152 = eq(_T_151, UInt<2>(0h2)) node _T_153 = leq(UInt<1>(0h0), uncommonBits_6) node _T_154 = and(_T_152, _T_153) node _T_155 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_156 = and(_T_154, _T_155) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_157 = shr(io.in.a.bits.source, 2) node _T_158 = eq(_T_157, UInt<2>(0h3)) node _T_159 = leq(UInt<1>(0h0), uncommonBits_7) node _T_160 = and(_T_158, _T_159) node _T_161 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_166 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_167 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_169 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_170 = or(_T_138, _T_144) node _T_171 = or(_T_170, _T_150) node _T_172 = or(_T_171, _T_156) node _T_173 = or(_T_172, _T_162) node _T_174 = or(_T_173, _T_163) node _T_175 = or(_T_174, _T_164) node _T_176 = or(_T_175, _T_165) node _T_177 = or(_T_176, _T_166) node _T_178 = or(_T_177, _T_167) node _T_179 = or(_T_178, _T_168) node _T_180 = or(_T_179, _T_169) node _T_181 = and(_T_137, _T_180) node _T_182 = or(UInt<1>(0h0), _T_181) node _T_183 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_184 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<14>(0h2000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<13>(0h1000))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<17>(0h10000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<18>(0h2f000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<17>(0h10000))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_210 = cvt(_T_209) node _T_211 = and(_T_210, asSInt(UInt<13>(0h1000))) node _T_212 = asSInt(_T_211) node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0))) node _T_214 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_215 = cvt(_T_214) node _T_216 = and(_T_215, asSInt(UInt<27>(0h4000000))) node _T_217 = asSInt(_T_216) node _T_218 = eq(_T_217, asSInt(UInt<1>(0h0))) node _T_219 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_220 = cvt(_T_219) node _T_221 = and(_T_220, asSInt(UInt<13>(0h1000))) node _T_222 = asSInt(_T_221) node _T_223 = eq(_T_222, asSInt(UInt<1>(0h0))) node _T_224 = or(_T_188, _T_193) node _T_225 = or(_T_224, _T_198) node _T_226 = or(_T_225, _T_203) node _T_227 = or(_T_226, _T_208) node _T_228 = or(_T_227, _T_213) node _T_229 = or(_T_228, _T_218) node _T_230 = or(_T_229, _T_223) node _T_231 = and(_T_183, _T_230) node _T_232 = or(UInt<1>(0h0), _T_231) node _T_233 = and(_T_182, _T_232) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_233, UInt<1>(0h1), "") : assert_2 node _T_237 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_238 = shr(io.in.a.bits.source, 2) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = leq(UInt<1>(0h0), uncommonBits_8) node _T_241 = and(_T_239, _T_240) node _T_242 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_243 = and(_T_241, _T_242) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_244 = shr(io.in.a.bits.source, 2) node _T_245 = eq(_T_244, UInt<1>(0h1)) node _T_246 = leq(UInt<1>(0h0), uncommonBits_9) node _T_247 = and(_T_245, _T_246) node _T_248 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_249 = and(_T_247, _T_248) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_250 = shr(io.in.a.bits.source, 2) node _T_251 = eq(_T_250, UInt<2>(0h2)) node _T_252 = leq(UInt<1>(0h0), uncommonBits_10) node _T_253 = and(_T_251, _T_252) node _T_254 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_255 = and(_T_253, _T_254) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_256 = shr(io.in.a.bits.source, 2) node _T_257 = eq(_T_256, UInt<2>(0h3)) node _T_258 = leq(UInt<1>(0h0), uncommonBits_11) node _T_259 = and(_T_257, _T_258) node _T_260 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_261 = and(_T_259, _T_260) node _T_262 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_263 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_265 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_266 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_267 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_268 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[12] connect _WIRE[0], _T_237 connect _WIRE[1], _T_243 connect _WIRE[2], _T_249 connect _WIRE[3], _T_255 connect _WIRE[4], _T_261 connect _WIRE[5], _T_262 connect _WIRE[6], _T_263 connect _WIRE[7], _T_264 connect _WIRE[8], _T_265 connect _WIRE[9], _T_266 connect _WIRE[10], _T_267 connect _WIRE[11], _T_268 node _T_269 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_270 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_271 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_272 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_273 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_274 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_275 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_276 = mux(_WIRE[5], _T_269, UInt<1>(0h0)) node _T_277 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_278 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_279 = mux(_WIRE[8], _T_270, UInt<1>(0h0)) node _T_280 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_281 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_282 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = or(_T_271, _T_272) node _T_284 = or(_T_283, _T_273) node _T_285 = or(_T_284, _T_274) node _T_286 = or(_T_285, _T_275) node _T_287 = or(_T_286, _T_276) node _T_288 = or(_T_287, _T_277) node _T_289 = or(_T_288, _T_278) node _T_290 = or(_T_289, _T_279) node _T_291 = or(_T_290, _T_280) node _T_292 = or(_T_291, _T_281) node _T_293 = or(_T_292, _T_282) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_293 node _T_294 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_295 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_296 = and(_T_294, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<14>(0h2000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<18>(0h2f000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<17>(0h10000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<13>(0h1000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<27>(0h4000000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<13>(0h1000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = or(_T_302, _T_307) node _T_339 = or(_T_338, _T_312) node _T_340 = or(_T_339, _T_317) node _T_341 = or(_T_340, _T_322) node _T_342 = or(_T_341, _T_327) node _T_343 = or(_T_342, _T_332) node _T_344 = or(_T_343, _T_337) node _T_345 = and(_T_297, _T_344) node _T_346 = or(UInt<1>(0h0), _T_345) node _T_347 = and(_WIRE_1, _T_346) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_347, UInt<1>(0h1), "") : assert_3 node _T_351 = asUInt(reset) node _T_352 = eq(_T_351, UInt<1>(0h0)) when _T_352 : node _T_353 = eq(source_ok, UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_354 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_T_354, UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_354, UInt<1>(0h1), "") : assert_5 node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(is_aligned, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_361 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_361, UInt<1>(0h1), "") : assert_7 node _T_365 = not(io.in.a.bits.mask) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_366, UInt<1>(0h1), "") : assert_8 node _T_370 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(_T_370, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_370, UInt<1>(0h1), "") : assert_9 node _T_374 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_374 : node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_377 = and(_T_375, _T_376) node _T_378 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_379 = shr(io.in.a.bits.source, 2) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = leq(UInt<1>(0h0), uncommonBits_12) node _T_382 = and(_T_380, _T_381) node _T_383 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_384 = and(_T_382, _T_383) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_385 = shr(io.in.a.bits.source, 2) node _T_386 = eq(_T_385, UInt<1>(0h1)) node _T_387 = leq(UInt<1>(0h0), uncommonBits_13) node _T_388 = and(_T_386, _T_387) node _T_389 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_390 = and(_T_388, _T_389) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_391 = shr(io.in.a.bits.source, 2) node _T_392 = eq(_T_391, UInt<2>(0h2)) node _T_393 = leq(UInt<1>(0h0), uncommonBits_14) node _T_394 = and(_T_392, _T_393) node _T_395 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_396 = and(_T_394, _T_395) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_397 = shr(io.in.a.bits.source, 2) node _T_398 = eq(_T_397, UInt<2>(0h3)) node _T_399 = leq(UInt<1>(0h0), uncommonBits_15) node _T_400 = and(_T_398, _T_399) node _T_401 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_404 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_405 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_406 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_407 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_408 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_409 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_410 = or(_T_378, _T_384) node _T_411 = or(_T_410, _T_390) node _T_412 = or(_T_411, _T_396) node _T_413 = or(_T_412, _T_402) node _T_414 = or(_T_413, _T_403) node _T_415 = or(_T_414, _T_404) node _T_416 = or(_T_415, _T_405) node _T_417 = or(_T_416, _T_406) node _T_418 = or(_T_417, _T_407) node _T_419 = or(_T_418, _T_408) node _T_420 = or(_T_419, _T_409) node _T_421 = and(_T_377, _T_420) node _T_422 = or(UInt<1>(0h0), _T_421) node _T_423 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_424 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<14>(0h2000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<13>(0h1000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<17>(0h10000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<18>(0h2f000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_445 = cvt(_T_444) node _T_446 = and(_T_445, asSInt(UInt<17>(0h10000))) node _T_447 = asSInt(_T_446) node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) node _T_449 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_450 = cvt(_T_449) node _T_451 = and(_T_450, asSInt(UInt<13>(0h1000))) node _T_452 = asSInt(_T_451) node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0))) node _T_454 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_455 = cvt(_T_454) node _T_456 = and(_T_455, asSInt(UInt<27>(0h4000000))) node _T_457 = asSInt(_T_456) node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0))) node _T_459 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_460 = cvt(_T_459) node _T_461 = and(_T_460, asSInt(UInt<13>(0h1000))) node _T_462 = asSInt(_T_461) node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0))) node _T_464 = or(_T_428, _T_433) node _T_465 = or(_T_464, _T_438) node _T_466 = or(_T_465, _T_443) node _T_467 = or(_T_466, _T_448) node _T_468 = or(_T_467, _T_453) node _T_469 = or(_T_468, _T_458) node _T_470 = or(_T_469, _T_463) node _T_471 = and(_T_423, _T_470) node _T_472 = or(UInt<1>(0h0), _T_471) node _T_473 = and(_T_422, _T_472) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_473, UInt<1>(0h1), "") : assert_10 node _T_477 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_478 = shr(io.in.a.bits.source, 2) node _T_479 = eq(_T_478, UInt<1>(0h0)) node _T_480 = leq(UInt<1>(0h0), uncommonBits_16) node _T_481 = and(_T_479, _T_480) node _T_482 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_483 = and(_T_481, _T_482) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<1>(0h1)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_17) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<2>(0h2)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_18) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_496 = shr(io.in.a.bits.source, 2) node _T_497 = eq(_T_496, UInt<2>(0h3)) node _T_498 = leq(UInt<1>(0h0), uncommonBits_19) node _T_499 = and(_T_497, _T_498) node _T_500 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_503 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_504 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_505 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_506 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_507 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_508 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[12] connect _WIRE_2[0], _T_477 connect _WIRE_2[1], _T_483 connect _WIRE_2[2], _T_489 connect _WIRE_2[3], _T_495 connect _WIRE_2[4], _T_501 connect _WIRE_2[5], _T_502 connect _WIRE_2[6], _T_503 connect _WIRE_2[7], _T_504 connect _WIRE_2[8], _T_505 connect _WIRE_2[9], _T_506 connect _WIRE_2[10], _T_507 connect _WIRE_2[11], _T_508 node _T_509 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_510 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_511 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_512 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_513 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_515 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_516 = mux(_WIRE_2[5], _T_509, UInt<1>(0h0)) node _T_517 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_518 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_519 = mux(_WIRE_2[8], _T_510, UInt<1>(0h0)) node _T_520 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_521 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_522 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_523 = or(_T_511, _T_512) node _T_524 = or(_T_523, _T_513) node _T_525 = or(_T_524, _T_514) node _T_526 = or(_T_525, _T_515) node _T_527 = or(_T_526, _T_516) node _T_528 = or(_T_527, _T_517) node _T_529 = or(_T_528, _T_518) node _T_530 = or(_T_529, _T_519) node _T_531 = or(_T_530, _T_520) node _T_532 = or(_T_531, _T_521) node _T_533 = or(_T_532, _T_522) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_533 node _T_534 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_535 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_536 = and(_T_534, _T_535) node _T_537 = or(UInt<1>(0h0), _T_536) node _T_538 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_539 = cvt(_T_538) node _T_540 = and(_T_539, asSInt(UInt<14>(0h2000))) node _T_541 = asSInt(_T_540) node _T_542 = eq(_T_541, asSInt(UInt<1>(0h0))) node _T_543 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_544 = cvt(_T_543) node _T_545 = and(_T_544, asSInt(UInt<13>(0h1000))) node _T_546 = asSInt(_T_545) node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0))) node _T_548 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_549 = cvt(_T_548) node _T_550 = and(_T_549, asSInt(UInt<17>(0h10000))) node _T_551 = asSInt(_T_550) node _T_552 = eq(_T_551, asSInt(UInt<1>(0h0))) node _T_553 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_554 = cvt(_T_553) node _T_555 = and(_T_554, asSInt(UInt<18>(0h2f000))) node _T_556 = asSInt(_T_555) node _T_557 = eq(_T_556, asSInt(UInt<1>(0h0))) node _T_558 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_559 = cvt(_T_558) node _T_560 = and(_T_559, asSInt(UInt<17>(0h10000))) node _T_561 = asSInt(_T_560) node _T_562 = eq(_T_561, asSInt(UInt<1>(0h0))) node _T_563 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_564 = cvt(_T_563) node _T_565 = and(_T_564, asSInt(UInt<13>(0h1000))) node _T_566 = asSInt(_T_565) node _T_567 = eq(_T_566, asSInt(UInt<1>(0h0))) node _T_568 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_569 = cvt(_T_568) node _T_570 = and(_T_569, asSInt(UInt<27>(0h4000000))) node _T_571 = asSInt(_T_570) node _T_572 = eq(_T_571, asSInt(UInt<1>(0h0))) node _T_573 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_574 = cvt(_T_573) node _T_575 = and(_T_574, asSInt(UInt<13>(0h1000))) node _T_576 = asSInt(_T_575) node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0))) node _T_578 = or(_T_542, _T_547) node _T_579 = or(_T_578, _T_552) node _T_580 = or(_T_579, _T_557) node _T_581 = or(_T_580, _T_562) node _T_582 = or(_T_581, _T_567) node _T_583 = or(_T_582, _T_572) node _T_584 = or(_T_583, _T_577) node _T_585 = and(_T_537, _T_584) node _T_586 = or(UInt<1>(0h0), _T_585) node _T_587 = and(_WIRE_3, _T_586) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_587, UInt<1>(0h1), "") : assert_11 node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(source_ok, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_594 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_594, UInt<1>(0h1), "") : assert_13 node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(is_aligned, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_601 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_601, UInt<1>(0h1), "") : assert_15 node _T_605 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_605, UInt<1>(0h1), "") : assert_16 node _T_609 = not(io.in.a.bits.mask) node _T_610 = eq(_T_609, UInt<1>(0h0)) node _T_611 = asUInt(reset) node _T_612 = eq(_T_611, UInt<1>(0h0)) when _T_612 : node _T_613 = eq(_T_610, UInt<1>(0h0)) when _T_613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_610, UInt<1>(0h1), "") : assert_17 node _T_614 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_614, UInt<1>(0h1), "") : assert_18 node _T_618 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_618 : node _T_619 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_620 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_621 = and(_T_619, _T_620) node _T_622 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_623 = shr(io.in.a.bits.source, 2) node _T_624 = eq(_T_623, UInt<1>(0h0)) node _T_625 = leq(UInt<1>(0h0), uncommonBits_20) node _T_626 = and(_T_624, _T_625) node _T_627 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_628 = and(_T_626, _T_627) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_629 = shr(io.in.a.bits.source, 2) node _T_630 = eq(_T_629, UInt<1>(0h1)) node _T_631 = leq(UInt<1>(0h0), uncommonBits_21) node _T_632 = and(_T_630, _T_631) node _T_633 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_634 = and(_T_632, _T_633) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_635 = shr(io.in.a.bits.source, 2) node _T_636 = eq(_T_635, UInt<2>(0h2)) node _T_637 = leq(UInt<1>(0h0), uncommonBits_22) node _T_638 = and(_T_636, _T_637) node _T_639 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_640 = and(_T_638, _T_639) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_641 = shr(io.in.a.bits.source, 2) node _T_642 = eq(_T_641, UInt<2>(0h3)) node _T_643 = leq(UInt<1>(0h0), uncommonBits_23) node _T_644 = and(_T_642, _T_643) node _T_645 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_646 = and(_T_644, _T_645) node _T_647 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_648 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_649 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_650 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_651 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_652 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_653 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_654 = or(_T_622, _T_628) node _T_655 = or(_T_654, _T_634) node _T_656 = or(_T_655, _T_640) node _T_657 = or(_T_656, _T_646) node _T_658 = or(_T_657, _T_647) node _T_659 = or(_T_658, _T_648) node _T_660 = or(_T_659, _T_649) node _T_661 = or(_T_660, _T_650) node _T_662 = or(_T_661, _T_651) node _T_663 = or(_T_662, _T_652) node _T_664 = or(_T_663, _T_653) node _T_665 = and(_T_621, _T_664) node _T_666 = or(UInt<1>(0h0), _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_666, UInt<1>(0h1), "") : assert_19 node _T_670 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_671 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_672 = and(_T_670, _T_671) node _T_673 = or(UInt<1>(0h0), _T_672) node _T_674 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_675 = cvt(_T_674) node _T_676 = and(_T_675, asSInt(UInt<13>(0h1000))) node _T_677 = asSInt(_T_676) node _T_678 = eq(_T_677, asSInt(UInt<1>(0h0))) node _T_679 = and(_T_673, _T_678) node _T_680 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_681 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_682 = and(_T_680, _T_681) node _T_683 = or(UInt<1>(0h0), _T_682) node _T_684 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_685 = cvt(_T_684) node _T_686 = and(_T_685, asSInt(UInt<14>(0h2000))) node _T_687 = asSInt(_T_686) node _T_688 = eq(_T_687, asSInt(UInt<1>(0h0))) node _T_689 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_690 = cvt(_T_689) node _T_691 = and(_T_690, asSInt(UInt<17>(0h10000))) node _T_692 = asSInt(_T_691) node _T_693 = eq(_T_692, asSInt(UInt<1>(0h0))) node _T_694 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_695 = cvt(_T_694) node _T_696 = and(_T_695, asSInt(UInt<18>(0h2f000))) node _T_697 = asSInt(_T_696) node _T_698 = eq(_T_697, asSInt(UInt<1>(0h0))) node _T_699 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_700 = cvt(_T_699) node _T_701 = and(_T_700, asSInt(UInt<17>(0h10000))) node _T_702 = asSInt(_T_701) node _T_703 = eq(_T_702, asSInt(UInt<1>(0h0))) node _T_704 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_705 = cvt(_T_704) node _T_706 = and(_T_705, asSInt(UInt<13>(0h1000))) node _T_707 = asSInt(_T_706) node _T_708 = eq(_T_707, asSInt(UInt<1>(0h0))) node _T_709 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_710 = cvt(_T_709) node _T_711 = and(_T_710, asSInt(UInt<27>(0h4000000))) node _T_712 = asSInt(_T_711) node _T_713 = eq(_T_712, asSInt(UInt<1>(0h0))) node _T_714 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_715 = cvt(_T_714) node _T_716 = and(_T_715, asSInt(UInt<13>(0h1000))) node _T_717 = asSInt(_T_716) node _T_718 = eq(_T_717, asSInt(UInt<1>(0h0))) node _T_719 = or(_T_688, _T_693) node _T_720 = or(_T_719, _T_698) node _T_721 = or(_T_720, _T_703) node _T_722 = or(_T_721, _T_708) node _T_723 = or(_T_722, _T_713) node _T_724 = or(_T_723, _T_718) node _T_725 = and(_T_683, _T_724) node _T_726 = or(UInt<1>(0h0), _T_679) node _T_727 = or(_T_726, _T_725) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_727, UInt<1>(0h1), "") : assert_20 node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(source_ok, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_734 = asUInt(reset) node _T_735 = eq(_T_734, UInt<1>(0h0)) when _T_735 : node _T_736 = eq(is_aligned, UInt<1>(0h0)) when _T_736 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_737 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_737, UInt<1>(0h1), "") : assert_23 node _T_741 = eq(io.in.a.bits.mask, mask) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_741, UInt<1>(0h1), "") : assert_24 node _T_745 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_745, UInt<1>(0h1), "") : assert_25 node _T_749 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_754 = shr(io.in.a.bits.source, 2) node _T_755 = eq(_T_754, UInt<1>(0h0)) node _T_756 = leq(UInt<1>(0h0), uncommonBits_24) node _T_757 = and(_T_755, _T_756) node _T_758 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_759 = and(_T_757, _T_758) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_760 = shr(io.in.a.bits.source, 2) node _T_761 = eq(_T_760, UInt<1>(0h1)) node _T_762 = leq(UInt<1>(0h0), uncommonBits_25) node _T_763 = and(_T_761, _T_762) node _T_764 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_765 = and(_T_763, _T_764) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_766 = shr(io.in.a.bits.source, 2) node _T_767 = eq(_T_766, UInt<2>(0h2)) node _T_768 = leq(UInt<1>(0h0), uncommonBits_26) node _T_769 = and(_T_767, _T_768) node _T_770 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_771 = and(_T_769, _T_770) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<2>(0h3)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_27) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_779 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_780 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_781 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_784 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_785 = or(_T_753, _T_759) node _T_786 = or(_T_785, _T_765) node _T_787 = or(_T_786, _T_771) node _T_788 = or(_T_787, _T_777) node _T_789 = or(_T_788, _T_778) node _T_790 = or(_T_789, _T_779) node _T_791 = or(_T_790, _T_780) node _T_792 = or(_T_791, _T_781) node _T_793 = or(_T_792, _T_782) node _T_794 = or(_T_793, _T_783) node _T_795 = or(_T_794, _T_784) node _T_796 = and(_T_752, _T_795) node _T_797 = or(UInt<1>(0h0), _T_796) node _T_798 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_799 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_800 = and(_T_798, _T_799) node _T_801 = or(UInt<1>(0h0), _T_800) node _T_802 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_803 = cvt(_T_802) node _T_804 = and(_T_803, asSInt(UInt<13>(0h1000))) node _T_805 = asSInt(_T_804) node _T_806 = eq(_T_805, asSInt(UInt<1>(0h0))) node _T_807 = and(_T_801, _T_806) node _T_808 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_809 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_810 = and(_T_808, _T_809) node _T_811 = or(UInt<1>(0h0), _T_810) node _T_812 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_813 = cvt(_T_812) node _T_814 = and(_T_813, asSInt(UInt<14>(0h2000))) node _T_815 = asSInt(_T_814) node _T_816 = eq(_T_815, asSInt(UInt<1>(0h0))) node _T_817 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_818 = cvt(_T_817) node _T_819 = and(_T_818, asSInt(UInt<18>(0h2f000))) node _T_820 = asSInt(_T_819) node _T_821 = eq(_T_820, asSInt(UInt<1>(0h0))) node _T_822 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_823 = cvt(_T_822) node _T_824 = and(_T_823, asSInt(UInt<17>(0h10000))) node _T_825 = asSInt(_T_824) node _T_826 = eq(_T_825, asSInt(UInt<1>(0h0))) node _T_827 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_828 = cvt(_T_827) node _T_829 = and(_T_828, asSInt(UInt<13>(0h1000))) node _T_830 = asSInt(_T_829) node _T_831 = eq(_T_830, asSInt(UInt<1>(0h0))) node _T_832 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_833 = cvt(_T_832) node _T_834 = and(_T_833, asSInt(UInt<27>(0h4000000))) node _T_835 = asSInt(_T_834) node _T_836 = eq(_T_835, asSInt(UInt<1>(0h0))) node _T_837 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_838 = cvt(_T_837) node _T_839 = and(_T_838, asSInt(UInt<13>(0h1000))) node _T_840 = asSInt(_T_839) node _T_841 = eq(_T_840, asSInt(UInt<1>(0h0))) node _T_842 = or(_T_816, _T_821) node _T_843 = or(_T_842, _T_826) node _T_844 = or(_T_843, _T_831) node _T_845 = or(_T_844, _T_836) node _T_846 = or(_T_845, _T_841) node _T_847 = and(_T_811, _T_846) node _T_848 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_849 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<17>(0h10000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = and(_T_848, _T_853) node _T_855 = or(UInt<1>(0h0), _T_807) node _T_856 = or(_T_855, _T_847) node _T_857 = or(_T_856, _T_854) node _T_858 = and(_T_797, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_858, UInt<1>(0h1), "") : assert_26 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(source_ok, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_868 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_868, UInt<1>(0h1), "") : assert_29 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_872, UInt<1>(0h1), "") : assert_30 node _T_876 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _T_880 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_881 = shr(io.in.a.bits.source, 2) node _T_882 = eq(_T_881, UInt<1>(0h0)) node _T_883 = leq(UInt<1>(0h0), uncommonBits_28) node _T_884 = and(_T_882, _T_883) node _T_885 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_886 = and(_T_884, _T_885) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_887 = shr(io.in.a.bits.source, 2) node _T_888 = eq(_T_887, UInt<1>(0h1)) node _T_889 = leq(UInt<1>(0h0), uncommonBits_29) node _T_890 = and(_T_888, _T_889) node _T_891 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_892 = and(_T_890, _T_891) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_893 = shr(io.in.a.bits.source, 2) node _T_894 = eq(_T_893, UInt<2>(0h2)) node _T_895 = leq(UInt<1>(0h0), uncommonBits_30) node _T_896 = and(_T_894, _T_895) node _T_897 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_898 = and(_T_896, _T_897) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_899 = shr(io.in.a.bits.source, 2) node _T_900 = eq(_T_899, UInt<2>(0h3)) node _T_901 = leq(UInt<1>(0h0), uncommonBits_31) node _T_902 = and(_T_900, _T_901) node _T_903 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_904 = and(_T_902, _T_903) node _T_905 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_906 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_907 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_908 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_909 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_910 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_911 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_912 = or(_T_880, _T_886) node _T_913 = or(_T_912, _T_892) node _T_914 = or(_T_913, _T_898) node _T_915 = or(_T_914, _T_904) node _T_916 = or(_T_915, _T_905) node _T_917 = or(_T_916, _T_906) node _T_918 = or(_T_917, _T_907) node _T_919 = or(_T_918, _T_908) node _T_920 = or(_T_919, _T_909) node _T_921 = or(_T_920, _T_910) node _T_922 = or(_T_921, _T_911) node _T_923 = and(_T_879, _T_922) node _T_924 = or(UInt<1>(0h0), _T_923) node _T_925 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_926 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_927 = and(_T_925, _T_926) node _T_928 = or(UInt<1>(0h0), _T_927) node _T_929 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = and(_T_928, _T_933) node _T_935 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_936 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_937 = and(_T_935, _T_936) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_940 = cvt(_T_939) node _T_941 = and(_T_940, asSInt(UInt<14>(0h2000))) node _T_942 = asSInt(_T_941) node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0))) node _T_944 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_945 = cvt(_T_944) node _T_946 = and(_T_945, asSInt(UInt<18>(0h2f000))) node _T_947 = asSInt(_T_946) node _T_948 = eq(_T_947, asSInt(UInt<1>(0h0))) node _T_949 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_950 = cvt(_T_949) node _T_951 = and(_T_950, asSInt(UInt<17>(0h10000))) node _T_952 = asSInt(_T_951) node _T_953 = eq(_T_952, asSInt(UInt<1>(0h0))) node _T_954 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_955 = cvt(_T_954) node _T_956 = and(_T_955, asSInt(UInt<13>(0h1000))) node _T_957 = asSInt(_T_956) node _T_958 = eq(_T_957, asSInt(UInt<1>(0h0))) node _T_959 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_960 = cvt(_T_959) node _T_961 = and(_T_960, asSInt(UInt<27>(0h4000000))) node _T_962 = asSInt(_T_961) node _T_963 = eq(_T_962, asSInt(UInt<1>(0h0))) node _T_964 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_965 = cvt(_T_964) node _T_966 = and(_T_965, asSInt(UInt<13>(0h1000))) node _T_967 = asSInt(_T_966) node _T_968 = eq(_T_967, asSInt(UInt<1>(0h0))) node _T_969 = or(_T_943, _T_948) node _T_970 = or(_T_969, _T_953) node _T_971 = or(_T_970, _T_958) node _T_972 = or(_T_971, _T_963) node _T_973 = or(_T_972, _T_968) node _T_974 = and(_T_938, _T_973) node _T_975 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_976 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_977 = cvt(_T_976) node _T_978 = and(_T_977, asSInt(UInt<17>(0h10000))) node _T_979 = asSInt(_T_978) node _T_980 = eq(_T_979, asSInt(UInt<1>(0h0))) node _T_981 = and(_T_975, _T_980) node _T_982 = or(UInt<1>(0h0), _T_934) node _T_983 = or(_T_982, _T_974) node _T_984 = or(_T_983, _T_981) node _T_985 = and(_T_924, _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_985, UInt<1>(0h1), "") : assert_31 node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(source_ok, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(is_aligned, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_995 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_995, UInt<1>(0h1), "") : assert_34 node _T_999 = not(mask) node _T_1000 = and(io.in.a.bits.mask, _T_999) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_35 node _T_1005 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1005 : node _T_1006 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1007 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1008 = and(_T_1006, _T_1007) node _T_1009 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1010 = shr(io.in.a.bits.source, 2) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) node _T_1012 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1013 = and(_T_1011, _T_1012) node _T_1014 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1015 = and(_T_1013, _T_1014) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1016 = shr(io.in.a.bits.source, 2) node _T_1017 = eq(_T_1016, UInt<1>(0h1)) node _T_1018 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1019 = and(_T_1017, _T_1018) node _T_1020 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1021 = and(_T_1019, _T_1020) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1022 = shr(io.in.a.bits.source, 2) node _T_1023 = eq(_T_1022, UInt<2>(0h2)) node _T_1024 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1025 = and(_T_1023, _T_1024) node _T_1026 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1027 = and(_T_1025, _T_1026) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1028 = shr(io.in.a.bits.source, 2) node _T_1029 = eq(_T_1028, UInt<2>(0h3)) node _T_1030 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1031 = and(_T_1029, _T_1030) node _T_1032 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1033 = and(_T_1031, _T_1032) node _T_1034 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1035 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1036 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1037 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1038 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1039 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1040 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1041 = or(_T_1009, _T_1015) node _T_1042 = or(_T_1041, _T_1021) node _T_1043 = or(_T_1042, _T_1027) node _T_1044 = or(_T_1043, _T_1033) node _T_1045 = or(_T_1044, _T_1034) node _T_1046 = or(_T_1045, _T_1035) node _T_1047 = or(_T_1046, _T_1036) node _T_1048 = or(_T_1047, _T_1037) node _T_1049 = or(_T_1048, _T_1038) node _T_1050 = or(_T_1049, _T_1039) node _T_1051 = or(_T_1050, _T_1040) node _T_1052 = and(_T_1008, _T_1051) node _T_1053 = or(UInt<1>(0h0), _T_1052) node _T_1054 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1055 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1056 = and(_T_1054, _T_1055) node _T_1057 = or(UInt<1>(0h0), _T_1056) node _T_1058 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1059 = cvt(_T_1058) node _T_1060 = and(_T_1059, asSInt(UInt<14>(0h2000))) node _T_1061 = asSInt(_T_1060) node _T_1062 = eq(_T_1061, asSInt(UInt<1>(0h0))) node _T_1063 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1064 = cvt(_T_1063) node _T_1065 = and(_T_1064, asSInt(UInt<13>(0h1000))) node _T_1066 = asSInt(_T_1065) node _T_1067 = eq(_T_1066, asSInt(UInt<1>(0h0))) node _T_1068 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1069 = cvt(_T_1068) node _T_1070 = and(_T_1069, asSInt(UInt<18>(0h2f000))) node _T_1071 = asSInt(_T_1070) node _T_1072 = eq(_T_1071, asSInt(UInt<1>(0h0))) node _T_1073 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1074 = cvt(_T_1073) node _T_1075 = and(_T_1074, asSInt(UInt<17>(0h10000))) node _T_1076 = asSInt(_T_1075) node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0))) node _T_1078 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1079 = cvt(_T_1078) node _T_1080 = and(_T_1079, asSInt(UInt<13>(0h1000))) node _T_1081 = asSInt(_T_1080) node _T_1082 = eq(_T_1081, asSInt(UInt<1>(0h0))) node _T_1083 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1084 = cvt(_T_1083) node _T_1085 = and(_T_1084, asSInt(UInt<27>(0h4000000))) node _T_1086 = asSInt(_T_1085) node _T_1087 = eq(_T_1086, asSInt(UInt<1>(0h0))) node _T_1088 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1089 = cvt(_T_1088) node _T_1090 = and(_T_1089, asSInt(UInt<13>(0h1000))) node _T_1091 = asSInt(_T_1090) node _T_1092 = eq(_T_1091, asSInt(UInt<1>(0h0))) node _T_1093 = or(_T_1062, _T_1067) node _T_1094 = or(_T_1093, _T_1072) node _T_1095 = or(_T_1094, _T_1077) node _T_1096 = or(_T_1095, _T_1082) node _T_1097 = or(_T_1096, _T_1087) node _T_1098 = or(_T_1097, _T_1092) node _T_1099 = and(_T_1057, _T_1098) node _T_1100 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1101 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1102 = cvt(_T_1101) node _T_1103 = and(_T_1102, asSInt(UInt<17>(0h10000))) node _T_1104 = asSInt(_T_1103) node _T_1105 = eq(_T_1104, asSInt(UInt<1>(0h0))) node _T_1106 = and(_T_1100, _T_1105) node _T_1107 = or(UInt<1>(0h0), _T_1099) node _T_1108 = or(_T_1107, _T_1106) node _T_1109 = and(_T_1053, _T_1108) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_36 node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(source_ok, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(is_aligned, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1119 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_39 node _T_1123 = eq(io.in.a.bits.mask, mask) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_40 node _T_1127 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1127 : node _T_1128 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1129 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1130 = and(_T_1128, _T_1129) node _T_1131 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1132 = shr(io.in.a.bits.source, 2) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) node _T_1134 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1135 = and(_T_1133, _T_1134) node _T_1136 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1137 = and(_T_1135, _T_1136) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1138 = shr(io.in.a.bits.source, 2) node _T_1139 = eq(_T_1138, UInt<1>(0h1)) node _T_1140 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1141 = and(_T_1139, _T_1140) node _T_1142 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1143 = and(_T_1141, _T_1142) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1144 = shr(io.in.a.bits.source, 2) node _T_1145 = eq(_T_1144, UInt<2>(0h2)) node _T_1146 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1147 = and(_T_1145, _T_1146) node _T_1148 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1149 = and(_T_1147, _T_1148) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1150 = shr(io.in.a.bits.source, 2) node _T_1151 = eq(_T_1150, UInt<2>(0h3)) node _T_1152 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1153 = and(_T_1151, _T_1152) node _T_1154 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1155 = and(_T_1153, _T_1154) node _T_1156 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1157 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1158 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1159 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1160 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1161 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1162 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1163 = or(_T_1131, _T_1137) node _T_1164 = or(_T_1163, _T_1143) node _T_1165 = or(_T_1164, _T_1149) node _T_1166 = or(_T_1165, _T_1155) node _T_1167 = or(_T_1166, _T_1156) node _T_1168 = or(_T_1167, _T_1157) node _T_1169 = or(_T_1168, _T_1158) node _T_1170 = or(_T_1169, _T_1159) node _T_1171 = or(_T_1170, _T_1160) node _T_1172 = or(_T_1171, _T_1161) node _T_1173 = or(_T_1172, _T_1162) node _T_1174 = and(_T_1130, _T_1173) node _T_1175 = or(UInt<1>(0h0), _T_1174) node _T_1176 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1177 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1178 = and(_T_1176, _T_1177) node _T_1179 = or(UInt<1>(0h0), _T_1178) node _T_1180 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1181 = cvt(_T_1180) node _T_1182 = and(_T_1181, asSInt(UInt<14>(0h2000))) node _T_1183 = asSInt(_T_1182) node _T_1184 = eq(_T_1183, asSInt(UInt<1>(0h0))) node _T_1185 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1186 = cvt(_T_1185) node _T_1187 = and(_T_1186, asSInt(UInt<13>(0h1000))) node _T_1188 = asSInt(_T_1187) node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0))) node _T_1190 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1191 = cvt(_T_1190) node _T_1192 = and(_T_1191, asSInt(UInt<18>(0h2f000))) node _T_1193 = asSInt(_T_1192) node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1196 = cvt(_T_1195) node _T_1197 = and(_T_1196, asSInt(UInt<17>(0h10000))) node _T_1198 = asSInt(_T_1197) node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0))) node _T_1200 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1201 = cvt(_T_1200) node _T_1202 = and(_T_1201, asSInt(UInt<13>(0h1000))) node _T_1203 = asSInt(_T_1202) node _T_1204 = eq(_T_1203, asSInt(UInt<1>(0h0))) node _T_1205 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1206 = cvt(_T_1205) node _T_1207 = and(_T_1206, asSInt(UInt<27>(0h4000000))) node _T_1208 = asSInt(_T_1207) node _T_1209 = eq(_T_1208, asSInt(UInt<1>(0h0))) node _T_1210 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1211 = cvt(_T_1210) node _T_1212 = and(_T_1211, asSInt(UInt<13>(0h1000))) node _T_1213 = asSInt(_T_1212) node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = or(_T_1184, _T_1189) node _T_1216 = or(_T_1215, _T_1194) node _T_1217 = or(_T_1216, _T_1199) node _T_1218 = or(_T_1217, _T_1204) node _T_1219 = or(_T_1218, _T_1209) node _T_1220 = or(_T_1219, _T_1214) node _T_1221 = and(_T_1179, _T_1220) node _T_1222 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1223 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1224 = cvt(_T_1223) node _T_1225 = and(_T_1224, asSInt(UInt<17>(0h10000))) node _T_1226 = asSInt(_T_1225) node _T_1227 = eq(_T_1226, asSInt(UInt<1>(0h0))) node _T_1228 = and(_T_1222, _T_1227) node _T_1229 = or(UInt<1>(0h0), _T_1221) node _T_1230 = or(_T_1229, _T_1228) node _T_1231 = and(_T_1175, _T_1230) node _T_1232 = asUInt(reset) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) when _T_1233 : node _T_1234 = eq(_T_1231, UInt<1>(0h0)) when _T_1234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1231, UInt<1>(0h1), "") : assert_41 node _T_1235 = asUInt(reset) node _T_1236 = eq(_T_1235, UInt<1>(0h0)) when _T_1236 : node _T_1237 = eq(source_ok, UInt<1>(0h0)) when _T_1237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(is_aligned, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1241 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(_T_1241, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1241, UInt<1>(0h1), "") : assert_44 node _T_1245 = eq(io.in.a.bits.mask, mask) node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(_T_1245, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1245, UInt<1>(0h1), "") : assert_45 node _T_1249 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1249 : node _T_1250 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1251 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1252 = and(_T_1250, _T_1251) node _T_1253 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1254 = shr(io.in.a.bits.source, 2) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) node _T_1256 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1257 = and(_T_1255, _T_1256) node _T_1258 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1259 = and(_T_1257, _T_1258) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1260 = shr(io.in.a.bits.source, 2) node _T_1261 = eq(_T_1260, UInt<1>(0h1)) node _T_1262 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1265 = and(_T_1263, _T_1264) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1266 = shr(io.in.a.bits.source, 2) node _T_1267 = eq(_T_1266, UInt<2>(0h2)) node _T_1268 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1271 = and(_T_1269, _T_1270) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1272 = shr(io.in.a.bits.source, 2) node _T_1273 = eq(_T_1272, UInt<2>(0h3)) node _T_1274 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1275 = and(_T_1273, _T_1274) node _T_1276 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1277 = and(_T_1275, _T_1276) node _T_1278 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1279 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1280 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1281 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1282 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1283 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1284 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1285 = or(_T_1253, _T_1259) node _T_1286 = or(_T_1285, _T_1265) node _T_1287 = or(_T_1286, _T_1271) node _T_1288 = or(_T_1287, _T_1277) node _T_1289 = or(_T_1288, _T_1278) node _T_1290 = or(_T_1289, _T_1279) node _T_1291 = or(_T_1290, _T_1280) node _T_1292 = or(_T_1291, _T_1281) node _T_1293 = or(_T_1292, _T_1282) node _T_1294 = or(_T_1293, _T_1283) node _T_1295 = or(_T_1294, _T_1284) node _T_1296 = and(_T_1252, _T_1295) node _T_1297 = or(UInt<1>(0h0), _T_1296) node _T_1298 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1299 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1300 = and(_T_1298, _T_1299) node _T_1301 = or(UInt<1>(0h0), _T_1300) node _T_1302 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1303 = cvt(_T_1302) node _T_1304 = and(_T_1303, asSInt(UInt<13>(0h1000))) node _T_1305 = asSInt(_T_1304) node _T_1306 = eq(_T_1305, asSInt(UInt<1>(0h0))) node _T_1307 = and(_T_1301, _T_1306) node _T_1308 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1309 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1310 = cvt(_T_1309) node _T_1311 = and(_T_1310, asSInt(UInt<14>(0h2000))) node _T_1312 = asSInt(_T_1311) node _T_1313 = eq(_T_1312, asSInt(UInt<1>(0h0))) node _T_1314 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1315 = cvt(_T_1314) node _T_1316 = and(_T_1315, asSInt(UInt<17>(0h10000))) node _T_1317 = asSInt(_T_1316) node _T_1318 = eq(_T_1317, asSInt(UInt<1>(0h0))) node _T_1319 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1320 = cvt(_T_1319) node _T_1321 = and(_T_1320, asSInt(UInt<18>(0h2f000))) node _T_1322 = asSInt(_T_1321) node _T_1323 = eq(_T_1322, asSInt(UInt<1>(0h0))) node _T_1324 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1325 = cvt(_T_1324) node _T_1326 = and(_T_1325, asSInt(UInt<17>(0h10000))) node _T_1327 = asSInt(_T_1326) node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0))) node _T_1329 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1330 = cvt(_T_1329) node _T_1331 = and(_T_1330, asSInt(UInt<13>(0h1000))) node _T_1332 = asSInt(_T_1331) node _T_1333 = eq(_T_1332, asSInt(UInt<1>(0h0))) node _T_1334 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1335 = cvt(_T_1334) node _T_1336 = and(_T_1335, asSInt(UInt<27>(0h4000000))) node _T_1337 = asSInt(_T_1336) node _T_1338 = eq(_T_1337, asSInt(UInt<1>(0h0))) node _T_1339 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1340 = cvt(_T_1339) node _T_1341 = and(_T_1340, asSInt(UInt<13>(0h1000))) node _T_1342 = asSInt(_T_1341) node _T_1343 = eq(_T_1342, asSInt(UInt<1>(0h0))) node _T_1344 = or(_T_1313, _T_1318) node _T_1345 = or(_T_1344, _T_1323) node _T_1346 = or(_T_1345, _T_1328) node _T_1347 = or(_T_1346, _T_1333) node _T_1348 = or(_T_1347, _T_1338) node _T_1349 = or(_T_1348, _T_1343) node _T_1350 = and(_T_1308, _T_1349) node _T_1351 = or(UInt<1>(0h0), _T_1307) node _T_1352 = or(_T_1351, _T_1350) node _T_1353 = and(_T_1297, _T_1352) node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(_T_1353, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1353, UInt<1>(0h1), "") : assert_46 node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(source_ok, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(is_aligned, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1363 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1364 = asUInt(reset) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) when _T_1365 : node _T_1366 = eq(_T_1363, UInt<1>(0h0)) when _T_1366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1363, UInt<1>(0h1), "") : assert_49 node _T_1367 = eq(io.in.a.bits.mask, mask) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_50 node _T_1371 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1375 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_52 node _source_ok_T_42 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h0)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<1>(0h1)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h2)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_61 = shr(io.in.d.bits.source, 2) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<2>(0h3)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_68 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_69 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[12] connect _source_ok_WIRE_1[0], _source_ok_T_42 connect _source_ok_WIRE_1[1], _source_ok_T_48 connect _source_ok_WIRE_1[2], _source_ok_T_54 connect _source_ok_WIRE_1[3], _source_ok_T_60 connect _source_ok_WIRE_1[4], _source_ok_T_66 connect _source_ok_WIRE_1[5], _source_ok_T_67 connect _source_ok_WIRE_1[6], _source_ok_T_68 connect _source_ok_WIRE_1[7], _source_ok_T_69 connect _source_ok_WIRE_1[8], _source_ok_T_70 connect _source_ok_WIRE_1[9], _source_ok_T_71 connect _source_ok_WIRE_1[10], _source_ok_T_72 connect _source_ok_WIRE_1[11], _source_ok_T_73 node _source_ok_T_74 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[2]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[3]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[4]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[5]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[6]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[7]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[8]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[9]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[10]) node source_ok_1 = or(_source_ok_T_83, _source_ok_WIRE_1[11]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1379 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1379 : node _T_1380 = asUInt(reset) node _T_1381 = eq(_T_1380, UInt<1>(0h0)) when _T_1381 : node _T_1382 = eq(source_ok_1, UInt<1>(0h0)) when _T_1382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1383 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(_T_1383, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1383, UInt<1>(0h1), "") : assert_54 node _T_1387 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1388 = asUInt(reset) node _T_1389 = eq(_T_1388, UInt<1>(0h0)) when _T_1389 : node _T_1390 = eq(_T_1387, UInt<1>(0h0)) when _T_1390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1387, UInt<1>(0h1), "") : assert_55 node _T_1391 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1392 = asUInt(reset) node _T_1393 = eq(_T_1392, UInt<1>(0h0)) when _T_1393 : node _T_1394 = eq(_T_1391, UInt<1>(0h0)) when _T_1394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1391, UInt<1>(0h1), "") : assert_56 node _T_1395 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1396 = asUInt(reset) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(_T_1395, UInt<1>(0h0)) when _T_1398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1395, UInt<1>(0h1), "") : assert_57 node _T_1399 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1399 : node _T_1400 = asUInt(reset) node _T_1401 = eq(_T_1400, UInt<1>(0h0)) when _T_1401 : node _T_1402 = eq(source_ok_1, UInt<1>(0h0)) when _T_1402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(sink_ok, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1406 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_60 node _T_1410 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_61 node _T_1414 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1415 = asUInt(reset) node _T_1416 = eq(_T_1415, UInt<1>(0h0)) when _T_1416 : node _T_1417 = eq(_T_1414, UInt<1>(0h0)) when _T_1417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1414, UInt<1>(0h1), "") : assert_62 node _T_1418 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(_T_1418, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1418, UInt<1>(0h1), "") : assert_63 node _T_1422 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1423 = or(UInt<1>(0h1), _T_1422) node _T_1424 = asUInt(reset) node _T_1425 = eq(_T_1424, UInt<1>(0h0)) when _T_1425 : node _T_1426 = eq(_T_1423, UInt<1>(0h0)) when _T_1426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1423, UInt<1>(0h1), "") : assert_64 node _T_1427 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1427 : node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(source_ok_1, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1431 = asUInt(reset) node _T_1432 = eq(_T_1431, UInt<1>(0h0)) when _T_1432 : node _T_1433 = eq(sink_ok, UInt<1>(0h0)) when _T_1433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1434 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1435 = asUInt(reset) node _T_1436 = eq(_T_1435, UInt<1>(0h0)) when _T_1436 : node _T_1437 = eq(_T_1434, UInt<1>(0h0)) when _T_1437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1434, UInt<1>(0h1), "") : assert_67 node _T_1438 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1439 = asUInt(reset) node _T_1440 = eq(_T_1439, UInt<1>(0h0)) when _T_1440 : node _T_1441 = eq(_T_1438, UInt<1>(0h0)) when _T_1441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1438, UInt<1>(0h1), "") : assert_68 node _T_1442 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_69 node _T_1446 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1447 = or(_T_1446, io.in.d.bits.corrupt) node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(_T_1447, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1447, UInt<1>(0h1), "") : assert_70 node _T_1451 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1452 = or(UInt<1>(0h1), _T_1451) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_71 node _T_1456 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1456 : node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(source_ok_1, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1460 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1461 = asUInt(reset) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) when _T_1462 : node _T_1463 = eq(_T_1460, UInt<1>(0h0)) when _T_1463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1460, UInt<1>(0h1), "") : assert_73 node _T_1464 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1465 = asUInt(reset) node _T_1466 = eq(_T_1465, UInt<1>(0h0)) when _T_1466 : node _T_1467 = eq(_T_1464, UInt<1>(0h0)) when _T_1467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1464, UInt<1>(0h1), "") : assert_74 node _T_1468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1469 = or(UInt<1>(0h1), _T_1468) node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(_T_1469, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1469, UInt<1>(0h1), "") : assert_75 node _T_1473 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1473 : node _T_1474 = asUInt(reset) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) when _T_1475 : node _T_1476 = eq(source_ok_1, UInt<1>(0h0)) when _T_1476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1477 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1478 = asUInt(reset) node _T_1479 = eq(_T_1478, UInt<1>(0h0)) when _T_1479 : node _T_1480 = eq(_T_1477, UInt<1>(0h0)) when _T_1480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1477, UInt<1>(0h1), "") : assert_77 node _T_1481 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1482 = or(_T_1481, io.in.d.bits.corrupt) node _T_1483 = asUInt(reset) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) when _T_1484 : node _T_1485 = eq(_T_1482, UInt<1>(0h0)) when _T_1485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1482, UInt<1>(0h1), "") : assert_78 node _T_1486 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1487 = or(UInt<1>(0h1), _T_1486) node _T_1488 = asUInt(reset) node _T_1489 = eq(_T_1488, UInt<1>(0h0)) when _T_1489 : node _T_1490 = eq(_T_1487, UInt<1>(0h0)) when _T_1490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1487, UInt<1>(0h1), "") : assert_79 node _T_1491 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1491 : node _T_1492 = asUInt(reset) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(source_ok_1, UInt<1>(0h0)) when _T_1494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1495 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1496 = asUInt(reset) node _T_1497 = eq(_T_1496, UInt<1>(0h0)) when _T_1497 : node _T_1498 = eq(_T_1495, UInt<1>(0h0)) when _T_1498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1495, UInt<1>(0h1), "") : assert_81 node _T_1499 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1500 = asUInt(reset) node _T_1501 = eq(_T_1500, UInt<1>(0h0)) when _T_1501 : node _T_1502 = eq(_T_1499, UInt<1>(0h0)) when _T_1502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1499, UInt<1>(0h1), "") : assert_82 node _T_1503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1504 = or(UInt<1>(0h1), _T_1503) node _T_1505 = asUInt(reset) node _T_1506 = eq(_T_1505, UInt<1>(0h0)) when _T_1506 : node _T_1507 = eq(_T_1504, UInt<1>(0h0)) when _T_1507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1504, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1508 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(_T_1508, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1508, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1512 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(_T_1512, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1512, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1516 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(_T_1516, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1516, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1520 = eq(a_first, UInt<1>(0h0)) node _T_1521 = and(io.in.a.valid, _T_1520) when _T_1521 : node _T_1522 = eq(io.in.a.bits.opcode, opcode) node _T_1523 = asUInt(reset) node _T_1524 = eq(_T_1523, UInt<1>(0h0)) when _T_1524 : node _T_1525 = eq(_T_1522, UInt<1>(0h0)) when _T_1525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1522, UInt<1>(0h1), "") : assert_87 node _T_1526 = eq(io.in.a.bits.param, param) node _T_1527 = asUInt(reset) node _T_1528 = eq(_T_1527, UInt<1>(0h0)) when _T_1528 : node _T_1529 = eq(_T_1526, UInt<1>(0h0)) when _T_1529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1526, UInt<1>(0h1), "") : assert_88 node _T_1530 = eq(io.in.a.bits.size, size) node _T_1531 = asUInt(reset) node _T_1532 = eq(_T_1531, UInt<1>(0h0)) when _T_1532 : node _T_1533 = eq(_T_1530, UInt<1>(0h0)) when _T_1533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1530, UInt<1>(0h1), "") : assert_89 node _T_1534 = eq(io.in.a.bits.source, source) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_90 node _T_1538 = eq(io.in.a.bits.address, address) node _T_1539 = asUInt(reset) node _T_1540 = eq(_T_1539, UInt<1>(0h0)) when _T_1540 : node _T_1541 = eq(_T_1538, UInt<1>(0h0)) when _T_1541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1538, UInt<1>(0h1), "") : assert_91 node _T_1542 = and(io.in.a.ready, io.in.a.valid) node _T_1543 = and(_T_1542, a_first) when _T_1543 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1544 = eq(d_first, UInt<1>(0h0)) node _T_1545 = and(io.in.d.valid, _T_1544) when _T_1545 : node _T_1546 = eq(io.in.d.bits.opcode, opcode_1) node _T_1547 = asUInt(reset) node _T_1548 = eq(_T_1547, UInt<1>(0h0)) when _T_1548 : node _T_1549 = eq(_T_1546, UInt<1>(0h0)) when _T_1549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1546, UInt<1>(0h1), "") : assert_92 node _T_1550 = eq(io.in.d.bits.param, param_1) node _T_1551 = asUInt(reset) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : node _T_1553 = eq(_T_1550, UInt<1>(0h0)) when _T_1553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1550, UInt<1>(0h1), "") : assert_93 node _T_1554 = eq(io.in.d.bits.size, size_1) node _T_1555 = asUInt(reset) node _T_1556 = eq(_T_1555, UInt<1>(0h0)) when _T_1556 : node _T_1557 = eq(_T_1554, UInt<1>(0h0)) when _T_1557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1554, UInt<1>(0h1), "") : assert_94 node _T_1558 = eq(io.in.d.bits.source, source_1) node _T_1559 = asUInt(reset) node _T_1560 = eq(_T_1559, UInt<1>(0h0)) when _T_1560 : node _T_1561 = eq(_T_1558, UInt<1>(0h0)) when _T_1561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1558, UInt<1>(0h1), "") : assert_95 node _T_1562 = eq(io.in.d.bits.sink, sink) node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(_T_1562, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1562, UInt<1>(0h1), "") : assert_96 node _T_1566 = eq(io.in.d.bits.denied, denied) node _T_1567 = asUInt(reset) node _T_1568 = eq(_T_1567, UInt<1>(0h0)) when _T_1568 : node _T_1569 = eq(_T_1566, UInt<1>(0h0)) when _T_1569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1566, UInt<1>(0h1), "") : assert_97 node _T_1570 = and(io.in.d.ready, io.in.d.valid) node _T_1571 = and(_T_1570, d_first) when _T_1571 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1572 = and(io.in.a.valid, a_first_1) node _T_1573 = and(_T_1572, UInt<1>(0h1)) when _T_1573 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1574 = and(io.in.a.ready, io.in.a.valid) node _T_1575 = and(_T_1574, a_first_1) node _T_1576 = and(_T_1575, UInt<1>(0h1)) when _T_1576 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1577 = dshr(inflight, io.in.a.bits.source) node _T_1578 = bits(_T_1577, 0, 0) node _T_1579 = eq(_T_1578, UInt<1>(0h0)) node _T_1580 = asUInt(reset) node _T_1581 = eq(_T_1580, UInt<1>(0h0)) when _T_1581 : node _T_1582 = eq(_T_1579, UInt<1>(0h0)) when _T_1582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1579, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1583 = and(io.in.d.valid, d_first_1) node _T_1584 = and(_T_1583, UInt<1>(0h1)) node _T_1585 = eq(d_release_ack, UInt<1>(0h0)) node _T_1586 = and(_T_1584, _T_1585) when _T_1586 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1587 = and(io.in.d.ready, io.in.d.valid) node _T_1588 = and(_T_1587, d_first_1) node _T_1589 = and(_T_1588, UInt<1>(0h1)) node _T_1590 = eq(d_release_ack, UInt<1>(0h0)) node _T_1591 = and(_T_1589, _T_1590) when _T_1591 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1592 = and(io.in.d.valid, d_first_1) node _T_1593 = and(_T_1592, UInt<1>(0h1)) node _T_1594 = eq(d_release_ack, UInt<1>(0h0)) node _T_1595 = and(_T_1593, _T_1594) when _T_1595 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1596 = dshr(inflight, io.in.d.bits.source) node _T_1597 = bits(_T_1596, 0, 0) node _T_1598 = or(_T_1597, same_cycle_resp) node _T_1599 = asUInt(reset) node _T_1600 = eq(_T_1599, UInt<1>(0h0)) when _T_1600 : node _T_1601 = eq(_T_1598, UInt<1>(0h0)) when _T_1601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1598, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1602 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1603 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1604 = or(_T_1602, _T_1603) node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(_T_1604, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1604, UInt<1>(0h1), "") : assert_100 node _T_1608 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1609 = asUInt(reset) node _T_1610 = eq(_T_1609, UInt<1>(0h0)) when _T_1610 : node _T_1611 = eq(_T_1608, UInt<1>(0h0)) when _T_1611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1608, UInt<1>(0h1), "") : assert_101 else : node _T_1612 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1613 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1614 = or(_T_1612, _T_1613) node _T_1615 = asUInt(reset) node _T_1616 = eq(_T_1615, UInt<1>(0h0)) when _T_1616 : node _T_1617 = eq(_T_1614, UInt<1>(0h0)) when _T_1617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1614, UInt<1>(0h1), "") : assert_102 node _T_1618 = eq(io.in.d.bits.size, a_size_lookup) node _T_1619 = asUInt(reset) node _T_1620 = eq(_T_1619, UInt<1>(0h0)) when _T_1620 : node _T_1621 = eq(_T_1618, UInt<1>(0h0)) when _T_1621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1618, UInt<1>(0h1), "") : assert_103 node _T_1622 = and(io.in.d.valid, d_first_1) node _T_1623 = and(_T_1622, a_first_1) node _T_1624 = and(_T_1623, io.in.a.valid) node _T_1625 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1626 = and(_T_1624, _T_1625) node _T_1627 = eq(d_release_ack, UInt<1>(0h0)) node _T_1628 = and(_T_1626, _T_1627) when _T_1628 : node _T_1629 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1630 = or(_T_1629, io.in.a.ready) node _T_1631 = asUInt(reset) node _T_1632 = eq(_T_1631, UInt<1>(0h0)) when _T_1632 : node _T_1633 = eq(_T_1630, UInt<1>(0h0)) when _T_1633 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1630, UInt<1>(0h1), "") : assert_104 node _T_1634 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1635 = orr(a_set_wo_ready) node _T_1636 = eq(_T_1635, UInt<1>(0h0)) node _T_1637 = or(_T_1634, _T_1636) node _T_1638 = asUInt(reset) node _T_1639 = eq(_T_1638, UInt<1>(0h0)) when _T_1639 : node _T_1640 = eq(_T_1637, UInt<1>(0h0)) when _T_1640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1637, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_38 node _T_1641 = orr(inflight) node _T_1642 = eq(_T_1641, UInt<1>(0h0)) node _T_1643 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1644 = or(_T_1642, _T_1643) node _T_1645 = lt(watchdog, plusarg_reader.out) node _T_1646 = or(_T_1644, _T_1645) node _T_1647 = asUInt(reset) node _T_1648 = eq(_T_1647, UInt<1>(0h0)) when _T_1648 : node _T_1649 = eq(_T_1646, UInt<1>(0h0)) when _T_1649 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1646, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1650 = and(io.in.a.ready, io.in.a.valid) node _T_1651 = and(io.in.d.ready, io.in.d.valid) node _T_1652 = or(_T_1650, _T_1651) when _T_1652 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1653 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1654 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1655 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1656 = and(_T_1654, _T_1655) node _T_1657 = and(_T_1653, _T_1656) when _T_1657 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1658 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1659 = and(_T_1658, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1660 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1661 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1662 = and(_T_1660, _T_1661) node _T_1663 = and(_T_1659, _T_1662) when _T_1663 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1664 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1665 = bits(_T_1664, 0, 0) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) node _T_1667 = asUInt(reset) node _T_1668 = eq(_T_1667, UInt<1>(0h0)) when _T_1668 : node _T_1669 = eq(_T_1666, UInt<1>(0h0)) when _T_1669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1666, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1670 = and(io.in.d.valid, d_first_2) node _T_1671 = and(_T_1670, UInt<1>(0h1)) node _T_1672 = and(_T_1671, d_release_ack_1) when _T_1672 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1673 = and(io.in.d.ready, io.in.d.valid) node _T_1674 = and(_T_1673, d_first_2) node _T_1675 = and(_T_1674, UInt<1>(0h1)) node _T_1676 = and(_T_1675, d_release_ack_1) when _T_1676 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1677 = and(io.in.d.valid, d_first_2) node _T_1678 = and(_T_1677, UInt<1>(0h1)) node _T_1679 = and(_T_1678, d_release_ack_1) when _T_1679 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1680 = dshr(inflight_1, io.in.d.bits.source) node _T_1681 = bits(_T_1680, 0, 0) node _T_1682 = or(_T_1681, same_cycle_resp_1) node _T_1683 = asUInt(reset) node _T_1684 = eq(_T_1683, UInt<1>(0h0)) when _T_1684 : node _T_1685 = eq(_T_1682, UInt<1>(0h0)) when _T_1685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1682, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1686 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1687 = asUInt(reset) node _T_1688 = eq(_T_1687, UInt<1>(0h0)) when _T_1688 : node _T_1689 = eq(_T_1686, UInt<1>(0h0)) when _T_1689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1686, UInt<1>(0h1), "") : assert_109 else : node _T_1690 = eq(io.in.d.bits.size, c_size_lookup) node _T_1691 = asUInt(reset) node _T_1692 = eq(_T_1691, UInt<1>(0h0)) when _T_1692 : node _T_1693 = eq(_T_1690, UInt<1>(0h0)) when _T_1693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1690, UInt<1>(0h1), "") : assert_110 node _T_1694 = and(io.in.d.valid, d_first_2) node _T_1695 = and(_T_1694, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1696 = and(_T_1695, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1697 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1698 = and(_T_1696, _T_1697) node _T_1699 = and(_T_1698, d_release_ack_1) node _T_1700 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1701 = and(_T_1699, _T_1700) when _T_1701 : node _T_1702 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1703 = or(_T_1702, _WIRE_27.ready) node _T_1704 = asUInt(reset) node _T_1705 = eq(_T_1704, UInt<1>(0h0)) when _T_1705 : node _T_1706 = eq(_T_1703, UInt<1>(0h0)) when _T_1706 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1703, UInt<1>(0h1), "") : assert_111 node _T_1707 = orr(c_set_wo_ready) when _T_1707 : node _T_1708 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1709 = asUInt(reset) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) when _T_1710 : node _T_1711 = eq(_T_1708, UInt<1>(0h0)) when _T_1711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1708, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_39 node _T_1712 = orr(inflight_1) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) node _T_1714 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1715 = or(_T_1713, _T_1714) node _T_1716 = lt(watchdog_1, plusarg_reader_1.out) node _T_1717 = or(_T_1715, _T_1716) node _T_1718 = asUInt(reset) node _T_1719 = eq(_T_1718, UInt<1>(0h0)) when _T_1719 : node _T_1720 = eq(_T_1717, UInt<1>(0h0)) when _T_1720 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1717, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1721 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1722 = and(io.in.d.ready, io.in.d.valid) node _T_1723 = or(_T_1721, _T_1722) when _T_1723 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_19( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_41 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_61 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_44 = _source_ok_T_43 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_62 = _source_ok_T_61 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire _source_ok_T_67 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire _source_ok_T_68 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire _source_ok_T_69 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_82 = _source_ok_T_81 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_83 = _source_ok_T_82 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_83 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _T_1650 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1650; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1650; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1723 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1723; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1723; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1723; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1576 = _T_1650 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1576 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1576 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1576 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1576 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1576 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1622 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1622 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1591 = _T_1723 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1591 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1591 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1591 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1694 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1694 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1676 = _T_1723 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1676 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1676 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1676 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_172 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_304 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_172( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_304 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntSyncAsyncCrossingSink_n1x1 : input clock : Clock input reset : Reset output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} wire nodeIn : { sync : UInt<1>[1]} invalidate nodeIn.sync[0] wire nodeOut : UInt<1>[1] invalidate nodeOut[0] connect auto.out, nodeOut connect nodeIn, auto.in inst chain of SynchronizerShiftReg_w1_d3 connect chain.clock, clock connect chain.reset, reset connect chain.io.d, nodeIn.sync[0] wire _WIRE : UInt<1>[1] wire _WIRE_1 : UInt<1> connect _WIRE_1, chain.io.q node _T = bits(_WIRE_1, 0, 0) connect _WIRE[0], _T connect nodeOut, _WIRE
module IntSyncAsyncCrossingSink_n1x1( // @[Crossing.scala:74:9] input clock, // @[Crossing.scala:74:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0 // @[LazyModuleImp.scala:107:25] ); SynchronizerShiftReg_w1_d3 chain ( // @[ShiftReg.scala:45:23] .clock (clock), .io_d (auto_in_sync_0), .io_q (auto_out_0) ); // @[ShiftReg.scala:45:23] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_TileResetSetter : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_66 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) reg dOrig : UInt, clock regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) node dFragnum = bits(anonOut.d.bits.source, 2, 0) node dFirst = eq(acknum, UInt<1>(0h0)) node dLast = eq(dFragnum, UInt<1>(0h0)) node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) node dsizeOH = bits(_dsizeOH_T, 3, 0) node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) node dsizeOH1 = not(_dsizeOH1_T_1) node dHasData = bits(anonOut.d.bits.opcode, 0, 0) node acknum_fragment = shl(dFragnum, 0) node acknum_size = shr(dsizeOH1, 3) node _T = eq(anonOut.d.valid, UInt<1>(0h0)) node _T_1 = and(acknum_fragment, acknum_size) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = or(_T, _T_2) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) node _ack_decrement_T = shr(dsizeOH, 3) node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) node _dFirst_size_T = shl(dFragnum, 3) node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) node _dFirst_size_T_5 = not(_dFirst_size_T_4) node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) node _dFirst_size_T_7 = orr(dFirst_size_hi) node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) node _dFirst_size_T_9 = orr(dFirst_size_hi_1) node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) node _T_7 = and(anonOut.d.ready, anonOut.d.valid) when _T_7 : node _acknum_T = sub(acknum, ack_decrement) node _acknum_T_1 = tail(_acknum_T, 1) node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) connect acknum, _acknum_T_2 when dFirst : connect dOrig, dFirst_size node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) connect dToggle, _dToggle_T node _drop_T = eq(dHasData, UInt<1>(0h0)) node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) node drop = and(_drop_T, _drop_T_2) node _anonOut_d_ready_T = or(anonIn.d.ready, drop) connect anonOut.d.ready, _anonOut_d_ready_T node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) connect anonIn.d.valid, _anonIn_d_valid_T_1 connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) connect anonIn.d.bits.source, _anonIn_d_bits_source_T node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) connect anonIn.d.bits.size, _anonIn_d_bits_size_T inst repeater of Repeater_TLBundleA_a21d64s8k1z3u_1 connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) node _find_T_1 = cvt(_find_T) node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) node _find_T_3 = asSInt(_find_T_2) node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) wire find : UInt<1>[1] connect find[0], _find_T_4 node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) node _aFrag_T = gt(repeater.io.deq.bits.size, limit) node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) node aOrigOH1 = not(_aOrigOH1_T_1) node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) node aFragOH1 = not(_aFragOH1_T_1) node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) node aFirst = eq(gennum, UInt<1>(0h0)) node _old_gennum1_T = shr(aOrigOH1, 3) node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) node _new_gennum_T = not(old_gennum1) node _new_gennum_T_1 = shr(aMask, 3) node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) node new_gennum = not(_new_gennum_T_2) node _aFragnum_T = shr(old_gennum1, 0) node _aFragnum_T_1 = not(_aFragnum_T) node _aFragnum_T_2 = shr(aFragOH1, 3) node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) node aFragnum = not(_aFragnum_T_3) node aLast = eq(aFragnum, UInt<1>(0h0)) reg aToggle_r : UInt<1>, clock when aFirst : connect aToggle_r, dToggle node _aToggle_T = mux(aFirst, dToggle, aToggle_r) node aToggle = eq(_aToggle_T, UInt<1>(0h0)) node _T_8 = and(anonOut.a.ready, anonOut.a.valid) when _T_8 : connect gennum, new_gennum node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) connect repeater.io.repeat, _repeater_io_repeat_T_2 connect anonOut.a.bits, repeater.io.deq.bits connect anonOut.a.valid, repeater.io.deq.valid connect repeater.io.deq.ready, anonOut.a.ready node _anonOut_a_bits_address_T = shl(old_gennum1, 3) node _anonOut_a_bits_address_T_1 = not(aOrigOH1) node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) connect anonOut.a.bits.source, _anonOut_a_bits_source_T connect anonOut.a.bits.size, aFrag node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) node _T_10 = eq(aHasData, UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 connect anonOut.a.bits.data, anonIn.a.bits.data node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) node _T_17 = or(_T_15, _T_16) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T wire anonOut_a_bits_user_out : { } wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)
module TLFragmenter_TileResetSetter( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_anon_out_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [20:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9] wire [20:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_d_bits_data = 64'h0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_d_bits_data = 64'h0; // @[Fragmenter.scala:92:9] wire [63:0] anonIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] anonOut_d_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36] wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50] wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50] wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84] wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49] wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59] wire find_0 = 1'h1; // @[Parameters.scala:616:12] wire [21:0] _find_T_2 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _find_T_3 = 22'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [20:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [11:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [11:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [20:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9] assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9] wire [7:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9] wire [11:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9] wire [20:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire [2:0] dFragnum = anonOut_d_bits_source[2:0]; // @[Fragmenter.scala:204:41] wire [2:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala:204:41, :206:30] wire _drop_T_1 = dLast; // @[Fragmenter.scala:206:30, :234:37] wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] dsizeOH = _dsizeOH_T; // @[OneHot.scala:65:{12,27}] wire [5:0] _dsizeOH1_T = 6'h7 << anonOut_d_bits_size; // @[package.scala:243:71] wire [2:0] _dsizeOH1_T_1 = _dsizeOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}] wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45] wire _ack_decrement_T = dsizeOH[3]; // @[OneHot.scala:65:27] wire ack_decrement = dHasData | _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}] wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala:204:41, :218:47] wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:3], _dFirst_size_T[2:0] | dsizeOH1}; // @[package.scala:243:46] wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35] wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}] wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53] wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}] wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}] wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18] wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18] wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} | dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28] wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28] wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}] wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}] wire [3:0] _acknum_T = {1'h0, acknum} - {3'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55] wire [2:0] _acknum_T_1 = _acknum_T[2:0]; // @[Fragmenter.scala:221:55] wire [2:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}] wire _dToggle_T = anonOut_d_bits_source[3]; // @[Fragmenter.scala:224:41] wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20] wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}] wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}] assign _anonOut_d_ready_T = anonIn_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35] assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39] assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}] assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign _anonIn_d_bits_source_T = anonOut_d_bits_source[11:4]; // @[Fragmenter.scala:238:47] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] wire [20:0] _find_T; // @[Parameters.scala:137:31] wire [21:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}] wire _limit_T = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49] wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31] wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}] wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71] wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}] wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30] wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46] wire [3:0] _old_gennum1_T_1 = {1'h0, gennum} - 4'h1; // @[Fragmenter.scala:303:29, :305:79] wire [2:0] _old_gennum1_T_2 = _old_gennum1_T_1[2:0]; // @[Fragmenter.scala:305:79] wire [2:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}] wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40] wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28] wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}] wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}] wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}] wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}] wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}] wire aLast = ~(|aFragnum); // @[Fragmenter.scala:307:24, :308:30] reg aToggle_r; // @[Fragmenter.scala:309:54] wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}] wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}] wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31] wire _repeater_io_repeat_T_1 = |aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53] wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}] wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65] wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T | _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}] wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] | aFragOH1}; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}] wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}] assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[20:6], _repeater_io_deq_bits_address[5:0] | _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}] assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] wire [8:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aToggle}; // @[Fragmenter.scala:274:30, :309:23, :317:33] assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, aFragnum}; // @[Fragmenter.scala:307:24, :317:33] assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25]
Generate the Verilog code corresponding to this FIRRTL code module IngressWidthWidget : input clock : Clock input reset : Reset output auto : { flip in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, egress_id : UInt}}}, out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}}} wire nodeIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, egress_id : UInt}}} invalidate nodeIn.flit.bits.egress_id invalidate nodeIn.flit.bits.payload invalidate nodeIn.flit.bits.tail invalidate nodeIn.flit.bits.head invalidate nodeIn.flit.valid invalidate nodeIn.flit.ready wire nodeOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} invalidate nodeOut.flit.bits.egress_id invalidate nodeOut.flit.bits.payload invalidate nodeOut.flit.bits.tail invalidate nodeOut.flit.bits.head invalidate nodeOut.flit.valid invalidate nodeOut.flit.ready connect auto.out, nodeOut connect nodeIn, auto.in regreset count : UInt<2>, clock, reset, UInt<2>(0h0) node first = eq(count, UInt<1>(0h0)) node last = eq(count, UInt<2>(0h3)) reg stored : UInt<111>, clock connect nodeOut.flit.valid, nodeIn.flit.valid connect nodeOut.flit.bits, nodeIn.flit.bits node _nodeOut_flit_bits_head_T = and(nodeIn.flit.bits.head, first) connect nodeOut.flit.bits.head, _nodeOut_flit_bits_head_T node _nodeOut_flit_bits_tail_T = and(nodeIn.flit.bits.tail, last) connect nodeOut.flit.bits.tail, _nodeOut_flit_bits_tail_T node _nodeOut_flit_bits_payload_T = mux(first, nodeIn.flit.bits.payload, stored) connect nodeOut.flit.bits.payload, _nodeOut_flit_bits_payload_T node _nodeIn_flit_ready_T = and(last, nodeOut.flit.ready) connect nodeIn.flit.ready, _nodeIn_flit_ready_T node _T = and(nodeOut.flit.ready, nodeOut.flit.valid) when _T : node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) node _count_T_2 = mux(last, UInt<1>(0h0), _count_T_1) connect count, _count_T_2 node _stored_T = mux(first, nodeIn.flit.bits.payload, stored) node _stored_T_1 = shr(_stored_T, 37) connect stored, _stored_T_1
module IngressWidthWidget( // @[WidthWidget.scala:75:25] input clock, // @[WidthWidget.scala:75:25] input reset, // @[WidthWidget.scala:75:25] output auto_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [147:0] auto_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] input auto_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_flit_bits_egress_id // @[LazyModuleImp.scala:107:25] ); reg [1:0] count; // @[WidthWidget.scala:15:24] wire first = count == 2'h0; // @[WidthWidget.scala:15:24, :16:23, :75:25] reg [110:0] stored; // @[WidthWidget.scala:18:21] wire [147:0] _stored_T = first ? auto_in_flit_bits_payload : {37'h0, stored}; // @[WidthWidget.scala:16:23, :18:21, :24:28] wire _GEN = auto_out_flit_ready & auto_in_flit_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[WidthWidget.scala:75:25] if (reset) // @[WidthWidget.scala:75:25] count <= 2'h0; // @[WidthWidget.scala:15:24, :75:25] else if (_GEN) // @[Decoupled.scala:51:35] count <= (&count) ? 2'h0 : count + 2'h1; // @[WidthWidget.scala:15:24, :17:22, :27:{19,37}, :75:25] if (_GEN) // @[Decoupled.scala:51:35] stored <= _stored_T[147:37]; // @[WidthWidget.scala:18:21, :24:28, :28:53] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module MSHR_6 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h20)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h20)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h20)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)
module MSHR_6( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire excluded_client = 1'h0; // @[MSHR.scala:279:28] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire allocate_as_full_prio_1 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire new_request_prio_1 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _io_schedule_bits_b_bits_clients_T = 1'h1; // @[MSHR.scala:289:53] wire _last_probe_T_1 = 1'h1; // @[MSHR.scala:459:66] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h20; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h20; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module Router_3 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[4], sa_stall : UInt[4]}, egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_8 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate destNodesIn_1.vc_free invalidate destNodesIn_1.credit_return invalidate destNodesIn_1.flit[0].bits.virt_channel_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_1.flit[0].bits.flow.ingress_node invalidate destNodesIn_1.flit[0].bits.flow.vnet_id invalidate destNodesIn_1.flit[0].bits.payload invalidate destNodesIn_1.flit[0].bits.tail invalidate destNodesIn_1.flit[0].bits.head invalidate destNodesIn_1.flit[0].valid inst monitor_1 of NoCMonitor_9 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>} invalidate sourceNodesOut_1.vc_free invalidate sourceNodesOut_1.credit_return invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_1.flit[0].bits.payload invalidate sourceNodesOut_1.flit[0].bits.tail invalidate sourceNodesOut_1.flit[0].bits.head invalidate sourceNodesOut_1.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}} invalidate ingressNodesIn_1.flit.bits.egress_id invalidate ingressNodesIn_1.flit.bits.payload invalidate ingressNodesIn_1.flit.bits.tail invalidate ingressNodesIn_1.flit.bits.head invalidate ingressNodesIn_1.flit.valid invalidate ingressNodesIn_1.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire debugNodeOut : { va_stall : UInt[4], sa_stall : UInt[4]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.sa_stall[3] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] invalidate debugNodeOut.va_stall[3] connect destNodesIn, auto.dest_nodes_in_0 connect destNodesIn_1, auto.dest_nodes_in_1 connect auto.source_nodes_out_0, sourceNodesOut connect auto.source_nodes_out_1, sourceNodesOut_1 connect ingressNodesIn, auto.ingress_nodes_in_0 connect ingressNodesIn_1, auto.ingress_nodes_in_1 connect auto.egress_nodes_out, egressNodesOut connect auto.debug_out, debugNodeOut inst input_unit_0_from_2 of InputUnit_8 connect input_unit_0_from_2.clock, clock connect input_unit_0_from_2.reset, reset inst input_unit_1_from_7 of InputUnit_9 connect input_unit_1_from_7.clock, clock connect input_unit_1_from_7.reset, reset inst ingress_unit_2_from_8 of IngressUnit_9 connect ingress_unit_2_from_8.clock, clock connect ingress_unit_2_from_8.reset, reset inst ingress_unit_3_from_9 of IngressUnit_10 connect ingress_unit_3_from_9.clock, clock connect ingress_unit_3_from_9.reset, reset inst output_unit_0_to_2 of OutputUnit_8 connect output_unit_0_to_2.clock, clock connect output_unit_0_to_2.reset, reset inst output_unit_1_to_7 of OutputUnit_9 connect output_unit_1_to_7.clock, clock connect output_unit_1_to_7.reset, reset inst egress_unit_2_to_4 of EgressUnit_6 connect egress_unit_2_to_4.clock, clock connect egress_unit_2_to_4.reset, reset inst switch of Switch_3 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_3 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_3 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_3 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = and(vc_allocator.io.req.`3`.ready, vc_allocator.io.req.`3`.valid) node _fires_count_T_4 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_5 = bits(_fires_count_T_4, 1, 0) node _fires_count_T_6 = add(_fires_count_T_2, _fires_count_T_3) node _fires_count_T_7 = bits(_fires_count_T_6, 1, 0) node _fires_count_T_8 = add(_fires_count_T_5, _fires_count_T_7) node _fires_count_T_9 = bits(_fires_count_T_8, 2, 0) wire fires_count : UInt connect fires_count, _fires_count_T_9 connect input_unit_0_from_2.io.in, destNodesIn connect input_unit_1_from_7.io.in, destNodesIn_1 connect ingress_unit_2_from_8.io.in, ingressNodesIn.flit connect ingress_unit_3_from_9.io.in, ingressNodesIn_1.flit connect output_unit_0_to_2.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_2.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_2.io.out.flit connect output_unit_1_to_7.io.out.vc_free, sourceNodesOut_1.vc_free connect output_unit_1_to_7.io.out.credit_return, sourceNodesOut_1.credit_return connect sourceNodesOut_1.flit, output_unit_1_to_7.io.out.flit connect egressNodesOut.flit.bits, egress_unit_2_to_4.io.out.bits connect egressNodesOut.flit.valid, egress_unit_2_to_4.io.out.valid connect egress_unit_2_to_4.io.out.ready, egressNodesOut.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_2.io.router_req connect route_computer.io.req.`1`, input_unit_1_from_7.io.router_req connect route_computer.io.req.`2`, ingress_unit_2_from_8.io.router_req connect route_computer.io.req.`3`, ingress_unit_3_from_9.io.router_req connect input_unit_0_from_2.io.router_resp, route_computer.io.resp.`0` connect input_unit_1_from_7.io.router_resp, route_computer.io.resp.`1` connect ingress_unit_2_from_8.io.router_resp, route_computer.io.resp.`2` connect ingress_unit_3_from_9.io.router_resp, route_computer.io.resp.`3` connect vc_allocator.io.req.`0`, input_unit_0_from_2.io.vcalloc_req connect vc_allocator.io.req.`1`, input_unit_1_from_7.io.vcalloc_req connect vc_allocator.io.req.`2`, ingress_unit_2_from_8.io.vcalloc_req connect vc_allocator.io.req.`3`, ingress_unit_3_from_9.io.vcalloc_req connect input_unit_0_from_2.io.vcalloc_resp, vc_allocator.io.resp.`0` connect input_unit_1_from_7.io.vcalloc_resp, vc_allocator.io.resp.`1` connect ingress_unit_2_from_8.io.vcalloc_resp, vc_allocator.io.resp.`2` connect ingress_unit_3_from_9.io.vcalloc_resp, vc_allocator.io.resp.`3` connect output_unit_0_to_2.io.allocs, vc_allocator.io.out_allocs.`0` connect output_unit_1_to_7.io.allocs, vc_allocator.io.out_allocs.`1` connect egress_unit_2_to_4.io.allocs, vc_allocator.io.out_allocs.`2` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_2.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_2.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_2.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_2.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_2.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_2.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_2.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_2.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_2.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_2.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_2.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_2.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_2.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_2.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_2.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_2.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_2.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_2.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_7.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_7.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_7.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_7.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_7.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_7.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_7.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_7.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_7.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_7.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_7.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_7.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_7.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_7.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_7.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_7.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_7.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_7.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_4.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_4.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_4.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_4.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_4.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_4.io.channel_status[0].occupied connect input_unit_0_from_2.io.out_credit_available.`0`[0], output_unit_0_to_2.io.credit_available[0] connect input_unit_0_from_2.io.out_credit_available.`0`[1], output_unit_0_to_2.io.credit_available[1] connect input_unit_0_from_2.io.out_credit_available.`0`[2], output_unit_0_to_2.io.credit_available[2] connect input_unit_0_from_2.io.out_credit_available.`1`[0], output_unit_1_to_7.io.credit_available[0] connect input_unit_0_from_2.io.out_credit_available.`1`[1], output_unit_1_to_7.io.credit_available[1] connect input_unit_0_from_2.io.out_credit_available.`1`[2], output_unit_1_to_7.io.credit_available[2] connect input_unit_0_from_2.io.out_credit_available.`2`[0], egress_unit_2_to_4.io.credit_available[0] connect input_unit_1_from_7.io.out_credit_available.`0`[0], output_unit_0_to_2.io.credit_available[0] connect input_unit_1_from_7.io.out_credit_available.`0`[1], output_unit_0_to_2.io.credit_available[1] connect input_unit_1_from_7.io.out_credit_available.`0`[2], output_unit_0_to_2.io.credit_available[2] connect input_unit_1_from_7.io.out_credit_available.`1`[0], output_unit_1_to_7.io.credit_available[0] connect input_unit_1_from_7.io.out_credit_available.`1`[1], output_unit_1_to_7.io.credit_available[1] connect input_unit_1_from_7.io.out_credit_available.`1`[2], output_unit_1_to_7.io.credit_available[2] connect input_unit_1_from_7.io.out_credit_available.`2`[0], egress_unit_2_to_4.io.credit_available[0] connect ingress_unit_2_from_8.io.out_credit_available.`0`[0], output_unit_0_to_2.io.credit_available[0] connect ingress_unit_2_from_8.io.out_credit_available.`0`[1], output_unit_0_to_2.io.credit_available[1] connect ingress_unit_2_from_8.io.out_credit_available.`0`[2], output_unit_0_to_2.io.credit_available[2] connect ingress_unit_2_from_8.io.out_credit_available.`1`[0], output_unit_1_to_7.io.credit_available[0] connect ingress_unit_2_from_8.io.out_credit_available.`1`[1], output_unit_1_to_7.io.credit_available[1] connect ingress_unit_2_from_8.io.out_credit_available.`1`[2], output_unit_1_to_7.io.credit_available[2] connect ingress_unit_2_from_8.io.out_credit_available.`2`[0], egress_unit_2_to_4.io.credit_available[0] connect ingress_unit_3_from_9.io.out_credit_available.`0`[0], output_unit_0_to_2.io.credit_available[0] connect ingress_unit_3_from_9.io.out_credit_available.`0`[1], output_unit_0_to_2.io.credit_available[1] connect ingress_unit_3_from_9.io.out_credit_available.`0`[2], output_unit_0_to_2.io.credit_available[2] connect ingress_unit_3_from_9.io.out_credit_available.`1`[0], output_unit_1_to_7.io.credit_available[0] connect ingress_unit_3_from_9.io.out_credit_available.`1`[1], output_unit_1_to_7.io.credit_available[1] connect ingress_unit_3_from_9.io.out_credit_available.`1`[2], output_unit_1_to_7.io.credit_available[2] connect ingress_unit_3_from_9.io.out_credit_available.`2`[0], egress_unit_2_to_4.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_2.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], input_unit_1_from_7.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_8.io.salloc_req[0] connect switch_allocator.io.req.`3`[0], ingress_unit_3_from_9.io.salloc_req[0] connect output_unit_0_to_2.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_2.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_2.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_2.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_2.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_2.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_1_to_7.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect output_unit_1_to_7.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect output_unit_1_to_7.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail connect output_unit_1_to_7.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc connect output_unit_1_to_7.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail connect output_unit_1_to_7.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc connect egress_unit_2_to_4.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect egress_unit_2_to_4.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_2.io.out[0] connect switch.io.in.`1`[0], input_unit_1_from_7.io.out[0] connect switch.io.in.`2`[0], ingress_unit_2_from_8.io.out[0] connect switch.io.in.`3`[0], ingress_unit_3_from_9.io.out[0] connect output_unit_0_to_2.io.in, switch.io.out.`0` connect output_unit_1_to_7.io.in, switch.io.out.`1` connect egress_unit_2_to_4.io.in, switch.io.out.`2` connect switch.io.sel.`0`[0].`0`[0], switch_allocator.io.switch_sel.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], switch_allocator.io.switch_sel.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], switch_allocator.io.switch_sel.`0`[0].`2`[0] connect switch.io.sel.`0`[0].`3`[0], switch_allocator.io.switch_sel.`0`[0].`3`[0] connect switch.io.sel.`1`[0].`0`[0], switch_allocator.io.switch_sel.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], switch_allocator.io.switch_sel.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], switch_allocator.io.switch_sel.`1`[0].`2`[0] connect switch.io.sel.`1`[0].`3`[0], switch_allocator.io.switch_sel.`1`[0].`3`[0] connect switch.io.sel.`2`[0].`0`[0], switch_allocator.io.switch_sel.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], switch_allocator.io.switch_sel.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], switch_allocator.io.switch_sel.`2`[0].`2`[0] connect switch.io.sel.`2`[0].`3`[0], switch_allocator.io.switch_sel.`2`[0].`3`[0] connect input_unit_0_from_2.io.block, UInt<1>(0h0) connect input_unit_1_from_7.io.block, UInt<1>(0h0) connect ingress_unit_2_from_8.io.block, UInt<1>(0h0) connect ingress_unit_3_from_9.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_2.io.debug.va_stall connect debugNodeOut.va_stall[1], input_unit_1_from_7.io.debug.va_stall connect debugNodeOut.va_stall[2], ingress_unit_2_from_8.io.debug.va_stall connect debugNodeOut.va_stall[3], ingress_unit_3_from_9.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_2.io.debug.sa_stall connect debugNodeOut.sa_stall[1], input_unit_1_from_7.io.debug.sa_stall connect debugNodeOut.sa_stall[2], ingress_unit_2_from_8.io.debug.sa_stall connect debugNodeOut.sa_stall[3], ingress_unit_3_from_9.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_29 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 2 3 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid) connect fired_1, _fired_T_1 node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_13 = tail(_T_12, 1) node _T_14 = eq(debug_sample, _T_13) node _T_15 = and(_T_11, _T_14) node _T_16 = and(_T_15, fired_1) when _T_16 : node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "nocsample %d 7 3 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, destNodesIn_1.flit[0].valid node _T_19 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, _T_19) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, _T_19) connect fired_2, _fired_T_2 node _T_20 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_21 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_22 = tail(_T_21, 1) node _T_23 = eq(debug_sample, _T_22) node _T_24 = and(_T_20, _T_23) node _T_25 = and(_T_24, fired_2) when _T_25 : node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : printf(clock, UInt<1>(0h1), "nocsample %d i8 3 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, _T_19 node _T_28 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid) regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_6 = add(util_ctr_3, _T_28) node _util_ctr_T_7 = tail(_util_ctr_T_6, 1) connect util_ctr_3, _util_ctr_T_7 node _fired_T_3 = or(fired_3, _T_28) connect fired_3, _fired_T_3 node _T_29 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_30 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_31 = tail(_T_30, 1) node _T_32 = eq(debug_sample, _T_31) node _T_33 = and(_T_29, _T_32) node _T_34 = and(_T_33, fired_3) when _T_34 : node _T_35 = asUInt(reset) node _T_36 = eq(_T_35, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "nocsample %d i9 3 %d\n", debug_tsc, util_ctr_3) : printf_3 connect fired_3, _T_28 node _T_37 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_8 = add(util_ctr_4, _T_37) node _util_ctr_T_9 = tail(_util_ctr_T_8, 1) connect util_ctr_4, _util_ctr_T_9 node _fired_T_4 = or(fired_4, _T_37) connect fired_4, _fired_T_4 node _T_38 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_39 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_40 = tail(_T_39, 1) node _T_41 = eq(debug_sample, _T_40) node _T_42 = and(_T_38, _T_41) node _T_43 = and(_T_42, fired_4) when _T_43 : node _T_44 = asUInt(reset) node _T_45 = eq(_T_44, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "nocsample %d 3 e4 %d\n", debug_tsc, util_ctr_4) : printf_4 connect fired_4, _T_37
module Router_3( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_0_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_2_to_4_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_2_to_4_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_2_to_4_io_out_valid; // @[Router.scala:125:13] wire _output_unit_1_to_7_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_1_to_7_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_2_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_2_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_2_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_2_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _ingress_unit_3_from_9_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [144:0] _ingress_unit_3_from_9_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_9_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_3_from_9_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_9_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_3_from_9_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_9_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_9_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_3_from_9_io_in_ready; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [144:0] _ingress_unit_2_from_8_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_8_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_2_from_8_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_8_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_2_from_8_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_8_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_8_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_2_from_8_io_in_ready; // @[Router.scala:116:13] wire _input_unit_1_from_7_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_7_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_7_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_7_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_7_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_7_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_7_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_7_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_7_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_7_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_7_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_7_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_7_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_1_from_7_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_7_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_7_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_7_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_7_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_7_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_2_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_2_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_2_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_0_from_2_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_2_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_7_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_8_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _ingress_unit_3_from_9_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_46 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_EntryData_46( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_101 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<5>, vc_free : UInt<5>}} wire _in_flight_WIRE : UInt<1>[5] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) regreset in_flight : UInt<1>[5], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_13 = and(_T_11, _T_12) node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_17 = and(_T_15, _T_16) node _T_18 = or(_T_10, _T_17) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_18, UInt<1>(0h1), "") : assert_2 node _T_22 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_23 = or(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_23, UInt<1>(0h1), "") : assert_3 node _T_27 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_28 = or(_T_27, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_28, UInt<1>(0h1), "") : assert_4 node _T_32 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_33 = or(_T_32, UInt<1>(0h0)) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_33, UInt<1>(0h1), "") : assert_5
module NoCMonitor_101( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h4; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_1 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_1 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags
module RoundRawFNToRecFN_e8_s24_1( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_1 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_61 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_61( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NBDTLB : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<34>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}[1], miss_rdy : UInt<1>, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}[1], flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<33>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<21>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<33>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} reg sectored_entries : { level : UInt<2>, tag : UInt<21>, data : UInt<34>[4], valid : UInt<1>[4]}[8], clock reg superpage_entries : { level : UInt<2>, tag : UInt<21>, data : UInt<34>[1], valid : UInt<1>[1]}[4], clock reg special_entry : { level : UInt<2>, tag : UInt<21>, data : UInt<34>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<21>, clock reg r_superpage_repl_addr : UInt<2>, clock reg r_sectored_repl_addr : UInt<3>, clock reg r_sectored_hit_addr : UInt<3>, clock reg r_sectored_hit : UInt<1>, clock node priv_s = bits(io.ptw.status.dprv, 0, 0) node priv_uses_vm = leq(io.ptw.status.dprv, UInt<1>(0h1)) node _vm_enabled_T = bits(io.ptw.ptbr.mode, 3, 3) node _vm_enabled_T_1 = and(UInt<1>(0h0), _vm_enabled_T) node _vm_enabled_T_2 = and(_vm_enabled_T_1, priv_uses_vm) node _vm_enabled_T_3 = eq(io.req[0].bits.passthrough, UInt<1>(0h0)) node _vm_enabled_T_4 = and(_vm_enabled_T_2, _vm_enabled_T_3) wire vm_enabled : UInt<1>[1] connect vm_enabled[0], _vm_enabled_T_4 node _vpn_T = bits(io.req[0].bits.vaddr, 32, 12) wire vpn : UInt<21>[1] connect vpn[0], _vpn_T node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h0), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled[0], UInt<1>(0h1)) wire _mpu_ppn_data_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_data_WIRE_1 : UInt<34> connect _mpu_ppn_data_WIRE_1, special_entry.data[0] node _mpu_ppn_data_T = bits(_mpu_ppn_data_WIRE_1, 0, 0) connect _mpu_ppn_data_WIRE.fragmented_superpage, _mpu_ppn_data_T node _mpu_ppn_data_T_1 = bits(_mpu_ppn_data_WIRE_1, 1, 1) connect _mpu_ppn_data_WIRE.c, _mpu_ppn_data_T_1 node _mpu_ppn_data_T_2 = bits(_mpu_ppn_data_WIRE_1, 2, 2) connect _mpu_ppn_data_WIRE.eff, _mpu_ppn_data_T_2 node _mpu_ppn_data_T_3 = bits(_mpu_ppn_data_WIRE_1, 3, 3) connect _mpu_ppn_data_WIRE.paa, _mpu_ppn_data_T_3 node _mpu_ppn_data_T_4 = bits(_mpu_ppn_data_WIRE_1, 4, 4) connect _mpu_ppn_data_WIRE.pal, _mpu_ppn_data_T_4 node _mpu_ppn_data_T_5 = bits(_mpu_ppn_data_WIRE_1, 5, 5) connect _mpu_ppn_data_WIRE.pr, _mpu_ppn_data_T_5 node _mpu_ppn_data_T_6 = bits(_mpu_ppn_data_WIRE_1, 6, 6) connect _mpu_ppn_data_WIRE.px, _mpu_ppn_data_T_6 node _mpu_ppn_data_T_7 = bits(_mpu_ppn_data_WIRE_1, 7, 7) connect _mpu_ppn_data_WIRE.pw, _mpu_ppn_data_T_7 node _mpu_ppn_data_T_8 = bits(_mpu_ppn_data_WIRE_1, 8, 8) connect _mpu_ppn_data_WIRE.sr, _mpu_ppn_data_T_8 node _mpu_ppn_data_T_9 = bits(_mpu_ppn_data_WIRE_1, 9, 9) connect _mpu_ppn_data_WIRE.sx, _mpu_ppn_data_T_9 node _mpu_ppn_data_T_10 = bits(_mpu_ppn_data_WIRE_1, 10, 10) connect _mpu_ppn_data_WIRE.sw, _mpu_ppn_data_T_10 node _mpu_ppn_data_T_11 = bits(_mpu_ppn_data_WIRE_1, 11, 11) connect _mpu_ppn_data_WIRE.ae, _mpu_ppn_data_T_11 node _mpu_ppn_data_T_12 = bits(_mpu_ppn_data_WIRE_1, 12, 12) connect _mpu_ppn_data_WIRE.g, _mpu_ppn_data_T_12 node _mpu_ppn_data_T_13 = bits(_mpu_ppn_data_WIRE_1, 13, 13) connect _mpu_ppn_data_WIRE.u, _mpu_ppn_data_T_13 node _mpu_ppn_data_T_14 = bits(_mpu_ppn_data_WIRE_1, 33, 14) connect _mpu_ppn_data_WIRE.ppn, _mpu_ppn_data_T_14 inst mpu_ppn_data_barrier of OptimizationBarrier_EntryData connect mpu_ppn_data_barrier.clock, clock connect mpu_ppn_data_barrier.reset, reset connect mpu_ppn_data_barrier.io.x.fragmented_superpage, _mpu_ppn_data_WIRE.fragmented_superpage connect mpu_ppn_data_barrier.io.x.c, _mpu_ppn_data_WIRE.c connect mpu_ppn_data_barrier.io.x.eff, _mpu_ppn_data_WIRE.eff connect mpu_ppn_data_barrier.io.x.paa, _mpu_ppn_data_WIRE.paa connect mpu_ppn_data_barrier.io.x.pal, _mpu_ppn_data_WIRE.pal connect mpu_ppn_data_barrier.io.x.pr, _mpu_ppn_data_WIRE.pr connect mpu_ppn_data_barrier.io.x.px, _mpu_ppn_data_WIRE.px connect mpu_ppn_data_barrier.io.x.pw, _mpu_ppn_data_WIRE.pw connect mpu_ppn_data_barrier.io.x.sr, _mpu_ppn_data_WIRE.sr connect mpu_ppn_data_barrier.io.x.sx, _mpu_ppn_data_WIRE.sx connect mpu_ppn_data_barrier.io.x.sw, _mpu_ppn_data_WIRE.sw connect mpu_ppn_data_barrier.io.x.ae, _mpu_ppn_data_WIRE.ae connect mpu_ppn_data_barrier.io.x.g, _mpu_ppn_data_WIRE.g connect mpu_ppn_data_barrier.io.x.u, _mpu_ppn_data_WIRE.u connect mpu_ppn_data_barrier.io.x.ppn, _mpu_ppn_data_WIRE.ppn node _mpu_ppn_T_1 = shr(io.req[0].bits.vaddr, 12) node _mpu_ppn_T_2 = mux(_mpu_ppn_T, mpu_ppn_data_barrier.io.y.ppn, _mpu_ppn_T_1) node _mpu_ppn_T_3 = mux(do_refill, refill_ppn, _mpu_ppn_T_2) wire mpu_ppn : UInt<22>[1] connect mpu_ppn[0], _mpu_ppn_T_3 node _mpu_physaddr_T = bits(io.req[0].bits.vaddr, 11, 0) node _mpu_physaddr_T_1 = cat(mpu_ppn[0], _mpu_physaddr_T) wire mpu_physaddr : UInt<34>[1] connect mpu_physaddr[0], _mpu_physaddr_T_1 inst pmp_0 of PMPChecker_s3 connect pmp_0.clock, clock connect pmp_0.reset, reset connect pmp_0.io.addr, mpu_physaddr[0] connect pmp_0.io.size, io.req[0].bits.size node _pmp_0_io_prv_T = or(do_refill, io.req[0].bits.passthrough) node _pmp_0_io_prv_T_1 = and(UInt<1>(0h0), _pmp_0_io_prv_T) node _pmp_0_io_prv_T_2 = mux(_pmp_0_io_prv_T_1, UInt<1>(0h1), io.ptw.status.dprv) connect pmp_0.io.prv, _pmp_0_io_prv_T_2 node _legal_address_T = xor(mpu_physaddr[0], UInt<14>(0h3000)) node _legal_address_T_1 = cvt(_legal_address_T) node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) node _legal_address_T_3 = asSInt(_legal_address_T_2) node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) node _legal_address_T_5 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _legal_address_T_6 = cvt(_legal_address_T_5) node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) node _legal_address_T_8 = asSInt(_legal_address_T_7) node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) node _legal_address_T_10 = xor(mpu_physaddr[0], UInt<21>(0h110000)) node _legal_address_T_11 = cvt(_legal_address_T_10) node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000))) node _legal_address_T_13 = asSInt(_legal_address_T_12) node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) node _legal_address_T_15 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _legal_address_T_16 = cvt(_legal_address_T_15) node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<13>(0h1000))) node _legal_address_T_18 = asSInt(_legal_address_T_17) node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) node _legal_address_T_20 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _legal_address_T_21 = cvt(_legal_address_T_20) node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<29>(0h10000000))) node _legal_address_T_23 = asSInt(_legal_address_T_22) node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) wire _legal_address_WIRE : UInt<1>[5] connect _legal_address_WIRE[0], _legal_address_T_4 connect _legal_address_WIRE[1], _legal_address_T_9 connect _legal_address_WIRE[2], _legal_address_T_14 connect _legal_address_WIRE[3], _legal_address_T_19 connect _legal_address_WIRE[4], _legal_address_T_24 node _legal_address_T_25 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) node _legal_address_T_26 = or(_legal_address_T_25, _legal_address_WIRE[2]) node _legal_address_T_27 = or(_legal_address_T_26, _legal_address_WIRE[3]) node _legal_address_T_28 = or(_legal_address_T_27, _legal_address_WIRE[4]) wire legal_address : UInt<1>[1] connect legal_address[0], _legal_address_T_28 node _cacheable_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _cacheable_T_1 = cvt(_cacheable_T) node _cacheable_T_2 = and(_cacheable_T_1, asSInt(UInt<33>(0h80000000))) node _cacheable_T_3 = asSInt(_cacheable_T_2) node _cacheable_T_4 = eq(_cacheable_T_3, asSInt(UInt<1>(0h0))) node _cacheable_T_5 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _cacheable_T_6 = cvt(_cacheable_T_5) node _cacheable_T_7 = and(_cacheable_T_6, asSInt(UInt<33>(0h80000000))) node _cacheable_T_8 = asSInt(_cacheable_T_7) node _cacheable_T_9 = eq(_cacheable_T_8, asSInt(UInt<1>(0h0))) node _cacheable_T_10 = mux(_cacheable_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _cacheable_T_11 = mux(_cacheable_T_9, UInt<1>(0h1), UInt<1>(0h0)) node _cacheable_T_12 = or(_cacheable_T_10, _cacheable_T_11) wire _cacheable_WIRE : UInt<1> connect _cacheable_WIRE, _cacheable_T_12 node _cacheable_T_13 = and(legal_address[0], _cacheable_WIRE) node _cacheable_T_14 = and(_cacheable_T_13, UInt<1>(0h1)) wire cacheable : UInt<1>[1] connect cacheable[0], _cacheable_T_14 node _homogeneous_T = xor(mpu_physaddr[0], UInt<14>(0h3000)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<13>(0h1000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<13>(0h1000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_21 = or(_homogeneous_T_20, _homogeneous_T_9) node _homogeneous_T_22 = or(_homogeneous_T_21, _homogeneous_T_14) node _homogeneous_T_23 = or(_homogeneous_T_22, _homogeneous_T_19) node _homogeneous_T_24 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_25 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_26 = xor(mpu_physaddr[0], UInt<1>(0h0)) node _homogeneous_T_27 = cvt(_homogeneous_T_26) node _homogeneous_T_28 = and(_homogeneous_T_27, asSInt(UInt<33>(0h80002000))) node _homogeneous_T_29 = asSInt(_homogeneous_T_28) node _homogeneous_T_30 = eq(_homogeneous_T_29, asSInt(UInt<1>(0h0))) node _homogeneous_T_31 = or(UInt<1>(0h0), _homogeneous_T_30) node _homogeneous_T_32 = eq(_homogeneous_T_31, UInt<1>(0h0)) node _homogeneous_T_33 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _homogeneous_T_34 = cvt(_homogeneous_T_33) node _homogeneous_T_35 = and(_homogeneous_T_34, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_36 = asSInt(_homogeneous_T_35) node _homogeneous_T_37 = eq(_homogeneous_T_36, asSInt(UInt<1>(0h0))) node _homogeneous_T_38 = or(UInt<1>(0h0), _homogeneous_T_37) node _homogeneous_T_39 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_40 = eq(UInt<1>(0h0), UInt<1>(0h0)) wire homogeneous : UInt<1>[1] connect homogeneous[0], _homogeneous_T_23 node _prot_r_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_r_T_1 = cvt(_prot_r_T) node _prot_r_T_2 = and(_prot_r_T_1, asSInt(UInt<1>(0h0))) node _prot_r_T_3 = asSInt(_prot_r_T_2) node _prot_r_T_4 = eq(_prot_r_T_3, asSInt(UInt<1>(0h0))) node _prot_r_T_5 = and(legal_address[0], UInt<1>(0h1)) node _prot_r_T_6 = and(_prot_r_T_5, pmp_0.io.r) wire prot_r : UInt<1>[1] connect prot_r[0], _prot_r_T_6 node _prot_w_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_w_T_1 = cvt(_prot_w_T) node _prot_w_T_2 = and(_prot_w_T_1, asSInt(UInt<1>(0h0))) node _prot_w_T_3 = asSInt(_prot_w_T_2) node _prot_w_T_4 = eq(_prot_w_T_3, asSInt(UInt<1>(0h0))) node _prot_w_T_5 = and(legal_address[0], UInt<1>(0h1)) node _prot_w_T_6 = and(_prot_w_T_5, pmp_0.io.w) wire prot_w : UInt<1>[1] connect prot_w[0], _prot_w_T_6 node _prot_al_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_al_T_1 = cvt(_prot_al_T) node _prot_al_T_2 = and(_prot_al_T_1, asSInt(UInt<1>(0h0))) node _prot_al_T_3 = asSInt(_prot_al_T_2) node _prot_al_T_4 = eq(_prot_al_T_3, asSInt(UInt<1>(0h0))) node _prot_al_T_5 = and(legal_address[0], UInt<1>(0h1)) wire prot_al : UInt<1>[1] connect prot_al[0], _prot_al_T_5 node _prot_aa_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_aa_T_1 = cvt(_prot_aa_T) node _prot_aa_T_2 = and(_prot_aa_T_1, asSInt(UInt<1>(0h0))) node _prot_aa_T_3 = asSInt(_prot_aa_T_2) node _prot_aa_T_4 = eq(_prot_aa_T_3, asSInt(UInt<1>(0h0))) node _prot_aa_T_5 = and(legal_address[0], UInt<1>(0h1)) wire prot_aa : UInt<1>[1] connect prot_aa[0], _prot_aa_T_5 node _prot_x_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_x_T_1 = cvt(_prot_x_T) node _prot_x_T_2 = and(_prot_x_T_1, asSInt(UInt<33>(0h80110000))) node _prot_x_T_3 = asSInt(_prot_x_T_2) node _prot_x_T_4 = eq(_prot_x_T_3, asSInt(UInt<1>(0h0))) node _prot_x_T_5 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _prot_x_T_6 = cvt(_prot_x_T_5) node _prot_x_T_7 = and(_prot_x_T_6, asSInt(UInt<33>(0h80000000))) node _prot_x_T_8 = asSInt(_prot_x_T_7) node _prot_x_T_9 = eq(_prot_x_T_8, asSInt(UInt<1>(0h0))) node _prot_x_T_10 = or(_prot_x_T_4, _prot_x_T_9) node _prot_x_T_11 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _prot_x_T_12 = cvt(_prot_x_T_11) node _prot_x_T_13 = and(_prot_x_T_12, asSInt(UInt<33>(0h80110000))) node _prot_x_T_14 = asSInt(_prot_x_T_13) node _prot_x_T_15 = eq(_prot_x_T_14, asSInt(UInt<1>(0h0))) node _prot_x_T_16 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _prot_x_T_17 = cvt(_prot_x_T_16) node _prot_x_T_18 = and(_prot_x_T_17, asSInt(UInt<33>(0h80100000))) node _prot_x_T_19 = asSInt(_prot_x_T_18) node _prot_x_T_20 = eq(_prot_x_T_19, asSInt(UInt<1>(0h0))) node _prot_x_T_21 = or(_prot_x_T_15, _prot_x_T_20) node _prot_x_T_22 = mux(_prot_x_T_10, UInt<1>(0h1), UInt<1>(0h0)) node _prot_x_T_23 = mux(_prot_x_T_21, UInt<1>(0h0), UInt<1>(0h0)) node _prot_x_T_24 = or(_prot_x_T_22, _prot_x_T_23) wire _prot_x_WIRE : UInt<1> connect _prot_x_WIRE, _prot_x_T_24 node _prot_x_T_25 = and(legal_address[0], _prot_x_WIRE) node _prot_x_T_26 = and(_prot_x_T_25, pmp_0.io.x) wire prot_x : UInt<1>[1] connect prot_x[0], _prot_x_T_26 node _prot_eff_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_eff_T_1 = cvt(_prot_eff_T) node _prot_eff_T_2 = and(_prot_eff_T_1, asSInt(UInt<33>(0h80110000))) node _prot_eff_T_3 = asSInt(_prot_eff_T_2) node _prot_eff_T_4 = eq(_prot_eff_T_3, asSInt(UInt<1>(0h0))) node _prot_eff_T_5 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _prot_eff_T_6 = cvt(_prot_eff_T_5) node _prot_eff_T_7 = and(_prot_eff_T_6, asSInt(UInt<33>(0h80000000))) node _prot_eff_T_8 = asSInt(_prot_eff_T_7) node _prot_eff_T_9 = eq(_prot_eff_T_8, asSInt(UInt<1>(0h0))) node _prot_eff_T_10 = or(_prot_eff_T_4, _prot_eff_T_9) node _prot_eff_T_11 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _prot_eff_T_12 = cvt(_prot_eff_T_11) node _prot_eff_T_13 = and(_prot_eff_T_12, asSInt(UInt<33>(0h80110000))) node _prot_eff_T_14 = asSInt(_prot_eff_T_13) node _prot_eff_T_15 = eq(_prot_eff_T_14, asSInt(UInt<1>(0h0))) node _prot_eff_T_16 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _prot_eff_T_17 = cvt(_prot_eff_T_16) node _prot_eff_T_18 = and(_prot_eff_T_17, asSInt(UInt<33>(0h80100000))) node _prot_eff_T_19 = asSInt(_prot_eff_T_18) node _prot_eff_T_20 = eq(_prot_eff_T_19, asSInt(UInt<1>(0h0))) node _prot_eff_T_21 = or(_prot_eff_T_15, _prot_eff_T_20) node _prot_eff_T_22 = mux(_prot_eff_T_10, UInt<1>(0h0), UInt<1>(0h0)) node _prot_eff_T_23 = mux(_prot_eff_T_21, UInt<1>(0h1), UInt<1>(0h0)) node _prot_eff_T_24 = or(_prot_eff_T_22, _prot_eff_T_23) wire _prot_eff_WIRE : UInt<1> connect _prot_eff_WIRE, _prot_eff_T_24 node _prot_eff_T_25 = and(legal_address[0], _prot_eff_WIRE) wire prot_eff : UInt<1>[1] connect prot_eff[0], _prot_eff_T_25 node _sector_hits_T = or(sectored_entries[0].valid[0], sectored_entries[0].valid[1]) node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0].valid[2]) node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0].valid[3]) node _sector_hits_T_3 = xor(sectored_entries[0].tag, vpn[0]) node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) node _sector_hits_T_6 = and(_sector_hits_T_2, _sector_hits_T_5) node _sector_hits_T_7 = or(sectored_entries[1].valid[0], sectored_entries[1].valid[1]) node _sector_hits_T_8 = or(_sector_hits_T_7, sectored_entries[1].valid[2]) node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[1].valid[3]) node _sector_hits_T_10 = xor(sectored_entries[1].tag, vpn[0]) node _sector_hits_T_11 = shr(_sector_hits_T_10, 2) node _sector_hits_T_12 = eq(_sector_hits_T_11, UInt<1>(0h0)) node _sector_hits_T_13 = and(_sector_hits_T_9, _sector_hits_T_12) node _sector_hits_T_14 = or(sectored_entries[2].valid[0], sectored_entries[2].valid[1]) node _sector_hits_T_15 = or(_sector_hits_T_14, sectored_entries[2].valid[2]) node _sector_hits_T_16 = or(_sector_hits_T_15, sectored_entries[2].valid[3]) node _sector_hits_T_17 = xor(sectored_entries[2].tag, vpn[0]) node _sector_hits_T_18 = shr(_sector_hits_T_17, 2) node _sector_hits_T_19 = eq(_sector_hits_T_18, UInt<1>(0h0)) node _sector_hits_T_20 = and(_sector_hits_T_16, _sector_hits_T_19) node _sector_hits_T_21 = or(sectored_entries[3].valid[0], sectored_entries[3].valid[1]) node _sector_hits_T_22 = or(_sector_hits_T_21, sectored_entries[3].valid[2]) node _sector_hits_T_23 = or(_sector_hits_T_22, sectored_entries[3].valid[3]) node _sector_hits_T_24 = xor(sectored_entries[3].tag, vpn[0]) node _sector_hits_T_25 = shr(_sector_hits_T_24, 2) node _sector_hits_T_26 = eq(_sector_hits_T_25, UInt<1>(0h0)) node _sector_hits_T_27 = and(_sector_hits_T_23, _sector_hits_T_26) node _sector_hits_T_28 = or(sectored_entries[4].valid[0], sectored_entries[4].valid[1]) node _sector_hits_T_29 = or(_sector_hits_T_28, sectored_entries[4].valid[2]) node _sector_hits_T_30 = or(_sector_hits_T_29, sectored_entries[4].valid[3]) node _sector_hits_T_31 = xor(sectored_entries[4].tag, vpn[0]) node _sector_hits_T_32 = shr(_sector_hits_T_31, 2) node _sector_hits_T_33 = eq(_sector_hits_T_32, UInt<1>(0h0)) node _sector_hits_T_34 = and(_sector_hits_T_30, _sector_hits_T_33) node _sector_hits_T_35 = or(sectored_entries[5].valid[0], sectored_entries[5].valid[1]) node _sector_hits_T_36 = or(_sector_hits_T_35, sectored_entries[5].valid[2]) node _sector_hits_T_37 = or(_sector_hits_T_36, sectored_entries[5].valid[3]) node _sector_hits_T_38 = xor(sectored_entries[5].tag, vpn[0]) node _sector_hits_T_39 = shr(_sector_hits_T_38, 2) node _sector_hits_T_40 = eq(_sector_hits_T_39, UInt<1>(0h0)) node _sector_hits_T_41 = and(_sector_hits_T_37, _sector_hits_T_40) node _sector_hits_T_42 = or(sectored_entries[6].valid[0], sectored_entries[6].valid[1]) node _sector_hits_T_43 = or(_sector_hits_T_42, sectored_entries[6].valid[2]) node _sector_hits_T_44 = or(_sector_hits_T_43, sectored_entries[6].valid[3]) node _sector_hits_T_45 = xor(sectored_entries[6].tag, vpn[0]) node _sector_hits_T_46 = shr(_sector_hits_T_45, 2) node _sector_hits_T_47 = eq(_sector_hits_T_46, UInt<1>(0h0)) node _sector_hits_T_48 = and(_sector_hits_T_44, _sector_hits_T_47) node _sector_hits_T_49 = or(sectored_entries[7].valid[0], sectored_entries[7].valid[1]) node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[7].valid[2]) node _sector_hits_T_51 = or(_sector_hits_T_50, sectored_entries[7].valid[3]) node _sector_hits_T_52 = xor(sectored_entries[7].tag, vpn[0]) node _sector_hits_T_53 = shr(_sector_hits_T_52, 2) node _sector_hits_T_54 = eq(_sector_hits_T_53, UInt<1>(0h0)) node _sector_hits_T_55 = and(_sector_hits_T_51, _sector_hits_T_54) wire _sector_hits_WIRE : UInt<1>[8] connect _sector_hits_WIRE[0], _sector_hits_T_6 connect _sector_hits_WIRE[1], _sector_hits_T_13 connect _sector_hits_WIRE[2], _sector_hits_T_20 connect _sector_hits_WIRE[3], _sector_hits_T_27 connect _sector_hits_WIRE[4], _sector_hits_T_34 connect _sector_hits_WIRE[5], _sector_hits_T_41 connect _sector_hits_WIRE[6], _sector_hits_T_48 connect _sector_hits_WIRE[7], _sector_hits_T_55 wire sector_hits : UInt<1>[8][1] connect sector_hits[0], _sector_hits_WIRE node _superpage_hits_T = xor(superpage_entries[0].tag, vpn[0]) node _superpage_hits_T_1 = shr(_superpage_hits_T, 0) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = and(superpage_entries[0].valid[0], _superpage_hits_T_2) node _superpage_hits_T_4 = xor(superpage_entries[1].tag, vpn[0]) node _superpage_hits_T_5 = shr(_superpage_hits_T_4, 0) node _superpage_hits_T_6 = eq(_superpage_hits_T_5, UInt<1>(0h0)) node _superpage_hits_T_7 = and(superpage_entries[1].valid[0], _superpage_hits_T_6) node _superpage_hits_T_8 = xor(superpage_entries[2].tag, vpn[0]) node _superpage_hits_T_9 = shr(_superpage_hits_T_8, 0) node _superpage_hits_T_10 = eq(_superpage_hits_T_9, UInt<1>(0h0)) node _superpage_hits_T_11 = and(superpage_entries[2].valid[0], _superpage_hits_T_10) node _superpage_hits_T_12 = xor(superpage_entries[3].tag, vpn[0]) node _superpage_hits_T_13 = shr(_superpage_hits_T_12, 0) node _superpage_hits_T_14 = eq(_superpage_hits_T_13, UInt<1>(0h0)) node _superpage_hits_T_15 = and(superpage_entries[3].valid[0], _superpage_hits_T_14) wire _superpage_hits_WIRE : UInt<1>[4] connect _superpage_hits_WIRE[0], _superpage_hits_T_3 connect _superpage_hits_WIRE[1], _superpage_hits_T_7 connect _superpage_hits_WIRE[2], _superpage_hits_T_11 connect _superpage_hits_WIRE[3], _superpage_hits_T_15 wire superpage_hits : UInt<1>[4][1] connect superpage_hits[0], _superpage_hits_WIRE node hitsVec_idx = bits(vpn[0], 1, 0) node _hitsVec_T = xor(sectored_entries[0].tag, vpn[0]) node _hitsVec_T_1 = shr(_hitsVec_T, 2) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = and(sectored_entries[0].valid[hitsVec_idx], _hitsVec_T_2) node _hitsVec_T_4 = and(vm_enabled[0], _hitsVec_T_3) node hitsVec_idx_1 = bits(vpn[0], 1, 0) node _hitsVec_T_5 = xor(sectored_entries[1].tag, vpn[0]) node _hitsVec_T_6 = shr(_hitsVec_T_5, 2) node _hitsVec_T_7 = eq(_hitsVec_T_6, UInt<1>(0h0)) node _hitsVec_T_8 = and(sectored_entries[1].valid[hitsVec_idx_1], _hitsVec_T_7) node _hitsVec_T_9 = and(vm_enabled[0], _hitsVec_T_8) node hitsVec_idx_2 = bits(vpn[0], 1, 0) node _hitsVec_T_10 = xor(sectored_entries[2].tag, vpn[0]) node _hitsVec_T_11 = shr(_hitsVec_T_10, 2) node _hitsVec_T_12 = eq(_hitsVec_T_11, UInt<1>(0h0)) node _hitsVec_T_13 = and(sectored_entries[2].valid[hitsVec_idx_2], _hitsVec_T_12) node _hitsVec_T_14 = and(vm_enabled[0], _hitsVec_T_13) node hitsVec_idx_3 = bits(vpn[0], 1, 0) node _hitsVec_T_15 = xor(sectored_entries[3].tag, vpn[0]) node _hitsVec_T_16 = shr(_hitsVec_T_15, 2) node _hitsVec_T_17 = eq(_hitsVec_T_16, UInt<1>(0h0)) node _hitsVec_T_18 = and(sectored_entries[3].valid[hitsVec_idx_3], _hitsVec_T_17) node _hitsVec_T_19 = and(vm_enabled[0], _hitsVec_T_18) node hitsVec_idx_4 = bits(vpn[0], 1, 0) node _hitsVec_T_20 = xor(sectored_entries[4].tag, vpn[0]) node _hitsVec_T_21 = shr(_hitsVec_T_20, 2) node _hitsVec_T_22 = eq(_hitsVec_T_21, UInt<1>(0h0)) node _hitsVec_T_23 = and(sectored_entries[4].valid[hitsVec_idx_4], _hitsVec_T_22) node _hitsVec_T_24 = and(vm_enabled[0], _hitsVec_T_23) node hitsVec_idx_5 = bits(vpn[0], 1, 0) node _hitsVec_T_25 = xor(sectored_entries[5].tag, vpn[0]) node _hitsVec_T_26 = shr(_hitsVec_T_25, 2) node _hitsVec_T_27 = eq(_hitsVec_T_26, UInt<1>(0h0)) node _hitsVec_T_28 = and(sectored_entries[5].valid[hitsVec_idx_5], _hitsVec_T_27) node _hitsVec_T_29 = and(vm_enabled[0], _hitsVec_T_28) node hitsVec_idx_6 = bits(vpn[0], 1, 0) node _hitsVec_T_30 = xor(sectored_entries[6].tag, vpn[0]) node _hitsVec_T_31 = shr(_hitsVec_T_30, 2) node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0)) node _hitsVec_T_33 = and(sectored_entries[6].valid[hitsVec_idx_6], _hitsVec_T_32) node _hitsVec_T_34 = and(vm_enabled[0], _hitsVec_T_33) node hitsVec_idx_7 = bits(vpn[0], 1, 0) node _hitsVec_T_35 = xor(sectored_entries[7].tag, vpn[0]) node _hitsVec_T_36 = shr(_hitsVec_T_35, 2) node _hitsVec_T_37 = eq(_hitsVec_T_36, UInt<1>(0h0)) node _hitsVec_T_38 = and(sectored_entries[7].valid[hitsVec_idx_7], _hitsVec_T_37) node _hitsVec_T_39 = and(vm_enabled[0], _hitsVec_T_38) node _hitsVec_T_40 = xor(superpage_entries[0].tag, vpn[0]) node _hitsVec_T_41 = shr(_hitsVec_T_40, 0) node _hitsVec_T_42 = eq(_hitsVec_T_41, UInt<1>(0h0)) node _hitsVec_T_43 = and(superpage_entries[0].valid[0], _hitsVec_T_42) node _hitsVec_T_44 = and(vm_enabled[0], _hitsVec_T_43) node _hitsVec_T_45 = xor(superpage_entries[1].tag, vpn[0]) node _hitsVec_T_46 = shr(_hitsVec_T_45, 0) node _hitsVec_T_47 = eq(_hitsVec_T_46, UInt<1>(0h0)) node _hitsVec_T_48 = and(superpage_entries[1].valid[0], _hitsVec_T_47) node _hitsVec_T_49 = and(vm_enabled[0], _hitsVec_T_48) node _hitsVec_T_50 = xor(superpage_entries[2].tag, vpn[0]) node _hitsVec_T_51 = shr(_hitsVec_T_50, 0) node _hitsVec_T_52 = eq(_hitsVec_T_51, UInt<1>(0h0)) node _hitsVec_T_53 = and(superpage_entries[2].valid[0], _hitsVec_T_52) node _hitsVec_T_54 = and(vm_enabled[0], _hitsVec_T_53) node _hitsVec_T_55 = xor(superpage_entries[3].tag, vpn[0]) node _hitsVec_T_56 = shr(_hitsVec_T_55, 0) node _hitsVec_T_57 = eq(_hitsVec_T_56, UInt<1>(0h0)) node _hitsVec_T_58 = and(superpage_entries[3].valid[0], _hitsVec_T_57) node _hitsVec_T_59 = and(vm_enabled[0], _hitsVec_T_58) node _hitsVec_T_60 = xor(special_entry.tag, vpn[0]) node _hitsVec_T_61 = shr(_hitsVec_T_60, 0) node _hitsVec_T_62 = eq(_hitsVec_T_61, UInt<1>(0h0)) node _hitsVec_T_63 = and(special_entry.valid[0], _hitsVec_T_62) node _hitsVec_T_64 = and(vm_enabled[0], _hitsVec_T_63) wire _hitsVec_WIRE : UInt<1>[13] connect _hitsVec_WIRE[0], _hitsVec_T_4 connect _hitsVec_WIRE[1], _hitsVec_T_9 connect _hitsVec_WIRE[2], _hitsVec_T_14 connect _hitsVec_WIRE[3], _hitsVec_T_19 connect _hitsVec_WIRE[4], _hitsVec_T_24 connect _hitsVec_WIRE[5], _hitsVec_T_29 connect _hitsVec_WIRE[6], _hitsVec_T_34 connect _hitsVec_WIRE[7], _hitsVec_T_39 connect _hitsVec_WIRE[8], _hitsVec_T_44 connect _hitsVec_WIRE[9], _hitsVec_T_49 connect _hitsVec_WIRE[10], _hitsVec_T_54 connect _hitsVec_WIRE[11], _hitsVec_T_59 connect _hitsVec_WIRE[12], _hitsVec_T_64 wire hitsVec : UInt<1>[13][1] connect hitsVec[0], _hitsVec_WIRE node real_hits_lo_lo_hi = cat(hitsVec[0][2], hitsVec[0][1]) node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec[0][0]) node real_hits_lo_hi_hi = cat(hitsVec[0][5], hitsVec[0][4]) node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec[0][3]) node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo) node real_hits_hi_lo_hi = cat(hitsVec[0][8], hitsVec[0][7]) node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec[0][6]) node real_hits_hi_hi_lo = cat(hitsVec[0][10], hitsVec[0][9]) node real_hits_hi_hi_hi = cat(hitsVec[0][12], hitsVec[0][11]) node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo) node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo) node _real_hits_T = cat(real_hits_hi, real_hits_lo) wire real_hits : UInt<13>[1] connect real_hits[0], _real_hits_T node _hits_T = eq(vm_enabled[0], UInt<1>(0h0)) node _hits_T_1 = cat(_hits_T, real_hits[0]) wire hits : UInt<14>[1] connect hits[0], _hits_T_1 node _ppn_T = eq(vm_enabled[0], UInt<1>(0h0)) node _ppn_data_T = bits(vpn[0], 1, 0) wire _ppn_data_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_1 : UInt<34> connect _ppn_data_WIRE_1, sectored_entries[0].data[_ppn_data_T] node _ppn_data_T_1 = bits(_ppn_data_WIRE_1, 0, 0) connect _ppn_data_WIRE.fragmented_superpage, _ppn_data_T_1 node _ppn_data_T_2 = bits(_ppn_data_WIRE_1, 1, 1) connect _ppn_data_WIRE.c, _ppn_data_T_2 node _ppn_data_T_3 = bits(_ppn_data_WIRE_1, 2, 2) connect _ppn_data_WIRE.eff, _ppn_data_T_3 node _ppn_data_T_4 = bits(_ppn_data_WIRE_1, 3, 3) connect _ppn_data_WIRE.paa, _ppn_data_T_4 node _ppn_data_T_5 = bits(_ppn_data_WIRE_1, 4, 4) connect _ppn_data_WIRE.pal, _ppn_data_T_5 node _ppn_data_T_6 = bits(_ppn_data_WIRE_1, 5, 5) connect _ppn_data_WIRE.pr, _ppn_data_T_6 node _ppn_data_T_7 = bits(_ppn_data_WIRE_1, 6, 6) connect _ppn_data_WIRE.px, _ppn_data_T_7 node _ppn_data_T_8 = bits(_ppn_data_WIRE_1, 7, 7) connect _ppn_data_WIRE.pw, _ppn_data_T_8 node _ppn_data_T_9 = bits(_ppn_data_WIRE_1, 8, 8) connect _ppn_data_WIRE.sr, _ppn_data_T_9 node _ppn_data_T_10 = bits(_ppn_data_WIRE_1, 9, 9) connect _ppn_data_WIRE.sx, _ppn_data_T_10 node _ppn_data_T_11 = bits(_ppn_data_WIRE_1, 10, 10) connect _ppn_data_WIRE.sw, _ppn_data_T_11 node _ppn_data_T_12 = bits(_ppn_data_WIRE_1, 11, 11) connect _ppn_data_WIRE.ae, _ppn_data_T_12 node _ppn_data_T_13 = bits(_ppn_data_WIRE_1, 12, 12) connect _ppn_data_WIRE.g, _ppn_data_T_13 node _ppn_data_T_14 = bits(_ppn_data_WIRE_1, 13, 13) connect _ppn_data_WIRE.u, _ppn_data_T_14 node _ppn_data_T_15 = bits(_ppn_data_WIRE_1, 33, 14) connect _ppn_data_WIRE.ppn, _ppn_data_T_15 inst ppn_data_barrier of OptimizationBarrier_EntryData_1 connect ppn_data_barrier.clock, clock connect ppn_data_barrier.reset, reset connect ppn_data_barrier.io.x.fragmented_superpage, _ppn_data_WIRE.fragmented_superpage connect ppn_data_barrier.io.x.c, _ppn_data_WIRE.c connect ppn_data_barrier.io.x.eff, _ppn_data_WIRE.eff connect ppn_data_barrier.io.x.paa, _ppn_data_WIRE.paa connect ppn_data_barrier.io.x.pal, _ppn_data_WIRE.pal connect ppn_data_barrier.io.x.pr, _ppn_data_WIRE.pr connect ppn_data_barrier.io.x.px, _ppn_data_WIRE.px connect ppn_data_barrier.io.x.pw, _ppn_data_WIRE.pw connect ppn_data_barrier.io.x.sr, _ppn_data_WIRE.sr connect ppn_data_barrier.io.x.sx, _ppn_data_WIRE.sx connect ppn_data_barrier.io.x.sw, _ppn_data_WIRE.sw connect ppn_data_barrier.io.x.ae, _ppn_data_WIRE.ae connect ppn_data_barrier.io.x.g, _ppn_data_WIRE.g connect ppn_data_barrier.io.x.u, _ppn_data_WIRE.u connect ppn_data_barrier.io.x.ppn, _ppn_data_WIRE.ppn node _ppn_data_T_16 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_3 : UInt<34> connect _ppn_data_WIRE_3, sectored_entries[1].data[_ppn_data_T_16] node _ppn_data_T_17 = bits(_ppn_data_WIRE_3, 0, 0) connect _ppn_data_WIRE_2.fragmented_superpage, _ppn_data_T_17 node _ppn_data_T_18 = bits(_ppn_data_WIRE_3, 1, 1) connect _ppn_data_WIRE_2.c, _ppn_data_T_18 node _ppn_data_T_19 = bits(_ppn_data_WIRE_3, 2, 2) connect _ppn_data_WIRE_2.eff, _ppn_data_T_19 node _ppn_data_T_20 = bits(_ppn_data_WIRE_3, 3, 3) connect _ppn_data_WIRE_2.paa, _ppn_data_T_20 node _ppn_data_T_21 = bits(_ppn_data_WIRE_3, 4, 4) connect _ppn_data_WIRE_2.pal, _ppn_data_T_21 node _ppn_data_T_22 = bits(_ppn_data_WIRE_3, 5, 5) connect _ppn_data_WIRE_2.pr, _ppn_data_T_22 node _ppn_data_T_23 = bits(_ppn_data_WIRE_3, 6, 6) connect _ppn_data_WIRE_2.px, _ppn_data_T_23 node _ppn_data_T_24 = bits(_ppn_data_WIRE_3, 7, 7) connect _ppn_data_WIRE_2.pw, _ppn_data_T_24 node _ppn_data_T_25 = bits(_ppn_data_WIRE_3, 8, 8) connect _ppn_data_WIRE_2.sr, _ppn_data_T_25 node _ppn_data_T_26 = bits(_ppn_data_WIRE_3, 9, 9) connect _ppn_data_WIRE_2.sx, _ppn_data_T_26 node _ppn_data_T_27 = bits(_ppn_data_WIRE_3, 10, 10) connect _ppn_data_WIRE_2.sw, _ppn_data_T_27 node _ppn_data_T_28 = bits(_ppn_data_WIRE_3, 11, 11) connect _ppn_data_WIRE_2.ae, _ppn_data_T_28 node _ppn_data_T_29 = bits(_ppn_data_WIRE_3, 12, 12) connect _ppn_data_WIRE_2.g, _ppn_data_T_29 node _ppn_data_T_30 = bits(_ppn_data_WIRE_3, 13, 13) connect _ppn_data_WIRE_2.u, _ppn_data_T_30 node _ppn_data_T_31 = bits(_ppn_data_WIRE_3, 33, 14) connect _ppn_data_WIRE_2.ppn, _ppn_data_T_31 inst ppn_data_barrier_1 of OptimizationBarrier_EntryData_2 connect ppn_data_barrier_1.clock, clock connect ppn_data_barrier_1.reset, reset connect ppn_data_barrier_1.io.x.fragmented_superpage, _ppn_data_WIRE_2.fragmented_superpage connect ppn_data_barrier_1.io.x.c, _ppn_data_WIRE_2.c connect ppn_data_barrier_1.io.x.eff, _ppn_data_WIRE_2.eff connect ppn_data_barrier_1.io.x.paa, _ppn_data_WIRE_2.paa connect ppn_data_barrier_1.io.x.pal, _ppn_data_WIRE_2.pal connect ppn_data_barrier_1.io.x.pr, _ppn_data_WIRE_2.pr connect ppn_data_barrier_1.io.x.px, _ppn_data_WIRE_2.px connect ppn_data_barrier_1.io.x.pw, _ppn_data_WIRE_2.pw connect ppn_data_barrier_1.io.x.sr, _ppn_data_WIRE_2.sr connect ppn_data_barrier_1.io.x.sx, _ppn_data_WIRE_2.sx connect ppn_data_barrier_1.io.x.sw, _ppn_data_WIRE_2.sw connect ppn_data_barrier_1.io.x.ae, _ppn_data_WIRE_2.ae connect ppn_data_barrier_1.io.x.g, _ppn_data_WIRE_2.g connect ppn_data_barrier_1.io.x.u, _ppn_data_WIRE_2.u connect ppn_data_barrier_1.io.x.ppn, _ppn_data_WIRE_2.ppn node _ppn_data_T_32 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_5 : UInt<34> connect _ppn_data_WIRE_5, sectored_entries[2].data[_ppn_data_T_32] node _ppn_data_T_33 = bits(_ppn_data_WIRE_5, 0, 0) connect _ppn_data_WIRE_4.fragmented_superpage, _ppn_data_T_33 node _ppn_data_T_34 = bits(_ppn_data_WIRE_5, 1, 1) connect _ppn_data_WIRE_4.c, _ppn_data_T_34 node _ppn_data_T_35 = bits(_ppn_data_WIRE_5, 2, 2) connect _ppn_data_WIRE_4.eff, _ppn_data_T_35 node _ppn_data_T_36 = bits(_ppn_data_WIRE_5, 3, 3) connect _ppn_data_WIRE_4.paa, _ppn_data_T_36 node _ppn_data_T_37 = bits(_ppn_data_WIRE_5, 4, 4) connect _ppn_data_WIRE_4.pal, _ppn_data_T_37 node _ppn_data_T_38 = bits(_ppn_data_WIRE_5, 5, 5) connect _ppn_data_WIRE_4.pr, _ppn_data_T_38 node _ppn_data_T_39 = bits(_ppn_data_WIRE_5, 6, 6) connect _ppn_data_WIRE_4.px, _ppn_data_T_39 node _ppn_data_T_40 = bits(_ppn_data_WIRE_5, 7, 7) connect _ppn_data_WIRE_4.pw, _ppn_data_T_40 node _ppn_data_T_41 = bits(_ppn_data_WIRE_5, 8, 8) connect _ppn_data_WIRE_4.sr, _ppn_data_T_41 node _ppn_data_T_42 = bits(_ppn_data_WIRE_5, 9, 9) connect _ppn_data_WIRE_4.sx, _ppn_data_T_42 node _ppn_data_T_43 = bits(_ppn_data_WIRE_5, 10, 10) connect _ppn_data_WIRE_4.sw, _ppn_data_T_43 node _ppn_data_T_44 = bits(_ppn_data_WIRE_5, 11, 11) connect _ppn_data_WIRE_4.ae, _ppn_data_T_44 node _ppn_data_T_45 = bits(_ppn_data_WIRE_5, 12, 12) connect _ppn_data_WIRE_4.g, _ppn_data_T_45 node _ppn_data_T_46 = bits(_ppn_data_WIRE_5, 13, 13) connect _ppn_data_WIRE_4.u, _ppn_data_T_46 node _ppn_data_T_47 = bits(_ppn_data_WIRE_5, 33, 14) connect _ppn_data_WIRE_4.ppn, _ppn_data_T_47 inst ppn_data_barrier_2 of OptimizationBarrier_EntryData_3 connect ppn_data_barrier_2.clock, clock connect ppn_data_barrier_2.reset, reset connect ppn_data_barrier_2.io.x.fragmented_superpage, _ppn_data_WIRE_4.fragmented_superpage connect ppn_data_barrier_2.io.x.c, _ppn_data_WIRE_4.c connect ppn_data_barrier_2.io.x.eff, _ppn_data_WIRE_4.eff connect ppn_data_barrier_2.io.x.paa, _ppn_data_WIRE_4.paa connect ppn_data_barrier_2.io.x.pal, _ppn_data_WIRE_4.pal connect ppn_data_barrier_2.io.x.pr, _ppn_data_WIRE_4.pr connect ppn_data_barrier_2.io.x.px, _ppn_data_WIRE_4.px connect ppn_data_barrier_2.io.x.pw, _ppn_data_WIRE_4.pw connect ppn_data_barrier_2.io.x.sr, _ppn_data_WIRE_4.sr connect ppn_data_barrier_2.io.x.sx, _ppn_data_WIRE_4.sx connect ppn_data_barrier_2.io.x.sw, _ppn_data_WIRE_4.sw connect ppn_data_barrier_2.io.x.ae, _ppn_data_WIRE_4.ae connect ppn_data_barrier_2.io.x.g, _ppn_data_WIRE_4.g connect ppn_data_barrier_2.io.x.u, _ppn_data_WIRE_4.u connect ppn_data_barrier_2.io.x.ppn, _ppn_data_WIRE_4.ppn node _ppn_data_T_48 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_7 : UInt<34> connect _ppn_data_WIRE_7, sectored_entries[3].data[_ppn_data_T_48] node _ppn_data_T_49 = bits(_ppn_data_WIRE_7, 0, 0) connect _ppn_data_WIRE_6.fragmented_superpage, _ppn_data_T_49 node _ppn_data_T_50 = bits(_ppn_data_WIRE_7, 1, 1) connect _ppn_data_WIRE_6.c, _ppn_data_T_50 node _ppn_data_T_51 = bits(_ppn_data_WIRE_7, 2, 2) connect _ppn_data_WIRE_6.eff, _ppn_data_T_51 node _ppn_data_T_52 = bits(_ppn_data_WIRE_7, 3, 3) connect _ppn_data_WIRE_6.paa, _ppn_data_T_52 node _ppn_data_T_53 = bits(_ppn_data_WIRE_7, 4, 4) connect _ppn_data_WIRE_6.pal, _ppn_data_T_53 node _ppn_data_T_54 = bits(_ppn_data_WIRE_7, 5, 5) connect _ppn_data_WIRE_6.pr, _ppn_data_T_54 node _ppn_data_T_55 = bits(_ppn_data_WIRE_7, 6, 6) connect _ppn_data_WIRE_6.px, _ppn_data_T_55 node _ppn_data_T_56 = bits(_ppn_data_WIRE_7, 7, 7) connect _ppn_data_WIRE_6.pw, _ppn_data_T_56 node _ppn_data_T_57 = bits(_ppn_data_WIRE_7, 8, 8) connect _ppn_data_WIRE_6.sr, _ppn_data_T_57 node _ppn_data_T_58 = bits(_ppn_data_WIRE_7, 9, 9) connect _ppn_data_WIRE_6.sx, _ppn_data_T_58 node _ppn_data_T_59 = bits(_ppn_data_WIRE_7, 10, 10) connect _ppn_data_WIRE_6.sw, _ppn_data_T_59 node _ppn_data_T_60 = bits(_ppn_data_WIRE_7, 11, 11) connect _ppn_data_WIRE_6.ae, _ppn_data_T_60 node _ppn_data_T_61 = bits(_ppn_data_WIRE_7, 12, 12) connect _ppn_data_WIRE_6.g, _ppn_data_T_61 node _ppn_data_T_62 = bits(_ppn_data_WIRE_7, 13, 13) connect _ppn_data_WIRE_6.u, _ppn_data_T_62 node _ppn_data_T_63 = bits(_ppn_data_WIRE_7, 33, 14) connect _ppn_data_WIRE_6.ppn, _ppn_data_T_63 inst ppn_data_barrier_3 of OptimizationBarrier_EntryData_4 connect ppn_data_barrier_3.clock, clock connect ppn_data_barrier_3.reset, reset connect ppn_data_barrier_3.io.x.fragmented_superpage, _ppn_data_WIRE_6.fragmented_superpage connect ppn_data_barrier_3.io.x.c, _ppn_data_WIRE_6.c connect ppn_data_barrier_3.io.x.eff, _ppn_data_WIRE_6.eff connect ppn_data_barrier_3.io.x.paa, _ppn_data_WIRE_6.paa connect ppn_data_barrier_3.io.x.pal, _ppn_data_WIRE_6.pal connect ppn_data_barrier_3.io.x.pr, _ppn_data_WIRE_6.pr connect ppn_data_barrier_3.io.x.px, _ppn_data_WIRE_6.px connect ppn_data_barrier_3.io.x.pw, _ppn_data_WIRE_6.pw connect ppn_data_barrier_3.io.x.sr, _ppn_data_WIRE_6.sr connect ppn_data_barrier_3.io.x.sx, _ppn_data_WIRE_6.sx connect ppn_data_barrier_3.io.x.sw, _ppn_data_WIRE_6.sw connect ppn_data_barrier_3.io.x.ae, _ppn_data_WIRE_6.ae connect ppn_data_barrier_3.io.x.g, _ppn_data_WIRE_6.g connect ppn_data_barrier_3.io.x.u, _ppn_data_WIRE_6.u connect ppn_data_barrier_3.io.x.ppn, _ppn_data_WIRE_6.ppn node _ppn_data_T_64 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_9 : UInt<34> connect _ppn_data_WIRE_9, sectored_entries[4].data[_ppn_data_T_64] node _ppn_data_T_65 = bits(_ppn_data_WIRE_9, 0, 0) connect _ppn_data_WIRE_8.fragmented_superpage, _ppn_data_T_65 node _ppn_data_T_66 = bits(_ppn_data_WIRE_9, 1, 1) connect _ppn_data_WIRE_8.c, _ppn_data_T_66 node _ppn_data_T_67 = bits(_ppn_data_WIRE_9, 2, 2) connect _ppn_data_WIRE_8.eff, _ppn_data_T_67 node _ppn_data_T_68 = bits(_ppn_data_WIRE_9, 3, 3) connect _ppn_data_WIRE_8.paa, _ppn_data_T_68 node _ppn_data_T_69 = bits(_ppn_data_WIRE_9, 4, 4) connect _ppn_data_WIRE_8.pal, _ppn_data_T_69 node _ppn_data_T_70 = bits(_ppn_data_WIRE_9, 5, 5) connect _ppn_data_WIRE_8.pr, _ppn_data_T_70 node _ppn_data_T_71 = bits(_ppn_data_WIRE_9, 6, 6) connect _ppn_data_WIRE_8.px, _ppn_data_T_71 node _ppn_data_T_72 = bits(_ppn_data_WIRE_9, 7, 7) connect _ppn_data_WIRE_8.pw, _ppn_data_T_72 node _ppn_data_T_73 = bits(_ppn_data_WIRE_9, 8, 8) connect _ppn_data_WIRE_8.sr, _ppn_data_T_73 node _ppn_data_T_74 = bits(_ppn_data_WIRE_9, 9, 9) connect _ppn_data_WIRE_8.sx, _ppn_data_T_74 node _ppn_data_T_75 = bits(_ppn_data_WIRE_9, 10, 10) connect _ppn_data_WIRE_8.sw, _ppn_data_T_75 node _ppn_data_T_76 = bits(_ppn_data_WIRE_9, 11, 11) connect _ppn_data_WIRE_8.ae, _ppn_data_T_76 node _ppn_data_T_77 = bits(_ppn_data_WIRE_9, 12, 12) connect _ppn_data_WIRE_8.g, _ppn_data_T_77 node _ppn_data_T_78 = bits(_ppn_data_WIRE_9, 13, 13) connect _ppn_data_WIRE_8.u, _ppn_data_T_78 node _ppn_data_T_79 = bits(_ppn_data_WIRE_9, 33, 14) connect _ppn_data_WIRE_8.ppn, _ppn_data_T_79 inst ppn_data_barrier_4 of OptimizationBarrier_EntryData_5 connect ppn_data_barrier_4.clock, clock connect ppn_data_barrier_4.reset, reset connect ppn_data_barrier_4.io.x.fragmented_superpage, _ppn_data_WIRE_8.fragmented_superpage connect ppn_data_barrier_4.io.x.c, _ppn_data_WIRE_8.c connect ppn_data_barrier_4.io.x.eff, _ppn_data_WIRE_8.eff connect ppn_data_barrier_4.io.x.paa, _ppn_data_WIRE_8.paa connect ppn_data_barrier_4.io.x.pal, _ppn_data_WIRE_8.pal connect ppn_data_barrier_4.io.x.pr, _ppn_data_WIRE_8.pr connect ppn_data_barrier_4.io.x.px, _ppn_data_WIRE_8.px connect ppn_data_barrier_4.io.x.pw, _ppn_data_WIRE_8.pw connect ppn_data_barrier_4.io.x.sr, _ppn_data_WIRE_8.sr connect ppn_data_barrier_4.io.x.sx, _ppn_data_WIRE_8.sx connect ppn_data_barrier_4.io.x.sw, _ppn_data_WIRE_8.sw connect ppn_data_barrier_4.io.x.ae, _ppn_data_WIRE_8.ae connect ppn_data_barrier_4.io.x.g, _ppn_data_WIRE_8.g connect ppn_data_barrier_4.io.x.u, _ppn_data_WIRE_8.u connect ppn_data_barrier_4.io.x.ppn, _ppn_data_WIRE_8.ppn node _ppn_data_T_80 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_11 : UInt<34> connect _ppn_data_WIRE_11, sectored_entries[5].data[_ppn_data_T_80] node _ppn_data_T_81 = bits(_ppn_data_WIRE_11, 0, 0) connect _ppn_data_WIRE_10.fragmented_superpage, _ppn_data_T_81 node _ppn_data_T_82 = bits(_ppn_data_WIRE_11, 1, 1) connect _ppn_data_WIRE_10.c, _ppn_data_T_82 node _ppn_data_T_83 = bits(_ppn_data_WIRE_11, 2, 2) connect _ppn_data_WIRE_10.eff, _ppn_data_T_83 node _ppn_data_T_84 = bits(_ppn_data_WIRE_11, 3, 3) connect _ppn_data_WIRE_10.paa, _ppn_data_T_84 node _ppn_data_T_85 = bits(_ppn_data_WIRE_11, 4, 4) connect _ppn_data_WIRE_10.pal, _ppn_data_T_85 node _ppn_data_T_86 = bits(_ppn_data_WIRE_11, 5, 5) connect _ppn_data_WIRE_10.pr, _ppn_data_T_86 node _ppn_data_T_87 = bits(_ppn_data_WIRE_11, 6, 6) connect _ppn_data_WIRE_10.px, _ppn_data_T_87 node _ppn_data_T_88 = bits(_ppn_data_WIRE_11, 7, 7) connect _ppn_data_WIRE_10.pw, _ppn_data_T_88 node _ppn_data_T_89 = bits(_ppn_data_WIRE_11, 8, 8) connect _ppn_data_WIRE_10.sr, _ppn_data_T_89 node _ppn_data_T_90 = bits(_ppn_data_WIRE_11, 9, 9) connect _ppn_data_WIRE_10.sx, _ppn_data_T_90 node _ppn_data_T_91 = bits(_ppn_data_WIRE_11, 10, 10) connect _ppn_data_WIRE_10.sw, _ppn_data_T_91 node _ppn_data_T_92 = bits(_ppn_data_WIRE_11, 11, 11) connect _ppn_data_WIRE_10.ae, _ppn_data_T_92 node _ppn_data_T_93 = bits(_ppn_data_WIRE_11, 12, 12) connect _ppn_data_WIRE_10.g, _ppn_data_T_93 node _ppn_data_T_94 = bits(_ppn_data_WIRE_11, 13, 13) connect _ppn_data_WIRE_10.u, _ppn_data_T_94 node _ppn_data_T_95 = bits(_ppn_data_WIRE_11, 33, 14) connect _ppn_data_WIRE_10.ppn, _ppn_data_T_95 inst ppn_data_barrier_5 of OptimizationBarrier_EntryData_6 connect ppn_data_barrier_5.clock, clock connect ppn_data_barrier_5.reset, reset connect ppn_data_barrier_5.io.x.fragmented_superpage, _ppn_data_WIRE_10.fragmented_superpage connect ppn_data_barrier_5.io.x.c, _ppn_data_WIRE_10.c connect ppn_data_barrier_5.io.x.eff, _ppn_data_WIRE_10.eff connect ppn_data_barrier_5.io.x.paa, _ppn_data_WIRE_10.paa connect ppn_data_barrier_5.io.x.pal, _ppn_data_WIRE_10.pal connect ppn_data_barrier_5.io.x.pr, _ppn_data_WIRE_10.pr connect ppn_data_barrier_5.io.x.px, _ppn_data_WIRE_10.px connect ppn_data_barrier_5.io.x.pw, _ppn_data_WIRE_10.pw connect ppn_data_barrier_5.io.x.sr, _ppn_data_WIRE_10.sr connect ppn_data_barrier_5.io.x.sx, _ppn_data_WIRE_10.sx connect ppn_data_barrier_5.io.x.sw, _ppn_data_WIRE_10.sw connect ppn_data_barrier_5.io.x.ae, _ppn_data_WIRE_10.ae connect ppn_data_barrier_5.io.x.g, _ppn_data_WIRE_10.g connect ppn_data_barrier_5.io.x.u, _ppn_data_WIRE_10.u connect ppn_data_barrier_5.io.x.ppn, _ppn_data_WIRE_10.ppn node _ppn_data_T_96 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_13 : UInt<34> connect _ppn_data_WIRE_13, sectored_entries[6].data[_ppn_data_T_96] node _ppn_data_T_97 = bits(_ppn_data_WIRE_13, 0, 0) connect _ppn_data_WIRE_12.fragmented_superpage, _ppn_data_T_97 node _ppn_data_T_98 = bits(_ppn_data_WIRE_13, 1, 1) connect _ppn_data_WIRE_12.c, _ppn_data_T_98 node _ppn_data_T_99 = bits(_ppn_data_WIRE_13, 2, 2) connect _ppn_data_WIRE_12.eff, _ppn_data_T_99 node _ppn_data_T_100 = bits(_ppn_data_WIRE_13, 3, 3) connect _ppn_data_WIRE_12.paa, _ppn_data_T_100 node _ppn_data_T_101 = bits(_ppn_data_WIRE_13, 4, 4) connect _ppn_data_WIRE_12.pal, _ppn_data_T_101 node _ppn_data_T_102 = bits(_ppn_data_WIRE_13, 5, 5) connect _ppn_data_WIRE_12.pr, _ppn_data_T_102 node _ppn_data_T_103 = bits(_ppn_data_WIRE_13, 6, 6) connect _ppn_data_WIRE_12.px, _ppn_data_T_103 node _ppn_data_T_104 = bits(_ppn_data_WIRE_13, 7, 7) connect _ppn_data_WIRE_12.pw, _ppn_data_T_104 node _ppn_data_T_105 = bits(_ppn_data_WIRE_13, 8, 8) connect _ppn_data_WIRE_12.sr, _ppn_data_T_105 node _ppn_data_T_106 = bits(_ppn_data_WIRE_13, 9, 9) connect _ppn_data_WIRE_12.sx, _ppn_data_T_106 node _ppn_data_T_107 = bits(_ppn_data_WIRE_13, 10, 10) connect _ppn_data_WIRE_12.sw, _ppn_data_T_107 node _ppn_data_T_108 = bits(_ppn_data_WIRE_13, 11, 11) connect _ppn_data_WIRE_12.ae, _ppn_data_T_108 node _ppn_data_T_109 = bits(_ppn_data_WIRE_13, 12, 12) connect _ppn_data_WIRE_12.g, _ppn_data_T_109 node _ppn_data_T_110 = bits(_ppn_data_WIRE_13, 13, 13) connect _ppn_data_WIRE_12.u, _ppn_data_T_110 node _ppn_data_T_111 = bits(_ppn_data_WIRE_13, 33, 14) connect _ppn_data_WIRE_12.ppn, _ppn_data_T_111 inst ppn_data_barrier_6 of OptimizationBarrier_EntryData_7 connect ppn_data_barrier_6.clock, clock connect ppn_data_barrier_6.reset, reset connect ppn_data_barrier_6.io.x.fragmented_superpage, _ppn_data_WIRE_12.fragmented_superpage connect ppn_data_barrier_6.io.x.c, _ppn_data_WIRE_12.c connect ppn_data_barrier_6.io.x.eff, _ppn_data_WIRE_12.eff connect ppn_data_barrier_6.io.x.paa, _ppn_data_WIRE_12.paa connect ppn_data_barrier_6.io.x.pal, _ppn_data_WIRE_12.pal connect ppn_data_barrier_6.io.x.pr, _ppn_data_WIRE_12.pr connect ppn_data_barrier_6.io.x.px, _ppn_data_WIRE_12.px connect ppn_data_barrier_6.io.x.pw, _ppn_data_WIRE_12.pw connect ppn_data_barrier_6.io.x.sr, _ppn_data_WIRE_12.sr connect ppn_data_barrier_6.io.x.sx, _ppn_data_WIRE_12.sx connect ppn_data_barrier_6.io.x.sw, _ppn_data_WIRE_12.sw connect ppn_data_barrier_6.io.x.ae, _ppn_data_WIRE_12.ae connect ppn_data_barrier_6.io.x.g, _ppn_data_WIRE_12.g connect ppn_data_barrier_6.io.x.u, _ppn_data_WIRE_12.u connect ppn_data_barrier_6.io.x.ppn, _ppn_data_WIRE_12.ppn node _ppn_data_T_112 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_15 : UInt<34> connect _ppn_data_WIRE_15, sectored_entries[7].data[_ppn_data_T_112] node _ppn_data_T_113 = bits(_ppn_data_WIRE_15, 0, 0) connect _ppn_data_WIRE_14.fragmented_superpage, _ppn_data_T_113 node _ppn_data_T_114 = bits(_ppn_data_WIRE_15, 1, 1) connect _ppn_data_WIRE_14.c, _ppn_data_T_114 node _ppn_data_T_115 = bits(_ppn_data_WIRE_15, 2, 2) connect _ppn_data_WIRE_14.eff, _ppn_data_T_115 node _ppn_data_T_116 = bits(_ppn_data_WIRE_15, 3, 3) connect _ppn_data_WIRE_14.paa, _ppn_data_T_116 node _ppn_data_T_117 = bits(_ppn_data_WIRE_15, 4, 4) connect _ppn_data_WIRE_14.pal, _ppn_data_T_117 node _ppn_data_T_118 = bits(_ppn_data_WIRE_15, 5, 5) connect _ppn_data_WIRE_14.pr, _ppn_data_T_118 node _ppn_data_T_119 = bits(_ppn_data_WIRE_15, 6, 6) connect _ppn_data_WIRE_14.px, _ppn_data_T_119 node _ppn_data_T_120 = bits(_ppn_data_WIRE_15, 7, 7) connect _ppn_data_WIRE_14.pw, _ppn_data_T_120 node _ppn_data_T_121 = bits(_ppn_data_WIRE_15, 8, 8) connect _ppn_data_WIRE_14.sr, _ppn_data_T_121 node _ppn_data_T_122 = bits(_ppn_data_WIRE_15, 9, 9) connect _ppn_data_WIRE_14.sx, _ppn_data_T_122 node _ppn_data_T_123 = bits(_ppn_data_WIRE_15, 10, 10) connect _ppn_data_WIRE_14.sw, _ppn_data_T_123 node _ppn_data_T_124 = bits(_ppn_data_WIRE_15, 11, 11) connect _ppn_data_WIRE_14.ae, _ppn_data_T_124 node _ppn_data_T_125 = bits(_ppn_data_WIRE_15, 12, 12) connect _ppn_data_WIRE_14.g, _ppn_data_T_125 node _ppn_data_T_126 = bits(_ppn_data_WIRE_15, 13, 13) connect _ppn_data_WIRE_14.u, _ppn_data_T_126 node _ppn_data_T_127 = bits(_ppn_data_WIRE_15, 33, 14) connect _ppn_data_WIRE_14.ppn, _ppn_data_T_127 inst ppn_data_barrier_7 of OptimizationBarrier_EntryData_8 connect ppn_data_barrier_7.clock, clock connect ppn_data_barrier_7.reset, reset connect ppn_data_barrier_7.io.x.fragmented_superpage, _ppn_data_WIRE_14.fragmented_superpage connect ppn_data_barrier_7.io.x.c, _ppn_data_WIRE_14.c connect ppn_data_barrier_7.io.x.eff, _ppn_data_WIRE_14.eff connect ppn_data_barrier_7.io.x.paa, _ppn_data_WIRE_14.paa connect ppn_data_barrier_7.io.x.pal, _ppn_data_WIRE_14.pal connect ppn_data_barrier_7.io.x.pr, _ppn_data_WIRE_14.pr connect ppn_data_barrier_7.io.x.px, _ppn_data_WIRE_14.px connect ppn_data_barrier_7.io.x.pw, _ppn_data_WIRE_14.pw connect ppn_data_barrier_7.io.x.sr, _ppn_data_WIRE_14.sr connect ppn_data_barrier_7.io.x.sx, _ppn_data_WIRE_14.sx connect ppn_data_barrier_7.io.x.sw, _ppn_data_WIRE_14.sw connect ppn_data_barrier_7.io.x.ae, _ppn_data_WIRE_14.ae connect ppn_data_barrier_7.io.x.g, _ppn_data_WIRE_14.g connect ppn_data_barrier_7.io.x.u, _ppn_data_WIRE_14.u connect ppn_data_barrier_7.io.x.ppn, _ppn_data_WIRE_14.ppn wire _ppn_data_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_17 : UInt<34> connect _ppn_data_WIRE_17, superpage_entries[0].data[0] node _ppn_data_T_128 = bits(_ppn_data_WIRE_17, 0, 0) connect _ppn_data_WIRE_16.fragmented_superpage, _ppn_data_T_128 node _ppn_data_T_129 = bits(_ppn_data_WIRE_17, 1, 1) connect _ppn_data_WIRE_16.c, _ppn_data_T_129 node _ppn_data_T_130 = bits(_ppn_data_WIRE_17, 2, 2) connect _ppn_data_WIRE_16.eff, _ppn_data_T_130 node _ppn_data_T_131 = bits(_ppn_data_WIRE_17, 3, 3) connect _ppn_data_WIRE_16.paa, _ppn_data_T_131 node _ppn_data_T_132 = bits(_ppn_data_WIRE_17, 4, 4) connect _ppn_data_WIRE_16.pal, _ppn_data_T_132 node _ppn_data_T_133 = bits(_ppn_data_WIRE_17, 5, 5) connect _ppn_data_WIRE_16.pr, _ppn_data_T_133 node _ppn_data_T_134 = bits(_ppn_data_WIRE_17, 6, 6) connect _ppn_data_WIRE_16.px, _ppn_data_T_134 node _ppn_data_T_135 = bits(_ppn_data_WIRE_17, 7, 7) connect _ppn_data_WIRE_16.pw, _ppn_data_T_135 node _ppn_data_T_136 = bits(_ppn_data_WIRE_17, 8, 8) connect _ppn_data_WIRE_16.sr, _ppn_data_T_136 node _ppn_data_T_137 = bits(_ppn_data_WIRE_17, 9, 9) connect _ppn_data_WIRE_16.sx, _ppn_data_T_137 node _ppn_data_T_138 = bits(_ppn_data_WIRE_17, 10, 10) connect _ppn_data_WIRE_16.sw, _ppn_data_T_138 node _ppn_data_T_139 = bits(_ppn_data_WIRE_17, 11, 11) connect _ppn_data_WIRE_16.ae, _ppn_data_T_139 node _ppn_data_T_140 = bits(_ppn_data_WIRE_17, 12, 12) connect _ppn_data_WIRE_16.g, _ppn_data_T_140 node _ppn_data_T_141 = bits(_ppn_data_WIRE_17, 13, 13) connect _ppn_data_WIRE_16.u, _ppn_data_T_141 node _ppn_data_T_142 = bits(_ppn_data_WIRE_17, 33, 14) connect _ppn_data_WIRE_16.ppn, _ppn_data_T_142 inst ppn_data_barrier_8 of OptimizationBarrier_EntryData_9 connect ppn_data_barrier_8.clock, clock connect ppn_data_barrier_8.reset, reset connect ppn_data_barrier_8.io.x.fragmented_superpage, _ppn_data_WIRE_16.fragmented_superpage connect ppn_data_barrier_8.io.x.c, _ppn_data_WIRE_16.c connect ppn_data_barrier_8.io.x.eff, _ppn_data_WIRE_16.eff connect ppn_data_barrier_8.io.x.paa, _ppn_data_WIRE_16.paa connect ppn_data_barrier_8.io.x.pal, _ppn_data_WIRE_16.pal connect ppn_data_barrier_8.io.x.pr, _ppn_data_WIRE_16.pr connect ppn_data_barrier_8.io.x.px, _ppn_data_WIRE_16.px connect ppn_data_barrier_8.io.x.pw, _ppn_data_WIRE_16.pw connect ppn_data_barrier_8.io.x.sr, _ppn_data_WIRE_16.sr connect ppn_data_barrier_8.io.x.sx, _ppn_data_WIRE_16.sx connect ppn_data_barrier_8.io.x.sw, _ppn_data_WIRE_16.sw connect ppn_data_barrier_8.io.x.ae, _ppn_data_WIRE_16.ae connect ppn_data_barrier_8.io.x.g, _ppn_data_WIRE_16.g connect ppn_data_barrier_8.io.x.u, _ppn_data_WIRE_16.u connect ppn_data_barrier_8.io.x.ppn, _ppn_data_WIRE_16.ppn wire _ppn_data_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_19 : UInt<34> connect _ppn_data_WIRE_19, superpage_entries[1].data[0] node _ppn_data_T_143 = bits(_ppn_data_WIRE_19, 0, 0) connect _ppn_data_WIRE_18.fragmented_superpage, _ppn_data_T_143 node _ppn_data_T_144 = bits(_ppn_data_WIRE_19, 1, 1) connect _ppn_data_WIRE_18.c, _ppn_data_T_144 node _ppn_data_T_145 = bits(_ppn_data_WIRE_19, 2, 2) connect _ppn_data_WIRE_18.eff, _ppn_data_T_145 node _ppn_data_T_146 = bits(_ppn_data_WIRE_19, 3, 3) connect _ppn_data_WIRE_18.paa, _ppn_data_T_146 node _ppn_data_T_147 = bits(_ppn_data_WIRE_19, 4, 4) connect _ppn_data_WIRE_18.pal, _ppn_data_T_147 node _ppn_data_T_148 = bits(_ppn_data_WIRE_19, 5, 5) connect _ppn_data_WIRE_18.pr, _ppn_data_T_148 node _ppn_data_T_149 = bits(_ppn_data_WIRE_19, 6, 6) connect _ppn_data_WIRE_18.px, _ppn_data_T_149 node _ppn_data_T_150 = bits(_ppn_data_WIRE_19, 7, 7) connect _ppn_data_WIRE_18.pw, _ppn_data_T_150 node _ppn_data_T_151 = bits(_ppn_data_WIRE_19, 8, 8) connect _ppn_data_WIRE_18.sr, _ppn_data_T_151 node _ppn_data_T_152 = bits(_ppn_data_WIRE_19, 9, 9) connect _ppn_data_WIRE_18.sx, _ppn_data_T_152 node _ppn_data_T_153 = bits(_ppn_data_WIRE_19, 10, 10) connect _ppn_data_WIRE_18.sw, _ppn_data_T_153 node _ppn_data_T_154 = bits(_ppn_data_WIRE_19, 11, 11) connect _ppn_data_WIRE_18.ae, _ppn_data_T_154 node _ppn_data_T_155 = bits(_ppn_data_WIRE_19, 12, 12) connect _ppn_data_WIRE_18.g, _ppn_data_T_155 node _ppn_data_T_156 = bits(_ppn_data_WIRE_19, 13, 13) connect _ppn_data_WIRE_18.u, _ppn_data_T_156 node _ppn_data_T_157 = bits(_ppn_data_WIRE_19, 33, 14) connect _ppn_data_WIRE_18.ppn, _ppn_data_T_157 inst ppn_data_barrier_9 of OptimizationBarrier_EntryData_10 connect ppn_data_barrier_9.clock, clock connect ppn_data_barrier_9.reset, reset connect ppn_data_barrier_9.io.x.fragmented_superpage, _ppn_data_WIRE_18.fragmented_superpage connect ppn_data_barrier_9.io.x.c, _ppn_data_WIRE_18.c connect ppn_data_barrier_9.io.x.eff, _ppn_data_WIRE_18.eff connect ppn_data_barrier_9.io.x.paa, _ppn_data_WIRE_18.paa connect ppn_data_barrier_9.io.x.pal, _ppn_data_WIRE_18.pal connect ppn_data_barrier_9.io.x.pr, _ppn_data_WIRE_18.pr connect ppn_data_barrier_9.io.x.px, _ppn_data_WIRE_18.px connect ppn_data_barrier_9.io.x.pw, _ppn_data_WIRE_18.pw connect ppn_data_barrier_9.io.x.sr, _ppn_data_WIRE_18.sr connect ppn_data_barrier_9.io.x.sx, _ppn_data_WIRE_18.sx connect ppn_data_barrier_9.io.x.sw, _ppn_data_WIRE_18.sw connect ppn_data_barrier_9.io.x.ae, _ppn_data_WIRE_18.ae connect ppn_data_barrier_9.io.x.g, _ppn_data_WIRE_18.g connect ppn_data_barrier_9.io.x.u, _ppn_data_WIRE_18.u connect ppn_data_barrier_9.io.x.ppn, _ppn_data_WIRE_18.ppn wire _ppn_data_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_21 : UInt<34> connect _ppn_data_WIRE_21, superpage_entries[2].data[0] node _ppn_data_T_158 = bits(_ppn_data_WIRE_21, 0, 0) connect _ppn_data_WIRE_20.fragmented_superpage, _ppn_data_T_158 node _ppn_data_T_159 = bits(_ppn_data_WIRE_21, 1, 1) connect _ppn_data_WIRE_20.c, _ppn_data_T_159 node _ppn_data_T_160 = bits(_ppn_data_WIRE_21, 2, 2) connect _ppn_data_WIRE_20.eff, _ppn_data_T_160 node _ppn_data_T_161 = bits(_ppn_data_WIRE_21, 3, 3) connect _ppn_data_WIRE_20.paa, _ppn_data_T_161 node _ppn_data_T_162 = bits(_ppn_data_WIRE_21, 4, 4) connect _ppn_data_WIRE_20.pal, _ppn_data_T_162 node _ppn_data_T_163 = bits(_ppn_data_WIRE_21, 5, 5) connect _ppn_data_WIRE_20.pr, _ppn_data_T_163 node _ppn_data_T_164 = bits(_ppn_data_WIRE_21, 6, 6) connect _ppn_data_WIRE_20.px, _ppn_data_T_164 node _ppn_data_T_165 = bits(_ppn_data_WIRE_21, 7, 7) connect _ppn_data_WIRE_20.pw, _ppn_data_T_165 node _ppn_data_T_166 = bits(_ppn_data_WIRE_21, 8, 8) connect _ppn_data_WIRE_20.sr, _ppn_data_T_166 node _ppn_data_T_167 = bits(_ppn_data_WIRE_21, 9, 9) connect _ppn_data_WIRE_20.sx, _ppn_data_T_167 node _ppn_data_T_168 = bits(_ppn_data_WIRE_21, 10, 10) connect _ppn_data_WIRE_20.sw, _ppn_data_T_168 node _ppn_data_T_169 = bits(_ppn_data_WIRE_21, 11, 11) connect _ppn_data_WIRE_20.ae, _ppn_data_T_169 node _ppn_data_T_170 = bits(_ppn_data_WIRE_21, 12, 12) connect _ppn_data_WIRE_20.g, _ppn_data_T_170 node _ppn_data_T_171 = bits(_ppn_data_WIRE_21, 13, 13) connect _ppn_data_WIRE_20.u, _ppn_data_T_171 node _ppn_data_T_172 = bits(_ppn_data_WIRE_21, 33, 14) connect _ppn_data_WIRE_20.ppn, _ppn_data_T_172 inst ppn_data_barrier_10 of OptimizationBarrier_EntryData_11 connect ppn_data_barrier_10.clock, clock connect ppn_data_barrier_10.reset, reset connect ppn_data_barrier_10.io.x.fragmented_superpage, _ppn_data_WIRE_20.fragmented_superpage connect ppn_data_barrier_10.io.x.c, _ppn_data_WIRE_20.c connect ppn_data_barrier_10.io.x.eff, _ppn_data_WIRE_20.eff connect ppn_data_barrier_10.io.x.paa, _ppn_data_WIRE_20.paa connect ppn_data_barrier_10.io.x.pal, _ppn_data_WIRE_20.pal connect ppn_data_barrier_10.io.x.pr, _ppn_data_WIRE_20.pr connect ppn_data_barrier_10.io.x.px, _ppn_data_WIRE_20.px connect ppn_data_barrier_10.io.x.pw, _ppn_data_WIRE_20.pw connect ppn_data_barrier_10.io.x.sr, _ppn_data_WIRE_20.sr connect ppn_data_barrier_10.io.x.sx, _ppn_data_WIRE_20.sx connect ppn_data_barrier_10.io.x.sw, _ppn_data_WIRE_20.sw connect ppn_data_barrier_10.io.x.ae, _ppn_data_WIRE_20.ae connect ppn_data_barrier_10.io.x.g, _ppn_data_WIRE_20.g connect ppn_data_barrier_10.io.x.u, _ppn_data_WIRE_20.u connect ppn_data_barrier_10.io.x.ppn, _ppn_data_WIRE_20.ppn wire _ppn_data_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_23 : UInt<34> connect _ppn_data_WIRE_23, superpage_entries[3].data[0] node _ppn_data_T_173 = bits(_ppn_data_WIRE_23, 0, 0) connect _ppn_data_WIRE_22.fragmented_superpage, _ppn_data_T_173 node _ppn_data_T_174 = bits(_ppn_data_WIRE_23, 1, 1) connect _ppn_data_WIRE_22.c, _ppn_data_T_174 node _ppn_data_T_175 = bits(_ppn_data_WIRE_23, 2, 2) connect _ppn_data_WIRE_22.eff, _ppn_data_T_175 node _ppn_data_T_176 = bits(_ppn_data_WIRE_23, 3, 3) connect _ppn_data_WIRE_22.paa, _ppn_data_T_176 node _ppn_data_T_177 = bits(_ppn_data_WIRE_23, 4, 4) connect _ppn_data_WIRE_22.pal, _ppn_data_T_177 node _ppn_data_T_178 = bits(_ppn_data_WIRE_23, 5, 5) connect _ppn_data_WIRE_22.pr, _ppn_data_T_178 node _ppn_data_T_179 = bits(_ppn_data_WIRE_23, 6, 6) connect _ppn_data_WIRE_22.px, _ppn_data_T_179 node _ppn_data_T_180 = bits(_ppn_data_WIRE_23, 7, 7) connect _ppn_data_WIRE_22.pw, _ppn_data_T_180 node _ppn_data_T_181 = bits(_ppn_data_WIRE_23, 8, 8) connect _ppn_data_WIRE_22.sr, _ppn_data_T_181 node _ppn_data_T_182 = bits(_ppn_data_WIRE_23, 9, 9) connect _ppn_data_WIRE_22.sx, _ppn_data_T_182 node _ppn_data_T_183 = bits(_ppn_data_WIRE_23, 10, 10) connect _ppn_data_WIRE_22.sw, _ppn_data_T_183 node _ppn_data_T_184 = bits(_ppn_data_WIRE_23, 11, 11) connect _ppn_data_WIRE_22.ae, _ppn_data_T_184 node _ppn_data_T_185 = bits(_ppn_data_WIRE_23, 12, 12) connect _ppn_data_WIRE_22.g, _ppn_data_T_185 node _ppn_data_T_186 = bits(_ppn_data_WIRE_23, 13, 13) connect _ppn_data_WIRE_22.u, _ppn_data_T_186 node _ppn_data_T_187 = bits(_ppn_data_WIRE_23, 33, 14) connect _ppn_data_WIRE_22.ppn, _ppn_data_T_187 inst ppn_data_barrier_11 of OptimizationBarrier_EntryData_12 connect ppn_data_barrier_11.clock, clock connect ppn_data_barrier_11.reset, reset connect ppn_data_barrier_11.io.x.fragmented_superpage, _ppn_data_WIRE_22.fragmented_superpage connect ppn_data_barrier_11.io.x.c, _ppn_data_WIRE_22.c connect ppn_data_barrier_11.io.x.eff, _ppn_data_WIRE_22.eff connect ppn_data_barrier_11.io.x.paa, _ppn_data_WIRE_22.paa connect ppn_data_barrier_11.io.x.pal, _ppn_data_WIRE_22.pal connect ppn_data_barrier_11.io.x.pr, _ppn_data_WIRE_22.pr connect ppn_data_barrier_11.io.x.px, _ppn_data_WIRE_22.px connect ppn_data_barrier_11.io.x.pw, _ppn_data_WIRE_22.pw connect ppn_data_barrier_11.io.x.sr, _ppn_data_WIRE_22.sr connect ppn_data_barrier_11.io.x.sx, _ppn_data_WIRE_22.sx connect ppn_data_barrier_11.io.x.sw, _ppn_data_WIRE_22.sw connect ppn_data_barrier_11.io.x.ae, _ppn_data_WIRE_22.ae connect ppn_data_barrier_11.io.x.g, _ppn_data_WIRE_22.g connect ppn_data_barrier_11.io.x.u, _ppn_data_WIRE_22.u connect ppn_data_barrier_11.io.x.ppn, _ppn_data_WIRE_22.ppn wire _ppn_data_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_25 : UInt<34> connect _ppn_data_WIRE_25, special_entry.data[0] node _ppn_data_T_188 = bits(_ppn_data_WIRE_25, 0, 0) connect _ppn_data_WIRE_24.fragmented_superpage, _ppn_data_T_188 node _ppn_data_T_189 = bits(_ppn_data_WIRE_25, 1, 1) connect _ppn_data_WIRE_24.c, _ppn_data_T_189 node _ppn_data_T_190 = bits(_ppn_data_WIRE_25, 2, 2) connect _ppn_data_WIRE_24.eff, _ppn_data_T_190 node _ppn_data_T_191 = bits(_ppn_data_WIRE_25, 3, 3) connect _ppn_data_WIRE_24.paa, _ppn_data_T_191 node _ppn_data_T_192 = bits(_ppn_data_WIRE_25, 4, 4) connect _ppn_data_WIRE_24.pal, _ppn_data_T_192 node _ppn_data_T_193 = bits(_ppn_data_WIRE_25, 5, 5) connect _ppn_data_WIRE_24.pr, _ppn_data_T_193 node _ppn_data_T_194 = bits(_ppn_data_WIRE_25, 6, 6) connect _ppn_data_WIRE_24.px, _ppn_data_T_194 node _ppn_data_T_195 = bits(_ppn_data_WIRE_25, 7, 7) connect _ppn_data_WIRE_24.pw, _ppn_data_T_195 node _ppn_data_T_196 = bits(_ppn_data_WIRE_25, 8, 8) connect _ppn_data_WIRE_24.sr, _ppn_data_T_196 node _ppn_data_T_197 = bits(_ppn_data_WIRE_25, 9, 9) connect _ppn_data_WIRE_24.sx, _ppn_data_T_197 node _ppn_data_T_198 = bits(_ppn_data_WIRE_25, 10, 10) connect _ppn_data_WIRE_24.sw, _ppn_data_T_198 node _ppn_data_T_199 = bits(_ppn_data_WIRE_25, 11, 11) connect _ppn_data_WIRE_24.ae, _ppn_data_T_199 node _ppn_data_T_200 = bits(_ppn_data_WIRE_25, 12, 12) connect _ppn_data_WIRE_24.g, _ppn_data_T_200 node _ppn_data_T_201 = bits(_ppn_data_WIRE_25, 13, 13) connect _ppn_data_WIRE_24.u, _ppn_data_T_201 node _ppn_data_T_202 = bits(_ppn_data_WIRE_25, 33, 14) connect _ppn_data_WIRE_24.ppn, _ppn_data_T_202 inst ppn_data_barrier_12 of OptimizationBarrier_EntryData_13 connect ppn_data_barrier_12.clock, clock connect ppn_data_barrier_12.reset, reset connect ppn_data_barrier_12.io.x.fragmented_superpage, _ppn_data_WIRE_24.fragmented_superpage connect ppn_data_barrier_12.io.x.c, _ppn_data_WIRE_24.c connect ppn_data_barrier_12.io.x.eff, _ppn_data_WIRE_24.eff connect ppn_data_barrier_12.io.x.paa, _ppn_data_WIRE_24.paa connect ppn_data_barrier_12.io.x.pal, _ppn_data_WIRE_24.pal connect ppn_data_barrier_12.io.x.pr, _ppn_data_WIRE_24.pr connect ppn_data_barrier_12.io.x.px, _ppn_data_WIRE_24.px connect ppn_data_barrier_12.io.x.pw, _ppn_data_WIRE_24.pw connect ppn_data_barrier_12.io.x.sr, _ppn_data_WIRE_24.sr connect ppn_data_barrier_12.io.x.sx, _ppn_data_WIRE_24.sx connect ppn_data_barrier_12.io.x.sw, _ppn_data_WIRE_24.sw connect ppn_data_barrier_12.io.x.ae, _ppn_data_WIRE_24.ae connect ppn_data_barrier_12.io.x.g, _ppn_data_WIRE_24.g connect ppn_data_barrier_12.io.x.u, _ppn_data_WIRE_24.u connect ppn_data_barrier_12.io.x.ppn, _ppn_data_WIRE_24.ppn node _ppn_T_1 = bits(vpn[0], 19, 0) node _ppn_T_2 = mux(hitsVec[0][0], ppn_data_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_3 = mux(hitsVec[0][1], ppn_data_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_4 = mux(hitsVec[0][2], ppn_data_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_5 = mux(hitsVec[0][3], ppn_data_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_6 = mux(hitsVec[0][4], ppn_data_barrier_4.io.y.ppn, UInt<1>(0h0)) node _ppn_T_7 = mux(hitsVec[0][5], ppn_data_barrier_5.io.y.ppn, UInt<1>(0h0)) node _ppn_T_8 = mux(hitsVec[0][6], ppn_data_barrier_6.io.y.ppn, UInt<1>(0h0)) node _ppn_T_9 = mux(hitsVec[0][7], ppn_data_barrier_7.io.y.ppn, UInt<1>(0h0)) node _ppn_T_10 = mux(hitsVec[0][8], ppn_data_barrier_8.io.y.ppn, UInt<1>(0h0)) node _ppn_T_11 = mux(hitsVec[0][9], ppn_data_barrier_9.io.y.ppn, UInt<1>(0h0)) node _ppn_T_12 = mux(hitsVec[0][10], ppn_data_barrier_10.io.y.ppn, UInt<1>(0h0)) node _ppn_T_13 = mux(hitsVec[0][11], ppn_data_barrier_11.io.y.ppn, UInt<1>(0h0)) node _ppn_T_14 = mux(hitsVec[0][12], ppn_data_barrier_12.io.y.ppn, UInt<1>(0h0)) node _ppn_T_15 = mux(_ppn_T, _ppn_T_1, UInt<1>(0h0)) node _ppn_T_16 = or(_ppn_T_2, _ppn_T_3) node _ppn_T_17 = or(_ppn_T_16, _ppn_T_4) node _ppn_T_18 = or(_ppn_T_17, _ppn_T_5) node _ppn_T_19 = or(_ppn_T_18, _ppn_T_6) node _ppn_T_20 = or(_ppn_T_19, _ppn_T_7) node _ppn_T_21 = or(_ppn_T_20, _ppn_T_8) node _ppn_T_22 = or(_ppn_T_21, _ppn_T_9) node _ppn_T_23 = or(_ppn_T_22, _ppn_T_10) node _ppn_T_24 = or(_ppn_T_23, _ppn_T_11) node _ppn_T_25 = or(_ppn_T_24, _ppn_T_12) node _ppn_T_26 = or(_ppn_T_25, _ppn_T_13) node _ppn_T_27 = or(_ppn_T_26, _ppn_T_14) node _ppn_T_28 = or(_ppn_T_27, _ppn_T_15) wire _ppn_WIRE : UInt<20> connect _ppn_WIRE, _ppn_T_28 wire ppn : UInt<20>[1] connect ppn[0], _ppn_WIRE when do_refill : wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable[0] connect newEntry.u, io.ptw.resp.bits.pte.u connect newEntry.g, io.ptw.resp.bits.pte.g connect newEntry.ae, io.ptw.resp.bits.ae_final node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r[0] connect newEntry.pw, prot_w[0] connect newEntry.px, prot_x[0] connect newEntry.pal, prot_al[0] connect newEntry.paa, prot_aa[0] connect newEntry.eff, prot_eff[0] connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag, r_refill_tag node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, newEntry.fragmented_superpage) node special_entry_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node special_entry_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node special_entry_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag, r_refill_tag node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_0_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_0_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) when _T_4 : connect superpage_entries[1].tag, r_refill_tag node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[1].level, _superpage_entries_1_level_T connect superpage_entries[1].valid[0], UInt<1>(0h1) node superpage_entries_1_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_1_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_1_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) node superpage_entries_1_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_1_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) node superpage_entries_1_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_1_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) when _T_5 : connect superpage_entries[2].tag, r_refill_tag node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[2].level, _superpage_entries_2_level_T connect superpage_entries[2].valid[0], UInt<1>(0h1) node superpage_entries_2_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_2_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_2_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) node superpage_entries_2_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_2_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) node superpage_entries_2_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_2_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) when _T_6 : connect superpage_entries[3].tag, r_refill_tag node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[3].level, _superpage_entries_3_level_T connect superpage_entries[3].valid[0], UInt<1>(0h1) node superpage_entries_3_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_3_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_3_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) node superpage_entries_3_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_3_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) node superpage_entries_3_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_3_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T else : node waddr = mux(r_sectored_hit, r_sectored_hit_addr, r_sectored_repl_addr) node _T_7 = eq(waddr, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_8 : connect sectored_entries[0].valid[0], UInt<1>(0h0) connect sectored_entries[0].valid[1], UInt<1>(0h0) connect sectored_entries[0].valid[2], UInt<1>(0h0) connect sectored_entries[0].valid[3], UInt<1>(0h0) connect sectored_entries[0].tag, r_refill_tag connect sectored_entries[0].level, UInt<2>(0h0) node idx = bits(r_refill_tag, 1, 0) connect sectored_entries[0].valid[idx], UInt<1>(0h1) node sectored_entries_0_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_0_data_lo_lo = cat(sectored_entries_0_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_0_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_data_lo_hi = cat(sectored_entries_0_data_lo_hi_hi, sectored_entries_0_data_lo_hi_lo) node sectored_entries_0_data_lo = cat(sectored_entries_0_data_lo_hi, sectored_entries_0_data_lo_lo) node sectored_entries_0_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_0_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_0_data_hi_lo = cat(sectored_entries_0_data_hi_lo_hi, sectored_entries_0_data_hi_lo_lo) node sectored_entries_0_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_0_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_data_hi_hi = cat(sectored_entries_0_data_hi_hi_hi, sectored_entries_0_data_hi_hi_lo) node sectored_entries_0_data_hi = cat(sectored_entries_0_data_hi_hi, sectored_entries_0_data_hi_lo) node _sectored_entries_0_data_T = cat(sectored_entries_0_data_hi, sectored_entries_0_data_lo) connect sectored_entries[0].data[idx], _sectored_entries_0_data_T node _T_9 = eq(waddr, UInt<1>(0h1)) when _T_9 : node _T_10 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_10 : connect sectored_entries[1].valid[0], UInt<1>(0h0) connect sectored_entries[1].valid[1], UInt<1>(0h0) connect sectored_entries[1].valid[2], UInt<1>(0h0) connect sectored_entries[1].valid[3], UInt<1>(0h0) connect sectored_entries[1].tag, r_refill_tag connect sectored_entries[1].level, UInt<2>(0h0) node idx_1 = bits(r_refill_tag, 1, 0) connect sectored_entries[1].valid[idx_1], UInt<1>(0h1) node sectored_entries_1_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_1_data_lo_lo = cat(sectored_entries_1_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_1_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_1_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_1_data_lo_hi = cat(sectored_entries_1_data_lo_hi_hi, sectored_entries_1_data_lo_hi_lo) node sectored_entries_1_data_lo = cat(sectored_entries_1_data_lo_hi, sectored_entries_1_data_lo_lo) node sectored_entries_1_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_1_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_1_data_hi_lo = cat(sectored_entries_1_data_hi_lo_hi, sectored_entries_1_data_hi_lo_lo) node sectored_entries_1_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_1_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_1_data_hi_hi = cat(sectored_entries_1_data_hi_hi_hi, sectored_entries_1_data_hi_hi_lo) node sectored_entries_1_data_hi = cat(sectored_entries_1_data_hi_hi, sectored_entries_1_data_hi_lo) node _sectored_entries_1_data_T = cat(sectored_entries_1_data_hi, sectored_entries_1_data_lo) connect sectored_entries[1].data[idx_1], _sectored_entries_1_data_T node _T_11 = eq(waddr, UInt<2>(0h2)) when _T_11 : node _T_12 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_12 : connect sectored_entries[2].valid[0], UInt<1>(0h0) connect sectored_entries[2].valid[1], UInt<1>(0h0) connect sectored_entries[2].valid[2], UInt<1>(0h0) connect sectored_entries[2].valid[3], UInt<1>(0h0) connect sectored_entries[2].tag, r_refill_tag connect sectored_entries[2].level, UInt<2>(0h0) node idx_2 = bits(r_refill_tag, 1, 0) connect sectored_entries[2].valid[idx_2], UInt<1>(0h1) node sectored_entries_2_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_2_data_lo_lo = cat(sectored_entries_2_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_2_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_2_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_2_data_lo_hi = cat(sectored_entries_2_data_lo_hi_hi, sectored_entries_2_data_lo_hi_lo) node sectored_entries_2_data_lo = cat(sectored_entries_2_data_lo_hi, sectored_entries_2_data_lo_lo) node sectored_entries_2_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_2_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_2_data_hi_lo = cat(sectored_entries_2_data_hi_lo_hi, sectored_entries_2_data_hi_lo_lo) node sectored_entries_2_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_2_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_2_data_hi_hi = cat(sectored_entries_2_data_hi_hi_hi, sectored_entries_2_data_hi_hi_lo) node sectored_entries_2_data_hi = cat(sectored_entries_2_data_hi_hi, sectored_entries_2_data_hi_lo) node _sectored_entries_2_data_T = cat(sectored_entries_2_data_hi, sectored_entries_2_data_lo) connect sectored_entries[2].data[idx_2], _sectored_entries_2_data_T node _T_13 = eq(waddr, UInt<2>(0h3)) when _T_13 : node _T_14 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_14 : connect sectored_entries[3].valid[0], UInt<1>(0h0) connect sectored_entries[3].valid[1], UInt<1>(0h0) connect sectored_entries[3].valid[2], UInt<1>(0h0) connect sectored_entries[3].valid[3], UInt<1>(0h0) connect sectored_entries[3].tag, r_refill_tag connect sectored_entries[3].level, UInt<2>(0h0) node idx_3 = bits(r_refill_tag, 1, 0) connect sectored_entries[3].valid[idx_3], UInt<1>(0h1) node sectored_entries_3_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_3_data_lo_lo = cat(sectored_entries_3_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_3_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_3_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_3_data_lo_hi = cat(sectored_entries_3_data_lo_hi_hi, sectored_entries_3_data_lo_hi_lo) node sectored_entries_3_data_lo = cat(sectored_entries_3_data_lo_hi, sectored_entries_3_data_lo_lo) node sectored_entries_3_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_3_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_3_data_hi_lo = cat(sectored_entries_3_data_hi_lo_hi, sectored_entries_3_data_hi_lo_lo) node sectored_entries_3_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_3_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_3_data_hi_hi = cat(sectored_entries_3_data_hi_hi_hi, sectored_entries_3_data_hi_hi_lo) node sectored_entries_3_data_hi = cat(sectored_entries_3_data_hi_hi, sectored_entries_3_data_hi_lo) node _sectored_entries_3_data_T = cat(sectored_entries_3_data_hi, sectored_entries_3_data_lo) connect sectored_entries[3].data[idx_3], _sectored_entries_3_data_T node _T_15 = eq(waddr, UInt<3>(0h4)) when _T_15 : node _T_16 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_16 : connect sectored_entries[4].valid[0], UInt<1>(0h0) connect sectored_entries[4].valid[1], UInt<1>(0h0) connect sectored_entries[4].valid[2], UInt<1>(0h0) connect sectored_entries[4].valid[3], UInt<1>(0h0) connect sectored_entries[4].tag, r_refill_tag connect sectored_entries[4].level, UInt<2>(0h0) node idx_4 = bits(r_refill_tag, 1, 0) connect sectored_entries[4].valid[idx_4], UInt<1>(0h1) node sectored_entries_4_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_4_data_lo_lo = cat(sectored_entries_4_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_4_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_4_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_4_data_lo_hi = cat(sectored_entries_4_data_lo_hi_hi, sectored_entries_4_data_lo_hi_lo) node sectored_entries_4_data_lo = cat(sectored_entries_4_data_lo_hi, sectored_entries_4_data_lo_lo) node sectored_entries_4_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_4_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_4_data_hi_lo = cat(sectored_entries_4_data_hi_lo_hi, sectored_entries_4_data_hi_lo_lo) node sectored_entries_4_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_4_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_4_data_hi_hi = cat(sectored_entries_4_data_hi_hi_hi, sectored_entries_4_data_hi_hi_lo) node sectored_entries_4_data_hi = cat(sectored_entries_4_data_hi_hi, sectored_entries_4_data_hi_lo) node _sectored_entries_4_data_T = cat(sectored_entries_4_data_hi, sectored_entries_4_data_lo) connect sectored_entries[4].data[idx_4], _sectored_entries_4_data_T node _T_17 = eq(waddr, UInt<3>(0h5)) when _T_17 : node _T_18 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_18 : connect sectored_entries[5].valid[0], UInt<1>(0h0) connect sectored_entries[5].valid[1], UInt<1>(0h0) connect sectored_entries[5].valid[2], UInt<1>(0h0) connect sectored_entries[5].valid[3], UInt<1>(0h0) connect sectored_entries[5].tag, r_refill_tag connect sectored_entries[5].level, UInt<2>(0h0) node idx_5 = bits(r_refill_tag, 1, 0) connect sectored_entries[5].valid[idx_5], UInt<1>(0h1) node sectored_entries_5_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_5_data_lo_lo = cat(sectored_entries_5_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_5_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_5_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_5_data_lo_hi = cat(sectored_entries_5_data_lo_hi_hi, sectored_entries_5_data_lo_hi_lo) node sectored_entries_5_data_lo = cat(sectored_entries_5_data_lo_hi, sectored_entries_5_data_lo_lo) node sectored_entries_5_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_5_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_5_data_hi_lo = cat(sectored_entries_5_data_hi_lo_hi, sectored_entries_5_data_hi_lo_lo) node sectored_entries_5_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_5_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_5_data_hi_hi = cat(sectored_entries_5_data_hi_hi_hi, sectored_entries_5_data_hi_hi_lo) node sectored_entries_5_data_hi = cat(sectored_entries_5_data_hi_hi, sectored_entries_5_data_hi_lo) node _sectored_entries_5_data_T = cat(sectored_entries_5_data_hi, sectored_entries_5_data_lo) connect sectored_entries[5].data[idx_5], _sectored_entries_5_data_T node _T_19 = eq(waddr, UInt<3>(0h6)) when _T_19 : node _T_20 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_20 : connect sectored_entries[6].valid[0], UInt<1>(0h0) connect sectored_entries[6].valid[1], UInt<1>(0h0) connect sectored_entries[6].valid[2], UInt<1>(0h0) connect sectored_entries[6].valid[3], UInt<1>(0h0) connect sectored_entries[6].tag, r_refill_tag connect sectored_entries[6].level, UInt<2>(0h0) node idx_6 = bits(r_refill_tag, 1, 0) connect sectored_entries[6].valid[idx_6], UInt<1>(0h1) node sectored_entries_6_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_6_data_lo_lo = cat(sectored_entries_6_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_6_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_6_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_6_data_lo_hi = cat(sectored_entries_6_data_lo_hi_hi, sectored_entries_6_data_lo_hi_lo) node sectored_entries_6_data_lo = cat(sectored_entries_6_data_lo_hi, sectored_entries_6_data_lo_lo) node sectored_entries_6_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_6_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_6_data_hi_lo = cat(sectored_entries_6_data_hi_lo_hi, sectored_entries_6_data_hi_lo_lo) node sectored_entries_6_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_6_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_6_data_hi_hi = cat(sectored_entries_6_data_hi_hi_hi, sectored_entries_6_data_hi_hi_lo) node sectored_entries_6_data_hi = cat(sectored_entries_6_data_hi_hi, sectored_entries_6_data_hi_lo) node _sectored_entries_6_data_T = cat(sectored_entries_6_data_hi, sectored_entries_6_data_lo) connect sectored_entries[6].data[idx_6], _sectored_entries_6_data_T node _T_21 = eq(waddr, UInt<3>(0h7)) when _T_21 : node _T_22 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_22 : connect sectored_entries[7].valid[0], UInt<1>(0h0) connect sectored_entries[7].valid[1], UInt<1>(0h0) connect sectored_entries[7].valid[2], UInt<1>(0h0) connect sectored_entries[7].valid[3], UInt<1>(0h0) connect sectored_entries[7].tag, r_refill_tag connect sectored_entries[7].level, UInt<2>(0h0) node idx_7 = bits(r_refill_tag, 1, 0) connect sectored_entries[7].valid[idx_7], UInt<1>(0h1) node sectored_entries_7_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_7_data_lo_lo = cat(sectored_entries_7_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_7_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_7_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_7_data_lo_hi = cat(sectored_entries_7_data_lo_hi_hi, sectored_entries_7_data_lo_hi_lo) node sectored_entries_7_data_lo = cat(sectored_entries_7_data_lo_hi, sectored_entries_7_data_lo_lo) node sectored_entries_7_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_7_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_7_data_hi_lo = cat(sectored_entries_7_data_hi_lo_hi, sectored_entries_7_data_hi_lo_lo) node sectored_entries_7_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_7_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_7_data_hi_hi = cat(sectored_entries_7_data_hi_hi_hi, sectored_entries_7_data_hi_hi_lo) node sectored_entries_7_data_hi = cat(sectored_entries_7_data_hi_hi, sectored_entries_7_data_hi_lo) node _sectored_entries_7_data_T = cat(sectored_entries_7_data_hi, sectored_entries_7_data_lo) connect sectored_entries[7].data[idx_7], _sectored_entries_7_data_T node _entries_T = bits(vpn[0], 1, 0) wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<34> connect _entries_WIRE_1, sectored_entries[0].data[_entries_T] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.pr, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.px, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.pw, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.sr, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.sx, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.sw, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.ae, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.g, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.u, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 33, 14) connect _entries_WIRE.ppn, _entries_T_15 inst entries_barrier of OptimizationBarrier_EntryData_14 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.ae, _entries_WIRE.ae connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn node _entries_T_16 = bits(vpn[0], 1, 0) wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<34> connect _entries_WIRE_3, sectored_entries[1].data[_entries_T_16] node _entries_T_17 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.pr, _entries_T_22 node _entries_T_23 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.px, _entries_T_23 node _entries_T_24 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.pw, _entries_T_24 node _entries_T_25 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.sr, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.sx, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.sw, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.ae, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.g, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.u, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 33, 14) connect _entries_WIRE_2.ppn, _entries_T_31 inst entries_barrier_1 of OptimizationBarrier_EntryData_15 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.ae, _entries_WIRE_2.ae connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn node _entries_T_32 = bits(vpn[0], 1, 0) wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<34> connect _entries_WIRE_5, sectored_entries[2].data[_entries_T_32] node _entries_T_33 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.pr, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.px, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.pw, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.sr, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.sx, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.sw, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.ae, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.g, _entries_T_45 node _entries_T_46 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.u, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_5, 33, 14) connect _entries_WIRE_4.ppn, _entries_T_47 inst entries_barrier_2 of OptimizationBarrier_EntryData_16 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.ae, _entries_WIRE_4.ae connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn node _entries_T_48 = bits(vpn[0], 1, 0) wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<34> connect _entries_WIRE_7, sectored_entries[3].data[_entries_T_48] node _entries_T_49 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.pr, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.px, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.pw, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.sr, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.sx, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.sw, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.ae, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.g, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.u, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_7, 33, 14) connect _entries_WIRE_6.ppn, _entries_T_63 inst entries_barrier_3 of OptimizationBarrier_EntryData_17 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.ae, _entries_WIRE_6.ae connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn node _entries_T_64 = bits(vpn[0], 1, 0) wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<34> connect _entries_WIRE_9, sectored_entries[4].data[_entries_T_64] node _entries_T_65 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_68 node _entries_T_69 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.pr, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.px, _entries_T_71 node _entries_T_72 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.pw, _entries_T_72 node _entries_T_73 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.sr, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.sx, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.sw, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.ae, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.g, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.u, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_9, 33, 14) connect _entries_WIRE_8.ppn, _entries_T_79 inst entries_barrier_4 of OptimizationBarrier_EntryData_18 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.ae, _entries_WIRE_8.ae connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn node _entries_T_80 = bits(vpn[0], 1, 0) wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<34> connect _entries_WIRE_11, sectored_entries[5].data[_entries_T_80] node _entries_T_81 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.pr, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.px, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.pw, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.sr, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.sx, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.sw, _entries_T_91 node _entries_T_92 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.ae, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.g, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.u, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_11, 33, 14) connect _entries_WIRE_10.ppn, _entries_T_95 inst entries_barrier_5 of OptimizationBarrier_EntryData_19 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.ae, _entries_WIRE_10.ae connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _entries_T_96 = bits(vpn[0], 1, 0) wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_13 : UInt<34> connect _entries_WIRE_13, sectored_entries[6].data[_entries_T_96] node _entries_T_97 = bits(_entries_WIRE_13, 0, 0) connect _entries_WIRE_12.fragmented_superpage, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_13, 1, 1) connect _entries_WIRE_12.c, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_13, 2, 2) connect _entries_WIRE_12.eff, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_13, 3, 3) connect _entries_WIRE_12.paa, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_13, 4, 4) connect _entries_WIRE_12.pal, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_13, 5, 5) connect _entries_WIRE_12.pr, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_13, 6, 6) connect _entries_WIRE_12.px, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_13, 7, 7) connect _entries_WIRE_12.pw, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_13, 8, 8) connect _entries_WIRE_12.sr, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_13, 9, 9) connect _entries_WIRE_12.sx, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_13, 10, 10) connect _entries_WIRE_12.sw, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_13, 11, 11) connect _entries_WIRE_12.ae, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_13, 12, 12) connect _entries_WIRE_12.g, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_13, 13, 13) connect _entries_WIRE_12.u, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_13, 33, 14) connect _entries_WIRE_12.ppn, _entries_T_111 inst entries_barrier_6 of OptimizationBarrier_EntryData_20 connect entries_barrier_6.clock, clock connect entries_barrier_6.reset, reset connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage connect entries_barrier_6.io.x.c, _entries_WIRE_12.c connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr connect entries_barrier_6.io.x.px, _entries_WIRE_12.px connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw connect entries_barrier_6.io.x.ae, _entries_WIRE_12.ae connect entries_barrier_6.io.x.g, _entries_WIRE_12.g connect entries_barrier_6.io.x.u, _entries_WIRE_12.u connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn node _entries_T_112 = bits(vpn[0], 1, 0) wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_15 : UInt<34> connect _entries_WIRE_15, sectored_entries[7].data[_entries_T_112] node _entries_T_113 = bits(_entries_WIRE_15, 0, 0) connect _entries_WIRE_14.fragmented_superpage, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_15, 1, 1) connect _entries_WIRE_14.c, _entries_T_114 node _entries_T_115 = bits(_entries_WIRE_15, 2, 2) connect _entries_WIRE_14.eff, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_15, 3, 3) connect _entries_WIRE_14.paa, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_15, 4, 4) connect _entries_WIRE_14.pal, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_15, 5, 5) connect _entries_WIRE_14.pr, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_15, 6, 6) connect _entries_WIRE_14.px, _entries_T_119 node _entries_T_120 = bits(_entries_WIRE_15, 7, 7) connect _entries_WIRE_14.pw, _entries_T_120 node _entries_T_121 = bits(_entries_WIRE_15, 8, 8) connect _entries_WIRE_14.sr, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_15, 9, 9) connect _entries_WIRE_14.sx, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_15, 10, 10) connect _entries_WIRE_14.sw, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_15, 11, 11) connect _entries_WIRE_14.ae, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_15, 12, 12) connect _entries_WIRE_14.g, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_15, 13, 13) connect _entries_WIRE_14.u, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_15, 33, 14) connect _entries_WIRE_14.ppn, _entries_T_127 inst entries_barrier_7 of OptimizationBarrier_EntryData_21 connect entries_barrier_7.clock, clock connect entries_barrier_7.reset, reset connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage connect entries_barrier_7.io.x.c, _entries_WIRE_14.c connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr connect entries_barrier_7.io.x.px, _entries_WIRE_14.px connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw connect entries_barrier_7.io.x.ae, _entries_WIRE_14.ae connect entries_barrier_7.io.x.g, _entries_WIRE_14.g connect entries_barrier_7.io.x.u, _entries_WIRE_14.u connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_17 : UInt<34> connect _entries_WIRE_17, superpage_entries[0].data[0] node _entries_T_128 = bits(_entries_WIRE_17, 0, 0) connect _entries_WIRE_16.fragmented_superpage, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_17, 1, 1) connect _entries_WIRE_16.c, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_17, 2, 2) connect _entries_WIRE_16.eff, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_17, 3, 3) connect _entries_WIRE_16.paa, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_17, 4, 4) connect _entries_WIRE_16.pal, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_17, 5, 5) connect _entries_WIRE_16.pr, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_17, 6, 6) connect _entries_WIRE_16.px, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_17, 7, 7) connect _entries_WIRE_16.pw, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_17, 8, 8) connect _entries_WIRE_16.sr, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_17, 9, 9) connect _entries_WIRE_16.sx, _entries_T_137 node _entries_T_138 = bits(_entries_WIRE_17, 10, 10) connect _entries_WIRE_16.sw, _entries_T_138 node _entries_T_139 = bits(_entries_WIRE_17, 11, 11) connect _entries_WIRE_16.ae, _entries_T_139 node _entries_T_140 = bits(_entries_WIRE_17, 12, 12) connect _entries_WIRE_16.g, _entries_T_140 node _entries_T_141 = bits(_entries_WIRE_17, 13, 13) connect _entries_WIRE_16.u, _entries_T_141 node _entries_T_142 = bits(_entries_WIRE_17, 33, 14) connect _entries_WIRE_16.ppn, _entries_T_142 inst entries_barrier_8 of OptimizationBarrier_EntryData_22 connect entries_barrier_8.clock, clock connect entries_barrier_8.reset, reset connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage connect entries_barrier_8.io.x.c, _entries_WIRE_16.c connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr connect entries_barrier_8.io.x.px, _entries_WIRE_16.px connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw connect entries_barrier_8.io.x.ae, _entries_WIRE_16.ae connect entries_barrier_8.io.x.g, _entries_WIRE_16.g connect entries_barrier_8.io.x.u, _entries_WIRE_16.u connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_19 : UInt<34> connect _entries_WIRE_19, superpage_entries[1].data[0] node _entries_T_143 = bits(_entries_WIRE_19, 0, 0) connect _entries_WIRE_18.fragmented_superpage, _entries_T_143 node _entries_T_144 = bits(_entries_WIRE_19, 1, 1) connect _entries_WIRE_18.c, _entries_T_144 node _entries_T_145 = bits(_entries_WIRE_19, 2, 2) connect _entries_WIRE_18.eff, _entries_T_145 node _entries_T_146 = bits(_entries_WIRE_19, 3, 3) connect _entries_WIRE_18.paa, _entries_T_146 node _entries_T_147 = bits(_entries_WIRE_19, 4, 4) connect _entries_WIRE_18.pal, _entries_T_147 node _entries_T_148 = bits(_entries_WIRE_19, 5, 5) connect _entries_WIRE_18.pr, _entries_T_148 node _entries_T_149 = bits(_entries_WIRE_19, 6, 6) connect _entries_WIRE_18.px, _entries_T_149 node _entries_T_150 = bits(_entries_WIRE_19, 7, 7) connect _entries_WIRE_18.pw, _entries_T_150 node _entries_T_151 = bits(_entries_WIRE_19, 8, 8) connect _entries_WIRE_18.sr, _entries_T_151 node _entries_T_152 = bits(_entries_WIRE_19, 9, 9) connect _entries_WIRE_18.sx, _entries_T_152 node _entries_T_153 = bits(_entries_WIRE_19, 10, 10) connect _entries_WIRE_18.sw, _entries_T_153 node _entries_T_154 = bits(_entries_WIRE_19, 11, 11) connect _entries_WIRE_18.ae, _entries_T_154 node _entries_T_155 = bits(_entries_WIRE_19, 12, 12) connect _entries_WIRE_18.g, _entries_T_155 node _entries_T_156 = bits(_entries_WIRE_19, 13, 13) connect _entries_WIRE_18.u, _entries_T_156 node _entries_T_157 = bits(_entries_WIRE_19, 33, 14) connect _entries_WIRE_18.ppn, _entries_T_157 inst entries_barrier_9 of OptimizationBarrier_EntryData_23 connect entries_barrier_9.clock, clock connect entries_barrier_9.reset, reset connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage connect entries_barrier_9.io.x.c, _entries_WIRE_18.c connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr connect entries_barrier_9.io.x.px, _entries_WIRE_18.px connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw connect entries_barrier_9.io.x.ae, _entries_WIRE_18.ae connect entries_barrier_9.io.x.g, _entries_WIRE_18.g connect entries_barrier_9.io.x.u, _entries_WIRE_18.u connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_21 : UInt<34> connect _entries_WIRE_21, superpage_entries[2].data[0] node _entries_T_158 = bits(_entries_WIRE_21, 0, 0) connect _entries_WIRE_20.fragmented_superpage, _entries_T_158 node _entries_T_159 = bits(_entries_WIRE_21, 1, 1) connect _entries_WIRE_20.c, _entries_T_159 node _entries_T_160 = bits(_entries_WIRE_21, 2, 2) connect _entries_WIRE_20.eff, _entries_T_160 node _entries_T_161 = bits(_entries_WIRE_21, 3, 3) connect _entries_WIRE_20.paa, _entries_T_161 node _entries_T_162 = bits(_entries_WIRE_21, 4, 4) connect _entries_WIRE_20.pal, _entries_T_162 node _entries_T_163 = bits(_entries_WIRE_21, 5, 5) connect _entries_WIRE_20.pr, _entries_T_163 node _entries_T_164 = bits(_entries_WIRE_21, 6, 6) connect _entries_WIRE_20.px, _entries_T_164 node _entries_T_165 = bits(_entries_WIRE_21, 7, 7) connect _entries_WIRE_20.pw, _entries_T_165 node _entries_T_166 = bits(_entries_WIRE_21, 8, 8) connect _entries_WIRE_20.sr, _entries_T_166 node _entries_T_167 = bits(_entries_WIRE_21, 9, 9) connect _entries_WIRE_20.sx, _entries_T_167 node _entries_T_168 = bits(_entries_WIRE_21, 10, 10) connect _entries_WIRE_20.sw, _entries_T_168 node _entries_T_169 = bits(_entries_WIRE_21, 11, 11) connect _entries_WIRE_20.ae, _entries_T_169 node _entries_T_170 = bits(_entries_WIRE_21, 12, 12) connect _entries_WIRE_20.g, _entries_T_170 node _entries_T_171 = bits(_entries_WIRE_21, 13, 13) connect _entries_WIRE_20.u, _entries_T_171 node _entries_T_172 = bits(_entries_WIRE_21, 33, 14) connect _entries_WIRE_20.ppn, _entries_T_172 inst entries_barrier_10 of OptimizationBarrier_EntryData_24 connect entries_barrier_10.clock, clock connect entries_barrier_10.reset, reset connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage connect entries_barrier_10.io.x.c, _entries_WIRE_20.c connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr connect entries_barrier_10.io.x.px, _entries_WIRE_20.px connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw connect entries_barrier_10.io.x.ae, _entries_WIRE_20.ae connect entries_barrier_10.io.x.g, _entries_WIRE_20.g connect entries_barrier_10.io.x.u, _entries_WIRE_20.u connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_23 : UInt<34> connect _entries_WIRE_23, superpage_entries[3].data[0] node _entries_T_173 = bits(_entries_WIRE_23, 0, 0) connect _entries_WIRE_22.fragmented_superpage, _entries_T_173 node _entries_T_174 = bits(_entries_WIRE_23, 1, 1) connect _entries_WIRE_22.c, _entries_T_174 node _entries_T_175 = bits(_entries_WIRE_23, 2, 2) connect _entries_WIRE_22.eff, _entries_T_175 node _entries_T_176 = bits(_entries_WIRE_23, 3, 3) connect _entries_WIRE_22.paa, _entries_T_176 node _entries_T_177 = bits(_entries_WIRE_23, 4, 4) connect _entries_WIRE_22.pal, _entries_T_177 node _entries_T_178 = bits(_entries_WIRE_23, 5, 5) connect _entries_WIRE_22.pr, _entries_T_178 node _entries_T_179 = bits(_entries_WIRE_23, 6, 6) connect _entries_WIRE_22.px, _entries_T_179 node _entries_T_180 = bits(_entries_WIRE_23, 7, 7) connect _entries_WIRE_22.pw, _entries_T_180 node _entries_T_181 = bits(_entries_WIRE_23, 8, 8) connect _entries_WIRE_22.sr, _entries_T_181 node _entries_T_182 = bits(_entries_WIRE_23, 9, 9) connect _entries_WIRE_22.sx, _entries_T_182 node _entries_T_183 = bits(_entries_WIRE_23, 10, 10) connect _entries_WIRE_22.sw, _entries_T_183 node _entries_T_184 = bits(_entries_WIRE_23, 11, 11) connect _entries_WIRE_22.ae, _entries_T_184 node _entries_T_185 = bits(_entries_WIRE_23, 12, 12) connect _entries_WIRE_22.g, _entries_T_185 node _entries_T_186 = bits(_entries_WIRE_23, 13, 13) connect _entries_WIRE_22.u, _entries_T_186 node _entries_T_187 = bits(_entries_WIRE_23, 33, 14) connect _entries_WIRE_22.ppn, _entries_T_187 inst entries_barrier_11 of OptimizationBarrier_EntryData_25 connect entries_barrier_11.clock, clock connect entries_barrier_11.reset, reset connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage connect entries_barrier_11.io.x.c, _entries_WIRE_22.c connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr connect entries_barrier_11.io.x.px, _entries_WIRE_22.px connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw connect entries_barrier_11.io.x.ae, _entries_WIRE_22.ae connect entries_barrier_11.io.x.g, _entries_WIRE_22.g connect entries_barrier_11.io.x.u, _entries_WIRE_22.u connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_25 : UInt<34> connect _entries_WIRE_25, special_entry.data[0] node _entries_T_188 = bits(_entries_WIRE_25, 0, 0) connect _entries_WIRE_24.fragmented_superpage, _entries_T_188 node _entries_T_189 = bits(_entries_WIRE_25, 1, 1) connect _entries_WIRE_24.c, _entries_T_189 node _entries_T_190 = bits(_entries_WIRE_25, 2, 2) connect _entries_WIRE_24.eff, _entries_T_190 node _entries_T_191 = bits(_entries_WIRE_25, 3, 3) connect _entries_WIRE_24.paa, _entries_T_191 node _entries_T_192 = bits(_entries_WIRE_25, 4, 4) connect _entries_WIRE_24.pal, _entries_T_192 node _entries_T_193 = bits(_entries_WIRE_25, 5, 5) connect _entries_WIRE_24.pr, _entries_T_193 node _entries_T_194 = bits(_entries_WIRE_25, 6, 6) connect _entries_WIRE_24.px, _entries_T_194 node _entries_T_195 = bits(_entries_WIRE_25, 7, 7) connect _entries_WIRE_24.pw, _entries_T_195 node _entries_T_196 = bits(_entries_WIRE_25, 8, 8) connect _entries_WIRE_24.sr, _entries_T_196 node _entries_T_197 = bits(_entries_WIRE_25, 9, 9) connect _entries_WIRE_24.sx, _entries_T_197 node _entries_T_198 = bits(_entries_WIRE_25, 10, 10) connect _entries_WIRE_24.sw, _entries_T_198 node _entries_T_199 = bits(_entries_WIRE_25, 11, 11) connect _entries_WIRE_24.ae, _entries_T_199 node _entries_T_200 = bits(_entries_WIRE_25, 12, 12) connect _entries_WIRE_24.g, _entries_T_200 node _entries_T_201 = bits(_entries_WIRE_25, 13, 13) connect _entries_WIRE_24.u, _entries_T_201 node _entries_T_202 = bits(_entries_WIRE_25, 33, 14) connect _entries_WIRE_24.ppn, _entries_T_202 inst entries_barrier_12 of OptimizationBarrier_EntryData_26 connect entries_barrier_12.clock, clock connect entries_barrier_12.reset, reset connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage connect entries_barrier_12.io.x.c, _entries_WIRE_24.c connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr connect entries_barrier_12.io.x.px, _entries_WIRE_24.px connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw connect entries_barrier_12.io.x.ae, _entries_WIRE_24.ae connect entries_barrier_12.io.x.g, _entries_WIRE_24.g connect entries_barrier_12.io.x.u, _entries_WIRE_24.u connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn wire _entries_WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[13] connect _entries_WIRE_26[0], entries_barrier.io.y connect _entries_WIRE_26[1], entries_barrier_1.io.y connect _entries_WIRE_26[2], entries_barrier_2.io.y connect _entries_WIRE_26[3], entries_barrier_3.io.y connect _entries_WIRE_26[4], entries_barrier_4.io.y connect _entries_WIRE_26[5], entries_barrier_5.io.y connect _entries_WIRE_26[6], entries_barrier_6.io.y connect _entries_WIRE_26[7], entries_barrier_7.io.y connect _entries_WIRE_26[8], entries_barrier_8.io.y connect _entries_WIRE_26[9], entries_barrier_9.io.y connect _entries_WIRE_26[10], entries_barrier_10.io.y connect _entries_WIRE_26[11], entries_barrier_11.io.y connect _entries_WIRE_26[12], entries_barrier_12.io.y wire entries : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[13][1] connect entries[0], _entries_WIRE_26 node _normal_entries_T = bits(vpn[0], 1, 0) wire _normal_entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_1 : UInt<34> connect _normal_entries_WIRE_1, sectored_entries[0].data[_normal_entries_T] node _normal_entries_T_1 = bits(_normal_entries_WIRE_1, 0, 0) connect _normal_entries_WIRE.fragmented_superpage, _normal_entries_T_1 node _normal_entries_T_2 = bits(_normal_entries_WIRE_1, 1, 1) connect _normal_entries_WIRE.c, _normal_entries_T_2 node _normal_entries_T_3 = bits(_normal_entries_WIRE_1, 2, 2) connect _normal_entries_WIRE.eff, _normal_entries_T_3 node _normal_entries_T_4 = bits(_normal_entries_WIRE_1, 3, 3) connect _normal_entries_WIRE.paa, _normal_entries_T_4 node _normal_entries_T_5 = bits(_normal_entries_WIRE_1, 4, 4) connect _normal_entries_WIRE.pal, _normal_entries_T_5 node _normal_entries_T_6 = bits(_normal_entries_WIRE_1, 5, 5) connect _normal_entries_WIRE.pr, _normal_entries_T_6 node _normal_entries_T_7 = bits(_normal_entries_WIRE_1, 6, 6) connect _normal_entries_WIRE.px, _normal_entries_T_7 node _normal_entries_T_8 = bits(_normal_entries_WIRE_1, 7, 7) connect _normal_entries_WIRE.pw, _normal_entries_T_8 node _normal_entries_T_9 = bits(_normal_entries_WIRE_1, 8, 8) connect _normal_entries_WIRE.sr, _normal_entries_T_9 node _normal_entries_T_10 = bits(_normal_entries_WIRE_1, 9, 9) connect _normal_entries_WIRE.sx, _normal_entries_T_10 node _normal_entries_T_11 = bits(_normal_entries_WIRE_1, 10, 10) connect _normal_entries_WIRE.sw, _normal_entries_T_11 node _normal_entries_T_12 = bits(_normal_entries_WIRE_1, 11, 11) connect _normal_entries_WIRE.ae, _normal_entries_T_12 node _normal_entries_T_13 = bits(_normal_entries_WIRE_1, 12, 12) connect _normal_entries_WIRE.g, _normal_entries_T_13 node _normal_entries_T_14 = bits(_normal_entries_WIRE_1, 13, 13) connect _normal_entries_WIRE.u, _normal_entries_T_14 node _normal_entries_T_15 = bits(_normal_entries_WIRE_1, 33, 14) connect _normal_entries_WIRE.ppn, _normal_entries_T_15 inst normal_entries_barrier of OptimizationBarrier_EntryData_27 connect normal_entries_barrier.clock, clock connect normal_entries_barrier.reset, reset connect normal_entries_barrier.io.x.fragmented_superpage, _normal_entries_WIRE.fragmented_superpage connect normal_entries_barrier.io.x.c, _normal_entries_WIRE.c connect normal_entries_barrier.io.x.eff, _normal_entries_WIRE.eff connect normal_entries_barrier.io.x.paa, _normal_entries_WIRE.paa connect normal_entries_barrier.io.x.pal, _normal_entries_WIRE.pal connect normal_entries_barrier.io.x.pr, _normal_entries_WIRE.pr connect normal_entries_barrier.io.x.px, _normal_entries_WIRE.px connect normal_entries_barrier.io.x.pw, _normal_entries_WIRE.pw connect normal_entries_barrier.io.x.sr, _normal_entries_WIRE.sr connect normal_entries_barrier.io.x.sx, _normal_entries_WIRE.sx connect normal_entries_barrier.io.x.sw, _normal_entries_WIRE.sw connect normal_entries_barrier.io.x.ae, _normal_entries_WIRE.ae connect normal_entries_barrier.io.x.g, _normal_entries_WIRE.g connect normal_entries_barrier.io.x.u, _normal_entries_WIRE.u connect normal_entries_barrier.io.x.ppn, _normal_entries_WIRE.ppn node _normal_entries_T_16 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_3 : UInt<34> connect _normal_entries_WIRE_3, sectored_entries[1].data[_normal_entries_T_16] node _normal_entries_T_17 = bits(_normal_entries_WIRE_3, 0, 0) connect _normal_entries_WIRE_2.fragmented_superpage, _normal_entries_T_17 node _normal_entries_T_18 = bits(_normal_entries_WIRE_3, 1, 1) connect _normal_entries_WIRE_2.c, _normal_entries_T_18 node _normal_entries_T_19 = bits(_normal_entries_WIRE_3, 2, 2) connect _normal_entries_WIRE_2.eff, _normal_entries_T_19 node _normal_entries_T_20 = bits(_normal_entries_WIRE_3, 3, 3) connect _normal_entries_WIRE_2.paa, _normal_entries_T_20 node _normal_entries_T_21 = bits(_normal_entries_WIRE_3, 4, 4) connect _normal_entries_WIRE_2.pal, _normal_entries_T_21 node _normal_entries_T_22 = bits(_normal_entries_WIRE_3, 5, 5) connect _normal_entries_WIRE_2.pr, _normal_entries_T_22 node _normal_entries_T_23 = bits(_normal_entries_WIRE_3, 6, 6) connect _normal_entries_WIRE_2.px, _normal_entries_T_23 node _normal_entries_T_24 = bits(_normal_entries_WIRE_3, 7, 7) connect _normal_entries_WIRE_2.pw, _normal_entries_T_24 node _normal_entries_T_25 = bits(_normal_entries_WIRE_3, 8, 8) connect _normal_entries_WIRE_2.sr, _normal_entries_T_25 node _normal_entries_T_26 = bits(_normal_entries_WIRE_3, 9, 9) connect _normal_entries_WIRE_2.sx, _normal_entries_T_26 node _normal_entries_T_27 = bits(_normal_entries_WIRE_3, 10, 10) connect _normal_entries_WIRE_2.sw, _normal_entries_T_27 node _normal_entries_T_28 = bits(_normal_entries_WIRE_3, 11, 11) connect _normal_entries_WIRE_2.ae, _normal_entries_T_28 node _normal_entries_T_29 = bits(_normal_entries_WIRE_3, 12, 12) connect _normal_entries_WIRE_2.g, _normal_entries_T_29 node _normal_entries_T_30 = bits(_normal_entries_WIRE_3, 13, 13) connect _normal_entries_WIRE_2.u, _normal_entries_T_30 node _normal_entries_T_31 = bits(_normal_entries_WIRE_3, 33, 14) connect _normal_entries_WIRE_2.ppn, _normal_entries_T_31 inst normal_entries_barrier_1 of OptimizationBarrier_EntryData_28 connect normal_entries_barrier_1.clock, clock connect normal_entries_barrier_1.reset, reset connect normal_entries_barrier_1.io.x.fragmented_superpage, _normal_entries_WIRE_2.fragmented_superpage connect normal_entries_barrier_1.io.x.c, _normal_entries_WIRE_2.c connect normal_entries_barrier_1.io.x.eff, _normal_entries_WIRE_2.eff connect normal_entries_barrier_1.io.x.paa, _normal_entries_WIRE_2.paa connect normal_entries_barrier_1.io.x.pal, _normal_entries_WIRE_2.pal connect normal_entries_barrier_1.io.x.pr, _normal_entries_WIRE_2.pr connect normal_entries_barrier_1.io.x.px, _normal_entries_WIRE_2.px connect normal_entries_barrier_1.io.x.pw, _normal_entries_WIRE_2.pw connect normal_entries_barrier_1.io.x.sr, _normal_entries_WIRE_2.sr connect normal_entries_barrier_1.io.x.sx, _normal_entries_WIRE_2.sx connect normal_entries_barrier_1.io.x.sw, _normal_entries_WIRE_2.sw connect normal_entries_barrier_1.io.x.ae, _normal_entries_WIRE_2.ae connect normal_entries_barrier_1.io.x.g, _normal_entries_WIRE_2.g connect normal_entries_barrier_1.io.x.u, _normal_entries_WIRE_2.u connect normal_entries_barrier_1.io.x.ppn, _normal_entries_WIRE_2.ppn node _normal_entries_T_32 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_5 : UInt<34> connect _normal_entries_WIRE_5, sectored_entries[2].data[_normal_entries_T_32] node _normal_entries_T_33 = bits(_normal_entries_WIRE_5, 0, 0) connect _normal_entries_WIRE_4.fragmented_superpage, _normal_entries_T_33 node _normal_entries_T_34 = bits(_normal_entries_WIRE_5, 1, 1) connect _normal_entries_WIRE_4.c, _normal_entries_T_34 node _normal_entries_T_35 = bits(_normal_entries_WIRE_5, 2, 2) connect _normal_entries_WIRE_4.eff, _normal_entries_T_35 node _normal_entries_T_36 = bits(_normal_entries_WIRE_5, 3, 3) connect _normal_entries_WIRE_4.paa, _normal_entries_T_36 node _normal_entries_T_37 = bits(_normal_entries_WIRE_5, 4, 4) connect _normal_entries_WIRE_4.pal, _normal_entries_T_37 node _normal_entries_T_38 = bits(_normal_entries_WIRE_5, 5, 5) connect _normal_entries_WIRE_4.pr, _normal_entries_T_38 node _normal_entries_T_39 = bits(_normal_entries_WIRE_5, 6, 6) connect _normal_entries_WIRE_4.px, _normal_entries_T_39 node _normal_entries_T_40 = bits(_normal_entries_WIRE_5, 7, 7) connect _normal_entries_WIRE_4.pw, _normal_entries_T_40 node _normal_entries_T_41 = bits(_normal_entries_WIRE_5, 8, 8) connect _normal_entries_WIRE_4.sr, _normal_entries_T_41 node _normal_entries_T_42 = bits(_normal_entries_WIRE_5, 9, 9) connect _normal_entries_WIRE_4.sx, _normal_entries_T_42 node _normal_entries_T_43 = bits(_normal_entries_WIRE_5, 10, 10) connect _normal_entries_WIRE_4.sw, _normal_entries_T_43 node _normal_entries_T_44 = bits(_normal_entries_WIRE_5, 11, 11) connect _normal_entries_WIRE_4.ae, _normal_entries_T_44 node _normal_entries_T_45 = bits(_normal_entries_WIRE_5, 12, 12) connect _normal_entries_WIRE_4.g, _normal_entries_T_45 node _normal_entries_T_46 = bits(_normal_entries_WIRE_5, 13, 13) connect _normal_entries_WIRE_4.u, _normal_entries_T_46 node _normal_entries_T_47 = bits(_normal_entries_WIRE_5, 33, 14) connect _normal_entries_WIRE_4.ppn, _normal_entries_T_47 inst normal_entries_barrier_2 of OptimizationBarrier_EntryData_29 connect normal_entries_barrier_2.clock, clock connect normal_entries_barrier_2.reset, reset connect normal_entries_barrier_2.io.x.fragmented_superpage, _normal_entries_WIRE_4.fragmented_superpage connect normal_entries_barrier_2.io.x.c, _normal_entries_WIRE_4.c connect normal_entries_barrier_2.io.x.eff, _normal_entries_WIRE_4.eff connect normal_entries_barrier_2.io.x.paa, _normal_entries_WIRE_4.paa connect normal_entries_barrier_2.io.x.pal, _normal_entries_WIRE_4.pal connect normal_entries_barrier_2.io.x.pr, _normal_entries_WIRE_4.pr connect normal_entries_barrier_2.io.x.px, _normal_entries_WIRE_4.px connect normal_entries_barrier_2.io.x.pw, _normal_entries_WIRE_4.pw connect normal_entries_barrier_2.io.x.sr, _normal_entries_WIRE_4.sr connect normal_entries_barrier_2.io.x.sx, _normal_entries_WIRE_4.sx connect normal_entries_barrier_2.io.x.sw, _normal_entries_WIRE_4.sw connect normal_entries_barrier_2.io.x.ae, _normal_entries_WIRE_4.ae connect normal_entries_barrier_2.io.x.g, _normal_entries_WIRE_4.g connect normal_entries_barrier_2.io.x.u, _normal_entries_WIRE_4.u connect normal_entries_barrier_2.io.x.ppn, _normal_entries_WIRE_4.ppn node _normal_entries_T_48 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_7 : UInt<34> connect _normal_entries_WIRE_7, sectored_entries[3].data[_normal_entries_T_48] node _normal_entries_T_49 = bits(_normal_entries_WIRE_7, 0, 0) connect _normal_entries_WIRE_6.fragmented_superpage, _normal_entries_T_49 node _normal_entries_T_50 = bits(_normal_entries_WIRE_7, 1, 1) connect _normal_entries_WIRE_6.c, _normal_entries_T_50 node _normal_entries_T_51 = bits(_normal_entries_WIRE_7, 2, 2) connect _normal_entries_WIRE_6.eff, _normal_entries_T_51 node _normal_entries_T_52 = bits(_normal_entries_WIRE_7, 3, 3) connect _normal_entries_WIRE_6.paa, _normal_entries_T_52 node _normal_entries_T_53 = bits(_normal_entries_WIRE_7, 4, 4) connect _normal_entries_WIRE_6.pal, _normal_entries_T_53 node _normal_entries_T_54 = bits(_normal_entries_WIRE_7, 5, 5) connect _normal_entries_WIRE_6.pr, _normal_entries_T_54 node _normal_entries_T_55 = bits(_normal_entries_WIRE_7, 6, 6) connect _normal_entries_WIRE_6.px, _normal_entries_T_55 node _normal_entries_T_56 = bits(_normal_entries_WIRE_7, 7, 7) connect _normal_entries_WIRE_6.pw, _normal_entries_T_56 node _normal_entries_T_57 = bits(_normal_entries_WIRE_7, 8, 8) connect _normal_entries_WIRE_6.sr, _normal_entries_T_57 node _normal_entries_T_58 = bits(_normal_entries_WIRE_7, 9, 9) connect _normal_entries_WIRE_6.sx, _normal_entries_T_58 node _normal_entries_T_59 = bits(_normal_entries_WIRE_7, 10, 10) connect _normal_entries_WIRE_6.sw, _normal_entries_T_59 node _normal_entries_T_60 = bits(_normal_entries_WIRE_7, 11, 11) connect _normal_entries_WIRE_6.ae, _normal_entries_T_60 node _normal_entries_T_61 = bits(_normal_entries_WIRE_7, 12, 12) connect _normal_entries_WIRE_6.g, _normal_entries_T_61 node _normal_entries_T_62 = bits(_normal_entries_WIRE_7, 13, 13) connect _normal_entries_WIRE_6.u, _normal_entries_T_62 node _normal_entries_T_63 = bits(_normal_entries_WIRE_7, 33, 14) connect _normal_entries_WIRE_6.ppn, _normal_entries_T_63 inst normal_entries_barrier_3 of OptimizationBarrier_EntryData_30 connect normal_entries_barrier_3.clock, clock connect normal_entries_barrier_3.reset, reset connect normal_entries_barrier_3.io.x.fragmented_superpage, _normal_entries_WIRE_6.fragmented_superpage connect normal_entries_barrier_3.io.x.c, _normal_entries_WIRE_6.c connect normal_entries_barrier_3.io.x.eff, _normal_entries_WIRE_6.eff connect normal_entries_barrier_3.io.x.paa, _normal_entries_WIRE_6.paa connect normal_entries_barrier_3.io.x.pal, _normal_entries_WIRE_6.pal connect normal_entries_barrier_3.io.x.pr, _normal_entries_WIRE_6.pr connect normal_entries_barrier_3.io.x.px, _normal_entries_WIRE_6.px connect normal_entries_barrier_3.io.x.pw, _normal_entries_WIRE_6.pw connect normal_entries_barrier_3.io.x.sr, _normal_entries_WIRE_6.sr connect normal_entries_barrier_3.io.x.sx, _normal_entries_WIRE_6.sx connect normal_entries_barrier_3.io.x.sw, _normal_entries_WIRE_6.sw connect normal_entries_barrier_3.io.x.ae, _normal_entries_WIRE_6.ae connect normal_entries_barrier_3.io.x.g, _normal_entries_WIRE_6.g connect normal_entries_barrier_3.io.x.u, _normal_entries_WIRE_6.u connect normal_entries_barrier_3.io.x.ppn, _normal_entries_WIRE_6.ppn node _normal_entries_T_64 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_9 : UInt<34> connect _normal_entries_WIRE_9, sectored_entries[4].data[_normal_entries_T_64] node _normal_entries_T_65 = bits(_normal_entries_WIRE_9, 0, 0) connect _normal_entries_WIRE_8.fragmented_superpage, _normal_entries_T_65 node _normal_entries_T_66 = bits(_normal_entries_WIRE_9, 1, 1) connect _normal_entries_WIRE_8.c, _normal_entries_T_66 node _normal_entries_T_67 = bits(_normal_entries_WIRE_9, 2, 2) connect _normal_entries_WIRE_8.eff, _normal_entries_T_67 node _normal_entries_T_68 = bits(_normal_entries_WIRE_9, 3, 3) connect _normal_entries_WIRE_8.paa, _normal_entries_T_68 node _normal_entries_T_69 = bits(_normal_entries_WIRE_9, 4, 4) connect _normal_entries_WIRE_8.pal, _normal_entries_T_69 node _normal_entries_T_70 = bits(_normal_entries_WIRE_9, 5, 5) connect _normal_entries_WIRE_8.pr, _normal_entries_T_70 node _normal_entries_T_71 = bits(_normal_entries_WIRE_9, 6, 6) connect _normal_entries_WIRE_8.px, _normal_entries_T_71 node _normal_entries_T_72 = bits(_normal_entries_WIRE_9, 7, 7) connect _normal_entries_WIRE_8.pw, _normal_entries_T_72 node _normal_entries_T_73 = bits(_normal_entries_WIRE_9, 8, 8) connect _normal_entries_WIRE_8.sr, _normal_entries_T_73 node _normal_entries_T_74 = bits(_normal_entries_WIRE_9, 9, 9) connect _normal_entries_WIRE_8.sx, _normal_entries_T_74 node _normal_entries_T_75 = bits(_normal_entries_WIRE_9, 10, 10) connect _normal_entries_WIRE_8.sw, _normal_entries_T_75 node _normal_entries_T_76 = bits(_normal_entries_WIRE_9, 11, 11) connect _normal_entries_WIRE_8.ae, _normal_entries_T_76 node _normal_entries_T_77 = bits(_normal_entries_WIRE_9, 12, 12) connect _normal_entries_WIRE_8.g, _normal_entries_T_77 node _normal_entries_T_78 = bits(_normal_entries_WIRE_9, 13, 13) connect _normal_entries_WIRE_8.u, _normal_entries_T_78 node _normal_entries_T_79 = bits(_normal_entries_WIRE_9, 33, 14) connect _normal_entries_WIRE_8.ppn, _normal_entries_T_79 inst normal_entries_barrier_4 of OptimizationBarrier_EntryData_31 connect normal_entries_barrier_4.clock, clock connect normal_entries_barrier_4.reset, reset connect normal_entries_barrier_4.io.x.fragmented_superpage, _normal_entries_WIRE_8.fragmented_superpage connect normal_entries_barrier_4.io.x.c, _normal_entries_WIRE_8.c connect normal_entries_barrier_4.io.x.eff, _normal_entries_WIRE_8.eff connect normal_entries_barrier_4.io.x.paa, _normal_entries_WIRE_8.paa connect normal_entries_barrier_4.io.x.pal, _normal_entries_WIRE_8.pal connect normal_entries_barrier_4.io.x.pr, _normal_entries_WIRE_8.pr connect normal_entries_barrier_4.io.x.px, _normal_entries_WIRE_8.px connect normal_entries_barrier_4.io.x.pw, _normal_entries_WIRE_8.pw connect normal_entries_barrier_4.io.x.sr, _normal_entries_WIRE_8.sr connect normal_entries_barrier_4.io.x.sx, _normal_entries_WIRE_8.sx connect normal_entries_barrier_4.io.x.sw, _normal_entries_WIRE_8.sw connect normal_entries_barrier_4.io.x.ae, _normal_entries_WIRE_8.ae connect normal_entries_barrier_4.io.x.g, _normal_entries_WIRE_8.g connect normal_entries_barrier_4.io.x.u, _normal_entries_WIRE_8.u connect normal_entries_barrier_4.io.x.ppn, _normal_entries_WIRE_8.ppn node _normal_entries_T_80 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_11 : UInt<34> connect _normal_entries_WIRE_11, sectored_entries[5].data[_normal_entries_T_80] node _normal_entries_T_81 = bits(_normal_entries_WIRE_11, 0, 0) connect _normal_entries_WIRE_10.fragmented_superpage, _normal_entries_T_81 node _normal_entries_T_82 = bits(_normal_entries_WIRE_11, 1, 1) connect _normal_entries_WIRE_10.c, _normal_entries_T_82 node _normal_entries_T_83 = bits(_normal_entries_WIRE_11, 2, 2) connect _normal_entries_WIRE_10.eff, _normal_entries_T_83 node _normal_entries_T_84 = bits(_normal_entries_WIRE_11, 3, 3) connect _normal_entries_WIRE_10.paa, _normal_entries_T_84 node _normal_entries_T_85 = bits(_normal_entries_WIRE_11, 4, 4) connect _normal_entries_WIRE_10.pal, _normal_entries_T_85 node _normal_entries_T_86 = bits(_normal_entries_WIRE_11, 5, 5) connect _normal_entries_WIRE_10.pr, _normal_entries_T_86 node _normal_entries_T_87 = bits(_normal_entries_WIRE_11, 6, 6) connect _normal_entries_WIRE_10.px, _normal_entries_T_87 node _normal_entries_T_88 = bits(_normal_entries_WIRE_11, 7, 7) connect _normal_entries_WIRE_10.pw, _normal_entries_T_88 node _normal_entries_T_89 = bits(_normal_entries_WIRE_11, 8, 8) connect _normal_entries_WIRE_10.sr, _normal_entries_T_89 node _normal_entries_T_90 = bits(_normal_entries_WIRE_11, 9, 9) connect _normal_entries_WIRE_10.sx, _normal_entries_T_90 node _normal_entries_T_91 = bits(_normal_entries_WIRE_11, 10, 10) connect _normal_entries_WIRE_10.sw, _normal_entries_T_91 node _normal_entries_T_92 = bits(_normal_entries_WIRE_11, 11, 11) connect _normal_entries_WIRE_10.ae, _normal_entries_T_92 node _normal_entries_T_93 = bits(_normal_entries_WIRE_11, 12, 12) connect _normal_entries_WIRE_10.g, _normal_entries_T_93 node _normal_entries_T_94 = bits(_normal_entries_WIRE_11, 13, 13) connect _normal_entries_WIRE_10.u, _normal_entries_T_94 node _normal_entries_T_95 = bits(_normal_entries_WIRE_11, 33, 14) connect _normal_entries_WIRE_10.ppn, _normal_entries_T_95 inst normal_entries_barrier_5 of OptimizationBarrier_EntryData_32 connect normal_entries_barrier_5.clock, clock connect normal_entries_barrier_5.reset, reset connect normal_entries_barrier_5.io.x.fragmented_superpage, _normal_entries_WIRE_10.fragmented_superpage connect normal_entries_barrier_5.io.x.c, _normal_entries_WIRE_10.c connect normal_entries_barrier_5.io.x.eff, _normal_entries_WIRE_10.eff connect normal_entries_barrier_5.io.x.paa, _normal_entries_WIRE_10.paa connect normal_entries_barrier_5.io.x.pal, _normal_entries_WIRE_10.pal connect normal_entries_barrier_5.io.x.pr, _normal_entries_WIRE_10.pr connect normal_entries_barrier_5.io.x.px, _normal_entries_WIRE_10.px connect normal_entries_barrier_5.io.x.pw, _normal_entries_WIRE_10.pw connect normal_entries_barrier_5.io.x.sr, _normal_entries_WIRE_10.sr connect normal_entries_barrier_5.io.x.sx, _normal_entries_WIRE_10.sx connect normal_entries_barrier_5.io.x.sw, _normal_entries_WIRE_10.sw connect normal_entries_barrier_5.io.x.ae, _normal_entries_WIRE_10.ae connect normal_entries_barrier_5.io.x.g, _normal_entries_WIRE_10.g connect normal_entries_barrier_5.io.x.u, _normal_entries_WIRE_10.u connect normal_entries_barrier_5.io.x.ppn, _normal_entries_WIRE_10.ppn node _normal_entries_T_96 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_13 : UInt<34> connect _normal_entries_WIRE_13, sectored_entries[6].data[_normal_entries_T_96] node _normal_entries_T_97 = bits(_normal_entries_WIRE_13, 0, 0) connect _normal_entries_WIRE_12.fragmented_superpage, _normal_entries_T_97 node _normal_entries_T_98 = bits(_normal_entries_WIRE_13, 1, 1) connect _normal_entries_WIRE_12.c, _normal_entries_T_98 node _normal_entries_T_99 = bits(_normal_entries_WIRE_13, 2, 2) connect _normal_entries_WIRE_12.eff, _normal_entries_T_99 node _normal_entries_T_100 = bits(_normal_entries_WIRE_13, 3, 3) connect _normal_entries_WIRE_12.paa, _normal_entries_T_100 node _normal_entries_T_101 = bits(_normal_entries_WIRE_13, 4, 4) connect _normal_entries_WIRE_12.pal, _normal_entries_T_101 node _normal_entries_T_102 = bits(_normal_entries_WIRE_13, 5, 5) connect _normal_entries_WIRE_12.pr, _normal_entries_T_102 node _normal_entries_T_103 = bits(_normal_entries_WIRE_13, 6, 6) connect _normal_entries_WIRE_12.px, _normal_entries_T_103 node _normal_entries_T_104 = bits(_normal_entries_WIRE_13, 7, 7) connect _normal_entries_WIRE_12.pw, _normal_entries_T_104 node _normal_entries_T_105 = bits(_normal_entries_WIRE_13, 8, 8) connect _normal_entries_WIRE_12.sr, _normal_entries_T_105 node _normal_entries_T_106 = bits(_normal_entries_WIRE_13, 9, 9) connect _normal_entries_WIRE_12.sx, _normal_entries_T_106 node _normal_entries_T_107 = bits(_normal_entries_WIRE_13, 10, 10) connect _normal_entries_WIRE_12.sw, _normal_entries_T_107 node _normal_entries_T_108 = bits(_normal_entries_WIRE_13, 11, 11) connect _normal_entries_WIRE_12.ae, _normal_entries_T_108 node _normal_entries_T_109 = bits(_normal_entries_WIRE_13, 12, 12) connect _normal_entries_WIRE_12.g, _normal_entries_T_109 node _normal_entries_T_110 = bits(_normal_entries_WIRE_13, 13, 13) connect _normal_entries_WIRE_12.u, _normal_entries_T_110 node _normal_entries_T_111 = bits(_normal_entries_WIRE_13, 33, 14) connect _normal_entries_WIRE_12.ppn, _normal_entries_T_111 inst normal_entries_barrier_6 of OptimizationBarrier_EntryData_33 connect normal_entries_barrier_6.clock, clock connect normal_entries_barrier_6.reset, reset connect normal_entries_barrier_6.io.x.fragmented_superpage, _normal_entries_WIRE_12.fragmented_superpage connect normal_entries_barrier_6.io.x.c, _normal_entries_WIRE_12.c connect normal_entries_barrier_6.io.x.eff, _normal_entries_WIRE_12.eff connect normal_entries_barrier_6.io.x.paa, _normal_entries_WIRE_12.paa connect normal_entries_barrier_6.io.x.pal, _normal_entries_WIRE_12.pal connect normal_entries_barrier_6.io.x.pr, _normal_entries_WIRE_12.pr connect normal_entries_barrier_6.io.x.px, _normal_entries_WIRE_12.px connect normal_entries_barrier_6.io.x.pw, _normal_entries_WIRE_12.pw connect normal_entries_barrier_6.io.x.sr, _normal_entries_WIRE_12.sr connect normal_entries_barrier_6.io.x.sx, _normal_entries_WIRE_12.sx connect normal_entries_barrier_6.io.x.sw, _normal_entries_WIRE_12.sw connect normal_entries_barrier_6.io.x.ae, _normal_entries_WIRE_12.ae connect normal_entries_barrier_6.io.x.g, _normal_entries_WIRE_12.g connect normal_entries_barrier_6.io.x.u, _normal_entries_WIRE_12.u connect normal_entries_barrier_6.io.x.ppn, _normal_entries_WIRE_12.ppn node _normal_entries_T_112 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_15 : UInt<34> connect _normal_entries_WIRE_15, sectored_entries[7].data[_normal_entries_T_112] node _normal_entries_T_113 = bits(_normal_entries_WIRE_15, 0, 0) connect _normal_entries_WIRE_14.fragmented_superpage, _normal_entries_T_113 node _normal_entries_T_114 = bits(_normal_entries_WIRE_15, 1, 1) connect _normal_entries_WIRE_14.c, _normal_entries_T_114 node _normal_entries_T_115 = bits(_normal_entries_WIRE_15, 2, 2) connect _normal_entries_WIRE_14.eff, _normal_entries_T_115 node _normal_entries_T_116 = bits(_normal_entries_WIRE_15, 3, 3) connect _normal_entries_WIRE_14.paa, _normal_entries_T_116 node _normal_entries_T_117 = bits(_normal_entries_WIRE_15, 4, 4) connect _normal_entries_WIRE_14.pal, _normal_entries_T_117 node _normal_entries_T_118 = bits(_normal_entries_WIRE_15, 5, 5) connect _normal_entries_WIRE_14.pr, _normal_entries_T_118 node _normal_entries_T_119 = bits(_normal_entries_WIRE_15, 6, 6) connect _normal_entries_WIRE_14.px, _normal_entries_T_119 node _normal_entries_T_120 = bits(_normal_entries_WIRE_15, 7, 7) connect _normal_entries_WIRE_14.pw, _normal_entries_T_120 node _normal_entries_T_121 = bits(_normal_entries_WIRE_15, 8, 8) connect _normal_entries_WIRE_14.sr, _normal_entries_T_121 node _normal_entries_T_122 = bits(_normal_entries_WIRE_15, 9, 9) connect _normal_entries_WIRE_14.sx, _normal_entries_T_122 node _normal_entries_T_123 = bits(_normal_entries_WIRE_15, 10, 10) connect _normal_entries_WIRE_14.sw, _normal_entries_T_123 node _normal_entries_T_124 = bits(_normal_entries_WIRE_15, 11, 11) connect _normal_entries_WIRE_14.ae, _normal_entries_T_124 node _normal_entries_T_125 = bits(_normal_entries_WIRE_15, 12, 12) connect _normal_entries_WIRE_14.g, _normal_entries_T_125 node _normal_entries_T_126 = bits(_normal_entries_WIRE_15, 13, 13) connect _normal_entries_WIRE_14.u, _normal_entries_T_126 node _normal_entries_T_127 = bits(_normal_entries_WIRE_15, 33, 14) connect _normal_entries_WIRE_14.ppn, _normal_entries_T_127 inst normal_entries_barrier_7 of OptimizationBarrier_EntryData_34 connect normal_entries_barrier_7.clock, clock connect normal_entries_barrier_7.reset, reset connect normal_entries_barrier_7.io.x.fragmented_superpage, _normal_entries_WIRE_14.fragmented_superpage connect normal_entries_barrier_7.io.x.c, _normal_entries_WIRE_14.c connect normal_entries_barrier_7.io.x.eff, _normal_entries_WIRE_14.eff connect normal_entries_barrier_7.io.x.paa, _normal_entries_WIRE_14.paa connect normal_entries_barrier_7.io.x.pal, _normal_entries_WIRE_14.pal connect normal_entries_barrier_7.io.x.pr, _normal_entries_WIRE_14.pr connect normal_entries_barrier_7.io.x.px, _normal_entries_WIRE_14.px connect normal_entries_barrier_7.io.x.pw, _normal_entries_WIRE_14.pw connect normal_entries_barrier_7.io.x.sr, _normal_entries_WIRE_14.sr connect normal_entries_barrier_7.io.x.sx, _normal_entries_WIRE_14.sx connect normal_entries_barrier_7.io.x.sw, _normal_entries_WIRE_14.sw connect normal_entries_barrier_7.io.x.ae, _normal_entries_WIRE_14.ae connect normal_entries_barrier_7.io.x.g, _normal_entries_WIRE_14.g connect normal_entries_barrier_7.io.x.u, _normal_entries_WIRE_14.u connect normal_entries_barrier_7.io.x.ppn, _normal_entries_WIRE_14.ppn wire _normal_entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_17 : UInt<34> connect _normal_entries_WIRE_17, superpage_entries[0].data[0] node _normal_entries_T_128 = bits(_normal_entries_WIRE_17, 0, 0) connect _normal_entries_WIRE_16.fragmented_superpage, _normal_entries_T_128 node _normal_entries_T_129 = bits(_normal_entries_WIRE_17, 1, 1) connect _normal_entries_WIRE_16.c, _normal_entries_T_129 node _normal_entries_T_130 = bits(_normal_entries_WIRE_17, 2, 2) connect _normal_entries_WIRE_16.eff, _normal_entries_T_130 node _normal_entries_T_131 = bits(_normal_entries_WIRE_17, 3, 3) connect _normal_entries_WIRE_16.paa, _normal_entries_T_131 node _normal_entries_T_132 = bits(_normal_entries_WIRE_17, 4, 4) connect _normal_entries_WIRE_16.pal, _normal_entries_T_132 node _normal_entries_T_133 = bits(_normal_entries_WIRE_17, 5, 5) connect _normal_entries_WIRE_16.pr, _normal_entries_T_133 node _normal_entries_T_134 = bits(_normal_entries_WIRE_17, 6, 6) connect _normal_entries_WIRE_16.px, _normal_entries_T_134 node _normal_entries_T_135 = bits(_normal_entries_WIRE_17, 7, 7) connect _normal_entries_WIRE_16.pw, _normal_entries_T_135 node _normal_entries_T_136 = bits(_normal_entries_WIRE_17, 8, 8) connect _normal_entries_WIRE_16.sr, _normal_entries_T_136 node _normal_entries_T_137 = bits(_normal_entries_WIRE_17, 9, 9) connect _normal_entries_WIRE_16.sx, _normal_entries_T_137 node _normal_entries_T_138 = bits(_normal_entries_WIRE_17, 10, 10) connect _normal_entries_WIRE_16.sw, _normal_entries_T_138 node _normal_entries_T_139 = bits(_normal_entries_WIRE_17, 11, 11) connect _normal_entries_WIRE_16.ae, _normal_entries_T_139 node _normal_entries_T_140 = bits(_normal_entries_WIRE_17, 12, 12) connect _normal_entries_WIRE_16.g, _normal_entries_T_140 node _normal_entries_T_141 = bits(_normal_entries_WIRE_17, 13, 13) connect _normal_entries_WIRE_16.u, _normal_entries_T_141 node _normal_entries_T_142 = bits(_normal_entries_WIRE_17, 33, 14) connect _normal_entries_WIRE_16.ppn, _normal_entries_T_142 inst normal_entries_barrier_8 of OptimizationBarrier_EntryData_35 connect normal_entries_barrier_8.clock, clock connect normal_entries_barrier_8.reset, reset connect normal_entries_barrier_8.io.x.fragmented_superpage, _normal_entries_WIRE_16.fragmented_superpage connect normal_entries_barrier_8.io.x.c, _normal_entries_WIRE_16.c connect normal_entries_barrier_8.io.x.eff, _normal_entries_WIRE_16.eff connect normal_entries_barrier_8.io.x.paa, _normal_entries_WIRE_16.paa connect normal_entries_barrier_8.io.x.pal, _normal_entries_WIRE_16.pal connect normal_entries_barrier_8.io.x.pr, _normal_entries_WIRE_16.pr connect normal_entries_barrier_8.io.x.px, _normal_entries_WIRE_16.px connect normal_entries_barrier_8.io.x.pw, _normal_entries_WIRE_16.pw connect normal_entries_barrier_8.io.x.sr, _normal_entries_WIRE_16.sr connect normal_entries_barrier_8.io.x.sx, _normal_entries_WIRE_16.sx connect normal_entries_barrier_8.io.x.sw, _normal_entries_WIRE_16.sw connect normal_entries_barrier_8.io.x.ae, _normal_entries_WIRE_16.ae connect normal_entries_barrier_8.io.x.g, _normal_entries_WIRE_16.g connect normal_entries_barrier_8.io.x.u, _normal_entries_WIRE_16.u connect normal_entries_barrier_8.io.x.ppn, _normal_entries_WIRE_16.ppn wire _normal_entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_19 : UInt<34> connect _normal_entries_WIRE_19, superpage_entries[1].data[0] node _normal_entries_T_143 = bits(_normal_entries_WIRE_19, 0, 0) connect _normal_entries_WIRE_18.fragmented_superpage, _normal_entries_T_143 node _normal_entries_T_144 = bits(_normal_entries_WIRE_19, 1, 1) connect _normal_entries_WIRE_18.c, _normal_entries_T_144 node _normal_entries_T_145 = bits(_normal_entries_WIRE_19, 2, 2) connect _normal_entries_WIRE_18.eff, _normal_entries_T_145 node _normal_entries_T_146 = bits(_normal_entries_WIRE_19, 3, 3) connect _normal_entries_WIRE_18.paa, _normal_entries_T_146 node _normal_entries_T_147 = bits(_normal_entries_WIRE_19, 4, 4) connect _normal_entries_WIRE_18.pal, _normal_entries_T_147 node _normal_entries_T_148 = bits(_normal_entries_WIRE_19, 5, 5) connect _normal_entries_WIRE_18.pr, _normal_entries_T_148 node _normal_entries_T_149 = bits(_normal_entries_WIRE_19, 6, 6) connect _normal_entries_WIRE_18.px, _normal_entries_T_149 node _normal_entries_T_150 = bits(_normal_entries_WIRE_19, 7, 7) connect _normal_entries_WIRE_18.pw, _normal_entries_T_150 node _normal_entries_T_151 = bits(_normal_entries_WIRE_19, 8, 8) connect _normal_entries_WIRE_18.sr, _normal_entries_T_151 node _normal_entries_T_152 = bits(_normal_entries_WIRE_19, 9, 9) connect _normal_entries_WIRE_18.sx, _normal_entries_T_152 node _normal_entries_T_153 = bits(_normal_entries_WIRE_19, 10, 10) connect _normal_entries_WIRE_18.sw, _normal_entries_T_153 node _normal_entries_T_154 = bits(_normal_entries_WIRE_19, 11, 11) connect _normal_entries_WIRE_18.ae, _normal_entries_T_154 node _normal_entries_T_155 = bits(_normal_entries_WIRE_19, 12, 12) connect _normal_entries_WIRE_18.g, _normal_entries_T_155 node _normal_entries_T_156 = bits(_normal_entries_WIRE_19, 13, 13) connect _normal_entries_WIRE_18.u, _normal_entries_T_156 node _normal_entries_T_157 = bits(_normal_entries_WIRE_19, 33, 14) connect _normal_entries_WIRE_18.ppn, _normal_entries_T_157 inst normal_entries_barrier_9 of OptimizationBarrier_EntryData_36 connect normal_entries_barrier_9.clock, clock connect normal_entries_barrier_9.reset, reset connect normal_entries_barrier_9.io.x.fragmented_superpage, _normal_entries_WIRE_18.fragmented_superpage connect normal_entries_barrier_9.io.x.c, _normal_entries_WIRE_18.c connect normal_entries_barrier_9.io.x.eff, _normal_entries_WIRE_18.eff connect normal_entries_barrier_9.io.x.paa, _normal_entries_WIRE_18.paa connect normal_entries_barrier_9.io.x.pal, _normal_entries_WIRE_18.pal connect normal_entries_barrier_9.io.x.pr, _normal_entries_WIRE_18.pr connect normal_entries_barrier_9.io.x.px, _normal_entries_WIRE_18.px connect normal_entries_barrier_9.io.x.pw, _normal_entries_WIRE_18.pw connect normal_entries_barrier_9.io.x.sr, _normal_entries_WIRE_18.sr connect normal_entries_barrier_9.io.x.sx, _normal_entries_WIRE_18.sx connect normal_entries_barrier_9.io.x.sw, _normal_entries_WIRE_18.sw connect normal_entries_barrier_9.io.x.ae, _normal_entries_WIRE_18.ae connect normal_entries_barrier_9.io.x.g, _normal_entries_WIRE_18.g connect normal_entries_barrier_9.io.x.u, _normal_entries_WIRE_18.u connect normal_entries_barrier_9.io.x.ppn, _normal_entries_WIRE_18.ppn wire _normal_entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_21 : UInt<34> connect _normal_entries_WIRE_21, superpage_entries[2].data[0] node _normal_entries_T_158 = bits(_normal_entries_WIRE_21, 0, 0) connect _normal_entries_WIRE_20.fragmented_superpage, _normal_entries_T_158 node _normal_entries_T_159 = bits(_normal_entries_WIRE_21, 1, 1) connect _normal_entries_WIRE_20.c, _normal_entries_T_159 node _normal_entries_T_160 = bits(_normal_entries_WIRE_21, 2, 2) connect _normal_entries_WIRE_20.eff, _normal_entries_T_160 node _normal_entries_T_161 = bits(_normal_entries_WIRE_21, 3, 3) connect _normal_entries_WIRE_20.paa, _normal_entries_T_161 node _normal_entries_T_162 = bits(_normal_entries_WIRE_21, 4, 4) connect _normal_entries_WIRE_20.pal, _normal_entries_T_162 node _normal_entries_T_163 = bits(_normal_entries_WIRE_21, 5, 5) connect _normal_entries_WIRE_20.pr, _normal_entries_T_163 node _normal_entries_T_164 = bits(_normal_entries_WIRE_21, 6, 6) connect _normal_entries_WIRE_20.px, _normal_entries_T_164 node _normal_entries_T_165 = bits(_normal_entries_WIRE_21, 7, 7) connect _normal_entries_WIRE_20.pw, _normal_entries_T_165 node _normal_entries_T_166 = bits(_normal_entries_WIRE_21, 8, 8) connect _normal_entries_WIRE_20.sr, _normal_entries_T_166 node _normal_entries_T_167 = bits(_normal_entries_WIRE_21, 9, 9) connect _normal_entries_WIRE_20.sx, _normal_entries_T_167 node _normal_entries_T_168 = bits(_normal_entries_WIRE_21, 10, 10) connect _normal_entries_WIRE_20.sw, _normal_entries_T_168 node _normal_entries_T_169 = bits(_normal_entries_WIRE_21, 11, 11) connect _normal_entries_WIRE_20.ae, _normal_entries_T_169 node _normal_entries_T_170 = bits(_normal_entries_WIRE_21, 12, 12) connect _normal_entries_WIRE_20.g, _normal_entries_T_170 node _normal_entries_T_171 = bits(_normal_entries_WIRE_21, 13, 13) connect _normal_entries_WIRE_20.u, _normal_entries_T_171 node _normal_entries_T_172 = bits(_normal_entries_WIRE_21, 33, 14) connect _normal_entries_WIRE_20.ppn, _normal_entries_T_172 inst normal_entries_barrier_10 of OptimizationBarrier_EntryData_37 connect normal_entries_barrier_10.clock, clock connect normal_entries_barrier_10.reset, reset connect normal_entries_barrier_10.io.x.fragmented_superpage, _normal_entries_WIRE_20.fragmented_superpage connect normal_entries_barrier_10.io.x.c, _normal_entries_WIRE_20.c connect normal_entries_barrier_10.io.x.eff, _normal_entries_WIRE_20.eff connect normal_entries_barrier_10.io.x.paa, _normal_entries_WIRE_20.paa connect normal_entries_barrier_10.io.x.pal, _normal_entries_WIRE_20.pal connect normal_entries_barrier_10.io.x.pr, _normal_entries_WIRE_20.pr connect normal_entries_barrier_10.io.x.px, _normal_entries_WIRE_20.px connect normal_entries_barrier_10.io.x.pw, _normal_entries_WIRE_20.pw connect normal_entries_barrier_10.io.x.sr, _normal_entries_WIRE_20.sr connect normal_entries_barrier_10.io.x.sx, _normal_entries_WIRE_20.sx connect normal_entries_barrier_10.io.x.sw, _normal_entries_WIRE_20.sw connect normal_entries_barrier_10.io.x.ae, _normal_entries_WIRE_20.ae connect normal_entries_barrier_10.io.x.g, _normal_entries_WIRE_20.g connect normal_entries_barrier_10.io.x.u, _normal_entries_WIRE_20.u connect normal_entries_barrier_10.io.x.ppn, _normal_entries_WIRE_20.ppn wire _normal_entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_23 : UInt<34> connect _normal_entries_WIRE_23, superpage_entries[3].data[0] node _normal_entries_T_173 = bits(_normal_entries_WIRE_23, 0, 0) connect _normal_entries_WIRE_22.fragmented_superpage, _normal_entries_T_173 node _normal_entries_T_174 = bits(_normal_entries_WIRE_23, 1, 1) connect _normal_entries_WIRE_22.c, _normal_entries_T_174 node _normal_entries_T_175 = bits(_normal_entries_WIRE_23, 2, 2) connect _normal_entries_WIRE_22.eff, _normal_entries_T_175 node _normal_entries_T_176 = bits(_normal_entries_WIRE_23, 3, 3) connect _normal_entries_WIRE_22.paa, _normal_entries_T_176 node _normal_entries_T_177 = bits(_normal_entries_WIRE_23, 4, 4) connect _normal_entries_WIRE_22.pal, _normal_entries_T_177 node _normal_entries_T_178 = bits(_normal_entries_WIRE_23, 5, 5) connect _normal_entries_WIRE_22.pr, _normal_entries_T_178 node _normal_entries_T_179 = bits(_normal_entries_WIRE_23, 6, 6) connect _normal_entries_WIRE_22.px, _normal_entries_T_179 node _normal_entries_T_180 = bits(_normal_entries_WIRE_23, 7, 7) connect _normal_entries_WIRE_22.pw, _normal_entries_T_180 node _normal_entries_T_181 = bits(_normal_entries_WIRE_23, 8, 8) connect _normal_entries_WIRE_22.sr, _normal_entries_T_181 node _normal_entries_T_182 = bits(_normal_entries_WIRE_23, 9, 9) connect _normal_entries_WIRE_22.sx, _normal_entries_T_182 node _normal_entries_T_183 = bits(_normal_entries_WIRE_23, 10, 10) connect _normal_entries_WIRE_22.sw, _normal_entries_T_183 node _normal_entries_T_184 = bits(_normal_entries_WIRE_23, 11, 11) connect _normal_entries_WIRE_22.ae, _normal_entries_T_184 node _normal_entries_T_185 = bits(_normal_entries_WIRE_23, 12, 12) connect _normal_entries_WIRE_22.g, _normal_entries_T_185 node _normal_entries_T_186 = bits(_normal_entries_WIRE_23, 13, 13) connect _normal_entries_WIRE_22.u, _normal_entries_T_186 node _normal_entries_T_187 = bits(_normal_entries_WIRE_23, 33, 14) connect _normal_entries_WIRE_22.ppn, _normal_entries_T_187 inst normal_entries_barrier_11 of OptimizationBarrier_EntryData_38 connect normal_entries_barrier_11.clock, clock connect normal_entries_barrier_11.reset, reset connect normal_entries_barrier_11.io.x.fragmented_superpage, _normal_entries_WIRE_22.fragmented_superpage connect normal_entries_barrier_11.io.x.c, _normal_entries_WIRE_22.c connect normal_entries_barrier_11.io.x.eff, _normal_entries_WIRE_22.eff connect normal_entries_barrier_11.io.x.paa, _normal_entries_WIRE_22.paa connect normal_entries_barrier_11.io.x.pal, _normal_entries_WIRE_22.pal connect normal_entries_barrier_11.io.x.pr, _normal_entries_WIRE_22.pr connect normal_entries_barrier_11.io.x.px, _normal_entries_WIRE_22.px connect normal_entries_barrier_11.io.x.pw, _normal_entries_WIRE_22.pw connect normal_entries_barrier_11.io.x.sr, _normal_entries_WIRE_22.sr connect normal_entries_barrier_11.io.x.sx, _normal_entries_WIRE_22.sx connect normal_entries_barrier_11.io.x.sw, _normal_entries_WIRE_22.sw connect normal_entries_barrier_11.io.x.ae, _normal_entries_WIRE_22.ae connect normal_entries_barrier_11.io.x.g, _normal_entries_WIRE_22.g connect normal_entries_barrier_11.io.x.u, _normal_entries_WIRE_22.u connect normal_entries_barrier_11.io.x.ppn, _normal_entries_WIRE_22.ppn wire _normal_entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[12] connect _normal_entries_WIRE_24[0], normal_entries_barrier.io.y connect _normal_entries_WIRE_24[1], normal_entries_barrier_1.io.y connect _normal_entries_WIRE_24[2], normal_entries_barrier_2.io.y connect _normal_entries_WIRE_24[3], normal_entries_barrier_3.io.y connect _normal_entries_WIRE_24[4], normal_entries_barrier_4.io.y connect _normal_entries_WIRE_24[5], normal_entries_barrier_5.io.y connect _normal_entries_WIRE_24[6], normal_entries_barrier_6.io.y connect _normal_entries_WIRE_24[7], normal_entries_barrier_7.io.y connect _normal_entries_WIRE_24[8], normal_entries_barrier_8.io.y connect _normal_entries_WIRE_24[9], normal_entries_barrier_9.io.y connect _normal_entries_WIRE_24[10], normal_entries_barrier_10.io.y connect _normal_entries_WIRE_24[11], normal_entries_barrier_11.io.y wire normal_entries : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[12][1] connect normal_entries[0], _normal_entries_WIRE_24 node ptw_ae_array_lo_lo_hi = cat(entries[0][2].ae, entries[0][1].ae) node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries[0][0].ae) node ptw_ae_array_lo_hi_hi = cat(entries[0][5].ae, entries[0][4].ae) node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries[0][3].ae) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo) node ptw_ae_array_hi_lo_hi = cat(entries[0][8].ae, entries[0][7].ae) node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries[0][6].ae) node ptw_ae_array_hi_hi_lo = cat(entries[0][10].ae, entries[0][9].ae) node ptw_ae_array_hi_hi_hi = cat(entries[0][12].ae, entries[0][11].ae) node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node _ptw_ae_array_T_1 = cat(UInt<1>(0h0), _ptw_ae_array_T) wire ptw_ae_array : UInt<14>[1] connect ptw_ae_array[0], _ptw_ae_array_T_1 node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, io.ptw.status.sum) node priv_rw_ok_lo_lo_hi = cat(entries[0][2].u, entries[0][1].u) node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries[0][0].u) node priv_rw_ok_lo_hi_hi = cat(entries[0][5].u, entries[0][4].u) node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries[0][3].u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo) node priv_rw_ok_hi_lo_hi = cat(entries[0][8].u, entries[0][7].u) node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries[0][6].u) node priv_rw_ok_hi_hi_lo = cat(entries[0][10].u, entries[0][9].u) node priv_rw_ok_hi_hi_hi = cat(entries[0][12].u, entries[0][11].u) node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_lo_hi_1 = cat(entries[0][2].u, entries[0][1].u) node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries[0][0].u) node priv_rw_ok_lo_hi_hi_1 = cat(entries[0][5].u, entries[0][4].u) node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries[0][3].u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1) node priv_rw_ok_hi_lo_hi_1 = cat(entries[0][8].u, entries[0][7].u) node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries[0][6].u) node priv_rw_ok_hi_hi_lo_1 = cat(entries[0][10].u, entries[0][9].u) node priv_rw_ok_hi_hi_hi_1 = cat(entries[0][12].u, entries[0][11].u) node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node _priv_rw_ok_T_7 = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) wire priv_rw_ok : UInt<13>[1] connect priv_rw_ok[0], _priv_rw_ok_T_7 node priv_x_ok_lo_lo_hi = cat(entries[0][2].u, entries[0][1].u) node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries[0][0].u) node priv_x_ok_lo_hi_hi = cat(entries[0][5].u, entries[0][4].u) node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries[0][3].u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo) node priv_x_ok_hi_lo_hi = cat(entries[0][8].u, entries[0][7].u) node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries[0][6].u) node priv_x_ok_hi_hi_lo = cat(entries[0][10].u, entries[0][9].u) node priv_x_ok_hi_hi_hi = cat(entries[0][12].u, entries[0][11].u) node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_lo_hi_1 = cat(entries[0][2].u, entries[0][1].u) node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries[0][0].u) node priv_x_ok_lo_hi_hi_1 = cat(entries[0][5].u, entries[0][4].u) node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries[0][3].u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1) node priv_x_ok_hi_lo_hi_1 = cat(entries[0][8].u, entries[0][7].u) node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries[0][6].u) node priv_x_ok_hi_hi_lo_1 = cat(entries[0][10].u, entries[0][9].u) node priv_x_ok_hi_hi_hi_1 = cat(entries[0][12].u, entries[0][11].u) node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node _priv_x_ok_T_3 = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) wire priv_x_ok : UInt<13>[1] connect priv_x_ok[0], _priv_x_ok_T_3 node r_array_lo_lo_hi = cat(entries[0][2].sr, entries[0][1].sr) node r_array_lo_lo = cat(r_array_lo_lo_hi, entries[0][0].sr) node r_array_lo_hi_hi = cat(entries[0][5].sr, entries[0][4].sr) node r_array_lo_hi = cat(r_array_lo_hi_hi, entries[0][3].sr) node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo) node r_array_hi_lo_hi = cat(entries[0][8].sr, entries[0][7].sr) node r_array_hi_lo = cat(r_array_hi_lo_hi, entries[0][6].sr) node r_array_hi_hi_lo = cat(entries[0][10].sr, entries[0][9].sr) node r_array_hi_hi_hi = cat(entries[0][12].sr, entries[0][11].sr) node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo) node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_lo_hi_1 = cat(entries[0][2].sx, entries[0][1].sx) node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries[0][0].sx) node r_array_lo_hi_hi_1 = cat(entries[0][5].sx, entries[0][4].sx) node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries[0][3].sx) node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1) node r_array_hi_lo_hi_1 = cat(entries[0][8].sx, entries[0][7].sx) node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries[0][6].sx) node r_array_hi_hi_lo_1 = cat(entries[0][10].sx, entries[0][9].sx) node r_array_hi_hi_hi_1 = cat(entries[0][12].sx, entries[0][11].sx) node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1) node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(io.ptw.status.mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok[0], _r_array_T_3) node _r_array_T_5 = cat(UInt<1>(0h1), _r_array_T_4) wire r_array : UInt<14>[1] connect r_array[0], _r_array_T_5 node w_array_lo_lo_hi = cat(entries[0][2].sw, entries[0][1].sw) node w_array_lo_lo = cat(w_array_lo_lo_hi, entries[0][0].sw) node w_array_lo_hi_hi = cat(entries[0][5].sw, entries[0][4].sw) node w_array_lo_hi = cat(w_array_lo_hi_hi, entries[0][3].sw) node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo) node w_array_hi_lo_hi = cat(entries[0][8].sw, entries[0][7].sw) node w_array_hi_lo = cat(w_array_hi_lo_hi, entries[0][6].sw) node w_array_hi_hi_lo = cat(entries[0][10].sw, entries[0][9].sw) node w_array_hi_hi_hi = cat(entries[0][12].sw, entries[0][11].sw) node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo) node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok[0], _w_array_T) node _w_array_T_2 = cat(UInt<1>(0h1), _w_array_T_1) wire w_array : UInt<14>[1] connect w_array[0], _w_array_T_2 node x_array_lo_lo_hi = cat(entries[0][2].sx, entries[0][1].sx) node x_array_lo_lo = cat(x_array_lo_lo_hi, entries[0][0].sx) node x_array_lo_hi_hi = cat(entries[0][5].sx, entries[0][4].sx) node x_array_lo_hi = cat(x_array_lo_hi_hi, entries[0][3].sx) node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo) node x_array_hi_lo_hi = cat(entries[0][8].sx, entries[0][7].sx) node x_array_hi_lo = cat(x_array_hi_lo_hi, entries[0][6].sx) node x_array_hi_hi_lo = cat(entries[0][10].sx, entries[0][9].sx) node x_array_hi_hi_hi = cat(entries[0][12].sx, entries[0][11].sx) node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo) node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok[0], _x_array_T) node _x_array_T_2 = cat(UInt<1>(0h1), _x_array_T_1) wire x_array : UInt<14>[1] connect x_array[0], _x_array_T_2 node _pr_array_T = mux(prot_r[0], UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo_lo_hi = cat(normal_entries[0][2].pr, normal_entries[0][1].pr) node pr_array_lo_lo = cat(pr_array_lo_lo_hi, normal_entries[0][0].pr) node pr_array_lo_hi_hi = cat(normal_entries[0][5].pr, normal_entries[0][4].pr) node pr_array_lo_hi = cat(pr_array_lo_hi_hi, normal_entries[0][3].pr) node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo) node pr_array_hi_lo_hi = cat(normal_entries[0][8].pr, normal_entries[0][7].pr) node pr_array_hi_lo = cat(pr_array_hi_lo_hi, normal_entries[0][6].pr) node pr_array_hi_hi_hi = cat(normal_entries[0][11].pr, normal_entries[0][10].pr) node pr_array_hi_hi = cat(pr_array_hi_hi_hi, normal_entries[0][9].pr) node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = not(ptw_ae_array[0]) node _pr_array_T_4 = and(_pr_array_T_2, _pr_array_T_3) wire pr_array : UInt<14>[1] connect pr_array[0], _pr_array_T_4 node _pw_array_T = mux(prot_w[0], UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo_lo_hi = cat(normal_entries[0][2].pw, normal_entries[0][1].pw) node pw_array_lo_lo = cat(pw_array_lo_lo_hi, normal_entries[0][0].pw) node pw_array_lo_hi_hi = cat(normal_entries[0][5].pw, normal_entries[0][4].pw) node pw_array_lo_hi = cat(pw_array_lo_hi_hi, normal_entries[0][3].pw) node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo) node pw_array_hi_lo_hi = cat(normal_entries[0][8].pw, normal_entries[0][7].pw) node pw_array_hi_lo = cat(pw_array_hi_lo_hi, normal_entries[0][6].pw) node pw_array_hi_hi_hi = cat(normal_entries[0][11].pw, normal_entries[0][10].pw) node pw_array_hi_hi = cat(pw_array_hi_hi_hi, normal_entries[0][9].pw) node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = not(ptw_ae_array[0]) node _pw_array_T_4 = and(_pw_array_T_2, _pw_array_T_3) wire pw_array : UInt<14>[1] connect pw_array[0], _pw_array_T_4 node _px_array_T = mux(prot_x[0], UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo_lo_hi = cat(normal_entries[0][2].px, normal_entries[0][1].px) node px_array_lo_lo = cat(px_array_lo_lo_hi, normal_entries[0][0].px) node px_array_lo_hi_hi = cat(normal_entries[0][5].px, normal_entries[0][4].px) node px_array_lo_hi = cat(px_array_lo_hi_hi, normal_entries[0][3].px) node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo) node px_array_hi_lo_hi = cat(normal_entries[0][8].px, normal_entries[0][7].px) node px_array_hi_lo = cat(px_array_hi_lo_hi, normal_entries[0][6].px) node px_array_hi_hi_hi = cat(normal_entries[0][11].px, normal_entries[0][10].px) node px_array_hi_hi = cat(px_array_hi_hi_hi, normal_entries[0][9].px) node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = not(ptw_ae_array[0]) node _px_array_T_4 = and(_px_array_T_2, _px_array_T_3) wire px_array : UInt<14>[1] connect px_array[0], _px_array_T_4 node _eff_array_T = mux(prot_eff[0], UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo_lo_hi = cat(normal_entries[0][2].eff, normal_entries[0][1].eff) node eff_array_lo_lo = cat(eff_array_lo_lo_hi, normal_entries[0][0].eff) node eff_array_lo_hi_hi = cat(normal_entries[0][5].eff, normal_entries[0][4].eff) node eff_array_lo_hi = cat(eff_array_lo_hi_hi, normal_entries[0][3].eff) node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo) node eff_array_hi_lo_hi = cat(normal_entries[0][8].eff, normal_entries[0][7].eff) node eff_array_hi_lo = cat(eff_array_hi_lo_hi, normal_entries[0][6].eff) node eff_array_hi_hi_hi = cat(normal_entries[0][11].eff, normal_entries[0][10].eff) node eff_array_hi_hi = cat(eff_array_hi_hi_hi, normal_entries[0][9].eff) node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node _eff_array_T_2 = cat(_eff_array_T, _eff_array_T_1) wire eff_array : UInt<14>[1] connect eff_array[0], _eff_array_T_2 node _c_array_T = mux(cacheable[0], UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo_lo_hi = cat(normal_entries[0][2].c, normal_entries[0][1].c) node c_array_lo_lo = cat(c_array_lo_lo_hi, normal_entries[0][0].c) node c_array_lo_hi_hi = cat(normal_entries[0][5].c, normal_entries[0][4].c) node c_array_lo_hi = cat(c_array_lo_hi_hi, normal_entries[0][3].c) node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo) node c_array_hi_lo_hi = cat(normal_entries[0][8].c, normal_entries[0][7].c) node c_array_hi_lo = cat(c_array_hi_lo_hi, normal_entries[0][6].c) node c_array_hi_hi_hi = cat(normal_entries[0][11].c, normal_entries[0][10].c) node c_array_hi_hi = cat(c_array_hi_hi_hi, normal_entries[0][9].c) node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node _c_array_T_2 = cat(_c_array_T, _c_array_T_1) wire c_array : UInt<14>[1] connect c_array[0], _c_array_T_2 node _paa_array_T = mux(prot_aa[0], UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo_lo_hi = cat(normal_entries[0][2].paa, normal_entries[0][1].paa) node paa_array_lo_lo = cat(paa_array_lo_lo_hi, normal_entries[0][0].paa) node paa_array_lo_hi_hi = cat(normal_entries[0][5].paa, normal_entries[0][4].paa) node paa_array_lo_hi = cat(paa_array_lo_hi_hi, normal_entries[0][3].paa) node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo) node paa_array_hi_lo_hi = cat(normal_entries[0][8].paa, normal_entries[0][7].paa) node paa_array_hi_lo = cat(paa_array_hi_lo_hi, normal_entries[0][6].paa) node paa_array_hi_hi_hi = cat(normal_entries[0][11].paa, normal_entries[0][10].paa) node paa_array_hi_hi = cat(paa_array_hi_hi_hi, normal_entries[0][9].paa) node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node _paa_array_T_2 = cat(_paa_array_T, _paa_array_T_1) wire paa_array : UInt<14>[1] connect paa_array[0], _paa_array_T_2 node _pal_array_T = mux(prot_al[0], UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo_lo_hi = cat(normal_entries[0][2].pal, normal_entries[0][1].pal) node pal_array_lo_lo = cat(pal_array_lo_lo_hi, normal_entries[0][0].pal) node pal_array_lo_hi_hi = cat(normal_entries[0][5].pal, normal_entries[0][4].pal) node pal_array_lo_hi = cat(pal_array_lo_hi_hi, normal_entries[0][3].pal) node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo) node pal_array_hi_lo_hi = cat(normal_entries[0][8].pal, normal_entries[0][7].pal) node pal_array_hi_lo = cat(pal_array_hi_lo_hi, normal_entries[0][6].pal) node pal_array_hi_hi_hi = cat(normal_entries[0][11].pal, normal_entries[0][10].pal) node pal_array_hi_hi = cat(pal_array_hi_hi_hi, normal_entries[0][9].pal) node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node _pal_array_T_2 = cat(_pal_array_T, _pal_array_T_1) wire pal_array : UInt<14>[1] connect pal_array[0], _pal_array_T_2 node _paa_array_if_cached_T = mux(UInt<1>(0h1), c_array[0], UInt<1>(0h0)) node _paa_array_if_cached_T_1 = or(paa_array[0], _paa_array_if_cached_T) wire paa_array_if_cached : UInt<14>[1] connect paa_array_if_cached[0], _paa_array_if_cached_T_1 node _pal_array_if_cached_T = mux(UInt<1>(0h1), c_array[0], UInt<1>(0h0)) node _pal_array_if_cached_T_1 = or(pal_array[0], _pal_array_if_cached_T) wire pal_array_if_cached : UInt<14>[1] connect pal_array_if_cached[0], _pal_array_if_cached_T_1 node _prefetchable_array_T = and(cacheable[0], homogeneous[0]) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo_lo_hi = cat(normal_entries[0][2].c, normal_entries[0][1].c) node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, normal_entries[0][0].c) node prefetchable_array_lo_hi_hi = cat(normal_entries[0][5].c, normal_entries[0][4].c) node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, normal_entries[0][3].c) node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo) node prefetchable_array_hi_lo_hi = cat(normal_entries[0][8].c, normal_entries[0][7].c) node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, normal_entries[0][6].c) node prefetchable_array_hi_hi_hi = cat(normal_entries[0][11].c, normal_entries[0][10].c) node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, normal_entries[0][9].c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node _prefetchable_array_T_3 = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) wire prefetchable_array : UInt<14>[1] connect prefetchable_array[0], _prefetchable_array_T_3 node _misaligned_T = dshl(UInt<1>(0h1), io.req[0].bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req[0].bits.vaddr, _misaligned_T_2) node _misaligned_T_4 = orr(_misaligned_T_3) wire misaligned : UInt<1>[1] connect misaligned[0], _misaligned_T_4 wire bad_va : UInt<1>[1] connect bad_va[0], UInt<1>(0h0) node _cmd_lrsc_T = eq(io.req[0].bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req[0].bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node _cmd_lrsc_T_3 = and(UInt<1>(0h1), _cmd_lrsc_T_2) wire cmd_lrsc : UInt<1>[1] connect cmd_lrsc[0], _cmd_lrsc_T_3 node _cmd_amo_logical_T = eq(io.req[0].bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req[0].bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req[0].bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req[0].bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node _cmd_amo_logical_T_7 = and(UInt<1>(0h1), _cmd_amo_logical_T_6) wire cmd_amo_logical : UInt<1>[1] connect cmd_amo_logical[0], _cmd_amo_logical_T_7 node _cmd_amo_arithmetic_T = eq(io.req[0].bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req[0].bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req[0].bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req[0].bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req[0].bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node _cmd_amo_arithmetic_T_9 = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) wire cmd_amo_arithmetic : UInt<1>[1] connect cmd_amo_arithmetic[0], _cmd_amo_arithmetic_T_9 node _cmd_read_T = eq(io.req[0].bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req[0].bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req[0].bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req[0].bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req[0].bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req[0].bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req[0].bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req[0].bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req[0].bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req[0].bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req[0].bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req[0].bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req[0].bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node _cmd_read_T_24 = or(_cmd_read_T_6, _cmd_read_T_23) wire cmd_read : UInt<1>[1] connect cmd_read[0], _cmd_read_T_24 node _cmd_write_T = eq(io.req[0].bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req[0].bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req[0].bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req[0].bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req[0].bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req[0].bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req[0].bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req[0].bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req[0].bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req[0].bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req[0].bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req[0].bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node _cmd_write_T_22 = or(_cmd_write_T_4, _cmd_write_T_21) wire cmd_write : UInt<1>[1] connect cmd_write[0], _cmd_write_T_22 node _cmd_write_perms_T = eq(io.req[0].bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = and(UInt<1>(0h0), _cmd_write_perms_T) node _cmd_write_perms_T_2 = or(cmd_write[0], _cmd_write_perms_T_1) wire cmd_write_perms : UInt<1>[1] connect cmd_write_perms[0], _cmd_write_perms_T_2 node _lrscAllowed_T = mux(UInt<1>(0h0), UInt<1>(0h0), c_array[0]) wire lrscAllowed : UInt<14>[1] connect lrscAllowed[0], _lrscAllowed_T node _ae_array_T = mux(misaligned[0], eff_array[0], UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed[0]) node _ae_array_T_2 = mux(cmd_lrsc[0], _ae_array_T_1, UInt<1>(0h0)) node _ae_array_T_3 = or(_ae_array_T, _ae_array_T_2) wire ae_array : UInt<14>[1] connect ae_array[0], _ae_array_T_3 node _ae_valid_array_T = eq(do_refill, UInt<1>(0h0)) node _ae_valid_array_T_1 = cat(UInt<1>(0h1), _ae_valid_array_T) node _ae_valid_array_T_2 = mux(UInt<1>(0h1), UInt<12>(0hfff), UInt<12>(0h0)) node _ae_valid_array_T_3 = cat(_ae_valid_array_T_1, _ae_valid_array_T_2) wire ae_valid_array : UInt<14>[1] connect ae_valid_array[0], _ae_valid_array_T_3 node _ae_ld_array_T = not(pr_array[0]) node _ae_ld_array_T_1 = or(ae_array[0], _ae_ld_array_T) node _ae_ld_array_T_2 = mux(cmd_read[0], _ae_ld_array_T_1, UInt<1>(0h0)) wire ae_ld_array : UInt<14>[1] connect ae_ld_array[0], _ae_ld_array_T_2 node _ae_st_array_T = not(pw_array[0]) node _ae_st_array_T_1 = or(ae_array[0], _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms[0], _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(pal_array_if_cached[0]) node _ae_st_array_T_4 = mux(cmd_amo_logical[0], _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(paa_array_if_cached[0]) node _ae_st_array_T_7 = mux(cmd_amo_arithmetic[0], _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) wire ae_st_array : UInt<14>[1] connect ae_st_array[0], _ae_st_array_T_8 node _must_alloc_array_T = not(paa_array[0]) node _must_alloc_array_T_1 = mux(cmd_amo_logical[0], _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array[0]) node _must_alloc_array_T_3 = mux(cmd_amo_arithmetic[0], _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(UInt<14>(0h0)) node _must_alloc_array_T_6 = mux(cmd_lrsc[0], _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) wire must_alloc_array : UInt<14>[1] connect must_alloc_array[0], _must_alloc_array_T_7 node _ma_ld_array_T = and(misaligned[0], cmd_read[0]) node _ma_ld_array_T_1 = not(eff_array[0]) node _ma_ld_array_T_2 = mux(_ma_ld_array_T, _ma_ld_array_T_1, UInt<1>(0h0)) wire ma_ld_array : UInt<14>[1] connect ma_ld_array[0], _ma_ld_array_T_2 node _ma_st_array_T = and(misaligned[0], cmd_write[0]) node _ma_st_array_T_1 = not(eff_array[0]) node _ma_st_array_T_2 = mux(_ma_st_array_T, _ma_st_array_T_1, UInt<1>(0h0)) wire ma_st_array : UInt<14>[1] connect ma_st_array[0], _ma_st_array_T_2 node _pf_ld_array_T = or(r_array[0], ptw_ae_array[0]) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = mux(cmd_read[0], _pf_ld_array_T_1, UInt<1>(0h0)) wire pf_ld_array : UInt<14>[1] connect pf_ld_array[0], _pf_ld_array_T_2 node _pf_st_array_T = or(w_array[0], ptw_ae_array[0]) node _pf_st_array_T_1 = not(_pf_st_array_T) node _pf_st_array_T_2 = mux(cmd_write_perms[0], _pf_st_array_T_1, UInt<1>(0h0)) wire pf_st_array : UInt<14>[1] connect pf_st_array[0], _pf_st_array_T_2 node _pf_inst_array_T = or(x_array[0], ptw_ae_array[0]) node _pf_inst_array_T_1 = not(_pf_inst_array_T) wire pf_inst_array : UInt<14>[1] connect pf_inst_array[0], _pf_inst_array_T_1 node _tlb_hit_T = orr(real_hits[0]) wire tlb_hit : UInt<1>[1] connect tlb_hit[0], _tlb_hit_T node _tlb_miss_T = eq(bad_va[0], UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled[0], _tlb_miss_T) node _tlb_miss_T_2 = eq(tlb_hit[0], UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) wire tlb_miss : UInt<1>[1] connect tlb_miss[0], _tlb_miss_T_3 regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0) regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _T_23 = and(io.req[0].valid, vm_enabled[0]) when _T_23 : node _T_24 = or(sector_hits[0][0], sector_hits[0][1]) node _T_25 = or(_T_24, sector_hits[0][2]) node _T_26 = or(_T_25, sector_hits[0][3]) node _T_27 = or(_T_26, sector_hits[0][4]) node _T_28 = or(_T_27, sector_hits[0][5]) node _T_29 = or(_T_28, sector_hits[0][6]) node _T_30 = or(_T_29, sector_hits[0][7]) when _T_30 : node lo_lo = cat(sector_hits[0][1], sector_hits[0][0]) node lo_hi = cat(sector_hits[0][3], sector_hits[0][2]) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(sector_hits[0][5], sector_hits[0][4]) node hi_hi = cat(sector_hits[0][7], sector_hits[0][6]) node hi = cat(hi_hi, hi_lo) node _T_31 = cat(hi, lo) node hi_1 = bits(_T_31, 7, 4) node lo_1 = bits(_T_31, 3, 0) node _T_32 = orr(hi_1) node _T_33 = or(hi_1, lo_1) node hi_2 = bits(_T_33, 3, 2) node lo_2 = bits(_T_33, 1, 0) node _T_34 = orr(hi_2) node _T_35 = or(hi_2, lo_2) node _T_36 = bits(_T_35, 1, 1) node _T_37 = cat(_T_34, _T_36) node _T_38 = cat(_T_32, _T_37) node state_reg_touch_way_sized = bits(_T_38, 2, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 2, 2) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg, 5, 3) node state_reg_right_subtree_state = bits(state_reg, 2, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 1, 0) node _state_reg_set_left_older_T_1 = bits(_state_reg_T, 1, 1) node state_reg_set_left_older_1 = eq(_state_reg_set_left_older_T_1, UInt<1>(0h0)) node state_reg_left_subtree_state_1 = bits(state_reg_left_subtree_state, 1, 1) node state_reg_right_subtree_state_1 = bits(state_reg_left_subtree_state, 0, 0) node _state_reg_T_1 = bits(_state_reg_T, 0, 0) node _state_reg_T_2 = bits(_state_reg_T_1, 0, 0) node _state_reg_T_3 = eq(_state_reg_T_2, UInt<1>(0h0)) node _state_reg_T_4 = mux(state_reg_set_left_older_1, state_reg_left_subtree_state_1, _state_reg_T_3) node _state_reg_T_5 = bits(_state_reg_T, 0, 0) node _state_reg_T_6 = bits(_state_reg_T_5, 0, 0) node _state_reg_T_7 = eq(_state_reg_T_6, UInt<1>(0h0)) node _state_reg_T_8 = mux(state_reg_set_left_older_1, _state_reg_T_7, state_reg_right_subtree_state_1) node state_reg_hi = cat(state_reg_set_left_older_1, _state_reg_T_4) node _state_reg_T_9 = cat(state_reg_hi, _state_reg_T_8) node _state_reg_T_10 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_9) node _state_reg_T_11 = bits(state_reg_touch_way_sized, 1, 0) node _state_reg_set_left_older_T_2 = bits(_state_reg_T_11, 1, 1) node state_reg_set_left_older_2 = eq(_state_reg_set_left_older_T_2, UInt<1>(0h0)) node state_reg_left_subtree_state_2 = bits(state_reg_right_subtree_state, 1, 1) node state_reg_right_subtree_state_2 = bits(state_reg_right_subtree_state, 0, 0) node _state_reg_T_12 = bits(_state_reg_T_11, 0, 0) node _state_reg_T_13 = bits(_state_reg_T_12, 0, 0) node _state_reg_T_14 = eq(_state_reg_T_13, UInt<1>(0h0)) node _state_reg_T_15 = mux(state_reg_set_left_older_2, state_reg_left_subtree_state_2, _state_reg_T_14) node _state_reg_T_16 = bits(_state_reg_T_11, 0, 0) node _state_reg_T_17 = bits(_state_reg_T_16, 0, 0) node _state_reg_T_18 = eq(_state_reg_T_17, UInt<1>(0h0)) node _state_reg_T_19 = mux(state_reg_set_left_older_2, _state_reg_T_18, state_reg_right_subtree_state_2) node state_reg_hi_1 = cat(state_reg_set_left_older_2, _state_reg_T_15) node _state_reg_T_20 = cat(state_reg_hi_1, _state_reg_T_19) node _state_reg_T_21 = mux(state_reg_set_left_older, _state_reg_T_20, state_reg_right_subtree_state) node state_reg_hi_2 = cat(state_reg_set_left_older, _state_reg_T_10) node _state_reg_T_22 = cat(state_reg_hi_2, _state_reg_T_21) connect state_reg, _state_reg_T_22 node _T_39 = or(superpage_hits[0][0], superpage_hits[0][1]) node _T_40 = or(_T_39, superpage_hits[0][2]) node _T_41 = or(_T_40, superpage_hits[0][3]) when _T_41 : node lo_3 = cat(superpage_hits[0][1], superpage_hits[0][0]) node hi_3 = cat(superpage_hits[0][3], superpage_hits[0][2]) node _T_42 = cat(hi_3, lo_3) node hi_4 = bits(_T_42, 3, 2) node lo_4 = bits(_T_42, 1, 0) node _T_43 = orr(hi_4) node _T_44 = or(hi_4, lo_4) node _T_45 = bits(_T_44, 1, 1) node _T_46 = cat(_T_43, _T_45) node state_reg_touch_way_sized_1 = bits(_T_46, 1, 0) node _state_reg_set_left_older_T_3 = bits(state_reg_touch_way_sized_1, 1, 1) node state_reg_set_left_older_3 = eq(_state_reg_set_left_older_T_3, UInt<1>(0h0)) node state_reg_left_subtree_state_3 = bits(state_reg_1, 1, 1) node state_reg_right_subtree_state_3 = bits(state_reg_1, 0, 0) node _state_reg_T_23 = bits(state_reg_touch_way_sized_1, 0, 0) node _state_reg_T_24 = bits(_state_reg_T_23, 0, 0) node _state_reg_T_25 = eq(_state_reg_T_24, UInt<1>(0h0)) node _state_reg_T_26 = mux(state_reg_set_left_older_3, state_reg_left_subtree_state_3, _state_reg_T_25) node _state_reg_T_27 = bits(state_reg_touch_way_sized_1, 0, 0) node _state_reg_T_28 = bits(_state_reg_T_27, 0, 0) node _state_reg_T_29 = eq(_state_reg_T_28, UInt<1>(0h0)) node _state_reg_T_30 = mux(state_reg_set_left_older_3, _state_reg_T_29, state_reg_right_subtree_state_3) node state_reg_hi_3 = cat(state_reg_set_left_older_3, _state_reg_T_26) node _state_reg_T_31 = cat(state_reg_hi_3, _state_reg_T_30) connect state_reg_1, _state_reg_T_31 node _multipleHits_T = bits(real_hits[0], 5, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0) node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0) node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1) node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0) node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9) node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3) node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0) node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1) node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0) node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18) node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20) node _multipleHits_T_21 = bits(real_hits[0], 12, 6) node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0) node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0) node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0) node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1) node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0) node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0) node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1) node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0) node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5) node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5) node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28) node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6) node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3) node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6) node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30) node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3) node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0) node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0) node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0) node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1) node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0) node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7) node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7) node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36) node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2) node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0) node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0) node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1) node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0) node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8) node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8) node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41) node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9) node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4) node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9) node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43) node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10) node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5) node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10) node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45) node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11) node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6) node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11) node _multipleHits_T_49 = or(_multipleHits_T_47, _multipleHits_T_48) wire multipleHits : UInt<1>[1] connect multipleHits[0], _multipleHits_T_49 node _io_miss_rdy_T = eq(state, UInt<2>(0h0)) connect io.miss_rdy, _io_miss_rdy_T connect io.req[0].ready, UInt<1>(0h1) invalidate io.resp[0].gpa invalidate io.resp[0].gpa_is_pte connect io.resp[0].gf.ld, UInt<1>(0h0) connect io.resp[0].gf.st, UInt<1>(0h0) connect io.resp[0].gf.inst, UInt<1>(0h0) node _io_resp_0_pf_ld_T = and(bad_va[0], cmd_read[0]) node _io_resp_0_pf_ld_T_1 = and(pf_ld_array[0], hits[0]) node _io_resp_0_pf_ld_T_2 = orr(_io_resp_0_pf_ld_T_1) node _io_resp_0_pf_ld_T_3 = or(_io_resp_0_pf_ld_T, _io_resp_0_pf_ld_T_2) connect io.resp[0].pf.ld, _io_resp_0_pf_ld_T_3 node _io_resp_0_pf_st_T = and(bad_va[0], cmd_write_perms[0]) node _io_resp_0_pf_st_T_1 = and(pf_st_array[0], hits[0]) node _io_resp_0_pf_st_T_2 = orr(_io_resp_0_pf_st_T_1) node _io_resp_0_pf_st_T_3 = or(_io_resp_0_pf_st_T, _io_resp_0_pf_st_T_2) connect io.resp[0].pf.st, _io_resp_0_pf_st_T_3 node _io_resp_0_pf_inst_T = and(pf_inst_array[0], hits[0]) node _io_resp_0_pf_inst_T_1 = orr(_io_resp_0_pf_inst_T) node _io_resp_0_pf_inst_T_2 = or(bad_va[0], _io_resp_0_pf_inst_T_1) connect io.resp[0].pf.inst, _io_resp_0_pf_inst_T_2 node _io_resp_0_ae_ld_T = and(ae_valid_array[0], ae_ld_array[0]) node _io_resp_0_ae_ld_T_1 = and(_io_resp_0_ae_ld_T, hits[0]) node _io_resp_0_ae_ld_T_2 = orr(_io_resp_0_ae_ld_T_1) connect io.resp[0].ae.ld, _io_resp_0_ae_ld_T_2 node _io_resp_0_ae_st_T = and(ae_valid_array[0], ae_st_array[0]) node _io_resp_0_ae_st_T_1 = and(_io_resp_0_ae_st_T, hits[0]) node _io_resp_0_ae_st_T_2 = orr(_io_resp_0_ae_st_T_1) connect io.resp[0].ae.st, _io_resp_0_ae_st_T_2 node _io_resp_0_ae_inst_T = not(px_array[0]) node _io_resp_0_ae_inst_T_1 = and(ae_valid_array[0], _io_resp_0_ae_inst_T) node _io_resp_0_ae_inst_T_2 = and(_io_resp_0_ae_inst_T_1, hits[0]) node _io_resp_0_ae_inst_T_3 = orr(_io_resp_0_ae_inst_T_2) connect io.resp[0].ae.inst, _io_resp_0_ae_inst_T_3 node _io_resp_0_ma_ld_T = and(ma_ld_array[0], hits[0]) node _io_resp_0_ma_ld_T_1 = orr(_io_resp_0_ma_ld_T) connect io.resp[0].ma.ld, _io_resp_0_ma_ld_T_1 node _io_resp_0_ma_st_T = and(ma_st_array[0], hits[0]) node _io_resp_0_ma_st_T_1 = orr(_io_resp_0_ma_st_T) connect io.resp[0].ma.st, _io_resp_0_ma_st_T_1 connect io.resp[0].ma.inst, UInt<1>(0h0) node _io_resp_0_cacheable_T = and(c_array[0], hits[0]) node _io_resp_0_cacheable_T_1 = orr(_io_resp_0_cacheable_T) connect io.resp[0].cacheable, _io_resp_0_cacheable_T_1 node _io_resp_0_must_alloc_T = and(must_alloc_array[0], hits[0]) node _io_resp_0_must_alloc_T_1 = orr(_io_resp_0_must_alloc_T) connect io.resp[0].must_alloc, _io_resp_0_must_alloc_T_1 node _io_resp_0_prefetchable_T = and(prefetchable_array[0], hits[0]) node _io_resp_0_prefetchable_T_1 = orr(_io_resp_0_prefetchable_T) node _io_resp_0_prefetchable_T_2 = and(_io_resp_0_prefetchable_T_1, UInt<1>(0h1)) connect io.resp[0].prefetchable, _io_resp_0_prefetchable_T_2 node _io_resp_0_miss_T = or(do_refill, tlb_miss[0]) node _io_resp_0_miss_T_1 = or(_io_resp_0_miss_T, multipleHits[0]) connect io.resp[0].miss, _io_resp_0_miss_T_1 node _io_resp_0_paddr_T = bits(io.req[0].bits.vaddr, 11, 0) node _io_resp_0_paddr_T_1 = cat(ppn[0], _io_resp_0_paddr_T) connect io.resp[0].paddr, _io_resp_0_paddr_T_1 connect io.resp[0].size, io.req[0].bits.size connect io.resp[0].cmd, io.req[0].bits.cmd invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T invalidate io.ptw.req.bits.bits.stage2 invalidate io.ptw.req.bits.bits.vstage1 invalidate io.ptw.req.bits.bits.need_gpa invalidate io.ptw.req.bits.bits.addr invalidate io.ptw.req.bits.valid node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag
module NBDTLB( // @[tlb.scala:17:7] input clock, // @[tlb.scala:17:7] input reset, // @[tlb.scala:17:7] input io_req_0_valid, // @[tlb.scala:19:14] input [33:0] io_req_0_bits_vaddr, // @[tlb.scala:19:14] input [1:0] io_req_0_bits_size, // @[tlb.scala:19:14] input [4:0] io_req_0_bits_cmd, // @[tlb.scala:19:14] output [31:0] io_resp_0_paddr, // @[tlb.scala:19:14] output io_resp_0_pf_ld, // @[tlb.scala:19:14] output io_resp_0_pf_st, // @[tlb.scala:19:14] output io_resp_0_ae_ld, // @[tlb.scala:19:14] output io_resp_0_ae_st, // @[tlb.scala:19:14] output io_resp_0_ma_ld, // @[tlb.scala:19:14] output io_resp_0_ma_st, // @[tlb.scala:19:14] output io_resp_0_cacheable, // @[tlb.scala:19:14] output [20:0] io_ptw_req_bits_bits_addr, // @[tlb.scala:19:14] input io_ptw_resp_valid, // @[tlb.scala:19:14] input [43:0] io_ptw_resp_bits_pte_ppn // @[tlb.scala:19:14] ); wire _normal_entries_WIRE_24_11_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_11_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_11_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_11_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_11_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_11_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_11_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_11_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_11_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_11_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_11_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_11_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_11_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_11_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_24_11_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_10_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_10_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_10_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_10_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_10_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_10_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_10_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_10_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_10_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_10_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_10_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_10_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_10_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_10_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_24_10_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_9_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_9_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_9_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_9_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_9_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_9_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_9_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_9_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_9_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_9_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_9_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_9_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_9_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_9_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_24_9_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_8_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_8_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_8_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_8_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_8_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_8_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_8_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_8_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_8_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_8_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_8_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_8_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_8_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_8_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_24_8_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_7_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_7_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_7_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_7_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_7_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_7_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_7_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_7_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_7_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_7_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_7_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_7_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_7_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_7_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_24_7_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_6_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_6_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_6_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_6_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_6_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_6_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_6_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_6_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_6_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_6_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_6_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_6_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_6_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_6_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_24_6_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_5_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_5_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_5_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_5_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_5_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_5_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_5_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_5_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_5_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_5_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_5_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_5_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_5_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_5_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_24_5_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_4_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_4_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_4_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_4_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_4_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_4_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_4_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_4_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_4_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_4_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_4_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_4_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_4_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_4_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_24_4_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_3_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_3_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_3_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_3_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_3_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_3_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_3_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_3_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_3_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_3_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_3_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_3_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_3_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_3_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_24_3_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_2_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_2_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_2_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_2_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_2_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_2_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_2_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_2_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_2_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_2_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_2_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_2_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_2_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_2_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_24_2_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_1_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_1_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_1_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_1_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_1_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_1_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_1_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_1_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_1_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_1_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_1_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_1_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_1_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_1_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_24_1_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_0_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_0_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_0_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_0_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_0_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_0_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_0_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_0_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_0_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_0_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_0_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_0_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_0_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_24_0_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_24_0_ppn; // @[tlb.scala:212:45] wire _entries_WIRE_26_12_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_26_12_c; // @[tlb.scala:211:38] wire _entries_WIRE_26_12_eff; // @[tlb.scala:211:38] wire _entries_WIRE_26_12_paa; // @[tlb.scala:211:38] wire _entries_WIRE_26_12_pal; // @[tlb.scala:211:38] wire _entries_WIRE_26_12_pr; // @[tlb.scala:211:38] wire _entries_WIRE_26_12_px; // @[tlb.scala:211:38] wire _entries_WIRE_26_12_pw; // @[tlb.scala:211:38] wire _entries_WIRE_26_12_sr; // @[tlb.scala:211:38] wire _entries_WIRE_26_12_sx; // @[tlb.scala:211:38] wire _entries_WIRE_26_12_sw; // @[tlb.scala:211:38] wire _entries_WIRE_26_12_ae; // @[tlb.scala:211:38] wire _entries_WIRE_26_12_g; // @[tlb.scala:211:38] wire _entries_WIRE_26_12_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_26_12_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_26_11_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_26_11_c; // @[tlb.scala:211:38] wire _entries_WIRE_26_11_eff; // @[tlb.scala:211:38] wire _entries_WIRE_26_11_paa; // @[tlb.scala:211:38] wire _entries_WIRE_26_11_pal; // @[tlb.scala:211:38] wire _entries_WIRE_26_11_pr; // @[tlb.scala:211:38] wire _entries_WIRE_26_11_px; // @[tlb.scala:211:38] wire _entries_WIRE_26_11_pw; // @[tlb.scala:211:38] wire _entries_WIRE_26_11_sr; // @[tlb.scala:211:38] wire _entries_WIRE_26_11_sx; // @[tlb.scala:211:38] wire _entries_WIRE_26_11_sw; // @[tlb.scala:211:38] wire _entries_WIRE_26_11_ae; // @[tlb.scala:211:38] wire _entries_WIRE_26_11_g; // @[tlb.scala:211:38] wire _entries_WIRE_26_11_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_26_11_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_26_10_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_26_10_c; // @[tlb.scala:211:38] wire _entries_WIRE_26_10_eff; // @[tlb.scala:211:38] wire _entries_WIRE_26_10_paa; // @[tlb.scala:211:38] wire _entries_WIRE_26_10_pal; // @[tlb.scala:211:38] wire _entries_WIRE_26_10_pr; // @[tlb.scala:211:38] wire _entries_WIRE_26_10_px; // @[tlb.scala:211:38] wire _entries_WIRE_26_10_pw; // @[tlb.scala:211:38] wire _entries_WIRE_26_10_sr; // @[tlb.scala:211:38] wire _entries_WIRE_26_10_sx; // @[tlb.scala:211:38] wire _entries_WIRE_26_10_sw; // @[tlb.scala:211:38] wire _entries_WIRE_26_10_ae; // @[tlb.scala:211:38] wire _entries_WIRE_26_10_g; // @[tlb.scala:211:38] wire _entries_WIRE_26_10_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_26_10_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_26_9_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_26_9_c; // @[tlb.scala:211:38] wire _entries_WIRE_26_9_eff; // @[tlb.scala:211:38] wire _entries_WIRE_26_9_paa; // @[tlb.scala:211:38] wire _entries_WIRE_26_9_pal; // @[tlb.scala:211:38] wire _entries_WIRE_26_9_pr; // @[tlb.scala:211:38] wire _entries_WIRE_26_9_px; // @[tlb.scala:211:38] wire _entries_WIRE_26_9_pw; // @[tlb.scala:211:38] wire _entries_WIRE_26_9_sr; // @[tlb.scala:211:38] wire _entries_WIRE_26_9_sx; // @[tlb.scala:211:38] wire _entries_WIRE_26_9_sw; // @[tlb.scala:211:38] wire _entries_WIRE_26_9_ae; // @[tlb.scala:211:38] wire _entries_WIRE_26_9_g; // @[tlb.scala:211:38] wire _entries_WIRE_26_9_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_26_9_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_26_8_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_26_8_c; // @[tlb.scala:211:38] wire _entries_WIRE_26_8_eff; // @[tlb.scala:211:38] wire _entries_WIRE_26_8_paa; // @[tlb.scala:211:38] wire _entries_WIRE_26_8_pal; // @[tlb.scala:211:38] wire _entries_WIRE_26_8_pr; // @[tlb.scala:211:38] wire _entries_WIRE_26_8_px; // @[tlb.scala:211:38] wire _entries_WIRE_26_8_pw; // @[tlb.scala:211:38] wire _entries_WIRE_26_8_sr; // @[tlb.scala:211:38] wire _entries_WIRE_26_8_sx; // @[tlb.scala:211:38] wire _entries_WIRE_26_8_sw; // @[tlb.scala:211:38] wire _entries_WIRE_26_8_ae; // @[tlb.scala:211:38] wire _entries_WIRE_26_8_g; // @[tlb.scala:211:38] wire _entries_WIRE_26_8_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_26_8_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_26_7_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_26_7_c; // @[tlb.scala:211:38] wire _entries_WIRE_26_7_eff; // @[tlb.scala:211:38] wire _entries_WIRE_26_7_paa; // @[tlb.scala:211:38] wire _entries_WIRE_26_7_pal; // @[tlb.scala:211:38] wire _entries_WIRE_26_7_pr; // @[tlb.scala:211:38] wire _entries_WIRE_26_7_px; // @[tlb.scala:211:38] wire _entries_WIRE_26_7_pw; // @[tlb.scala:211:38] wire _entries_WIRE_26_7_sr; // @[tlb.scala:211:38] wire _entries_WIRE_26_7_sx; // @[tlb.scala:211:38] wire _entries_WIRE_26_7_sw; // @[tlb.scala:211:38] wire _entries_WIRE_26_7_ae; // @[tlb.scala:211:38] wire _entries_WIRE_26_7_g; // @[tlb.scala:211:38] wire _entries_WIRE_26_7_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_26_7_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_26_6_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_26_6_c; // @[tlb.scala:211:38] wire _entries_WIRE_26_6_eff; // @[tlb.scala:211:38] wire _entries_WIRE_26_6_paa; // @[tlb.scala:211:38] wire _entries_WIRE_26_6_pal; // @[tlb.scala:211:38] wire _entries_WIRE_26_6_pr; // @[tlb.scala:211:38] wire _entries_WIRE_26_6_px; // @[tlb.scala:211:38] wire _entries_WIRE_26_6_pw; // @[tlb.scala:211:38] wire _entries_WIRE_26_6_sr; // @[tlb.scala:211:38] wire _entries_WIRE_26_6_sx; // @[tlb.scala:211:38] wire _entries_WIRE_26_6_sw; // @[tlb.scala:211:38] wire _entries_WIRE_26_6_ae; // @[tlb.scala:211:38] wire _entries_WIRE_26_6_g; // @[tlb.scala:211:38] wire _entries_WIRE_26_6_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_26_6_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_26_5_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_26_5_c; // @[tlb.scala:211:38] wire _entries_WIRE_26_5_eff; // @[tlb.scala:211:38] wire _entries_WIRE_26_5_paa; // @[tlb.scala:211:38] wire _entries_WIRE_26_5_pal; // @[tlb.scala:211:38] wire _entries_WIRE_26_5_pr; // @[tlb.scala:211:38] wire _entries_WIRE_26_5_px; // @[tlb.scala:211:38] wire _entries_WIRE_26_5_pw; // @[tlb.scala:211:38] wire _entries_WIRE_26_5_sr; // @[tlb.scala:211:38] wire _entries_WIRE_26_5_sx; // @[tlb.scala:211:38] wire _entries_WIRE_26_5_sw; // @[tlb.scala:211:38] wire _entries_WIRE_26_5_ae; // @[tlb.scala:211:38] wire _entries_WIRE_26_5_g; // @[tlb.scala:211:38] wire _entries_WIRE_26_5_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_26_5_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_26_4_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_26_4_c; // @[tlb.scala:211:38] wire _entries_WIRE_26_4_eff; // @[tlb.scala:211:38] wire _entries_WIRE_26_4_paa; // @[tlb.scala:211:38] wire _entries_WIRE_26_4_pal; // @[tlb.scala:211:38] wire _entries_WIRE_26_4_pr; // @[tlb.scala:211:38] wire _entries_WIRE_26_4_px; // @[tlb.scala:211:38] wire _entries_WIRE_26_4_pw; // @[tlb.scala:211:38] wire _entries_WIRE_26_4_sr; // @[tlb.scala:211:38] wire _entries_WIRE_26_4_sx; // @[tlb.scala:211:38] wire _entries_WIRE_26_4_sw; // @[tlb.scala:211:38] wire _entries_WIRE_26_4_ae; // @[tlb.scala:211:38] wire _entries_WIRE_26_4_g; // @[tlb.scala:211:38] wire _entries_WIRE_26_4_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_26_4_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_26_3_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_26_3_c; // @[tlb.scala:211:38] wire _entries_WIRE_26_3_eff; // @[tlb.scala:211:38] wire _entries_WIRE_26_3_paa; // @[tlb.scala:211:38] wire _entries_WIRE_26_3_pal; // @[tlb.scala:211:38] wire _entries_WIRE_26_3_pr; // @[tlb.scala:211:38] wire _entries_WIRE_26_3_px; // @[tlb.scala:211:38] wire _entries_WIRE_26_3_pw; // @[tlb.scala:211:38] wire _entries_WIRE_26_3_sr; // @[tlb.scala:211:38] wire _entries_WIRE_26_3_sx; // @[tlb.scala:211:38] wire _entries_WIRE_26_3_sw; // @[tlb.scala:211:38] wire _entries_WIRE_26_3_ae; // @[tlb.scala:211:38] wire _entries_WIRE_26_3_g; // @[tlb.scala:211:38] wire _entries_WIRE_26_3_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_26_3_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_26_2_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_26_2_c; // @[tlb.scala:211:38] wire _entries_WIRE_26_2_eff; // @[tlb.scala:211:38] wire _entries_WIRE_26_2_paa; // @[tlb.scala:211:38] wire _entries_WIRE_26_2_pal; // @[tlb.scala:211:38] wire _entries_WIRE_26_2_pr; // @[tlb.scala:211:38] wire _entries_WIRE_26_2_px; // @[tlb.scala:211:38] wire _entries_WIRE_26_2_pw; // @[tlb.scala:211:38] wire _entries_WIRE_26_2_sr; // @[tlb.scala:211:38] wire _entries_WIRE_26_2_sx; // @[tlb.scala:211:38] wire _entries_WIRE_26_2_sw; // @[tlb.scala:211:38] wire _entries_WIRE_26_2_ae; // @[tlb.scala:211:38] wire _entries_WIRE_26_2_g; // @[tlb.scala:211:38] wire _entries_WIRE_26_2_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_26_2_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_26_1_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_26_1_c; // @[tlb.scala:211:38] wire _entries_WIRE_26_1_eff; // @[tlb.scala:211:38] wire _entries_WIRE_26_1_paa; // @[tlb.scala:211:38] wire _entries_WIRE_26_1_pal; // @[tlb.scala:211:38] wire _entries_WIRE_26_1_pr; // @[tlb.scala:211:38] wire _entries_WIRE_26_1_px; // @[tlb.scala:211:38] wire _entries_WIRE_26_1_pw; // @[tlb.scala:211:38] wire _entries_WIRE_26_1_sr; // @[tlb.scala:211:38] wire _entries_WIRE_26_1_sx; // @[tlb.scala:211:38] wire _entries_WIRE_26_1_sw; // @[tlb.scala:211:38] wire _entries_WIRE_26_1_ae; // @[tlb.scala:211:38] wire _entries_WIRE_26_1_g; // @[tlb.scala:211:38] wire _entries_WIRE_26_1_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_26_1_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_26_0_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_26_0_c; // @[tlb.scala:211:38] wire _entries_WIRE_26_0_eff; // @[tlb.scala:211:38] wire _entries_WIRE_26_0_paa; // @[tlb.scala:211:38] wire _entries_WIRE_26_0_pal; // @[tlb.scala:211:38] wire _entries_WIRE_26_0_pr; // @[tlb.scala:211:38] wire _entries_WIRE_26_0_px; // @[tlb.scala:211:38] wire _entries_WIRE_26_0_pw; // @[tlb.scala:211:38] wire _entries_WIRE_26_0_sr; // @[tlb.scala:211:38] wire _entries_WIRE_26_0_sx; // @[tlb.scala:211:38] wire _entries_WIRE_26_0_sw; // @[tlb.scala:211:38] wire _entries_WIRE_26_0_ae; // @[tlb.scala:211:38] wire _entries_WIRE_26_0_g; // @[tlb.scala:211:38] wire _entries_WIRE_26_0_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_26_0_ppn; // @[tlb.scala:211:38] wire io_req_0_valid_0 = io_req_0_valid; // @[tlb.scala:17:7] wire [33:0] io_req_0_bits_vaddr_0 = io_req_0_bits_vaddr; // @[tlb.scala:17:7] wire [1:0] io_req_0_bits_size_0 = io_req_0_bits_size; // @[tlb.scala:17:7] wire [4:0] io_req_0_bits_cmd_0 = io_req_0_bits_cmd; // @[tlb.scala:17:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[tlb.scala:17:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[tlb.scala:17:7] wire [20:0] io_ptw_req_bits_bits_addr_0 = 21'h0; // @[tlb.scala:17:7, :122:29] wire [11:0] _ae_valid_array_T_2 = 12'hFFF; // @[tlb.scala:255:9] wire [34:0] _prot_r_T_2 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _prot_r_T_3 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _prot_w_T_2 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _prot_w_T_3 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _prot_al_T_2 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _prot_al_T_3 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _prot_aa_T_2 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _prot_aa_T_3 = 35'h0; // @[Parameters.scala:137:46] wire [13:0] _hits_T_1 = 14'h2000; // @[tlb.scala:119:49, :173:31] wire [13:0] hits_0 = 14'h2000; // @[tlb.scala:119:49, :173:31] wire [19:0] _ppn_T_2 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_3 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_4 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_5 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_6 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_7 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_8 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_9 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_10 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_11 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_12 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_13 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_14 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_16 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_17 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_18 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_19 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_20 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_21 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_22 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_23 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_24 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_25 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_26 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_27 = 20'h0; // @[Mux.scala:30:73] wire [12:0] _real_hits_T = 13'h0; // @[tlb.scala:172:44] wire [12:0] real_hits_0 = 13'h0; // @[tlb.scala:119:49] wire [12:0] _priv_rw_ok_T_6 = 13'h0; // @[tlb.scala:215:108] wire [12:0] _r_array_T_2 = 13'h0; // @[tlb.scala:217:98] wire [1:0] _ae_valid_array_T_1 = 2'h3; // @[tlb.scala:254:84] wire [13:0] _ae_valid_array_T_3 = 14'h3FFF; // @[tlb.scala:254:41] wire [13:0] ae_valid_array_0 = 14'h3FFF; // @[tlb.scala:119:49] wire [13:0] _must_alloc_array_T_5 = 14'h3FFF; // @[tlb.scala:264:32] wire [6:0] real_hits_hi = 7'h0; // @[tlb.scala:172:44] wire [6:0] _multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_2_value = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_3_value = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[tlb.scala:17:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[tlb.scala:17:7, :19:14] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[Misc.scala:181:37] wire [5:0] real_hits_lo = 6'h0; // @[Misc.scala:181:37] wire [5:0] _multipleHits_T = 6'h0; // @[Misc.scala:181:37] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[tlb.scala:17:7, :19:14] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[tlb.scala:17:7, :19:14] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[tlb.scala:17:7, :19:14] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[tlb.scala:17:7, :19:14] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[tlb.scala:17:7, :19:14] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[tlb.scala:17:7, :19:14] wire [31:0] io_ptw_status_isa = 32'h0; // @[tlb.scala:17:7, :19:14] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[tlb.scala:17:7, :19:14] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[Misc.scala:182:39] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[Misc.scala:182:39] wire [3:0] real_hits_hi_hi = 4'h0; // @[Misc.scala:182:39] wire [3:0] _multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39] wire [43:0] io_ptw_ptbr_ppn = 44'h0; // @[tlb.scala:17:7, :19:14] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[tlb.scala:17:7, :19:14] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[tlb.scala:17:7, :19:14] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[tlb.scala:17:7, :19:14] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[tlb.scala:17:7, :19:14] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[tlb.scala:17:7, :19:14] wire [3:0] io_ptw_ptbr_mode = 4'h8; // @[tlb.scala:17:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future = 10'h0; // @[tlb.scala:17:7, :19:14] wire [32:0] io_sfence_bits_addr = 33'h0; // @[tlb.scala:17:7, :19:14] wire [32:0] io_ptw_resp_bits_gpa_bits = 33'h0; // @[tlb.scala:17:7, :19:14] wire [33:0] io_resp_0_gpa = 34'h0; // @[tlb.scala:17:7] wire [33:0] _mpu_ppn_data_WIRE_1 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _ppn_data_WIRE_1 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _ppn_data_WIRE_3 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _ppn_data_WIRE_5 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _ppn_data_WIRE_7 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _ppn_data_WIRE_9 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _ppn_data_WIRE_11 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _ppn_data_WIRE_13 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _ppn_data_WIRE_15 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _ppn_data_WIRE_17 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _ppn_data_WIRE_19 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _ppn_data_WIRE_21 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _ppn_data_WIRE_23 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _ppn_data_WIRE_25 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_1 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_3 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_5 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_7 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_9 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_11 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_13 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_15 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_17 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_19 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_21 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_23 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_25 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_1 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_3 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_5 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_7 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_9 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_11 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_13 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_15 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_17 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_19 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_21 = 34'h0; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_23 = 34'h0; // @[tlb.scala:58:79] wire [1:0] io_req_0_bits_prv = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_dprv = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_prv = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_sxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_uxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_fs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_mpp = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[tlb.scala:17:7] wire [1:0] _pmp_0_io_prv_T_2 = 2'h0; // @[tlb.scala:155:25] wire [1:0] real_hits_lo_lo_hi = 2'h0; // @[tlb.scala:172:44] wire [1:0] real_hits_lo_hi_hi = 2'h0; // @[tlb.scala:172:44] wire [1:0] real_hits_hi_lo_hi = 2'h0; // @[tlb.scala:172:44] wire [1:0] real_hits_hi_hi_lo = 2'h0; // @[tlb.scala:172:44] wire [1:0] real_hits_hi_hi_hi = 2'h0; // @[tlb.scala:172:44] wire [1:0] special_entry_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:95:26] wire [1:0] idx = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_0_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26] wire [1:0] idx_1 = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_1_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26] wire [1:0] idx_2 = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_2_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26] wire [1:0] idx_3 = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_3_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26] wire [1:0] idx_4 = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_4_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26] wire [1:0] idx_5 = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_5_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26] wire [1:0] idx_6 = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_6_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26] wire [1:0] idx_7 = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_7_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26] wire [1:0] _multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37] wire [1:0] _multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39] wire [1:0] io_ptw_resp_bits_level = 2'h2; // @[tlb.scala:17:7] wire [1:0] _special_entry_level_T = 2'h2; // @[package.scala:163:13] wire [1:0] special_entry_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26] wire [1:0] sectored_entries_2_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26] wire [1:0] sectored_entries_3_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26] wire [1:0] sectored_entries_4_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26] wire [1:0] sectored_entries_5_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26] wire [1:0] sectored_entries_6_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26] wire [1:0] sectored_entries_7_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26] wire [2:0] real_hits_lo_lo = 3'h0; // @[tlb.scala:172:44] wire [2:0] real_hits_lo_hi = 3'h0; // @[tlb.scala:172:44] wire [2:0] real_hits_hi_lo = 3'h0; // @[tlb.scala:172:44] wire [2:0] waddr = 3'h0; // @[tlb.scala:203:22] wire [2:0] state_reg_left_subtree_state = 3'h0; // @[package.scala:163:13] wire [2:0] state_reg_right_subtree_state = 3'h0; // @[Replacement.scala:198:38] wire [2:0] _multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37] wire [2:0] _multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39] wire [2:0] _multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37] wire io_req_0_ready = 1'h1; // @[tlb.scala:17:7] wire io_miss_rdy = 1'h1; // @[tlb.scala:17:7] wire io_ptw_req_ready = 1'h1; // @[tlb.scala:17:7] wire io_ptw_req_bits_valid = 1'h1; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_d = 1'h1; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_a = 1'h1; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_u = 1'h1; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_w = 1'h1; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_r = 1'h1; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_v = 1'h1; // @[tlb.scala:17:7] wire priv_uses_vm = 1'h1; // @[tlb.scala:138:27] wire _vm_enabled_T = 1'h1; // @[tlb.scala:139:63] wire _vm_enabled_T_3 = 1'h1; // @[tlb.scala:139:112] wire _homogeneous_T_24 = 1'h1; // @[TLBPermissions.scala:87:22] wire _homogeneous_T_25 = 1'h1; // @[TLBPermissions.scala:87:22] wire _homogeneous_T_39 = 1'h1; // @[TLBPermissions.scala:87:22] wire _homogeneous_T_40 = 1'h1; // @[TLBPermissions.scala:87:22] wire _prot_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _prot_w_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _prot_al_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _prot_aa_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _hits_T = 1'h1; // @[tlb.scala:173:32] wire _ppn_T = 1'h1; // @[tlb.scala:174:47] wire newEntry_u = 1'h1; // @[tlb.scala:179:24] wire newEntry_sw = 1'h1; // @[tlb.scala:179:24] wire newEntry_sr = 1'h1; // @[tlb.scala:179:24] wire _newEntry_sr_T_2 = 1'h1; // @[PTW.scala:141:38] wire _newEntry_sr_T_3 = 1'h1; // @[PTW.scala:141:32] wire _newEntry_sr_T_4 = 1'h1; // @[PTW.scala:141:52] wire _newEntry_sr_T_5 = 1'h1; // @[PTW.scala:149:35] wire _newEntry_sw_T_2 = 1'h1; // @[PTW.scala:141:38] wire _newEntry_sw_T_3 = 1'h1; // @[PTW.scala:141:32] wire _newEntry_sw_T_4 = 1'h1; // @[PTW.scala:141:52] wire _newEntry_sw_T_5 = 1'h1; // @[PTW.scala:151:35] wire _newEntry_sw_T_6 = 1'h1; // @[PTW.scala:151:40] wire _newEntry_sx_T_2 = 1'h1; // @[PTW.scala:141:38] wire _newEntry_sx_T_3 = 1'h1; // @[PTW.scala:141:32] wire _newEntry_sx_T_4 = 1'h1; // @[PTW.scala:141:52] wire _priv_rw_ok_T = 1'h1; // @[tlb.scala:215:40] wire _priv_rw_ok_T_1 = 1'h1; // @[tlb.scala:215:48] wire _ae_valid_array_T = 1'h1; // @[tlb.scala:254:118] wire _tlb_miss_T = 1'h1; // @[tlb.scala:272:49] wire _tlb_miss_T_2 = 1'h1; // @[tlb.scala:272:63] wire _io_miss_rdy_T = 1'h1; // @[tlb.scala:290:24] wire _io_ptw_req_bits_valid_T = 1'h1; // @[tlb.scala:319:28] wire io_req_0_bits_passthrough = 1'h0; // @[tlb.scala:17:7] wire io_req_0_bits_v = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_miss = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_gpa_is_pte = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_gf_ld = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_gf_st = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_gf_inst = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_ma_inst = 1'h0; // @[tlb.scala:17:7] wire io_sfence_valid = 1'h0; // @[tlb.scala:17:7] wire io_sfence_bits_rs1 = 1'h0; // @[tlb.scala:17:7] wire io_sfence_bits_rs2 = 1'h0; // @[tlb.scala:17:7] wire io_sfence_bits_asid = 1'h0; // @[tlb.scala:17:7] wire io_sfence_bits_hv = 1'h0; // @[tlb.scala:17:7] wire io_sfence_bits_hg = 1'h0; // @[tlb.scala:17:7] wire io_ptw_req_valid = 1'h0; // @[tlb.scala:17:7] wire io_ptw_req_bits_bits_need_gpa = 1'h0; // @[tlb.scala:17:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_ae_ptw = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_ae_final = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pf = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_gf = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_hr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_hw = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_hx = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_g = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_x = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_homogeneous = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_gpa_valid = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_gpa_is_pte = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_debug = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_cease = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_wfi = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_dv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_v = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_sd = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_mpv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_gva = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_mbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_sbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_tsr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_tw = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_tvm = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_mxr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_sum = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_mprv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_spp = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_mpie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_ube = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_spie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_upie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_mie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_hie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_sie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_uie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vtw = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_hu = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_spvp = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_spv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_gva = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_debug = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_cease = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_wfi = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_dv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_v = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sd = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mpv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_gva = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_tsr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_tw = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_tvm = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mxr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sum = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mprv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_spp = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mpie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_ube = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_spie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_upie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_hie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_uie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[tlb.scala:17:7] wire io_kill = 1'h0; // @[tlb.scala:17:7] wire priv_s = 1'h0; // @[tlb.scala:137:20] wire _vm_enabled_T_1 = 1'h0; // @[tlb.scala:139:44] wire _vm_enabled_T_2 = 1'h0; // @[tlb.scala:139:93] wire _vm_enabled_T_4 = 1'h0; // @[tlb.scala:139:109] wire vm_enabled_0 = 1'h0; // @[tlb.scala:119:49] wire do_refill = 1'h0; // @[tlb.scala:144:29] wire _invalidate_refill_T = 1'h0; // @[package.scala:16:47] wire _invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47] wire _invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59] wire invalidate_refill = 1'h0; // @[tlb.scala:145:88] wire _mpu_ppn_T = 1'h0; // @[tlb.scala:148:35] wire _pmp_0_io_prv_T = 1'h0; // @[tlb.scala:155:50] wire _pmp_0_io_prv_T_1 = 1'h0; // @[tlb.scala:155:36] wire _cacheable_T_10 = 1'h0; // @[Mux.scala:30:73] wire _prot_x_T_23 = 1'h0; // @[Mux.scala:30:73] wire _prot_eff_T_22 = 1'h0; // @[Mux.scala:30:73] wire _sector_hits_T = 1'h0; // @[package.scala:81:59] wire _sector_hits_T_7 = 1'h0; // @[package.scala:81:59] wire _sector_hits_T_14 = 1'h0; // @[package.scala:81:59] wire _sector_hits_T_21 = 1'h0; // @[package.scala:81:59] wire _sector_hits_T_28 = 1'h0; // @[package.scala:81:59] wire _sector_hits_T_35 = 1'h0; // @[package.scala:81:59] wire _sector_hits_T_42 = 1'h0; // @[package.scala:81:59] wire _sector_hits_T_49 = 1'h0; // @[package.scala:81:59] wire _superpage_hits_T_3 = 1'h0; // @[tlb.scala:72:20] wire _superpage_hits_T_7 = 1'h0; // @[tlb.scala:72:20] wire _superpage_hits_T_11 = 1'h0; // @[tlb.scala:72:20] wire _superpage_hits_T_15 = 1'h0; // @[tlb.scala:72:20] wire _hitsVec_T_3 = 1'h0; // @[tlb.scala:72:20] wire _hitsVec_T_4 = 1'h0; // @[tlb.scala:171:69] wire _hitsVec_T_8 = 1'h0; // @[tlb.scala:72:20] wire _hitsVec_T_9 = 1'h0; // @[tlb.scala:171:69] wire _hitsVec_T_13 = 1'h0; // @[tlb.scala:72:20] wire _hitsVec_T_14 = 1'h0; // @[tlb.scala:171:69] wire _hitsVec_T_18 = 1'h0; // @[tlb.scala:72:20] wire _hitsVec_T_19 = 1'h0; // @[tlb.scala:171:69] wire _hitsVec_T_23 = 1'h0; // @[tlb.scala:72:20] wire _hitsVec_T_24 = 1'h0; // @[tlb.scala:171:69] wire _hitsVec_T_28 = 1'h0; // @[tlb.scala:72:20] wire _hitsVec_T_29 = 1'h0; // @[tlb.scala:171:69] wire _hitsVec_T_33 = 1'h0; // @[tlb.scala:72:20] wire _hitsVec_T_34 = 1'h0; // @[tlb.scala:171:69] wire _hitsVec_T_38 = 1'h0; // @[tlb.scala:72:20] wire _hitsVec_T_39 = 1'h0; // @[tlb.scala:171:69] wire _hitsVec_T_43 = 1'h0; // @[tlb.scala:72:20] wire _hitsVec_T_44 = 1'h0; // @[tlb.scala:171:69] wire _hitsVec_T_48 = 1'h0; // @[tlb.scala:72:20] wire _hitsVec_T_49 = 1'h0; // @[tlb.scala:171:69] wire _hitsVec_T_53 = 1'h0; // @[tlb.scala:72:20] wire _hitsVec_T_54 = 1'h0; // @[tlb.scala:171:69] wire _hitsVec_T_58 = 1'h0; // @[tlb.scala:72:20] wire _hitsVec_T_59 = 1'h0; // @[tlb.scala:171:69] wire _hitsVec_T_64 = 1'h0; // @[tlb.scala:171:69] wire _hitsVec_WIRE_0 = 1'h0; // @[tlb.scala:171:38] wire _hitsVec_WIRE_1 = 1'h0; // @[tlb.scala:171:38] wire _hitsVec_WIRE_2 = 1'h0; // @[tlb.scala:171:38] wire _hitsVec_WIRE_3 = 1'h0; // @[tlb.scala:171:38] wire _hitsVec_WIRE_4 = 1'h0; // @[tlb.scala:171:38] wire _hitsVec_WIRE_5 = 1'h0; // @[tlb.scala:171:38] wire _hitsVec_WIRE_6 = 1'h0; // @[tlb.scala:171:38] wire _hitsVec_WIRE_7 = 1'h0; // @[tlb.scala:171:38] wire _hitsVec_WIRE_8 = 1'h0; // @[tlb.scala:171:38] wire _hitsVec_WIRE_9 = 1'h0; // @[tlb.scala:171:38] wire _hitsVec_WIRE_10 = 1'h0; // @[tlb.scala:171:38] wire _hitsVec_WIRE_11 = 1'h0; // @[tlb.scala:171:38] wire _hitsVec_WIRE_12 = 1'h0; // @[tlb.scala:171:38] wire hitsVec_0_0 = 1'h0; // @[tlb.scala:119:49] wire hitsVec_0_1 = 1'h0; // @[tlb.scala:119:49] wire hitsVec_0_2 = 1'h0; // @[tlb.scala:119:49] wire hitsVec_0_3 = 1'h0; // @[tlb.scala:119:49] wire hitsVec_0_4 = 1'h0; // @[tlb.scala:119:49] wire hitsVec_0_5 = 1'h0; // @[tlb.scala:119:49] wire hitsVec_0_6 = 1'h0; // @[tlb.scala:119:49] wire hitsVec_0_7 = 1'h0; // @[tlb.scala:119:49] wire hitsVec_0_8 = 1'h0; // @[tlb.scala:119:49] wire hitsVec_0_9 = 1'h0; // @[tlb.scala:119:49] wire hitsVec_0_10 = 1'h0; // @[tlb.scala:119:49] wire hitsVec_0_11 = 1'h0; // @[tlb.scala:119:49] wire hitsVec_0_12 = 1'h0; // @[tlb.scala:119:49] wire newEntry_g = 1'h0; // @[tlb.scala:179:24] wire newEntry_ae = 1'h0; // @[tlb.scala:179:24] wire newEntry_sx = 1'h0; // @[tlb.scala:179:24] wire newEntry_fragmented_superpage = 1'h0; // @[tlb.scala:179:24] wire _newEntry_sr_T = 1'h0; // @[PTW.scala:141:47] wire _newEntry_sr_T_1 = 1'h0; // @[PTW.scala:141:44] wire _newEntry_sw_T = 1'h0; // @[PTW.scala:141:47] wire _newEntry_sw_T_1 = 1'h0; // @[PTW.scala:141:44] wire _newEntry_sx_T = 1'h0; // @[PTW.scala:141:47] wire _newEntry_sx_T_1 = 1'h0; // @[PTW.scala:141:44] wire _newEntry_sx_T_5 = 1'h0; // @[PTW.scala:153:35] wire _superpage_entries_0_level_T = 1'h0; // @[package.scala:163:13] wire _superpage_entries_1_level_T = 1'h0; // @[package.scala:163:13] wire _superpage_entries_2_level_T = 1'h0; // @[package.scala:163:13] wire _superpage_entries_3_level_T = 1'h0; // @[package.scala:163:13] wire bad_va_0 = 1'h0; // @[tlb.scala:119:49] wire _cmd_write_perms_T_1 = 1'h0; // @[tlb.scala:248:29] wire _tlb_hit_T = 1'h0; // @[tlb.scala:271:44] wire tlb_hit_0 = 1'h0; // @[tlb.scala:119:49] wire _tlb_miss_T_1 = 1'h0; // @[tlb.scala:272:46] wire _tlb_miss_T_3 = 1'h0; // @[tlb.scala:272:60] wire tlb_miss_0 = 1'h0; // @[tlb.scala:119:49] wire state_reg_left_subtree_state_1 = 1'h0; // @[package.scala:163:13] wire state_reg_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38] wire state_reg_left_subtree_state_2 = 1'h0; // @[package.scala:163:13] wire state_reg_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38] wire state_reg_left_subtree_state_3 = 1'h0; // @[package.scala:163:13] wire state_reg_right_subtree_state_3 = 1'h0; // @[Replacement.scala:198:38] wire _multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39] wire multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18] wire multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49] wire multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49] wire _multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18] wire multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49] wire multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49] wire multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49] wire _multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39] wire multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18] wire multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49] wire multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49] wire _multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39] wire multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18] wire multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49] wire _multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39] wire multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18] wire multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49] wire multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49] wire multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49] wire _multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61] wire _multipleHits_T_49 = 1'h0; // @[Misc.scala:183:49] wire multipleHits_0 = 1'h0; // @[tlb.scala:119:49] wire _io_resp_0_pf_ld_T = 1'h0; // @[tlb.scala:298:38] wire _io_resp_0_pf_st_T = 1'h0; // @[tlb.scala:299:38] wire _io_resp_0_miss_T = 1'h0; // @[tlb.scala:310:35] wire _io_resp_0_miss_T_1 = 1'h0; // @[tlb.scala:310:50] wire _io_ptw_req_valid_T = 1'h0; // @[tlb.scala:317:29] wire [1:0] io_resp_0_size = io_req_0_bits_size_0; // @[tlb.scala:17:7] wire [4:0] io_resp_0_cmd = io_req_0_bits_cmd_0; // @[tlb.scala:17:7] wire [31:0] _io_resp_0_paddr_T_1; // @[tlb.scala:311:28] wire _io_resp_0_pf_ld_T_3; // @[tlb.scala:298:54] wire _io_resp_0_pf_st_T_3; // @[tlb.scala:299:61] wire _io_resp_0_pf_inst_T_2; // @[tlb.scala:300:37] wire _io_resp_0_ae_ld_T_2; // @[tlb.scala:301:74] wire _io_resp_0_ae_st_T_2; // @[tlb.scala:302:74] wire _io_resp_0_ae_inst_T_3; // @[tlb.scala:303:74] wire _io_resp_0_ma_ld_T_1; // @[tlb.scala:304:54] wire _io_resp_0_ma_st_T_1; // @[tlb.scala:305:54] wire _io_resp_0_cacheable_T_1; // @[tlb.scala:307:55] wire _io_resp_0_must_alloc_T_1; // @[tlb.scala:308:64] wire _io_resp_0_prefetchable_T_2; // @[tlb.scala:309:70] wire io_resp_0_pf_ld_0; // @[tlb.scala:17:7] wire io_resp_0_pf_st_0; // @[tlb.scala:17:7] wire io_resp_0_pf_inst; // @[tlb.scala:17:7] wire io_resp_0_ae_ld_0; // @[tlb.scala:17:7] wire io_resp_0_ae_st_0; // @[tlb.scala:17:7] wire io_resp_0_ae_inst; // @[tlb.scala:17:7] wire io_resp_0_ma_ld_0; // @[tlb.scala:17:7] wire io_resp_0_ma_st_0; // @[tlb.scala:17:7] wire [31:0] io_resp_0_paddr_0; // @[tlb.scala:17:7] wire io_resp_0_cacheable_0; // @[tlb.scala:17:7] wire io_resp_0_must_alloc; // @[tlb.scala:17:7] wire io_resp_0_prefetchable; // @[tlb.scala:17:7] wire [20:0] _vpn_T = io_req_0_bits_vaddr_0[32:12]; // @[tlb.scala:17:7, :142:47] wire [20:0] vpn_0 = _vpn_T; // @[tlb.scala:119:49, :142:47] wire [20:0] _sector_hits_T_3 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _sector_hits_T_10 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _sector_hits_T_17 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _sector_hits_T_24 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _sector_hits_T_31 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _sector_hits_T_38 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _sector_hits_T_45 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _sector_hits_T_52 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _superpage_hits_T = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _superpage_hits_T_4 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _superpage_hits_T_8 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _superpage_hits_T_12 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _hitsVec_T = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _hitsVec_T_5 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _hitsVec_T_10 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _hitsVec_T_15 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _hitsVec_T_20 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _hitsVec_T_25 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _hitsVec_T_30 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _hitsVec_T_35 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _hitsVec_T_40 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _hitsVec_T_45 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _hitsVec_T_50 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _hitsVec_T_55 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [20:0] _hitsVec_T_60 = vpn_0; // @[tlb.scala:60:43, :119:49] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[tlb.scala:17:7, :143:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[tlb.scala:17:7, :143:44, :179:24] wire [19:0] _mpu_ppn_data_T_14; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_13; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_12; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_11; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_10; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_9; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_8; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_7; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_6; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_5; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_4; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_3; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_2; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_1; // @[tlb.scala:58:79] wire _mpu_ppn_data_T; // @[tlb.scala:58:79] assign _mpu_ppn_data_T = _mpu_ppn_data_WIRE_1[0]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_fragmented_superpage = _mpu_ppn_data_T; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_1 = _mpu_ppn_data_WIRE_1[1]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_c = _mpu_ppn_data_T_1; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_2 = _mpu_ppn_data_WIRE_1[2]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_eff = _mpu_ppn_data_T_2; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_3 = _mpu_ppn_data_WIRE_1[3]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_paa = _mpu_ppn_data_T_3; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_4 = _mpu_ppn_data_WIRE_1[4]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_pal = _mpu_ppn_data_T_4; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_5 = _mpu_ppn_data_WIRE_1[5]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_pr = _mpu_ppn_data_T_5; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_6 = _mpu_ppn_data_WIRE_1[6]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_px = _mpu_ppn_data_T_6; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_7 = _mpu_ppn_data_WIRE_1[7]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_pw = _mpu_ppn_data_T_7; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_8 = _mpu_ppn_data_WIRE_1[8]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_sr = _mpu_ppn_data_T_8; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_9 = _mpu_ppn_data_WIRE_1[9]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_sx = _mpu_ppn_data_T_9; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_10 = _mpu_ppn_data_WIRE_1[10]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_sw = _mpu_ppn_data_T_10; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_11 = _mpu_ppn_data_WIRE_1[11]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_ae = _mpu_ppn_data_T_11; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_12 = _mpu_ppn_data_WIRE_1[12]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_g = _mpu_ppn_data_T_12; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_13 = _mpu_ppn_data_WIRE_1[13]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_u = _mpu_ppn_data_T_13; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_14 = _mpu_ppn_data_WIRE_1[33:14]; // @[tlb.scala:58:79] wire [19:0] _mpu_ppn_data_WIRE_ppn = _mpu_ppn_data_T_14; // @[tlb.scala:58:79] wire [21:0] _mpu_ppn_T_1 = io_req_0_bits_vaddr_0[33:12]; // @[tlb.scala:17:7, :148:134] wire [21:0] _mpu_ppn_T_2 = _mpu_ppn_T_1; // @[tlb.scala:148:{20,134}] wire [21:0] _mpu_ppn_T_3 = _mpu_ppn_T_2; // @[tlb.scala:147:20, :148:20] wire [21:0] mpu_ppn_0 = _mpu_ppn_T_3; // @[tlb.scala:119:49, :147:20] wire [11:0] _mpu_physaddr_T = io_req_0_bits_vaddr_0[11:0]; // @[tlb.scala:17:7, :149:72] wire [11:0] _io_resp_0_paddr_T = io_req_0_bits_vaddr_0[11:0]; // @[tlb.scala:17:7, :149:72, :311:57] wire [33:0] _mpu_physaddr_T_1 = {mpu_ppn_0, _mpu_physaddr_T}; // @[tlb.scala:119:49, :149:{39,72}] wire [33:0] mpu_physaddr_0 = _mpu_physaddr_T_1; // @[tlb.scala:119:49, :149:39] wire [33:0] _cacheable_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _homogeneous_T_26 = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _prot_r_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _prot_w_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _prot_al_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _prot_aa_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _prot_x_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _prot_eff_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _GEN = {mpu_physaddr_0[33:14], mpu_physaddr_0[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [33:0] _legal_address_T; // @[Parameters.scala:137:31] assign _legal_address_T = _GEN; // @[Parameters.scala:137:31] wire [33:0] _homogeneous_T; // @[Parameters.scala:137:31] assign _homogeneous_T = _GEN; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_2 = _legal_address_T_1 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [33:0] _GEN_0 = {mpu_physaddr_0[33:21], mpu_physaddr_0[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [33:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] _prot_x_T_16; // @[Parameters.scala:137:31] assign _prot_x_T_16 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] _prot_eff_T_16; // @[Parameters.scala:137:31] assign _prot_eff_T_16 = _GEN_0; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_7 = _legal_address_T_6 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [33:0] _legal_address_T_10 = {mpu_physaddr_0[33:21], mpu_physaddr_0[20:0] ^ 21'h110000}; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_12 = _legal_address_T_11 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [33:0] _GEN_1 = {mpu_physaddr_0[33:26], mpu_physaddr_0[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [33:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_17 = _legal_address_T_16 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [33:0] _GEN_2 = {mpu_physaddr_0[33:32], mpu_physaddr_0[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [33:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _cacheable_T_5; // @[Parameters.scala:137:31] assign _cacheable_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _homogeneous_T_15; // @[Parameters.scala:137:31] assign _homogeneous_T_15 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _homogeneous_T_33; // @[Parameters.scala:137:31] assign _homogeneous_T_33 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _prot_x_T_5; // @[Parameters.scala:137:31] assign _prot_x_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _prot_eff_T_5; // @[Parameters.scala:137:31] assign _prot_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_22 = _legal_address_T_21 & 35'h7F0000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire _legal_address_T_25 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_26 = _legal_address_T_25 | _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_27 = _legal_address_T_26 | _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_28 = _legal_address_T_27 | _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire legal_address_0 = _legal_address_T_28; // @[tlb.scala:119:49, :157:84] wire _prot_r_T_5 = legal_address_0; // @[tlb.scala:119:49, :159:22] wire _prot_w_T_5 = legal_address_0; // @[tlb.scala:119:49, :159:22] wire _prot_al_T_5 = legal_address_0; // @[tlb.scala:119:49, :159:22] wire _prot_aa_T_5 = legal_address_0; // @[tlb.scala:119:49, :159:22] wire [34:0] _cacheable_T_1 = {1'h0, _cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _cacheable_T_2 = _cacheable_T_1 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _cacheable_T_3 = _cacheable_T_2; // @[Parameters.scala:137:46] wire _cacheable_T_4 = _cacheable_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _cacheable_T_6 = {1'h0, _cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _cacheable_T_7 = _cacheable_T_6 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _cacheable_T_8 = _cacheable_T_7; // @[Parameters.scala:137:46] wire _cacheable_T_9 = _cacheable_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _cacheable_T_11 = _cacheable_T_9; // @[Mux.scala:30:73] wire _cacheable_T_12 = _cacheable_T_11; // @[Mux.scala:30:73] wire _cacheable_WIRE = _cacheable_T_12; // @[Mux.scala:30:73] wire _cacheable_T_13 = legal_address_0 & _cacheable_WIRE; // @[Mux.scala:30:73] wire _cacheable_T_14 = _cacheable_T_13; // @[tlb.scala:159:22, :160:66] wire cacheable_0 = _cacheable_T_14; // @[tlb.scala:119:49, :160:66] wire newEntry_c = cacheable_0; // @[tlb.scala:119:49, :179:24] wire [34:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _homogeneous_T_2 = _homogeneous_T_1 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_20 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [34:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _homogeneous_T_7 = _homogeneous_T_6 & 35'h7FFFEF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _homogeneous_T_12 = _homogeneous_T_11 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] _homogeneous_T_17 = _homogeneous_T_16 & 35'h7F0000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_21 = _homogeneous_T_20 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_22 = _homogeneous_T_21 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_23 = _homogeneous_T_22 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire homogeneous_0 = _homogeneous_T_23; // @[TLBPermissions.scala:101:65] wire [34:0] _homogeneous_T_27 = {1'h0, _homogeneous_T_26}; // @[Parameters.scala:137:{31,41}] wire [34:0] _homogeneous_T_28 = _homogeneous_T_27 & 35'h80002000; // @[Parameters.scala:137:{41,46}] wire [34:0] _homogeneous_T_29 = _homogeneous_T_28; // @[Parameters.scala:137:46] wire _homogeneous_T_30 = _homogeneous_T_29 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_31 = _homogeneous_T_30; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_32 = ~_homogeneous_T_31; // @[TLBPermissions.scala:87:{22,66}] wire [34:0] _homogeneous_T_34 = {1'h0, _homogeneous_T_33}; // @[Parameters.scala:137:{31,41}] wire [34:0] _homogeneous_T_35 = _homogeneous_T_34 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _homogeneous_T_36 = _homogeneous_T_35; // @[Parameters.scala:137:46] wire _homogeneous_T_37 = _homogeneous_T_36 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_38 = _homogeneous_T_37; // @[TLBPermissions.scala:85:66] wire [34:0] _prot_r_T_1 = {1'h0, _prot_r_T}; // @[Parameters.scala:137:{31,41}] wire _prot_r_T_6 = _prot_r_T_5; // @[tlb.scala:159:22, :162:60] wire prot_r_0 = _prot_r_T_6; // @[tlb.scala:119:49, :162:60] wire newEntry_pr = prot_r_0; // @[tlb.scala:119:49, :179:24] wire [34:0] _prot_w_T_1 = {1'h0, _prot_w_T}; // @[Parameters.scala:137:{31,41}] wire _prot_w_T_6 = _prot_w_T_5; // @[tlb.scala:159:22, :163:64] wire prot_w_0 = _prot_w_T_6; // @[tlb.scala:119:49, :163:64] wire newEntry_pw = prot_w_0; // @[tlb.scala:119:49, :179:24] wire [34:0] _prot_al_T_1 = {1'h0, _prot_al_T}; // @[Parameters.scala:137:{31,41}] wire prot_al_0 = _prot_al_T_5; // @[tlb.scala:119:49, :159:22] wire newEntry_pal = prot_al_0; // @[tlb.scala:119:49, :179:24] wire [34:0] _prot_aa_T_1 = {1'h0, _prot_aa_T}; // @[Parameters.scala:137:{31,41}] wire prot_aa_0 = _prot_aa_T_5; // @[tlb.scala:119:49, :159:22] wire newEntry_paa = prot_aa_0; // @[tlb.scala:119:49, :179:24] wire [34:0] _prot_x_T_1 = {1'h0, _prot_x_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_x_T_2 = _prot_x_T_1 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_x_T_3 = _prot_x_T_2; // @[Parameters.scala:137:46] wire _prot_x_T_4 = _prot_x_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _prot_x_T_6 = {1'h0, _prot_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_x_T_7 = _prot_x_T_6 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_x_T_8 = _prot_x_T_7; // @[Parameters.scala:137:46] wire _prot_x_T_9 = _prot_x_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _prot_x_T_10 = _prot_x_T_4 | _prot_x_T_9; // @[Parameters.scala:629:89] wire _prot_x_T_22 = _prot_x_T_10; // @[Mux.scala:30:73] wire [33:0] _GEN_3 = {mpu_physaddr_0[33:17], mpu_physaddr_0[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [33:0] _prot_x_T_11; // @[Parameters.scala:137:31] assign _prot_x_T_11 = _GEN_3; // @[Parameters.scala:137:31] wire [33:0] _prot_eff_T_11; // @[Parameters.scala:137:31] assign _prot_eff_T_11 = _GEN_3; // @[Parameters.scala:137:31] wire [34:0] _prot_x_T_12 = {1'h0, _prot_x_T_11}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_x_T_13 = _prot_x_T_12 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_x_T_14 = _prot_x_T_13; // @[Parameters.scala:137:46] wire _prot_x_T_15 = _prot_x_T_14 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _prot_x_T_17 = {1'h0, _prot_x_T_16}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_x_T_18 = _prot_x_T_17 & 35'h80100000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_x_T_19 = _prot_x_T_18; // @[Parameters.scala:137:46] wire _prot_x_T_20 = _prot_x_T_19 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _prot_x_T_21 = _prot_x_T_15 | _prot_x_T_20; // @[Parameters.scala:629:89] wire _prot_x_T_24 = _prot_x_T_22; // @[Mux.scala:30:73] wire _prot_x_WIRE = _prot_x_T_24; // @[Mux.scala:30:73] wire _prot_x_T_25 = legal_address_0 & _prot_x_WIRE; // @[Mux.scala:30:73] wire _prot_x_T_26 = _prot_x_T_25; // @[tlb.scala:159:22, :166:59] wire prot_x_0 = _prot_x_T_26; // @[tlb.scala:119:49, :166:59] wire newEntry_px = prot_x_0; // @[tlb.scala:119:49, :179:24] wire [34:0] _prot_eff_T_1 = {1'h0, _prot_eff_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_eff_T_2 = _prot_eff_T_1 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_eff_T_3 = _prot_eff_T_2; // @[Parameters.scala:137:46] wire _prot_eff_T_4 = _prot_eff_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _prot_eff_T_6 = {1'h0, _prot_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_eff_T_7 = _prot_eff_T_6 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_eff_T_8 = _prot_eff_T_7; // @[Parameters.scala:137:46] wire _prot_eff_T_9 = _prot_eff_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _prot_eff_T_10 = _prot_eff_T_4 | _prot_eff_T_9; // @[Parameters.scala:629:89] wire [34:0] _prot_eff_T_12 = {1'h0, _prot_eff_T_11}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_eff_T_13 = _prot_eff_T_12 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_eff_T_14 = _prot_eff_T_13; // @[Parameters.scala:137:46] wire _prot_eff_T_15 = _prot_eff_T_14 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _prot_eff_T_17 = {1'h0, _prot_eff_T_16}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_eff_T_18 = _prot_eff_T_17 & 35'h80100000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_eff_T_19 = _prot_eff_T_18; // @[Parameters.scala:137:46] wire _prot_eff_T_20 = _prot_eff_T_19 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _prot_eff_T_21 = _prot_eff_T_15 | _prot_eff_T_20; // @[Parameters.scala:629:89] wire _prot_eff_T_23 = _prot_eff_T_21; // @[Mux.scala:30:73] wire _prot_eff_T_24 = _prot_eff_T_23; // @[Mux.scala:30:73] wire _prot_eff_WIRE = _prot_eff_T_24; // @[Mux.scala:30:73] wire _prot_eff_T_25 = legal_address_0 & _prot_eff_WIRE; // @[Mux.scala:30:73] wire prot_eff_0 = _prot_eff_T_25; // @[tlb.scala:119:49, :159:22] wire newEntry_eff = prot_eff_0; // @[tlb.scala:119:49, :179:24] wire _sector_hits_T_1 = _sector_hits_T; // @[package.scala:81:59] wire _sector_hits_T_2 = _sector_hits_T_1; // @[package.scala:81:59] wire [18:0] _sector_hits_T_4 = _sector_hits_T_3[20:2]; // @[tlb.scala:60:{43,50}] wire _sector_hits_T_5 = _sector_hits_T_4 == 19'h0; // @[tlb.scala:60:{50,73}] wire _sector_hits_T_6 = _sector_hits_T_2 & _sector_hits_T_5; // @[package.scala:81:59] wire _sector_hits_WIRE_0 = _sector_hits_T_6; // @[tlb.scala:59:42, :169:42] wire _sector_hits_T_8 = _sector_hits_T_7; // @[package.scala:81:59] wire _sector_hits_T_9 = _sector_hits_T_8; // @[package.scala:81:59] wire [18:0] _sector_hits_T_11 = _sector_hits_T_10[20:2]; // @[tlb.scala:60:{43,50}] wire _sector_hits_T_12 = _sector_hits_T_11 == 19'h0; // @[tlb.scala:60:{50,73}] wire _sector_hits_T_13 = _sector_hits_T_9 & _sector_hits_T_12; // @[package.scala:81:59] wire _sector_hits_WIRE_1 = _sector_hits_T_13; // @[tlb.scala:59:42, :169:42] wire _sector_hits_T_15 = _sector_hits_T_14; // @[package.scala:81:59] wire _sector_hits_T_16 = _sector_hits_T_15; // @[package.scala:81:59] wire [18:0] _sector_hits_T_18 = _sector_hits_T_17[20:2]; // @[tlb.scala:60:{43,50}] wire _sector_hits_T_19 = _sector_hits_T_18 == 19'h0; // @[tlb.scala:60:{50,73}] wire _sector_hits_T_20 = _sector_hits_T_16 & _sector_hits_T_19; // @[package.scala:81:59] wire _sector_hits_WIRE_2 = _sector_hits_T_20; // @[tlb.scala:59:42, :169:42] wire _sector_hits_T_22 = _sector_hits_T_21; // @[package.scala:81:59] wire _sector_hits_T_23 = _sector_hits_T_22; // @[package.scala:81:59] wire [18:0] _sector_hits_T_25 = _sector_hits_T_24[20:2]; // @[tlb.scala:60:{43,50}] wire _sector_hits_T_26 = _sector_hits_T_25 == 19'h0; // @[tlb.scala:60:{50,73}] wire _sector_hits_T_27 = _sector_hits_T_23 & _sector_hits_T_26; // @[package.scala:81:59] wire _sector_hits_WIRE_3 = _sector_hits_T_27; // @[tlb.scala:59:42, :169:42] wire _sector_hits_T_29 = _sector_hits_T_28; // @[package.scala:81:59] wire _sector_hits_T_30 = _sector_hits_T_29; // @[package.scala:81:59] wire [18:0] _sector_hits_T_32 = _sector_hits_T_31[20:2]; // @[tlb.scala:60:{43,50}] wire _sector_hits_T_33 = _sector_hits_T_32 == 19'h0; // @[tlb.scala:60:{50,73}] wire _sector_hits_T_34 = _sector_hits_T_30 & _sector_hits_T_33; // @[package.scala:81:59] wire _sector_hits_WIRE_4 = _sector_hits_T_34; // @[tlb.scala:59:42, :169:42] wire _sector_hits_T_36 = _sector_hits_T_35; // @[package.scala:81:59] wire _sector_hits_T_37 = _sector_hits_T_36; // @[package.scala:81:59] wire [18:0] _sector_hits_T_39 = _sector_hits_T_38[20:2]; // @[tlb.scala:60:{43,50}] wire _sector_hits_T_40 = _sector_hits_T_39 == 19'h0; // @[tlb.scala:60:{50,73}] wire _sector_hits_T_41 = _sector_hits_T_37 & _sector_hits_T_40; // @[package.scala:81:59] wire _sector_hits_WIRE_5 = _sector_hits_T_41; // @[tlb.scala:59:42, :169:42] wire _sector_hits_T_43 = _sector_hits_T_42; // @[package.scala:81:59] wire _sector_hits_T_44 = _sector_hits_T_43; // @[package.scala:81:59] wire [18:0] _sector_hits_T_46 = _sector_hits_T_45[20:2]; // @[tlb.scala:60:{43,50}] wire _sector_hits_T_47 = _sector_hits_T_46 == 19'h0; // @[tlb.scala:60:{50,73}] wire _sector_hits_T_48 = _sector_hits_T_44 & _sector_hits_T_47; // @[package.scala:81:59] wire _sector_hits_WIRE_6 = _sector_hits_T_48; // @[tlb.scala:59:42, :169:42] wire _sector_hits_T_50 = _sector_hits_T_49; // @[package.scala:81:59] wire _sector_hits_T_51 = _sector_hits_T_50; // @[package.scala:81:59] wire [18:0] _sector_hits_T_53 = _sector_hits_T_52[20:2]; // @[tlb.scala:60:{43,50}] wire _sector_hits_T_54 = _sector_hits_T_53 == 19'h0; // @[tlb.scala:60:{50,73}] wire _sector_hits_T_55 = _sector_hits_T_51 & _sector_hits_T_54; // @[package.scala:81:59] wire _sector_hits_WIRE_7 = _sector_hits_T_55; // @[tlb.scala:59:42, :169:42] wire sector_hits_0_0 = _sector_hits_WIRE_0; // @[tlb.scala:119:49, :169:42] wire sector_hits_0_1 = _sector_hits_WIRE_1; // @[tlb.scala:119:49, :169:42] wire sector_hits_0_2 = _sector_hits_WIRE_2; // @[tlb.scala:119:49, :169:42] wire sector_hits_0_3 = _sector_hits_WIRE_3; // @[tlb.scala:119:49, :169:42] wire sector_hits_0_4 = _sector_hits_WIRE_4; // @[tlb.scala:119:49, :169:42] wire sector_hits_0_5 = _sector_hits_WIRE_5; // @[tlb.scala:119:49, :169:42] wire sector_hits_0_6 = _sector_hits_WIRE_6; // @[tlb.scala:119:49, :169:42] wire sector_hits_0_7 = _sector_hits_WIRE_7; // @[tlb.scala:119:49, :169:42] wire [20:0] _superpage_hits_T_1 = _superpage_hits_T; // @[tlb.scala:60:{43,50}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29] wire _superpage_hits_WIRE_0 = _superpage_hits_T_3; // @[tlb.scala:72:20, :170:45] wire [20:0] _superpage_hits_T_5 = _superpage_hits_T_4; // @[tlb.scala:60:{43,50}] wire _superpage_hits_T_6 = _superpage_hits_T_5 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29] wire _superpage_hits_WIRE_1 = _superpage_hits_T_7; // @[tlb.scala:72:20, :170:45] wire [20:0] _superpage_hits_T_9 = _superpage_hits_T_8; // @[tlb.scala:60:{43,50}] wire _superpage_hits_T_10 = _superpage_hits_T_9 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29] wire _superpage_hits_WIRE_2 = _superpage_hits_T_11; // @[tlb.scala:72:20, :170:45] wire [20:0] _superpage_hits_T_13 = _superpage_hits_T_12; // @[tlb.scala:60:{43,50}] wire _superpage_hits_T_14 = _superpage_hits_T_13 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29] wire _superpage_hits_WIRE_3 = _superpage_hits_T_15; // @[tlb.scala:72:20, :170:45] wire superpage_hits_0_0 = _superpage_hits_WIRE_0; // @[tlb.scala:119:49, :170:45] wire superpage_hits_0_1 = _superpage_hits_WIRE_1; // @[tlb.scala:119:49, :170:45] wire superpage_hits_0_2 = _superpage_hits_WIRE_2; // @[tlb.scala:119:49, :170:45] wire superpage_hits_0_3 = _superpage_hits_WIRE_3; // @[tlb.scala:119:49, :170:45] wire [1:0] hitsVec_idx = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_1 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_2 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_3 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_4 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_5 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_6 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_7 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_16 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_32 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_48 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_64 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_80 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_96 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_112 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_16 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_32 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_48 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_64 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_80 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_96 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_112 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_16 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_32 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_48 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_64 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_80 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_96 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_112 = vpn_0[1:0]; // @[package.scala:163:13] wire [18:0] _hitsVec_T_1 = _hitsVec_T[20:2]; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_2 = _hitsVec_T_1 == 19'h0; // @[tlb.scala:60:{50,73}] wire [18:0] _hitsVec_T_6 = _hitsVec_T_5[20:2]; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_7 = _hitsVec_T_6 == 19'h0; // @[tlb.scala:60:{50,73}] wire [18:0] _hitsVec_T_11 = _hitsVec_T_10[20:2]; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_12 = _hitsVec_T_11 == 19'h0; // @[tlb.scala:60:{50,73}] wire [18:0] _hitsVec_T_16 = _hitsVec_T_15[20:2]; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_17 = _hitsVec_T_16 == 19'h0; // @[tlb.scala:60:{50,73}] wire [18:0] _hitsVec_T_21 = _hitsVec_T_20[20:2]; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_22 = _hitsVec_T_21 == 19'h0; // @[tlb.scala:60:{50,73}] wire [18:0] _hitsVec_T_26 = _hitsVec_T_25[20:2]; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_27 = _hitsVec_T_26 == 19'h0; // @[tlb.scala:60:{50,73}] wire [18:0] _hitsVec_T_31 = _hitsVec_T_30[20:2]; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_32 = _hitsVec_T_31 == 19'h0; // @[tlb.scala:60:{50,73}] wire [18:0] _hitsVec_T_36 = _hitsVec_T_35[20:2]; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_37 = _hitsVec_T_36 == 19'h0; // @[tlb.scala:60:{50,73}] wire [20:0] _hitsVec_T_41 = _hitsVec_T_40; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_42 = _hitsVec_T_41 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29] wire [20:0] _hitsVec_T_46 = _hitsVec_T_45; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_47 = _hitsVec_T_46 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29] wire [20:0] _hitsVec_T_51 = _hitsVec_T_50; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_52 = _hitsVec_T_51 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29] wire [20:0] _hitsVec_T_56 = _hitsVec_T_55; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_57 = _hitsVec_T_56 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29] wire [20:0] _hitsVec_T_61 = _hitsVec_T_60; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_62 = _hitsVec_T_61 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29] wire _hitsVec_T_63 = _hitsVec_T_62; // @[tlb.scala:60:73, :72:20] wire [19:0] _ppn_data_T_15; // @[tlb.scala:58:79] wire _ppn_data_T_14; // @[tlb.scala:58:79] wire _ppn_data_T_13; // @[tlb.scala:58:79] wire _ppn_data_T_12; // @[tlb.scala:58:79] wire _ppn_data_T_11; // @[tlb.scala:58:79] wire _ppn_data_T_10; // @[tlb.scala:58:79] wire _ppn_data_T_9; // @[tlb.scala:58:79] wire _ppn_data_T_8; // @[tlb.scala:58:79] wire _ppn_data_T_7; // @[tlb.scala:58:79] wire _ppn_data_T_6; // @[tlb.scala:58:79] wire _ppn_data_T_5; // @[tlb.scala:58:79] wire _ppn_data_T_4; // @[tlb.scala:58:79] wire _ppn_data_T_3; // @[tlb.scala:58:79] wire _ppn_data_T_2; // @[tlb.scala:58:79] wire _ppn_data_T_1; // @[tlb.scala:58:79] assign _ppn_data_T_1 = _ppn_data_WIRE_1[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_fragmented_superpage = _ppn_data_T_1; // @[tlb.scala:58:79] assign _ppn_data_T_2 = _ppn_data_WIRE_1[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_c = _ppn_data_T_2; // @[tlb.scala:58:79] assign _ppn_data_T_3 = _ppn_data_WIRE_1[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_eff = _ppn_data_T_3; // @[tlb.scala:58:79] assign _ppn_data_T_4 = _ppn_data_WIRE_1[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_paa = _ppn_data_T_4; // @[tlb.scala:58:79] assign _ppn_data_T_5 = _ppn_data_WIRE_1[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_pal = _ppn_data_T_5; // @[tlb.scala:58:79] assign _ppn_data_T_6 = _ppn_data_WIRE_1[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_pr = _ppn_data_T_6; // @[tlb.scala:58:79] assign _ppn_data_T_7 = _ppn_data_WIRE_1[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_px = _ppn_data_T_7; // @[tlb.scala:58:79] assign _ppn_data_T_8 = _ppn_data_WIRE_1[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_pw = _ppn_data_T_8; // @[tlb.scala:58:79] assign _ppn_data_T_9 = _ppn_data_WIRE_1[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_sr = _ppn_data_T_9; // @[tlb.scala:58:79] assign _ppn_data_T_10 = _ppn_data_WIRE_1[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_sx = _ppn_data_T_10; // @[tlb.scala:58:79] assign _ppn_data_T_11 = _ppn_data_WIRE_1[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_sw = _ppn_data_T_11; // @[tlb.scala:58:79] assign _ppn_data_T_12 = _ppn_data_WIRE_1[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_ae = _ppn_data_T_12; // @[tlb.scala:58:79] assign _ppn_data_T_13 = _ppn_data_WIRE_1[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_g = _ppn_data_T_13; // @[tlb.scala:58:79] assign _ppn_data_T_14 = _ppn_data_WIRE_1[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_u = _ppn_data_T_14; // @[tlb.scala:58:79] assign _ppn_data_T_15 = _ppn_data_WIRE_1[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_ppn = _ppn_data_T_15; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_31; // @[tlb.scala:58:79] wire _ppn_data_T_30; // @[tlb.scala:58:79] wire _ppn_data_T_29; // @[tlb.scala:58:79] wire _ppn_data_T_28; // @[tlb.scala:58:79] wire _ppn_data_T_27; // @[tlb.scala:58:79] wire _ppn_data_T_26; // @[tlb.scala:58:79] wire _ppn_data_T_25; // @[tlb.scala:58:79] wire _ppn_data_T_24; // @[tlb.scala:58:79] wire _ppn_data_T_23; // @[tlb.scala:58:79] wire _ppn_data_T_22; // @[tlb.scala:58:79] wire _ppn_data_T_21; // @[tlb.scala:58:79] wire _ppn_data_T_20; // @[tlb.scala:58:79] wire _ppn_data_T_19; // @[tlb.scala:58:79] wire _ppn_data_T_18; // @[tlb.scala:58:79] wire _ppn_data_T_17; // @[tlb.scala:58:79] assign _ppn_data_T_17 = _ppn_data_WIRE_3[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_fragmented_superpage = _ppn_data_T_17; // @[tlb.scala:58:79] assign _ppn_data_T_18 = _ppn_data_WIRE_3[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_c = _ppn_data_T_18; // @[tlb.scala:58:79] assign _ppn_data_T_19 = _ppn_data_WIRE_3[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_eff = _ppn_data_T_19; // @[tlb.scala:58:79] assign _ppn_data_T_20 = _ppn_data_WIRE_3[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_paa = _ppn_data_T_20; // @[tlb.scala:58:79] assign _ppn_data_T_21 = _ppn_data_WIRE_3[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_pal = _ppn_data_T_21; // @[tlb.scala:58:79] assign _ppn_data_T_22 = _ppn_data_WIRE_3[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_pr = _ppn_data_T_22; // @[tlb.scala:58:79] assign _ppn_data_T_23 = _ppn_data_WIRE_3[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_px = _ppn_data_T_23; // @[tlb.scala:58:79] assign _ppn_data_T_24 = _ppn_data_WIRE_3[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_pw = _ppn_data_T_24; // @[tlb.scala:58:79] assign _ppn_data_T_25 = _ppn_data_WIRE_3[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_sr = _ppn_data_T_25; // @[tlb.scala:58:79] assign _ppn_data_T_26 = _ppn_data_WIRE_3[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_sx = _ppn_data_T_26; // @[tlb.scala:58:79] assign _ppn_data_T_27 = _ppn_data_WIRE_3[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_sw = _ppn_data_T_27; // @[tlb.scala:58:79] assign _ppn_data_T_28 = _ppn_data_WIRE_3[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_ae = _ppn_data_T_28; // @[tlb.scala:58:79] assign _ppn_data_T_29 = _ppn_data_WIRE_3[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_g = _ppn_data_T_29; // @[tlb.scala:58:79] assign _ppn_data_T_30 = _ppn_data_WIRE_3[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_u = _ppn_data_T_30; // @[tlb.scala:58:79] assign _ppn_data_T_31 = _ppn_data_WIRE_3[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_2_ppn = _ppn_data_T_31; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_47; // @[tlb.scala:58:79] wire _ppn_data_T_46; // @[tlb.scala:58:79] wire _ppn_data_T_45; // @[tlb.scala:58:79] wire _ppn_data_T_44; // @[tlb.scala:58:79] wire _ppn_data_T_43; // @[tlb.scala:58:79] wire _ppn_data_T_42; // @[tlb.scala:58:79] wire _ppn_data_T_41; // @[tlb.scala:58:79] wire _ppn_data_T_40; // @[tlb.scala:58:79] wire _ppn_data_T_39; // @[tlb.scala:58:79] wire _ppn_data_T_38; // @[tlb.scala:58:79] wire _ppn_data_T_37; // @[tlb.scala:58:79] wire _ppn_data_T_36; // @[tlb.scala:58:79] wire _ppn_data_T_35; // @[tlb.scala:58:79] wire _ppn_data_T_34; // @[tlb.scala:58:79] wire _ppn_data_T_33; // @[tlb.scala:58:79] assign _ppn_data_T_33 = _ppn_data_WIRE_5[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_fragmented_superpage = _ppn_data_T_33; // @[tlb.scala:58:79] assign _ppn_data_T_34 = _ppn_data_WIRE_5[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_c = _ppn_data_T_34; // @[tlb.scala:58:79] assign _ppn_data_T_35 = _ppn_data_WIRE_5[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_eff = _ppn_data_T_35; // @[tlb.scala:58:79] assign _ppn_data_T_36 = _ppn_data_WIRE_5[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_paa = _ppn_data_T_36; // @[tlb.scala:58:79] assign _ppn_data_T_37 = _ppn_data_WIRE_5[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_pal = _ppn_data_T_37; // @[tlb.scala:58:79] assign _ppn_data_T_38 = _ppn_data_WIRE_5[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_pr = _ppn_data_T_38; // @[tlb.scala:58:79] assign _ppn_data_T_39 = _ppn_data_WIRE_5[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_px = _ppn_data_T_39; // @[tlb.scala:58:79] assign _ppn_data_T_40 = _ppn_data_WIRE_5[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_pw = _ppn_data_T_40; // @[tlb.scala:58:79] assign _ppn_data_T_41 = _ppn_data_WIRE_5[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_sr = _ppn_data_T_41; // @[tlb.scala:58:79] assign _ppn_data_T_42 = _ppn_data_WIRE_5[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_sx = _ppn_data_T_42; // @[tlb.scala:58:79] assign _ppn_data_T_43 = _ppn_data_WIRE_5[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_sw = _ppn_data_T_43; // @[tlb.scala:58:79] assign _ppn_data_T_44 = _ppn_data_WIRE_5[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_ae = _ppn_data_T_44; // @[tlb.scala:58:79] assign _ppn_data_T_45 = _ppn_data_WIRE_5[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_g = _ppn_data_T_45; // @[tlb.scala:58:79] assign _ppn_data_T_46 = _ppn_data_WIRE_5[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_u = _ppn_data_T_46; // @[tlb.scala:58:79] assign _ppn_data_T_47 = _ppn_data_WIRE_5[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_4_ppn = _ppn_data_T_47; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_63; // @[tlb.scala:58:79] wire _ppn_data_T_62; // @[tlb.scala:58:79] wire _ppn_data_T_61; // @[tlb.scala:58:79] wire _ppn_data_T_60; // @[tlb.scala:58:79] wire _ppn_data_T_59; // @[tlb.scala:58:79] wire _ppn_data_T_58; // @[tlb.scala:58:79] wire _ppn_data_T_57; // @[tlb.scala:58:79] wire _ppn_data_T_56; // @[tlb.scala:58:79] wire _ppn_data_T_55; // @[tlb.scala:58:79] wire _ppn_data_T_54; // @[tlb.scala:58:79] wire _ppn_data_T_53; // @[tlb.scala:58:79] wire _ppn_data_T_52; // @[tlb.scala:58:79] wire _ppn_data_T_51; // @[tlb.scala:58:79] wire _ppn_data_T_50; // @[tlb.scala:58:79] wire _ppn_data_T_49; // @[tlb.scala:58:79] assign _ppn_data_T_49 = _ppn_data_WIRE_7[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_fragmented_superpage = _ppn_data_T_49; // @[tlb.scala:58:79] assign _ppn_data_T_50 = _ppn_data_WIRE_7[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_c = _ppn_data_T_50; // @[tlb.scala:58:79] assign _ppn_data_T_51 = _ppn_data_WIRE_7[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_eff = _ppn_data_T_51; // @[tlb.scala:58:79] assign _ppn_data_T_52 = _ppn_data_WIRE_7[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_paa = _ppn_data_T_52; // @[tlb.scala:58:79] assign _ppn_data_T_53 = _ppn_data_WIRE_7[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_pal = _ppn_data_T_53; // @[tlb.scala:58:79] assign _ppn_data_T_54 = _ppn_data_WIRE_7[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_pr = _ppn_data_T_54; // @[tlb.scala:58:79] assign _ppn_data_T_55 = _ppn_data_WIRE_7[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_px = _ppn_data_T_55; // @[tlb.scala:58:79] assign _ppn_data_T_56 = _ppn_data_WIRE_7[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_pw = _ppn_data_T_56; // @[tlb.scala:58:79] assign _ppn_data_T_57 = _ppn_data_WIRE_7[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_sr = _ppn_data_T_57; // @[tlb.scala:58:79] assign _ppn_data_T_58 = _ppn_data_WIRE_7[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_sx = _ppn_data_T_58; // @[tlb.scala:58:79] assign _ppn_data_T_59 = _ppn_data_WIRE_7[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_sw = _ppn_data_T_59; // @[tlb.scala:58:79] assign _ppn_data_T_60 = _ppn_data_WIRE_7[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_ae = _ppn_data_T_60; // @[tlb.scala:58:79] assign _ppn_data_T_61 = _ppn_data_WIRE_7[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_g = _ppn_data_T_61; // @[tlb.scala:58:79] assign _ppn_data_T_62 = _ppn_data_WIRE_7[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_u = _ppn_data_T_62; // @[tlb.scala:58:79] assign _ppn_data_T_63 = _ppn_data_WIRE_7[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_6_ppn = _ppn_data_T_63; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_79; // @[tlb.scala:58:79] wire _ppn_data_T_78; // @[tlb.scala:58:79] wire _ppn_data_T_77; // @[tlb.scala:58:79] wire _ppn_data_T_76; // @[tlb.scala:58:79] wire _ppn_data_T_75; // @[tlb.scala:58:79] wire _ppn_data_T_74; // @[tlb.scala:58:79] wire _ppn_data_T_73; // @[tlb.scala:58:79] wire _ppn_data_T_72; // @[tlb.scala:58:79] wire _ppn_data_T_71; // @[tlb.scala:58:79] wire _ppn_data_T_70; // @[tlb.scala:58:79] wire _ppn_data_T_69; // @[tlb.scala:58:79] wire _ppn_data_T_68; // @[tlb.scala:58:79] wire _ppn_data_T_67; // @[tlb.scala:58:79] wire _ppn_data_T_66; // @[tlb.scala:58:79] wire _ppn_data_T_65; // @[tlb.scala:58:79] assign _ppn_data_T_65 = _ppn_data_WIRE_9[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_fragmented_superpage = _ppn_data_T_65; // @[tlb.scala:58:79] assign _ppn_data_T_66 = _ppn_data_WIRE_9[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_c = _ppn_data_T_66; // @[tlb.scala:58:79] assign _ppn_data_T_67 = _ppn_data_WIRE_9[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_eff = _ppn_data_T_67; // @[tlb.scala:58:79] assign _ppn_data_T_68 = _ppn_data_WIRE_9[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_paa = _ppn_data_T_68; // @[tlb.scala:58:79] assign _ppn_data_T_69 = _ppn_data_WIRE_9[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_pal = _ppn_data_T_69; // @[tlb.scala:58:79] assign _ppn_data_T_70 = _ppn_data_WIRE_9[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_pr = _ppn_data_T_70; // @[tlb.scala:58:79] assign _ppn_data_T_71 = _ppn_data_WIRE_9[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_px = _ppn_data_T_71; // @[tlb.scala:58:79] assign _ppn_data_T_72 = _ppn_data_WIRE_9[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_pw = _ppn_data_T_72; // @[tlb.scala:58:79] assign _ppn_data_T_73 = _ppn_data_WIRE_9[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_sr = _ppn_data_T_73; // @[tlb.scala:58:79] assign _ppn_data_T_74 = _ppn_data_WIRE_9[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_sx = _ppn_data_T_74; // @[tlb.scala:58:79] assign _ppn_data_T_75 = _ppn_data_WIRE_9[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_sw = _ppn_data_T_75; // @[tlb.scala:58:79] assign _ppn_data_T_76 = _ppn_data_WIRE_9[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_ae = _ppn_data_T_76; // @[tlb.scala:58:79] assign _ppn_data_T_77 = _ppn_data_WIRE_9[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_g = _ppn_data_T_77; // @[tlb.scala:58:79] assign _ppn_data_T_78 = _ppn_data_WIRE_9[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_u = _ppn_data_T_78; // @[tlb.scala:58:79] assign _ppn_data_T_79 = _ppn_data_WIRE_9[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_8_ppn = _ppn_data_T_79; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_95; // @[tlb.scala:58:79] wire _ppn_data_T_94; // @[tlb.scala:58:79] wire _ppn_data_T_93; // @[tlb.scala:58:79] wire _ppn_data_T_92; // @[tlb.scala:58:79] wire _ppn_data_T_91; // @[tlb.scala:58:79] wire _ppn_data_T_90; // @[tlb.scala:58:79] wire _ppn_data_T_89; // @[tlb.scala:58:79] wire _ppn_data_T_88; // @[tlb.scala:58:79] wire _ppn_data_T_87; // @[tlb.scala:58:79] wire _ppn_data_T_86; // @[tlb.scala:58:79] wire _ppn_data_T_85; // @[tlb.scala:58:79] wire _ppn_data_T_84; // @[tlb.scala:58:79] wire _ppn_data_T_83; // @[tlb.scala:58:79] wire _ppn_data_T_82; // @[tlb.scala:58:79] wire _ppn_data_T_81; // @[tlb.scala:58:79] assign _ppn_data_T_81 = _ppn_data_WIRE_11[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_fragmented_superpage = _ppn_data_T_81; // @[tlb.scala:58:79] assign _ppn_data_T_82 = _ppn_data_WIRE_11[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_c = _ppn_data_T_82; // @[tlb.scala:58:79] assign _ppn_data_T_83 = _ppn_data_WIRE_11[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_eff = _ppn_data_T_83; // @[tlb.scala:58:79] assign _ppn_data_T_84 = _ppn_data_WIRE_11[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_paa = _ppn_data_T_84; // @[tlb.scala:58:79] assign _ppn_data_T_85 = _ppn_data_WIRE_11[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_pal = _ppn_data_T_85; // @[tlb.scala:58:79] assign _ppn_data_T_86 = _ppn_data_WIRE_11[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_pr = _ppn_data_T_86; // @[tlb.scala:58:79] assign _ppn_data_T_87 = _ppn_data_WIRE_11[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_px = _ppn_data_T_87; // @[tlb.scala:58:79] assign _ppn_data_T_88 = _ppn_data_WIRE_11[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_pw = _ppn_data_T_88; // @[tlb.scala:58:79] assign _ppn_data_T_89 = _ppn_data_WIRE_11[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_sr = _ppn_data_T_89; // @[tlb.scala:58:79] assign _ppn_data_T_90 = _ppn_data_WIRE_11[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_sx = _ppn_data_T_90; // @[tlb.scala:58:79] assign _ppn_data_T_91 = _ppn_data_WIRE_11[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_sw = _ppn_data_T_91; // @[tlb.scala:58:79] assign _ppn_data_T_92 = _ppn_data_WIRE_11[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_ae = _ppn_data_T_92; // @[tlb.scala:58:79] assign _ppn_data_T_93 = _ppn_data_WIRE_11[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_g = _ppn_data_T_93; // @[tlb.scala:58:79] assign _ppn_data_T_94 = _ppn_data_WIRE_11[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_u = _ppn_data_T_94; // @[tlb.scala:58:79] assign _ppn_data_T_95 = _ppn_data_WIRE_11[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_10_ppn = _ppn_data_T_95; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_111; // @[tlb.scala:58:79] wire _ppn_data_T_110; // @[tlb.scala:58:79] wire _ppn_data_T_109; // @[tlb.scala:58:79] wire _ppn_data_T_108; // @[tlb.scala:58:79] wire _ppn_data_T_107; // @[tlb.scala:58:79] wire _ppn_data_T_106; // @[tlb.scala:58:79] wire _ppn_data_T_105; // @[tlb.scala:58:79] wire _ppn_data_T_104; // @[tlb.scala:58:79] wire _ppn_data_T_103; // @[tlb.scala:58:79] wire _ppn_data_T_102; // @[tlb.scala:58:79] wire _ppn_data_T_101; // @[tlb.scala:58:79] wire _ppn_data_T_100; // @[tlb.scala:58:79] wire _ppn_data_T_99; // @[tlb.scala:58:79] wire _ppn_data_T_98; // @[tlb.scala:58:79] wire _ppn_data_T_97; // @[tlb.scala:58:79] assign _ppn_data_T_97 = _ppn_data_WIRE_13[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_fragmented_superpage = _ppn_data_T_97; // @[tlb.scala:58:79] assign _ppn_data_T_98 = _ppn_data_WIRE_13[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_c = _ppn_data_T_98; // @[tlb.scala:58:79] assign _ppn_data_T_99 = _ppn_data_WIRE_13[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_eff = _ppn_data_T_99; // @[tlb.scala:58:79] assign _ppn_data_T_100 = _ppn_data_WIRE_13[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_paa = _ppn_data_T_100; // @[tlb.scala:58:79] assign _ppn_data_T_101 = _ppn_data_WIRE_13[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_pal = _ppn_data_T_101; // @[tlb.scala:58:79] assign _ppn_data_T_102 = _ppn_data_WIRE_13[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_pr = _ppn_data_T_102; // @[tlb.scala:58:79] assign _ppn_data_T_103 = _ppn_data_WIRE_13[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_px = _ppn_data_T_103; // @[tlb.scala:58:79] assign _ppn_data_T_104 = _ppn_data_WIRE_13[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_pw = _ppn_data_T_104; // @[tlb.scala:58:79] assign _ppn_data_T_105 = _ppn_data_WIRE_13[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_sr = _ppn_data_T_105; // @[tlb.scala:58:79] assign _ppn_data_T_106 = _ppn_data_WIRE_13[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_sx = _ppn_data_T_106; // @[tlb.scala:58:79] assign _ppn_data_T_107 = _ppn_data_WIRE_13[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_sw = _ppn_data_T_107; // @[tlb.scala:58:79] assign _ppn_data_T_108 = _ppn_data_WIRE_13[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_ae = _ppn_data_T_108; // @[tlb.scala:58:79] assign _ppn_data_T_109 = _ppn_data_WIRE_13[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_g = _ppn_data_T_109; // @[tlb.scala:58:79] assign _ppn_data_T_110 = _ppn_data_WIRE_13[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_u = _ppn_data_T_110; // @[tlb.scala:58:79] assign _ppn_data_T_111 = _ppn_data_WIRE_13[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_12_ppn = _ppn_data_T_111; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_127; // @[tlb.scala:58:79] wire _ppn_data_T_126; // @[tlb.scala:58:79] wire _ppn_data_T_125; // @[tlb.scala:58:79] wire _ppn_data_T_124; // @[tlb.scala:58:79] wire _ppn_data_T_123; // @[tlb.scala:58:79] wire _ppn_data_T_122; // @[tlb.scala:58:79] wire _ppn_data_T_121; // @[tlb.scala:58:79] wire _ppn_data_T_120; // @[tlb.scala:58:79] wire _ppn_data_T_119; // @[tlb.scala:58:79] wire _ppn_data_T_118; // @[tlb.scala:58:79] wire _ppn_data_T_117; // @[tlb.scala:58:79] wire _ppn_data_T_116; // @[tlb.scala:58:79] wire _ppn_data_T_115; // @[tlb.scala:58:79] wire _ppn_data_T_114; // @[tlb.scala:58:79] wire _ppn_data_T_113; // @[tlb.scala:58:79] assign _ppn_data_T_113 = _ppn_data_WIRE_15[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_14_fragmented_superpage = _ppn_data_T_113; // @[tlb.scala:58:79] assign _ppn_data_T_114 = _ppn_data_WIRE_15[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_14_c = _ppn_data_T_114; // @[tlb.scala:58:79] assign _ppn_data_T_115 = _ppn_data_WIRE_15[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_14_eff = _ppn_data_T_115; // @[tlb.scala:58:79] assign _ppn_data_T_116 = _ppn_data_WIRE_15[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_14_paa = _ppn_data_T_116; // @[tlb.scala:58:79] assign _ppn_data_T_117 = _ppn_data_WIRE_15[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_14_pal = _ppn_data_T_117; // @[tlb.scala:58:79] assign _ppn_data_T_118 = _ppn_data_WIRE_15[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_14_pr = _ppn_data_T_118; // @[tlb.scala:58:79] assign _ppn_data_T_119 = _ppn_data_WIRE_15[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_14_px = _ppn_data_T_119; // @[tlb.scala:58:79] assign _ppn_data_T_120 = _ppn_data_WIRE_15[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_14_pw = _ppn_data_T_120; // @[tlb.scala:58:79] assign _ppn_data_T_121 = _ppn_data_WIRE_15[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_14_sr = _ppn_data_T_121; // @[tlb.scala:58:79] assign _ppn_data_T_122 = _ppn_data_WIRE_15[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_14_sx = _ppn_data_T_122; // @[tlb.scala:58:79] assign _ppn_data_T_123 = _ppn_data_WIRE_15[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_14_sw = _ppn_data_T_123; // @[tlb.scala:58:79] assign _ppn_data_T_124 = _ppn_data_WIRE_15[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_14_ae = _ppn_data_T_124; // @[tlb.scala:58:79] assign _ppn_data_T_125 = _ppn_data_WIRE_15[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_14_g = _ppn_data_T_125; // @[tlb.scala:58:79] assign _ppn_data_T_126 = _ppn_data_WIRE_15[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_14_u = _ppn_data_T_126; // @[tlb.scala:58:79] assign _ppn_data_T_127 = _ppn_data_WIRE_15[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_14_ppn = _ppn_data_T_127; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_142; // @[tlb.scala:58:79] wire _ppn_data_T_141; // @[tlb.scala:58:79] wire _ppn_data_T_140; // @[tlb.scala:58:79] wire _ppn_data_T_139; // @[tlb.scala:58:79] wire _ppn_data_T_138; // @[tlb.scala:58:79] wire _ppn_data_T_137; // @[tlb.scala:58:79] wire _ppn_data_T_136; // @[tlb.scala:58:79] wire _ppn_data_T_135; // @[tlb.scala:58:79] wire _ppn_data_T_134; // @[tlb.scala:58:79] wire _ppn_data_T_133; // @[tlb.scala:58:79] wire _ppn_data_T_132; // @[tlb.scala:58:79] wire _ppn_data_T_131; // @[tlb.scala:58:79] wire _ppn_data_T_130; // @[tlb.scala:58:79] wire _ppn_data_T_129; // @[tlb.scala:58:79] wire _ppn_data_T_128; // @[tlb.scala:58:79] assign _ppn_data_T_128 = _ppn_data_WIRE_17[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_16_fragmented_superpage = _ppn_data_T_128; // @[tlb.scala:58:79] assign _ppn_data_T_129 = _ppn_data_WIRE_17[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_16_c = _ppn_data_T_129; // @[tlb.scala:58:79] assign _ppn_data_T_130 = _ppn_data_WIRE_17[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_16_eff = _ppn_data_T_130; // @[tlb.scala:58:79] assign _ppn_data_T_131 = _ppn_data_WIRE_17[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_16_paa = _ppn_data_T_131; // @[tlb.scala:58:79] assign _ppn_data_T_132 = _ppn_data_WIRE_17[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_16_pal = _ppn_data_T_132; // @[tlb.scala:58:79] assign _ppn_data_T_133 = _ppn_data_WIRE_17[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_16_pr = _ppn_data_T_133; // @[tlb.scala:58:79] assign _ppn_data_T_134 = _ppn_data_WIRE_17[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_16_px = _ppn_data_T_134; // @[tlb.scala:58:79] assign _ppn_data_T_135 = _ppn_data_WIRE_17[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_16_pw = _ppn_data_T_135; // @[tlb.scala:58:79] assign _ppn_data_T_136 = _ppn_data_WIRE_17[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_16_sr = _ppn_data_T_136; // @[tlb.scala:58:79] assign _ppn_data_T_137 = _ppn_data_WIRE_17[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_16_sx = _ppn_data_T_137; // @[tlb.scala:58:79] assign _ppn_data_T_138 = _ppn_data_WIRE_17[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_16_sw = _ppn_data_T_138; // @[tlb.scala:58:79] assign _ppn_data_T_139 = _ppn_data_WIRE_17[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_16_ae = _ppn_data_T_139; // @[tlb.scala:58:79] assign _ppn_data_T_140 = _ppn_data_WIRE_17[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_16_g = _ppn_data_T_140; // @[tlb.scala:58:79] assign _ppn_data_T_141 = _ppn_data_WIRE_17[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_16_u = _ppn_data_T_141; // @[tlb.scala:58:79] assign _ppn_data_T_142 = _ppn_data_WIRE_17[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_16_ppn = _ppn_data_T_142; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_157; // @[tlb.scala:58:79] wire _ppn_data_T_156; // @[tlb.scala:58:79] wire _ppn_data_T_155; // @[tlb.scala:58:79] wire _ppn_data_T_154; // @[tlb.scala:58:79] wire _ppn_data_T_153; // @[tlb.scala:58:79] wire _ppn_data_T_152; // @[tlb.scala:58:79] wire _ppn_data_T_151; // @[tlb.scala:58:79] wire _ppn_data_T_150; // @[tlb.scala:58:79] wire _ppn_data_T_149; // @[tlb.scala:58:79] wire _ppn_data_T_148; // @[tlb.scala:58:79] wire _ppn_data_T_147; // @[tlb.scala:58:79] wire _ppn_data_T_146; // @[tlb.scala:58:79] wire _ppn_data_T_145; // @[tlb.scala:58:79] wire _ppn_data_T_144; // @[tlb.scala:58:79] wire _ppn_data_T_143; // @[tlb.scala:58:79] assign _ppn_data_T_143 = _ppn_data_WIRE_19[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_18_fragmented_superpage = _ppn_data_T_143; // @[tlb.scala:58:79] assign _ppn_data_T_144 = _ppn_data_WIRE_19[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_18_c = _ppn_data_T_144; // @[tlb.scala:58:79] assign _ppn_data_T_145 = _ppn_data_WIRE_19[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_18_eff = _ppn_data_T_145; // @[tlb.scala:58:79] assign _ppn_data_T_146 = _ppn_data_WIRE_19[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_18_paa = _ppn_data_T_146; // @[tlb.scala:58:79] assign _ppn_data_T_147 = _ppn_data_WIRE_19[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_18_pal = _ppn_data_T_147; // @[tlb.scala:58:79] assign _ppn_data_T_148 = _ppn_data_WIRE_19[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_18_pr = _ppn_data_T_148; // @[tlb.scala:58:79] assign _ppn_data_T_149 = _ppn_data_WIRE_19[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_18_px = _ppn_data_T_149; // @[tlb.scala:58:79] assign _ppn_data_T_150 = _ppn_data_WIRE_19[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_18_pw = _ppn_data_T_150; // @[tlb.scala:58:79] assign _ppn_data_T_151 = _ppn_data_WIRE_19[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_18_sr = _ppn_data_T_151; // @[tlb.scala:58:79] assign _ppn_data_T_152 = _ppn_data_WIRE_19[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_18_sx = _ppn_data_T_152; // @[tlb.scala:58:79] assign _ppn_data_T_153 = _ppn_data_WIRE_19[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_18_sw = _ppn_data_T_153; // @[tlb.scala:58:79] assign _ppn_data_T_154 = _ppn_data_WIRE_19[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_18_ae = _ppn_data_T_154; // @[tlb.scala:58:79] assign _ppn_data_T_155 = _ppn_data_WIRE_19[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_18_g = _ppn_data_T_155; // @[tlb.scala:58:79] assign _ppn_data_T_156 = _ppn_data_WIRE_19[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_18_u = _ppn_data_T_156; // @[tlb.scala:58:79] assign _ppn_data_T_157 = _ppn_data_WIRE_19[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_18_ppn = _ppn_data_T_157; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_172; // @[tlb.scala:58:79] wire _ppn_data_T_171; // @[tlb.scala:58:79] wire _ppn_data_T_170; // @[tlb.scala:58:79] wire _ppn_data_T_169; // @[tlb.scala:58:79] wire _ppn_data_T_168; // @[tlb.scala:58:79] wire _ppn_data_T_167; // @[tlb.scala:58:79] wire _ppn_data_T_166; // @[tlb.scala:58:79] wire _ppn_data_T_165; // @[tlb.scala:58:79] wire _ppn_data_T_164; // @[tlb.scala:58:79] wire _ppn_data_T_163; // @[tlb.scala:58:79] wire _ppn_data_T_162; // @[tlb.scala:58:79] wire _ppn_data_T_161; // @[tlb.scala:58:79] wire _ppn_data_T_160; // @[tlb.scala:58:79] wire _ppn_data_T_159; // @[tlb.scala:58:79] wire _ppn_data_T_158; // @[tlb.scala:58:79] assign _ppn_data_T_158 = _ppn_data_WIRE_21[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_20_fragmented_superpage = _ppn_data_T_158; // @[tlb.scala:58:79] assign _ppn_data_T_159 = _ppn_data_WIRE_21[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_20_c = _ppn_data_T_159; // @[tlb.scala:58:79] assign _ppn_data_T_160 = _ppn_data_WIRE_21[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_20_eff = _ppn_data_T_160; // @[tlb.scala:58:79] assign _ppn_data_T_161 = _ppn_data_WIRE_21[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_20_paa = _ppn_data_T_161; // @[tlb.scala:58:79] assign _ppn_data_T_162 = _ppn_data_WIRE_21[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_20_pal = _ppn_data_T_162; // @[tlb.scala:58:79] assign _ppn_data_T_163 = _ppn_data_WIRE_21[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_20_pr = _ppn_data_T_163; // @[tlb.scala:58:79] assign _ppn_data_T_164 = _ppn_data_WIRE_21[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_20_px = _ppn_data_T_164; // @[tlb.scala:58:79] assign _ppn_data_T_165 = _ppn_data_WIRE_21[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_20_pw = _ppn_data_T_165; // @[tlb.scala:58:79] assign _ppn_data_T_166 = _ppn_data_WIRE_21[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_20_sr = _ppn_data_T_166; // @[tlb.scala:58:79] assign _ppn_data_T_167 = _ppn_data_WIRE_21[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_20_sx = _ppn_data_T_167; // @[tlb.scala:58:79] assign _ppn_data_T_168 = _ppn_data_WIRE_21[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_20_sw = _ppn_data_T_168; // @[tlb.scala:58:79] assign _ppn_data_T_169 = _ppn_data_WIRE_21[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_20_ae = _ppn_data_T_169; // @[tlb.scala:58:79] assign _ppn_data_T_170 = _ppn_data_WIRE_21[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_20_g = _ppn_data_T_170; // @[tlb.scala:58:79] assign _ppn_data_T_171 = _ppn_data_WIRE_21[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_20_u = _ppn_data_T_171; // @[tlb.scala:58:79] assign _ppn_data_T_172 = _ppn_data_WIRE_21[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_20_ppn = _ppn_data_T_172; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_187; // @[tlb.scala:58:79] wire _ppn_data_T_186; // @[tlb.scala:58:79] wire _ppn_data_T_185; // @[tlb.scala:58:79] wire _ppn_data_T_184; // @[tlb.scala:58:79] wire _ppn_data_T_183; // @[tlb.scala:58:79] wire _ppn_data_T_182; // @[tlb.scala:58:79] wire _ppn_data_T_181; // @[tlb.scala:58:79] wire _ppn_data_T_180; // @[tlb.scala:58:79] wire _ppn_data_T_179; // @[tlb.scala:58:79] wire _ppn_data_T_178; // @[tlb.scala:58:79] wire _ppn_data_T_177; // @[tlb.scala:58:79] wire _ppn_data_T_176; // @[tlb.scala:58:79] wire _ppn_data_T_175; // @[tlb.scala:58:79] wire _ppn_data_T_174; // @[tlb.scala:58:79] wire _ppn_data_T_173; // @[tlb.scala:58:79] assign _ppn_data_T_173 = _ppn_data_WIRE_23[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_22_fragmented_superpage = _ppn_data_T_173; // @[tlb.scala:58:79] assign _ppn_data_T_174 = _ppn_data_WIRE_23[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_22_c = _ppn_data_T_174; // @[tlb.scala:58:79] assign _ppn_data_T_175 = _ppn_data_WIRE_23[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_22_eff = _ppn_data_T_175; // @[tlb.scala:58:79] assign _ppn_data_T_176 = _ppn_data_WIRE_23[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_22_paa = _ppn_data_T_176; // @[tlb.scala:58:79] assign _ppn_data_T_177 = _ppn_data_WIRE_23[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_22_pal = _ppn_data_T_177; // @[tlb.scala:58:79] assign _ppn_data_T_178 = _ppn_data_WIRE_23[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_22_pr = _ppn_data_T_178; // @[tlb.scala:58:79] assign _ppn_data_T_179 = _ppn_data_WIRE_23[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_22_px = _ppn_data_T_179; // @[tlb.scala:58:79] assign _ppn_data_T_180 = _ppn_data_WIRE_23[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_22_pw = _ppn_data_T_180; // @[tlb.scala:58:79] assign _ppn_data_T_181 = _ppn_data_WIRE_23[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_22_sr = _ppn_data_T_181; // @[tlb.scala:58:79] assign _ppn_data_T_182 = _ppn_data_WIRE_23[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_22_sx = _ppn_data_T_182; // @[tlb.scala:58:79] assign _ppn_data_T_183 = _ppn_data_WIRE_23[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_22_sw = _ppn_data_T_183; // @[tlb.scala:58:79] assign _ppn_data_T_184 = _ppn_data_WIRE_23[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_22_ae = _ppn_data_T_184; // @[tlb.scala:58:79] assign _ppn_data_T_185 = _ppn_data_WIRE_23[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_22_g = _ppn_data_T_185; // @[tlb.scala:58:79] assign _ppn_data_T_186 = _ppn_data_WIRE_23[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_22_u = _ppn_data_T_186; // @[tlb.scala:58:79] assign _ppn_data_T_187 = _ppn_data_WIRE_23[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_22_ppn = _ppn_data_T_187; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_202; // @[tlb.scala:58:79] wire _ppn_data_T_201; // @[tlb.scala:58:79] wire _ppn_data_T_200; // @[tlb.scala:58:79] wire _ppn_data_T_199; // @[tlb.scala:58:79] wire _ppn_data_T_198; // @[tlb.scala:58:79] wire _ppn_data_T_197; // @[tlb.scala:58:79] wire _ppn_data_T_196; // @[tlb.scala:58:79] wire _ppn_data_T_195; // @[tlb.scala:58:79] wire _ppn_data_T_194; // @[tlb.scala:58:79] wire _ppn_data_T_193; // @[tlb.scala:58:79] wire _ppn_data_T_192; // @[tlb.scala:58:79] wire _ppn_data_T_191; // @[tlb.scala:58:79] wire _ppn_data_T_190; // @[tlb.scala:58:79] wire _ppn_data_T_189; // @[tlb.scala:58:79] wire _ppn_data_T_188; // @[tlb.scala:58:79] assign _ppn_data_T_188 = _ppn_data_WIRE_25[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_24_fragmented_superpage = _ppn_data_T_188; // @[tlb.scala:58:79] assign _ppn_data_T_189 = _ppn_data_WIRE_25[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_24_c = _ppn_data_T_189; // @[tlb.scala:58:79] assign _ppn_data_T_190 = _ppn_data_WIRE_25[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_24_eff = _ppn_data_T_190; // @[tlb.scala:58:79] assign _ppn_data_T_191 = _ppn_data_WIRE_25[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_24_paa = _ppn_data_T_191; // @[tlb.scala:58:79] assign _ppn_data_T_192 = _ppn_data_WIRE_25[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_24_pal = _ppn_data_T_192; // @[tlb.scala:58:79] assign _ppn_data_T_193 = _ppn_data_WIRE_25[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_24_pr = _ppn_data_T_193; // @[tlb.scala:58:79] assign _ppn_data_T_194 = _ppn_data_WIRE_25[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_24_px = _ppn_data_T_194; // @[tlb.scala:58:79] assign _ppn_data_T_195 = _ppn_data_WIRE_25[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_24_pw = _ppn_data_T_195; // @[tlb.scala:58:79] assign _ppn_data_T_196 = _ppn_data_WIRE_25[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_24_sr = _ppn_data_T_196; // @[tlb.scala:58:79] assign _ppn_data_T_197 = _ppn_data_WIRE_25[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_24_sx = _ppn_data_T_197; // @[tlb.scala:58:79] assign _ppn_data_T_198 = _ppn_data_WIRE_25[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_24_sw = _ppn_data_T_198; // @[tlb.scala:58:79] assign _ppn_data_T_199 = _ppn_data_WIRE_25[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_24_ae = _ppn_data_T_199; // @[tlb.scala:58:79] assign _ppn_data_T_200 = _ppn_data_WIRE_25[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_24_g = _ppn_data_T_200; // @[tlb.scala:58:79] assign _ppn_data_T_201 = _ppn_data_WIRE_25[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_24_u = _ppn_data_T_201; // @[tlb.scala:58:79] assign _ppn_data_T_202 = _ppn_data_WIRE_25[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_24_ppn = _ppn_data_T_202; // @[tlb.scala:58:79] wire [19:0] _ppn_T_1 = vpn_0[19:0]; // @[tlb.scala:119:49, :174:103] wire [19:0] _ppn_T_15 = _ppn_T_1; // @[Mux.scala:30:73] wire [19:0] _ppn_T_28 = _ppn_T_15; // @[Mux.scala:30:73] wire [19:0] _ppn_WIRE = _ppn_T_28; // @[Mux.scala:30:73] wire [19:0] ppn_0 = _ppn_WIRE; // @[Mux.scala:30:73] wire [1:0] _GEN_4 = {newEntry_eff, newEntry_c}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_lo_lo_hi; // @[tlb.scala:95:26] assign special_entry_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_lo_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_lo_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_lo_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_lo_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_lo_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_0_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_lo_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_1_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26] wire [1:0] sectored_entries_2_data_lo_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_2_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26] wire [1:0] sectored_entries_3_data_lo_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_3_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26] wire [1:0] sectored_entries_4_data_lo_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_4_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26] wire [1:0] sectored_entries_5_data_lo_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_5_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26] wire [1:0] sectored_entries_6_data_lo_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_6_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26] wire [1:0] sectored_entries_7_data_lo_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_7_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26] wire [2:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [1:0] _GEN_5 = {newEntry_pal, newEntry_paa}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_lo_hi_lo; // @[tlb.scala:95:26] assign special_entry_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_lo_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_lo_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_lo_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_lo_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_lo_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_0_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_lo_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_1_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26] wire [1:0] sectored_entries_2_data_lo_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_2_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26] wire [1:0] sectored_entries_3_data_lo_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_3_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26] wire [1:0] sectored_entries_4_data_lo_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_4_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26] wire [1:0] sectored_entries_5_data_lo_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_5_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26] wire [1:0] sectored_entries_6_data_lo_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_6_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26] wire [1:0] sectored_entries_7_data_lo_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_7_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26] wire [1:0] _GEN_6 = {newEntry_px, newEntry_pr}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_lo_hi_hi; // @[tlb.scala:95:26] assign special_entry_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_lo_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_lo_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_lo_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_lo_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_lo_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_0_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_lo_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_1_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26] wire [1:0] sectored_entries_2_data_lo_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_2_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26] wire [1:0] sectored_entries_3_data_lo_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_3_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26] wire [1:0] sectored_entries_4_data_lo_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_4_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26] wire [1:0] sectored_entries_5_data_lo_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_5_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26] wire [1:0] sectored_entries_6_data_lo_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_6_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26] wire [1:0] sectored_entries_7_data_lo_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_7_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26] wire [3:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[tlb.scala:95:26] wire [1:0] _GEN_7 = {1'h1, newEntry_pw}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_hi_lo_lo; // @[tlb.scala:95:26] assign special_entry_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_hi_lo_lo; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_hi_lo_lo; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_hi_lo_lo; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_hi_lo_lo; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_hi_lo_lo; // @[tlb.scala:95:26] assign sectored_entries_0_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_hi_lo_lo; // @[tlb.scala:95:26] assign sectored_entries_1_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26] wire [1:0] sectored_entries_2_data_hi_lo_lo; // @[tlb.scala:95:26] assign sectored_entries_2_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26] wire [1:0] sectored_entries_3_data_hi_lo_lo; // @[tlb.scala:95:26] assign sectored_entries_3_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26] wire [1:0] sectored_entries_4_data_hi_lo_lo; // @[tlb.scala:95:26] assign sectored_entries_4_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26] wire [1:0] sectored_entries_5_data_hi_lo_lo; // @[tlb.scala:95:26] assign sectored_entries_5_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26] wire [1:0] sectored_entries_6_data_hi_lo_lo; // @[tlb.scala:95:26] assign sectored_entries_6_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26] wire [1:0] sectored_entries_7_data_hi_lo_lo; // @[tlb.scala:95:26] assign sectored_entries_7_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26] wire [3:0] special_entry_data_0_hi_lo = {2'h2, special_entry_data_0_hi_lo_lo}; // @[tlb.scala:95:26] wire [20:0] _GEN_8 = {newEntry_ppn, 1'h1}; // @[tlb.scala:95:26, :179:24] wire [20:0] special_entry_data_0_hi_hi_hi; // @[tlb.scala:95:26] assign special_entry_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26] wire [20:0] superpage_entries_0_data_0_hi_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26] wire [20:0] superpage_entries_1_data_0_hi_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26] wire [20:0] superpage_entries_2_data_0_hi_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26] wire [20:0] superpage_entries_3_data_0_hi_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26] wire [20:0] sectored_entries_0_data_hi_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_0_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26] wire [20:0] sectored_entries_1_data_hi_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_1_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26] wire [20:0] sectored_entries_2_data_hi_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_2_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26] wire [20:0] sectored_entries_3_data_hi_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_3_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26] wire [20:0] sectored_entries_4_data_hi_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_4_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26] wire [20:0] sectored_entries_5_data_hi_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_5_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26] wire [20:0] sectored_entries_6_data_hi_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_6_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26] wire [20:0] sectored_entries_7_data_hi_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_7_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26] wire [22:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26] wire [26:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[tlb.scala:95:26] wire [2:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_0_data_0_hi_lo = {2'h2, superpage_entries_0_data_0_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26] wire [26:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[tlb.scala:95:26] wire [2:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_1_data_0_hi_lo = {2'h2, superpage_entries_1_data_0_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26] wire [26:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[tlb.scala:95:26] wire [2:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_2_data_0_hi_lo = {2'h2, superpage_entries_2_data_0_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26] wire [26:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[tlb.scala:95:26] wire [2:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_3_data_0_hi_lo = {2'h2, superpage_entries_3_data_0_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26] wire [26:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[tlb.scala:95:26] wire [2:0] sectored_entries_0_data_lo_lo = {sectored_entries_0_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_0_data_lo_hi = {sectored_entries_0_data_lo_hi_hi, sectored_entries_0_data_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] sectored_entries_0_data_lo = {sectored_entries_0_data_lo_hi, sectored_entries_0_data_lo_lo}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_0_data_hi_lo = {2'h2, sectored_entries_0_data_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] sectored_entries_0_data_hi_hi = {sectored_entries_0_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26] wire [26:0] sectored_entries_0_data_hi = {sectored_entries_0_data_hi_hi, sectored_entries_0_data_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _sectored_entries_0_data_T = {sectored_entries_0_data_hi, sectored_entries_0_data_lo}; // @[tlb.scala:95:26] wire [2:0] sectored_entries_1_data_lo_lo = {sectored_entries_1_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_1_data_lo_hi = {sectored_entries_1_data_lo_hi_hi, sectored_entries_1_data_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] sectored_entries_1_data_lo = {sectored_entries_1_data_lo_hi, sectored_entries_1_data_lo_lo}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_1_data_hi_lo = {2'h2, sectored_entries_1_data_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] sectored_entries_1_data_hi_hi = {sectored_entries_1_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26] wire [26:0] sectored_entries_1_data_hi = {sectored_entries_1_data_hi_hi, sectored_entries_1_data_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _sectored_entries_1_data_T = {sectored_entries_1_data_hi, sectored_entries_1_data_lo}; // @[tlb.scala:95:26] wire [2:0] sectored_entries_2_data_lo_lo = {sectored_entries_2_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_2_data_lo_hi = {sectored_entries_2_data_lo_hi_hi, sectored_entries_2_data_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] sectored_entries_2_data_lo = {sectored_entries_2_data_lo_hi, sectored_entries_2_data_lo_lo}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_2_data_hi_lo = {2'h2, sectored_entries_2_data_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] sectored_entries_2_data_hi_hi = {sectored_entries_2_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26] wire [26:0] sectored_entries_2_data_hi = {sectored_entries_2_data_hi_hi, sectored_entries_2_data_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _sectored_entries_2_data_T = {sectored_entries_2_data_hi, sectored_entries_2_data_lo}; // @[tlb.scala:95:26] wire [2:0] sectored_entries_3_data_lo_lo = {sectored_entries_3_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_3_data_lo_hi = {sectored_entries_3_data_lo_hi_hi, sectored_entries_3_data_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] sectored_entries_3_data_lo = {sectored_entries_3_data_lo_hi, sectored_entries_3_data_lo_lo}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_3_data_hi_lo = {2'h2, sectored_entries_3_data_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] sectored_entries_3_data_hi_hi = {sectored_entries_3_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26] wire [26:0] sectored_entries_3_data_hi = {sectored_entries_3_data_hi_hi, sectored_entries_3_data_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _sectored_entries_3_data_T = {sectored_entries_3_data_hi, sectored_entries_3_data_lo}; // @[tlb.scala:95:26] wire [2:0] sectored_entries_4_data_lo_lo = {sectored_entries_4_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_4_data_lo_hi = {sectored_entries_4_data_lo_hi_hi, sectored_entries_4_data_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] sectored_entries_4_data_lo = {sectored_entries_4_data_lo_hi, sectored_entries_4_data_lo_lo}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_4_data_hi_lo = {2'h2, sectored_entries_4_data_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] sectored_entries_4_data_hi_hi = {sectored_entries_4_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26] wire [26:0] sectored_entries_4_data_hi = {sectored_entries_4_data_hi_hi, sectored_entries_4_data_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _sectored_entries_4_data_T = {sectored_entries_4_data_hi, sectored_entries_4_data_lo}; // @[tlb.scala:95:26] wire [2:0] sectored_entries_5_data_lo_lo = {sectored_entries_5_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_5_data_lo_hi = {sectored_entries_5_data_lo_hi_hi, sectored_entries_5_data_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] sectored_entries_5_data_lo = {sectored_entries_5_data_lo_hi, sectored_entries_5_data_lo_lo}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_5_data_hi_lo = {2'h2, sectored_entries_5_data_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] sectored_entries_5_data_hi_hi = {sectored_entries_5_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26] wire [26:0] sectored_entries_5_data_hi = {sectored_entries_5_data_hi_hi, sectored_entries_5_data_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _sectored_entries_5_data_T = {sectored_entries_5_data_hi, sectored_entries_5_data_lo}; // @[tlb.scala:95:26] wire [2:0] sectored_entries_6_data_lo_lo = {sectored_entries_6_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_6_data_lo_hi = {sectored_entries_6_data_lo_hi_hi, sectored_entries_6_data_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] sectored_entries_6_data_lo = {sectored_entries_6_data_lo_hi, sectored_entries_6_data_lo_lo}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_6_data_hi_lo = {2'h2, sectored_entries_6_data_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] sectored_entries_6_data_hi_hi = {sectored_entries_6_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26] wire [26:0] sectored_entries_6_data_hi = {sectored_entries_6_data_hi_hi, sectored_entries_6_data_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _sectored_entries_6_data_T = {sectored_entries_6_data_hi, sectored_entries_6_data_lo}; // @[tlb.scala:95:26] wire [2:0] sectored_entries_7_data_lo_lo = {sectored_entries_7_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_7_data_lo_hi = {sectored_entries_7_data_lo_hi_hi, sectored_entries_7_data_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] sectored_entries_7_data_lo = {sectored_entries_7_data_lo_hi, sectored_entries_7_data_lo_lo}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_7_data_hi_lo = {2'h2, sectored_entries_7_data_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] sectored_entries_7_data_hi_hi = {sectored_entries_7_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26] wire [26:0] sectored_entries_7_data_hi = {sectored_entries_7_data_hi_hi, sectored_entries_7_data_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _sectored_entries_7_data_T = {sectored_entries_7_data_hi, sectored_entries_7_data_lo}; // @[tlb.scala:95:26] wire [19:0] _entries_T_15; // @[tlb.scala:58:79] wire _entries_T_14; // @[tlb.scala:58:79] wire _entries_T_13; // @[tlb.scala:58:79] wire _entries_T_12; // @[tlb.scala:58:79] wire _entries_T_11; // @[tlb.scala:58:79] wire _entries_T_10; // @[tlb.scala:58:79] wire _entries_T_9; // @[tlb.scala:58:79] wire _entries_T_8; // @[tlb.scala:58:79] wire _entries_T_7; // @[tlb.scala:58:79] wire _entries_T_6; // @[tlb.scala:58:79] wire _entries_T_5; // @[tlb.scala:58:79] wire _entries_T_4; // @[tlb.scala:58:79] wire _entries_T_3; // @[tlb.scala:58:79] wire _entries_T_2; // @[tlb.scala:58:79] wire _entries_T_1; // @[tlb.scala:58:79] assign _entries_T_1 = _entries_WIRE_1[0]; // @[tlb.scala:58:79] wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[tlb.scala:58:79] assign _entries_T_2 = _entries_WIRE_1[1]; // @[tlb.scala:58:79] wire _entries_WIRE_c = _entries_T_2; // @[tlb.scala:58:79] assign _entries_T_3 = _entries_WIRE_1[2]; // @[tlb.scala:58:79] wire _entries_WIRE_eff = _entries_T_3; // @[tlb.scala:58:79] assign _entries_T_4 = _entries_WIRE_1[3]; // @[tlb.scala:58:79] wire _entries_WIRE_paa = _entries_T_4; // @[tlb.scala:58:79] assign _entries_T_5 = _entries_WIRE_1[4]; // @[tlb.scala:58:79] wire _entries_WIRE_pal = _entries_T_5; // @[tlb.scala:58:79] assign _entries_T_6 = _entries_WIRE_1[5]; // @[tlb.scala:58:79] wire _entries_WIRE_pr = _entries_T_6; // @[tlb.scala:58:79] assign _entries_T_7 = _entries_WIRE_1[6]; // @[tlb.scala:58:79] wire _entries_WIRE_px = _entries_T_7; // @[tlb.scala:58:79] assign _entries_T_8 = _entries_WIRE_1[7]; // @[tlb.scala:58:79] wire _entries_WIRE_pw = _entries_T_8; // @[tlb.scala:58:79] assign _entries_T_9 = _entries_WIRE_1[8]; // @[tlb.scala:58:79] wire _entries_WIRE_sr = _entries_T_9; // @[tlb.scala:58:79] assign _entries_T_10 = _entries_WIRE_1[9]; // @[tlb.scala:58:79] wire _entries_WIRE_sx = _entries_T_10; // @[tlb.scala:58:79] assign _entries_T_11 = _entries_WIRE_1[10]; // @[tlb.scala:58:79] wire _entries_WIRE_sw = _entries_T_11; // @[tlb.scala:58:79] assign _entries_T_12 = _entries_WIRE_1[11]; // @[tlb.scala:58:79] wire _entries_WIRE_ae = _entries_T_12; // @[tlb.scala:58:79] assign _entries_T_13 = _entries_WIRE_1[12]; // @[tlb.scala:58:79] wire _entries_WIRE_g = _entries_T_13; // @[tlb.scala:58:79] assign _entries_T_14 = _entries_WIRE_1[13]; // @[tlb.scala:58:79] wire _entries_WIRE_u = _entries_T_14; // @[tlb.scala:58:79] assign _entries_T_15 = _entries_WIRE_1[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_ppn = _entries_T_15; // @[tlb.scala:58:79] wire [19:0] _entries_T_31; // @[tlb.scala:58:79] wire _entries_T_30; // @[tlb.scala:58:79] wire _entries_T_29; // @[tlb.scala:58:79] wire _entries_T_28; // @[tlb.scala:58:79] wire _entries_T_27; // @[tlb.scala:58:79] wire _entries_T_26; // @[tlb.scala:58:79] wire _entries_T_25; // @[tlb.scala:58:79] wire _entries_T_24; // @[tlb.scala:58:79] wire _entries_T_23; // @[tlb.scala:58:79] wire _entries_T_22; // @[tlb.scala:58:79] wire _entries_T_21; // @[tlb.scala:58:79] wire _entries_T_20; // @[tlb.scala:58:79] wire _entries_T_19; // @[tlb.scala:58:79] wire _entries_T_18; // @[tlb.scala:58:79] wire _entries_T_17; // @[tlb.scala:58:79] assign _entries_T_17 = _entries_WIRE_3[0]; // @[tlb.scala:58:79] wire _entries_WIRE_2_fragmented_superpage = _entries_T_17; // @[tlb.scala:58:79] assign _entries_T_18 = _entries_WIRE_3[1]; // @[tlb.scala:58:79] wire _entries_WIRE_2_c = _entries_T_18; // @[tlb.scala:58:79] assign _entries_T_19 = _entries_WIRE_3[2]; // @[tlb.scala:58:79] wire _entries_WIRE_2_eff = _entries_T_19; // @[tlb.scala:58:79] assign _entries_T_20 = _entries_WIRE_3[3]; // @[tlb.scala:58:79] wire _entries_WIRE_2_paa = _entries_T_20; // @[tlb.scala:58:79] assign _entries_T_21 = _entries_WIRE_3[4]; // @[tlb.scala:58:79] wire _entries_WIRE_2_pal = _entries_T_21; // @[tlb.scala:58:79] assign _entries_T_22 = _entries_WIRE_3[5]; // @[tlb.scala:58:79] wire _entries_WIRE_2_pr = _entries_T_22; // @[tlb.scala:58:79] assign _entries_T_23 = _entries_WIRE_3[6]; // @[tlb.scala:58:79] wire _entries_WIRE_2_px = _entries_T_23; // @[tlb.scala:58:79] assign _entries_T_24 = _entries_WIRE_3[7]; // @[tlb.scala:58:79] wire _entries_WIRE_2_pw = _entries_T_24; // @[tlb.scala:58:79] assign _entries_T_25 = _entries_WIRE_3[8]; // @[tlb.scala:58:79] wire _entries_WIRE_2_sr = _entries_T_25; // @[tlb.scala:58:79] assign _entries_T_26 = _entries_WIRE_3[9]; // @[tlb.scala:58:79] wire _entries_WIRE_2_sx = _entries_T_26; // @[tlb.scala:58:79] assign _entries_T_27 = _entries_WIRE_3[10]; // @[tlb.scala:58:79] wire _entries_WIRE_2_sw = _entries_T_27; // @[tlb.scala:58:79] assign _entries_T_28 = _entries_WIRE_3[11]; // @[tlb.scala:58:79] wire _entries_WIRE_2_ae = _entries_T_28; // @[tlb.scala:58:79] assign _entries_T_29 = _entries_WIRE_3[12]; // @[tlb.scala:58:79] wire _entries_WIRE_2_g = _entries_T_29; // @[tlb.scala:58:79] assign _entries_T_30 = _entries_WIRE_3[13]; // @[tlb.scala:58:79] wire _entries_WIRE_2_u = _entries_T_30; // @[tlb.scala:58:79] assign _entries_T_31 = _entries_WIRE_3[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_2_ppn = _entries_T_31; // @[tlb.scala:58:79] wire [19:0] _entries_T_47; // @[tlb.scala:58:79] wire _entries_T_46; // @[tlb.scala:58:79] wire _entries_T_45; // @[tlb.scala:58:79] wire _entries_T_44; // @[tlb.scala:58:79] wire _entries_T_43; // @[tlb.scala:58:79] wire _entries_T_42; // @[tlb.scala:58:79] wire _entries_T_41; // @[tlb.scala:58:79] wire _entries_T_40; // @[tlb.scala:58:79] wire _entries_T_39; // @[tlb.scala:58:79] wire _entries_T_38; // @[tlb.scala:58:79] wire _entries_T_37; // @[tlb.scala:58:79] wire _entries_T_36; // @[tlb.scala:58:79] wire _entries_T_35; // @[tlb.scala:58:79] wire _entries_T_34; // @[tlb.scala:58:79] wire _entries_T_33; // @[tlb.scala:58:79] assign _entries_T_33 = _entries_WIRE_5[0]; // @[tlb.scala:58:79] wire _entries_WIRE_4_fragmented_superpage = _entries_T_33; // @[tlb.scala:58:79] assign _entries_T_34 = _entries_WIRE_5[1]; // @[tlb.scala:58:79] wire _entries_WIRE_4_c = _entries_T_34; // @[tlb.scala:58:79] assign _entries_T_35 = _entries_WIRE_5[2]; // @[tlb.scala:58:79] wire _entries_WIRE_4_eff = _entries_T_35; // @[tlb.scala:58:79] assign _entries_T_36 = _entries_WIRE_5[3]; // @[tlb.scala:58:79] wire _entries_WIRE_4_paa = _entries_T_36; // @[tlb.scala:58:79] assign _entries_T_37 = _entries_WIRE_5[4]; // @[tlb.scala:58:79] wire _entries_WIRE_4_pal = _entries_T_37; // @[tlb.scala:58:79] assign _entries_T_38 = _entries_WIRE_5[5]; // @[tlb.scala:58:79] wire _entries_WIRE_4_pr = _entries_T_38; // @[tlb.scala:58:79] assign _entries_T_39 = _entries_WIRE_5[6]; // @[tlb.scala:58:79] wire _entries_WIRE_4_px = _entries_T_39; // @[tlb.scala:58:79] assign _entries_T_40 = _entries_WIRE_5[7]; // @[tlb.scala:58:79] wire _entries_WIRE_4_pw = _entries_T_40; // @[tlb.scala:58:79] assign _entries_T_41 = _entries_WIRE_5[8]; // @[tlb.scala:58:79] wire _entries_WIRE_4_sr = _entries_T_41; // @[tlb.scala:58:79] assign _entries_T_42 = _entries_WIRE_5[9]; // @[tlb.scala:58:79] wire _entries_WIRE_4_sx = _entries_T_42; // @[tlb.scala:58:79] assign _entries_T_43 = _entries_WIRE_5[10]; // @[tlb.scala:58:79] wire _entries_WIRE_4_sw = _entries_T_43; // @[tlb.scala:58:79] assign _entries_T_44 = _entries_WIRE_5[11]; // @[tlb.scala:58:79] wire _entries_WIRE_4_ae = _entries_T_44; // @[tlb.scala:58:79] assign _entries_T_45 = _entries_WIRE_5[12]; // @[tlb.scala:58:79] wire _entries_WIRE_4_g = _entries_T_45; // @[tlb.scala:58:79] assign _entries_T_46 = _entries_WIRE_5[13]; // @[tlb.scala:58:79] wire _entries_WIRE_4_u = _entries_T_46; // @[tlb.scala:58:79] assign _entries_T_47 = _entries_WIRE_5[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_4_ppn = _entries_T_47; // @[tlb.scala:58:79] wire [19:0] _entries_T_63; // @[tlb.scala:58:79] wire _entries_T_62; // @[tlb.scala:58:79] wire _entries_T_61; // @[tlb.scala:58:79] wire _entries_T_60; // @[tlb.scala:58:79] wire _entries_T_59; // @[tlb.scala:58:79] wire _entries_T_58; // @[tlb.scala:58:79] wire _entries_T_57; // @[tlb.scala:58:79] wire _entries_T_56; // @[tlb.scala:58:79] wire _entries_T_55; // @[tlb.scala:58:79] wire _entries_T_54; // @[tlb.scala:58:79] wire _entries_T_53; // @[tlb.scala:58:79] wire _entries_T_52; // @[tlb.scala:58:79] wire _entries_T_51; // @[tlb.scala:58:79] wire _entries_T_50; // @[tlb.scala:58:79] wire _entries_T_49; // @[tlb.scala:58:79] assign _entries_T_49 = _entries_WIRE_7[0]; // @[tlb.scala:58:79] wire _entries_WIRE_6_fragmented_superpage = _entries_T_49; // @[tlb.scala:58:79] assign _entries_T_50 = _entries_WIRE_7[1]; // @[tlb.scala:58:79] wire _entries_WIRE_6_c = _entries_T_50; // @[tlb.scala:58:79] assign _entries_T_51 = _entries_WIRE_7[2]; // @[tlb.scala:58:79] wire _entries_WIRE_6_eff = _entries_T_51; // @[tlb.scala:58:79] assign _entries_T_52 = _entries_WIRE_7[3]; // @[tlb.scala:58:79] wire _entries_WIRE_6_paa = _entries_T_52; // @[tlb.scala:58:79] assign _entries_T_53 = _entries_WIRE_7[4]; // @[tlb.scala:58:79] wire _entries_WIRE_6_pal = _entries_T_53; // @[tlb.scala:58:79] assign _entries_T_54 = _entries_WIRE_7[5]; // @[tlb.scala:58:79] wire _entries_WIRE_6_pr = _entries_T_54; // @[tlb.scala:58:79] assign _entries_T_55 = _entries_WIRE_7[6]; // @[tlb.scala:58:79] wire _entries_WIRE_6_px = _entries_T_55; // @[tlb.scala:58:79] assign _entries_T_56 = _entries_WIRE_7[7]; // @[tlb.scala:58:79] wire _entries_WIRE_6_pw = _entries_T_56; // @[tlb.scala:58:79] assign _entries_T_57 = _entries_WIRE_7[8]; // @[tlb.scala:58:79] wire _entries_WIRE_6_sr = _entries_T_57; // @[tlb.scala:58:79] assign _entries_T_58 = _entries_WIRE_7[9]; // @[tlb.scala:58:79] wire _entries_WIRE_6_sx = _entries_T_58; // @[tlb.scala:58:79] assign _entries_T_59 = _entries_WIRE_7[10]; // @[tlb.scala:58:79] wire _entries_WIRE_6_sw = _entries_T_59; // @[tlb.scala:58:79] assign _entries_T_60 = _entries_WIRE_7[11]; // @[tlb.scala:58:79] wire _entries_WIRE_6_ae = _entries_T_60; // @[tlb.scala:58:79] assign _entries_T_61 = _entries_WIRE_7[12]; // @[tlb.scala:58:79] wire _entries_WIRE_6_g = _entries_T_61; // @[tlb.scala:58:79] assign _entries_T_62 = _entries_WIRE_7[13]; // @[tlb.scala:58:79] wire _entries_WIRE_6_u = _entries_T_62; // @[tlb.scala:58:79] assign _entries_T_63 = _entries_WIRE_7[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_6_ppn = _entries_T_63; // @[tlb.scala:58:79] wire [19:0] _entries_T_79; // @[tlb.scala:58:79] wire _entries_T_78; // @[tlb.scala:58:79] wire _entries_T_77; // @[tlb.scala:58:79] wire _entries_T_76; // @[tlb.scala:58:79] wire _entries_T_75; // @[tlb.scala:58:79] wire _entries_T_74; // @[tlb.scala:58:79] wire _entries_T_73; // @[tlb.scala:58:79] wire _entries_T_72; // @[tlb.scala:58:79] wire _entries_T_71; // @[tlb.scala:58:79] wire _entries_T_70; // @[tlb.scala:58:79] wire _entries_T_69; // @[tlb.scala:58:79] wire _entries_T_68; // @[tlb.scala:58:79] wire _entries_T_67; // @[tlb.scala:58:79] wire _entries_T_66; // @[tlb.scala:58:79] wire _entries_T_65; // @[tlb.scala:58:79] assign _entries_T_65 = _entries_WIRE_9[0]; // @[tlb.scala:58:79] wire _entries_WIRE_8_fragmented_superpage = _entries_T_65; // @[tlb.scala:58:79] assign _entries_T_66 = _entries_WIRE_9[1]; // @[tlb.scala:58:79] wire _entries_WIRE_8_c = _entries_T_66; // @[tlb.scala:58:79] assign _entries_T_67 = _entries_WIRE_9[2]; // @[tlb.scala:58:79] wire _entries_WIRE_8_eff = _entries_T_67; // @[tlb.scala:58:79] assign _entries_T_68 = _entries_WIRE_9[3]; // @[tlb.scala:58:79] wire _entries_WIRE_8_paa = _entries_T_68; // @[tlb.scala:58:79] assign _entries_T_69 = _entries_WIRE_9[4]; // @[tlb.scala:58:79] wire _entries_WIRE_8_pal = _entries_T_69; // @[tlb.scala:58:79] assign _entries_T_70 = _entries_WIRE_9[5]; // @[tlb.scala:58:79] wire _entries_WIRE_8_pr = _entries_T_70; // @[tlb.scala:58:79] assign _entries_T_71 = _entries_WIRE_9[6]; // @[tlb.scala:58:79] wire _entries_WIRE_8_px = _entries_T_71; // @[tlb.scala:58:79] assign _entries_T_72 = _entries_WIRE_9[7]; // @[tlb.scala:58:79] wire _entries_WIRE_8_pw = _entries_T_72; // @[tlb.scala:58:79] assign _entries_T_73 = _entries_WIRE_9[8]; // @[tlb.scala:58:79] wire _entries_WIRE_8_sr = _entries_T_73; // @[tlb.scala:58:79] assign _entries_T_74 = _entries_WIRE_9[9]; // @[tlb.scala:58:79] wire _entries_WIRE_8_sx = _entries_T_74; // @[tlb.scala:58:79] assign _entries_T_75 = _entries_WIRE_9[10]; // @[tlb.scala:58:79] wire _entries_WIRE_8_sw = _entries_T_75; // @[tlb.scala:58:79] assign _entries_T_76 = _entries_WIRE_9[11]; // @[tlb.scala:58:79] wire _entries_WIRE_8_ae = _entries_T_76; // @[tlb.scala:58:79] assign _entries_T_77 = _entries_WIRE_9[12]; // @[tlb.scala:58:79] wire _entries_WIRE_8_g = _entries_T_77; // @[tlb.scala:58:79] assign _entries_T_78 = _entries_WIRE_9[13]; // @[tlb.scala:58:79] wire _entries_WIRE_8_u = _entries_T_78; // @[tlb.scala:58:79] assign _entries_T_79 = _entries_WIRE_9[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_8_ppn = _entries_T_79; // @[tlb.scala:58:79] wire [19:0] _entries_T_95; // @[tlb.scala:58:79] wire _entries_T_94; // @[tlb.scala:58:79] wire _entries_T_93; // @[tlb.scala:58:79] wire _entries_T_92; // @[tlb.scala:58:79] wire _entries_T_91; // @[tlb.scala:58:79] wire _entries_T_90; // @[tlb.scala:58:79] wire _entries_T_89; // @[tlb.scala:58:79] wire _entries_T_88; // @[tlb.scala:58:79] wire _entries_T_87; // @[tlb.scala:58:79] wire _entries_T_86; // @[tlb.scala:58:79] wire _entries_T_85; // @[tlb.scala:58:79] wire _entries_T_84; // @[tlb.scala:58:79] wire _entries_T_83; // @[tlb.scala:58:79] wire _entries_T_82; // @[tlb.scala:58:79] wire _entries_T_81; // @[tlb.scala:58:79] assign _entries_T_81 = _entries_WIRE_11[0]; // @[tlb.scala:58:79] wire _entries_WIRE_10_fragmented_superpage = _entries_T_81; // @[tlb.scala:58:79] assign _entries_T_82 = _entries_WIRE_11[1]; // @[tlb.scala:58:79] wire _entries_WIRE_10_c = _entries_T_82; // @[tlb.scala:58:79] assign _entries_T_83 = _entries_WIRE_11[2]; // @[tlb.scala:58:79] wire _entries_WIRE_10_eff = _entries_T_83; // @[tlb.scala:58:79] assign _entries_T_84 = _entries_WIRE_11[3]; // @[tlb.scala:58:79] wire _entries_WIRE_10_paa = _entries_T_84; // @[tlb.scala:58:79] assign _entries_T_85 = _entries_WIRE_11[4]; // @[tlb.scala:58:79] wire _entries_WIRE_10_pal = _entries_T_85; // @[tlb.scala:58:79] assign _entries_T_86 = _entries_WIRE_11[5]; // @[tlb.scala:58:79] wire _entries_WIRE_10_pr = _entries_T_86; // @[tlb.scala:58:79] assign _entries_T_87 = _entries_WIRE_11[6]; // @[tlb.scala:58:79] wire _entries_WIRE_10_px = _entries_T_87; // @[tlb.scala:58:79] assign _entries_T_88 = _entries_WIRE_11[7]; // @[tlb.scala:58:79] wire _entries_WIRE_10_pw = _entries_T_88; // @[tlb.scala:58:79] assign _entries_T_89 = _entries_WIRE_11[8]; // @[tlb.scala:58:79] wire _entries_WIRE_10_sr = _entries_T_89; // @[tlb.scala:58:79] assign _entries_T_90 = _entries_WIRE_11[9]; // @[tlb.scala:58:79] wire _entries_WIRE_10_sx = _entries_T_90; // @[tlb.scala:58:79] assign _entries_T_91 = _entries_WIRE_11[10]; // @[tlb.scala:58:79] wire _entries_WIRE_10_sw = _entries_T_91; // @[tlb.scala:58:79] assign _entries_T_92 = _entries_WIRE_11[11]; // @[tlb.scala:58:79] wire _entries_WIRE_10_ae = _entries_T_92; // @[tlb.scala:58:79] assign _entries_T_93 = _entries_WIRE_11[12]; // @[tlb.scala:58:79] wire _entries_WIRE_10_g = _entries_T_93; // @[tlb.scala:58:79] assign _entries_T_94 = _entries_WIRE_11[13]; // @[tlb.scala:58:79] wire _entries_WIRE_10_u = _entries_T_94; // @[tlb.scala:58:79] assign _entries_T_95 = _entries_WIRE_11[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_10_ppn = _entries_T_95; // @[tlb.scala:58:79] wire [19:0] _entries_T_111; // @[tlb.scala:58:79] wire _entries_T_110; // @[tlb.scala:58:79] wire _entries_T_109; // @[tlb.scala:58:79] wire _entries_T_108; // @[tlb.scala:58:79] wire _entries_T_107; // @[tlb.scala:58:79] wire _entries_T_106; // @[tlb.scala:58:79] wire _entries_T_105; // @[tlb.scala:58:79] wire _entries_T_104; // @[tlb.scala:58:79] wire _entries_T_103; // @[tlb.scala:58:79] wire _entries_T_102; // @[tlb.scala:58:79] wire _entries_T_101; // @[tlb.scala:58:79] wire _entries_T_100; // @[tlb.scala:58:79] wire _entries_T_99; // @[tlb.scala:58:79] wire _entries_T_98; // @[tlb.scala:58:79] wire _entries_T_97; // @[tlb.scala:58:79] assign _entries_T_97 = _entries_WIRE_13[0]; // @[tlb.scala:58:79] wire _entries_WIRE_12_fragmented_superpage = _entries_T_97; // @[tlb.scala:58:79] assign _entries_T_98 = _entries_WIRE_13[1]; // @[tlb.scala:58:79] wire _entries_WIRE_12_c = _entries_T_98; // @[tlb.scala:58:79] assign _entries_T_99 = _entries_WIRE_13[2]; // @[tlb.scala:58:79] wire _entries_WIRE_12_eff = _entries_T_99; // @[tlb.scala:58:79] assign _entries_T_100 = _entries_WIRE_13[3]; // @[tlb.scala:58:79] wire _entries_WIRE_12_paa = _entries_T_100; // @[tlb.scala:58:79] assign _entries_T_101 = _entries_WIRE_13[4]; // @[tlb.scala:58:79] wire _entries_WIRE_12_pal = _entries_T_101; // @[tlb.scala:58:79] assign _entries_T_102 = _entries_WIRE_13[5]; // @[tlb.scala:58:79] wire _entries_WIRE_12_pr = _entries_T_102; // @[tlb.scala:58:79] assign _entries_T_103 = _entries_WIRE_13[6]; // @[tlb.scala:58:79] wire _entries_WIRE_12_px = _entries_T_103; // @[tlb.scala:58:79] assign _entries_T_104 = _entries_WIRE_13[7]; // @[tlb.scala:58:79] wire _entries_WIRE_12_pw = _entries_T_104; // @[tlb.scala:58:79] assign _entries_T_105 = _entries_WIRE_13[8]; // @[tlb.scala:58:79] wire _entries_WIRE_12_sr = _entries_T_105; // @[tlb.scala:58:79] assign _entries_T_106 = _entries_WIRE_13[9]; // @[tlb.scala:58:79] wire _entries_WIRE_12_sx = _entries_T_106; // @[tlb.scala:58:79] assign _entries_T_107 = _entries_WIRE_13[10]; // @[tlb.scala:58:79] wire _entries_WIRE_12_sw = _entries_T_107; // @[tlb.scala:58:79] assign _entries_T_108 = _entries_WIRE_13[11]; // @[tlb.scala:58:79] wire _entries_WIRE_12_ae = _entries_T_108; // @[tlb.scala:58:79] assign _entries_T_109 = _entries_WIRE_13[12]; // @[tlb.scala:58:79] wire _entries_WIRE_12_g = _entries_T_109; // @[tlb.scala:58:79] assign _entries_T_110 = _entries_WIRE_13[13]; // @[tlb.scala:58:79] wire _entries_WIRE_12_u = _entries_T_110; // @[tlb.scala:58:79] assign _entries_T_111 = _entries_WIRE_13[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_12_ppn = _entries_T_111; // @[tlb.scala:58:79] wire [19:0] _entries_T_127; // @[tlb.scala:58:79] wire _entries_T_126; // @[tlb.scala:58:79] wire _entries_T_125; // @[tlb.scala:58:79] wire _entries_T_124; // @[tlb.scala:58:79] wire _entries_T_123; // @[tlb.scala:58:79] wire _entries_T_122; // @[tlb.scala:58:79] wire _entries_T_121; // @[tlb.scala:58:79] wire _entries_T_120; // @[tlb.scala:58:79] wire _entries_T_119; // @[tlb.scala:58:79] wire _entries_T_118; // @[tlb.scala:58:79] wire _entries_T_117; // @[tlb.scala:58:79] wire _entries_T_116; // @[tlb.scala:58:79] wire _entries_T_115; // @[tlb.scala:58:79] wire _entries_T_114; // @[tlb.scala:58:79] wire _entries_T_113; // @[tlb.scala:58:79] assign _entries_T_113 = _entries_WIRE_15[0]; // @[tlb.scala:58:79] wire _entries_WIRE_14_fragmented_superpage = _entries_T_113; // @[tlb.scala:58:79] assign _entries_T_114 = _entries_WIRE_15[1]; // @[tlb.scala:58:79] wire _entries_WIRE_14_c = _entries_T_114; // @[tlb.scala:58:79] assign _entries_T_115 = _entries_WIRE_15[2]; // @[tlb.scala:58:79] wire _entries_WIRE_14_eff = _entries_T_115; // @[tlb.scala:58:79] assign _entries_T_116 = _entries_WIRE_15[3]; // @[tlb.scala:58:79] wire _entries_WIRE_14_paa = _entries_T_116; // @[tlb.scala:58:79] assign _entries_T_117 = _entries_WIRE_15[4]; // @[tlb.scala:58:79] wire _entries_WIRE_14_pal = _entries_T_117; // @[tlb.scala:58:79] assign _entries_T_118 = _entries_WIRE_15[5]; // @[tlb.scala:58:79] wire _entries_WIRE_14_pr = _entries_T_118; // @[tlb.scala:58:79] assign _entries_T_119 = _entries_WIRE_15[6]; // @[tlb.scala:58:79] wire _entries_WIRE_14_px = _entries_T_119; // @[tlb.scala:58:79] assign _entries_T_120 = _entries_WIRE_15[7]; // @[tlb.scala:58:79] wire _entries_WIRE_14_pw = _entries_T_120; // @[tlb.scala:58:79] assign _entries_T_121 = _entries_WIRE_15[8]; // @[tlb.scala:58:79] wire _entries_WIRE_14_sr = _entries_T_121; // @[tlb.scala:58:79] assign _entries_T_122 = _entries_WIRE_15[9]; // @[tlb.scala:58:79] wire _entries_WIRE_14_sx = _entries_T_122; // @[tlb.scala:58:79] assign _entries_T_123 = _entries_WIRE_15[10]; // @[tlb.scala:58:79] wire _entries_WIRE_14_sw = _entries_T_123; // @[tlb.scala:58:79] assign _entries_T_124 = _entries_WIRE_15[11]; // @[tlb.scala:58:79] wire _entries_WIRE_14_ae = _entries_T_124; // @[tlb.scala:58:79] assign _entries_T_125 = _entries_WIRE_15[12]; // @[tlb.scala:58:79] wire _entries_WIRE_14_g = _entries_T_125; // @[tlb.scala:58:79] assign _entries_T_126 = _entries_WIRE_15[13]; // @[tlb.scala:58:79] wire _entries_WIRE_14_u = _entries_T_126; // @[tlb.scala:58:79] assign _entries_T_127 = _entries_WIRE_15[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_14_ppn = _entries_T_127; // @[tlb.scala:58:79] wire [19:0] _entries_T_142; // @[tlb.scala:58:79] wire _entries_T_141; // @[tlb.scala:58:79] wire _entries_T_140; // @[tlb.scala:58:79] wire _entries_T_139; // @[tlb.scala:58:79] wire _entries_T_138; // @[tlb.scala:58:79] wire _entries_T_137; // @[tlb.scala:58:79] wire _entries_T_136; // @[tlb.scala:58:79] wire _entries_T_135; // @[tlb.scala:58:79] wire _entries_T_134; // @[tlb.scala:58:79] wire _entries_T_133; // @[tlb.scala:58:79] wire _entries_T_132; // @[tlb.scala:58:79] wire _entries_T_131; // @[tlb.scala:58:79] wire _entries_T_130; // @[tlb.scala:58:79] wire _entries_T_129; // @[tlb.scala:58:79] wire _entries_T_128; // @[tlb.scala:58:79] assign _entries_T_128 = _entries_WIRE_17[0]; // @[tlb.scala:58:79] wire _entries_WIRE_16_fragmented_superpage = _entries_T_128; // @[tlb.scala:58:79] assign _entries_T_129 = _entries_WIRE_17[1]; // @[tlb.scala:58:79] wire _entries_WIRE_16_c = _entries_T_129; // @[tlb.scala:58:79] assign _entries_T_130 = _entries_WIRE_17[2]; // @[tlb.scala:58:79] wire _entries_WIRE_16_eff = _entries_T_130; // @[tlb.scala:58:79] assign _entries_T_131 = _entries_WIRE_17[3]; // @[tlb.scala:58:79] wire _entries_WIRE_16_paa = _entries_T_131; // @[tlb.scala:58:79] assign _entries_T_132 = _entries_WIRE_17[4]; // @[tlb.scala:58:79] wire _entries_WIRE_16_pal = _entries_T_132; // @[tlb.scala:58:79] assign _entries_T_133 = _entries_WIRE_17[5]; // @[tlb.scala:58:79] wire _entries_WIRE_16_pr = _entries_T_133; // @[tlb.scala:58:79] assign _entries_T_134 = _entries_WIRE_17[6]; // @[tlb.scala:58:79] wire _entries_WIRE_16_px = _entries_T_134; // @[tlb.scala:58:79] assign _entries_T_135 = _entries_WIRE_17[7]; // @[tlb.scala:58:79] wire _entries_WIRE_16_pw = _entries_T_135; // @[tlb.scala:58:79] assign _entries_T_136 = _entries_WIRE_17[8]; // @[tlb.scala:58:79] wire _entries_WIRE_16_sr = _entries_T_136; // @[tlb.scala:58:79] assign _entries_T_137 = _entries_WIRE_17[9]; // @[tlb.scala:58:79] wire _entries_WIRE_16_sx = _entries_T_137; // @[tlb.scala:58:79] assign _entries_T_138 = _entries_WIRE_17[10]; // @[tlb.scala:58:79] wire _entries_WIRE_16_sw = _entries_T_138; // @[tlb.scala:58:79] assign _entries_T_139 = _entries_WIRE_17[11]; // @[tlb.scala:58:79] wire _entries_WIRE_16_ae = _entries_T_139; // @[tlb.scala:58:79] assign _entries_T_140 = _entries_WIRE_17[12]; // @[tlb.scala:58:79] wire _entries_WIRE_16_g = _entries_T_140; // @[tlb.scala:58:79] assign _entries_T_141 = _entries_WIRE_17[13]; // @[tlb.scala:58:79] wire _entries_WIRE_16_u = _entries_T_141; // @[tlb.scala:58:79] assign _entries_T_142 = _entries_WIRE_17[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_16_ppn = _entries_T_142; // @[tlb.scala:58:79] wire [19:0] _entries_T_157; // @[tlb.scala:58:79] wire _entries_T_156; // @[tlb.scala:58:79] wire _entries_T_155; // @[tlb.scala:58:79] wire _entries_T_154; // @[tlb.scala:58:79] wire _entries_T_153; // @[tlb.scala:58:79] wire _entries_T_152; // @[tlb.scala:58:79] wire _entries_T_151; // @[tlb.scala:58:79] wire _entries_T_150; // @[tlb.scala:58:79] wire _entries_T_149; // @[tlb.scala:58:79] wire _entries_T_148; // @[tlb.scala:58:79] wire _entries_T_147; // @[tlb.scala:58:79] wire _entries_T_146; // @[tlb.scala:58:79] wire _entries_T_145; // @[tlb.scala:58:79] wire _entries_T_144; // @[tlb.scala:58:79] wire _entries_T_143; // @[tlb.scala:58:79] assign _entries_T_143 = _entries_WIRE_19[0]; // @[tlb.scala:58:79] wire _entries_WIRE_18_fragmented_superpage = _entries_T_143; // @[tlb.scala:58:79] assign _entries_T_144 = _entries_WIRE_19[1]; // @[tlb.scala:58:79] wire _entries_WIRE_18_c = _entries_T_144; // @[tlb.scala:58:79] assign _entries_T_145 = _entries_WIRE_19[2]; // @[tlb.scala:58:79] wire _entries_WIRE_18_eff = _entries_T_145; // @[tlb.scala:58:79] assign _entries_T_146 = _entries_WIRE_19[3]; // @[tlb.scala:58:79] wire _entries_WIRE_18_paa = _entries_T_146; // @[tlb.scala:58:79] assign _entries_T_147 = _entries_WIRE_19[4]; // @[tlb.scala:58:79] wire _entries_WIRE_18_pal = _entries_T_147; // @[tlb.scala:58:79] assign _entries_T_148 = _entries_WIRE_19[5]; // @[tlb.scala:58:79] wire _entries_WIRE_18_pr = _entries_T_148; // @[tlb.scala:58:79] assign _entries_T_149 = _entries_WIRE_19[6]; // @[tlb.scala:58:79] wire _entries_WIRE_18_px = _entries_T_149; // @[tlb.scala:58:79] assign _entries_T_150 = _entries_WIRE_19[7]; // @[tlb.scala:58:79] wire _entries_WIRE_18_pw = _entries_T_150; // @[tlb.scala:58:79] assign _entries_T_151 = _entries_WIRE_19[8]; // @[tlb.scala:58:79] wire _entries_WIRE_18_sr = _entries_T_151; // @[tlb.scala:58:79] assign _entries_T_152 = _entries_WIRE_19[9]; // @[tlb.scala:58:79] wire _entries_WIRE_18_sx = _entries_T_152; // @[tlb.scala:58:79] assign _entries_T_153 = _entries_WIRE_19[10]; // @[tlb.scala:58:79] wire _entries_WIRE_18_sw = _entries_T_153; // @[tlb.scala:58:79] assign _entries_T_154 = _entries_WIRE_19[11]; // @[tlb.scala:58:79] wire _entries_WIRE_18_ae = _entries_T_154; // @[tlb.scala:58:79] assign _entries_T_155 = _entries_WIRE_19[12]; // @[tlb.scala:58:79] wire _entries_WIRE_18_g = _entries_T_155; // @[tlb.scala:58:79] assign _entries_T_156 = _entries_WIRE_19[13]; // @[tlb.scala:58:79] wire _entries_WIRE_18_u = _entries_T_156; // @[tlb.scala:58:79] assign _entries_T_157 = _entries_WIRE_19[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_18_ppn = _entries_T_157; // @[tlb.scala:58:79] wire [19:0] _entries_T_172; // @[tlb.scala:58:79] wire _entries_T_171; // @[tlb.scala:58:79] wire _entries_T_170; // @[tlb.scala:58:79] wire _entries_T_169; // @[tlb.scala:58:79] wire _entries_T_168; // @[tlb.scala:58:79] wire _entries_T_167; // @[tlb.scala:58:79] wire _entries_T_166; // @[tlb.scala:58:79] wire _entries_T_165; // @[tlb.scala:58:79] wire _entries_T_164; // @[tlb.scala:58:79] wire _entries_T_163; // @[tlb.scala:58:79] wire _entries_T_162; // @[tlb.scala:58:79] wire _entries_T_161; // @[tlb.scala:58:79] wire _entries_T_160; // @[tlb.scala:58:79] wire _entries_T_159; // @[tlb.scala:58:79] wire _entries_T_158; // @[tlb.scala:58:79] assign _entries_T_158 = _entries_WIRE_21[0]; // @[tlb.scala:58:79] wire _entries_WIRE_20_fragmented_superpage = _entries_T_158; // @[tlb.scala:58:79] assign _entries_T_159 = _entries_WIRE_21[1]; // @[tlb.scala:58:79] wire _entries_WIRE_20_c = _entries_T_159; // @[tlb.scala:58:79] assign _entries_T_160 = _entries_WIRE_21[2]; // @[tlb.scala:58:79] wire _entries_WIRE_20_eff = _entries_T_160; // @[tlb.scala:58:79] assign _entries_T_161 = _entries_WIRE_21[3]; // @[tlb.scala:58:79] wire _entries_WIRE_20_paa = _entries_T_161; // @[tlb.scala:58:79] assign _entries_T_162 = _entries_WIRE_21[4]; // @[tlb.scala:58:79] wire _entries_WIRE_20_pal = _entries_T_162; // @[tlb.scala:58:79] assign _entries_T_163 = _entries_WIRE_21[5]; // @[tlb.scala:58:79] wire _entries_WIRE_20_pr = _entries_T_163; // @[tlb.scala:58:79] assign _entries_T_164 = _entries_WIRE_21[6]; // @[tlb.scala:58:79] wire _entries_WIRE_20_px = _entries_T_164; // @[tlb.scala:58:79] assign _entries_T_165 = _entries_WIRE_21[7]; // @[tlb.scala:58:79] wire _entries_WIRE_20_pw = _entries_T_165; // @[tlb.scala:58:79] assign _entries_T_166 = _entries_WIRE_21[8]; // @[tlb.scala:58:79] wire _entries_WIRE_20_sr = _entries_T_166; // @[tlb.scala:58:79] assign _entries_T_167 = _entries_WIRE_21[9]; // @[tlb.scala:58:79] wire _entries_WIRE_20_sx = _entries_T_167; // @[tlb.scala:58:79] assign _entries_T_168 = _entries_WIRE_21[10]; // @[tlb.scala:58:79] wire _entries_WIRE_20_sw = _entries_T_168; // @[tlb.scala:58:79] assign _entries_T_169 = _entries_WIRE_21[11]; // @[tlb.scala:58:79] wire _entries_WIRE_20_ae = _entries_T_169; // @[tlb.scala:58:79] assign _entries_T_170 = _entries_WIRE_21[12]; // @[tlb.scala:58:79] wire _entries_WIRE_20_g = _entries_T_170; // @[tlb.scala:58:79] assign _entries_T_171 = _entries_WIRE_21[13]; // @[tlb.scala:58:79] wire _entries_WIRE_20_u = _entries_T_171; // @[tlb.scala:58:79] assign _entries_T_172 = _entries_WIRE_21[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_20_ppn = _entries_T_172; // @[tlb.scala:58:79] wire [19:0] _entries_T_187; // @[tlb.scala:58:79] wire _entries_T_186; // @[tlb.scala:58:79] wire _entries_T_185; // @[tlb.scala:58:79] wire _entries_T_184; // @[tlb.scala:58:79] wire _entries_T_183; // @[tlb.scala:58:79] wire _entries_T_182; // @[tlb.scala:58:79] wire _entries_T_181; // @[tlb.scala:58:79] wire _entries_T_180; // @[tlb.scala:58:79] wire _entries_T_179; // @[tlb.scala:58:79] wire _entries_T_178; // @[tlb.scala:58:79] wire _entries_T_177; // @[tlb.scala:58:79] wire _entries_T_176; // @[tlb.scala:58:79] wire _entries_T_175; // @[tlb.scala:58:79] wire _entries_T_174; // @[tlb.scala:58:79] wire _entries_T_173; // @[tlb.scala:58:79] assign _entries_T_173 = _entries_WIRE_23[0]; // @[tlb.scala:58:79] wire _entries_WIRE_22_fragmented_superpage = _entries_T_173; // @[tlb.scala:58:79] assign _entries_T_174 = _entries_WIRE_23[1]; // @[tlb.scala:58:79] wire _entries_WIRE_22_c = _entries_T_174; // @[tlb.scala:58:79] assign _entries_T_175 = _entries_WIRE_23[2]; // @[tlb.scala:58:79] wire _entries_WIRE_22_eff = _entries_T_175; // @[tlb.scala:58:79] assign _entries_T_176 = _entries_WIRE_23[3]; // @[tlb.scala:58:79] wire _entries_WIRE_22_paa = _entries_T_176; // @[tlb.scala:58:79] assign _entries_T_177 = _entries_WIRE_23[4]; // @[tlb.scala:58:79] wire _entries_WIRE_22_pal = _entries_T_177; // @[tlb.scala:58:79] assign _entries_T_178 = _entries_WIRE_23[5]; // @[tlb.scala:58:79] wire _entries_WIRE_22_pr = _entries_T_178; // @[tlb.scala:58:79] assign _entries_T_179 = _entries_WIRE_23[6]; // @[tlb.scala:58:79] wire _entries_WIRE_22_px = _entries_T_179; // @[tlb.scala:58:79] assign _entries_T_180 = _entries_WIRE_23[7]; // @[tlb.scala:58:79] wire _entries_WIRE_22_pw = _entries_T_180; // @[tlb.scala:58:79] assign _entries_T_181 = _entries_WIRE_23[8]; // @[tlb.scala:58:79] wire _entries_WIRE_22_sr = _entries_T_181; // @[tlb.scala:58:79] assign _entries_T_182 = _entries_WIRE_23[9]; // @[tlb.scala:58:79] wire _entries_WIRE_22_sx = _entries_T_182; // @[tlb.scala:58:79] assign _entries_T_183 = _entries_WIRE_23[10]; // @[tlb.scala:58:79] wire _entries_WIRE_22_sw = _entries_T_183; // @[tlb.scala:58:79] assign _entries_T_184 = _entries_WIRE_23[11]; // @[tlb.scala:58:79] wire _entries_WIRE_22_ae = _entries_T_184; // @[tlb.scala:58:79] assign _entries_T_185 = _entries_WIRE_23[12]; // @[tlb.scala:58:79] wire _entries_WIRE_22_g = _entries_T_185; // @[tlb.scala:58:79] assign _entries_T_186 = _entries_WIRE_23[13]; // @[tlb.scala:58:79] wire _entries_WIRE_22_u = _entries_T_186; // @[tlb.scala:58:79] assign _entries_T_187 = _entries_WIRE_23[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_22_ppn = _entries_T_187; // @[tlb.scala:58:79] wire [19:0] _entries_T_202; // @[tlb.scala:58:79] wire _entries_T_201; // @[tlb.scala:58:79] wire _entries_T_200; // @[tlb.scala:58:79] wire _entries_T_199; // @[tlb.scala:58:79] wire _entries_T_198; // @[tlb.scala:58:79] wire _entries_T_197; // @[tlb.scala:58:79] wire _entries_T_196; // @[tlb.scala:58:79] wire _entries_T_195; // @[tlb.scala:58:79] wire _entries_T_194; // @[tlb.scala:58:79] wire _entries_T_193; // @[tlb.scala:58:79] wire _entries_T_192; // @[tlb.scala:58:79] wire _entries_T_191; // @[tlb.scala:58:79] wire _entries_T_190; // @[tlb.scala:58:79] wire _entries_T_189; // @[tlb.scala:58:79] wire _entries_T_188; // @[tlb.scala:58:79] assign _entries_T_188 = _entries_WIRE_25[0]; // @[tlb.scala:58:79] wire _entries_WIRE_24_fragmented_superpage = _entries_T_188; // @[tlb.scala:58:79] assign _entries_T_189 = _entries_WIRE_25[1]; // @[tlb.scala:58:79] wire _entries_WIRE_24_c = _entries_T_189; // @[tlb.scala:58:79] assign _entries_T_190 = _entries_WIRE_25[2]; // @[tlb.scala:58:79] wire _entries_WIRE_24_eff = _entries_T_190; // @[tlb.scala:58:79] assign _entries_T_191 = _entries_WIRE_25[3]; // @[tlb.scala:58:79] wire _entries_WIRE_24_paa = _entries_T_191; // @[tlb.scala:58:79] assign _entries_T_192 = _entries_WIRE_25[4]; // @[tlb.scala:58:79] wire _entries_WIRE_24_pal = _entries_T_192; // @[tlb.scala:58:79] assign _entries_T_193 = _entries_WIRE_25[5]; // @[tlb.scala:58:79] wire _entries_WIRE_24_pr = _entries_T_193; // @[tlb.scala:58:79] assign _entries_T_194 = _entries_WIRE_25[6]; // @[tlb.scala:58:79] wire _entries_WIRE_24_px = _entries_T_194; // @[tlb.scala:58:79] assign _entries_T_195 = _entries_WIRE_25[7]; // @[tlb.scala:58:79] wire _entries_WIRE_24_pw = _entries_T_195; // @[tlb.scala:58:79] assign _entries_T_196 = _entries_WIRE_25[8]; // @[tlb.scala:58:79] wire _entries_WIRE_24_sr = _entries_T_196; // @[tlb.scala:58:79] assign _entries_T_197 = _entries_WIRE_25[9]; // @[tlb.scala:58:79] wire _entries_WIRE_24_sx = _entries_T_197; // @[tlb.scala:58:79] assign _entries_T_198 = _entries_WIRE_25[10]; // @[tlb.scala:58:79] wire _entries_WIRE_24_sw = _entries_T_198; // @[tlb.scala:58:79] assign _entries_T_199 = _entries_WIRE_25[11]; // @[tlb.scala:58:79] wire _entries_WIRE_24_ae = _entries_T_199; // @[tlb.scala:58:79] assign _entries_T_200 = _entries_WIRE_25[12]; // @[tlb.scala:58:79] wire _entries_WIRE_24_g = _entries_T_200; // @[tlb.scala:58:79] assign _entries_T_201 = _entries_WIRE_25[13]; // @[tlb.scala:58:79] wire _entries_WIRE_24_u = _entries_T_201; // @[tlb.scala:58:79] assign _entries_T_202 = _entries_WIRE_25[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_24_ppn = _entries_T_202; // @[tlb.scala:58:79] wire [19:0] entries_0_0_ppn = _entries_WIRE_26_0_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_0_u = _entries_WIRE_26_0_u; // @[tlb.scala:119:49, :211:38] wire entries_0_0_g = _entries_WIRE_26_0_g; // @[tlb.scala:119:49, :211:38] wire entries_0_0_ae = _entries_WIRE_26_0_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_0_sw = _entries_WIRE_26_0_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_0_sx = _entries_WIRE_26_0_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_0_sr = _entries_WIRE_26_0_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_0_pw = _entries_WIRE_26_0_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_0_px = _entries_WIRE_26_0_px; // @[tlb.scala:119:49, :211:38] wire entries_0_0_pr = _entries_WIRE_26_0_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_0_pal = _entries_WIRE_26_0_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_0_paa = _entries_WIRE_26_0_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_0_eff = _entries_WIRE_26_0_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_0_c = _entries_WIRE_26_0_c; // @[tlb.scala:119:49, :211:38] wire entries_0_0_fragmented_superpage = _entries_WIRE_26_0_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_1_ppn = _entries_WIRE_26_1_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_1_u = _entries_WIRE_26_1_u; // @[tlb.scala:119:49, :211:38] wire entries_0_1_g = _entries_WIRE_26_1_g; // @[tlb.scala:119:49, :211:38] wire entries_0_1_ae = _entries_WIRE_26_1_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_1_sw = _entries_WIRE_26_1_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_1_sx = _entries_WIRE_26_1_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_1_sr = _entries_WIRE_26_1_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_1_pw = _entries_WIRE_26_1_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_1_px = _entries_WIRE_26_1_px; // @[tlb.scala:119:49, :211:38] wire entries_0_1_pr = _entries_WIRE_26_1_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_1_pal = _entries_WIRE_26_1_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_1_paa = _entries_WIRE_26_1_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_1_eff = _entries_WIRE_26_1_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_1_c = _entries_WIRE_26_1_c; // @[tlb.scala:119:49, :211:38] wire entries_0_1_fragmented_superpage = _entries_WIRE_26_1_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_2_ppn = _entries_WIRE_26_2_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_2_u = _entries_WIRE_26_2_u; // @[tlb.scala:119:49, :211:38] wire entries_0_2_g = _entries_WIRE_26_2_g; // @[tlb.scala:119:49, :211:38] wire entries_0_2_ae = _entries_WIRE_26_2_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_2_sw = _entries_WIRE_26_2_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_2_sx = _entries_WIRE_26_2_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_2_sr = _entries_WIRE_26_2_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_2_pw = _entries_WIRE_26_2_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_2_px = _entries_WIRE_26_2_px; // @[tlb.scala:119:49, :211:38] wire entries_0_2_pr = _entries_WIRE_26_2_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_2_pal = _entries_WIRE_26_2_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_2_paa = _entries_WIRE_26_2_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_2_eff = _entries_WIRE_26_2_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_2_c = _entries_WIRE_26_2_c; // @[tlb.scala:119:49, :211:38] wire entries_0_2_fragmented_superpage = _entries_WIRE_26_2_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_3_ppn = _entries_WIRE_26_3_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_3_u = _entries_WIRE_26_3_u; // @[tlb.scala:119:49, :211:38] wire entries_0_3_g = _entries_WIRE_26_3_g; // @[tlb.scala:119:49, :211:38] wire entries_0_3_ae = _entries_WIRE_26_3_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_3_sw = _entries_WIRE_26_3_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_3_sx = _entries_WIRE_26_3_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_3_sr = _entries_WIRE_26_3_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_3_pw = _entries_WIRE_26_3_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_3_px = _entries_WIRE_26_3_px; // @[tlb.scala:119:49, :211:38] wire entries_0_3_pr = _entries_WIRE_26_3_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_3_pal = _entries_WIRE_26_3_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_3_paa = _entries_WIRE_26_3_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_3_eff = _entries_WIRE_26_3_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_3_c = _entries_WIRE_26_3_c; // @[tlb.scala:119:49, :211:38] wire entries_0_3_fragmented_superpage = _entries_WIRE_26_3_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_4_ppn = _entries_WIRE_26_4_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_4_u = _entries_WIRE_26_4_u; // @[tlb.scala:119:49, :211:38] wire entries_0_4_g = _entries_WIRE_26_4_g; // @[tlb.scala:119:49, :211:38] wire entries_0_4_ae = _entries_WIRE_26_4_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_4_sw = _entries_WIRE_26_4_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_4_sx = _entries_WIRE_26_4_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_4_sr = _entries_WIRE_26_4_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_4_pw = _entries_WIRE_26_4_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_4_px = _entries_WIRE_26_4_px; // @[tlb.scala:119:49, :211:38] wire entries_0_4_pr = _entries_WIRE_26_4_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_4_pal = _entries_WIRE_26_4_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_4_paa = _entries_WIRE_26_4_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_4_eff = _entries_WIRE_26_4_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_4_c = _entries_WIRE_26_4_c; // @[tlb.scala:119:49, :211:38] wire entries_0_4_fragmented_superpage = _entries_WIRE_26_4_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_5_ppn = _entries_WIRE_26_5_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_5_u = _entries_WIRE_26_5_u; // @[tlb.scala:119:49, :211:38] wire entries_0_5_g = _entries_WIRE_26_5_g; // @[tlb.scala:119:49, :211:38] wire entries_0_5_ae = _entries_WIRE_26_5_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_5_sw = _entries_WIRE_26_5_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_5_sx = _entries_WIRE_26_5_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_5_sr = _entries_WIRE_26_5_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_5_pw = _entries_WIRE_26_5_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_5_px = _entries_WIRE_26_5_px; // @[tlb.scala:119:49, :211:38] wire entries_0_5_pr = _entries_WIRE_26_5_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_5_pal = _entries_WIRE_26_5_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_5_paa = _entries_WIRE_26_5_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_5_eff = _entries_WIRE_26_5_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_5_c = _entries_WIRE_26_5_c; // @[tlb.scala:119:49, :211:38] wire entries_0_5_fragmented_superpage = _entries_WIRE_26_5_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_6_ppn = _entries_WIRE_26_6_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_6_u = _entries_WIRE_26_6_u; // @[tlb.scala:119:49, :211:38] wire entries_0_6_g = _entries_WIRE_26_6_g; // @[tlb.scala:119:49, :211:38] wire entries_0_6_ae = _entries_WIRE_26_6_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_6_sw = _entries_WIRE_26_6_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_6_sx = _entries_WIRE_26_6_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_6_sr = _entries_WIRE_26_6_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_6_pw = _entries_WIRE_26_6_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_6_px = _entries_WIRE_26_6_px; // @[tlb.scala:119:49, :211:38] wire entries_0_6_pr = _entries_WIRE_26_6_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_6_pal = _entries_WIRE_26_6_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_6_paa = _entries_WIRE_26_6_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_6_eff = _entries_WIRE_26_6_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_6_c = _entries_WIRE_26_6_c; // @[tlb.scala:119:49, :211:38] wire entries_0_6_fragmented_superpage = _entries_WIRE_26_6_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_7_ppn = _entries_WIRE_26_7_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_7_u = _entries_WIRE_26_7_u; // @[tlb.scala:119:49, :211:38] wire entries_0_7_g = _entries_WIRE_26_7_g; // @[tlb.scala:119:49, :211:38] wire entries_0_7_ae = _entries_WIRE_26_7_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_7_sw = _entries_WIRE_26_7_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_7_sx = _entries_WIRE_26_7_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_7_sr = _entries_WIRE_26_7_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_7_pw = _entries_WIRE_26_7_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_7_px = _entries_WIRE_26_7_px; // @[tlb.scala:119:49, :211:38] wire entries_0_7_pr = _entries_WIRE_26_7_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_7_pal = _entries_WIRE_26_7_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_7_paa = _entries_WIRE_26_7_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_7_eff = _entries_WIRE_26_7_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_7_c = _entries_WIRE_26_7_c; // @[tlb.scala:119:49, :211:38] wire entries_0_7_fragmented_superpage = _entries_WIRE_26_7_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_8_ppn = _entries_WIRE_26_8_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_8_u = _entries_WIRE_26_8_u; // @[tlb.scala:119:49, :211:38] wire entries_0_8_g = _entries_WIRE_26_8_g; // @[tlb.scala:119:49, :211:38] wire entries_0_8_ae = _entries_WIRE_26_8_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_8_sw = _entries_WIRE_26_8_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_8_sx = _entries_WIRE_26_8_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_8_sr = _entries_WIRE_26_8_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_8_pw = _entries_WIRE_26_8_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_8_px = _entries_WIRE_26_8_px; // @[tlb.scala:119:49, :211:38] wire entries_0_8_pr = _entries_WIRE_26_8_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_8_pal = _entries_WIRE_26_8_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_8_paa = _entries_WIRE_26_8_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_8_eff = _entries_WIRE_26_8_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_8_c = _entries_WIRE_26_8_c; // @[tlb.scala:119:49, :211:38] wire entries_0_8_fragmented_superpage = _entries_WIRE_26_8_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_9_ppn = _entries_WIRE_26_9_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_9_u = _entries_WIRE_26_9_u; // @[tlb.scala:119:49, :211:38] wire entries_0_9_g = _entries_WIRE_26_9_g; // @[tlb.scala:119:49, :211:38] wire entries_0_9_ae = _entries_WIRE_26_9_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_9_sw = _entries_WIRE_26_9_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_9_sx = _entries_WIRE_26_9_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_9_sr = _entries_WIRE_26_9_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_9_pw = _entries_WIRE_26_9_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_9_px = _entries_WIRE_26_9_px; // @[tlb.scala:119:49, :211:38] wire entries_0_9_pr = _entries_WIRE_26_9_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_9_pal = _entries_WIRE_26_9_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_9_paa = _entries_WIRE_26_9_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_9_eff = _entries_WIRE_26_9_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_9_c = _entries_WIRE_26_9_c; // @[tlb.scala:119:49, :211:38] wire entries_0_9_fragmented_superpage = _entries_WIRE_26_9_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_10_ppn = _entries_WIRE_26_10_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_10_u = _entries_WIRE_26_10_u; // @[tlb.scala:119:49, :211:38] wire entries_0_10_g = _entries_WIRE_26_10_g; // @[tlb.scala:119:49, :211:38] wire entries_0_10_ae = _entries_WIRE_26_10_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_10_sw = _entries_WIRE_26_10_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_10_sx = _entries_WIRE_26_10_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_10_sr = _entries_WIRE_26_10_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_10_pw = _entries_WIRE_26_10_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_10_px = _entries_WIRE_26_10_px; // @[tlb.scala:119:49, :211:38] wire entries_0_10_pr = _entries_WIRE_26_10_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_10_pal = _entries_WIRE_26_10_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_10_paa = _entries_WIRE_26_10_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_10_eff = _entries_WIRE_26_10_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_10_c = _entries_WIRE_26_10_c; // @[tlb.scala:119:49, :211:38] wire entries_0_10_fragmented_superpage = _entries_WIRE_26_10_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_11_ppn = _entries_WIRE_26_11_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_11_u = _entries_WIRE_26_11_u; // @[tlb.scala:119:49, :211:38] wire entries_0_11_g = _entries_WIRE_26_11_g; // @[tlb.scala:119:49, :211:38] wire entries_0_11_ae = _entries_WIRE_26_11_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_11_sw = _entries_WIRE_26_11_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_11_sx = _entries_WIRE_26_11_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_11_sr = _entries_WIRE_26_11_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_11_pw = _entries_WIRE_26_11_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_11_px = _entries_WIRE_26_11_px; // @[tlb.scala:119:49, :211:38] wire entries_0_11_pr = _entries_WIRE_26_11_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_11_pal = _entries_WIRE_26_11_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_11_paa = _entries_WIRE_26_11_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_11_eff = _entries_WIRE_26_11_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_11_c = _entries_WIRE_26_11_c; // @[tlb.scala:119:49, :211:38] wire entries_0_11_fragmented_superpage = _entries_WIRE_26_11_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_12_ppn = _entries_WIRE_26_12_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_12_u = _entries_WIRE_26_12_u; // @[tlb.scala:119:49, :211:38] wire entries_0_12_g = _entries_WIRE_26_12_g; // @[tlb.scala:119:49, :211:38] wire entries_0_12_ae = _entries_WIRE_26_12_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_12_sw = _entries_WIRE_26_12_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_12_sx = _entries_WIRE_26_12_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_12_sr = _entries_WIRE_26_12_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_12_pw = _entries_WIRE_26_12_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_12_px = _entries_WIRE_26_12_px; // @[tlb.scala:119:49, :211:38] wire entries_0_12_pr = _entries_WIRE_26_12_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_12_pal = _entries_WIRE_26_12_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_12_paa = _entries_WIRE_26_12_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_12_eff = _entries_WIRE_26_12_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_12_c = _entries_WIRE_26_12_c; // @[tlb.scala:119:49, :211:38] wire entries_0_12_fragmented_superpage = _entries_WIRE_26_12_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] _normal_entries_T_15; // @[tlb.scala:58:79] wire _normal_entries_T_14; // @[tlb.scala:58:79] wire _normal_entries_T_13; // @[tlb.scala:58:79] wire _normal_entries_T_12; // @[tlb.scala:58:79] wire _normal_entries_T_11; // @[tlb.scala:58:79] wire _normal_entries_T_10; // @[tlb.scala:58:79] wire _normal_entries_T_9; // @[tlb.scala:58:79] wire _normal_entries_T_8; // @[tlb.scala:58:79] wire _normal_entries_T_7; // @[tlb.scala:58:79] wire _normal_entries_T_6; // @[tlb.scala:58:79] wire _normal_entries_T_5; // @[tlb.scala:58:79] wire _normal_entries_T_4; // @[tlb.scala:58:79] wire _normal_entries_T_3; // @[tlb.scala:58:79] wire _normal_entries_T_2; // @[tlb.scala:58:79] wire _normal_entries_T_1; // @[tlb.scala:58:79] assign _normal_entries_T_1 = _normal_entries_WIRE_1[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_fragmented_superpage = _normal_entries_T_1; // @[tlb.scala:58:79] assign _normal_entries_T_2 = _normal_entries_WIRE_1[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_c = _normal_entries_T_2; // @[tlb.scala:58:79] assign _normal_entries_T_3 = _normal_entries_WIRE_1[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_eff = _normal_entries_T_3; // @[tlb.scala:58:79] assign _normal_entries_T_4 = _normal_entries_WIRE_1[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_paa = _normal_entries_T_4; // @[tlb.scala:58:79] assign _normal_entries_T_5 = _normal_entries_WIRE_1[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_pal = _normal_entries_T_5; // @[tlb.scala:58:79] assign _normal_entries_T_6 = _normal_entries_WIRE_1[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_pr = _normal_entries_T_6; // @[tlb.scala:58:79] assign _normal_entries_T_7 = _normal_entries_WIRE_1[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_px = _normal_entries_T_7; // @[tlb.scala:58:79] assign _normal_entries_T_8 = _normal_entries_WIRE_1[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_pw = _normal_entries_T_8; // @[tlb.scala:58:79] assign _normal_entries_T_9 = _normal_entries_WIRE_1[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_sr = _normal_entries_T_9; // @[tlb.scala:58:79] assign _normal_entries_T_10 = _normal_entries_WIRE_1[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_sx = _normal_entries_T_10; // @[tlb.scala:58:79] assign _normal_entries_T_11 = _normal_entries_WIRE_1[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_sw = _normal_entries_T_11; // @[tlb.scala:58:79] assign _normal_entries_T_12 = _normal_entries_WIRE_1[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_ae = _normal_entries_T_12; // @[tlb.scala:58:79] assign _normal_entries_T_13 = _normal_entries_WIRE_1[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_g = _normal_entries_T_13; // @[tlb.scala:58:79] assign _normal_entries_T_14 = _normal_entries_WIRE_1[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_u = _normal_entries_T_14; // @[tlb.scala:58:79] assign _normal_entries_T_15 = _normal_entries_WIRE_1[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_ppn = _normal_entries_T_15; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_31; // @[tlb.scala:58:79] wire _normal_entries_T_30; // @[tlb.scala:58:79] wire _normal_entries_T_29; // @[tlb.scala:58:79] wire _normal_entries_T_28; // @[tlb.scala:58:79] wire _normal_entries_T_27; // @[tlb.scala:58:79] wire _normal_entries_T_26; // @[tlb.scala:58:79] wire _normal_entries_T_25; // @[tlb.scala:58:79] wire _normal_entries_T_24; // @[tlb.scala:58:79] wire _normal_entries_T_23; // @[tlb.scala:58:79] wire _normal_entries_T_22; // @[tlb.scala:58:79] wire _normal_entries_T_21; // @[tlb.scala:58:79] wire _normal_entries_T_20; // @[tlb.scala:58:79] wire _normal_entries_T_19; // @[tlb.scala:58:79] wire _normal_entries_T_18; // @[tlb.scala:58:79] wire _normal_entries_T_17; // @[tlb.scala:58:79] assign _normal_entries_T_17 = _normal_entries_WIRE_3[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_fragmented_superpage = _normal_entries_T_17; // @[tlb.scala:58:79] assign _normal_entries_T_18 = _normal_entries_WIRE_3[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_c = _normal_entries_T_18; // @[tlb.scala:58:79] assign _normal_entries_T_19 = _normal_entries_WIRE_3[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_eff = _normal_entries_T_19; // @[tlb.scala:58:79] assign _normal_entries_T_20 = _normal_entries_WIRE_3[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_paa = _normal_entries_T_20; // @[tlb.scala:58:79] assign _normal_entries_T_21 = _normal_entries_WIRE_3[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_pal = _normal_entries_T_21; // @[tlb.scala:58:79] assign _normal_entries_T_22 = _normal_entries_WIRE_3[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_pr = _normal_entries_T_22; // @[tlb.scala:58:79] assign _normal_entries_T_23 = _normal_entries_WIRE_3[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_px = _normal_entries_T_23; // @[tlb.scala:58:79] assign _normal_entries_T_24 = _normal_entries_WIRE_3[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_pw = _normal_entries_T_24; // @[tlb.scala:58:79] assign _normal_entries_T_25 = _normal_entries_WIRE_3[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_sr = _normal_entries_T_25; // @[tlb.scala:58:79] assign _normal_entries_T_26 = _normal_entries_WIRE_3[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_sx = _normal_entries_T_26; // @[tlb.scala:58:79] assign _normal_entries_T_27 = _normal_entries_WIRE_3[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_sw = _normal_entries_T_27; // @[tlb.scala:58:79] assign _normal_entries_T_28 = _normal_entries_WIRE_3[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_ae = _normal_entries_T_28; // @[tlb.scala:58:79] assign _normal_entries_T_29 = _normal_entries_WIRE_3[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_g = _normal_entries_T_29; // @[tlb.scala:58:79] assign _normal_entries_T_30 = _normal_entries_WIRE_3[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_u = _normal_entries_T_30; // @[tlb.scala:58:79] assign _normal_entries_T_31 = _normal_entries_WIRE_3[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_2_ppn = _normal_entries_T_31; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_47; // @[tlb.scala:58:79] wire _normal_entries_T_46; // @[tlb.scala:58:79] wire _normal_entries_T_45; // @[tlb.scala:58:79] wire _normal_entries_T_44; // @[tlb.scala:58:79] wire _normal_entries_T_43; // @[tlb.scala:58:79] wire _normal_entries_T_42; // @[tlb.scala:58:79] wire _normal_entries_T_41; // @[tlb.scala:58:79] wire _normal_entries_T_40; // @[tlb.scala:58:79] wire _normal_entries_T_39; // @[tlb.scala:58:79] wire _normal_entries_T_38; // @[tlb.scala:58:79] wire _normal_entries_T_37; // @[tlb.scala:58:79] wire _normal_entries_T_36; // @[tlb.scala:58:79] wire _normal_entries_T_35; // @[tlb.scala:58:79] wire _normal_entries_T_34; // @[tlb.scala:58:79] wire _normal_entries_T_33; // @[tlb.scala:58:79] assign _normal_entries_T_33 = _normal_entries_WIRE_5[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_fragmented_superpage = _normal_entries_T_33; // @[tlb.scala:58:79] assign _normal_entries_T_34 = _normal_entries_WIRE_5[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_c = _normal_entries_T_34; // @[tlb.scala:58:79] assign _normal_entries_T_35 = _normal_entries_WIRE_5[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_eff = _normal_entries_T_35; // @[tlb.scala:58:79] assign _normal_entries_T_36 = _normal_entries_WIRE_5[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_paa = _normal_entries_T_36; // @[tlb.scala:58:79] assign _normal_entries_T_37 = _normal_entries_WIRE_5[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_pal = _normal_entries_T_37; // @[tlb.scala:58:79] assign _normal_entries_T_38 = _normal_entries_WIRE_5[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_pr = _normal_entries_T_38; // @[tlb.scala:58:79] assign _normal_entries_T_39 = _normal_entries_WIRE_5[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_px = _normal_entries_T_39; // @[tlb.scala:58:79] assign _normal_entries_T_40 = _normal_entries_WIRE_5[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_pw = _normal_entries_T_40; // @[tlb.scala:58:79] assign _normal_entries_T_41 = _normal_entries_WIRE_5[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_sr = _normal_entries_T_41; // @[tlb.scala:58:79] assign _normal_entries_T_42 = _normal_entries_WIRE_5[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_sx = _normal_entries_T_42; // @[tlb.scala:58:79] assign _normal_entries_T_43 = _normal_entries_WIRE_5[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_sw = _normal_entries_T_43; // @[tlb.scala:58:79] assign _normal_entries_T_44 = _normal_entries_WIRE_5[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_ae = _normal_entries_T_44; // @[tlb.scala:58:79] assign _normal_entries_T_45 = _normal_entries_WIRE_5[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_g = _normal_entries_T_45; // @[tlb.scala:58:79] assign _normal_entries_T_46 = _normal_entries_WIRE_5[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_u = _normal_entries_T_46; // @[tlb.scala:58:79] assign _normal_entries_T_47 = _normal_entries_WIRE_5[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_4_ppn = _normal_entries_T_47; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_63; // @[tlb.scala:58:79] wire _normal_entries_T_62; // @[tlb.scala:58:79] wire _normal_entries_T_61; // @[tlb.scala:58:79] wire _normal_entries_T_60; // @[tlb.scala:58:79] wire _normal_entries_T_59; // @[tlb.scala:58:79] wire _normal_entries_T_58; // @[tlb.scala:58:79] wire _normal_entries_T_57; // @[tlb.scala:58:79] wire _normal_entries_T_56; // @[tlb.scala:58:79] wire _normal_entries_T_55; // @[tlb.scala:58:79] wire _normal_entries_T_54; // @[tlb.scala:58:79] wire _normal_entries_T_53; // @[tlb.scala:58:79] wire _normal_entries_T_52; // @[tlb.scala:58:79] wire _normal_entries_T_51; // @[tlb.scala:58:79] wire _normal_entries_T_50; // @[tlb.scala:58:79] wire _normal_entries_T_49; // @[tlb.scala:58:79] assign _normal_entries_T_49 = _normal_entries_WIRE_7[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_fragmented_superpage = _normal_entries_T_49; // @[tlb.scala:58:79] assign _normal_entries_T_50 = _normal_entries_WIRE_7[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_c = _normal_entries_T_50; // @[tlb.scala:58:79] assign _normal_entries_T_51 = _normal_entries_WIRE_7[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_eff = _normal_entries_T_51; // @[tlb.scala:58:79] assign _normal_entries_T_52 = _normal_entries_WIRE_7[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_paa = _normal_entries_T_52; // @[tlb.scala:58:79] assign _normal_entries_T_53 = _normal_entries_WIRE_7[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_pal = _normal_entries_T_53; // @[tlb.scala:58:79] assign _normal_entries_T_54 = _normal_entries_WIRE_7[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_pr = _normal_entries_T_54; // @[tlb.scala:58:79] assign _normal_entries_T_55 = _normal_entries_WIRE_7[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_px = _normal_entries_T_55; // @[tlb.scala:58:79] assign _normal_entries_T_56 = _normal_entries_WIRE_7[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_pw = _normal_entries_T_56; // @[tlb.scala:58:79] assign _normal_entries_T_57 = _normal_entries_WIRE_7[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_sr = _normal_entries_T_57; // @[tlb.scala:58:79] assign _normal_entries_T_58 = _normal_entries_WIRE_7[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_sx = _normal_entries_T_58; // @[tlb.scala:58:79] assign _normal_entries_T_59 = _normal_entries_WIRE_7[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_sw = _normal_entries_T_59; // @[tlb.scala:58:79] assign _normal_entries_T_60 = _normal_entries_WIRE_7[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_ae = _normal_entries_T_60; // @[tlb.scala:58:79] assign _normal_entries_T_61 = _normal_entries_WIRE_7[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_g = _normal_entries_T_61; // @[tlb.scala:58:79] assign _normal_entries_T_62 = _normal_entries_WIRE_7[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_u = _normal_entries_T_62; // @[tlb.scala:58:79] assign _normal_entries_T_63 = _normal_entries_WIRE_7[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_6_ppn = _normal_entries_T_63; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_79; // @[tlb.scala:58:79] wire _normal_entries_T_78; // @[tlb.scala:58:79] wire _normal_entries_T_77; // @[tlb.scala:58:79] wire _normal_entries_T_76; // @[tlb.scala:58:79] wire _normal_entries_T_75; // @[tlb.scala:58:79] wire _normal_entries_T_74; // @[tlb.scala:58:79] wire _normal_entries_T_73; // @[tlb.scala:58:79] wire _normal_entries_T_72; // @[tlb.scala:58:79] wire _normal_entries_T_71; // @[tlb.scala:58:79] wire _normal_entries_T_70; // @[tlb.scala:58:79] wire _normal_entries_T_69; // @[tlb.scala:58:79] wire _normal_entries_T_68; // @[tlb.scala:58:79] wire _normal_entries_T_67; // @[tlb.scala:58:79] wire _normal_entries_T_66; // @[tlb.scala:58:79] wire _normal_entries_T_65; // @[tlb.scala:58:79] assign _normal_entries_T_65 = _normal_entries_WIRE_9[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_fragmented_superpage = _normal_entries_T_65; // @[tlb.scala:58:79] assign _normal_entries_T_66 = _normal_entries_WIRE_9[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_c = _normal_entries_T_66; // @[tlb.scala:58:79] assign _normal_entries_T_67 = _normal_entries_WIRE_9[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_eff = _normal_entries_T_67; // @[tlb.scala:58:79] assign _normal_entries_T_68 = _normal_entries_WIRE_9[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_paa = _normal_entries_T_68; // @[tlb.scala:58:79] assign _normal_entries_T_69 = _normal_entries_WIRE_9[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_pal = _normal_entries_T_69; // @[tlb.scala:58:79] assign _normal_entries_T_70 = _normal_entries_WIRE_9[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_pr = _normal_entries_T_70; // @[tlb.scala:58:79] assign _normal_entries_T_71 = _normal_entries_WIRE_9[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_px = _normal_entries_T_71; // @[tlb.scala:58:79] assign _normal_entries_T_72 = _normal_entries_WIRE_9[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_pw = _normal_entries_T_72; // @[tlb.scala:58:79] assign _normal_entries_T_73 = _normal_entries_WIRE_9[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_sr = _normal_entries_T_73; // @[tlb.scala:58:79] assign _normal_entries_T_74 = _normal_entries_WIRE_9[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_sx = _normal_entries_T_74; // @[tlb.scala:58:79] assign _normal_entries_T_75 = _normal_entries_WIRE_9[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_sw = _normal_entries_T_75; // @[tlb.scala:58:79] assign _normal_entries_T_76 = _normal_entries_WIRE_9[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_ae = _normal_entries_T_76; // @[tlb.scala:58:79] assign _normal_entries_T_77 = _normal_entries_WIRE_9[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_g = _normal_entries_T_77; // @[tlb.scala:58:79] assign _normal_entries_T_78 = _normal_entries_WIRE_9[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_u = _normal_entries_T_78; // @[tlb.scala:58:79] assign _normal_entries_T_79 = _normal_entries_WIRE_9[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_8_ppn = _normal_entries_T_79; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_95; // @[tlb.scala:58:79] wire _normal_entries_T_94; // @[tlb.scala:58:79] wire _normal_entries_T_93; // @[tlb.scala:58:79] wire _normal_entries_T_92; // @[tlb.scala:58:79] wire _normal_entries_T_91; // @[tlb.scala:58:79] wire _normal_entries_T_90; // @[tlb.scala:58:79] wire _normal_entries_T_89; // @[tlb.scala:58:79] wire _normal_entries_T_88; // @[tlb.scala:58:79] wire _normal_entries_T_87; // @[tlb.scala:58:79] wire _normal_entries_T_86; // @[tlb.scala:58:79] wire _normal_entries_T_85; // @[tlb.scala:58:79] wire _normal_entries_T_84; // @[tlb.scala:58:79] wire _normal_entries_T_83; // @[tlb.scala:58:79] wire _normal_entries_T_82; // @[tlb.scala:58:79] wire _normal_entries_T_81; // @[tlb.scala:58:79] assign _normal_entries_T_81 = _normal_entries_WIRE_11[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_fragmented_superpage = _normal_entries_T_81; // @[tlb.scala:58:79] assign _normal_entries_T_82 = _normal_entries_WIRE_11[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_c = _normal_entries_T_82; // @[tlb.scala:58:79] assign _normal_entries_T_83 = _normal_entries_WIRE_11[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_eff = _normal_entries_T_83; // @[tlb.scala:58:79] assign _normal_entries_T_84 = _normal_entries_WIRE_11[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_paa = _normal_entries_T_84; // @[tlb.scala:58:79] assign _normal_entries_T_85 = _normal_entries_WIRE_11[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_pal = _normal_entries_T_85; // @[tlb.scala:58:79] assign _normal_entries_T_86 = _normal_entries_WIRE_11[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_pr = _normal_entries_T_86; // @[tlb.scala:58:79] assign _normal_entries_T_87 = _normal_entries_WIRE_11[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_px = _normal_entries_T_87; // @[tlb.scala:58:79] assign _normal_entries_T_88 = _normal_entries_WIRE_11[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_pw = _normal_entries_T_88; // @[tlb.scala:58:79] assign _normal_entries_T_89 = _normal_entries_WIRE_11[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_sr = _normal_entries_T_89; // @[tlb.scala:58:79] assign _normal_entries_T_90 = _normal_entries_WIRE_11[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_sx = _normal_entries_T_90; // @[tlb.scala:58:79] assign _normal_entries_T_91 = _normal_entries_WIRE_11[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_sw = _normal_entries_T_91; // @[tlb.scala:58:79] assign _normal_entries_T_92 = _normal_entries_WIRE_11[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_ae = _normal_entries_T_92; // @[tlb.scala:58:79] assign _normal_entries_T_93 = _normal_entries_WIRE_11[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_g = _normal_entries_T_93; // @[tlb.scala:58:79] assign _normal_entries_T_94 = _normal_entries_WIRE_11[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_u = _normal_entries_T_94; // @[tlb.scala:58:79] assign _normal_entries_T_95 = _normal_entries_WIRE_11[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_10_ppn = _normal_entries_T_95; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_111; // @[tlb.scala:58:79] wire _normal_entries_T_110; // @[tlb.scala:58:79] wire _normal_entries_T_109; // @[tlb.scala:58:79] wire _normal_entries_T_108; // @[tlb.scala:58:79] wire _normal_entries_T_107; // @[tlb.scala:58:79] wire _normal_entries_T_106; // @[tlb.scala:58:79] wire _normal_entries_T_105; // @[tlb.scala:58:79] wire _normal_entries_T_104; // @[tlb.scala:58:79] wire _normal_entries_T_103; // @[tlb.scala:58:79] wire _normal_entries_T_102; // @[tlb.scala:58:79] wire _normal_entries_T_101; // @[tlb.scala:58:79] wire _normal_entries_T_100; // @[tlb.scala:58:79] wire _normal_entries_T_99; // @[tlb.scala:58:79] wire _normal_entries_T_98; // @[tlb.scala:58:79] wire _normal_entries_T_97; // @[tlb.scala:58:79] assign _normal_entries_T_97 = _normal_entries_WIRE_13[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_12_fragmented_superpage = _normal_entries_T_97; // @[tlb.scala:58:79] assign _normal_entries_T_98 = _normal_entries_WIRE_13[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_12_c = _normal_entries_T_98; // @[tlb.scala:58:79] assign _normal_entries_T_99 = _normal_entries_WIRE_13[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_12_eff = _normal_entries_T_99; // @[tlb.scala:58:79] assign _normal_entries_T_100 = _normal_entries_WIRE_13[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_12_paa = _normal_entries_T_100; // @[tlb.scala:58:79] assign _normal_entries_T_101 = _normal_entries_WIRE_13[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_12_pal = _normal_entries_T_101; // @[tlb.scala:58:79] assign _normal_entries_T_102 = _normal_entries_WIRE_13[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_12_pr = _normal_entries_T_102; // @[tlb.scala:58:79] assign _normal_entries_T_103 = _normal_entries_WIRE_13[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_12_px = _normal_entries_T_103; // @[tlb.scala:58:79] assign _normal_entries_T_104 = _normal_entries_WIRE_13[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_12_pw = _normal_entries_T_104; // @[tlb.scala:58:79] assign _normal_entries_T_105 = _normal_entries_WIRE_13[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_12_sr = _normal_entries_T_105; // @[tlb.scala:58:79] assign _normal_entries_T_106 = _normal_entries_WIRE_13[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_12_sx = _normal_entries_T_106; // @[tlb.scala:58:79] assign _normal_entries_T_107 = _normal_entries_WIRE_13[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_12_sw = _normal_entries_T_107; // @[tlb.scala:58:79] assign _normal_entries_T_108 = _normal_entries_WIRE_13[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_12_ae = _normal_entries_T_108; // @[tlb.scala:58:79] assign _normal_entries_T_109 = _normal_entries_WIRE_13[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_12_g = _normal_entries_T_109; // @[tlb.scala:58:79] assign _normal_entries_T_110 = _normal_entries_WIRE_13[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_12_u = _normal_entries_T_110; // @[tlb.scala:58:79] assign _normal_entries_T_111 = _normal_entries_WIRE_13[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_12_ppn = _normal_entries_T_111; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_127; // @[tlb.scala:58:79] wire _normal_entries_T_126; // @[tlb.scala:58:79] wire _normal_entries_T_125; // @[tlb.scala:58:79] wire _normal_entries_T_124; // @[tlb.scala:58:79] wire _normal_entries_T_123; // @[tlb.scala:58:79] wire _normal_entries_T_122; // @[tlb.scala:58:79] wire _normal_entries_T_121; // @[tlb.scala:58:79] wire _normal_entries_T_120; // @[tlb.scala:58:79] wire _normal_entries_T_119; // @[tlb.scala:58:79] wire _normal_entries_T_118; // @[tlb.scala:58:79] wire _normal_entries_T_117; // @[tlb.scala:58:79] wire _normal_entries_T_116; // @[tlb.scala:58:79] wire _normal_entries_T_115; // @[tlb.scala:58:79] wire _normal_entries_T_114; // @[tlb.scala:58:79] wire _normal_entries_T_113; // @[tlb.scala:58:79] assign _normal_entries_T_113 = _normal_entries_WIRE_15[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_14_fragmented_superpage = _normal_entries_T_113; // @[tlb.scala:58:79] assign _normal_entries_T_114 = _normal_entries_WIRE_15[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_14_c = _normal_entries_T_114; // @[tlb.scala:58:79] assign _normal_entries_T_115 = _normal_entries_WIRE_15[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_14_eff = _normal_entries_T_115; // @[tlb.scala:58:79] assign _normal_entries_T_116 = _normal_entries_WIRE_15[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_14_paa = _normal_entries_T_116; // @[tlb.scala:58:79] assign _normal_entries_T_117 = _normal_entries_WIRE_15[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_14_pal = _normal_entries_T_117; // @[tlb.scala:58:79] assign _normal_entries_T_118 = _normal_entries_WIRE_15[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_14_pr = _normal_entries_T_118; // @[tlb.scala:58:79] assign _normal_entries_T_119 = _normal_entries_WIRE_15[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_14_px = _normal_entries_T_119; // @[tlb.scala:58:79] assign _normal_entries_T_120 = _normal_entries_WIRE_15[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_14_pw = _normal_entries_T_120; // @[tlb.scala:58:79] assign _normal_entries_T_121 = _normal_entries_WIRE_15[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_14_sr = _normal_entries_T_121; // @[tlb.scala:58:79] assign _normal_entries_T_122 = _normal_entries_WIRE_15[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_14_sx = _normal_entries_T_122; // @[tlb.scala:58:79] assign _normal_entries_T_123 = _normal_entries_WIRE_15[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_14_sw = _normal_entries_T_123; // @[tlb.scala:58:79] assign _normal_entries_T_124 = _normal_entries_WIRE_15[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_14_ae = _normal_entries_T_124; // @[tlb.scala:58:79] assign _normal_entries_T_125 = _normal_entries_WIRE_15[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_14_g = _normal_entries_T_125; // @[tlb.scala:58:79] assign _normal_entries_T_126 = _normal_entries_WIRE_15[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_14_u = _normal_entries_T_126; // @[tlb.scala:58:79] assign _normal_entries_T_127 = _normal_entries_WIRE_15[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_14_ppn = _normal_entries_T_127; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_142; // @[tlb.scala:58:79] wire _normal_entries_T_141; // @[tlb.scala:58:79] wire _normal_entries_T_140; // @[tlb.scala:58:79] wire _normal_entries_T_139; // @[tlb.scala:58:79] wire _normal_entries_T_138; // @[tlb.scala:58:79] wire _normal_entries_T_137; // @[tlb.scala:58:79] wire _normal_entries_T_136; // @[tlb.scala:58:79] wire _normal_entries_T_135; // @[tlb.scala:58:79] wire _normal_entries_T_134; // @[tlb.scala:58:79] wire _normal_entries_T_133; // @[tlb.scala:58:79] wire _normal_entries_T_132; // @[tlb.scala:58:79] wire _normal_entries_T_131; // @[tlb.scala:58:79] wire _normal_entries_T_130; // @[tlb.scala:58:79] wire _normal_entries_T_129; // @[tlb.scala:58:79] wire _normal_entries_T_128; // @[tlb.scala:58:79] assign _normal_entries_T_128 = _normal_entries_WIRE_17[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_16_fragmented_superpage = _normal_entries_T_128; // @[tlb.scala:58:79] assign _normal_entries_T_129 = _normal_entries_WIRE_17[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_16_c = _normal_entries_T_129; // @[tlb.scala:58:79] assign _normal_entries_T_130 = _normal_entries_WIRE_17[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_16_eff = _normal_entries_T_130; // @[tlb.scala:58:79] assign _normal_entries_T_131 = _normal_entries_WIRE_17[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_16_paa = _normal_entries_T_131; // @[tlb.scala:58:79] assign _normal_entries_T_132 = _normal_entries_WIRE_17[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_16_pal = _normal_entries_T_132; // @[tlb.scala:58:79] assign _normal_entries_T_133 = _normal_entries_WIRE_17[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_16_pr = _normal_entries_T_133; // @[tlb.scala:58:79] assign _normal_entries_T_134 = _normal_entries_WIRE_17[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_16_px = _normal_entries_T_134; // @[tlb.scala:58:79] assign _normal_entries_T_135 = _normal_entries_WIRE_17[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_16_pw = _normal_entries_T_135; // @[tlb.scala:58:79] assign _normal_entries_T_136 = _normal_entries_WIRE_17[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_16_sr = _normal_entries_T_136; // @[tlb.scala:58:79] assign _normal_entries_T_137 = _normal_entries_WIRE_17[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_16_sx = _normal_entries_T_137; // @[tlb.scala:58:79] assign _normal_entries_T_138 = _normal_entries_WIRE_17[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_16_sw = _normal_entries_T_138; // @[tlb.scala:58:79] assign _normal_entries_T_139 = _normal_entries_WIRE_17[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_16_ae = _normal_entries_T_139; // @[tlb.scala:58:79] assign _normal_entries_T_140 = _normal_entries_WIRE_17[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_16_g = _normal_entries_T_140; // @[tlb.scala:58:79] assign _normal_entries_T_141 = _normal_entries_WIRE_17[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_16_u = _normal_entries_T_141; // @[tlb.scala:58:79] assign _normal_entries_T_142 = _normal_entries_WIRE_17[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_16_ppn = _normal_entries_T_142; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_157; // @[tlb.scala:58:79] wire _normal_entries_T_156; // @[tlb.scala:58:79] wire _normal_entries_T_155; // @[tlb.scala:58:79] wire _normal_entries_T_154; // @[tlb.scala:58:79] wire _normal_entries_T_153; // @[tlb.scala:58:79] wire _normal_entries_T_152; // @[tlb.scala:58:79] wire _normal_entries_T_151; // @[tlb.scala:58:79] wire _normal_entries_T_150; // @[tlb.scala:58:79] wire _normal_entries_T_149; // @[tlb.scala:58:79] wire _normal_entries_T_148; // @[tlb.scala:58:79] wire _normal_entries_T_147; // @[tlb.scala:58:79] wire _normal_entries_T_146; // @[tlb.scala:58:79] wire _normal_entries_T_145; // @[tlb.scala:58:79] wire _normal_entries_T_144; // @[tlb.scala:58:79] wire _normal_entries_T_143; // @[tlb.scala:58:79] assign _normal_entries_T_143 = _normal_entries_WIRE_19[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_18_fragmented_superpage = _normal_entries_T_143; // @[tlb.scala:58:79] assign _normal_entries_T_144 = _normal_entries_WIRE_19[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_18_c = _normal_entries_T_144; // @[tlb.scala:58:79] assign _normal_entries_T_145 = _normal_entries_WIRE_19[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_18_eff = _normal_entries_T_145; // @[tlb.scala:58:79] assign _normal_entries_T_146 = _normal_entries_WIRE_19[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_18_paa = _normal_entries_T_146; // @[tlb.scala:58:79] assign _normal_entries_T_147 = _normal_entries_WIRE_19[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_18_pal = _normal_entries_T_147; // @[tlb.scala:58:79] assign _normal_entries_T_148 = _normal_entries_WIRE_19[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_18_pr = _normal_entries_T_148; // @[tlb.scala:58:79] assign _normal_entries_T_149 = _normal_entries_WIRE_19[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_18_px = _normal_entries_T_149; // @[tlb.scala:58:79] assign _normal_entries_T_150 = _normal_entries_WIRE_19[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_18_pw = _normal_entries_T_150; // @[tlb.scala:58:79] assign _normal_entries_T_151 = _normal_entries_WIRE_19[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_18_sr = _normal_entries_T_151; // @[tlb.scala:58:79] assign _normal_entries_T_152 = _normal_entries_WIRE_19[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_18_sx = _normal_entries_T_152; // @[tlb.scala:58:79] assign _normal_entries_T_153 = _normal_entries_WIRE_19[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_18_sw = _normal_entries_T_153; // @[tlb.scala:58:79] assign _normal_entries_T_154 = _normal_entries_WIRE_19[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_18_ae = _normal_entries_T_154; // @[tlb.scala:58:79] assign _normal_entries_T_155 = _normal_entries_WIRE_19[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_18_g = _normal_entries_T_155; // @[tlb.scala:58:79] assign _normal_entries_T_156 = _normal_entries_WIRE_19[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_18_u = _normal_entries_T_156; // @[tlb.scala:58:79] assign _normal_entries_T_157 = _normal_entries_WIRE_19[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_18_ppn = _normal_entries_T_157; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_172; // @[tlb.scala:58:79] wire _normal_entries_T_171; // @[tlb.scala:58:79] wire _normal_entries_T_170; // @[tlb.scala:58:79] wire _normal_entries_T_169; // @[tlb.scala:58:79] wire _normal_entries_T_168; // @[tlb.scala:58:79] wire _normal_entries_T_167; // @[tlb.scala:58:79] wire _normal_entries_T_166; // @[tlb.scala:58:79] wire _normal_entries_T_165; // @[tlb.scala:58:79] wire _normal_entries_T_164; // @[tlb.scala:58:79] wire _normal_entries_T_163; // @[tlb.scala:58:79] wire _normal_entries_T_162; // @[tlb.scala:58:79] wire _normal_entries_T_161; // @[tlb.scala:58:79] wire _normal_entries_T_160; // @[tlb.scala:58:79] wire _normal_entries_T_159; // @[tlb.scala:58:79] wire _normal_entries_T_158; // @[tlb.scala:58:79] assign _normal_entries_T_158 = _normal_entries_WIRE_21[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_20_fragmented_superpage = _normal_entries_T_158; // @[tlb.scala:58:79] assign _normal_entries_T_159 = _normal_entries_WIRE_21[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_20_c = _normal_entries_T_159; // @[tlb.scala:58:79] assign _normal_entries_T_160 = _normal_entries_WIRE_21[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_20_eff = _normal_entries_T_160; // @[tlb.scala:58:79] assign _normal_entries_T_161 = _normal_entries_WIRE_21[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_20_paa = _normal_entries_T_161; // @[tlb.scala:58:79] assign _normal_entries_T_162 = _normal_entries_WIRE_21[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_20_pal = _normal_entries_T_162; // @[tlb.scala:58:79] assign _normal_entries_T_163 = _normal_entries_WIRE_21[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_20_pr = _normal_entries_T_163; // @[tlb.scala:58:79] assign _normal_entries_T_164 = _normal_entries_WIRE_21[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_20_px = _normal_entries_T_164; // @[tlb.scala:58:79] assign _normal_entries_T_165 = _normal_entries_WIRE_21[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_20_pw = _normal_entries_T_165; // @[tlb.scala:58:79] assign _normal_entries_T_166 = _normal_entries_WIRE_21[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_20_sr = _normal_entries_T_166; // @[tlb.scala:58:79] assign _normal_entries_T_167 = _normal_entries_WIRE_21[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_20_sx = _normal_entries_T_167; // @[tlb.scala:58:79] assign _normal_entries_T_168 = _normal_entries_WIRE_21[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_20_sw = _normal_entries_T_168; // @[tlb.scala:58:79] assign _normal_entries_T_169 = _normal_entries_WIRE_21[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_20_ae = _normal_entries_T_169; // @[tlb.scala:58:79] assign _normal_entries_T_170 = _normal_entries_WIRE_21[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_20_g = _normal_entries_T_170; // @[tlb.scala:58:79] assign _normal_entries_T_171 = _normal_entries_WIRE_21[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_20_u = _normal_entries_T_171; // @[tlb.scala:58:79] assign _normal_entries_T_172 = _normal_entries_WIRE_21[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_20_ppn = _normal_entries_T_172; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_187; // @[tlb.scala:58:79] wire _normal_entries_T_186; // @[tlb.scala:58:79] wire _normal_entries_T_185; // @[tlb.scala:58:79] wire _normal_entries_T_184; // @[tlb.scala:58:79] wire _normal_entries_T_183; // @[tlb.scala:58:79] wire _normal_entries_T_182; // @[tlb.scala:58:79] wire _normal_entries_T_181; // @[tlb.scala:58:79] wire _normal_entries_T_180; // @[tlb.scala:58:79] wire _normal_entries_T_179; // @[tlb.scala:58:79] wire _normal_entries_T_178; // @[tlb.scala:58:79] wire _normal_entries_T_177; // @[tlb.scala:58:79] wire _normal_entries_T_176; // @[tlb.scala:58:79] wire _normal_entries_T_175; // @[tlb.scala:58:79] wire _normal_entries_T_174; // @[tlb.scala:58:79] wire _normal_entries_T_173; // @[tlb.scala:58:79] assign _normal_entries_T_173 = _normal_entries_WIRE_23[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_22_fragmented_superpage = _normal_entries_T_173; // @[tlb.scala:58:79] assign _normal_entries_T_174 = _normal_entries_WIRE_23[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_22_c = _normal_entries_T_174; // @[tlb.scala:58:79] assign _normal_entries_T_175 = _normal_entries_WIRE_23[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_22_eff = _normal_entries_T_175; // @[tlb.scala:58:79] assign _normal_entries_T_176 = _normal_entries_WIRE_23[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_22_paa = _normal_entries_T_176; // @[tlb.scala:58:79] assign _normal_entries_T_177 = _normal_entries_WIRE_23[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_22_pal = _normal_entries_T_177; // @[tlb.scala:58:79] assign _normal_entries_T_178 = _normal_entries_WIRE_23[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_22_pr = _normal_entries_T_178; // @[tlb.scala:58:79] assign _normal_entries_T_179 = _normal_entries_WIRE_23[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_22_px = _normal_entries_T_179; // @[tlb.scala:58:79] assign _normal_entries_T_180 = _normal_entries_WIRE_23[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_22_pw = _normal_entries_T_180; // @[tlb.scala:58:79] assign _normal_entries_T_181 = _normal_entries_WIRE_23[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_22_sr = _normal_entries_T_181; // @[tlb.scala:58:79] assign _normal_entries_T_182 = _normal_entries_WIRE_23[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_22_sx = _normal_entries_T_182; // @[tlb.scala:58:79] assign _normal_entries_T_183 = _normal_entries_WIRE_23[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_22_sw = _normal_entries_T_183; // @[tlb.scala:58:79] assign _normal_entries_T_184 = _normal_entries_WIRE_23[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_22_ae = _normal_entries_T_184; // @[tlb.scala:58:79] assign _normal_entries_T_185 = _normal_entries_WIRE_23[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_22_g = _normal_entries_T_185; // @[tlb.scala:58:79] assign _normal_entries_T_186 = _normal_entries_WIRE_23[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_22_u = _normal_entries_T_186; // @[tlb.scala:58:79] assign _normal_entries_T_187 = _normal_entries_WIRE_23[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_22_ppn = _normal_entries_T_187; // @[tlb.scala:58:79] wire [19:0] normal_entries_0_0_ppn = _normal_entries_WIRE_24_0_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_u = _normal_entries_WIRE_24_0_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_g = _normal_entries_WIRE_24_0_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_ae = _normal_entries_WIRE_24_0_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_sw = _normal_entries_WIRE_24_0_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_sx = _normal_entries_WIRE_24_0_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_sr = _normal_entries_WIRE_24_0_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_pw = _normal_entries_WIRE_24_0_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_px = _normal_entries_WIRE_24_0_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_pr = _normal_entries_WIRE_24_0_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_pal = _normal_entries_WIRE_24_0_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_paa = _normal_entries_WIRE_24_0_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_eff = _normal_entries_WIRE_24_0_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_c = _normal_entries_WIRE_24_0_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_fragmented_superpage = _normal_entries_WIRE_24_0_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_1_ppn = _normal_entries_WIRE_24_1_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_u = _normal_entries_WIRE_24_1_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_g = _normal_entries_WIRE_24_1_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_ae = _normal_entries_WIRE_24_1_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_sw = _normal_entries_WIRE_24_1_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_sx = _normal_entries_WIRE_24_1_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_sr = _normal_entries_WIRE_24_1_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_pw = _normal_entries_WIRE_24_1_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_px = _normal_entries_WIRE_24_1_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_pr = _normal_entries_WIRE_24_1_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_pal = _normal_entries_WIRE_24_1_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_paa = _normal_entries_WIRE_24_1_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_eff = _normal_entries_WIRE_24_1_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_c = _normal_entries_WIRE_24_1_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_fragmented_superpage = _normal_entries_WIRE_24_1_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_2_ppn = _normal_entries_WIRE_24_2_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_u = _normal_entries_WIRE_24_2_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_g = _normal_entries_WIRE_24_2_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_ae = _normal_entries_WIRE_24_2_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_sw = _normal_entries_WIRE_24_2_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_sx = _normal_entries_WIRE_24_2_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_sr = _normal_entries_WIRE_24_2_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_pw = _normal_entries_WIRE_24_2_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_px = _normal_entries_WIRE_24_2_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_pr = _normal_entries_WIRE_24_2_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_pal = _normal_entries_WIRE_24_2_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_paa = _normal_entries_WIRE_24_2_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_eff = _normal_entries_WIRE_24_2_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_c = _normal_entries_WIRE_24_2_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_fragmented_superpage = _normal_entries_WIRE_24_2_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_3_ppn = _normal_entries_WIRE_24_3_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_u = _normal_entries_WIRE_24_3_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_g = _normal_entries_WIRE_24_3_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_ae = _normal_entries_WIRE_24_3_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_sw = _normal_entries_WIRE_24_3_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_sx = _normal_entries_WIRE_24_3_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_sr = _normal_entries_WIRE_24_3_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_pw = _normal_entries_WIRE_24_3_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_px = _normal_entries_WIRE_24_3_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_pr = _normal_entries_WIRE_24_3_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_pal = _normal_entries_WIRE_24_3_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_paa = _normal_entries_WIRE_24_3_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_eff = _normal_entries_WIRE_24_3_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_c = _normal_entries_WIRE_24_3_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_fragmented_superpage = _normal_entries_WIRE_24_3_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_4_ppn = _normal_entries_WIRE_24_4_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_u = _normal_entries_WIRE_24_4_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_g = _normal_entries_WIRE_24_4_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_ae = _normal_entries_WIRE_24_4_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_sw = _normal_entries_WIRE_24_4_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_sx = _normal_entries_WIRE_24_4_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_sr = _normal_entries_WIRE_24_4_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_pw = _normal_entries_WIRE_24_4_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_px = _normal_entries_WIRE_24_4_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_pr = _normal_entries_WIRE_24_4_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_pal = _normal_entries_WIRE_24_4_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_paa = _normal_entries_WIRE_24_4_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_eff = _normal_entries_WIRE_24_4_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_c = _normal_entries_WIRE_24_4_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_fragmented_superpage = _normal_entries_WIRE_24_4_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_5_ppn = _normal_entries_WIRE_24_5_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_u = _normal_entries_WIRE_24_5_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_g = _normal_entries_WIRE_24_5_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_ae = _normal_entries_WIRE_24_5_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_sw = _normal_entries_WIRE_24_5_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_sx = _normal_entries_WIRE_24_5_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_sr = _normal_entries_WIRE_24_5_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_pw = _normal_entries_WIRE_24_5_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_px = _normal_entries_WIRE_24_5_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_pr = _normal_entries_WIRE_24_5_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_pal = _normal_entries_WIRE_24_5_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_paa = _normal_entries_WIRE_24_5_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_eff = _normal_entries_WIRE_24_5_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_c = _normal_entries_WIRE_24_5_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_fragmented_superpage = _normal_entries_WIRE_24_5_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_6_ppn = _normal_entries_WIRE_24_6_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_6_u = _normal_entries_WIRE_24_6_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_6_g = _normal_entries_WIRE_24_6_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_6_ae = _normal_entries_WIRE_24_6_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_6_sw = _normal_entries_WIRE_24_6_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_6_sx = _normal_entries_WIRE_24_6_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_6_sr = _normal_entries_WIRE_24_6_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_6_pw = _normal_entries_WIRE_24_6_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_6_px = _normal_entries_WIRE_24_6_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_6_pr = _normal_entries_WIRE_24_6_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_6_pal = _normal_entries_WIRE_24_6_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_6_paa = _normal_entries_WIRE_24_6_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_6_eff = _normal_entries_WIRE_24_6_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_6_c = _normal_entries_WIRE_24_6_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_6_fragmented_superpage = _normal_entries_WIRE_24_6_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_7_ppn = _normal_entries_WIRE_24_7_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_7_u = _normal_entries_WIRE_24_7_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_7_g = _normal_entries_WIRE_24_7_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_7_ae = _normal_entries_WIRE_24_7_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_7_sw = _normal_entries_WIRE_24_7_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_7_sx = _normal_entries_WIRE_24_7_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_7_sr = _normal_entries_WIRE_24_7_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_7_pw = _normal_entries_WIRE_24_7_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_7_px = _normal_entries_WIRE_24_7_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_7_pr = _normal_entries_WIRE_24_7_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_7_pal = _normal_entries_WIRE_24_7_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_7_paa = _normal_entries_WIRE_24_7_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_7_eff = _normal_entries_WIRE_24_7_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_7_c = _normal_entries_WIRE_24_7_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_7_fragmented_superpage = _normal_entries_WIRE_24_7_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_8_ppn = _normal_entries_WIRE_24_8_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_8_u = _normal_entries_WIRE_24_8_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_8_g = _normal_entries_WIRE_24_8_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_8_ae = _normal_entries_WIRE_24_8_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_8_sw = _normal_entries_WIRE_24_8_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_8_sx = _normal_entries_WIRE_24_8_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_8_sr = _normal_entries_WIRE_24_8_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_8_pw = _normal_entries_WIRE_24_8_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_8_px = _normal_entries_WIRE_24_8_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_8_pr = _normal_entries_WIRE_24_8_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_8_pal = _normal_entries_WIRE_24_8_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_8_paa = _normal_entries_WIRE_24_8_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_8_eff = _normal_entries_WIRE_24_8_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_8_c = _normal_entries_WIRE_24_8_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_8_fragmented_superpage = _normal_entries_WIRE_24_8_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_9_ppn = _normal_entries_WIRE_24_9_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_9_u = _normal_entries_WIRE_24_9_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_9_g = _normal_entries_WIRE_24_9_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_9_ae = _normal_entries_WIRE_24_9_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_9_sw = _normal_entries_WIRE_24_9_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_9_sx = _normal_entries_WIRE_24_9_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_9_sr = _normal_entries_WIRE_24_9_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_9_pw = _normal_entries_WIRE_24_9_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_9_px = _normal_entries_WIRE_24_9_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_9_pr = _normal_entries_WIRE_24_9_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_9_pal = _normal_entries_WIRE_24_9_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_9_paa = _normal_entries_WIRE_24_9_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_9_eff = _normal_entries_WIRE_24_9_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_9_c = _normal_entries_WIRE_24_9_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_9_fragmented_superpage = _normal_entries_WIRE_24_9_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_10_ppn = _normal_entries_WIRE_24_10_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_10_u = _normal_entries_WIRE_24_10_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_10_g = _normal_entries_WIRE_24_10_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_10_ae = _normal_entries_WIRE_24_10_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_10_sw = _normal_entries_WIRE_24_10_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_10_sx = _normal_entries_WIRE_24_10_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_10_sr = _normal_entries_WIRE_24_10_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_10_pw = _normal_entries_WIRE_24_10_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_10_px = _normal_entries_WIRE_24_10_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_10_pr = _normal_entries_WIRE_24_10_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_10_pal = _normal_entries_WIRE_24_10_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_10_paa = _normal_entries_WIRE_24_10_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_10_eff = _normal_entries_WIRE_24_10_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_10_c = _normal_entries_WIRE_24_10_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_10_fragmented_superpage = _normal_entries_WIRE_24_10_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_11_ppn = _normal_entries_WIRE_24_11_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_11_u = _normal_entries_WIRE_24_11_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_11_g = _normal_entries_WIRE_24_11_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_11_ae = _normal_entries_WIRE_24_11_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_11_sw = _normal_entries_WIRE_24_11_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_11_sx = _normal_entries_WIRE_24_11_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_11_sr = _normal_entries_WIRE_24_11_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_11_pw = _normal_entries_WIRE_24_11_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_11_px = _normal_entries_WIRE_24_11_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_11_pr = _normal_entries_WIRE_24_11_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_11_pal = _normal_entries_WIRE_24_11_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_11_paa = _normal_entries_WIRE_24_11_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_11_eff = _normal_entries_WIRE_24_11_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_11_c = _normal_entries_WIRE_24_11_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_11_fragmented_superpage = _normal_entries_WIRE_24_11_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [1:0] ptw_ae_array_lo_lo_hi = {entries_0_2_ae, entries_0_1_ae}; // @[package.scala:45:27] wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, entries_0_0_ae}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_lo_hi_hi = {entries_0_5_ae, entries_0_4_ae}; // @[package.scala:45:27] wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, entries_0_3_ae}; // @[package.scala:45:27] wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_lo_hi = {entries_0_8_ae, entries_0_7_ae}; // @[package.scala:45:27] wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, entries_0_6_ae}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_hi_lo = {entries_0_10_ae, entries_0_9_ae}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_hi_hi = {entries_0_12_ae, entries_0_11_ae}; // @[package.scala:45:27] wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] _ptw_ae_array_T_1 = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [13:0] ptw_ae_array_0 = _ptw_ae_array_T_1; // @[tlb.scala:119:49, :214:39] wire [1:0] _GEN_9 = {entries_0_2_u, entries_0_1_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi = _GEN_9; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi_1 = _GEN_9; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi = _GEN_9; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi_1 = _GEN_9; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, entries_0_0_u}; // @[package.scala:45:27] wire [1:0] _GEN_10 = {entries_0_5_u, entries_0_4_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi = _GEN_10; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi_1 = _GEN_10; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi = _GEN_10; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi_1 = _GEN_10; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, entries_0_3_u}; // @[package.scala:45:27] wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_11 = {entries_0_8_u, entries_0_7_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi = _GEN_11; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi_1 = _GEN_11; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi = _GEN_11; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi_1 = _GEN_11; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, entries_0_6_u}; // @[package.scala:45:27] wire [1:0] _GEN_12 = {entries_0_10_u, entries_0_9_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo = _GEN_12; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo_1 = _GEN_12; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo = _GEN_12; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo_1 = _GEN_12; // @[package.scala:45:27] wire [1:0] _GEN_13 = {entries_0_12_u, entries_0_11_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi = _GEN_13; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi_1 = _GEN_13; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi = _GEN_13; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi_1 = _GEN_13; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_2; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_7 = _priv_rw_ok_T_3; // @[tlb.scala:215:{39,103}] wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, entries_0_0_u}; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, entries_0_3_u}; // @[package.scala:45:27] wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, entries_0_6_u}; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] priv_rw_ok_0 = _priv_rw_ok_T_7; // @[tlb.scala:119:49, :215:103] wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, entries_0_0_u}; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, entries_0_3_u}; // @[package.scala:45:27] wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, entries_0_6_u}; // @[package.scala:45:27] wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, entries_0_0_u}; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, entries_0_3_u}; // @[package.scala:45:27] wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, entries_0_6_u}; // @[package.scala:45:27] wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_3 = _priv_x_ok_T_2; // @[package.scala:45:27] wire [12:0] priv_x_ok_0 = _priv_x_ok_T_3; // @[tlb.scala:119:49, :216:39] wire [1:0] r_array_lo_lo_hi = {entries_0_2_sr, entries_0_1_sr}; // @[package.scala:45:27] wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, entries_0_0_sr}; // @[package.scala:45:27] wire [1:0] r_array_lo_hi_hi = {entries_0_5_sr, entries_0_4_sr}; // @[package.scala:45:27] wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, entries_0_3_sr}; // @[package.scala:45:27] wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_hi = {entries_0_8_sr, entries_0_7_sr}; // @[package.scala:45:27] wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, entries_0_6_sr}; // @[package.scala:45:27] wire [1:0] r_array_hi_hi_lo = {entries_0_10_sr, entries_0_9_sr}; // @[package.scala:45:27] wire [1:0] r_array_hi_hi_hi = {entries_0_12_sr, entries_0_11_sr}; // @[package.scala:45:27] wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [12:0] _r_array_T_3 = _r_array_T; // @[package.scala:45:27] wire [1:0] _GEN_14 = {entries_0_2_sx, entries_0_1_sx}; // @[package.scala:45:27] wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_lo_hi_1 = _GEN_14; // @[package.scala:45:27] wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27] assign x_array_lo_lo_hi = _GEN_14; // @[package.scala:45:27] wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, entries_0_0_sx}; // @[package.scala:45:27] wire [1:0] _GEN_15 = {entries_0_5_sx, entries_0_4_sx}; // @[package.scala:45:27] wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_hi_1 = _GEN_15; // @[package.scala:45:27] wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27] assign x_array_lo_hi_hi = _GEN_15; // @[package.scala:45:27] wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, entries_0_3_sx}; // @[package.scala:45:27] wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_16 = {entries_0_8_sx, entries_0_7_sx}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27] assign r_array_hi_lo_hi_1 = _GEN_16; // @[package.scala:45:27] wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27] assign x_array_hi_lo_hi = _GEN_16; // @[package.scala:45:27] wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, entries_0_6_sx}; // @[package.scala:45:27] wire [1:0] _GEN_17 = {entries_0_10_sx, entries_0_9_sx}; // @[package.scala:45:27] wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27] assign r_array_hi_hi_lo_1 = _GEN_17; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27] assign x_array_hi_hi_lo = _GEN_17; // @[package.scala:45:27] wire [1:0] _GEN_18 = {entries_0_12_sx, entries_0_11_sx}; // @[package.scala:45:27] wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_hi_1 = _GEN_18; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi_hi = _GEN_18; // @[package.scala:45:27] wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_4 = priv_rw_ok_0 & _r_array_T_3; // @[tlb.scala:119:49, :217:{62,93}] wire [13:0] _r_array_T_5 = {1'h1, _r_array_T_4}; // @[tlb.scala:217:{39,62}] wire [13:0] r_array_0 = _r_array_T_5; // @[tlb.scala:119:49, :217:39] wire [1:0] w_array_lo_lo_hi = {entries_0_2_sw, entries_0_1_sw}; // @[package.scala:45:27] wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, entries_0_0_sw}; // @[package.scala:45:27] wire [1:0] w_array_lo_hi_hi = {entries_0_5_sw, entries_0_4_sw}; // @[package.scala:45:27] wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, entries_0_3_sw}; // @[package.scala:45:27] wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] w_array_hi_lo_hi = {entries_0_8_sw, entries_0_7_sw}; // @[package.scala:45:27] wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, entries_0_6_sw}; // @[package.scala:45:27] wire [1:0] w_array_hi_hi_lo = {entries_0_10_sw, entries_0_9_sw}; // @[package.scala:45:27] wire [1:0] w_array_hi_hi_hi = {entries_0_12_sw, entries_0_11_sw}; // @[package.scala:45:27] wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T_1 = priv_rw_ok_0 & _w_array_T; // @[package.scala:45:27] wire [13:0] _w_array_T_2 = {1'h1, _w_array_T_1}; // @[tlb.scala:218:{39,62}] wire [13:0] w_array_0 = _w_array_T_2; // @[tlb.scala:119:49, :218:39] wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, entries_0_0_sx}; // @[package.scala:45:27] wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, entries_0_3_sx}; // @[package.scala:45:27] wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, entries_0_6_sx}; // @[package.scala:45:27] wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T_1 = priv_x_ok_0 & _x_array_T; // @[package.scala:45:27] wire [13:0] _x_array_T_2 = {1'h1, _x_array_T_1}; // @[tlb.scala:219:{39,62}] wire [13:0] x_array_0 = _x_array_T_2; // @[tlb.scala:119:49, :219:39] wire [1:0] _pr_array_T = {2{prot_r_0}}; // @[tlb.scala:119:49, :220:44] wire [1:0] pr_array_lo_lo_hi = {normal_entries_0_2_pr, normal_entries_0_1_pr}; // @[package.scala:45:27] wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, normal_entries_0_0_pr}; // @[package.scala:45:27] wire [1:0] pr_array_lo_hi_hi = {normal_entries_0_5_pr, normal_entries_0_4_pr}; // @[package.scala:45:27] wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, normal_entries_0_3_pr}; // @[package.scala:45:27] wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pr_array_hi_lo_hi = {normal_entries_0_8_pr, normal_entries_0_7_pr}; // @[package.scala:45:27] wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, normal_entries_0_6_pr}; // @[package.scala:45:27] wire [1:0] pr_array_hi_hi_hi = {normal_entries_0_11_pr, normal_entries_0_10_pr}; // @[package.scala:45:27] wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, normal_entries_0_9_pr}; // @[package.scala:45:27] wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _pr_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:119:49, :220:116] wire [13:0] _pr_array_T_4 = _pr_array_T_2 & _pr_array_T_3; // @[tlb.scala:220:{39,114,116}] wire [13:0] pr_array_0 = _pr_array_T_4; // @[tlb.scala:119:49, :220:114] wire [1:0] _pw_array_T = {2{prot_w_0}}; // @[tlb.scala:119:49, :221:44] wire [1:0] pw_array_lo_lo_hi = {normal_entries_0_2_pw, normal_entries_0_1_pw}; // @[package.scala:45:27] wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, normal_entries_0_0_pw}; // @[package.scala:45:27] wire [1:0] pw_array_lo_hi_hi = {normal_entries_0_5_pw, normal_entries_0_4_pw}; // @[package.scala:45:27] wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, normal_entries_0_3_pw}; // @[package.scala:45:27] wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pw_array_hi_lo_hi = {normal_entries_0_8_pw, normal_entries_0_7_pw}; // @[package.scala:45:27] wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, normal_entries_0_6_pw}; // @[package.scala:45:27] wire [1:0] pw_array_hi_hi_hi = {normal_entries_0_11_pw, normal_entries_0_10_pw}; // @[package.scala:45:27] wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, normal_entries_0_9_pw}; // @[package.scala:45:27] wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [13:0] _pw_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:119:49, :220:116, :221:116] wire [13:0] _pw_array_T_4 = _pw_array_T_2 & _pw_array_T_3; // @[tlb.scala:221:{39,114,116}] wire [13:0] pw_array_0 = _pw_array_T_4; // @[tlb.scala:119:49, :221:114] wire [1:0] _px_array_T = {2{prot_x_0}}; // @[tlb.scala:119:49, :222:44] wire [1:0] px_array_lo_lo_hi = {normal_entries_0_2_px, normal_entries_0_1_px}; // @[package.scala:45:27] wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, normal_entries_0_0_px}; // @[package.scala:45:27] wire [1:0] px_array_lo_hi_hi = {normal_entries_0_5_px, normal_entries_0_4_px}; // @[package.scala:45:27] wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, normal_entries_0_3_px}; // @[package.scala:45:27] wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] px_array_hi_lo_hi = {normal_entries_0_8_px, normal_entries_0_7_px}; // @[package.scala:45:27] wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, normal_entries_0_6_px}; // @[package.scala:45:27] wire [1:0] px_array_hi_hi_hi = {normal_entries_0_11_px, normal_entries_0_10_px}; // @[package.scala:45:27] wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, normal_entries_0_9_px}; // @[package.scala:45:27] wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [13:0] _px_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:119:49, :220:116, :222:116] wire [13:0] _px_array_T_4 = _px_array_T_2 & _px_array_T_3; // @[tlb.scala:222:{39,114,116}] wire [13:0] px_array_0 = _px_array_T_4; // @[tlb.scala:119:49, :222:114] wire [1:0] _eff_array_T = {2{prot_eff_0}}; // @[tlb.scala:119:49, :223:44] wire [1:0] eff_array_lo_lo_hi = {normal_entries_0_2_eff, normal_entries_0_1_eff}; // @[package.scala:45:27] wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, normal_entries_0_0_eff}; // @[package.scala:45:27] wire [1:0] eff_array_lo_hi_hi = {normal_entries_0_5_eff, normal_entries_0_4_eff}; // @[package.scala:45:27] wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, normal_entries_0_3_eff}; // @[package.scala:45:27] wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] eff_array_hi_lo_hi = {normal_entries_0_8_eff, normal_entries_0_7_eff}; // @[package.scala:45:27] wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, normal_entries_0_6_eff}; // @[package.scala:45:27] wire [1:0] eff_array_hi_hi_hi = {normal_entries_0_11_eff, normal_entries_0_10_eff}; // @[package.scala:45:27] wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, normal_entries_0_9_eff}; // @[package.scala:45:27] wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [13:0] _eff_array_T_2 = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [13:0] eff_array_0 = _eff_array_T_2; // @[tlb.scala:119:49, :223:39] wire [1:0] _c_array_T = {2{cacheable_0}}; // @[tlb.scala:119:49, :224:44] wire [1:0] _GEN_19 = {normal_entries_0_2_c, normal_entries_0_1_c}; // @[package.scala:45:27] wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27] assign c_array_lo_lo_hi = _GEN_19; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign prefetchable_array_lo_lo_hi = _GEN_19; // @[package.scala:45:27] wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, normal_entries_0_0_c}; // @[package.scala:45:27] wire [1:0] _GEN_20 = {normal_entries_0_5_c, normal_entries_0_4_c}; // @[package.scala:45:27] wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27] assign c_array_lo_hi_hi = _GEN_20; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign prefetchable_array_lo_hi_hi = _GEN_20; // @[package.scala:45:27] wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, normal_entries_0_3_c}; // @[package.scala:45:27] wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_21 = {normal_entries_0_8_c, normal_entries_0_7_c}; // @[package.scala:45:27] wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27] assign c_array_hi_lo_hi = _GEN_21; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign prefetchable_array_hi_lo_hi = _GEN_21; // @[package.scala:45:27] wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, normal_entries_0_6_c}; // @[package.scala:45:27] wire [1:0] _GEN_22 = {normal_entries_0_11_c, normal_entries_0_10_c}; // @[package.scala:45:27] wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi_hi = _GEN_22; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi_hi = _GEN_22; // @[package.scala:45:27] wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, normal_entries_0_9_c}; // @[package.scala:45:27] wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [13:0] _c_array_T_2 = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [13:0] c_array_0 = _c_array_T_2; // @[tlb.scala:119:49, :224:39] wire [13:0] _paa_array_if_cached_T = c_array_0; // @[tlb.scala:119:49, :227:61] wire [13:0] _pal_array_if_cached_T = c_array_0; // @[tlb.scala:119:49, :228:61] wire [13:0] _lrscAllowed_T = c_array_0; // @[tlb.scala:119:49, :250:38] wire [1:0] _paa_array_T = {2{prot_aa_0}}; // @[tlb.scala:119:49, :225:44] wire [1:0] paa_array_lo_lo_hi = {normal_entries_0_2_paa, normal_entries_0_1_paa}; // @[package.scala:45:27] wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, normal_entries_0_0_paa}; // @[package.scala:45:27] wire [1:0] paa_array_lo_hi_hi = {normal_entries_0_5_paa, normal_entries_0_4_paa}; // @[package.scala:45:27] wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, normal_entries_0_3_paa}; // @[package.scala:45:27] wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] paa_array_hi_lo_hi = {normal_entries_0_8_paa, normal_entries_0_7_paa}; // @[package.scala:45:27] wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, normal_entries_0_6_paa}; // @[package.scala:45:27] wire [1:0] paa_array_hi_hi_hi = {normal_entries_0_11_paa, normal_entries_0_10_paa}; // @[package.scala:45:27] wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, normal_entries_0_9_paa}; // @[package.scala:45:27] wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [13:0] _paa_array_T_2 = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [13:0] paa_array_0 = _paa_array_T_2; // @[tlb.scala:119:49, :225:39] wire [1:0] _pal_array_T = {2{prot_al_0}}; // @[tlb.scala:119:49, :226:44] wire [1:0] pal_array_lo_lo_hi = {normal_entries_0_2_pal, normal_entries_0_1_pal}; // @[package.scala:45:27] wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, normal_entries_0_0_pal}; // @[package.scala:45:27] wire [1:0] pal_array_lo_hi_hi = {normal_entries_0_5_pal, normal_entries_0_4_pal}; // @[package.scala:45:27] wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, normal_entries_0_3_pal}; // @[package.scala:45:27] wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pal_array_hi_lo_hi = {normal_entries_0_8_pal, normal_entries_0_7_pal}; // @[package.scala:45:27] wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, normal_entries_0_6_pal}; // @[package.scala:45:27] wire [1:0] pal_array_hi_hi_hi = {normal_entries_0_11_pal, normal_entries_0_10_pal}; // @[package.scala:45:27] wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, normal_entries_0_9_pal}; // @[package.scala:45:27] wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [13:0] _pal_array_T_2 = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [13:0] pal_array_0 = _pal_array_T_2; // @[tlb.scala:119:49, :226:39] wire [13:0] _paa_array_if_cached_T_1 = paa_array_0 | _paa_array_if_cached_T; // @[tlb.scala:119:49, :227:{56,61}] wire [13:0] paa_array_if_cached_0 = _paa_array_if_cached_T_1; // @[tlb.scala:119:49, :227:56] wire [13:0] _pal_array_if_cached_T_1 = pal_array_0 | _pal_array_if_cached_T; // @[tlb.scala:119:49, :228:{56,61}] wire [13:0] pal_array_if_cached_0 = _pal_array_if_cached_T_1; // @[tlb.scala:119:49, :228:56] wire _prefetchable_array_T = cacheable_0 & homogeneous_0; // @[tlb.scala:119:49, :229:61] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[tlb.scala:229:{61,80}] wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, normal_entries_0_0_c}; // @[package.scala:45:27] wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, normal_entries_0_3_c}; // @[package.scala:45:27] wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, normal_entries_0_6_c}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, normal_entries_0_9_c}; // @[package.scala:45:27] wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] _prefetchable_array_T_3 = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [13:0] prefetchable_array_0 = _prefetchable_array_T_3; // @[tlb.scala:119:49, :229:46] wire [3:0] _misaligned_T = 4'h1 << io_req_0_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[tlb.scala:231:89] wire [33:0] _misaligned_T_3 = {30'h0, io_req_0_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[tlb.scala:17:7, :19:14, :231:{56,89}] wire _misaligned_T_4 = |_misaligned_T_3; // @[tlb.scala:231:{56,97}] wire misaligned_0 = _misaligned_T_4; // @[tlb.scala:119:49, :231:97] wire _GEN_23 = io_req_0_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_23; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_0_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_24; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_24; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_24; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire _cmd_lrsc_T_3 = _cmd_lrsc_T_2; // @[package.scala:81:59] wire cmd_lrsc_0 = _cmd_lrsc_T_3; // @[tlb.scala:119:49, :242:57] wire _GEN_25 = io_req_0_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_25; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_25; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_25; // @[package.scala:16:47] wire _GEN_26 = io_req_0_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_26; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_26; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_26; // @[package.scala:16:47] wire _GEN_27 = io_req_0_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_27; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_27; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_27; // @[package.scala:16:47] wire _GEN_28 = io_req_0_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_28; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_28; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_28; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T | _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 | _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 | _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_7 = _cmd_amo_logical_T_6; // @[package.scala:81:59] wire cmd_amo_logical_0 = _cmd_amo_logical_T_7; // @[tlb.scala:119:49, :243:57] wire _GEN_29 = io_req_0_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_29; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_29; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_29; // @[package.scala:16:47] wire _GEN_30 = io_req_0_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_30; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_30; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = io_req_0_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_31; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_31; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_31; // @[package.scala:16:47] wire _GEN_32 = io_req_0_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_32; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_32; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = io_req_0_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_33; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_33; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_33; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 | _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 | _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 | _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_9 = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire cmd_amo_arithmetic_0 = _cmd_amo_arithmetic_T_9; // @[tlb.scala:119:49, :244:57] wire _cmd_read_T = io_req_0_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _cmd_read_T_1 = io_req_0_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T | _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 | _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 | _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 | _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 | _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 | _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 | _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 | _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 | _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 | _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 | _cmd_read_T_22; // @[package.scala:81:59] wire _cmd_read_T_24 = _cmd_read_T_6 | _cmd_read_T_23; // @[package.scala:81:59] wire cmd_read_0 = _cmd_read_T_24; // @[Consts.scala:89:68] wire _cmd_write_T = io_req_0_bits_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _cmd_write_T_1 = io_req_0_bits_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _cmd_write_T_2 = _cmd_write_T | _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 | _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 | _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 | _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 | _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 | _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 | _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 | _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 | _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 | _cmd_write_T_20; // @[package.scala:81:59] wire _cmd_write_T_22 = _cmd_write_T_4 | _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire cmd_write_0 = _cmd_write_T_22; // @[Consts.scala:90:76] wire _cmd_write_perms_T_2 = cmd_write_0; // @[tlb.scala:119:49, :247:55] wire _cmd_write_perms_T = io_req_0_bits_cmd_0 == 5'h5; // @[tlb.scala:17:7, :248:51] wire cmd_write_perms_0 = _cmd_write_perms_T_2; // @[tlb.scala:119:49, :247:55] wire [13:0] lrscAllowed_0 = _lrscAllowed_T; // @[tlb.scala:119:49, :250:38] wire [13:0] _ae_array_T = misaligned_0 ? eff_array_0 : 14'h0; // @[tlb.scala:119:49, :252:8] wire [13:0] _ae_array_T_1 = ~lrscAllowed_0; // @[tlb.scala:119:49, :253:24] wire [13:0] _ae_array_T_2 = cmd_lrsc_0 ? _ae_array_T_1 : 14'h0; // @[tlb.scala:119:49, :253:{8,24}] wire [13:0] _ae_array_T_3 = _ae_array_T | _ae_array_T_2; // @[tlb.scala:252:{8,43}, :253:8] wire [13:0] ae_array_0 = _ae_array_T_3; // @[tlb.scala:119:49, :252:43] wire [13:0] _ae_ld_array_T = ~pr_array_0; // @[tlb.scala:119:49, :256:66] wire [13:0] _ae_ld_array_T_1 = ae_array_0 | _ae_ld_array_T; // @[tlb.scala:119:49, :256:{64,66}] wire [13:0] _ae_ld_array_T_2 = cmd_read_0 ? _ae_ld_array_T_1 : 14'h0; // @[tlb.scala:119:49, :256:{38,64}] wire [13:0] ae_ld_array_0 = _ae_ld_array_T_2; // @[tlb.scala:119:49, :256:38] wire [13:0] _io_resp_0_ae_ld_T = ae_ld_array_0; // @[tlb.scala:119:49, :301:46] wire [13:0] _ae_st_array_T = ~pw_array_0; // @[tlb.scala:119:49, :258:46] wire [13:0] _ae_st_array_T_1 = ae_array_0 | _ae_st_array_T; // @[tlb.scala:119:49, :258:{44,46}] wire [13:0] _ae_st_array_T_2 = cmd_write_perms_0 ? _ae_st_array_T_1 : 14'h0; // @[tlb.scala:119:49, :258:{8,44}] wire [13:0] _ae_st_array_T_3 = ~pal_array_if_cached_0; // @[tlb.scala:119:49, :259:32] wire [13:0] _ae_st_array_T_4 = cmd_amo_logical_0 ? _ae_st_array_T_3 : 14'h0; // @[tlb.scala:119:49, :259:{8,32}] wire [13:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[tlb.scala:258:{8,65}, :259:8] wire [13:0] _ae_st_array_T_6 = ~paa_array_if_cached_0; // @[tlb.scala:119:49, :260:32] wire [13:0] _ae_st_array_T_7 = cmd_amo_arithmetic_0 ? _ae_st_array_T_6 : 14'h0; // @[tlb.scala:119:49, :260:{8,32}] wire [13:0] _ae_st_array_T_8 = _ae_st_array_T_5 | _ae_st_array_T_7; // @[tlb.scala:258:65, :259:62, :260:8] wire [13:0] ae_st_array_0 = _ae_st_array_T_8; // @[tlb.scala:119:49, :259:62] wire [13:0] _io_resp_0_ae_st_T = ae_st_array_0; // @[tlb.scala:119:49, :302:46] wire [13:0] _must_alloc_array_T = ~paa_array_0; // @[tlb.scala:119:49, :262:32] wire [13:0] _must_alloc_array_T_1 = cmd_amo_logical_0 ? _must_alloc_array_T : 14'h0; // @[tlb.scala:119:49, :262:{8,32}] wire [13:0] _must_alloc_array_T_2 = ~pal_array_0; // @[tlb.scala:119:49, :263:32] wire [13:0] _must_alloc_array_T_3 = cmd_amo_arithmetic_0 ? _must_alloc_array_T_2 : 14'h0; // @[tlb.scala:119:49, :263:{8,32}] wire [13:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 | _must_alloc_array_T_3; // @[tlb.scala:262:{8,52}, :263:8] wire [13:0] _must_alloc_array_T_6 = {14{cmd_lrsc_0}}; // @[tlb.scala:119:49, :264:8] wire [13:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 | _must_alloc_array_T_6; // @[tlb.scala:262:52, :263:52, :264:8] wire [13:0] must_alloc_array_0 = _must_alloc_array_T_7; // @[tlb.scala:119:49, :263:52] wire _ma_ld_array_T = misaligned_0 & cmd_read_0; // @[tlb.scala:119:49, :265:53] wire [13:0] _ma_ld_array_T_1 = ~eff_array_0; // @[tlb.scala:119:49, :265:70] wire [13:0] _ma_ld_array_T_2 = _ma_ld_array_T ? _ma_ld_array_T_1 : 14'h0; // @[tlb.scala:265:{38,53,70}] wire [13:0] ma_ld_array_0 = _ma_ld_array_T_2; // @[tlb.scala:119:49, :265:38] wire _ma_st_array_T = misaligned_0 & cmd_write_0; // @[tlb.scala:119:49, :266:53] wire [13:0] _ma_st_array_T_1 = ~eff_array_0; // @[tlb.scala:119:49, :265:70, :266:70] wire [13:0] _ma_st_array_T_2 = _ma_st_array_T ? _ma_st_array_T_1 : 14'h0; // @[tlb.scala:266:{38,53,70}] wire [13:0] ma_st_array_0 = _ma_st_array_T_2; // @[tlb.scala:119:49, :266:38] wire [13:0] _pf_ld_array_T = r_array_0 | ptw_ae_array_0; // @[tlb.scala:119:49, :267:72] wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[tlb.scala:267:{59,72}] wire [13:0] _pf_ld_array_T_2 = cmd_read_0 ? _pf_ld_array_T_1 : 14'h0; // @[tlb.scala:119:49, :267:{38,59}] wire [13:0] pf_ld_array_0 = _pf_ld_array_T_2; // @[tlb.scala:119:49, :267:38] wire [13:0] _pf_st_array_T = w_array_0 | ptw_ae_array_0; // @[tlb.scala:119:49, :268:72] wire [13:0] _pf_st_array_T_1 = ~_pf_st_array_T; // @[tlb.scala:268:{59,72}] wire [13:0] _pf_st_array_T_2 = cmd_write_perms_0 ? _pf_st_array_T_1 : 14'h0; // @[tlb.scala:119:49, :268:{38,59}] wire [13:0] pf_st_array_0 = _pf_st_array_T_2; // @[tlb.scala:119:49, :268:38] wire [13:0] _pf_inst_array_T = x_array_0 | ptw_ae_array_0; // @[tlb.scala:119:49, :269:50] wire [13:0] _pf_inst_array_T_1 = ~_pf_inst_array_T; // @[tlb.scala:269:{37,50}] wire [13:0] pf_inst_array_0 = _pf_inst_array_T_1; // @[tlb.scala:119:49, :269:37] wire [1:0] lo_lo = {sector_hits_0_1, sector_hits_0_0}; // @[OneHot.scala:22:45] wire [1:0] lo_hi = {sector_hits_0_3, sector_hits_0_2}; // @[OneHot.scala:22:45] wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:22:45] wire [3:0] lo_1 = lo; // @[OneHot.scala:22:45, :31:18] wire [1:0] hi_lo = {sector_hits_0_5, sector_hits_0_4}; // @[OneHot.scala:22:45] wire [1:0] hi_hi = {sector_hits_0_7, sector_hits_0_6}; // @[OneHot.scala:22:45] wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:22:45] wire [3:0] hi_1 = hi; // @[OneHot.scala:22:45, :30:18] wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_reg_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[2]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_11 = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_1 = _state_reg_T[1]; // @[package.scala:163:13] wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire _state_reg_T_1 = _state_reg_T[0]; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T[0]; // @[package.scala:163:13] wire _state_reg_T_2 = _state_reg_T_1; // @[package.scala:163:13] wire _state_reg_T_3 = ~_state_reg_T_2; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_4 = ~state_reg_set_left_older_1 & _state_reg_T_3; // @[Replacement.scala:196:33, :203:16, :218:7] wire _state_reg_T_6 = _state_reg_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_7 = ~_state_reg_T_6; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_8 = state_reg_set_left_older_1 & _state_reg_T_7; // @[Replacement.scala:196:33, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older_1, _state_reg_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_9 = {state_reg_hi, _state_reg_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_10 = state_reg_set_left_older ? 3'h0 : _state_reg_T_9; // @[Replacement.scala:196:33, :202:12, :203:16] wire _state_reg_set_left_older_T_2 = _state_reg_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire _state_reg_T_12 = _state_reg_T_11[0]; // @[package.scala:163:13] wire _state_reg_T_16 = _state_reg_T_11[0]; // @[package.scala:163:13] wire _state_reg_T_13 = _state_reg_T_12; // @[package.scala:163:13] wire _state_reg_T_14 = ~_state_reg_T_13; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_15 = ~state_reg_set_left_older_2 & _state_reg_T_14; // @[Replacement.scala:196:33, :203:16, :218:7] wire _state_reg_T_17 = _state_reg_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_18 = ~_state_reg_T_17; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_19 = state_reg_set_left_older_2 & _state_reg_T_18; // @[Replacement.scala:196:33, :206:16, :218:7] wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_2, _state_reg_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_20 = {state_reg_hi_1, _state_reg_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_21 = state_reg_set_left_older ? _state_reg_T_20 : 3'h0; // @[Replacement.scala:196:33, :202:12, :206:16] wire [3:0] state_reg_hi_2 = {state_reg_set_left_older, _state_reg_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_22 = {state_reg_hi_2, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16] wire [1:0] lo_3 = {superpage_hits_0_1, superpage_hits_0_0}; // @[OneHot.scala:22:45] wire [1:0] lo_4 = lo_3; // @[OneHot.scala:22:45, :31:18] wire [1:0] hi_3 = {superpage_hits_0_3, superpage_hits_0_2}; // @[OneHot.scala:22:45] wire [1:0] hi_4 = hi_3; // @[OneHot.scala:22:45, :30:18] wire [1:0] state_reg_touch_way_sized_1 = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T_3 = state_reg_touch_way_sized_1[1]; // @[package.scala:163:13] wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}] wire _state_reg_T_23 = state_reg_touch_way_sized_1[0]; // @[package.scala:163:13] wire _state_reg_T_27 = state_reg_touch_way_sized_1[0]; // @[package.scala:163:13] wire _state_reg_T_24 = _state_reg_T_23; // @[package.scala:163:13] wire _state_reg_T_25 = ~_state_reg_T_24; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_26 = ~state_reg_set_left_older_3 & _state_reg_T_25; // @[Replacement.scala:196:33, :203:16, :218:7] wire _state_reg_T_28 = _state_reg_T_27; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_29 = ~_state_reg_T_28; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_30 = state_reg_set_left_older_3 & _state_reg_T_29; // @[Replacement.scala:196:33, :206:16, :218:7] wire [1:0] state_reg_hi_3 = {state_reg_set_left_older_3, _state_reg_T_26}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_31 = {state_reg_hi_3, _state_reg_T_30}; // @[Replacement.scala:202:12, :206:16] wire [13:0] _io_resp_0_pf_ld_T_1 = pf_ld_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :298:73] wire _io_resp_0_pf_ld_T_2 = |_io_resp_0_pf_ld_T_1; // @[tlb.scala:298:{73,84}] assign _io_resp_0_pf_ld_T_3 = _io_resp_0_pf_ld_T_2; // @[tlb.scala:298:{54,84}] assign io_resp_0_pf_ld_0 = _io_resp_0_pf_ld_T_3; // @[tlb.scala:17:7, :298:54] wire [13:0] _io_resp_0_pf_st_T_1 = pf_st_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :299:80] wire _io_resp_0_pf_st_T_2 = |_io_resp_0_pf_st_T_1; // @[tlb.scala:299:{80,91}] assign _io_resp_0_pf_st_T_3 = _io_resp_0_pf_st_T_2; // @[tlb.scala:299:{61,91}] assign io_resp_0_pf_st_0 = _io_resp_0_pf_st_T_3; // @[tlb.scala:17:7, :299:61] wire [13:0] _io_resp_0_pf_inst_T = pf_inst_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :300:58] wire _io_resp_0_pf_inst_T_1 = |_io_resp_0_pf_inst_T; // @[tlb.scala:300:{58,69}] assign _io_resp_0_pf_inst_T_2 = _io_resp_0_pf_inst_T_1; // @[tlb.scala:300:{37,69}] assign io_resp_0_pf_inst = _io_resp_0_pf_inst_T_2; // @[tlb.scala:17:7, :300:37] wire [13:0] _io_resp_0_ae_ld_T_1 = _io_resp_0_ae_ld_T & 14'h2000; // @[tlb.scala:119:49, :173:31, :301:{46,63}] assign _io_resp_0_ae_ld_T_2 = |_io_resp_0_ae_ld_T_1; // @[tlb.scala:301:{63,74}] assign io_resp_0_ae_ld_0 = _io_resp_0_ae_ld_T_2; // @[tlb.scala:17:7, :301:74] wire [13:0] _io_resp_0_ae_st_T_1 = _io_resp_0_ae_st_T & 14'h2000; // @[tlb.scala:119:49, :173:31, :302:{46,63}] assign _io_resp_0_ae_st_T_2 = |_io_resp_0_ae_st_T_1; // @[tlb.scala:302:{63,74}] assign io_resp_0_ae_st_0 = _io_resp_0_ae_st_T_2; // @[tlb.scala:17:7, :302:74] wire [13:0] _io_resp_0_ae_inst_T = ~px_array_0; // @[tlb.scala:119:49, :303:48] wire [13:0] _io_resp_0_ae_inst_T_1 = _io_resp_0_ae_inst_T; // @[tlb.scala:303:{46,48}] wire [13:0] _io_resp_0_ae_inst_T_2 = _io_resp_0_ae_inst_T_1 & 14'h2000; // @[tlb.scala:119:49, :173:31, :303:{46,63}] assign _io_resp_0_ae_inst_T_3 = |_io_resp_0_ae_inst_T_2; // @[tlb.scala:303:{63,74}] assign io_resp_0_ae_inst = _io_resp_0_ae_inst_T_3; // @[tlb.scala:17:7, :303:74] wire [13:0] _io_resp_0_ma_ld_T = ma_ld_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :304:43] assign _io_resp_0_ma_ld_T_1 = |_io_resp_0_ma_ld_T; // @[tlb.scala:304:{43,54}] assign io_resp_0_ma_ld_0 = _io_resp_0_ma_ld_T_1; // @[tlb.scala:17:7, :304:54] wire [13:0] _io_resp_0_ma_st_T = ma_st_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :305:43] assign _io_resp_0_ma_st_T_1 = |_io_resp_0_ma_st_T; // @[tlb.scala:305:{43,54}] assign io_resp_0_ma_st_0 = _io_resp_0_ma_st_T_1; // @[tlb.scala:17:7, :305:54] wire [13:0] _io_resp_0_cacheable_T = c_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :307:44] assign _io_resp_0_cacheable_T_1 = |_io_resp_0_cacheable_T; // @[tlb.scala:307:{44,55}] assign io_resp_0_cacheable_0 = _io_resp_0_cacheable_T_1; // @[tlb.scala:17:7, :307:55] wire [13:0] _io_resp_0_must_alloc_T = must_alloc_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :308:53] assign _io_resp_0_must_alloc_T_1 = |_io_resp_0_must_alloc_T; // @[tlb.scala:308:{53,64}] assign io_resp_0_must_alloc = _io_resp_0_must_alloc_T_1; // @[tlb.scala:17:7, :308:64] wire [13:0] _io_resp_0_prefetchable_T = prefetchable_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :309:55] wire _io_resp_0_prefetchable_T_1 = |_io_resp_0_prefetchable_T; // @[tlb.scala:309:{55,66}] assign _io_resp_0_prefetchable_T_2 = _io_resp_0_prefetchable_T_1; // @[tlb.scala:309:{66,70}] assign io_resp_0_prefetchable = _io_resp_0_prefetchable_T_2; // @[tlb.scala:17:7, :309:70] assign _io_resp_0_paddr_T_1 = {ppn_0, _io_resp_0_paddr_T}; // @[tlb.scala:119:49, :311:{28,57}] assign io_resp_0_paddr_0 = _io_resp_0_paddr_T_1; // @[tlb.scala:17:7, :311:28] OptimizationBarrier_EntryData mpu_ppn_data_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_mpu_ppn_data_WIRE_ppn), // @[tlb.scala:58:79] .io_x_u (_mpu_ppn_data_WIRE_u), // @[tlb.scala:58:79] .io_x_g (_mpu_ppn_data_WIRE_g), // @[tlb.scala:58:79] .io_x_ae (_mpu_ppn_data_WIRE_ae), // @[tlb.scala:58:79] .io_x_sw (_mpu_ppn_data_WIRE_sw), // @[tlb.scala:58:79] .io_x_sx (_mpu_ppn_data_WIRE_sx), // @[tlb.scala:58:79] .io_x_sr (_mpu_ppn_data_WIRE_sr), // @[tlb.scala:58:79] .io_x_pw (_mpu_ppn_data_WIRE_pw), // @[tlb.scala:58:79] .io_x_px (_mpu_ppn_data_WIRE_px), // @[tlb.scala:58:79] .io_x_pr (_mpu_ppn_data_WIRE_pr), // @[tlb.scala:58:79] .io_x_pal (_mpu_ppn_data_WIRE_pal), // @[tlb.scala:58:79] .io_x_paa (_mpu_ppn_data_WIRE_paa), // @[tlb.scala:58:79] .io_x_eff (_mpu_ppn_data_WIRE_eff), // @[tlb.scala:58:79] .io_x_c (_mpu_ppn_data_WIRE_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_mpu_ppn_data_WIRE_fragmented_superpage) // @[tlb.scala:58:79] ); // @[package.scala:267:25] PMPChecker_s3 pmp_0 ( // @[tlb.scala:150:40] .clock (clock), .reset (reset), .io_addr (mpu_physaddr_0[31:0]), // @[tlb.scala:119:49, :152:20] .io_size (io_req_0_bits_size_0) // @[tlb.scala:17:7] ); // @[tlb.scala:150:40] OptimizationBarrier_EntryData_1 ppn_data_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_ppn), // @[tlb.scala:58:79] .io_x_u (_ppn_data_WIRE_u), // @[tlb.scala:58:79] .io_x_g (_ppn_data_WIRE_g), // @[tlb.scala:58:79] .io_x_ae (_ppn_data_WIRE_ae), // @[tlb.scala:58:79] .io_x_sw (_ppn_data_WIRE_sw), // @[tlb.scala:58:79] .io_x_sx (_ppn_data_WIRE_sx), // @[tlb.scala:58:79] .io_x_sr (_ppn_data_WIRE_sr), // @[tlb.scala:58:79] .io_x_pw (_ppn_data_WIRE_pw), // @[tlb.scala:58:79] .io_x_px (_ppn_data_WIRE_px), // @[tlb.scala:58:79] .io_x_pr (_ppn_data_WIRE_pr), // @[tlb.scala:58:79] .io_x_pal (_ppn_data_WIRE_pal), // @[tlb.scala:58:79] .io_x_paa (_ppn_data_WIRE_paa), // @[tlb.scala:58:79] .io_x_eff (_ppn_data_WIRE_eff), // @[tlb.scala:58:79] .io_x_c (_ppn_data_WIRE_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_ppn_data_WIRE_fragmented_superpage) // @[tlb.scala:58:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_2 ppn_data_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_2_ppn), // @[tlb.scala:58:79] .io_x_u (_ppn_data_WIRE_2_u), // @[tlb.scala:58:79] .io_x_g (_ppn_data_WIRE_2_g), // @[tlb.scala:58:79] .io_x_ae (_ppn_data_WIRE_2_ae), // @[tlb.scala:58:79] .io_x_sw (_ppn_data_WIRE_2_sw), // @[tlb.scala:58:79] .io_x_sx (_ppn_data_WIRE_2_sx), // @[tlb.scala:58:79] .io_x_sr (_ppn_data_WIRE_2_sr), // @[tlb.scala:58:79] .io_x_pw (_ppn_data_WIRE_2_pw), // @[tlb.scala:58:79] .io_x_px (_ppn_data_WIRE_2_px), // @[tlb.scala:58:79] .io_x_pr (_ppn_data_WIRE_2_pr), // @[tlb.scala:58:79] .io_x_pal (_ppn_data_WIRE_2_pal), // @[tlb.scala:58:79] .io_x_paa (_ppn_data_WIRE_2_paa), // @[tlb.scala:58:79] .io_x_eff (_ppn_data_WIRE_2_eff), // @[tlb.scala:58:79] .io_x_c (_ppn_data_WIRE_2_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_ppn_data_WIRE_2_fragmented_superpage) // @[tlb.scala:58:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_3 ppn_data_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_4_ppn), // @[tlb.scala:58:79] .io_x_u (_ppn_data_WIRE_4_u), // @[tlb.scala:58:79] .io_x_g (_ppn_data_WIRE_4_g), // @[tlb.scala:58:79] .io_x_ae (_ppn_data_WIRE_4_ae), // @[tlb.scala:58:79] .io_x_sw (_ppn_data_WIRE_4_sw), // @[tlb.scala:58:79] .io_x_sx (_ppn_data_WIRE_4_sx), // @[tlb.scala:58:79] .io_x_sr (_ppn_data_WIRE_4_sr), // @[tlb.scala:58:79] .io_x_pw (_ppn_data_WIRE_4_pw), // @[tlb.scala:58:79] .io_x_px (_ppn_data_WIRE_4_px), // @[tlb.scala:58:79] .io_x_pr (_ppn_data_WIRE_4_pr), // @[tlb.scala:58:79] .io_x_pal (_ppn_data_WIRE_4_pal), // @[tlb.scala:58:79] .io_x_paa (_ppn_data_WIRE_4_paa), // @[tlb.scala:58:79] .io_x_eff (_ppn_data_WIRE_4_eff), // @[tlb.scala:58:79] .io_x_c (_ppn_data_WIRE_4_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_ppn_data_WIRE_4_fragmented_superpage) // @[tlb.scala:58:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_4 ppn_data_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_6_ppn), // @[tlb.scala:58:79] .io_x_u (_ppn_data_WIRE_6_u), // @[tlb.scala:58:79] .io_x_g (_ppn_data_WIRE_6_g), // @[tlb.scala:58:79] .io_x_ae (_ppn_data_WIRE_6_ae), // @[tlb.scala:58:79] .io_x_sw (_ppn_data_WIRE_6_sw), // @[tlb.scala:58:79] .io_x_sx (_ppn_data_WIRE_6_sx), // @[tlb.scala:58:79] .io_x_sr (_ppn_data_WIRE_6_sr), // @[tlb.scala:58:79] .io_x_pw (_ppn_data_WIRE_6_pw), // @[tlb.scala:58:79] .io_x_px (_ppn_data_WIRE_6_px), // @[tlb.scala:58:79] .io_x_pr (_ppn_data_WIRE_6_pr), // @[tlb.scala:58:79] .io_x_pal (_ppn_data_WIRE_6_pal), // @[tlb.scala:58:79] .io_x_paa (_ppn_data_WIRE_6_paa), // @[tlb.scala:58:79] .io_x_eff (_ppn_data_WIRE_6_eff), // @[tlb.scala:58:79] .io_x_c (_ppn_data_WIRE_6_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_ppn_data_WIRE_6_fragmented_superpage) // @[tlb.scala:58:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_5 ppn_data_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_8_ppn), // @[tlb.scala:58:79] .io_x_u (_ppn_data_WIRE_8_u), // @[tlb.scala:58:79] .io_x_g (_ppn_data_WIRE_8_g), // @[tlb.scala:58:79] .io_x_ae (_ppn_data_WIRE_8_ae), // @[tlb.scala:58:79] .io_x_sw (_ppn_data_WIRE_8_sw), // @[tlb.scala:58:79] .io_x_sx (_ppn_data_WIRE_8_sx), // @[tlb.scala:58:79] .io_x_sr (_ppn_data_WIRE_8_sr), // @[tlb.scala:58:79] .io_x_pw (_ppn_data_WIRE_8_pw), // @[tlb.scala:58:79] .io_x_px (_ppn_data_WIRE_8_px), // @[tlb.scala:58:79] .io_x_pr (_ppn_data_WIRE_8_pr), // @[tlb.scala:58:79] .io_x_pal (_ppn_data_WIRE_8_pal), // @[tlb.scala:58:79] .io_x_paa (_ppn_data_WIRE_8_paa), // @[tlb.scala:58:79] .io_x_eff (_ppn_data_WIRE_8_eff), // @[tlb.scala:58:79] .io_x_c (_ppn_data_WIRE_8_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_ppn_data_WIRE_8_fragmented_superpage) // @[tlb.scala:58:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_6 ppn_data_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_10_ppn), // @[tlb.scala:58:79] .io_x_u (_ppn_data_WIRE_10_u), // @[tlb.scala:58:79] .io_x_g (_ppn_data_WIRE_10_g), // @[tlb.scala:58:79] .io_x_ae (_ppn_data_WIRE_10_ae), // @[tlb.scala:58:79] .io_x_sw (_ppn_data_WIRE_10_sw), // @[tlb.scala:58:79] .io_x_sx (_ppn_data_WIRE_10_sx), // @[tlb.scala:58:79] .io_x_sr (_ppn_data_WIRE_10_sr), // @[tlb.scala:58:79] .io_x_pw (_ppn_data_WIRE_10_pw), // @[tlb.scala:58:79] .io_x_px (_ppn_data_WIRE_10_px), // @[tlb.scala:58:79] .io_x_pr (_ppn_data_WIRE_10_pr), // @[tlb.scala:58:79] .io_x_pal (_ppn_data_WIRE_10_pal), // @[tlb.scala:58:79] .io_x_paa (_ppn_data_WIRE_10_paa), // @[tlb.scala:58:79] .io_x_eff (_ppn_data_WIRE_10_eff), // @[tlb.scala:58:79] .io_x_c (_ppn_data_WIRE_10_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_ppn_data_WIRE_10_fragmented_superpage) // @[tlb.scala:58:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_7 ppn_data_barrier_6 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_12_ppn), // @[tlb.scala:58:79] .io_x_u (_ppn_data_WIRE_12_u), // @[tlb.scala:58:79] .io_x_g (_ppn_data_WIRE_12_g), // @[tlb.scala:58:79] .io_x_ae (_ppn_data_WIRE_12_ae), // @[tlb.scala:58:79] .io_x_sw (_ppn_data_WIRE_12_sw), // @[tlb.scala:58:79] .io_x_sx (_ppn_data_WIRE_12_sx), // @[tlb.scala:58:79] .io_x_sr (_ppn_data_WIRE_12_sr), // @[tlb.scala:58:79] .io_x_pw (_ppn_data_WIRE_12_pw), // @[tlb.scala:58:79] .io_x_px (_ppn_data_WIRE_12_px), // @[tlb.scala:58:79] .io_x_pr (_ppn_data_WIRE_12_pr), // @[tlb.scala:58:79] .io_x_pal (_ppn_data_WIRE_12_pal), // @[tlb.scala:58:79] .io_x_paa (_ppn_data_WIRE_12_paa), // @[tlb.scala:58:79] .io_x_eff (_ppn_data_WIRE_12_eff), // @[tlb.scala:58:79] .io_x_c (_ppn_data_WIRE_12_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_ppn_data_WIRE_12_fragmented_superpage) // @[tlb.scala:58:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_8 ppn_data_barrier_7 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_14_ppn), // @[tlb.scala:58:79] .io_x_u (_ppn_data_WIRE_14_u), // @[tlb.scala:58:79] .io_x_g (_ppn_data_WIRE_14_g), // @[tlb.scala:58:79] .io_x_ae (_ppn_data_WIRE_14_ae), // @[tlb.scala:58:79] .io_x_sw (_ppn_data_WIRE_14_sw), // @[tlb.scala:58:79] .io_x_sx (_ppn_data_WIRE_14_sx), // @[tlb.scala:58:79] .io_x_sr (_ppn_data_WIRE_14_sr), // @[tlb.scala:58:79] .io_x_pw (_ppn_data_WIRE_14_pw), // @[tlb.scala:58:79] .io_x_px (_ppn_data_WIRE_14_px), // @[tlb.scala:58:79] .io_x_pr (_ppn_data_WIRE_14_pr), // @[tlb.scala:58:79] .io_x_pal (_ppn_data_WIRE_14_pal), // @[tlb.scala:58:79] .io_x_paa (_ppn_data_WIRE_14_paa), // @[tlb.scala:58:79] .io_x_eff (_ppn_data_WIRE_14_eff), // @[tlb.scala:58:79] .io_x_c (_ppn_data_WIRE_14_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_ppn_data_WIRE_14_fragmented_superpage) // @[tlb.scala:58:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_9 ppn_data_barrier_8 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_16_ppn), // @[tlb.scala:58:79] .io_x_u (_ppn_data_WIRE_16_u), // @[tlb.scala:58:79] .io_x_g (_ppn_data_WIRE_16_g), // @[tlb.scala:58:79] .io_x_ae (_ppn_data_WIRE_16_ae), // @[tlb.scala:58:79] .io_x_sw (_ppn_data_WIRE_16_sw), // @[tlb.scala:58:79] .io_x_sx (_ppn_data_WIRE_16_sx), // @[tlb.scala:58:79] .io_x_sr (_ppn_data_WIRE_16_sr), // @[tlb.scala:58:79] .io_x_pw (_ppn_data_WIRE_16_pw), // @[tlb.scala:58:79] .io_x_px (_ppn_data_WIRE_16_px), // @[tlb.scala:58:79] .io_x_pr (_ppn_data_WIRE_16_pr), // @[tlb.scala:58:79] .io_x_pal (_ppn_data_WIRE_16_pal), // @[tlb.scala:58:79] .io_x_paa (_ppn_data_WIRE_16_paa), // @[tlb.scala:58:79] .io_x_eff (_ppn_data_WIRE_16_eff), // @[tlb.scala:58:79] .io_x_c (_ppn_data_WIRE_16_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_ppn_data_WIRE_16_fragmented_superpage) // @[tlb.scala:58:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_10 ppn_data_barrier_9 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_18_ppn), // @[tlb.scala:58:79] .io_x_u (_ppn_data_WIRE_18_u), // @[tlb.scala:58:79] .io_x_g (_ppn_data_WIRE_18_g), // @[tlb.scala:58:79] .io_x_ae (_ppn_data_WIRE_18_ae), // @[tlb.scala:58:79] .io_x_sw (_ppn_data_WIRE_18_sw), // @[tlb.scala:58:79] .io_x_sx (_ppn_data_WIRE_18_sx), // @[tlb.scala:58:79] .io_x_sr (_ppn_data_WIRE_18_sr), // @[tlb.scala:58:79] .io_x_pw (_ppn_data_WIRE_18_pw), // @[tlb.scala:58:79] .io_x_px (_ppn_data_WIRE_18_px), // @[tlb.scala:58:79] .io_x_pr (_ppn_data_WIRE_18_pr), // @[tlb.scala:58:79] .io_x_pal (_ppn_data_WIRE_18_pal), // @[tlb.scala:58:79] .io_x_paa (_ppn_data_WIRE_18_paa), // @[tlb.scala:58:79] .io_x_eff (_ppn_data_WIRE_18_eff), // @[tlb.scala:58:79] .io_x_c (_ppn_data_WIRE_18_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_ppn_data_WIRE_18_fragmented_superpage) // @[tlb.scala:58:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_11 ppn_data_barrier_10 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_20_ppn), // @[tlb.scala:58:79] .io_x_u (_ppn_data_WIRE_20_u), // @[tlb.scala:58:79] .io_x_g (_ppn_data_WIRE_20_g), // @[tlb.scala:58:79] .io_x_ae (_ppn_data_WIRE_20_ae), // @[tlb.scala:58:79] .io_x_sw (_ppn_data_WIRE_20_sw), // @[tlb.scala:58:79] .io_x_sx (_ppn_data_WIRE_20_sx), // @[tlb.scala:58:79] .io_x_sr (_ppn_data_WIRE_20_sr), // @[tlb.scala:58:79] .io_x_pw (_ppn_data_WIRE_20_pw), // @[tlb.scala:58:79] .io_x_px (_ppn_data_WIRE_20_px), // @[tlb.scala:58:79] .io_x_pr (_ppn_data_WIRE_20_pr), // @[tlb.scala:58:79] .io_x_pal (_ppn_data_WIRE_20_pal), // @[tlb.scala:58:79] .io_x_paa (_ppn_data_WIRE_20_paa), // @[tlb.scala:58:79] .io_x_eff (_ppn_data_WIRE_20_eff), // @[tlb.scala:58:79] .io_x_c (_ppn_data_WIRE_20_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_ppn_data_WIRE_20_fragmented_superpage) // @[tlb.scala:58:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_12 ppn_data_barrier_11 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_22_ppn), // @[tlb.scala:58:79] .io_x_u (_ppn_data_WIRE_22_u), // @[tlb.scala:58:79] .io_x_g (_ppn_data_WIRE_22_g), // @[tlb.scala:58:79] .io_x_ae (_ppn_data_WIRE_22_ae), // @[tlb.scala:58:79] .io_x_sw (_ppn_data_WIRE_22_sw), // @[tlb.scala:58:79] .io_x_sx (_ppn_data_WIRE_22_sx), // @[tlb.scala:58:79] .io_x_sr (_ppn_data_WIRE_22_sr), // @[tlb.scala:58:79] .io_x_pw (_ppn_data_WIRE_22_pw), // @[tlb.scala:58:79] .io_x_px (_ppn_data_WIRE_22_px), // @[tlb.scala:58:79] .io_x_pr (_ppn_data_WIRE_22_pr), // @[tlb.scala:58:79] .io_x_pal (_ppn_data_WIRE_22_pal), // @[tlb.scala:58:79] .io_x_paa (_ppn_data_WIRE_22_paa), // @[tlb.scala:58:79] .io_x_eff (_ppn_data_WIRE_22_eff), // @[tlb.scala:58:79] .io_x_c (_ppn_data_WIRE_22_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_ppn_data_WIRE_22_fragmented_superpage) // @[tlb.scala:58:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_13 ppn_data_barrier_12 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_24_ppn), // @[tlb.scala:58:79] .io_x_u (_ppn_data_WIRE_24_u), // @[tlb.scala:58:79] .io_x_g (_ppn_data_WIRE_24_g), // @[tlb.scala:58:79] .io_x_ae (_ppn_data_WIRE_24_ae), // @[tlb.scala:58:79] .io_x_sw (_ppn_data_WIRE_24_sw), // @[tlb.scala:58:79] .io_x_sx (_ppn_data_WIRE_24_sx), // @[tlb.scala:58:79] .io_x_sr (_ppn_data_WIRE_24_sr), // @[tlb.scala:58:79] .io_x_pw (_ppn_data_WIRE_24_pw), // @[tlb.scala:58:79] .io_x_px (_ppn_data_WIRE_24_px), // @[tlb.scala:58:79] .io_x_pr (_ppn_data_WIRE_24_pr), // @[tlb.scala:58:79] .io_x_pal (_ppn_data_WIRE_24_pal), // @[tlb.scala:58:79] .io_x_paa (_ppn_data_WIRE_24_paa), // @[tlb.scala:58:79] .io_x_eff (_ppn_data_WIRE_24_eff), // @[tlb.scala:58:79] .io_x_c (_ppn_data_WIRE_24_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_ppn_data_WIRE_24_fragmented_superpage) // @[tlb.scala:58:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_14 entries_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_ppn), // @[tlb.scala:58:79] .io_x_u (_entries_WIRE_u), // @[tlb.scala:58:79] .io_x_g (_entries_WIRE_g), // @[tlb.scala:58:79] .io_x_ae (_entries_WIRE_ae), // @[tlb.scala:58:79] .io_x_sw (_entries_WIRE_sw), // @[tlb.scala:58:79] .io_x_sx (_entries_WIRE_sx), // @[tlb.scala:58:79] .io_x_sr (_entries_WIRE_sr), // @[tlb.scala:58:79] .io_x_pw (_entries_WIRE_pw), // @[tlb.scala:58:79] .io_x_px (_entries_WIRE_px), // @[tlb.scala:58:79] .io_x_pr (_entries_WIRE_pr), // @[tlb.scala:58:79] .io_x_pal (_entries_WIRE_pal), // @[tlb.scala:58:79] .io_x_paa (_entries_WIRE_paa), // @[tlb.scala:58:79] .io_x_eff (_entries_WIRE_eff), // @[tlb.scala:58:79] .io_x_c (_entries_WIRE_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_entries_WIRE_26_0_ppn), .io_y_u (_entries_WIRE_26_0_u), .io_y_g (_entries_WIRE_26_0_g), .io_y_ae (_entries_WIRE_26_0_ae), .io_y_sw (_entries_WIRE_26_0_sw), .io_y_sx (_entries_WIRE_26_0_sx), .io_y_sr (_entries_WIRE_26_0_sr), .io_y_pw (_entries_WIRE_26_0_pw), .io_y_px (_entries_WIRE_26_0_px), .io_y_pr (_entries_WIRE_26_0_pr), .io_y_pal (_entries_WIRE_26_0_pal), .io_y_paa (_entries_WIRE_26_0_paa), .io_y_eff (_entries_WIRE_26_0_eff), .io_y_c (_entries_WIRE_26_0_c), .io_y_fragmented_superpage (_entries_WIRE_26_0_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_15 entries_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_2_ppn), // @[tlb.scala:58:79] .io_x_u (_entries_WIRE_2_u), // @[tlb.scala:58:79] .io_x_g (_entries_WIRE_2_g), // @[tlb.scala:58:79] .io_x_ae (_entries_WIRE_2_ae), // @[tlb.scala:58:79] .io_x_sw (_entries_WIRE_2_sw), // @[tlb.scala:58:79] .io_x_sx (_entries_WIRE_2_sx), // @[tlb.scala:58:79] .io_x_sr (_entries_WIRE_2_sr), // @[tlb.scala:58:79] .io_x_pw (_entries_WIRE_2_pw), // @[tlb.scala:58:79] .io_x_px (_entries_WIRE_2_px), // @[tlb.scala:58:79] .io_x_pr (_entries_WIRE_2_pr), // @[tlb.scala:58:79] .io_x_pal (_entries_WIRE_2_pal), // @[tlb.scala:58:79] .io_x_paa (_entries_WIRE_2_paa), // @[tlb.scala:58:79] .io_x_eff (_entries_WIRE_2_eff), // @[tlb.scala:58:79] .io_x_c (_entries_WIRE_2_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_entries_WIRE_26_1_ppn), .io_y_u (_entries_WIRE_26_1_u), .io_y_g (_entries_WIRE_26_1_g), .io_y_ae (_entries_WIRE_26_1_ae), .io_y_sw (_entries_WIRE_26_1_sw), .io_y_sx (_entries_WIRE_26_1_sx), .io_y_sr (_entries_WIRE_26_1_sr), .io_y_pw (_entries_WIRE_26_1_pw), .io_y_px (_entries_WIRE_26_1_px), .io_y_pr (_entries_WIRE_26_1_pr), .io_y_pal (_entries_WIRE_26_1_pal), .io_y_paa (_entries_WIRE_26_1_paa), .io_y_eff (_entries_WIRE_26_1_eff), .io_y_c (_entries_WIRE_26_1_c), .io_y_fragmented_superpage (_entries_WIRE_26_1_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_16 entries_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_4_ppn), // @[tlb.scala:58:79] .io_x_u (_entries_WIRE_4_u), // @[tlb.scala:58:79] .io_x_g (_entries_WIRE_4_g), // @[tlb.scala:58:79] .io_x_ae (_entries_WIRE_4_ae), // @[tlb.scala:58:79] .io_x_sw (_entries_WIRE_4_sw), // @[tlb.scala:58:79] .io_x_sx (_entries_WIRE_4_sx), // @[tlb.scala:58:79] .io_x_sr (_entries_WIRE_4_sr), // @[tlb.scala:58:79] .io_x_pw (_entries_WIRE_4_pw), // @[tlb.scala:58:79] .io_x_px (_entries_WIRE_4_px), // @[tlb.scala:58:79] .io_x_pr (_entries_WIRE_4_pr), // @[tlb.scala:58:79] .io_x_pal (_entries_WIRE_4_pal), // @[tlb.scala:58:79] .io_x_paa (_entries_WIRE_4_paa), // @[tlb.scala:58:79] .io_x_eff (_entries_WIRE_4_eff), // @[tlb.scala:58:79] .io_x_c (_entries_WIRE_4_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_entries_WIRE_26_2_ppn), .io_y_u (_entries_WIRE_26_2_u), .io_y_g (_entries_WIRE_26_2_g), .io_y_ae (_entries_WIRE_26_2_ae), .io_y_sw (_entries_WIRE_26_2_sw), .io_y_sx (_entries_WIRE_26_2_sx), .io_y_sr (_entries_WIRE_26_2_sr), .io_y_pw (_entries_WIRE_26_2_pw), .io_y_px (_entries_WIRE_26_2_px), .io_y_pr (_entries_WIRE_26_2_pr), .io_y_pal (_entries_WIRE_26_2_pal), .io_y_paa (_entries_WIRE_26_2_paa), .io_y_eff (_entries_WIRE_26_2_eff), .io_y_c (_entries_WIRE_26_2_c), .io_y_fragmented_superpage (_entries_WIRE_26_2_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_17 entries_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_6_ppn), // @[tlb.scala:58:79] .io_x_u (_entries_WIRE_6_u), // @[tlb.scala:58:79] .io_x_g (_entries_WIRE_6_g), // @[tlb.scala:58:79] .io_x_ae (_entries_WIRE_6_ae), // @[tlb.scala:58:79] .io_x_sw (_entries_WIRE_6_sw), // @[tlb.scala:58:79] .io_x_sx (_entries_WIRE_6_sx), // @[tlb.scala:58:79] .io_x_sr (_entries_WIRE_6_sr), // @[tlb.scala:58:79] .io_x_pw (_entries_WIRE_6_pw), // @[tlb.scala:58:79] .io_x_px (_entries_WIRE_6_px), // @[tlb.scala:58:79] .io_x_pr (_entries_WIRE_6_pr), // @[tlb.scala:58:79] .io_x_pal (_entries_WIRE_6_pal), // @[tlb.scala:58:79] .io_x_paa (_entries_WIRE_6_paa), // @[tlb.scala:58:79] .io_x_eff (_entries_WIRE_6_eff), // @[tlb.scala:58:79] .io_x_c (_entries_WIRE_6_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_entries_WIRE_26_3_ppn), .io_y_u (_entries_WIRE_26_3_u), .io_y_g (_entries_WIRE_26_3_g), .io_y_ae (_entries_WIRE_26_3_ae), .io_y_sw (_entries_WIRE_26_3_sw), .io_y_sx (_entries_WIRE_26_3_sx), .io_y_sr (_entries_WIRE_26_3_sr), .io_y_pw (_entries_WIRE_26_3_pw), .io_y_px (_entries_WIRE_26_3_px), .io_y_pr (_entries_WIRE_26_3_pr), .io_y_pal (_entries_WIRE_26_3_pal), .io_y_paa (_entries_WIRE_26_3_paa), .io_y_eff (_entries_WIRE_26_3_eff), .io_y_c (_entries_WIRE_26_3_c), .io_y_fragmented_superpage (_entries_WIRE_26_3_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_18 entries_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_8_ppn), // @[tlb.scala:58:79] .io_x_u (_entries_WIRE_8_u), // @[tlb.scala:58:79] .io_x_g (_entries_WIRE_8_g), // @[tlb.scala:58:79] .io_x_ae (_entries_WIRE_8_ae), // @[tlb.scala:58:79] .io_x_sw (_entries_WIRE_8_sw), // @[tlb.scala:58:79] .io_x_sx (_entries_WIRE_8_sx), // @[tlb.scala:58:79] .io_x_sr (_entries_WIRE_8_sr), // @[tlb.scala:58:79] .io_x_pw (_entries_WIRE_8_pw), // @[tlb.scala:58:79] .io_x_px (_entries_WIRE_8_px), // @[tlb.scala:58:79] .io_x_pr (_entries_WIRE_8_pr), // @[tlb.scala:58:79] .io_x_pal (_entries_WIRE_8_pal), // @[tlb.scala:58:79] .io_x_paa (_entries_WIRE_8_paa), // @[tlb.scala:58:79] .io_x_eff (_entries_WIRE_8_eff), // @[tlb.scala:58:79] .io_x_c (_entries_WIRE_8_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_entries_WIRE_26_4_ppn), .io_y_u (_entries_WIRE_26_4_u), .io_y_g (_entries_WIRE_26_4_g), .io_y_ae (_entries_WIRE_26_4_ae), .io_y_sw (_entries_WIRE_26_4_sw), .io_y_sx (_entries_WIRE_26_4_sx), .io_y_sr (_entries_WIRE_26_4_sr), .io_y_pw (_entries_WIRE_26_4_pw), .io_y_px (_entries_WIRE_26_4_px), .io_y_pr (_entries_WIRE_26_4_pr), .io_y_pal (_entries_WIRE_26_4_pal), .io_y_paa (_entries_WIRE_26_4_paa), .io_y_eff (_entries_WIRE_26_4_eff), .io_y_c (_entries_WIRE_26_4_c), .io_y_fragmented_superpage (_entries_WIRE_26_4_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_19 entries_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_10_ppn), // @[tlb.scala:58:79] .io_x_u (_entries_WIRE_10_u), // @[tlb.scala:58:79] .io_x_g (_entries_WIRE_10_g), // @[tlb.scala:58:79] .io_x_ae (_entries_WIRE_10_ae), // @[tlb.scala:58:79] .io_x_sw (_entries_WIRE_10_sw), // @[tlb.scala:58:79] .io_x_sx (_entries_WIRE_10_sx), // @[tlb.scala:58:79] .io_x_sr (_entries_WIRE_10_sr), // @[tlb.scala:58:79] .io_x_pw (_entries_WIRE_10_pw), // @[tlb.scala:58:79] .io_x_px (_entries_WIRE_10_px), // @[tlb.scala:58:79] .io_x_pr (_entries_WIRE_10_pr), // @[tlb.scala:58:79] .io_x_pal (_entries_WIRE_10_pal), // @[tlb.scala:58:79] .io_x_paa (_entries_WIRE_10_paa), // @[tlb.scala:58:79] .io_x_eff (_entries_WIRE_10_eff), // @[tlb.scala:58:79] .io_x_c (_entries_WIRE_10_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_entries_WIRE_26_5_ppn), .io_y_u (_entries_WIRE_26_5_u), .io_y_g (_entries_WIRE_26_5_g), .io_y_ae (_entries_WIRE_26_5_ae), .io_y_sw (_entries_WIRE_26_5_sw), .io_y_sx (_entries_WIRE_26_5_sx), .io_y_sr (_entries_WIRE_26_5_sr), .io_y_pw (_entries_WIRE_26_5_pw), .io_y_px (_entries_WIRE_26_5_px), .io_y_pr (_entries_WIRE_26_5_pr), .io_y_pal (_entries_WIRE_26_5_pal), .io_y_paa (_entries_WIRE_26_5_paa), .io_y_eff (_entries_WIRE_26_5_eff), .io_y_c (_entries_WIRE_26_5_c), .io_y_fragmented_superpage (_entries_WIRE_26_5_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_20 entries_barrier_6 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_12_ppn), // @[tlb.scala:58:79] .io_x_u (_entries_WIRE_12_u), // @[tlb.scala:58:79] .io_x_g (_entries_WIRE_12_g), // @[tlb.scala:58:79] .io_x_ae (_entries_WIRE_12_ae), // @[tlb.scala:58:79] .io_x_sw (_entries_WIRE_12_sw), // @[tlb.scala:58:79] .io_x_sx (_entries_WIRE_12_sx), // @[tlb.scala:58:79] .io_x_sr (_entries_WIRE_12_sr), // @[tlb.scala:58:79] .io_x_pw (_entries_WIRE_12_pw), // @[tlb.scala:58:79] .io_x_px (_entries_WIRE_12_px), // @[tlb.scala:58:79] .io_x_pr (_entries_WIRE_12_pr), // @[tlb.scala:58:79] .io_x_pal (_entries_WIRE_12_pal), // @[tlb.scala:58:79] .io_x_paa (_entries_WIRE_12_paa), // @[tlb.scala:58:79] .io_x_eff (_entries_WIRE_12_eff), // @[tlb.scala:58:79] .io_x_c (_entries_WIRE_12_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_entries_WIRE_12_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_entries_WIRE_26_6_ppn), .io_y_u (_entries_WIRE_26_6_u), .io_y_g (_entries_WIRE_26_6_g), .io_y_ae (_entries_WIRE_26_6_ae), .io_y_sw (_entries_WIRE_26_6_sw), .io_y_sx (_entries_WIRE_26_6_sx), .io_y_sr (_entries_WIRE_26_6_sr), .io_y_pw (_entries_WIRE_26_6_pw), .io_y_px (_entries_WIRE_26_6_px), .io_y_pr (_entries_WIRE_26_6_pr), .io_y_pal (_entries_WIRE_26_6_pal), .io_y_paa (_entries_WIRE_26_6_paa), .io_y_eff (_entries_WIRE_26_6_eff), .io_y_c (_entries_WIRE_26_6_c), .io_y_fragmented_superpage (_entries_WIRE_26_6_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_21 entries_barrier_7 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_14_ppn), // @[tlb.scala:58:79] .io_x_u (_entries_WIRE_14_u), // @[tlb.scala:58:79] .io_x_g (_entries_WIRE_14_g), // @[tlb.scala:58:79] .io_x_ae (_entries_WIRE_14_ae), // @[tlb.scala:58:79] .io_x_sw (_entries_WIRE_14_sw), // @[tlb.scala:58:79] .io_x_sx (_entries_WIRE_14_sx), // @[tlb.scala:58:79] .io_x_sr (_entries_WIRE_14_sr), // @[tlb.scala:58:79] .io_x_pw (_entries_WIRE_14_pw), // @[tlb.scala:58:79] .io_x_px (_entries_WIRE_14_px), // @[tlb.scala:58:79] .io_x_pr (_entries_WIRE_14_pr), // @[tlb.scala:58:79] .io_x_pal (_entries_WIRE_14_pal), // @[tlb.scala:58:79] .io_x_paa (_entries_WIRE_14_paa), // @[tlb.scala:58:79] .io_x_eff (_entries_WIRE_14_eff), // @[tlb.scala:58:79] .io_x_c (_entries_WIRE_14_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_entries_WIRE_14_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_entries_WIRE_26_7_ppn), .io_y_u (_entries_WIRE_26_7_u), .io_y_g (_entries_WIRE_26_7_g), .io_y_ae (_entries_WIRE_26_7_ae), .io_y_sw (_entries_WIRE_26_7_sw), .io_y_sx (_entries_WIRE_26_7_sx), .io_y_sr (_entries_WIRE_26_7_sr), .io_y_pw (_entries_WIRE_26_7_pw), .io_y_px (_entries_WIRE_26_7_px), .io_y_pr (_entries_WIRE_26_7_pr), .io_y_pal (_entries_WIRE_26_7_pal), .io_y_paa (_entries_WIRE_26_7_paa), .io_y_eff (_entries_WIRE_26_7_eff), .io_y_c (_entries_WIRE_26_7_c), .io_y_fragmented_superpage (_entries_WIRE_26_7_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_22 entries_barrier_8 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_16_ppn), // @[tlb.scala:58:79] .io_x_u (_entries_WIRE_16_u), // @[tlb.scala:58:79] .io_x_g (_entries_WIRE_16_g), // @[tlb.scala:58:79] .io_x_ae (_entries_WIRE_16_ae), // @[tlb.scala:58:79] .io_x_sw (_entries_WIRE_16_sw), // @[tlb.scala:58:79] .io_x_sx (_entries_WIRE_16_sx), // @[tlb.scala:58:79] .io_x_sr (_entries_WIRE_16_sr), // @[tlb.scala:58:79] .io_x_pw (_entries_WIRE_16_pw), // @[tlb.scala:58:79] .io_x_px (_entries_WIRE_16_px), // @[tlb.scala:58:79] .io_x_pr (_entries_WIRE_16_pr), // @[tlb.scala:58:79] .io_x_pal (_entries_WIRE_16_pal), // @[tlb.scala:58:79] .io_x_paa (_entries_WIRE_16_paa), // @[tlb.scala:58:79] .io_x_eff (_entries_WIRE_16_eff), // @[tlb.scala:58:79] .io_x_c (_entries_WIRE_16_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_entries_WIRE_16_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_entries_WIRE_26_8_ppn), .io_y_u (_entries_WIRE_26_8_u), .io_y_g (_entries_WIRE_26_8_g), .io_y_ae (_entries_WIRE_26_8_ae), .io_y_sw (_entries_WIRE_26_8_sw), .io_y_sx (_entries_WIRE_26_8_sx), .io_y_sr (_entries_WIRE_26_8_sr), .io_y_pw (_entries_WIRE_26_8_pw), .io_y_px (_entries_WIRE_26_8_px), .io_y_pr (_entries_WIRE_26_8_pr), .io_y_pal (_entries_WIRE_26_8_pal), .io_y_paa (_entries_WIRE_26_8_paa), .io_y_eff (_entries_WIRE_26_8_eff), .io_y_c (_entries_WIRE_26_8_c), .io_y_fragmented_superpage (_entries_WIRE_26_8_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_23 entries_barrier_9 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_18_ppn), // @[tlb.scala:58:79] .io_x_u (_entries_WIRE_18_u), // @[tlb.scala:58:79] .io_x_g (_entries_WIRE_18_g), // @[tlb.scala:58:79] .io_x_ae (_entries_WIRE_18_ae), // @[tlb.scala:58:79] .io_x_sw (_entries_WIRE_18_sw), // @[tlb.scala:58:79] .io_x_sx (_entries_WIRE_18_sx), // @[tlb.scala:58:79] .io_x_sr (_entries_WIRE_18_sr), // @[tlb.scala:58:79] .io_x_pw (_entries_WIRE_18_pw), // @[tlb.scala:58:79] .io_x_px (_entries_WIRE_18_px), // @[tlb.scala:58:79] .io_x_pr (_entries_WIRE_18_pr), // @[tlb.scala:58:79] .io_x_pal (_entries_WIRE_18_pal), // @[tlb.scala:58:79] .io_x_paa (_entries_WIRE_18_paa), // @[tlb.scala:58:79] .io_x_eff (_entries_WIRE_18_eff), // @[tlb.scala:58:79] .io_x_c (_entries_WIRE_18_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_entries_WIRE_18_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_entries_WIRE_26_9_ppn), .io_y_u (_entries_WIRE_26_9_u), .io_y_g (_entries_WIRE_26_9_g), .io_y_ae (_entries_WIRE_26_9_ae), .io_y_sw (_entries_WIRE_26_9_sw), .io_y_sx (_entries_WIRE_26_9_sx), .io_y_sr (_entries_WIRE_26_9_sr), .io_y_pw (_entries_WIRE_26_9_pw), .io_y_px (_entries_WIRE_26_9_px), .io_y_pr (_entries_WIRE_26_9_pr), .io_y_pal (_entries_WIRE_26_9_pal), .io_y_paa (_entries_WIRE_26_9_paa), .io_y_eff (_entries_WIRE_26_9_eff), .io_y_c (_entries_WIRE_26_9_c), .io_y_fragmented_superpage (_entries_WIRE_26_9_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_24 entries_barrier_10 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_20_ppn), // @[tlb.scala:58:79] .io_x_u (_entries_WIRE_20_u), // @[tlb.scala:58:79] .io_x_g (_entries_WIRE_20_g), // @[tlb.scala:58:79] .io_x_ae (_entries_WIRE_20_ae), // @[tlb.scala:58:79] .io_x_sw (_entries_WIRE_20_sw), // @[tlb.scala:58:79] .io_x_sx (_entries_WIRE_20_sx), // @[tlb.scala:58:79] .io_x_sr (_entries_WIRE_20_sr), // @[tlb.scala:58:79] .io_x_pw (_entries_WIRE_20_pw), // @[tlb.scala:58:79] .io_x_px (_entries_WIRE_20_px), // @[tlb.scala:58:79] .io_x_pr (_entries_WIRE_20_pr), // @[tlb.scala:58:79] .io_x_pal (_entries_WIRE_20_pal), // @[tlb.scala:58:79] .io_x_paa (_entries_WIRE_20_paa), // @[tlb.scala:58:79] .io_x_eff (_entries_WIRE_20_eff), // @[tlb.scala:58:79] .io_x_c (_entries_WIRE_20_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_entries_WIRE_20_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_entries_WIRE_26_10_ppn), .io_y_u (_entries_WIRE_26_10_u), .io_y_g (_entries_WIRE_26_10_g), .io_y_ae (_entries_WIRE_26_10_ae), .io_y_sw (_entries_WIRE_26_10_sw), .io_y_sx (_entries_WIRE_26_10_sx), .io_y_sr (_entries_WIRE_26_10_sr), .io_y_pw (_entries_WIRE_26_10_pw), .io_y_px (_entries_WIRE_26_10_px), .io_y_pr (_entries_WIRE_26_10_pr), .io_y_pal (_entries_WIRE_26_10_pal), .io_y_paa (_entries_WIRE_26_10_paa), .io_y_eff (_entries_WIRE_26_10_eff), .io_y_c (_entries_WIRE_26_10_c), .io_y_fragmented_superpage (_entries_WIRE_26_10_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_25 entries_barrier_11 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_22_ppn), // @[tlb.scala:58:79] .io_x_u (_entries_WIRE_22_u), // @[tlb.scala:58:79] .io_x_g (_entries_WIRE_22_g), // @[tlb.scala:58:79] .io_x_ae (_entries_WIRE_22_ae), // @[tlb.scala:58:79] .io_x_sw (_entries_WIRE_22_sw), // @[tlb.scala:58:79] .io_x_sx (_entries_WIRE_22_sx), // @[tlb.scala:58:79] .io_x_sr (_entries_WIRE_22_sr), // @[tlb.scala:58:79] .io_x_pw (_entries_WIRE_22_pw), // @[tlb.scala:58:79] .io_x_px (_entries_WIRE_22_px), // @[tlb.scala:58:79] .io_x_pr (_entries_WIRE_22_pr), // @[tlb.scala:58:79] .io_x_pal (_entries_WIRE_22_pal), // @[tlb.scala:58:79] .io_x_paa (_entries_WIRE_22_paa), // @[tlb.scala:58:79] .io_x_eff (_entries_WIRE_22_eff), // @[tlb.scala:58:79] .io_x_c (_entries_WIRE_22_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_entries_WIRE_22_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_entries_WIRE_26_11_ppn), .io_y_u (_entries_WIRE_26_11_u), .io_y_g (_entries_WIRE_26_11_g), .io_y_ae (_entries_WIRE_26_11_ae), .io_y_sw (_entries_WIRE_26_11_sw), .io_y_sx (_entries_WIRE_26_11_sx), .io_y_sr (_entries_WIRE_26_11_sr), .io_y_pw (_entries_WIRE_26_11_pw), .io_y_px (_entries_WIRE_26_11_px), .io_y_pr (_entries_WIRE_26_11_pr), .io_y_pal (_entries_WIRE_26_11_pal), .io_y_paa (_entries_WIRE_26_11_paa), .io_y_eff (_entries_WIRE_26_11_eff), .io_y_c (_entries_WIRE_26_11_c), .io_y_fragmented_superpage (_entries_WIRE_26_11_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_26 entries_barrier_12 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_24_ppn), // @[tlb.scala:58:79] .io_x_u (_entries_WIRE_24_u), // @[tlb.scala:58:79] .io_x_g (_entries_WIRE_24_g), // @[tlb.scala:58:79] .io_x_ae (_entries_WIRE_24_ae), // @[tlb.scala:58:79] .io_x_sw (_entries_WIRE_24_sw), // @[tlb.scala:58:79] .io_x_sx (_entries_WIRE_24_sx), // @[tlb.scala:58:79] .io_x_sr (_entries_WIRE_24_sr), // @[tlb.scala:58:79] .io_x_pw (_entries_WIRE_24_pw), // @[tlb.scala:58:79] .io_x_px (_entries_WIRE_24_px), // @[tlb.scala:58:79] .io_x_pr (_entries_WIRE_24_pr), // @[tlb.scala:58:79] .io_x_pal (_entries_WIRE_24_pal), // @[tlb.scala:58:79] .io_x_paa (_entries_WIRE_24_paa), // @[tlb.scala:58:79] .io_x_eff (_entries_WIRE_24_eff), // @[tlb.scala:58:79] .io_x_c (_entries_WIRE_24_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_entries_WIRE_24_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_entries_WIRE_26_12_ppn), .io_y_u (_entries_WIRE_26_12_u), .io_y_g (_entries_WIRE_26_12_g), .io_y_ae (_entries_WIRE_26_12_ae), .io_y_sw (_entries_WIRE_26_12_sw), .io_y_sx (_entries_WIRE_26_12_sx), .io_y_sr (_entries_WIRE_26_12_sr), .io_y_pw (_entries_WIRE_26_12_pw), .io_y_px (_entries_WIRE_26_12_px), .io_y_pr (_entries_WIRE_26_12_pr), .io_y_pal (_entries_WIRE_26_12_pal), .io_y_paa (_entries_WIRE_26_12_paa), .io_y_eff (_entries_WIRE_26_12_eff), .io_y_c (_entries_WIRE_26_12_c), .io_y_fragmented_superpage (_entries_WIRE_26_12_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_27 normal_entries_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_ppn), // @[tlb.scala:58:79] .io_x_u (_normal_entries_WIRE_u), // @[tlb.scala:58:79] .io_x_g (_normal_entries_WIRE_g), // @[tlb.scala:58:79] .io_x_ae (_normal_entries_WIRE_ae), // @[tlb.scala:58:79] .io_x_sw (_normal_entries_WIRE_sw), // @[tlb.scala:58:79] .io_x_sx (_normal_entries_WIRE_sx), // @[tlb.scala:58:79] .io_x_sr (_normal_entries_WIRE_sr), // @[tlb.scala:58:79] .io_x_pw (_normal_entries_WIRE_pw), // @[tlb.scala:58:79] .io_x_px (_normal_entries_WIRE_px), // @[tlb.scala:58:79] .io_x_pr (_normal_entries_WIRE_pr), // @[tlb.scala:58:79] .io_x_pal (_normal_entries_WIRE_pal), // @[tlb.scala:58:79] .io_x_paa (_normal_entries_WIRE_paa), // @[tlb.scala:58:79] .io_x_eff (_normal_entries_WIRE_eff), // @[tlb.scala:58:79] .io_x_c (_normal_entries_WIRE_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_normal_entries_WIRE_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_normal_entries_WIRE_24_0_ppn), .io_y_u (_normal_entries_WIRE_24_0_u), .io_y_g (_normal_entries_WIRE_24_0_g), .io_y_ae (_normal_entries_WIRE_24_0_ae), .io_y_sw (_normal_entries_WIRE_24_0_sw), .io_y_sx (_normal_entries_WIRE_24_0_sx), .io_y_sr (_normal_entries_WIRE_24_0_sr), .io_y_pw (_normal_entries_WIRE_24_0_pw), .io_y_px (_normal_entries_WIRE_24_0_px), .io_y_pr (_normal_entries_WIRE_24_0_pr), .io_y_pal (_normal_entries_WIRE_24_0_pal), .io_y_paa (_normal_entries_WIRE_24_0_paa), .io_y_eff (_normal_entries_WIRE_24_0_eff), .io_y_c (_normal_entries_WIRE_24_0_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_0_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_28 normal_entries_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_2_ppn), // @[tlb.scala:58:79] .io_x_u (_normal_entries_WIRE_2_u), // @[tlb.scala:58:79] .io_x_g (_normal_entries_WIRE_2_g), // @[tlb.scala:58:79] .io_x_ae (_normal_entries_WIRE_2_ae), // @[tlb.scala:58:79] .io_x_sw (_normal_entries_WIRE_2_sw), // @[tlb.scala:58:79] .io_x_sx (_normal_entries_WIRE_2_sx), // @[tlb.scala:58:79] .io_x_sr (_normal_entries_WIRE_2_sr), // @[tlb.scala:58:79] .io_x_pw (_normal_entries_WIRE_2_pw), // @[tlb.scala:58:79] .io_x_px (_normal_entries_WIRE_2_px), // @[tlb.scala:58:79] .io_x_pr (_normal_entries_WIRE_2_pr), // @[tlb.scala:58:79] .io_x_pal (_normal_entries_WIRE_2_pal), // @[tlb.scala:58:79] .io_x_paa (_normal_entries_WIRE_2_paa), // @[tlb.scala:58:79] .io_x_eff (_normal_entries_WIRE_2_eff), // @[tlb.scala:58:79] .io_x_c (_normal_entries_WIRE_2_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_normal_entries_WIRE_2_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_normal_entries_WIRE_24_1_ppn), .io_y_u (_normal_entries_WIRE_24_1_u), .io_y_g (_normal_entries_WIRE_24_1_g), .io_y_ae (_normal_entries_WIRE_24_1_ae), .io_y_sw (_normal_entries_WIRE_24_1_sw), .io_y_sx (_normal_entries_WIRE_24_1_sx), .io_y_sr (_normal_entries_WIRE_24_1_sr), .io_y_pw (_normal_entries_WIRE_24_1_pw), .io_y_px (_normal_entries_WIRE_24_1_px), .io_y_pr (_normal_entries_WIRE_24_1_pr), .io_y_pal (_normal_entries_WIRE_24_1_pal), .io_y_paa (_normal_entries_WIRE_24_1_paa), .io_y_eff (_normal_entries_WIRE_24_1_eff), .io_y_c (_normal_entries_WIRE_24_1_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_1_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_29 normal_entries_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_4_ppn), // @[tlb.scala:58:79] .io_x_u (_normal_entries_WIRE_4_u), // @[tlb.scala:58:79] .io_x_g (_normal_entries_WIRE_4_g), // @[tlb.scala:58:79] .io_x_ae (_normal_entries_WIRE_4_ae), // @[tlb.scala:58:79] .io_x_sw (_normal_entries_WIRE_4_sw), // @[tlb.scala:58:79] .io_x_sx (_normal_entries_WIRE_4_sx), // @[tlb.scala:58:79] .io_x_sr (_normal_entries_WIRE_4_sr), // @[tlb.scala:58:79] .io_x_pw (_normal_entries_WIRE_4_pw), // @[tlb.scala:58:79] .io_x_px (_normal_entries_WIRE_4_px), // @[tlb.scala:58:79] .io_x_pr (_normal_entries_WIRE_4_pr), // @[tlb.scala:58:79] .io_x_pal (_normal_entries_WIRE_4_pal), // @[tlb.scala:58:79] .io_x_paa (_normal_entries_WIRE_4_paa), // @[tlb.scala:58:79] .io_x_eff (_normal_entries_WIRE_4_eff), // @[tlb.scala:58:79] .io_x_c (_normal_entries_WIRE_4_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_normal_entries_WIRE_4_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_normal_entries_WIRE_24_2_ppn), .io_y_u (_normal_entries_WIRE_24_2_u), .io_y_g (_normal_entries_WIRE_24_2_g), .io_y_ae (_normal_entries_WIRE_24_2_ae), .io_y_sw (_normal_entries_WIRE_24_2_sw), .io_y_sx (_normal_entries_WIRE_24_2_sx), .io_y_sr (_normal_entries_WIRE_24_2_sr), .io_y_pw (_normal_entries_WIRE_24_2_pw), .io_y_px (_normal_entries_WIRE_24_2_px), .io_y_pr (_normal_entries_WIRE_24_2_pr), .io_y_pal (_normal_entries_WIRE_24_2_pal), .io_y_paa (_normal_entries_WIRE_24_2_paa), .io_y_eff (_normal_entries_WIRE_24_2_eff), .io_y_c (_normal_entries_WIRE_24_2_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_2_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_30 normal_entries_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_6_ppn), // @[tlb.scala:58:79] .io_x_u (_normal_entries_WIRE_6_u), // @[tlb.scala:58:79] .io_x_g (_normal_entries_WIRE_6_g), // @[tlb.scala:58:79] .io_x_ae (_normal_entries_WIRE_6_ae), // @[tlb.scala:58:79] .io_x_sw (_normal_entries_WIRE_6_sw), // @[tlb.scala:58:79] .io_x_sx (_normal_entries_WIRE_6_sx), // @[tlb.scala:58:79] .io_x_sr (_normal_entries_WIRE_6_sr), // @[tlb.scala:58:79] .io_x_pw (_normal_entries_WIRE_6_pw), // @[tlb.scala:58:79] .io_x_px (_normal_entries_WIRE_6_px), // @[tlb.scala:58:79] .io_x_pr (_normal_entries_WIRE_6_pr), // @[tlb.scala:58:79] .io_x_pal (_normal_entries_WIRE_6_pal), // @[tlb.scala:58:79] .io_x_paa (_normal_entries_WIRE_6_paa), // @[tlb.scala:58:79] .io_x_eff (_normal_entries_WIRE_6_eff), // @[tlb.scala:58:79] .io_x_c (_normal_entries_WIRE_6_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_normal_entries_WIRE_6_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_normal_entries_WIRE_24_3_ppn), .io_y_u (_normal_entries_WIRE_24_3_u), .io_y_g (_normal_entries_WIRE_24_3_g), .io_y_ae (_normal_entries_WIRE_24_3_ae), .io_y_sw (_normal_entries_WIRE_24_3_sw), .io_y_sx (_normal_entries_WIRE_24_3_sx), .io_y_sr (_normal_entries_WIRE_24_3_sr), .io_y_pw (_normal_entries_WIRE_24_3_pw), .io_y_px (_normal_entries_WIRE_24_3_px), .io_y_pr (_normal_entries_WIRE_24_3_pr), .io_y_pal (_normal_entries_WIRE_24_3_pal), .io_y_paa (_normal_entries_WIRE_24_3_paa), .io_y_eff (_normal_entries_WIRE_24_3_eff), .io_y_c (_normal_entries_WIRE_24_3_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_3_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_31 normal_entries_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_8_ppn), // @[tlb.scala:58:79] .io_x_u (_normal_entries_WIRE_8_u), // @[tlb.scala:58:79] .io_x_g (_normal_entries_WIRE_8_g), // @[tlb.scala:58:79] .io_x_ae (_normal_entries_WIRE_8_ae), // @[tlb.scala:58:79] .io_x_sw (_normal_entries_WIRE_8_sw), // @[tlb.scala:58:79] .io_x_sx (_normal_entries_WIRE_8_sx), // @[tlb.scala:58:79] .io_x_sr (_normal_entries_WIRE_8_sr), // @[tlb.scala:58:79] .io_x_pw (_normal_entries_WIRE_8_pw), // @[tlb.scala:58:79] .io_x_px (_normal_entries_WIRE_8_px), // @[tlb.scala:58:79] .io_x_pr (_normal_entries_WIRE_8_pr), // @[tlb.scala:58:79] .io_x_pal (_normal_entries_WIRE_8_pal), // @[tlb.scala:58:79] .io_x_paa (_normal_entries_WIRE_8_paa), // @[tlb.scala:58:79] .io_x_eff (_normal_entries_WIRE_8_eff), // @[tlb.scala:58:79] .io_x_c (_normal_entries_WIRE_8_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_normal_entries_WIRE_8_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_normal_entries_WIRE_24_4_ppn), .io_y_u (_normal_entries_WIRE_24_4_u), .io_y_g (_normal_entries_WIRE_24_4_g), .io_y_ae (_normal_entries_WIRE_24_4_ae), .io_y_sw (_normal_entries_WIRE_24_4_sw), .io_y_sx (_normal_entries_WIRE_24_4_sx), .io_y_sr (_normal_entries_WIRE_24_4_sr), .io_y_pw (_normal_entries_WIRE_24_4_pw), .io_y_px (_normal_entries_WIRE_24_4_px), .io_y_pr (_normal_entries_WIRE_24_4_pr), .io_y_pal (_normal_entries_WIRE_24_4_pal), .io_y_paa (_normal_entries_WIRE_24_4_paa), .io_y_eff (_normal_entries_WIRE_24_4_eff), .io_y_c (_normal_entries_WIRE_24_4_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_4_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_32 normal_entries_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_10_ppn), // @[tlb.scala:58:79] .io_x_u (_normal_entries_WIRE_10_u), // @[tlb.scala:58:79] .io_x_g (_normal_entries_WIRE_10_g), // @[tlb.scala:58:79] .io_x_ae (_normal_entries_WIRE_10_ae), // @[tlb.scala:58:79] .io_x_sw (_normal_entries_WIRE_10_sw), // @[tlb.scala:58:79] .io_x_sx (_normal_entries_WIRE_10_sx), // @[tlb.scala:58:79] .io_x_sr (_normal_entries_WIRE_10_sr), // @[tlb.scala:58:79] .io_x_pw (_normal_entries_WIRE_10_pw), // @[tlb.scala:58:79] .io_x_px (_normal_entries_WIRE_10_px), // @[tlb.scala:58:79] .io_x_pr (_normal_entries_WIRE_10_pr), // @[tlb.scala:58:79] .io_x_pal (_normal_entries_WIRE_10_pal), // @[tlb.scala:58:79] .io_x_paa (_normal_entries_WIRE_10_paa), // @[tlb.scala:58:79] .io_x_eff (_normal_entries_WIRE_10_eff), // @[tlb.scala:58:79] .io_x_c (_normal_entries_WIRE_10_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_normal_entries_WIRE_10_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_normal_entries_WIRE_24_5_ppn), .io_y_u (_normal_entries_WIRE_24_5_u), .io_y_g (_normal_entries_WIRE_24_5_g), .io_y_ae (_normal_entries_WIRE_24_5_ae), .io_y_sw (_normal_entries_WIRE_24_5_sw), .io_y_sx (_normal_entries_WIRE_24_5_sx), .io_y_sr (_normal_entries_WIRE_24_5_sr), .io_y_pw (_normal_entries_WIRE_24_5_pw), .io_y_px (_normal_entries_WIRE_24_5_px), .io_y_pr (_normal_entries_WIRE_24_5_pr), .io_y_pal (_normal_entries_WIRE_24_5_pal), .io_y_paa (_normal_entries_WIRE_24_5_paa), .io_y_eff (_normal_entries_WIRE_24_5_eff), .io_y_c (_normal_entries_WIRE_24_5_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_5_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_33 normal_entries_barrier_6 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_12_ppn), // @[tlb.scala:58:79] .io_x_u (_normal_entries_WIRE_12_u), // @[tlb.scala:58:79] .io_x_g (_normal_entries_WIRE_12_g), // @[tlb.scala:58:79] .io_x_ae (_normal_entries_WIRE_12_ae), // @[tlb.scala:58:79] .io_x_sw (_normal_entries_WIRE_12_sw), // @[tlb.scala:58:79] .io_x_sx (_normal_entries_WIRE_12_sx), // @[tlb.scala:58:79] .io_x_sr (_normal_entries_WIRE_12_sr), // @[tlb.scala:58:79] .io_x_pw (_normal_entries_WIRE_12_pw), // @[tlb.scala:58:79] .io_x_px (_normal_entries_WIRE_12_px), // @[tlb.scala:58:79] .io_x_pr (_normal_entries_WIRE_12_pr), // @[tlb.scala:58:79] .io_x_pal (_normal_entries_WIRE_12_pal), // @[tlb.scala:58:79] .io_x_paa (_normal_entries_WIRE_12_paa), // @[tlb.scala:58:79] .io_x_eff (_normal_entries_WIRE_12_eff), // @[tlb.scala:58:79] .io_x_c (_normal_entries_WIRE_12_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_normal_entries_WIRE_12_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_normal_entries_WIRE_24_6_ppn), .io_y_u (_normal_entries_WIRE_24_6_u), .io_y_g (_normal_entries_WIRE_24_6_g), .io_y_ae (_normal_entries_WIRE_24_6_ae), .io_y_sw (_normal_entries_WIRE_24_6_sw), .io_y_sx (_normal_entries_WIRE_24_6_sx), .io_y_sr (_normal_entries_WIRE_24_6_sr), .io_y_pw (_normal_entries_WIRE_24_6_pw), .io_y_px (_normal_entries_WIRE_24_6_px), .io_y_pr (_normal_entries_WIRE_24_6_pr), .io_y_pal (_normal_entries_WIRE_24_6_pal), .io_y_paa (_normal_entries_WIRE_24_6_paa), .io_y_eff (_normal_entries_WIRE_24_6_eff), .io_y_c (_normal_entries_WIRE_24_6_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_6_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_34 normal_entries_barrier_7 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_14_ppn), // @[tlb.scala:58:79] .io_x_u (_normal_entries_WIRE_14_u), // @[tlb.scala:58:79] .io_x_g (_normal_entries_WIRE_14_g), // @[tlb.scala:58:79] .io_x_ae (_normal_entries_WIRE_14_ae), // @[tlb.scala:58:79] .io_x_sw (_normal_entries_WIRE_14_sw), // @[tlb.scala:58:79] .io_x_sx (_normal_entries_WIRE_14_sx), // @[tlb.scala:58:79] .io_x_sr (_normal_entries_WIRE_14_sr), // @[tlb.scala:58:79] .io_x_pw (_normal_entries_WIRE_14_pw), // @[tlb.scala:58:79] .io_x_px (_normal_entries_WIRE_14_px), // @[tlb.scala:58:79] .io_x_pr (_normal_entries_WIRE_14_pr), // @[tlb.scala:58:79] .io_x_pal (_normal_entries_WIRE_14_pal), // @[tlb.scala:58:79] .io_x_paa (_normal_entries_WIRE_14_paa), // @[tlb.scala:58:79] .io_x_eff (_normal_entries_WIRE_14_eff), // @[tlb.scala:58:79] .io_x_c (_normal_entries_WIRE_14_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_normal_entries_WIRE_14_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_normal_entries_WIRE_24_7_ppn), .io_y_u (_normal_entries_WIRE_24_7_u), .io_y_g (_normal_entries_WIRE_24_7_g), .io_y_ae (_normal_entries_WIRE_24_7_ae), .io_y_sw (_normal_entries_WIRE_24_7_sw), .io_y_sx (_normal_entries_WIRE_24_7_sx), .io_y_sr (_normal_entries_WIRE_24_7_sr), .io_y_pw (_normal_entries_WIRE_24_7_pw), .io_y_px (_normal_entries_WIRE_24_7_px), .io_y_pr (_normal_entries_WIRE_24_7_pr), .io_y_pal (_normal_entries_WIRE_24_7_pal), .io_y_paa (_normal_entries_WIRE_24_7_paa), .io_y_eff (_normal_entries_WIRE_24_7_eff), .io_y_c (_normal_entries_WIRE_24_7_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_7_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_35 normal_entries_barrier_8 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_16_ppn), // @[tlb.scala:58:79] .io_x_u (_normal_entries_WIRE_16_u), // @[tlb.scala:58:79] .io_x_g (_normal_entries_WIRE_16_g), // @[tlb.scala:58:79] .io_x_ae (_normal_entries_WIRE_16_ae), // @[tlb.scala:58:79] .io_x_sw (_normal_entries_WIRE_16_sw), // @[tlb.scala:58:79] .io_x_sx (_normal_entries_WIRE_16_sx), // @[tlb.scala:58:79] .io_x_sr (_normal_entries_WIRE_16_sr), // @[tlb.scala:58:79] .io_x_pw (_normal_entries_WIRE_16_pw), // @[tlb.scala:58:79] .io_x_px (_normal_entries_WIRE_16_px), // @[tlb.scala:58:79] .io_x_pr (_normal_entries_WIRE_16_pr), // @[tlb.scala:58:79] .io_x_pal (_normal_entries_WIRE_16_pal), // @[tlb.scala:58:79] .io_x_paa (_normal_entries_WIRE_16_paa), // @[tlb.scala:58:79] .io_x_eff (_normal_entries_WIRE_16_eff), // @[tlb.scala:58:79] .io_x_c (_normal_entries_WIRE_16_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_normal_entries_WIRE_16_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_normal_entries_WIRE_24_8_ppn), .io_y_u (_normal_entries_WIRE_24_8_u), .io_y_g (_normal_entries_WIRE_24_8_g), .io_y_ae (_normal_entries_WIRE_24_8_ae), .io_y_sw (_normal_entries_WIRE_24_8_sw), .io_y_sx (_normal_entries_WIRE_24_8_sx), .io_y_sr (_normal_entries_WIRE_24_8_sr), .io_y_pw (_normal_entries_WIRE_24_8_pw), .io_y_px (_normal_entries_WIRE_24_8_px), .io_y_pr (_normal_entries_WIRE_24_8_pr), .io_y_pal (_normal_entries_WIRE_24_8_pal), .io_y_paa (_normal_entries_WIRE_24_8_paa), .io_y_eff (_normal_entries_WIRE_24_8_eff), .io_y_c (_normal_entries_WIRE_24_8_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_8_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_36 normal_entries_barrier_9 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_18_ppn), // @[tlb.scala:58:79] .io_x_u (_normal_entries_WIRE_18_u), // @[tlb.scala:58:79] .io_x_g (_normal_entries_WIRE_18_g), // @[tlb.scala:58:79] .io_x_ae (_normal_entries_WIRE_18_ae), // @[tlb.scala:58:79] .io_x_sw (_normal_entries_WIRE_18_sw), // @[tlb.scala:58:79] .io_x_sx (_normal_entries_WIRE_18_sx), // @[tlb.scala:58:79] .io_x_sr (_normal_entries_WIRE_18_sr), // @[tlb.scala:58:79] .io_x_pw (_normal_entries_WIRE_18_pw), // @[tlb.scala:58:79] .io_x_px (_normal_entries_WIRE_18_px), // @[tlb.scala:58:79] .io_x_pr (_normal_entries_WIRE_18_pr), // @[tlb.scala:58:79] .io_x_pal (_normal_entries_WIRE_18_pal), // @[tlb.scala:58:79] .io_x_paa (_normal_entries_WIRE_18_paa), // @[tlb.scala:58:79] .io_x_eff (_normal_entries_WIRE_18_eff), // @[tlb.scala:58:79] .io_x_c (_normal_entries_WIRE_18_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_normal_entries_WIRE_18_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_normal_entries_WIRE_24_9_ppn), .io_y_u (_normal_entries_WIRE_24_9_u), .io_y_g (_normal_entries_WIRE_24_9_g), .io_y_ae (_normal_entries_WIRE_24_9_ae), .io_y_sw (_normal_entries_WIRE_24_9_sw), .io_y_sx (_normal_entries_WIRE_24_9_sx), .io_y_sr (_normal_entries_WIRE_24_9_sr), .io_y_pw (_normal_entries_WIRE_24_9_pw), .io_y_px (_normal_entries_WIRE_24_9_px), .io_y_pr (_normal_entries_WIRE_24_9_pr), .io_y_pal (_normal_entries_WIRE_24_9_pal), .io_y_paa (_normal_entries_WIRE_24_9_paa), .io_y_eff (_normal_entries_WIRE_24_9_eff), .io_y_c (_normal_entries_WIRE_24_9_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_9_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_37 normal_entries_barrier_10 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_20_ppn), // @[tlb.scala:58:79] .io_x_u (_normal_entries_WIRE_20_u), // @[tlb.scala:58:79] .io_x_g (_normal_entries_WIRE_20_g), // @[tlb.scala:58:79] .io_x_ae (_normal_entries_WIRE_20_ae), // @[tlb.scala:58:79] .io_x_sw (_normal_entries_WIRE_20_sw), // @[tlb.scala:58:79] .io_x_sx (_normal_entries_WIRE_20_sx), // @[tlb.scala:58:79] .io_x_sr (_normal_entries_WIRE_20_sr), // @[tlb.scala:58:79] .io_x_pw (_normal_entries_WIRE_20_pw), // @[tlb.scala:58:79] .io_x_px (_normal_entries_WIRE_20_px), // @[tlb.scala:58:79] .io_x_pr (_normal_entries_WIRE_20_pr), // @[tlb.scala:58:79] .io_x_pal (_normal_entries_WIRE_20_pal), // @[tlb.scala:58:79] .io_x_paa (_normal_entries_WIRE_20_paa), // @[tlb.scala:58:79] .io_x_eff (_normal_entries_WIRE_20_eff), // @[tlb.scala:58:79] .io_x_c (_normal_entries_WIRE_20_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_normal_entries_WIRE_20_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_normal_entries_WIRE_24_10_ppn), .io_y_u (_normal_entries_WIRE_24_10_u), .io_y_g (_normal_entries_WIRE_24_10_g), .io_y_ae (_normal_entries_WIRE_24_10_ae), .io_y_sw (_normal_entries_WIRE_24_10_sw), .io_y_sx (_normal_entries_WIRE_24_10_sx), .io_y_sr (_normal_entries_WIRE_24_10_sr), .io_y_pw (_normal_entries_WIRE_24_10_pw), .io_y_px (_normal_entries_WIRE_24_10_px), .io_y_pr (_normal_entries_WIRE_24_10_pr), .io_y_pal (_normal_entries_WIRE_24_10_pal), .io_y_paa (_normal_entries_WIRE_24_10_paa), .io_y_eff (_normal_entries_WIRE_24_10_eff), .io_y_c (_normal_entries_WIRE_24_10_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_10_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_38 normal_entries_barrier_11 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_22_ppn), // @[tlb.scala:58:79] .io_x_u (_normal_entries_WIRE_22_u), // @[tlb.scala:58:79] .io_x_g (_normal_entries_WIRE_22_g), // @[tlb.scala:58:79] .io_x_ae (_normal_entries_WIRE_22_ae), // @[tlb.scala:58:79] .io_x_sw (_normal_entries_WIRE_22_sw), // @[tlb.scala:58:79] .io_x_sx (_normal_entries_WIRE_22_sx), // @[tlb.scala:58:79] .io_x_sr (_normal_entries_WIRE_22_sr), // @[tlb.scala:58:79] .io_x_pw (_normal_entries_WIRE_22_pw), // @[tlb.scala:58:79] .io_x_px (_normal_entries_WIRE_22_px), // @[tlb.scala:58:79] .io_x_pr (_normal_entries_WIRE_22_pr), // @[tlb.scala:58:79] .io_x_pal (_normal_entries_WIRE_22_pal), // @[tlb.scala:58:79] .io_x_paa (_normal_entries_WIRE_22_paa), // @[tlb.scala:58:79] .io_x_eff (_normal_entries_WIRE_22_eff), // @[tlb.scala:58:79] .io_x_c (_normal_entries_WIRE_22_c), // @[tlb.scala:58:79] .io_x_fragmented_superpage (_normal_entries_WIRE_22_fragmented_superpage), // @[tlb.scala:58:79] .io_y_ppn (_normal_entries_WIRE_24_11_ppn), .io_y_u (_normal_entries_WIRE_24_11_u), .io_y_g (_normal_entries_WIRE_24_11_g), .io_y_ae (_normal_entries_WIRE_24_11_ae), .io_y_sw (_normal_entries_WIRE_24_11_sw), .io_y_sx (_normal_entries_WIRE_24_11_sx), .io_y_sr (_normal_entries_WIRE_24_11_sr), .io_y_pw (_normal_entries_WIRE_24_11_pw), .io_y_px (_normal_entries_WIRE_24_11_px), .io_y_pr (_normal_entries_WIRE_24_11_pr), .io_y_pal (_normal_entries_WIRE_24_11_pal), .io_y_paa (_normal_entries_WIRE_24_11_paa), .io_y_eff (_normal_entries_WIRE_24_11_eff), .io_y_c (_normal_entries_WIRE_24_11_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_11_fragmented_superpage) ); // @[package.scala:267:25] assign io_resp_0_paddr = io_resp_0_paddr_0; // @[tlb.scala:17:7] assign io_resp_0_pf_ld = io_resp_0_pf_ld_0; // @[tlb.scala:17:7] assign io_resp_0_pf_st = io_resp_0_pf_st_0; // @[tlb.scala:17:7] assign io_resp_0_ae_ld = io_resp_0_ae_ld_0; // @[tlb.scala:17:7] assign io_resp_0_ae_st = io_resp_0_ae_st_0; // @[tlb.scala:17:7] assign io_resp_0_ma_ld = io_resp_0_ma_ld_0; // @[tlb.scala:17:7] assign io_resp_0_ma_st = io_resp_0_ma_st_0; // @[tlb.scala:17:7] assign io_resp_0_cacheable = io_resp_0_cacheable_0; // @[tlb.scala:17:7] assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[tlb.scala:17:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_21 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h110)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h40)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h41)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h42)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h43)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0) node _source_ok_T_28 = shr(io.in.a.bits.source, 5) node _source_ok_T_29 = eq(_source_ok_T_28, UInt<1>(0h0)) node _source_ok_T_30 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) node _source_ok_T_32 = leq(source_ok_uncommonBits_4, UInt<5>(0h1f)) node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0) node _source_ok_T_34 = shr(io.in.a.bits.source, 5) node _source_ok_T_35 = eq(_source_ok_T_34, UInt<1>(0h1)) node _source_ok_T_36 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) node _source_ok_T_38 = leq(source_ok_uncommonBits_5, UInt<5>(0h1f)) node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_40 = shr(io.in.a.bits.source, 5) node _source_ok_T_41 = eq(_source_ok_T_40, UInt<2>(0h2)) node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_T_44 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f)) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_46 = shr(io.in.a.bits.source, 5) node _source_ok_T_47 = eq(_source_ok_T_46, UInt<2>(0h3)) node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_T_50 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f)) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_52 = shr(io.in.a.bits.source, 5) node _source_ok_T_53 = eq(_source_ok_T_52, UInt<3>(0h4)) node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_T_56 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f)) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_58 = shr(io.in.a.bits.source, 5) node _source_ok_T_59 = eq(_source_ok_T_58, UInt<3>(0h5)) node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_T_62 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f)) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_64 = shr(io.in.a.bits.source, 5) node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h6)) node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_T_68 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f)) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_70 = shr(io.in.a.bits.source, 5) node _source_ok_T_71 = eq(_source_ok_T_70, UInt<3>(0h7)) node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_T_74 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f)) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_T_76 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE : UInt<1>[17] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_33 connect _source_ok_WIRE[9], _source_ok_T_39 connect _source_ok_WIRE[10], _source_ok_T_45 connect _source_ok_WIRE[11], _source_ok_T_51 connect _source_ok_WIRE[12], _source_ok_T_57 connect _source_ok_WIRE[13], _source_ok_T_63 connect _source_ok_WIRE[14], _source_ok_T_69 connect _source_ok_WIRE[15], _source_ok_T_75 connect _source_ok_WIRE[16], _source_ok_T_76 node _source_ok_T_77 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[2]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[3]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[4]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[5]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[6]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[7]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[8]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[9]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[10]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[11]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[12]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[13]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[14]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[15]) node source_ok = or(_source_ok_T_91, _source_ok_WIRE[16]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<7>(0h40)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<7>(0h41)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<7>(0h42)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<7>(0h43)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_88 = shr(io.in.a.bits.source, 5) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = leq(UInt<1>(0h0), uncommonBits_4) node _T_91 = and(_T_89, _T_90) node _T_92 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_93 = and(_T_91, _T_92) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_101 = shr(io.in.a.bits.source, 5) node _T_102 = eq(_T_101, UInt<1>(0h1)) node _T_103 = leq(UInt<1>(0h0), uncommonBits_5) node _T_104 = and(_T_102, _T_103) node _T_105 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_114 = shr(io.in.a.bits.source, 5) node _T_115 = eq(_T_114, UInt<2>(0h2)) node _T_116 = leq(UInt<1>(0h0), uncommonBits_6) node _T_117 = and(_T_115, _T_116) node _T_118 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = or(_T_120, _T_125) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_127 = shr(io.in.a.bits.source, 5) node _T_128 = eq(_T_127, UInt<2>(0h3)) node _T_129 = leq(UInt<1>(0h0), uncommonBits_7) node _T_130 = and(_T_128, _T_129) node _T_131 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_132 = and(_T_130, _T_131) node _T_133 = eq(_T_132, UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = or(_T_133, _T_138) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_140 = shr(io.in.a.bits.source, 5) node _T_141 = eq(_T_140, UInt<3>(0h4)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_8) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_145 = and(_T_143, _T_144) node _T_146 = eq(_T_145, UInt<1>(0h0)) node _T_147 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = or(_T_146, _T_151) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_153 = shr(io.in.a.bits.source, 5) node _T_154 = eq(_T_153, UInt<3>(0h5)) node _T_155 = leq(UInt<1>(0h0), uncommonBits_9) node _T_156 = and(_T_154, _T_155) node _T_157 = leq(uncommonBits_9, UInt<5>(0h1f)) node _T_158 = and(_T_156, _T_157) node _T_159 = eq(_T_158, UInt<1>(0h0)) node _T_160 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<1>(0h0))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = or(_T_159, _T_164) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_166 = shr(io.in.a.bits.source, 5) node _T_167 = eq(_T_166, UInt<3>(0h6)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_10) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_10, UInt<5>(0h1f)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(_T_171, UInt<1>(0h0)) node _T_173 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_174 = cvt(_T_173) node _T_175 = and(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = asSInt(_T_175) node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = or(_T_172, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_179 = shr(io.in.a.bits.source, 5) node _T_180 = eq(_T_179, UInt<3>(0h7)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<5>(0h1f)) node _T_184 = and(_T_182, _T_183) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = and(_T_11, _T_24) node _T_201 = and(_T_200, _T_37) node _T_202 = and(_T_201, _T_50) node _T_203 = and(_T_202, _T_63) node _T_204 = and(_T_203, _T_71) node _T_205 = and(_T_204, _T_79) node _T_206 = and(_T_205, _T_87) node _T_207 = and(_T_206, _T_100) node _T_208 = and(_T_207, _T_113) node _T_209 = and(_T_208, _T_126) node _T_210 = and(_T_209, _T_139) node _T_211 = and(_T_210, _T_152) node _T_212 = and(_T_211, _T_165) node _T_213 = and(_T_212, _T_178) node _T_214 = and(_T_213, _T_191) node _T_215 = and(_T_214, _T_199) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_215, UInt<1>(0h1), "") : assert_1 node _T_219 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_219 : node _T_220 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_221 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_222 = and(_T_220, _T_221) node _T_223 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_224 = shr(io.in.a.bits.source, 2) node _T_225 = eq(_T_224, UInt<7>(0h40)) node _T_226 = leq(UInt<1>(0h0), uncommonBits_12) node _T_227 = and(_T_225, _T_226) node _T_228 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_229 = and(_T_227, _T_228) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_230 = shr(io.in.a.bits.source, 2) node _T_231 = eq(_T_230, UInt<7>(0h41)) node _T_232 = leq(UInt<1>(0h0), uncommonBits_13) node _T_233 = and(_T_231, _T_232) node _T_234 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_235 = and(_T_233, _T_234) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_236 = shr(io.in.a.bits.source, 2) node _T_237 = eq(_T_236, UInt<7>(0h42)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_14) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_242 = shr(io.in.a.bits.source, 2) node _T_243 = eq(_T_242, UInt<7>(0h43)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_15) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_247 = and(_T_245, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_249 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_250 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_251 = shr(io.in.a.bits.source, 5) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_16) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_16, UInt<5>(0h1f)) node _T_256 = and(_T_254, _T_255) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_257 = shr(io.in.a.bits.source, 5) node _T_258 = eq(_T_257, UInt<1>(0h1)) node _T_259 = leq(UInt<1>(0h0), uncommonBits_17) node _T_260 = and(_T_258, _T_259) node _T_261 = leq(uncommonBits_17, UInt<5>(0h1f)) node _T_262 = and(_T_260, _T_261) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_263 = shr(io.in.a.bits.source, 5) node _T_264 = eq(_T_263, UInt<2>(0h2)) node _T_265 = leq(UInt<1>(0h0), uncommonBits_18) node _T_266 = and(_T_264, _T_265) node _T_267 = leq(uncommonBits_18, UInt<5>(0h1f)) node _T_268 = and(_T_266, _T_267) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_269 = shr(io.in.a.bits.source, 5) node _T_270 = eq(_T_269, UInt<2>(0h3)) node _T_271 = leq(UInt<1>(0h0), uncommonBits_19) node _T_272 = and(_T_270, _T_271) node _T_273 = leq(uncommonBits_19, UInt<5>(0h1f)) node _T_274 = and(_T_272, _T_273) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_275 = shr(io.in.a.bits.source, 5) node _T_276 = eq(_T_275, UInt<3>(0h4)) node _T_277 = leq(UInt<1>(0h0), uncommonBits_20) node _T_278 = and(_T_276, _T_277) node _T_279 = leq(uncommonBits_20, UInt<5>(0h1f)) node _T_280 = and(_T_278, _T_279) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_281 = shr(io.in.a.bits.source, 5) node _T_282 = eq(_T_281, UInt<3>(0h5)) node _T_283 = leq(UInt<1>(0h0), uncommonBits_21) node _T_284 = and(_T_282, _T_283) node _T_285 = leq(uncommonBits_21, UInt<5>(0h1f)) node _T_286 = and(_T_284, _T_285) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0) node _T_287 = shr(io.in.a.bits.source, 5) node _T_288 = eq(_T_287, UInt<3>(0h6)) node _T_289 = leq(UInt<1>(0h0), uncommonBits_22) node _T_290 = and(_T_288, _T_289) node _T_291 = leq(uncommonBits_22, UInt<5>(0h1f)) node _T_292 = and(_T_290, _T_291) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0) node _T_293 = shr(io.in.a.bits.source, 5) node _T_294 = eq(_T_293, UInt<3>(0h7)) node _T_295 = leq(UInt<1>(0h0), uncommonBits_23) node _T_296 = and(_T_294, _T_295) node _T_297 = leq(uncommonBits_23, UInt<5>(0h1f)) node _T_298 = and(_T_296, _T_297) node _T_299 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_300 = or(_T_223, _T_229) node _T_301 = or(_T_300, _T_235) node _T_302 = or(_T_301, _T_241) node _T_303 = or(_T_302, _T_247) node _T_304 = or(_T_303, _T_248) node _T_305 = or(_T_304, _T_249) node _T_306 = or(_T_305, _T_250) node _T_307 = or(_T_306, _T_256) node _T_308 = or(_T_307, _T_262) node _T_309 = or(_T_308, _T_268) node _T_310 = or(_T_309, _T_274) node _T_311 = or(_T_310, _T_280) node _T_312 = or(_T_311, _T_286) node _T_313 = or(_T_312, _T_292) node _T_314 = or(_T_313, _T_298) node _T_315 = or(_T_314, _T_299) node _T_316 = and(_T_222, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<14>(0h2000))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<13>(0h1000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_330 = cvt(_T_329) node _T_331 = and(_T_330, asSInt(UInt<17>(0h10000))) node _T_332 = asSInt(_T_331) node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0))) node _T_334 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<18>(0h2f000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<17>(0h10000))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_345 = cvt(_T_344) node _T_346 = and(_T_345, asSInt(UInt<13>(0h1000))) node _T_347 = asSInt(_T_346) node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_350 = cvt(_T_349) node _T_351 = and(_T_350, asSInt(UInt<27>(0h4000000))) node _T_352 = asSInt(_T_351) node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0))) node _T_354 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<13>(0h1000))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_360 = cvt(_T_359) node _T_361 = and(_T_360, asSInt(UInt<19>(0h40000))) node _T_362 = asSInt(_T_361) node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0))) node _T_364 = or(_T_323, _T_328) node _T_365 = or(_T_364, _T_333) node _T_366 = or(_T_365, _T_338) node _T_367 = or(_T_366, _T_343) node _T_368 = or(_T_367, _T_348) node _T_369 = or(_T_368, _T_353) node _T_370 = or(_T_369, _T_358) node _T_371 = or(_T_370, _T_363) node _T_372 = and(_T_318, _T_371) node _T_373 = or(UInt<1>(0h0), _T_372) node _T_374 = and(_T_317, _T_373) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_374, UInt<1>(0h1), "") : assert_2 node _T_378 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_379 = shr(io.in.a.bits.source, 2) node _T_380 = eq(_T_379, UInt<7>(0h40)) node _T_381 = leq(UInt<1>(0h0), uncommonBits_24) node _T_382 = and(_T_380, _T_381) node _T_383 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_384 = and(_T_382, _T_383) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_385 = shr(io.in.a.bits.source, 2) node _T_386 = eq(_T_385, UInt<7>(0h41)) node _T_387 = leq(UInt<1>(0h0), uncommonBits_25) node _T_388 = and(_T_386, _T_387) node _T_389 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_390 = and(_T_388, _T_389) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_391 = shr(io.in.a.bits.source, 2) node _T_392 = eq(_T_391, UInt<7>(0h42)) node _T_393 = leq(UInt<1>(0h0), uncommonBits_26) node _T_394 = and(_T_392, _T_393) node _T_395 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_396 = and(_T_394, _T_395) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_397 = shr(io.in.a.bits.source, 2) node _T_398 = eq(_T_397, UInt<7>(0h43)) node _T_399 = leq(UInt<1>(0h0), uncommonBits_27) node _T_400 = and(_T_398, _T_399) node _T_401 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_404 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_405 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_406 = shr(io.in.a.bits.source, 5) node _T_407 = eq(_T_406, UInt<1>(0h0)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_28) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_28, UInt<5>(0h1f)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_412 = shr(io.in.a.bits.source, 5) node _T_413 = eq(_T_412, UInt<1>(0h1)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_29) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_29, UInt<5>(0h1f)) node _T_417 = and(_T_415, _T_416) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_418 = shr(io.in.a.bits.source, 5) node _T_419 = eq(_T_418, UInt<2>(0h2)) node _T_420 = leq(UInt<1>(0h0), uncommonBits_30) node _T_421 = and(_T_419, _T_420) node _T_422 = leq(uncommonBits_30, UInt<5>(0h1f)) node _T_423 = and(_T_421, _T_422) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_424 = shr(io.in.a.bits.source, 5) node _T_425 = eq(_T_424, UInt<2>(0h3)) node _T_426 = leq(UInt<1>(0h0), uncommonBits_31) node _T_427 = and(_T_425, _T_426) node _T_428 = leq(uncommonBits_31, UInt<5>(0h1f)) node _T_429 = and(_T_427, _T_428) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_430 = shr(io.in.a.bits.source, 5) node _T_431 = eq(_T_430, UInt<3>(0h4)) node _T_432 = leq(UInt<1>(0h0), uncommonBits_32) node _T_433 = and(_T_431, _T_432) node _T_434 = leq(uncommonBits_32, UInt<5>(0h1f)) node _T_435 = and(_T_433, _T_434) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_436 = shr(io.in.a.bits.source, 5) node _T_437 = eq(_T_436, UInt<3>(0h5)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_33) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_33, UInt<5>(0h1f)) node _T_441 = and(_T_439, _T_440) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0) node _T_442 = shr(io.in.a.bits.source, 5) node _T_443 = eq(_T_442, UInt<3>(0h6)) node _T_444 = leq(UInt<1>(0h0), uncommonBits_34) node _T_445 = and(_T_443, _T_444) node _T_446 = leq(uncommonBits_34, UInt<5>(0h1f)) node _T_447 = and(_T_445, _T_446) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0) node _T_448 = shr(io.in.a.bits.source, 5) node _T_449 = eq(_T_448, UInt<3>(0h7)) node _T_450 = leq(UInt<1>(0h0), uncommonBits_35) node _T_451 = and(_T_449, _T_450) node _T_452 = leq(uncommonBits_35, UInt<5>(0h1f)) node _T_453 = and(_T_451, _T_452) node _T_454 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE : UInt<1>[17] connect _WIRE[0], _T_378 connect _WIRE[1], _T_384 connect _WIRE[2], _T_390 connect _WIRE[3], _T_396 connect _WIRE[4], _T_402 connect _WIRE[5], _T_403 connect _WIRE[6], _T_404 connect _WIRE[7], _T_405 connect _WIRE[8], _T_411 connect _WIRE[9], _T_417 connect _WIRE[10], _T_423 connect _WIRE[11], _T_429 connect _WIRE[12], _T_435 connect _WIRE[13], _T_441 connect _WIRE[14], _T_447 connect _WIRE[15], _T_453 connect _WIRE[16], _T_454 node _T_455 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_456 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_457 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_458 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_459 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_460 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_461 = mux(_WIRE[5], _T_455, UInt<1>(0h0)) node _T_462 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_463 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_464 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_465 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_466 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_468 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_469 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_470 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_471 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_472 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_473 = or(_T_456, _T_457) node _T_474 = or(_T_473, _T_458) node _T_475 = or(_T_474, _T_459) node _T_476 = or(_T_475, _T_460) node _T_477 = or(_T_476, _T_461) node _T_478 = or(_T_477, _T_462) node _T_479 = or(_T_478, _T_463) node _T_480 = or(_T_479, _T_464) node _T_481 = or(_T_480, _T_465) node _T_482 = or(_T_481, _T_466) node _T_483 = or(_T_482, _T_467) node _T_484 = or(_T_483, _T_468) node _T_485 = or(_T_484, _T_469) node _T_486 = or(_T_485, _T_470) node _T_487 = or(_T_486, _T_471) node _T_488 = or(_T_487, _T_472) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_488 node _T_489 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_490 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_491 = and(_T_489, _T_490) node _T_492 = or(UInt<1>(0h0), _T_491) node _T_493 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_494 = cvt(_T_493) node _T_495 = and(_T_494, asSInt(UInt<14>(0h2000))) node _T_496 = asSInt(_T_495) node _T_497 = eq(_T_496, asSInt(UInt<1>(0h0))) node _T_498 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_499 = cvt(_T_498) node _T_500 = and(_T_499, asSInt(UInt<13>(0h1000))) node _T_501 = asSInt(_T_500) node _T_502 = eq(_T_501, asSInt(UInt<1>(0h0))) node _T_503 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_504 = cvt(_T_503) node _T_505 = and(_T_504, asSInt(UInt<17>(0h10000))) node _T_506 = asSInt(_T_505) node _T_507 = eq(_T_506, asSInt(UInt<1>(0h0))) node _T_508 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_509 = cvt(_T_508) node _T_510 = and(_T_509, asSInt(UInt<18>(0h2f000))) node _T_511 = asSInt(_T_510) node _T_512 = eq(_T_511, asSInt(UInt<1>(0h0))) node _T_513 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_514 = cvt(_T_513) node _T_515 = and(_T_514, asSInt(UInt<17>(0h10000))) node _T_516 = asSInt(_T_515) node _T_517 = eq(_T_516, asSInt(UInt<1>(0h0))) node _T_518 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_519 = cvt(_T_518) node _T_520 = and(_T_519, asSInt(UInt<13>(0h1000))) node _T_521 = asSInt(_T_520) node _T_522 = eq(_T_521, asSInt(UInt<1>(0h0))) node _T_523 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_524 = cvt(_T_523) node _T_525 = and(_T_524, asSInt(UInt<27>(0h4000000))) node _T_526 = asSInt(_T_525) node _T_527 = eq(_T_526, asSInt(UInt<1>(0h0))) node _T_528 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_529 = cvt(_T_528) node _T_530 = and(_T_529, asSInt(UInt<13>(0h1000))) node _T_531 = asSInt(_T_530) node _T_532 = eq(_T_531, asSInt(UInt<1>(0h0))) node _T_533 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_534 = cvt(_T_533) node _T_535 = and(_T_534, asSInt(UInt<19>(0h40000))) node _T_536 = asSInt(_T_535) node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0))) node _T_538 = or(_T_497, _T_502) node _T_539 = or(_T_538, _T_507) node _T_540 = or(_T_539, _T_512) node _T_541 = or(_T_540, _T_517) node _T_542 = or(_T_541, _T_522) node _T_543 = or(_T_542, _T_527) node _T_544 = or(_T_543, _T_532) node _T_545 = or(_T_544, _T_537) node _T_546 = and(_T_492, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_WIRE_1, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_548, UInt<1>(0h1), "") : assert_3 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(source_ok, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_555 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(_T_555, UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_555, UInt<1>(0h1), "") : assert_5 node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(is_aligned, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_562 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_562, UInt<1>(0h1), "") : assert_7 node _T_566 = not(io.in.a.bits.mask) node _T_567 = eq(_T_566, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_567, UInt<1>(0h1), "") : assert_8 node _T_571 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_571, UInt<1>(0h1), "") : assert_9 node _T_575 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_575 : node _T_576 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_577 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_578 = and(_T_576, _T_577) node _T_579 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_580 = shr(io.in.a.bits.source, 2) node _T_581 = eq(_T_580, UInt<7>(0h40)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_36) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<7>(0h41)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_37) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_592 = shr(io.in.a.bits.source, 2) node _T_593 = eq(_T_592, UInt<7>(0h42)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_38) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_597 = and(_T_595, _T_596) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_598 = shr(io.in.a.bits.source, 2) node _T_599 = eq(_T_598, UInt<7>(0h43)) node _T_600 = leq(UInt<1>(0h0), uncommonBits_39) node _T_601 = and(_T_599, _T_600) node _T_602 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_603 = and(_T_601, _T_602) node _T_604 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_605 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_606 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_607 = shr(io.in.a.bits.source, 5) node _T_608 = eq(_T_607, UInt<1>(0h0)) node _T_609 = leq(UInt<1>(0h0), uncommonBits_40) node _T_610 = and(_T_608, _T_609) node _T_611 = leq(uncommonBits_40, UInt<5>(0h1f)) node _T_612 = and(_T_610, _T_611) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_613 = shr(io.in.a.bits.source, 5) node _T_614 = eq(_T_613, UInt<1>(0h1)) node _T_615 = leq(UInt<1>(0h0), uncommonBits_41) node _T_616 = and(_T_614, _T_615) node _T_617 = leq(uncommonBits_41, UInt<5>(0h1f)) node _T_618 = and(_T_616, _T_617) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_619 = shr(io.in.a.bits.source, 5) node _T_620 = eq(_T_619, UInt<2>(0h2)) node _T_621 = leq(UInt<1>(0h0), uncommonBits_42) node _T_622 = and(_T_620, _T_621) node _T_623 = leq(uncommonBits_42, UInt<5>(0h1f)) node _T_624 = and(_T_622, _T_623) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_625 = shr(io.in.a.bits.source, 5) node _T_626 = eq(_T_625, UInt<2>(0h3)) node _T_627 = leq(UInt<1>(0h0), uncommonBits_43) node _T_628 = and(_T_626, _T_627) node _T_629 = leq(uncommonBits_43, UInt<5>(0h1f)) node _T_630 = and(_T_628, _T_629) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0) node _T_631 = shr(io.in.a.bits.source, 5) node _T_632 = eq(_T_631, UInt<3>(0h4)) node _T_633 = leq(UInt<1>(0h0), uncommonBits_44) node _T_634 = and(_T_632, _T_633) node _T_635 = leq(uncommonBits_44, UInt<5>(0h1f)) node _T_636 = and(_T_634, _T_635) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0) node _T_637 = shr(io.in.a.bits.source, 5) node _T_638 = eq(_T_637, UInt<3>(0h5)) node _T_639 = leq(UInt<1>(0h0), uncommonBits_45) node _T_640 = and(_T_638, _T_639) node _T_641 = leq(uncommonBits_45, UInt<5>(0h1f)) node _T_642 = and(_T_640, _T_641) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0) node _T_643 = shr(io.in.a.bits.source, 5) node _T_644 = eq(_T_643, UInt<3>(0h6)) node _T_645 = leq(UInt<1>(0h0), uncommonBits_46) node _T_646 = and(_T_644, _T_645) node _T_647 = leq(uncommonBits_46, UInt<5>(0h1f)) node _T_648 = and(_T_646, _T_647) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0) node _T_649 = shr(io.in.a.bits.source, 5) node _T_650 = eq(_T_649, UInt<3>(0h7)) node _T_651 = leq(UInt<1>(0h0), uncommonBits_47) node _T_652 = and(_T_650, _T_651) node _T_653 = leq(uncommonBits_47, UInt<5>(0h1f)) node _T_654 = and(_T_652, _T_653) node _T_655 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_656 = or(_T_579, _T_585) node _T_657 = or(_T_656, _T_591) node _T_658 = or(_T_657, _T_597) node _T_659 = or(_T_658, _T_603) node _T_660 = or(_T_659, _T_604) node _T_661 = or(_T_660, _T_605) node _T_662 = or(_T_661, _T_606) node _T_663 = or(_T_662, _T_612) node _T_664 = or(_T_663, _T_618) node _T_665 = or(_T_664, _T_624) node _T_666 = or(_T_665, _T_630) node _T_667 = or(_T_666, _T_636) node _T_668 = or(_T_667, _T_642) node _T_669 = or(_T_668, _T_648) node _T_670 = or(_T_669, _T_654) node _T_671 = or(_T_670, _T_655) node _T_672 = and(_T_578, _T_671) node _T_673 = or(UInt<1>(0h0), _T_672) node _T_674 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_675 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<14>(0h2000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<13>(0h1000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_686 = cvt(_T_685) node _T_687 = and(_T_686, asSInt(UInt<17>(0h10000))) node _T_688 = asSInt(_T_687) node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0))) node _T_690 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_691 = cvt(_T_690) node _T_692 = and(_T_691, asSInt(UInt<18>(0h2f000))) node _T_693 = asSInt(_T_692) node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) node _T_695 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_696 = cvt(_T_695) node _T_697 = and(_T_696, asSInt(UInt<17>(0h10000))) node _T_698 = asSInt(_T_697) node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0))) node _T_700 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_701 = cvt(_T_700) node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000))) node _T_703 = asSInt(_T_702) node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) node _T_705 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<27>(0h4000000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<13>(0h1000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<19>(0h40000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = or(_T_679, _T_684) node _T_721 = or(_T_720, _T_689) node _T_722 = or(_T_721, _T_694) node _T_723 = or(_T_722, _T_699) node _T_724 = or(_T_723, _T_704) node _T_725 = or(_T_724, _T_709) node _T_726 = or(_T_725, _T_714) node _T_727 = or(_T_726, _T_719) node _T_728 = and(_T_674, _T_727) node _T_729 = or(UInt<1>(0h0), _T_728) node _T_730 = and(_T_673, _T_729) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_730, UInt<1>(0h1), "") : assert_10 node _T_734 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_735 = shr(io.in.a.bits.source, 2) node _T_736 = eq(_T_735, UInt<7>(0h40)) node _T_737 = leq(UInt<1>(0h0), uncommonBits_48) node _T_738 = and(_T_736, _T_737) node _T_739 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_740 = and(_T_738, _T_739) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_741 = shr(io.in.a.bits.source, 2) node _T_742 = eq(_T_741, UInt<7>(0h41)) node _T_743 = leq(UInt<1>(0h0), uncommonBits_49) node _T_744 = and(_T_742, _T_743) node _T_745 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_746 = and(_T_744, _T_745) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_747 = shr(io.in.a.bits.source, 2) node _T_748 = eq(_T_747, UInt<7>(0h42)) node _T_749 = leq(UInt<1>(0h0), uncommonBits_50) node _T_750 = and(_T_748, _T_749) node _T_751 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_752 = and(_T_750, _T_751) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_753 = shr(io.in.a.bits.source, 2) node _T_754 = eq(_T_753, UInt<7>(0h43)) node _T_755 = leq(UInt<1>(0h0), uncommonBits_51) node _T_756 = and(_T_754, _T_755) node _T_757 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_760 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_761 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_762 = shr(io.in.a.bits.source, 5) node _T_763 = eq(_T_762, UInt<1>(0h0)) node _T_764 = leq(UInt<1>(0h0), uncommonBits_52) node _T_765 = and(_T_763, _T_764) node _T_766 = leq(uncommonBits_52, UInt<5>(0h1f)) node _T_767 = and(_T_765, _T_766) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_768 = shr(io.in.a.bits.source, 5) node _T_769 = eq(_T_768, UInt<1>(0h1)) node _T_770 = leq(UInt<1>(0h0), uncommonBits_53) node _T_771 = and(_T_769, _T_770) node _T_772 = leq(uncommonBits_53, UInt<5>(0h1f)) node _T_773 = and(_T_771, _T_772) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_774 = shr(io.in.a.bits.source, 5) node _T_775 = eq(_T_774, UInt<2>(0h2)) node _T_776 = leq(UInt<1>(0h0), uncommonBits_54) node _T_777 = and(_T_775, _T_776) node _T_778 = leq(uncommonBits_54, UInt<5>(0h1f)) node _T_779 = and(_T_777, _T_778) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_780 = shr(io.in.a.bits.source, 5) node _T_781 = eq(_T_780, UInt<2>(0h3)) node _T_782 = leq(UInt<1>(0h0), uncommonBits_55) node _T_783 = and(_T_781, _T_782) node _T_784 = leq(uncommonBits_55, UInt<5>(0h1f)) node _T_785 = and(_T_783, _T_784) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0) node _T_786 = shr(io.in.a.bits.source, 5) node _T_787 = eq(_T_786, UInt<3>(0h4)) node _T_788 = leq(UInt<1>(0h0), uncommonBits_56) node _T_789 = and(_T_787, _T_788) node _T_790 = leq(uncommonBits_56, UInt<5>(0h1f)) node _T_791 = and(_T_789, _T_790) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0) node _T_792 = shr(io.in.a.bits.source, 5) node _T_793 = eq(_T_792, UInt<3>(0h5)) node _T_794 = leq(UInt<1>(0h0), uncommonBits_57) node _T_795 = and(_T_793, _T_794) node _T_796 = leq(uncommonBits_57, UInt<5>(0h1f)) node _T_797 = and(_T_795, _T_796) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_798 = shr(io.in.a.bits.source, 5) node _T_799 = eq(_T_798, UInt<3>(0h6)) node _T_800 = leq(UInt<1>(0h0), uncommonBits_58) node _T_801 = and(_T_799, _T_800) node _T_802 = leq(uncommonBits_58, UInt<5>(0h1f)) node _T_803 = and(_T_801, _T_802) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_804 = shr(io.in.a.bits.source, 5) node _T_805 = eq(_T_804, UInt<3>(0h7)) node _T_806 = leq(UInt<1>(0h0), uncommonBits_59) node _T_807 = and(_T_805, _T_806) node _T_808 = leq(uncommonBits_59, UInt<5>(0h1f)) node _T_809 = and(_T_807, _T_808) node _T_810 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE_2 : UInt<1>[17] connect _WIRE_2[0], _T_734 connect _WIRE_2[1], _T_740 connect _WIRE_2[2], _T_746 connect _WIRE_2[3], _T_752 connect _WIRE_2[4], _T_758 connect _WIRE_2[5], _T_759 connect _WIRE_2[6], _T_760 connect _WIRE_2[7], _T_761 connect _WIRE_2[8], _T_767 connect _WIRE_2[9], _T_773 connect _WIRE_2[10], _T_779 connect _WIRE_2[11], _T_785 connect _WIRE_2[12], _T_791 connect _WIRE_2[13], _T_797 connect _WIRE_2[14], _T_803 connect _WIRE_2[15], _T_809 connect _WIRE_2[16], _T_810 node _T_811 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_812 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_813 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_814 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_815 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_816 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_817 = mux(_WIRE_2[5], _T_811, UInt<1>(0h0)) node _T_818 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_819 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_820 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_821 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_822 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_823 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_824 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_825 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_826 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_827 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_828 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_829 = or(_T_812, _T_813) node _T_830 = or(_T_829, _T_814) node _T_831 = or(_T_830, _T_815) node _T_832 = or(_T_831, _T_816) node _T_833 = or(_T_832, _T_817) node _T_834 = or(_T_833, _T_818) node _T_835 = or(_T_834, _T_819) node _T_836 = or(_T_835, _T_820) node _T_837 = or(_T_836, _T_821) node _T_838 = or(_T_837, _T_822) node _T_839 = or(_T_838, _T_823) node _T_840 = or(_T_839, _T_824) node _T_841 = or(_T_840, _T_825) node _T_842 = or(_T_841, _T_826) node _T_843 = or(_T_842, _T_827) node _T_844 = or(_T_843, _T_828) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_844 node _T_845 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_846 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_847 = and(_T_845, _T_846) node _T_848 = or(UInt<1>(0h0), _T_847) node _T_849 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<14>(0h2000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<19>(0h40000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = or(_T_853, _T_858) node _T_895 = or(_T_894, _T_863) node _T_896 = or(_T_895, _T_868) node _T_897 = or(_T_896, _T_873) node _T_898 = or(_T_897, _T_878) node _T_899 = or(_T_898, _T_883) node _T_900 = or(_T_899, _T_888) node _T_901 = or(_T_900, _T_893) node _T_902 = and(_T_848, _T_901) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = and(_WIRE_3, _T_903) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_904, UInt<1>(0h1), "") : assert_11 node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_911 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_911, UInt<1>(0h1), "") : assert_13 node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(is_aligned, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_918 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_918, UInt<1>(0h1), "") : assert_15 node _T_922 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_T_922, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_922, UInt<1>(0h1), "") : assert_16 node _T_926 = not(io.in.a.bits.mask) node _T_927 = eq(_T_926, UInt<1>(0h0)) node _T_928 = asUInt(reset) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(_T_927, UInt<1>(0h0)) when _T_930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_927, UInt<1>(0h1), "") : assert_17 node _T_931 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(_T_931, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_931, UInt<1>(0h1), "") : assert_18 node _T_935 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_935 : node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_937 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_938 = and(_T_936, _T_937) node _T_939 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_940 = shr(io.in.a.bits.source, 2) node _T_941 = eq(_T_940, UInt<7>(0h40)) node _T_942 = leq(UInt<1>(0h0), uncommonBits_60) node _T_943 = and(_T_941, _T_942) node _T_944 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_945 = and(_T_943, _T_944) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_946 = shr(io.in.a.bits.source, 2) node _T_947 = eq(_T_946, UInt<7>(0h41)) node _T_948 = leq(UInt<1>(0h0), uncommonBits_61) node _T_949 = and(_T_947, _T_948) node _T_950 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_951 = and(_T_949, _T_950) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_952 = shr(io.in.a.bits.source, 2) node _T_953 = eq(_T_952, UInt<7>(0h42)) node _T_954 = leq(UInt<1>(0h0), uncommonBits_62) node _T_955 = and(_T_953, _T_954) node _T_956 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_957 = and(_T_955, _T_956) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_958 = shr(io.in.a.bits.source, 2) node _T_959 = eq(_T_958, UInt<7>(0h43)) node _T_960 = leq(UInt<1>(0h0), uncommonBits_63) node _T_961 = and(_T_959, _T_960) node _T_962 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_963 = and(_T_961, _T_962) node _T_964 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_965 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_966 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_967 = shr(io.in.a.bits.source, 5) node _T_968 = eq(_T_967, UInt<1>(0h0)) node _T_969 = leq(UInt<1>(0h0), uncommonBits_64) node _T_970 = and(_T_968, _T_969) node _T_971 = leq(uncommonBits_64, UInt<5>(0h1f)) node _T_972 = and(_T_970, _T_971) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_973 = shr(io.in.a.bits.source, 5) node _T_974 = eq(_T_973, UInt<1>(0h1)) node _T_975 = leq(UInt<1>(0h0), uncommonBits_65) node _T_976 = and(_T_974, _T_975) node _T_977 = leq(uncommonBits_65, UInt<5>(0h1f)) node _T_978 = and(_T_976, _T_977) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0) node _T_979 = shr(io.in.a.bits.source, 5) node _T_980 = eq(_T_979, UInt<2>(0h2)) node _T_981 = leq(UInt<1>(0h0), uncommonBits_66) node _T_982 = and(_T_980, _T_981) node _T_983 = leq(uncommonBits_66, UInt<5>(0h1f)) node _T_984 = and(_T_982, _T_983) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0) node _T_985 = shr(io.in.a.bits.source, 5) node _T_986 = eq(_T_985, UInt<2>(0h3)) node _T_987 = leq(UInt<1>(0h0), uncommonBits_67) node _T_988 = and(_T_986, _T_987) node _T_989 = leq(uncommonBits_67, UInt<5>(0h1f)) node _T_990 = and(_T_988, _T_989) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0) node _T_991 = shr(io.in.a.bits.source, 5) node _T_992 = eq(_T_991, UInt<3>(0h4)) node _T_993 = leq(UInt<1>(0h0), uncommonBits_68) node _T_994 = and(_T_992, _T_993) node _T_995 = leq(uncommonBits_68, UInt<5>(0h1f)) node _T_996 = and(_T_994, _T_995) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0) node _T_997 = shr(io.in.a.bits.source, 5) node _T_998 = eq(_T_997, UInt<3>(0h5)) node _T_999 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1000 = and(_T_998, _T_999) node _T_1001 = leq(uncommonBits_69, UInt<5>(0h1f)) node _T_1002 = and(_T_1000, _T_1001) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0) node _T_1003 = shr(io.in.a.bits.source, 5) node _T_1004 = eq(_T_1003, UInt<3>(0h6)) node _T_1005 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1006 = and(_T_1004, _T_1005) node _T_1007 = leq(uncommonBits_70, UInt<5>(0h1f)) node _T_1008 = and(_T_1006, _T_1007) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0) node _T_1009 = shr(io.in.a.bits.source, 5) node _T_1010 = eq(_T_1009, UInt<3>(0h7)) node _T_1011 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1012 = and(_T_1010, _T_1011) node _T_1013 = leq(uncommonBits_71, UInt<5>(0h1f)) node _T_1014 = and(_T_1012, _T_1013) node _T_1015 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1016 = or(_T_939, _T_945) node _T_1017 = or(_T_1016, _T_951) node _T_1018 = or(_T_1017, _T_957) node _T_1019 = or(_T_1018, _T_963) node _T_1020 = or(_T_1019, _T_964) node _T_1021 = or(_T_1020, _T_965) node _T_1022 = or(_T_1021, _T_966) node _T_1023 = or(_T_1022, _T_972) node _T_1024 = or(_T_1023, _T_978) node _T_1025 = or(_T_1024, _T_984) node _T_1026 = or(_T_1025, _T_990) node _T_1027 = or(_T_1026, _T_996) node _T_1028 = or(_T_1027, _T_1002) node _T_1029 = or(_T_1028, _T_1008) node _T_1030 = or(_T_1029, _T_1014) node _T_1031 = or(_T_1030, _T_1015) node _T_1032 = and(_T_938, _T_1031) node _T_1033 = or(UInt<1>(0h0), _T_1032) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_19 node _T_1037 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1038 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1039 = and(_T_1037, _T_1038) node _T_1040 = or(UInt<1>(0h0), _T_1039) node _T_1041 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1042 = cvt(_T_1041) node _T_1043 = and(_T_1042, asSInt(UInt<13>(0h1000))) node _T_1044 = asSInt(_T_1043) node _T_1045 = eq(_T_1044, asSInt(UInt<1>(0h0))) node _T_1046 = and(_T_1040, _T_1045) node _T_1047 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1048 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = or(UInt<1>(0h0), _T_1049) node _T_1051 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1052 = cvt(_T_1051) node _T_1053 = and(_T_1052, asSInt(UInt<14>(0h2000))) node _T_1054 = asSInt(_T_1053) node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0))) node _T_1056 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1057 = cvt(_T_1056) node _T_1058 = and(_T_1057, asSInt(UInt<17>(0h10000))) node _T_1059 = asSInt(_T_1058) node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0))) node _T_1061 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1062 = cvt(_T_1061) node _T_1063 = and(_T_1062, asSInt(UInt<18>(0h2f000))) node _T_1064 = asSInt(_T_1063) node _T_1065 = eq(_T_1064, asSInt(UInt<1>(0h0))) node _T_1066 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1067 = cvt(_T_1066) node _T_1068 = and(_T_1067, asSInt(UInt<17>(0h10000))) node _T_1069 = asSInt(_T_1068) node _T_1070 = eq(_T_1069, asSInt(UInt<1>(0h0))) node _T_1071 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1072 = cvt(_T_1071) node _T_1073 = and(_T_1072, asSInt(UInt<13>(0h1000))) node _T_1074 = asSInt(_T_1073) node _T_1075 = eq(_T_1074, asSInt(UInt<1>(0h0))) node _T_1076 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1077 = cvt(_T_1076) node _T_1078 = and(_T_1077, asSInt(UInt<27>(0h4000000))) node _T_1079 = asSInt(_T_1078) node _T_1080 = eq(_T_1079, asSInt(UInt<1>(0h0))) node _T_1081 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1082 = cvt(_T_1081) node _T_1083 = and(_T_1082, asSInt(UInt<13>(0h1000))) node _T_1084 = asSInt(_T_1083) node _T_1085 = eq(_T_1084, asSInt(UInt<1>(0h0))) node _T_1086 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1087 = cvt(_T_1086) node _T_1088 = and(_T_1087, asSInt(UInt<19>(0h40000))) node _T_1089 = asSInt(_T_1088) node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0))) node _T_1091 = or(_T_1055, _T_1060) node _T_1092 = or(_T_1091, _T_1065) node _T_1093 = or(_T_1092, _T_1070) node _T_1094 = or(_T_1093, _T_1075) node _T_1095 = or(_T_1094, _T_1080) node _T_1096 = or(_T_1095, _T_1085) node _T_1097 = or(_T_1096, _T_1090) node _T_1098 = and(_T_1050, _T_1097) node _T_1099 = or(UInt<1>(0h0), _T_1046) node _T_1100 = or(_T_1099, _T_1098) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_20 node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(source_ok, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(is_aligned, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1110 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_23 node _T_1114 = eq(io.in.a.bits.mask, mask) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_24 node _T_1118 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_25 node _T_1122 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1122 : node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1125 = and(_T_1123, _T_1124) node _T_1126 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_1127 = shr(io.in.a.bits.source, 2) node _T_1128 = eq(_T_1127, UInt<7>(0h40)) node _T_1129 = leq(UInt<1>(0h0), uncommonBits_72) node _T_1130 = and(_T_1128, _T_1129) node _T_1131 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_1132 = and(_T_1130, _T_1131) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_1133 = shr(io.in.a.bits.source, 2) node _T_1134 = eq(_T_1133, UInt<7>(0h41)) node _T_1135 = leq(UInt<1>(0h0), uncommonBits_73) node _T_1136 = and(_T_1134, _T_1135) node _T_1137 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_1138 = and(_T_1136, _T_1137) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 1, 0) node _T_1139 = shr(io.in.a.bits.source, 2) node _T_1140 = eq(_T_1139, UInt<7>(0h42)) node _T_1141 = leq(UInt<1>(0h0), uncommonBits_74) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = leq(uncommonBits_74, UInt<2>(0h3)) node _T_1144 = and(_T_1142, _T_1143) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0) node _T_1145 = shr(io.in.a.bits.source, 2) node _T_1146 = eq(_T_1145, UInt<7>(0h43)) node _T_1147 = leq(UInt<1>(0h0), uncommonBits_75) node _T_1148 = and(_T_1146, _T_1147) node _T_1149 = leq(uncommonBits_75, UInt<2>(0h3)) node _T_1150 = and(_T_1148, _T_1149) node _T_1151 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1152 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1153 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0) node _T_1154 = shr(io.in.a.bits.source, 5) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) node _T_1156 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1157 = and(_T_1155, _T_1156) node _T_1158 = leq(uncommonBits_76, UInt<5>(0h1f)) node _T_1159 = and(_T_1157, _T_1158) node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0) node _T_1160 = shr(io.in.a.bits.source, 5) node _T_1161 = eq(_T_1160, UInt<1>(0h1)) node _T_1162 = leq(UInt<1>(0h0), uncommonBits_77) node _T_1163 = and(_T_1161, _T_1162) node _T_1164 = leq(uncommonBits_77, UInt<5>(0h1f)) node _T_1165 = and(_T_1163, _T_1164) node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 4, 0) node _T_1166 = shr(io.in.a.bits.source, 5) node _T_1167 = eq(_T_1166, UInt<2>(0h2)) node _T_1168 = leq(UInt<1>(0h0), uncommonBits_78) node _T_1169 = and(_T_1167, _T_1168) node _T_1170 = leq(uncommonBits_78, UInt<5>(0h1f)) node _T_1171 = and(_T_1169, _T_1170) node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 4, 0) node _T_1172 = shr(io.in.a.bits.source, 5) node _T_1173 = eq(_T_1172, UInt<2>(0h3)) node _T_1174 = leq(UInt<1>(0h0), uncommonBits_79) node _T_1175 = and(_T_1173, _T_1174) node _T_1176 = leq(uncommonBits_79, UInt<5>(0h1f)) node _T_1177 = and(_T_1175, _T_1176) node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0) node _T_1178 = shr(io.in.a.bits.source, 5) node _T_1179 = eq(_T_1178, UInt<3>(0h4)) node _T_1180 = leq(UInt<1>(0h0), uncommonBits_80) node _T_1181 = and(_T_1179, _T_1180) node _T_1182 = leq(uncommonBits_80, UInt<5>(0h1f)) node _T_1183 = and(_T_1181, _T_1182) node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0) node _T_1184 = shr(io.in.a.bits.source, 5) node _T_1185 = eq(_T_1184, UInt<3>(0h5)) node _T_1186 = leq(UInt<1>(0h0), uncommonBits_81) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = leq(uncommonBits_81, UInt<5>(0h1f)) node _T_1189 = and(_T_1187, _T_1188) node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0) node _T_1190 = shr(io.in.a.bits.source, 5) node _T_1191 = eq(_T_1190, UInt<3>(0h6)) node _T_1192 = leq(UInt<1>(0h0), uncommonBits_82) node _T_1193 = and(_T_1191, _T_1192) node _T_1194 = leq(uncommonBits_82, UInt<5>(0h1f)) node _T_1195 = and(_T_1193, _T_1194) node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0) node _T_1196 = shr(io.in.a.bits.source, 5) node _T_1197 = eq(_T_1196, UInt<3>(0h7)) node _T_1198 = leq(UInt<1>(0h0), uncommonBits_83) node _T_1199 = and(_T_1197, _T_1198) node _T_1200 = leq(uncommonBits_83, UInt<5>(0h1f)) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1203 = or(_T_1126, _T_1132) node _T_1204 = or(_T_1203, _T_1138) node _T_1205 = or(_T_1204, _T_1144) node _T_1206 = or(_T_1205, _T_1150) node _T_1207 = or(_T_1206, _T_1151) node _T_1208 = or(_T_1207, _T_1152) node _T_1209 = or(_T_1208, _T_1153) node _T_1210 = or(_T_1209, _T_1159) node _T_1211 = or(_T_1210, _T_1165) node _T_1212 = or(_T_1211, _T_1171) node _T_1213 = or(_T_1212, _T_1177) node _T_1214 = or(_T_1213, _T_1183) node _T_1215 = or(_T_1214, _T_1189) node _T_1216 = or(_T_1215, _T_1195) node _T_1217 = or(_T_1216, _T_1201) node _T_1218 = or(_T_1217, _T_1202) node _T_1219 = and(_T_1125, _T_1218) node _T_1220 = or(UInt<1>(0h0), _T_1219) node _T_1221 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1222 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1223 = and(_T_1221, _T_1222) node _T_1224 = or(UInt<1>(0h0), _T_1223) node _T_1225 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1226 = cvt(_T_1225) node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000))) node _T_1228 = asSInt(_T_1227) node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0))) node _T_1230 = and(_T_1224, _T_1229) node _T_1231 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1232 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = or(UInt<1>(0h0), _T_1233) node _T_1235 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1236 = cvt(_T_1235) node _T_1237 = and(_T_1236, asSInt(UInt<14>(0h2000))) node _T_1238 = asSInt(_T_1237) node _T_1239 = eq(_T_1238, asSInt(UInt<1>(0h0))) node _T_1240 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1241 = cvt(_T_1240) node _T_1242 = and(_T_1241, asSInt(UInt<18>(0h2f000))) node _T_1243 = asSInt(_T_1242) node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0))) node _T_1245 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1246 = cvt(_T_1245) node _T_1247 = and(_T_1246, asSInt(UInt<17>(0h10000))) node _T_1248 = asSInt(_T_1247) node _T_1249 = eq(_T_1248, asSInt(UInt<1>(0h0))) node _T_1250 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1251 = cvt(_T_1250) node _T_1252 = and(_T_1251, asSInt(UInt<13>(0h1000))) node _T_1253 = asSInt(_T_1252) node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0))) node _T_1255 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1256 = cvt(_T_1255) node _T_1257 = and(_T_1256, asSInt(UInt<27>(0h4000000))) node _T_1258 = asSInt(_T_1257) node _T_1259 = eq(_T_1258, asSInt(UInt<1>(0h0))) node _T_1260 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1261 = cvt(_T_1260) node _T_1262 = and(_T_1261, asSInt(UInt<13>(0h1000))) node _T_1263 = asSInt(_T_1262) node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0))) node _T_1265 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1266 = cvt(_T_1265) node _T_1267 = and(_T_1266, asSInt(UInt<19>(0h40000))) node _T_1268 = asSInt(_T_1267) node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0))) node _T_1270 = or(_T_1239, _T_1244) node _T_1271 = or(_T_1270, _T_1249) node _T_1272 = or(_T_1271, _T_1254) node _T_1273 = or(_T_1272, _T_1259) node _T_1274 = or(_T_1273, _T_1264) node _T_1275 = or(_T_1274, _T_1269) node _T_1276 = and(_T_1234, _T_1275) node _T_1277 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1278 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1279 = cvt(_T_1278) node _T_1280 = and(_T_1279, asSInt(UInt<17>(0h10000))) node _T_1281 = asSInt(_T_1280) node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0))) node _T_1283 = and(_T_1277, _T_1282) node _T_1284 = or(UInt<1>(0h0), _T_1230) node _T_1285 = or(_T_1284, _T_1276) node _T_1286 = or(_T_1285, _T_1283) node _T_1287 = and(_T_1220, _T_1286) node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(_T_1287, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1287, UInt<1>(0h1), "") : assert_26 node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(source_ok, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(is_aligned, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1297 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_29 node _T_1301 = eq(io.in.a.bits.mask, mask) node _T_1302 = asUInt(reset) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) when _T_1303 : node _T_1304 = eq(_T_1301, UInt<1>(0h0)) when _T_1304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1301, UInt<1>(0h1), "") : assert_30 node _T_1305 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1305 : node _T_1306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1307 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1308 = and(_T_1306, _T_1307) node _T_1309 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 1, 0) node _T_1310 = shr(io.in.a.bits.source, 2) node _T_1311 = eq(_T_1310, UInt<7>(0h40)) node _T_1312 = leq(UInt<1>(0h0), uncommonBits_84) node _T_1313 = and(_T_1311, _T_1312) node _T_1314 = leq(uncommonBits_84, UInt<2>(0h3)) node _T_1315 = and(_T_1313, _T_1314) node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0) node _T_1316 = shr(io.in.a.bits.source, 2) node _T_1317 = eq(_T_1316, UInt<7>(0h41)) node _T_1318 = leq(UInt<1>(0h0), uncommonBits_85) node _T_1319 = and(_T_1317, _T_1318) node _T_1320 = leq(uncommonBits_85, UInt<2>(0h3)) node _T_1321 = and(_T_1319, _T_1320) node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0) node _T_1322 = shr(io.in.a.bits.source, 2) node _T_1323 = eq(_T_1322, UInt<7>(0h42)) node _T_1324 = leq(UInt<1>(0h0), uncommonBits_86) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = leq(uncommonBits_86, UInt<2>(0h3)) node _T_1327 = and(_T_1325, _T_1326) node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0) node _T_1328 = shr(io.in.a.bits.source, 2) node _T_1329 = eq(_T_1328, UInt<7>(0h43)) node _T_1330 = leq(UInt<1>(0h0), uncommonBits_87) node _T_1331 = and(_T_1329, _T_1330) node _T_1332 = leq(uncommonBits_87, UInt<2>(0h3)) node _T_1333 = and(_T_1331, _T_1332) node _T_1334 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1335 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1336 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 4, 0) node _T_1337 = shr(io.in.a.bits.source, 5) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) node _T_1339 = leq(UInt<1>(0h0), uncommonBits_88) node _T_1340 = and(_T_1338, _T_1339) node _T_1341 = leq(uncommonBits_88, UInt<5>(0h1f)) node _T_1342 = and(_T_1340, _T_1341) node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 4, 0) node _T_1343 = shr(io.in.a.bits.source, 5) node _T_1344 = eq(_T_1343, UInt<1>(0h1)) node _T_1345 = leq(UInt<1>(0h0), uncommonBits_89) node _T_1346 = and(_T_1344, _T_1345) node _T_1347 = leq(uncommonBits_89, UInt<5>(0h1f)) node _T_1348 = and(_T_1346, _T_1347) node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_90 = bits(_uncommonBits_T_90, 4, 0) node _T_1349 = shr(io.in.a.bits.source, 5) node _T_1350 = eq(_T_1349, UInt<2>(0h2)) node _T_1351 = leq(UInt<1>(0h0), uncommonBits_90) node _T_1352 = and(_T_1350, _T_1351) node _T_1353 = leq(uncommonBits_90, UInt<5>(0h1f)) node _T_1354 = and(_T_1352, _T_1353) node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_91 = bits(_uncommonBits_T_91, 4, 0) node _T_1355 = shr(io.in.a.bits.source, 5) node _T_1356 = eq(_T_1355, UInt<2>(0h3)) node _T_1357 = leq(UInt<1>(0h0), uncommonBits_91) node _T_1358 = and(_T_1356, _T_1357) node _T_1359 = leq(uncommonBits_91, UInt<5>(0h1f)) node _T_1360 = and(_T_1358, _T_1359) node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_92 = bits(_uncommonBits_T_92, 4, 0) node _T_1361 = shr(io.in.a.bits.source, 5) node _T_1362 = eq(_T_1361, UInt<3>(0h4)) node _T_1363 = leq(UInt<1>(0h0), uncommonBits_92) node _T_1364 = and(_T_1362, _T_1363) node _T_1365 = leq(uncommonBits_92, UInt<5>(0h1f)) node _T_1366 = and(_T_1364, _T_1365) node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_93 = bits(_uncommonBits_T_93, 4, 0) node _T_1367 = shr(io.in.a.bits.source, 5) node _T_1368 = eq(_T_1367, UInt<3>(0h5)) node _T_1369 = leq(UInt<1>(0h0), uncommonBits_93) node _T_1370 = and(_T_1368, _T_1369) node _T_1371 = leq(uncommonBits_93, UInt<5>(0h1f)) node _T_1372 = and(_T_1370, _T_1371) node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0) node _T_1373 = shr(io.in.a.bits.source, 5) node _T_1374 = eq(_T_1373, UInt<3>(0h6)) node _T_1375 = leq(UInt<1>(0h0), uncommonBits_94) node _T_1376 = and(_T_1374, _T_1375) node _T_1377 = leq(uncommonBits_94, UInt<5>(0h1f)) node _T_1378 = and(_T_1376, _T_1377) node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0) node _T_1379 = shr(io.in.a.bits.source, 5) node _T_1380 = eq(_T_1379, UInt<3>(0h7)) node _T_1381 = leq(UInt<1>(0h0), uncommonBits_95) node _T_1382 = and(_T_1380, _T_1381) node _T_1383 = leq(uncommonBits_95, UInt<5>(0h1f)) node _T_1384 = and(_T_1382, _T_1383) node _T_1385 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1386 = or(_T_1309, _T_1315) node _T_1387 = or(_T_1386, _T_1321) node _T_1388 = or(_T_1387, _T_1327) node _T_1389 = or(_T_1388, _T_1333) node _T_1390 = or(_T_1389, _T_1334) node _T_1391 = or(_T_1390, _T_1335) node _T_1392 = or(_T_1391, _T_1336) node _T_1393 = or(_T_1392, _T_1342) node _T_1394 = or(_T_1393, _T_1348) node _T_1395 = or(_T_1394, _T_1354) node _T_1396 = or(_T_1395, _T_1360) node _T_1397 = or(_T_1396, _T_1366) node _T_1398 = or(_T_1397, _T_1372) node _T_1399 = or(_T_1398, _T_1378) node _T_1400 = or(_T_1399, _T_1384) node _T_1401 = or(_T_1400, _T_1385) node _T_1402 = and(_T_1308, _T_1401) node _T_1403 = or(UInt<1>(0h0), _T_1402) node _T_1404 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1405 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1406 = and(_T_1404, _T_1405) node _T_1407 = or(UInt<1>(0h0), _T_1406) node _T_1408 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1409 = cvt(_T_1408) node _T_1410 = and(_T_1409, asSInt(UInt<13>(0h1000))) node _T_1411 = asSInt(_T_1410) node _T_1412 = eq(_T_1411, asSInt(UInt<1>(0h0))) node _T_1413 = and(_T_1407, _T_1412) node _T_1414 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1415 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1416 = and(_T_1414, _T_1415) node _T_1417 = or(UInt<1>(0h0), _T_1416) node _T_1418 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1419 = cvt(_T_1418) node _T_1420 = and(_T_1419, asSInt(UInt<14>(0h2000))) node _T_1421 = asSInt(_T_1420) node _T_1422 = eq(_T_1421, asSInt(UInt<1>(0h0))) node _T_1423 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1424 = cvt(_T_1423) node _T_1425 = and(_T_1424, asSInt(UInt<18>(0h2f000))) node _T_1426 = asSInt(_T_1425) node _T_1427 = eq(_T_1426, asSInt(UInt<1>(0h0))) node _T_1428 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1429 = cvt(_T_1428) node _T_1430 = and(_T_1429, asSInt(UInt<17>(0h10000))) node _T_1431 = asSInt(_T_1430) node _T_1432 = eq(_T_1431, asSInt(UInt<1>(0h0))) node _T_1433 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1434 = cvt(_T_1433) node _T_1435 = and(_T_1434, asSInt(UInt<13>(0h1000))) node _T_1436 = asSInt(_T_1435) node _T_1437 = eq(_T_1436, asSInt(UInt<1>(0h0))) node _T_1438 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1439 = cvt(_T_1438) node _T_1440 = and(_T_1439, asSInt(UInt<27>(0h4000000))) node _T_1441 = asSInt(_T_1440) node _T_1442 = eq(_T_1441, asSInt(UInt<1>(0h0))) node _T_1443 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1444 = cvt(_T_1443) node _T_1445 = and(_T_1444, asSInt(UInt<13>(0h1000))) node _T_1446 = asSInt(_T_1445) node _T_1447 = eq(_T_1446, asSInt(UInt<1>(0h0))) node _T_1448 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1449 = cvt(_T_1448) node _T_1450 = and(_T_1449, asSInt(UInt<19>(0h40000))) node _T_1451 = asSInt(_T_1450) node _T_1452 = eq(_T_1451, asSInt(UInt<1>(0h0))) node _T_1453 = or(_T_1422, _T_1427) node _T_1454 = or(_T_1453, _T_1432) node _T_1455 = or(_T_1454, _T_1437) node _T_1456 = or(_T_1455, _T_1442) node _T_1457 = or(_T_1456, _T_1447) node _T_1458 = or(_T_1457, _T_1452) node _T_1459 = and(_T_1417, _T_1458) node _T_1460 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1461 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1462 = cvt(_T_1461) node _T_1463 = and(_T_1462, asSInt(UInt<17>(0h10000))) node _T_1464 = asSInt(_T_1463) node _T_1465 = eq(_T_1464, asSInt(UInt<1>(0h0))) node _T_1466 = and(_T_1460, _T_1465) node _T_1467 = or(UInt<1>(0h0), _T_1413) node _T_1468 = or(_T_1467, _T_1459) node _T_1469 = or(_T_1468, _T_1466) node _T_1470 = and(_T_1403, _T_1469) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_31 node _T_1474 = asUInt(reset) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) when _T_1475 : node _T_1476 = eq(source_ok, UInt<1>(0h0)) when _T_1476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1477 = asUInt(reset) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) when _T_1478 : node _T_1479 = eq(is_aligned, UInt<1>(0h0)) when _T_1479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1480 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1481 = asUInt(reset) node _T_1482 = eq(_T_1481, UInt<1>(0h0)) when _T_1482 : node _T_1483 = eq(_T_1480, UInt<1>(0h0)) when _T_1483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1480, UInt<1>(0h1), "") : assert_34 node _T_1484 = not(mask) node _T_1485 = and(io.in.a.bits.mask, _T_1484) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) node _T_1487 = asUInt(reset) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) when _T_1488 : node _T_1489 = eq(_T_1486, UInt<1>(0h0)) when _T_1489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1486, UInt<1>(0h1), "") : assert_35 node _T_1490 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1490 : node _T_1491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1492 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_96 = bits(_uncommonBits_T_96, 1, 0) node _T_1495 = shr(io.in.a.bits.source, 2) node _T_1496 = eq(_T_1495, UInt<7>(0h40)) node _T_1497 = leq(UInt<1>(0h0), uncommonBits_96) node _T_1498 = and(_T_1496, _T_1497) node _T_1499 = leq(uncommonBits_96, UInt<2>(0h3)) node _T_1500 = and(_T_1498, _T_1499) node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_97 = bits(_uncommonBits_T_97, 1, 0) node _T_1501 = shr(io.in.a.bits.source, 2) node _T_1502 = eq(_T_1501, UInt<7>(0h41)) node _T_1503 = leq(UInt<1>(0h0), uncommonBits_97) node _T_1504 = and(_T_1502, _T_1503) node _T_1505 = leq(uncommonBits_97, UInt<2>(0h3)) node _T_1506 = and(_T_1504, _T_1505) node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_98 = bits(_uncommonBits_T_98, 1, 0) node _T_1507 = shr(io.in.a.bits.source, 2) node _T_1508 = eq(_T_1507, UInt<7>(0h42)) node _T_1509 = leq(UInt<1>(0h0), uncommonBits_98) node _T_1510 = and(_T_1508, _T_1509) node _T_1511 = leq(uncommonBits_98, UInt<2>(0h3)) node _T_1512 = and(_T_1510, _T_1511) node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_99 = bits(_uncommonBits_T_99, 1, 0) node _T_1513 = shr(io.in.a.bits.source, 2) node _T_1514 = eq(_T_1513, UInt<7>(0h43)) node _T_1515 = leq(UInt<1>(0h0), uncommonBits_99) node _T_1516 = and(_T_1514, _T_1515) node _T_1517 = leq(uncommonBits_99, UInt<2>(0h3)) node _T_1518 = and(_T_1516, _T_1517) node _T_1519 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1520 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1521 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_100 = bits(_uncommonBits_T_100, 4, 0) node _T_1522 = shr(io.in.a.bits.source, 5) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) node _T_1524 = leq(UInt<1>(0h0), uncommonBits_100) node _T_1525 = and(_T_1523, _T_1524) node _T_1526 = leq(uncommonBits_100, UInt<5>(0h1f)) node _T_1527 = and(_T_1525, _T_1526) node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_101 = bits(_uncommonBits_T_101, 4, 0) node _T_1528 = shr(io.in.a.bits.source, 5) node _T_1529 = eq(_T_1528, UInt<1>(0h1)) node _T_1530 = leq(UInt<1>(0h0), uncommonBits_101) node _T_1531 = and(_T_1529, _T_1530) node _T_1532 = leq(uncommonBits_101, UInt<5>(0h1f)) node _T_1533 = and(_T_1531, _T_1532) node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0) node _T_1534 = shr(io.in.a.bits.source, 5) node _T_1535 = eq(_T_1534, UInt<2>(0h2)) node _T_1536 = leq(UInt<1>(0h0), uncommonBits_102) node _T_1537 = and(_T_1535, _T_1536) node _T_1538 = leq(uncommonBits_102, UInt<5>(0h1f)) node _T_1539 = and(_T_1537, _T_1538) node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0) node _T_1540 = shr(io.in.a.bits.source, 5) node _T_1541 = eq(_T_1540, UInt<2>(0h3)) node _T_1542 = leq(UInt<1>(0h0), uncommonBits_103) node _T_1543 = and(_T_1541, _T_1542) node _T_1544 = leq(uncommonBits_103, UInt<5>(0h1f)) node _T_1545 = and(_T_1543, _T_1544) node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0) node _T_1546 = shr(io.in.a.bits.source, 5) node _T_1547 = eq(_T_1546, UInt<3>(0h4)) node _T_1548 = leq(UInt<1>(0h0), uncommonBits_104) node _T_1549 = and(_T_1547, _T_1548) node _T_1550 = leq(uncommonBits_104, UInt<5>(0h1f)) node _T_1551 = and(_T_1549, _T_1550) node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0) node _T_1552 = shr(io.in.a.bits.source, 5) node _T_1553 = eq(_T_1552, UInt<3>(0h5)) node _T_1554 = leq(UInt<1>(0h0), uncommonBits_105) node _T_1555 = and(_T_1553, _T_1554) node _T_1556 = leq(uncommonBits_105, UInt<5>(0h1f)) node _T_1557 = and(_T_1555, _T_1556) node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0) node _T_1558 = shr(io.in.a.bits.source, 5) node _T_1559 = eq(_T_1558, UInt<3>(0h6)) node _T_1560 = leq(UInt<1>(0h0), uncommonBits_106) node _T_1561 = and(_T_1559, _T_1560) node _T_1562 = leq(uncommonBits_106, UInt<5>(0h1f)) node _T_1563 = and(_T_1561, _T_1562) node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0) node _T_1564 = shr(io.in.a.bits.source, 5) node _T_1565 = eq(_T_1564, UInt<3>(0h7)) node _T_1566 = leq(UInt<1>(0h0), uncommonBits_107) node _T_1567 = and(_T_1565, _T_1566) node _T_1568 = leq(uncommonBits_107, UInt<5>(0h1f)) node _T_1569 = and(_T_1567, _T_1568) node _T_1570 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1571 = or(_T_1494, _T_1500) node _T_1572 = or(_T_1571, _T_1506) node _T_1573 = or(_T_1572, _T_1512) node _T_1574 = or(_T_1573, _T_1518) node _T_1575 = or(_T_1574, _T_1519) node _T_1576 = or(_T_1575, _T_1520) node _T_1577 = or(_T_1576, _T_1521) node _T_1578 = or(_T_1577, _T_1527) node _T_1579 = or(_T_1578, _T_1533) node _T_1580 = or(_T_1579, _T_1539) node _T_1581 = or(_T_1580, _T_1545) node _T_1582 = or(_T_1581, _T_1551) node _T_1583 = or(_T_1582, _T_1557) node _T_1584 = or(_T_1583, _T_1563) node _T_1585 = or(_T_1584, _T_1569) node _T_1586 = or(_T_1585, _T_1570) node _T_1587 = and(_T_1493, _T_1586) node _T_1588 = or(UInt<1>(0h0), _T_1587) node _T_1589 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1590 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1591 = and(_T_1589, _T_1590) node _T_1592 = or(UInt<1>(0h0), _T_1591) node _T_1593 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1594 = cvt(_T_1593) node _T_1595 = and(_T_1594, asSInt(UInt<15>(0h5000))) node _T_1596 = asSInt(_T_1595) node _T_1597 = eq(_T_1596, asSInt(UInt<1>(0h0))) node _T_1598 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1599 = cvt(_T_1598) node _T_1600 = and(_T_1599, asSInt(UInt<13>(0h1000))) node _T_1601 = asSInt(_T_1600) node _T_1602 = eq(_T_1601, asSInt(UInt<1>(0h0))) node _T_1603 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1604 = cvt(_T_1603) node _T_1605 = and(_T_1604, asSInt(UInt<19>(0h40000))) node _T_1606 = asSInt(_T_1605) node _T_1607 = eq(_T_1606, asSInt(UInt<1>(0h0))) node _T_1608 = or(_T_1597, _T_1602) node _T_1609 = or(_T_1608, _T_1607) node _T_1610 = and(_T_1592, _T_1609) node _T_1611 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1612 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1613 = cvt(_T_1612) node _T_1614 = and(_T_1613, asSInt(UInt<13>(0h1000))) node _T_1615 = asSInt(_T_1614) node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0))) node _T_1617 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1618 = cvt(_T_1617) node _T_1619 = and(_T_1618, asSInt(UInt<17>(0h10000))) node _T_1620 = asSInt(_T_1619) node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0))) node _T_1622 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1623 = cvt(_T_1622) node _T_1624 = and(_T_1623, asSInt(UInt<18>(0h2f000))) node _T_1625 = asSInt(_T_1624) node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0))) node _T_1627 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1628 = cvt(_T_1627) node _T_1629 = and(_T_1628, asSInt(UInt<17>(0h10000))) node _T_1630 = asSInt(_T_1629) node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0))) node _T_1632 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1633 = cvt(_T_1632) node _T_1634 = and(_T_1633, asSInt(UInt<13>(0h1000))) node _T_1635 = asSInt(_T_1634) node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0))) node _T_1637 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1638 = cvt(_T_1637) node _T_1639 = and(_T_1638, asSInt(UInt<27>(0h4000000))) node _T_1640 = asSInt(_T_1639) node _T_1641 = eq(_T_1640, asSInt(UInt<1>(0h0))) node _T_1642 = or(_T_1616, _T_1621) node _T_1643 = or(_T_1642, _T_1626) node _T_1644 = or(_T_1643, _T_1631) node _T_1645 = or(_T_1644, _T_1636) node _T_1646 = or(_T_1645, _T_1641) node _T_1647 = and(_T_1611, _T_1646) node _T_1648 = or(UInt<1>(0h0), _T_1610) node _T_1649 = or(_T_1648, _T_1647) node _T_1650 = and(_T_1588, _T_1649) node _T_1651 = asUInt(reset) node _T_1652 = eq(_T_1651, UInt<1>(0h0)) when _T_1652 : node _T_1653 = eq(_T_1650, UInt<1>(0h0)) when _T_1653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1650, UInt<1>(0h1), "") : assert_36 node _T_1654 = asUInt(reset) node _T_1655 = eq(_T_1654, UInt<1>(0h0)) when _T_1655 : node _T_1656 = eq(source_ok, UInt<1>(0h0)) when _T_1656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(is_aligned, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1660 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1661 = asUInt(reset) node _T_1662 = eq(_T_1661, UInt<1>(0h0)) when _T_1662 : node _T_1663 = eq(_T_1660, UInt<1>(0h0)) when _T_1663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1660, UInt<1>(0h1), "") : assert_39 node _T_1664 = eq(io.in.a.bits.mask, mask) node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(_T_1664, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1664, UInt<1>(0h1), "") : assert_40 node _T_1668 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1668 : node _T_1669 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1670 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1671 = and(_T_1669, _T_1670) node _T_1672 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_108 = bits(_uncommonBits_T_108, 1, 0) node _T_1673 = shr(io.in.a.bits.source, 2) node _T_1674 = eq(_T_1673, UInt<7>(0h40)) node _T_1675 = leq(UInt<1>(0h0), uncommonBits_108) node _T_1676 = and(_T_1674, _T_1675) node _T_1677 = leq(uncommonBits_108, UInt<2>(0h3)) node _T_1678 = and(_T_1676, _T_1677) node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_109 = bits(_uncommonBits_T_109, 1, 0) node _T_1679 = shr(io.in.a.bits.source, 2) node _T_1680 = eq(_T_1679, UInt<7>(0h41)) node _T_1681 = leq(UInt<1>(0h0), uncommonBits_109) node _T_1682 = and(_T_1680, _T_1681) node _T_1683 = leq(uncommonBits_109, UInt<2>(0h3)) node _T_1684 = and(_T_1682, _T_1683) node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0) node _T_1685 = shr(io.in.a.bits.source, 2) node _T_1686 = eq(_T_1685, UInt<7>(0h42)) node _T_1687 = leq(UInt<1>(0h0), uncommonBits_110) node _T_1688 = and(_T_1686, _T_1687) node _T_1689 = leq(uncommonBits_110, UInt<2>(0h3)) node _T_1690 = and(_T_1688, _T_1689) node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0) node _T_1691 = shr(io.in.a.bits.source, 2) node _T_1692 = eq(_T_1691, UInt<7>(0h43)) node _T_1693 = leq(UInt<1>(0h0), uncommonBits_111) node _T_1694 = and(_T_1692, _T_1693) node _T_1695 = leq(uncommonBits_111, UInt<2>(0h3)) node _T_1696 = and(_T_1694, _T_1695) node _T_1697 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1698 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1699 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_112 = bits(_uncommonBits_T_112, 4, 0) node _T_1700 = shr(io.in.a.bits.source, 5) node _T_1701 = eq(_T_1700, UInt<1>(0h0)) node _T_1702 = leq(UInt<1>(0h0), uncommonBits_112) node _T_1703 = and(_T_1701, _T_1702) node _T_1704 = leq(uncommonBits_112, UInt<5>(0h1f)) node _T_1705 = and(_T_1703, _T_1704) node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_113 = bits(_uncommonBits_T_113, 4, 0) node _T_1706 = shr(io.in.a.bits.source, 5) node _T_1707 = eq(_T_1706, UInt<1>(0h1)) node _T_1708 = leq(UInt<1>(0h0), uncommonBits_113) node _T_1709 = and(_T_1707, _T_1708) node _T_1710 = leq(uncommonBits_113, UInt<5>(0h1f)) node _T_1711 = and(_T_1709, _T_1710) node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_114 = bits(_uncommonBits_T_114, 4, 0) node _T_1712 = shr(io.in.a.bits.source, 5) node _T_1713 = eq(_T_1712, UInt<2>(0h2)) node _T_1714 = leq(UInt<1>(0h0), uncommonBits_114) node _T_1715 = and(_T_1713, _T_1714) node _T_1716 = leq(uncommonBits_114, UInt<5>(0h1f)) node _T_1717 = and(_T_1715, _T_1716) node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_115 = bits(_uncommonBits_T_115, 4, 0) node _T_1718 = shr(io.in.a.bits.source, 5) node _T_1719 = eq(_T_1718, UInt<2>(0h3)) node _T_1720 = leq(UInt<1>(0h0), uncommonBits_115) node _T_1721 = and(_T_1719, _T_1720) node _T_1722 = leq(uncommonBits_115, UInt<5>(0h1f)) node _T_1723 = and(_T_1721, _T_1722) node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0) node _T_1724 = shr(io.in.a.bits.source, 5) node _T_1725 = eq(_T_1724, UInt<3>(0h4)) node _T_1726 = leq(UInt<1>(0h0), uncommonBits_116) node _T_1727 = and(_T_1725, _T_1726) node _T_1728 = leq(uncommonBits_116, UInt<5>(0h1f)) node _T_1729 = and(_T_1727, _T_1728) node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0) node _T_1730 = shr(io.in.a.bits.source, 5) node _T_1731 = eq(_T_1730, UInt<3>(0h5)) node _T_1732 = leq(UInt<1>(0h0), uncommonBits_117) node _T_1733 = and(_T_1731, _T_1732) node _T_1734 = leq(uncommonBits_117, UInt<5>(0h1f)) node _T_1735 = and(_T_1733, _T_1734) node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0) node _T_1736 = shr(io.in.a.bits.source, 5) node _T_1737 = eq(_T_1736, UInt<3>(0h6)) node _T_1738 = leq(UInt<1>(0h0), uncommonBits_118) node _T_1739 = and(_T_1737, _T_1738) node _T_1740 = leq(uncommonBits_118, UInt<5>(0h1f)) node _T_1741 = and(_T_1739, _T_1740) node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0) node _T_1742 = shr(io.in.a.bits.source, 5) node _T_1743 = eq(_T_1742, UInt<3>(0h7)) node _T_1744 = leq(UInt<1>(0h0), uncommonBits_119) node _T_1745 = and(_T_1743, _T_1744) node _T_1746 = leq(uncommonBits_119, UInt<5>(0h1f)) node _T_1747 = and(_T_1745, _T_1746) node _T_1748 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1749 = or(_T_1672, _T_1678) node _T_1750 = or(_T_1749, _T_1684) node _T_1751 = or(_T_1750, _T_1690) node _T_1752 = or(_T_1751, _T_1696) node _T_1753 = or(_T_1752, _T_1697) node _T_1754 = or(_T_1753, _T_1698) node _T_1755 = or(_T_1754, _T_1699) node _T_1756 = or(_T_1755, _T_1705) node _T_1757 = or(_T_1756, _T_1711) node _T_1758 = or(_T_1757, _T_1717) node _T_1759 = or(_T_1758, _T_1723) node _T_1760 = or(_T_1759, _T_1729) node _T_1761 = or(_T_1760, _T_1735) node _T_1762 = or(_T_1761, _T_1741) node _T_1763 = or(_T_1762, _T_1747) node _T_1764 = or(_T_1763, _T_1748) node _T_1765 = and(_T_1671, _T_1764) node _T_1766 = or(UInt<1>(0h0), _T_1765) node _T_1767 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1768 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1769 = and(_T_1767, _T_1768) node _T_1770 = or(UInt<1>(0h0), _T_1769) node _T_1771 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1772 = cvt(_T_1771) node _T_1773 = and(_T_1772, asSInt(UInt<15>(0h5000))) node _T_1774 = asSInt(_T_1773) node _T_1775 = eq(_T_1774, asSInt(UInt<1>(0h0))) node _T_1776 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1777 = cvt(_T_1776) node _T_1778 = and(_T_1777, asSInt(UInt<13>(0h1000))) node _T_1779 = asSInt(_T_1778) node _T_1780 = eq(_T_1779, asSInt(UInt<1>(0h0))) node _T_1781 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1782 = cvt(_T_1781) node _T_1783 = and(_T_1782, asSInt(UInt<19>(0h40000))) node _T_1784 = asSInt(_T_1783) node _T_1785 = eq(_T_1784, asSInt(UInt<1>(0h0))) node _T_1786 = or(_T_1775, _T_1780) node _T_1787 = or(_T_1786, _T_1785) node _T_1788 = and(_T_1770, _T_1787) node _T_1789 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1790 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1791 = cvt(_T_1790) node _T_1792 = and(_T_1791, asSInt(UInt<13>(0h1000))) node _T_1793 = asSInt(_T_1792) node _T_1794 = eq(_T_1793, asSInt(UInt<1>(0h0))) node _T_1795 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1796 = cvt(_T_1795) node _T_1797 = and(_T_1796, asSInt(UInt<17>(0h10000))) node _T_1798 = asSInt(_T_1797) node _T_1799 = eq(_T_1798, asSInt(UInt<1>(0h0))) node _T_1800 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1801 = cvt(_T_1800) node _T_1802 = and(_T_1801, asSInt(UInt<18>(0h2f000))) node _T_1803 = asSInt(_T_1802) node _T_1804 = eq(_T_1803, asSInt(UInt<1>(0h0))) node _T_1805 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1806 = cvt(_T_1805) node _T_1807 = and(_T_1806, asSInt(UInt<17>(0h10000))) node _T_1808 = asSInt(_T_1807) node _T_1809 = eq(_T_1808, asSInt(UInt<1>(0h0))) node _T_1810 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1811 = cvt(_T_1810) node _T_1812 = and(_T_1811, asSInt(UInt<13>(0h1000))) node _T_1813 = asSInt(_T_1812) node _T_1814 = eq(_T_1813, asSInt(UInt<1>(0h0))) node _T_1815 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1816 = cvt(_T_1815) node _T_1817 = and(_T_1816, asSInt(UInt<27>(0h4000000))) node _T_1818 = asSInt(_T_1817) node _T_1819 = eq(_T_1818, asSInt(UInt<1>(0h0))) node _T_1820 = or(_T_1794, _T_1799) node _T_1821 = or(_T_1820, _T_1804) node _T_1822 = or(_T_1821, _T_1809) node _T_1823 = or(_T_1822, _T_1814) node _T_1824 = or(_T_1823, _T_1819) node _T_1825 = and(_T_1789, _T_1824) node _T_1826 = or(UInt<1>(0h0), _T_1788) node _T_1827 = or(_T_1826, _T_1825) node _T_1828 = and(_T_1766, _T_1827) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_41 node _T_1832 = asUInt(reset) node _T_1833 = eq(_T_1832, UInt<1>(0h0)) when _T_1833 : node _T_1834 = eq(source_ok, UInt<1>(0h0)) when _T_1834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1835 = asUInt(reset) node _T_1836 = eq(_T_1835, UInt<1>(0h0)) when _T_1836 : node _T_1837 = eq(is_aligned, UInt<1>(0h0)) when _T_1837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1839 = asUInt(reset) node _T_1840 = eq(_T_1839, UInt<1>(0h0)) when _T_1840 : node _T_1841 = eq(_T_1838, UInt<1>(0h0)) when _T_1841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1838, UInt<1>(0h1), "") : assert_44 node _T_1842 = eq(io.in.a.bits.mask, mask) node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(_T_1842, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1842, UInt<1>(0h1), "") : assert_45 node _T_1846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1846 : node _T_1847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1849 = and(_T_1847, _T_1848) node _T_1850 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_120 = bits(_uncommonBits_T_120, 1, 0) node _T_1851 = shr(io.in.a.bits.source, 2) node _T_1852 = eq(_T_1851, UInt<7>(0h40)) node _T_1853 = leq(UInt<1>(0h0), uncommonBits_120) node _T_1854 = and(_T_1852, _T_1853) node _T_1855 = leq(uncommonBits_120, UInt<2>(0h3)) node _T_1856 = and(_T_1854, _T_1855) node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_121 = bits(_uncommonBits_T_121, 1, 0) node _T_1857 = shr(io.in.a.bits.source, 2) node _T_1858 = eq(_T_1857, UInt<7>(0h41)) node _T_1859 = leq(UInt<1>(0h0), uncommonBits_121) node _T_1860 = and(_T_1858, _T_1859) node _T_1861 = leq(uncommonBits_121, UInt<2>(0h3)) node _T_1862 = and(_T_1860, _T_1861) node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0) node _T_1863 = shr(io.in.a.bits.source, 2) node _T_1864 = eq(_T_1863, UInt<7>(0h42)) node _T_1865 = leq(UInt<1>(0h0), uncommonBits_122) node _T_1866 = and(_T_1864, _T_1865) node _T_1867 = leq(uncommonBits_122, UInt<2>(0h3)) node _T_1868 = and(_T_1866, _T_1867) node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0) node _T_1869 = shr(io.in.a.bits.source, 2) node _T_1870 = eq(_T_1869, UInt<7>(0h43)) node _T_1871 = leq(UInt<1>(0h0), uncommonBits_123) node _T_1872 = and(_T_1870, _T_1871) node _T_1873 = leq(uncommonBits_123, UInt<2>(0h3)) node _T_1874 = and(_T_1872, _T_1873) node _T_1875 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1876 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1877 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0) node _T_1878 = shr(io.in.a.bits.source, 5) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) node _T_1880 = leq(UInt<1>(0h0), uncommonBits_124) node _T_1881 = and(_T_1879, _T_1880) node _T_1882 = leq(uncommonBits_124, UInt<5>(0h1f)) node _T_1883 = and(_T_1881, _T_1882) node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0) node _T_1884 = shr(io.in.a.bits.source, 5) node _T_1885 = eq(_T_1884, UInt<1>(0h1)) node _T_1886 = leq(UInt<1>(0h0), uncommonBits_125) node _T_1887 = and(_T_1885, _T_1886) node _T_1888 = leq(uncommonBits_125, UInt<5>(0h1f)) node _T_1889 = and(_T_1887, _T_1888) node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0) node _T_1890 = shr(io.in.a.bits.source, 5) node _T_1891 = eq(_T_1890, UInt<2>(0h2)) node _T_1892 = leq(UInt<1>(0h0), uncommonBits_126) node _T_1893 = and(_T_1891, _T_1892) node _T_1894 = leq(uncommonBits_126, UInt<5>(0h1f)) node _T_1895 = and(_T_1893, _T_1894) node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0) node _T_1896 = shr(io.in.a.bits.source, 5) node _T_1897 = eq(_T_1896, UInt<2>(0h3)) node _T_1898 = leq(UInt<1>(0h0), uncommonBits_127) node _T_1899 = and(_T_1897, _T_1898) node _T_1900 = leq(uncommonBits_127, UInt<5>(0h1f)) node _T_1901 = and(_T_1899, _T_1900) node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0) node _T_1902 = shr(io.in.a.bits.source, 5) node _T_1903 = eq(_T_1902, UInt<3>(0h4)) node _T_1904 = leq(UInt<1>(0h0), uncommonBits_128) node _T_1905 = and(_T_1903, _T_1904) node _T_1906 = leq(uncommonBits_128, UInt<5>(0h1f)) node _T_1907 = and(_T_1905, _T_1906) node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0) node _T_1908 = shr(io.in.a.bits.source, 5) node _T_1909 = eq(_T_1908, UInt<3>(0h5)) node _T_1910 = leq(UInt<1>(0h0), uncommonBits_129) node _T_1911 = and(_T_1909, _T_1910) node _T_1912 = leq(uncommonBits_129, UInt<5>(0h1f)) node _T_1913 = and(_T_1911, _T_1912) node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0) node _T_1914 = shr(io.in.a.bits.source, 5) node _T_1915 = eq(_T_1914, UInt<3>(0h6)) node _T_1916 = leq(UInt<1>(0h0), uncommonBits_130) node _T_1917 = and(_T_1915, _T_1916) node _T_1918 = leq(uncommonBits_130, UInt<5>(0h1f)) node _T_1919 = and(_T_1917, _T_1918) node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0) node _T_1920 = shr(io.in.a.bits.source, 5) node _T_1921 = eq(_T_1920, UInt<3>(0h7)) node _T_1922 = leq(UInt<1>(0h0), uncommonBits_131) node _T_1923 = and(_T_1921, _T_1922) node _T_1924 = leq(uncommonBits_131, UInt<5>(0h1f)) node _T_1925 = and(_T_1923, _T_1924) node _T_1926 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1927 = or(_T_1850, _T_1856) node _T_1928 = or(_T_1927, _T_1862) node _T_1929 = or(_T_1928, _T_1868) node _T_1930 = or(_T_1929, _T_1874) node _T_1931 = or(_T_1930, _T_1875) node _T_1932 = or(_T_1931, _T_1876) node _T_1933 = or(_T_1932, _T_1877) node _T_1934 = or(_T_1933, _T_1883) node _T_1935 = or(_T_1934, _T_1889) node _T_1936 = or(_T_1935, _T_1895) node _T_1937 = or(_T_1936, _T_1901) node _T_1938 = or(_T_1937, _T_1907) node _T_1939 = or(_T_1938, _T_1913) node _T_1940 = or(_T_1939, _T_1919) node _T_1941 = or(_T_1940, _T_1925) node _T_1942 = or(_T_1941, _T_1926) node _T_1943 = and(_T_1849, _T_1942) node _T_1944 = or(UInt<1>(0h0), _T_1943) node _T_1945 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1946 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1947 = and(_T_1945, _T_1946) node _T_1948 = or(UInt<1>(0h0), _T_1947) node _T_1949 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1950 = cvt(_T_1949) node _T_1951 = and(_T_1950, asSInt(UInt<13>(0h1000))) node _T_1952 = asSInt(_T_1951) node _T_1953 = eq(_T_1952, asSInt(UInt<1>(0h0))) node _T_1954 = and(_T_1948, _T_1953) node _T_1955 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1956 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1957 = cvt(_T_1956) node _T_1958 = and(_T_1957, asSInt(UInt<14>(0h2000))) node _T_1959 = asSInt(_T_1958) node _T_1960 = eq(_T_1959, asSInt(UInt<1>(0h0))) node _T_1961 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1962 = cvt(_T_1961) node _T_1963 = and(_T_1962, asSInt(UInt<17>(0h10000))) node _T_1964 = asSInt(_T_1963) node _T_1965 = eq(_T_1964, asSInt(UInt<1>(0h0))) node _T_1966 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1967 = cvt(_T_1966) node _T_1968 = and(_T_1967, asSInt(UInt<18>(0h2f000))) node _T_1969 = asSInt(_T_1968) node _T_1970 = eq(_T_1969, asSInt(UInt<1>(0h0))) node _T_1971 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1972 = cvt(_T_1971) node _T_1973 = and(_T_1972, asSInt(UInt<17>(0h10000))) node _T_1974 = asSInt(_T_1973) node _T_1975 = eq(_T_1974, asSInt(UInt<1>(0h0))) node _T_1976 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1977 = cvt(_T_1976) node _T_1978 = and(_T_1977, asSInt(UInt<13>(0h1000))) node _T_1979 = asSInt(_T_1978) node _T_1980 = eq(_T_1979, asSInt(UInt<1>(0h0))) node _T_1981 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1982 = cvt(_T_1981) node _T_1983 = and(_T_1982, asSInt(UInt<27>(0h4000000))) node _T_1984 = asSInt(_T_1983) node _T_1985 = eq(_T_1984, asSInt(UInt<1>(0h0))) node _T_1986 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1987 = cvt(_T_1986) node _T_1988 = and(_T_1987, asSInt(UInt<13>(0h1000))) node _T_1989 = asSInt(_T_1988) node _T_1990 = eq(_T_1989, asSInt(UInt<1>(0h0))) node _T_1991 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1992 = cvt(_T_1991) node _T_1993 = and(_T_1992, asSInt(UInt<19>(0h40000))) node _T_1994 = asSInt(_T_1993) node _T_1995 = eq(_T_1994, asSInt(UInt<1>(0h0))) node _T_1996 = or(_T_1960, _T_1965) node _T_1997 = or(_T_1996, _T_1970) node _T_1998 = or(_T_1997, _T_1975) node _T_1999 = or(_T_1998, _T_1980) node _T_2000 = or(_T_1999, _T_1985) node _T_2001 = or(_T_2000, _T_1990) node _T_2002 = or(_T_2001, _T_1995) node _T_2003 = and(_T_1955, _T_2002) node _T_2004 = or(UInt<1>(0h0), _T_1954) node _T_2005 = or(_T_2004, _T_2003) node _T_2006 = and(_T_1944, _T_2005) node _T_2007 = asUInt(reset) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) when _T_2008 : node _T_2009 = eq(_T_2006, UInt<1>(0h0)) when _T_2009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_2006, UInt<1>(0h1), "") : assert_46 node _T_2010 = asUInt(reset) node _T_2011 = eq(_T_2010, UInt<1>(0h0)) when _T_2011 : node _T_2012 = eq(source_ok, UInt<1>(0h0)) when _T_2012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(is_aligned, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_2016 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_2017 = asUInt(reset) node _T_2018 = eq(_T_2017, UInt<1>(0h0)) when _T_2018 : node _T_2019 = eq(_T_2016, UInt<1>(0h0)) when _T_2019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_2016, UInt<1>(0h1), "") : assert_49 node _T_2020 = eq(io.in.a.bits.mask, mask) node _T_2021 = asUInt(reset) node _T_2022 = eq(_T_2021, UInt<1>(0h0)) when _T_2022 : node _T_2023 = eq(_T_2020, UInt<1>(0h0)) when _T_2023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_2020, UInt<1>(0h1), "") : assert_50 node _T_2024 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_2025 = asUInt(reset) node _T_2026 = eq(_T_2025, UInt<1>(0h0)) when _T_2026 : node _T_2027 = eq(_T_2024, UInt<1>(0h0)) when _T_2027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_2024, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_2028 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2029 = asUInt(reset) node _T_2030 = eq(_T_2029, UInt<1>(0h0)) when _T_2030 : node _T_2031 = eq(_T_2028, UInt<1>(0h0)) when _T_2031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_2028, UInt<1>(0h1), "") : assert_52 node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<9>(0h110)) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_93 = shr(io.in.d.bits.source, 2) node _source_ok_T_94 = eq(_source_ok_T_93, UInt<7>(0h40)) node _source_ok_T_95 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_T_97 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_99 = shr(io.in.d.bits.source, 2) node _source_ok_T_100 = eq(_source_ok_T_99, UInt<7>(0h41)) node _source_ok_T_101 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_T_103 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103) node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 1, 0) node _source_ok_T_105 = shr(io.in.d.bits.source, 2) node _source_ok_T_106 = eq(_source_ok_T_105, UInt<7>(0h42)) node _source_ok_T_107 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_T_109 = leq(source_ok_uncommonBits_14, UInt<2>(0h3)) node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109) node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 1, 0) node _source_ok_T_111 = shr(io.in.d.bits.source, 2) node _source_ok_T_112 = eq(_source_ok_T_111, UInt<7>(0h43)) node _source_ok_T_113 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_T_115 = leq(source_ok_uncommonBits_15, UInt<2>(0h3)) node _source_ok_T_116 = and(_source_ok_T_114, _source_ok_T_115) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<9>(0h120)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<9>(0h121)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<9>(0h122)) node _source_ok_uncommonBits_T_16 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0) node _source_ok_T_120 = shr(io.in.d.bits.source, 5) node _source_ok_T_121 = eq(_source_ok_T_120, UInt<1>(0h0)) node _source_ok_T_122 = leq(UInt<1>(0h0), source_ok_uncommonBits_16) node _source_ok_T_123 = and(_source_ok_T_121, _source_ok_T_122) node _source_ok_T_124 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f)) node _source_ok_T_125 = and(_source_ok_T_123, _source_ok_T_124) node _source_ok_uncommonBits_T_17 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0) node _source_ok_T_126 = shr(io.in.d.bits.source, 5) node _source_ok_T_127 = eq(_source_ok_T_126, UInt<1>(0h1)) node _source_ok_T_128 = leq(UInt<1>(0h0), source_ok_uncommonBits_17) node _source_ok_T_129 = and(_source_ok_T_127, _source_ok_T_128) node _source_ok_T_130 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f)) node _source_ok_T_131 = and(_source_ok_T_129, _source_ok_T_130) node _source_ok_uncommonBits_T_18 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0) node _source_ok_T_132 = shr(io.in.d.bits.source, 5) node _source_ok_T_133 = eq(_source_ok_T_132, UInt<2>(0h2)) node _source_ok_T_134 = leq(UInt<1>(0h0), source_ok_uncommonBits_18) node _source_ok_T_135 = and(_source_ok_T_133, _source_ok_T_134) node _source_ok_T_136 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f)) node _source_ok_T_137 = and(_source_ok_T_135, _source_ok_T_136) node _source_ok_uncommonBits_T_19 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0) node _source_ok_T_138 = shr(io.in.d.bits.source, 5) node _source_ok_T_139 = eq(_source_ok_T_138, UInt<2>(0h3)) node _source_ok_T_140 = leq(UInt<1>(0h0), source_ok_uncommonBits_19) node _source_ok_T_141 = and(_source_ok_T_139, _source_ok_T_140) node _source_ok_T_142 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f)) node _source_ok_T_143 = and(_source_ok_T_141, _source_ok_T_142) node _source_ok_uncommonBits_T_20 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0) node _source_ok_T_144 = shr(io.in.d.bits.source, 5) node _source_ok_T_145 = eq(_source_ok_T_144, UInt<3>(0h4)) node _source_ok_T_146 = leq(UInt<1>(0h0), source_ok_uncommonBits_20) node _source_ok_T_147 = and(_source_ok_T_145, _source_ok_T_146) node _source_ok_T_148 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f)) node _source_ok_T_149 = and(_source_ok_T_147, _source_ok_T_148) node _source_ok_uncommonBits_T_21 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0) node _source_ok_T_150 = shr(io.in.d.bits.source, 5) node _source_ok_T_151 = eq(_source_ok_T_150, UInt<3>(0h5)) node _source_ok_T_152 = leq(UInt<1>(0h0), source_ok_uncommonBits_21) node _source_ok_T_153 = and(_source_ok_T_151, _source_ok_T_152) node _source_ok_T_154 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f)) node _source_ok_T_155 = and(_source_ok_T_153, _source_ok_T_154) node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 4, 0) node _source_ok_T_156 = shr(io.in.d.bits.source, 5) node _source_ok_T_157 = eq(_source_ok_T_156, UInt<3>(0h6)) node _source_ok_T_158 = leq(UInt<1>(0h0), source_ok_uncommonBits_22) node _source_ok_T_159 = and(_source_ok_T_157, _source_ok_T_158) node _source_ok_T_160 = leq(source_ok_uncommonBits_22, UInt<5>(0h1f)) node _source_ok_T_161 = and(_source_ok_T_159, _source_ok_T_160) node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 4, 0) node _source_ok_T_162 = shr(io.in.d.bits.source, 5) node _source_ok_T_163 = eq(_source_ok_T_162, UInt<3>(0h7)) node _source_ok_T_164 = leq(UInt<1>(0h0), source_ok_uncommonBits_23) node _source_ok_T_165 = and(_source_ok_T_163, _source_ok_T_164) node _source_ok_T_166 = leq(source_ok_uncommonBits_23, UInt<5>(0h1f)) node _source_ok_T_167 = and(_source_ok_T_165, _source_ok_T_166) node _source_ok_T_168 = eq(io.in.d.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE_1 : UInt<1>[17] connect _source_ok_WIRE_1[0], _source_ok_T_92 connect _source_ok_WIRE_1[1], _source_ok_T_98 connect _source_ok_WIRE_1[2], _source_ok_T_104 connect _source_ok_WIRE_1[3], _source_ok_T_110 connect _source_ok_WIRE_1[4], _source_ok_T_116 connect _source_ok_WIRE_1[5], _source_ok_T_117 connect _source_ok_WIRE_1[6], _source_ok_T_118 connect _source_ok_WIRE_1[7], _source_ok_T_119 connect _source_ok_WIRE_1[8], _source_ok_T_125 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_137 connect _source_ok_WIRE_1[11], _source_ok_T_143 connect _source_ok_WIRE_1[12], _source_ok_T_149 connect _source_ok_WIRE_1[13], _source_ok_T_155 connect _source_ok_WIRE_1[14], _source_ok_T_161 connect _source_ok_WIRE_1[15], _source_ok_T_167 connect _source_ok_WIRE_1[16], _source_ok_T_168 node _source_ok_T_169 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[2]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[3]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[4]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[5]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[6]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[7]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[8]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[9]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[10]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[11]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[12]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[13]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[14]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[15]) node source_ok_1 = or(_source_ok_T_183, _source_ok_WIRE_1[16]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_2032 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_2032 : node _T_2033 = asUInt(reset) node _T_2034 = eq(_T_2033, UInt<1>(0h0)) when _T_2034 : node _T_2035 = eq(source_ok_1, UInt<1>(0h0)) when _T_2035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_2036 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(_T_2036, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_2036, UInt<1>(0h1), "") : assert_54 node _T_2040 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2041 = asUInt(reset) node _T_2042 = eq(_T_2041, UInt<1>(0h0)) when _T_2042 : node _T_2043 = eq(_T_2040, UInt<1>(0h0)) when _T_2043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_2040, UInt<1>(0h1), "") : assert_55 node _T_2044 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2045 = asUInt(reset) node _T_2046 = eq(_T_2045, UInt<1>(0h0)) when _T_2046 : node _T_2047 = eq(_T_2044, UInt<1>(0h0)) when _T_2047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_2044, UInt<1>(0h1), "") : assert_56 node _T_2048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2049 = asUInt(reset) node _T_2050 = eq(_T_2049, UInt<1>(0h0)) when _T_2050 : node _T_2051 = eq(_T_2048, UInt<1>(0h0)) when _T_2051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_2048, UInt<1>(0h1), "") : assert_57 node _T_2052 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_2052 : node _T_2053 = asUInt(reset) node _T_2054 = eq(_T_2053, UInt<1>(0h0)) when _T_2054 : node _T_2055 = eq(source_ok_1, UInt<1>(0h0)) when _T_2055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_2056 = asUInt(reset) node _T_2057 = eq(_T_2056, UInt<1>(0h0)) when _T_2057 : node _T_2058 = eq(sink_ok, UInt<1>(0h0)) when _T_2058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_2059 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2060 = asUInt(reset) node _T_2061 = eq(_T_2060, UInt<1>(0h0)) when _T_2061 : node _T_2062 = eq(_T_2059, UInt<1>(0h0)) when _T_2062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_2059, UInt<1>(0h1), "") : assert_60 node _T_2063 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2064 = asUInt(reset) node _T_2065 = eq(_T_2064, UInt<1>(0h0)) when _T_2065 : node _T_2066 = eq(_T_2063, UInt<1>(0h0)) when _T_2066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_2063, UInt<1>(0h1), "") : assert_61 node _T_2067 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2068 = asUInt(reset) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) when _T_2069 : node _T_2070 = eq(_T_2067, UInt<1>(0h0)) when _T_2070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_2067, UInt<1>(0h1), "") : assert_62 node _T_2071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2072 = asUInt(reset) node _T_2073 = eq(_T_2072, UInt<1>(0h0)) when _T_2073 : node _T_2074 = eq(_T_2071, UInt<1>(0h0)) when _T_2074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_2071, UInt<1>(0h1), "") : assert_63 node _T_2075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2076 = or(UInt<1>(0h1), _T_2075) node _T_2077 = asUInt(reset) node _T_2078 = eq(_T_2077, UInt<1>(0h0)) when _T_2078 : node _T_2079 = eq(_T_2076, UInt<1>(0h0)) when _T_2079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_2076, UInt<1>(0h1), "") : assert_64 node _T_2080 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_2080 : node _T_2081 = asUInt(reset) node _T_2082 = eq(_T_2081, UInt<1>(0h0)) when _T_2082 : node _T_2083 = eq(source_ok_1, UInt<1>(0h0)) when _T_2083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_2084 = asUInt(reset) node _T_2085 = eq(_T_2084, UInt<1>(0h0)) when _T_2085 : node _T_2086 = eq(sink_ok, UInt<1>(0h0)) when _T_2086 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_2087 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2088 = asUInt(reset) node _T_2089 = eq(_T_2088, UInt<1>(0h0)) when _T_2089 : node _T_2090 = eq(_T_2087, UInt<1>(0h0)) when _T_2090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_2087, UInt<1>(0h1), "") : assert_67 node _T_2091 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2092 = asUInt(reset) node _T_2093 = eq(_T_2092, UInt<1>(0h0)) when _T_2093 : node _T_2094 = eq(_T_2091, UInt<1>(0h0)) when _T_2094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_2091, UInt<1>(0h1), "") : assert_68 node _T_2095 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2096 = asUInt(reset) node _T_2097 = eq(_T_2096, UInt<1>(0h0)) when _T_2097 : node _T_2098 = eq(_T_2095, UInt<1>(0h0)) when _T_2098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_2095, UInt<1>(0h1), "") : assert_69 node _T_2099 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2100 = or(_T_2099, io.in.d.bits.corrupt) node _T_2101 = asUInt(reset) node _T_2102 = eq(_T_2101, UInt<1>(0h0)) when _T_2102 : node _T_2103 = eq(_T_2100, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_2100, UInt<1>(0h1), "") : assert_70 node _T_2104 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2105 = or(UInt<1>(0h1), _T_2104) node _T_2106 = asUInt(reset) node _T_2107 = eq(_T_2106, UInt<1>(0h0)) when _T_2107 : node _T_2108 = eq(_T_2105, UInt<1>(0h0)) when _T_2108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_2105, UInt<1>(0h1), "") : assert_71 node _T_2109 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_2109 : node _T_2110 = asUInt(reset) node _T_2111 = eq(_T_2110, UInt<1>(0h0)) when _T_2111 : node _T_2112 = eq(source_ok_1, UInt<1>(0h0)) when _T_2112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_2113 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2114 = asUInt(reset) node _T_2115 = eq(_T_2114, UInt<1>(0h0)) when _T_2115 : node _T_2116 = eq(_T_2113, UInt<1>(0h0)) when _T_2116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_2113, UInt<1>(0h1), "") : assert_73 node _T_2117 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2118 = asUInt(reset) node _T_2119 = eq(_T_2118, UInt<1>(0h0)) when _T_2119 : node _T_2120 = eq(_T_2117, UInt<1>(0h0)) when _T_2120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_2117, UInt<1>(0h1), "") : assert_74 node _T_2121 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2122 = or(UInt<1>(0h1), _T_2121) node _T_2123 = asUInt(reset) node _T_2124 = eq(_T_2123, UInt<1>(0h0)) when _T_2124 : node _T_2125 = eq(_T_2122, UInt<1>(0h0)) when _T_2125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_2122, UInt<1>(0h1), "") : assert_75 node _T_2126 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_2126 : node _T_2127 = asUInt(reset) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) when _T_2128 : node _T_2129 = eq(source_ok_1, UInt<1>(0h0)) when _T_2129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_2130 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2131 = asUInt(reset) node _T_2132 = eq(_T_2131, UInt<1>(0h0)) when _T_2132 : node _T_2133 = eq(_T_2130, UInt<1>(0h0)) when _T_2133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_2130, UInt<1>(0h1), "") : assert_77 node _T_2134 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2135 = or(_T_2134, io.in.d.bits.corrupt) node _T_2136 = asUInt(reset) node _T_2137 = eq(_T_2136, UInt<1>(0h0)) when _T_2137 : node _T_2138 = eq(_T_2135, UInt<1>(0h0)) when _T_2138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_2135, UInt<1>(0h1), "") : assert_78 node _T_2139 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2140 = or(UInt<1>(0h1), _T_2139) node _T_2141 = asUInt(reset) node _T_2142 = eq(_T_2141, UInt<1>(0h0)) when _T_2142 : node _T_2143 = eq(_T_2140, UInt<1>(0h0)) when _T_2143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_2140, UInt<1>(0h1), "") : assert_79 node _T_2144 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_2144 : node _T_2145 = asUInt(reset) node _T_2146 = eq(_T_2145, UInt<1>(0h0)) when _T_2146 : node _T_2147 = eq(source_ok_1, UInt<1>(0h0)) when _T_2147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2148 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2149 = asUInt(reset) node _T_2150 = eq(_T_2149, UInt<1>(0h0)) when _T_2150 : node _T_2151 = eq(_T_2148, UInt<1>(0h0)) when _T_2151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2148, UInt<1>(0h1), "") : assert_81 node _T_2152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2153 = asUInt(reset) node _T_2154 = eq(_T_2153, UInt<1>(0h0)) when _T_2154 : node _T_2155 = eq(_T_2152, UInt<1>(0h0)) when _T_2155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2152, UInt<1>(0h1), "") : assert_82 node _T_2156 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2157 = or(UInt<1>(0h1), _T_2156) node _T_2158 = asUInt(reset) node _T_2159 = eq(_T_2158, UInt<1>(0h0)) when _T_2159 : node _T_2160 = eq(_T_2157, UInt<1>(0h0)) when _T_2160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2157, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<10>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2161 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(_T_2161, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2161, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<10>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2165 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2166 = asUInt(reset) node _T_2167 = eq(_T_2166, UInt<1>(0h0)) when _T_2167 : node _T_2168 = eq(_T_2165, UInt<1>(0h0)) when _T_2168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2165, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2169 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2170 = asUInt(reset) node _T_2171 = eq(_T_2170, UInt<1>(0h0)) when _T_2171 : node _T_2172 = eq(_T_2169, UInt<1>(0h0)) when _T_2172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2169, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2173 = eq(a_first, UInt<1>(0h0)) node _T_2174 = and(io.in.a.valid, _T_2173) when _T_2174 : node _T_2175 = eq(io.in.a.bits.opcode, opcode) node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(_T_2175, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2175, UInt<1>(0h1), "") : assert_87 node _T_2179 = eq(io.in.a.bits.param, param) node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(_T_2179, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2179, UInt<1>(0h1), "") : assert_88 node _T_2183 = eq(io.in.a.bits.size, size) node _T_2184 = asUInt(reset) node _T_2185 = eq(_T_2184, UInt<1>(0h0)) when _T_2185 : node _T_2186 = eq(_T_2183, UInt<1>(0h0)) when _T_2186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2183, UInt<1>(0h1), "") : assert_89 node _T_2187 = eq(io.in.a.bits.source, source) node _T_2188 = asUInt(reset) node _T_2189 = eq(_T_2188, UInt<1>(0h0)) when _T_2189 : node _T_2190 = eq(_T_2187, UInt<1>(0h0)) when _T_2190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2187, UInt<1>(0h1), "") : assert_90 node _T_2191 = eq(io.in.a.bits.address, address) node _T_2192 = asUInt(reset) node _T_2193 = eq(_T_2192, UInt<1>(0h0)) when _T_2193 : node _T_2194 = eq(_T_2191, UInt<1>(0h0)) when _T_2194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2191, UInt<1>(0h1), "") : assert_91 node _T_2195 = and(io.in.a.ready, io.in.a.valid) node _T_2196 = and(_T_2195, a_first) when _T_2196 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2197 = eq(d_first, UInt<1>(0h0)) node _T_2198 = and(io.in.d.valid, _T_2197) when _T_2198 : node _T_2199 = eq(io.in.d.bits.opcode, opcode_1) node _T_2200 = asUInt(reset) node _T_2201 = eq(_T_2200, UInt<1>(0h0)) when _T_2201 : node _T_2202 = eq(_T_2199, UInt<1>(0h0)) when _T_2202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2199, UInt<1>(0h1), "") : assert_92 node _T_2203 = eq(io.in.d.bits.param, param_1) node _T_2204 = asUInt(reset) node _T_2205 = eq(_T_2204, UInt<1>(0h0)) when _T_2205 : node _T_2206 = eq(_T_2203, UInt<1>(0h0)) when _T_2206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2203, UInt<1>(0h1), "") : assert_93 node _T_2207 = eq(io.in.d.bits.size, size_1) node _T_2208 = asUInt(reset) node _T_2209 = eq(_T_2208, UInt<1>(0h0)) when _T_2209 : node _T_2210 = eq(_T_2207, UInt<1>(0h0)) when _T_2210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2207, UInt<1>(0h1), "") : assert_94 node _T_2211 = eq(io.in.d.bits.source, source_1) node _T_2212 = asUInt(reset) node _T_2213 = eq(_T_2212, UInt<1>(0h0)) when _T_2213 : node _T_2214 = eq(_T_2211, UInt<1>(0h0)) when _T_2214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2211, UInt<1>(0h1), "") : assert_95 node _T_2215 = eq(io.in.d.bits.sink, sink) node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(_T_2215, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2215, UInt<1>(0h1), "") : assert_96 node _T_2219 = eq(io.in.d.bits.denied, denied) node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(_T_2219, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2219, UInt<1>(0h1), "") : assert_97 node _T_2223 = and(io.in.d.ready, io.in.d.valid) node _T_2224 = and(_T_2223, d_first) when _T_2224 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes : UInt<4104>, clock, reset, UInt<4104>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<513> connect a_set, UInt<513>(0h0) wire a_set_wo_ready : UInt<513> connect a_set_wo_ready, UInt<513>(0h0) wire a_opcodes_set : UInt<2052> connect a_opcodes_set, UInt<2052>(0h0) wire a_sizes_set : UInt<4104> connect a_sizes_set, UInt<4104>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2225 = and(io.in.a.valid, a_first_1) node _T_2226 = and(_T_2225, UInt<1>(0h1)) when _T_2226 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2227 = and(io.in.a.ready, io.in.a.valid) node _T_2228 = and(_T_2227, a_first_1) node _T_2229 = and(_T_2228, UInt<1>(0h1)) when _T_2229 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2230 = dshr(inflight, io.in.a.bits.source) node _T_2231 = bits(_T_2230, 0, 0) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) node _T_2233 = asUInt(reset) node _T_2234 = eq(_T_2233, UInt<1>(0h0)) when _T_2234 : node _T_2235 = eq(_T_2232, UInt<1>(0h0)) when _T_2235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2232, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<513> connect d_clr, UInt<513>(0h0) wire d_clr_wo_ready : UInt<513> connect d_clr_wo_ready, UInt<513>(0h0) wire d_opcodes_clr : UInt<2052> connect d_opcodes_clr, UInt<2052>(0h0) wire d_sizes_clr : UInt<4104> connect d_sizes_clr, UInt<4104>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2236 = and(io.in.d.valid, d_first_1) node _T_2237 = and(_T_2236, UInt<1>(0h1)) node _T_2238 = eq(d_release_ack, UInt<1>(0h0)) node _T_2239 = and(_T_2237, _T_2238) when _T_2239 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2240 = and(io.in.d.ready, io.in.d.valid) node _T_2241 = and(_T_2240, d_first_1) node _T_2242 = and(_T_2241, UInt<1>(0h1)) node _T_2243 = eq(d_release_ack, UInt<1>(0h0)) node _T_2244 = and(_T_2242, _T_2243) when _T_2244 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2245 = and(io.in.d.valid, d_first_1) node _T_2246 = and(_T_2245, UInt<1>(0h1)) node _T_2247 = eq(d_release_ack, UInt<1>(0h0)) node _T_2248 = and(_T_2246, _T_2247) when _T_2248 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2249 = dshr(inflight, io.in.d.bits.source) node _T_2250 = bits(_T_2249, 0, 0) node _T_2251 = or(_T_2250, same_cycle_resp) node _T_2252 = asUInt(reset) node _T_2253 = eq(_T_2252, UInt<1>(0h0)) when _T_2253 : node _T_2254 = eq(_T_2251, UInt<1>(0h0)) when _T_2254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2251, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2255 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2256 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2257 = or(_T_2255, _T_2256) node _T_2258 = asUInt(reset) node _T_2259 = eq(_T_2258, UInt<1>(0h0)) when _T_2259 : node _T_2260 = eq(_T_2257, UInt<1>(0h0)) when _T_2260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2257, UInt<1>(0h1), "") : assert_100 node _T_2261 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2262 = asUInt(reset) node _T_2263 = eq(_T_2262, UInt<1>(0h0)) when _T_2263 : node _T_2264 = eq(_T_2261, UInt<1>(0h0)) when _T_2264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2261, UInt<1>(0h1), "") : assert_101 else : node _T_2265 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2266 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2267 = or(_T_2265, _T_2266) node _T_2268 = asUInt(reset) node _T_2269 = eq(_T_2268, UInt<1>(0h0)) when _T_2269 : node _T_2270 = eq(_T_2267, UInt<1>(0h0)) when _T_2270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2267, UInt<1>(0h1), "") : assert_102 node _T_2271 = eq(io.in.d.bits.size, a_size_lookup) node _T_2272 = asUInt(reset) node _T_2273 = eq(_T_2272, UInt<1>(0h0)) when _T_2273 : node _T_2274 = eq(_T_2271, UInt<1>(0h0)) when _T_2274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2271, UInt<1>(0h1), "") : assert_103 node _T_2275 = and(io.in.d.valid, d_first_1) node _T_2276 = and(_T_2275, a_first_1) node _T_2277 = and(_T_2276, io.in.a.valid) node _T_2278 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2279 = and(_T_2277, _T_2278) node _T_2280 = eq(d_release_ack, UInt<1>(0h0)) node _T_2281 = and(_T_2279, _T_2280) when _T_2281 : node _T_2282 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2283 = or(_T_2282, io.in.a.ready) node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : node _T_2286 = eq(_T_2283, UInt<1>(0h0)) when _T_2286 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2283, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_42 node _T_2287 = orr(inflight) node _T_2288 = eq(_T_2287, UInt<1>(0h0)) node _T_2289 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2290 = or(_T_2288, _T_2289) node _T_2291 = lt(watchdog, plusarg_reader.out) node _T_2292 = or(_T_2290, _T_2291) node _T_2293 = asUInt(reset) node _T_2294 = eq(_T_2293, UInt<1>(0h0)) when _T_2294 : node _T_2295 = eq(_T_2292, UInt<1>(0h0)) when _T_2295 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2292, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2296 = and(io.in.a.ready, io.in.a.valid) node _T_2297 = and(io.in.d.ready, io.in.d.valid) node _T_2298 = or(_T_2296, _T_2297) when _T_2298 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes_1 : UInt<4104>, clock, reset, UInt<4104>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<10>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<10>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<513> connect c_set, UInt<513>(0h0) wire c_set_wo_ready : UInt<513> connect c_set_wo_ready, UInt<513>(0h0) wire c_opcodes_set : UInt<2052> connect c_opcodes_set, UInt<2052>(0h0) wire c_sizes_set : UInt<4104> connect c_sizes_set, UInt<4104>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<10>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2299 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<10>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2300 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2301 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2302 = and(_T_2300, _T_2301) node _T_2303 = and(_T_2299, _T_2302) when _T_2303 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<10>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<10>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2304 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2305 = and(_T_2304, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<10>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2306 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2307 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2308 = and(_T_2306, _T_2307) node _T_2309 = and(_T_2305, _T_2308) when _T_2309 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<10>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<10>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2310 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2311 = bits(_T_2310, 0, 0) node _T_2312 = eq(_T_2311, UInt<1>(0h0)) node _T_2313 = asUInt(reset) node _T_2314 = eq(_T_2313, UInt<1>(0h0)) when _T_2314 : node _T_2315 = eq(_T_2312, UInt<1>(0h0)) when _T_2315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2312, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<513> connect d_clr_1, UInt<513>(0h0) wire d_clr_wo_ready_1 : UInt<513> connect d_clr_wo_ready_1, UInt<513>(0h0) wire d_opcodes_clr_1 : UInt<2052> connect d_opcodes_clr_1, UInt<2052>(0h0) wire d_sizes_clr_1 : UInt<4104> connect d_sizes_clr_1, UInt<4104>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2316 = and(io.in.d.valid, d_first_2) node _T_2317 = and(_T_2316, UInt<1>(0h1)) node _T_2318 = and(_T_2317, d_release_ack_1) when _T_2318 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2319 = and(io.in.d.ready, io.in.d.valid) node _T_2320 = and(_T_2319, d_first_2) node _T_2321 = and(_T_2320, UInt<1>(0h1)) node _T_2322 = and(_T_2321, d_release_ack_1) when _T_2322 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2323 = and(io.in.d.valid, d_first_2) node _T_2324 = and(_T_2323, UInt<1>(0h1)) node _T_2325 = and(_T_2324, d_release_ack_1) when _T_2325 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2326 = dshr(inflight_1, io.in.d.bits.source) node _T_2327 = bits(_T_2326, 0, 0) node _T_2328 = or(_T_2327, same_cycle_resp_1) node _T_2329 = asUInt(reset) node _T_2330 = eq(_T_2329, UInt<1>(0h0)) when _T_2330 : node _T_2331 = eq(_T_2328, UInt<1>(0h0)) when _T_2331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2328, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<10>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2332 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2333 = asUInt(reset) node _T_2334 = eq(_T_2333, UInt<1>(0h0)) when _T_2334 : node _T_2335 = eq(_T_2332, UInt<1>(0h0)) when _T_2335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2332, UInt<1>(0h1), "") : assert_108 else : node _T_2336 = eq(io.in.d.bits.size, c_size_lookup) node _T_2337 = asUInt(reset) node _T_2338 = eq(_T_2337, UInt<1>(0h0)) when _T_2338 : node _T_2339 = eq(_T_2336, UInt<1>(0h0)) when _T_2339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2336, UInt<1>(0h1), "") : assert_109 node _T_2340 = and(io.in.d.valid, d_first_2) node _T_2341 = and(_T_2340, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<10>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2342 = and(_T_2341, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<10>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2343 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2344 = and(_T_2342, _T_2343) node _T_2345 = and(_T_2344, d_release_ack_1) node _T_2346 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2347 = and(_T_2345, _T_2346) when _T_2347 : node _T_2348 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<10>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2349 = or(_T_2348, _WIRE_27.ready) node _T_2350 = asUInt(reset) node _T_2351 = eq(_T_2350, UInt<1>(0h0)) when _T_2351 : node _T_2352 = eq(_T_2349, UInt<1>(0h0)) when _T_2352 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2349, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_43 node _T_2353 = orr(inflight_1) node _T_2354 = eq(_T_2353, UInt<1>(0h0)) node _T_2355 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2356 = or(_T_2354, _T_2355) node _T_2357 = lt(watchdog_1, plusarg_reader_1.out) node _T_2358 = or(_T_2356, _T_2357) node _T_2359 = asUInt(reset) node _T_2360 = eq(_T_2359, UInt<1>(0h0)) when _T_2360 : node _T_2361 = eq(_T_2358, UInt<1>(0h0)) when _T_2361 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:61:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2358, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<10>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2362 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2363 = and(io.in.d.ready, io.in.d.valid) node _T_2364 = or(_T_2362, _T_2363) when _T_2364 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_21( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [9:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [9:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [512:0] inflight; // @[Monitor.scala:614:27] reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4103:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Monitor.scala:36:7] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Monitor.scala:36:7] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [512:0] inflight_1; // @[Monitor.scala:726:35] reg [4103:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Monitor.scala:36:7] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFMToRaw_small_e11_s53_3 : input clock : Clock input reset : Reset output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}} inst divSqrtRawFN of DivSqrtRawFN_small_e11_s53_3 connect divSqrtRawFN.clock, clock connect divSqrtRawFN.reset, reset connect io.inReady, divSqrtRawFN.io.inReady connect divSqrtRawFN.io.inValid, io.inValid connect divSqrtRawFN.io.sqrtOp, io.sqrtOp node divSqrtRawFN_io_a_exp = bits(io.a, 63, 52) node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 11, 9) node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 11, 10) node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 9, 9) node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T) connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1 node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 9, 9) node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1) connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2 connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 64, 64) connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp) connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T) node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 51, 0) node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2) connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3 connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN node divSqrtRawFN_io_b_exp = bits(io.b, 63, 52) node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 11, 9) node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 11, 10) node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 9, 9) node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T) connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1 node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 9, 9) node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1) connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2 connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 64, 64) connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp) connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T) node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 51, 0) node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2) connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3 connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN connect divSqrtRawFN.io.roundingMode, io.roundingMode connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut connect io.invalidExc, divSqrtRawFN.io.invalidExc connect io.infiniteExc, divSqrtRawFN.io.infiniteExc connect io.rawOut, divSqrtRawFN.io.rawOut
module DivSqrtRecFMToRaw_small_e11_s53_3( // @[DivSqrtRecFN_small.scala:422:5] input clock, // @[DivSqrtRecFN_small.scala:422:5] input reset, // @[DivSqrtRecFN_small.scala:422:5] output io_inReady, // @[DivSqrtRecFN_small.scala:426:16] input io_inValid, // @[DivSqrtRecFN_small.scala:426:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:426:16] input [64:0] io_a, // @[DivSqrtRecFN_small.scala:426:16] input [64:0] io_b, // @[DivSqrtRecFN_small.scala:426:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:426:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:426:16] output io_invalidExc, // @[DivSqrtRecFN_small.scala:426:16] output io_infiniteExc, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:426:16] output [12:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:426:16] output [55:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:426:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:422:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:422:5] wire [64:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:422:5] wire [64:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] wire [12:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] wire [55:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire [11:0] divSqrtRawFN_io_a_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_a_isZero_T = divSqrtRawFN_io_a_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_a_isZero = _divSqrtRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_a_out_isZero = divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_a_isSpecial_T = divSqrtRawFN_io_a_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_a_isSpecial = &_divSqrtRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] divSqrtRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] divSqrtRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_a_out_isNaN_T = divSqrtRawFN_io_a_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_a_out_isInf_T = divSqrtRawFN_io_a_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_a_out_isNaN_T_1 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_a_out_isNaN = _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_a_out_isInf_T_1 = ~_divSqrtRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_a_out_isInf_T_2 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_a_out_isInf = _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_a_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_a_out_sign = _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_a_out_sExp_T = {1'h0, divSqrtRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_a_out_sExp = _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_a_out_sig_T = ~divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_a_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _divSqrtRawFN_io_a_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_a_out_sig_T_3 = {_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_a_out_sig = _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [11:0] divSqrtRawFN_io_b_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_b_isZero_T = divSqrtRawFN_io_b_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_b_isZero = _divSqrtRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_b_out_isZero = divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_b_isSpecial_T = divSqrtRawFN_io_b_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_b_isSpecial = &_divSqrtRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] divSqrtRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] divSqrtRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_b_out_isNaN_T = divSqrtRawFN_io_b_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_b_out_isInf_T = divSqrtRawFN_io_b_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_b_out_isNaN_T_1 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_b_out_isNaN = _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_b_out_isInf_T_1 = ~_divSqrtRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_b_out_isInf_T_2 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_b_out_isInf = _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_b_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_b_out_sign = _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_b_out_sExp_T = {1'h0, divSqrtRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_b_out_sExp = _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_b_out_sig_T = ~divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_b_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _divSqrtRawFN_io_b_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_b_out_sig_T_3 = {_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_b_out_sig = _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] DivSqrtRawFN_small_e11_s53_3 divSqrtRawFN ( // @[DivSqrtRecFN_small.scala:446:15] .clock (clock), .reset (reset), .io_inReady (io_inReady_0), .io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:422:5] .io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:422:5] .io_a_isNaN (divSqrtRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (divSqrtRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (divSqrtRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (divSqrtRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (divSqrtRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (divSqrtRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (divSqrtRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (divSqrtRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (divSqrtRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (divSqrtRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (divSqrtRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (divSqrtRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:422:5] .io_rawOutValid_div (io_rawOutValid_div_0), .io_rawOutValid_sqrt (io_rawOutValid_sqrt_0), .io_roundingModeOut (io_roundingModeOut_0), .io_invalidExc (io_invalidExc_0), .io_infiniteExc (io_infiniteExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (io_rawOut_sig_0) ); // @[DivSqrtRecFN_small.scala:446:15] assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_80 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_80( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_70 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_33 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_34 = and(_T_32, _T_33) node _T_35 = or(UInt<1>(0h0), _T_34) node _T_36 = xor(io.in.a.bits.address, UInt<28>(0h8000100)) node _T_37 = cvt(_T_36) node _T_38 = and(_T_37, asSInt(UInt<17>(0h101c0))) node _T_39 = asSInt(_T_38) node _T_40 = eq(_T_39, asSInt(UInt<1>(0h0))) node _T_41 = xor(io.in.a.bits.address, UInt<32>(0h80000100)) node _T_42 = cvt(_T_41) node _T_43 = and(_T_42, asSInt(UInt<29>(0h100001c0))) node _T_44 = asSInt(_T_43) node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0))) node _T_46 = or(_T_40, _T_45) node _T_47 = and(_T_35, _T_46) node _T_48 = or(UInt<1>(0h0), _T_47) node _T_49 = and(_T_31, _T_48) node _T_50 = asUInt(reset) node _T_51 = eq(_T_50, UInt<1>(0h0)) when _T_51 : node _T_52 = eq(_T_49, UInt<1>(0h0)) when _T_52 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_49, UInt<1>(0h1), "") : assert_2 node _T_53 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_54 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_55 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_56 = and(_T_54, _T_55) node _T_57 = or(UInt<1>(0h0), _T_56) node _T_58 = xor(io.in.a.bits.address, UInt<28>(0h8000100)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<17>(0h101c0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<32>(0h80000100)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<29>(0h100001c0))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_62, _T_67) node _T_69 = and(_T_57, _T_68) node _T_70 = or(UInt<1>(0h0), _T_69) node _T_71 = and(_T_53, _T_70) node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(_T_71, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_71, UInt<1>(0h1), "") : assert_3 node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_78 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_78, UInt<1>(0h1), "") : assert_5 node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(is_aligned, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_85 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_85, UInt<1>(0h1), "") : assert_7 node _T_89 = not(io.in.a.bits.mask) node _T_90 = eq(_T_89, UInt<1>(0h0)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_90, UInt<1>(0h1), "") : assert_8 node _T_94 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_94, UInt<1>(0h1), "") : assert_9 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_102 = shr(io.in.a.bits.source, 4) node _T_103 = eq(_T_102, UInt<1>(0h0)) node _T_104 = leq(UInt<1>(0h0), uncommonBits_2) node _T_105 = and(_T_103, _T_104) node _T_106 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_107 = and(_T_105, _T_106) node _T_108 = and(_T_101, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_111 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_112 = and(_T_110, _T_111) node _T_113 = or(UInt<1>(0h0), _T_112) node _T_114 = xor(io.in.a.bits.address, UInt<28>(0h8000100)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<17>(0h101c0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = xor(io.in.a.bits.address, UInt<32>(0h80000100)) node _T_120 = cvt(_T_119) node _T_121 = and(_T_120, asSInt(UInt<29>(0h100001c0))) node _T_122 = asSInt(_T_121) node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = or(_T_118, _T_123) node _T_125 = and(_T_113, _T_124) node _T_126 = or(UInt<1>(0h0), _T_125) node _T_127 = and(_T_109, _T_126) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_127, UInt<1>(0h1), "") : assert_10 node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_132 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_133 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_134 = and(_T_132, _T_133) node _T_135 = or(UInt<1>(0h0), _T_134) node _T_136 = xor(io.in.a.bits.address, UInt<28>(0h8000100)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h101c0))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<32>(0h80000100)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<29>(0h100001c0))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = or(_T_140, _T_145) node _T_147 = and(_T_135, _T_146) node _T_148 = or(UInt<1>(0h0), _T_147) node _T_149 = and(_T_131, _T_148) node _T_150 = asUInt(reset) node _T_151 = eq(_T_150, UInt<1>(0h0)) when _T_151 : node _T_152 = eq(_T_149, UInt<1>(0h0)) when _T_152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_149, UInt<1>(0h1), "") : assert_11 node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_156 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_156, UInt<1>(0h1), "") : assert_13 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(is_aligned, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_163 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_163, UInt<1>(0h1), "") : assert_15 node _T_167 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_168 = asUInt(reset) node _T_169 = eq(_T_168, UInt<1>(0h0)) when _T_169 : node _T_170 = eq(_T_167, UInt<1>(0h0)) when _T_170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_167, UInt<1>(0h1), "") : assert_16 node _T_171 = not(io.in.a.bits.mask) node _T_172 = eq(_T_171, UInt<1>(0h0)) node _T_173 = asUInt(reset) node _T_174 = eq(_T_173, UInt<1>(0h0)) when _T_174 : node _T_175 = eq(_T_172, UInt<1>(0h0)) when _T_175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_172, UInt<1>(0h1), "") : assert_17 node _T_176 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_176, UInt<1>(0h1), "") : assert_18 node _T_180 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_180 : node _T_181 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_182 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_183 = and(_T_181, _T_182) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_184 = shr(io.in.a.bits.source, 4) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = leq(UInt<1>(0h0), uncommonBits_3) node _T_187 = and(_T_185, _T_186) node _T_188 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_189 = and(_T_187, _T_188) node _T_190 = and(_T_183, _T_189) node _T_191 = or(UInt<1>(0h0), _T_190) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_191, UInt<1>(0h1), "") : assert_19 node _T_195 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_196 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_197 = and(_T_195, _T_196) node _T_198 = or(UInt<1>(0h0), _T_197) node _T_199 = xor(io.in.a.bits.address, UInt<28>(0h8000100)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<17>(0h101c0))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<32>(0h80000100)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<29>(0h100001c0))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_203, _T_208) node _T_210 = and(_T_198, _T_209) node _T_211 = or(UInt<1>(0h0), _T_210) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_211, UInt<1>(0h1), "") : assert_20 node _T_215 = asUInt(reset) node _T_216 = eq(_T_215, UInt<1>(0h0)) when _T_216 : node _T_217 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_218 = asUInt(reset) node _T_219 = eq(_T_218, UInt<1>(0h0)) when _T_219 : node _T_220 = eq(is_aligned, UInt<1>(0h0)) when _T_220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_221 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_221, UInt<1>(0h1), "") : assert_23 node _T_225 = eq(io.in.a.bits.mask, mask) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_225, UInt<1>(0h1), "") : assert_24 node _T_229 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_229, UInt<1>(0h1), "") : assert_25 node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_233 : node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_237 = shr(io.in.a.bits.source, 4) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_4) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_242 = and(_T_240, _T_241) node _T_243 = and(_T_236, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_246 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_247 = and(_T_245, _T_246) node _T_248 = or(UInt<1>(0h0), _T_247) node _T_249 = xor(io.in.a.bits.address, UInt<28>(0h8000100)) node _T_250 = cvt(_T_249) node _T_251 = and(_T_250, asSInt(UInt<17>(0h101c0))) node _T_252 = asSInt(_T_251) node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0))) node _T_254 = xor(io.in.a.bits.address, UInt<32>(0h80000100)) node _T_255 = cvt(_T_254) node _T_256 = and(_T_255, asSInt(UInt<29>(0h100001c0))) node _T_257 = asSInt(_T_256) node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0))) node _T_259 = or(_T_253, _T_258) node _T_260 = and(_T_248, _T_259) node _T_261 = or(UInt<1>(0h0), _T_260) node _T_262 = and(_T_244, _T_261) node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_T_262, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_262, UInt<1>(0h1), "") : assert_26 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(is_aligned, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_272 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_273 = asUInt(reset) node _T_274 = eq(_T_273, UInt<1>(0h0)) when _T_274 : node _T_275 = eq(_T_272, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_272, UInt<1>(0h1), "") : assert_29 node _T_276 = eq(io.in.a.bits.mask, mask) node _T_277 = asUInt(reset) node _T_278 = eq(_T_277, UInt<1>(0h0)) when _T_278 : node _T_279 = eq(_T_276, UInt<1>(0h0)) when _T_279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_276, UInt<1>(0h1), "") : assert_30 node _T_280 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_280 : node _T_281 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_282 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_284 = shr(io.in.a.bits.source, 4) node _T_285 = eq(_T_284, UInt<1>(0h0)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_5) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_289 = and(_T_287, _T_288) node _T_290 = and(_T_283, _T_289) node _T_291 = or(UInt<1>(0h0), _T_290) node _T_292 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_293 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_294 = and(_T_292, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000100)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h101c0))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000100)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h100001c0))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_307) node _T_309 = and(_T_291, _T_308) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_309, UInt<1>(0h1), "") : assert_31 node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(is_aligned, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_319 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_320 = asUInt(reset) node _T_321 = eq(_T_320, UInt<1>(0h0)) when _T_321 : node _T_322 = eq(_T_319, UInt<1>(0h0)) when _T_322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_319, UInt<1>(0h1), "") : assert_34 node _T_323 = not(mask) node _T_324 = and(io.in.a.bits.mask, _T_323) node _T_325 = eq(_T_324, UInt<1>(0h0)) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_325, UInt<1>(0h1), "") : assert_35 node _T_329 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_329 : node _T_330 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_331 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_332 = and(_T_330, _T_331) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_333 = shr(io.in.a.bits.source, 4) node _T_334 = eq(_T_333, UInt<1>(0h0)) node _T_335 = leq(UInt<1>(0h0), uncommonBits_6) node _T_336 = and(_T_334, _T_335) node _T_337 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_338 = and(_T_336, _T_337) node _T_339 = and(_T_332, _T_338) node _T_340 = or(UInt<1>(0h0), _T_339) node _T_341 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_342 = xor(io.in.a.bits.address, UInt<28>(0h8000100)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<17>(0h101c0))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<32>(0h80000100)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<29>(0h100001c0))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = or(_T_346, _T_351) node _T_353 = and(_T_341, _T_352) node _T_354 = or(UInt<1>(0h0), _T_353) node _T_355 = and(_T_340, _T_354) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_355, UInt<1>(0h1), "") : assert_36 node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(is_aligned, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_365 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(_T_365, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_365, UInt<1>(0h1), "") : assert_39 node _T_369 = eq(io.in.a.bits.mask, mask) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_369, UInt<1>(0h1), "") : assert_40 node _T_373 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_373 : node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_377 = shr(io.in.a.bits.source, 4) node _T_378 = eq(_T_377, UInt<1>(0h0)) node _T_379 = leq(UInt<1>(0h0), uncommonBits_7) node _T_380 = and(_T_378, _T_379) node _T_381 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_382 = and(_T_380, _T_381) node _T_383 = and(_T_376, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_386 = xor(io.in.a.bits.address, UInt<28>(0h8000100)) node _T_387 = cvt(_T_386) node _T_388 = and(_T_387, asSInt(UInt<17>(0h101c0))) node _T_389 = asSInt(_T_388) node _T_390 = eq(_T_389, asSInt(UInt<1>(0h0))) node _T_391 = xor(io.in.a.bits.address, UInt<32>(0h80000100)) node _T_392 = cvt(_T_391) node _T_393 = and(_T_392, asSInt(UInt<29>(0h100001c0))) node _T_394 = asSInt(_T_393) node _T_395 = eq(_T_394, asSInt(UInt<1>(0h0))) node _T_396 = or(_T_390, _T_395) node _T_397 = and(_T_385, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = and(_T_384, _T_398) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_399, UInt<1>(0h1), "") : assert_41 node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(is_aligned, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_409 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_409, UInt<1>(0h1), "") : assert_44 node _T_413 = eq(io.in.a.bits.mask, mask) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_413, UInt<1>(0h1), "") : assert_45 node _T_417 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_417 : node _T_418 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_419 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_421 = shr(io.in.a.bits.source, 4) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_8) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_426 = and(_T_424, _T_425) node _T_427 = and(_T_420, _T_426) node _T_428 = or(UInt<1>(0h0), _T_427) node _T_429 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_430 = xor(io.in.a.bits.address, UInt<28>(0h8000100)) node _T_431 = cvt(_T_430) node _T_432 = and(_T_431, asSInt(UInt<17>(0h101c0))) node _T_433 = asSInt(_T_432) node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0))) node _T_435 = xor(io.in.a.bits.address, UInt<32>(0h80000100)) node _T_436 = cvt(_T_435) node _T_437 = and(_T_436, asSInt(UInt<29>(0h100001c0))) node _T_438 = asSInt(_T_437) node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0))) node _T_440 = or(_T_434, _T_439) node _T_441 = and(_T_429, _T_440) node _T_442 = or(UInt<1>(0h0), _T_441) node _T_443 = and(_T_428, _T_442) node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_T_443, UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_443, UInt<1>(0h1), "") : assert_46 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(is_aligned, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_453 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_453, UInt<1>(0h1), "") : assert_49 node _T_457 = eq(io.in.a.bits.mask, mask) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_457, UInt<1>(0h1), "") : assert_50 node _T_461 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_461, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_465 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_465, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_469 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_469 : node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_473 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_473, UInt<1>(0h1), "") : assert_54 node _T_477 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_477, UInt<1>(0h1), "") : assert_55 node _T_481 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_481, UInt<1>(0h1), "") : assert_56 node _T_485 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_485, UInt<1>(0h1), "") : assert_57 node _T_489 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_489 : node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(sink_ok, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_496 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_496, UInt<1>(0h1), "") : assert_60 node _T_500 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_500, UInt<1>(0h1), "") : assert_61 node _T_504 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_504, UInt<1>(0h1), "") : assert_62 node _T_508 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_509 = asUInt(reset) node _T_510 = eq(_T_509, UInt<1>(0h0)) when _T_510 : node _T_511 = eq(_T_508, UInt<1>(0h0)) when _T_511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_508, UInt<1>(0h1), "") : assert_63 node _T_512 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_513 = or(UInt<1>(0h1), _T_512) node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_T_513, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_513, UInt<1>(0h1), "") : assert_64 node _T_517 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_517 : node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(sink_ok, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_524 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_524, UInt<1>(0h1), "") : assert_67 node _T_528 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_528, UInt<1>(0h1), "") : assert_68 node _T_532 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(_T_532, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_532, UInt<1>(0h1), "") : assert_69 node _T_536 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_537 = or(_T_536, io.in.d.bits.corrupt) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_537, UInt<1>(0h1), "") : assert_70 node _T_541 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_542 = or(UInt<1>(0h1), _T_541) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_542, UInt<1>(0h1), "") : assert_71 node _T_546 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_546 : node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_550 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_551 = asUInt(reset) node _T_552 = eq(_T_551, UInt<1>(0h0)) when _T_552 : node _T_553 = eq(_T_550, UInt<1>(0h0)) when _T_553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_550, UInt<1>(0h1), "") : assert_73 node _T_554 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(_T_554, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_554, UInt<1>(0h1), "") : assert_74 node _T_558 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_559 = or(UInt<1>(0h1), _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_559, UInt<1>(0h1), "") : assert_75 node _T_563 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_563 : node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_567 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_567, UInt<1>(0h1), "") : assert_77 node _T_571 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_572 = or(_T_571, io.in.d.bits.corrupt) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_572, UInt<1>(0h1), "") : assert_78 node _T_576 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_577 = or(UInt<1>(0h1), _T_576) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_577, UInt<1>(0h1), "") : assert_79 node _T_581 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_581 : node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_585 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_585, UInt<1>(0h1), "") : assert_81 node _T_589 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_590 = asUInt(reset) node _T_591 = eq(_T_590, UInt<1>(0h0)) when _T_591 : node _T_592 = eq(_T_589, UInt<1>(0h0)) when _T_592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_589, UInt<1>(0h1), "") : assert_82 node _T_593 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_594 = or(UInt<1>(0h1), _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_594, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_598 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(_T_598, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_598, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_9 = or(io.in.b.bits.source, UInt<4>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0) node _T_602 = shr(io.in.b.bits.source, 4) node _T_603 = eq(_T_602, UInt<1>(0h0)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_9) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_9, UInt<4>(0h9)) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(_T_607, UInt<1>(0h0)) node _T_609 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<1>(0h0))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_608, _T_613) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_614, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000100)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h101c0))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000100)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100001c0))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<4>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 3, 0) node _legal_source_T = shr(io.in.b.bits.source, 4) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<4>(0h9)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) wire _legal_source_WIRE : UInt<1>[1] connect _legal_source_WIRE[0], _legal_source_T_5 node legal_source = eq(UInt<1>(0h0), io.in.b.bits.source) node _T_618 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_618 : node _T_619 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_620 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_621 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_622 = and(_T_620, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = xor(io.in.b.bits.address, UInt<28>(0h8000100)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h101c0))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.b.bits.address, UInt<32>(0h80000100)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<29>(0h100001c0))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = or(_T_628, _T_633) node _T_635 = and(_T_623, _T_634) node _T_636 = or(UInt<1>(0h0), _T_635) node _T_637 = and(_T_619, _T_636) node _T_638 = asUInt(reset) node _T_639 = eq(_T_638, UInt<1>(0h0)) when _T_639 : node _T_640 = eq(_T_637, UInt<1>(0h0)) when _T_640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_637, UInt<1>(0h1), "") : assert_86 node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(address_ok, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(legal_source, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(is_aligned_1, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_650 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_650, UInt<1>(0h1), "") : assert_90 node _T_654 = eq(io.in.b.bits.mask, mask_1) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_654, UInt<1>(0h1), "") : assert_91 node _T_658 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_659 = asUInt(reset) node _T_660 = eq(_T_659, UInt<1>(0h0)) when _T_660 : node _T_661 = eq(_T_658, UInt<1>(0h0)) when _T_661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_658, UInt<1>(0h1), "") : assert_92 node _T_662 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_662 : node _T_663 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_664 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_665 = and(_T_663, _T_664) node _T_666 = or(UInt<1>(0h0), _T_665) node _T_667 = xor(io.in.b.bits.address, UInt<28>(0h8000100)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<17>(0h101c0))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = xor(io.in.b.bits.address, UInt<32>(0h80000100)) node _T_673 = cvt(_T_672) node _T_674 = and(_T_673, asSInt(UInt<29>(0h100001c0))) node _T_675 = asSInt(_T_674) node _T_676 = eq(_T_675, asSInt(UInt<1>(0h0))) node _T_677 = or(_T_671, _T_676) node _T_678 = and(_T_666, _T_677) node _T_679 = or(UInt<1>(0h0), _T_678) node _T_680 = and(UInt<1>(0h0), _T_679) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_680, UInt<1>(0h1), "") : assert_93 node _T_684 = asUInt(reset) node _T_685 = eq(_T_684, UInt<1>(0h0)) when _T_685 : node _T_686 = eq(address_ok, UInt<1>(0h0)) when _T_686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(legal_source, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(is_aligned_1, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_693 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_693, UInt<1>(0h1), "") : assert_97 node _T_697 = eq(io.in.b.bits.mask, mask_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_697, UInt<1>(0h1), "") : assert_98 node _T_701 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_701, UInt<1>(0h1), "") : assert_99 node _T_705 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_705 : node _T_706 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_707 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_708 = and(_T_706, _T_707) node _T_709 = or(UInt<1>(0h0), _T_708) node _T_710 = xor(io.in.b.bits.address, UInt<28>(0h8000100)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<17>(0h101c0))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.b.bits.address, UInt<32>(0h80000100)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<29>(0h100001c0))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = or(_T_714, _T_719) node _T_721 = and(_T_709, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = and(UInt<1>(0h0), _T_722) node _T_724 = asUInt(reset) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(_T_723, UInt<1>(0h0)) when _T_726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_723, UInt<1>(0h1), "") : assert_100 node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(address_ok, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(legal_source, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned_1, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_736 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_736, UInt<1>(0h1), "") : assert_104 node _T_740 = eq(io.in.b.bits.mask, mask_1) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_740, UInt<1>(0h1), "") : assert_105 node _T_744 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_746 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = xor(io.in.b.bits.address, UInt<28>(0h8000100)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<17>(0h101c0))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = xor(io.in.b.bits.address, UInt<32>(0h80000100)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<29>(0h100001c0))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = or(_T_753, _T_758) node _T_760 = and(_T_748, _T_759) node _T_761 = or(UInt<1>(0h0), _T_760) node _T_762 = and(UInt<1>(0h0), _T_761) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_762, UInt<1>(0h1), "") : assert_106 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(address_ok, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(legal_source, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(is_aligned_1, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_775 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_775, UInt<1>(0h1), "") : assert_110 node _T_779 = not(mask_1) node _T_780 = and(io.in.b.bits.mask, _T_779) node _T_781 = eq(_T_780, UInt<1>(0h0)) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_781, UInt<1>(0h1), "") : assert_111 node _T_785 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_785 : node _T_786 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_787 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_788 = and(_T_786, _T_787) node _T_789 = or(UInt<1>(0h0), _T_788) node _T_790 = xor(io.in.b.bits.address, UInt<28>(0h8000100)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<17>(0h101c0))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.b.bits.address, UInt<32>(0h80000100)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h100001c0))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_794, _T_799) node _T_801 = and(_T_789, _T_800) node _T_802 = or(UInt<1>(0h0), _T_801) node _T_803 = and(UInt<1>(0h0), _T_802) node _T_804 = asUInt(reset) node _T_805 = eq(_T_804, UInt<1>(0h0)) when _T_805 : node _T_806 = eq(_T_803, UInt<1>(0h0)) when _T_806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_803, UInt<1>(0h1), "") : assert_112 node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(address_ok, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(legal_source, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_813 = asUInt(reset) node _T_814 = eq(_T_813, UInt<1>(0h0)) when _T_814 : node _T_815 = eq(is_aligned_1, UInt<1>(0h0)) when _T_815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_816 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_817 = asUInt(reset) node _T_818 = eq(_T_817, UInt<1>(0h0)) when _T_818 : node _T_819 = eq(_T_816, UInt<1>(0h0)) when _T_819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_816, UInt<1>(0h1), "") : assert_116 node _T_820 = eq(io.in.b.bits.mask, mask_1) node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(_T_820, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_820, UInt<1>(0h1), "") : assert_117 node _T_824 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_824 : node _T_825 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_826 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_827 = and(_T_825, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = xor(io.in.b.bits.address, UInt<28>(0h8000100)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<17>(0h101c0))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.b.bits.address, UInt<32>(0h80000100)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<29>(0h100001c0))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = or(_T_833, _T_838) node _T_840 = and(_T_828, _T_839) node _T_841 = or(UInt<1>(0h0), _T_840) node _T_842 = and(UInt<1>(0h0), _T_841) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_842, UInt<1>(0h1), "") : assert_118 node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(address_ok, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_849 = asUInt(reset) node _T_850 = eq(_T_849, UInt<1>(0h0)) when _T_850 : node _T_851 = eq(legal_source, UInt<1>(0h0)) when _T_851 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_852 = asUInt(reset) node _T_853 = eq(_T_852, UInt<1>(0h0)) when _T_853 : node _T_854 = eq(is_aligned_1, UInt<1>(0h0)) when _T_854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_855 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(_T_855, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_855, UInt<1>(0h1), "") : assert_122 node _T_859 = eq(io.in.b.bits.mask, mask_1) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_859, UInt<1>(0h1), "") : assert_123 node _T_863 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_863 : node _T_864 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_865 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_866 = and(_T_864, _T_865) node _T_867 = or(UInt<1>(0h0), _T_866) node _T_868 = xor(io.in.b.bits.address, UInt<28>(0h8000100)) node _T_869 = cvt(_T_868) node _T_870 = and(_T_869, asSInt(UInt<17>(0h101c0))) node _T_871 = asSInt(_T_870) node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0))) node _T_873 = xor(io.in.b.bits.address, UInt<32>(0h80000100)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<29>(0h100001c0))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = or(_T_872, _T_877) node _T_879 = and(_T_867, _T_878) node _T_880 = or(UInt<1>(0h0), _T_879) node _T_881 = and(UInt<1>(0h0), _T_880) node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(_T_881, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_881, UInt<1>(0h1), "") : assert_124 node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(address_ok, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(legal_source, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(is_aligned_1, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_894 = eq(io.in.b.bits.mask, mask_1) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_894, UInt<1>(0h1), "") : assert_128 node _T_898 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_898, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_902 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_902, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0) node _source_ok_T_12 = shr(io.in.c.bits.source, 4) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h0)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<4>(0h9)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) wire _source_ok_WIRE_2 : UInt<1>[1] connect _source_ok_WIRE_2[0], _source_ok_T_17 node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000100)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h101c0))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000100)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100001c0))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _uncommonBits_T_10 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_906 = shr(io.in.c.bits.source, 4) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = leq(UInt<1>(0h0), uncommonBits_10) node _T_909 = and(_T_907, _T_908) node _T_910 = leq(uncommonBits_10, UInt<4>(0h9)) node _T_911 = and(_T_909, _T_910) node _T_912 = eq(_T_911, UInt<1>(0h0)) node _T_913 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_914 = cvt(_T_913) node _T_915 = and(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = asSInt(_T_915) node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0))) node _T_918 = or(_T_912, _T_917) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_918, UInt<1>(0h1), "") : assert_131 node _T_922 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_922 : node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(address_ok_1, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_133 node _T_929 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_929, UInt<1>(0h1), "") : assert_134 node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(is_aligned_2, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_936 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_936, UInt<1>(0h1), "") : assert_136 node _T_940 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_940, UInt<1>(0h1), "") : assert_137 node _T_944 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_944 : node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(address_ok_1, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_139 node _T_951 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_951, UInt<1>(0h1), "") : assert_140 node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(is_aligned_2, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_958 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_958, UInt<1>(0h1), "") : assert_142 node _T_962 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_962 : node _T_963 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_964 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_965 = and(_T_963, _T_964) node _uncommonBits_T_11 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_966 = shr(io.in.c.bits.source, 4) node _T_967 = eq(_T_966, UInt<1>(0h0)) node _T_968 = leq(UInt<1>(0h0), uncommonBits_11) node _T_969 = and(_T_967, _T_968) node _T_970 = leq(uncommonBits_11, UInt<4>(0h9)) node _T_971 = and(_T_969, _T_970) node _T_972 = and(_T_965, _T_971) node _T_973 = or(UInt<1>(0h0), _T_972) node _T_974 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_975 = leq(io.in.c.bits.size, UInt<3>(0h6)) node _T_976 = and(_T_974, _T_975) node _T_977 = or(UInt<1>(0h0), _T_976) node _T_978 = xor(io.in.c.bits.address, UInt<28>(0h8000100)) node _T_979 = cvt(_T_978) node _T_980 = and(_T_979, asSInt(UInt<17>(0h101c0))) node _T_981 = asSInt(_T_980) node _T_982 = eq(_T_981, asSInt(UInt<1>(0h0))) node _T_983 = xor(io.in.c.bits.address, UInt<32>(0h80000100)) node _T_984 = cvt(_T_983) node _T_985 = and(_T_984, asSInt(UInt<29>(0h100001c0))) node _T_986 = asSInt(_T_985) node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0))) node _T_988 = or(_T_982, _T_987) node _T_989 = and(_T_977, _T_988) node _T_990 = or(UInt<1>(0h0), _T_989) node _T_991 = and(_T_973, _T_990) node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(_T_991, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_991, UInt<1>(0h1), "") : assert_143 node _T_995 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_996 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_997 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_998 = and(_T_996, _T_997) node _T_999 = or(UInt<1>(0h0), _T_998) node _T_1000 = xor(io.in.c.bits.address, UInt<28>(0h8000100)) node _T_1001 = cvt(_T_1000) node _T_1002 = and(_T_1001, asSInt(UInt<17>(0h101c0))) node _T_1003 = asSInt(_T_1002) node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0))) node _T_1005 = xor(io.in.c.bits.address, UInt<32>(0h80000100)) node _T_1006 = cvt(_T_1005) node _T_1007 = and(_T_1006, asSInt(UInt<29>(0h100001c0))) node _T_1008 = asSInt(_T_1007) node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0))) node _T_1010 = or(_T_1004, _T_1009) node _T_1011 = and(_T_999, _T_1010) node _T_1012 = or(UInt<1>(0h0), _T_1011) node _T_1013 = and(_T_995, _T_1012) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_144 node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_145 node _T_1020 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_146 node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1027 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_148 node _T_1031 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_149 node _T_1035 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1035 : node _T_1036 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1037 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1038 = and(_T_1036, _T_1037) node _uncommonBits_T_12 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0) node _T_1039 = shr(io.in.c.bits.source, 4) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) node _T_1041 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1042 = and(_T_1040, _T_1041) node _T_1043 = leq(uncommonBits_12, UInt<4>(0h9)) node _T_1044 = and(_T_1042, _T_1043) node _T_1045 = and(_T_1038, _T_1044) node _T_1046 = or(UInt<1>(0h0), _T_1045) node _T_1047 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1048 = leq(io.in.c.bits.size, UInt<3>(0h6)) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = or(UInt<1>(0h0), _T_1049) node _T_1051 = xor(io.in.c.bits.address, UInt<28>(0h8000100)) node _T_1052 = cvt(_T_1051) node _T_1053 = and(_T_1052, asSInt(UInt<17>(0h101c0))) node _T_1054 = asSInt(_T_1053) node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0))) node _T_1056 = xor(io.in.c.bits.address, UInt<32>(0h80000100)) node _T_1057 = cvt(_T_1056) node _T_1058 = and(_T_1057, asSInt(UInt<29>(0h100001c0))) node _T_1059 = asSInt(_T_1058) node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0))) node _T_1061 = or(_T_1055, _T_1060) node _T_1062 = and(_T_1050, _T_1061) node _T_1063 = or(UInt<1>(0h0), _T_1062) node _T_1064 = and(_T_1046, _T_1063) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_150 node _T_1068 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1069 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1070 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = or(UInt<1>(0h0), _T_1071) node _T_1073 = xor(io.in.c.bits.address, UInt<28>(0h8000100)) node _T_1074 = cvt(_T_1073) node _T_1075 = and(_T_1074, asSInt(UInt<17>(0h101c0))) node _T_1076 = asSInt(_T_1075) node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0))) node _T_1078 = xor(io.in.c.bits.address, UInt<32>(0h80000100)) node _T_1079 = cvt(_T_1078) node _T_1080 = and(_T_1079, asSInt(UInt<29>(0h100001c0))) node _T_1081 = asSInt(_T_1080) node _T_1082 = eq(_T_1081, asSInt(UInt<1>(0h0))) node _T_1083 = or(_T_1077, _T_1082) node _T_1084 = and(_T_1072, _T_1083) node _T_1085 = or(UInt<1>(0h0), _T_1084) node _T_1086 = and(_T_1068, _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_151 node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_152 node _T_1093 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1094 = asUInt(reset) node _T_1095 = eq(_T_1094, UInt<1>(0h0)) when _T_1095 : node _T_1096 = eq(_T_1093, UInt<1>(0h0)) when _T_1096 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1093, UInt<1>(0h1), "") : assert_153 node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1100 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_155 node _T_1104 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1104 : node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(address_ok_1, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_157 node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1114 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_159 node _T_1118 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_160 node _T_1122 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1122 : node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(address_ok_1, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_162 node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1132 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(_T_1132, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1132, UInt<1>(0h1), "") : assert_164 node _T_1136 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1136 : node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(address_ok_1, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_166 node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1146 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_168 node _T_1150 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1157 = eq(a_first, UInt<1>(0h0)) node _T_1158 = and(io.in.a.valid, _T_1157) when _T_1158 : node _T_1159 = eq(io.in.a.bits.opcode, opcode) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_171 node _T_1163 = eq(io.in.a.bits.param, param) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_172 node _T_1167 = eq(io.in.a.bits.size, size) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_173 node _T_1171 = eq(io.in.a.bits.source, source) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_174 node _T_1175 = eq(io.in.a.bits.address, address) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_175 node _T_1179 = and(io.in.a.ready, io.in.a.valid) node _T_1180 = and(_T_1179, a_first) when _T_1180 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1181 = eq(d_first, UInt<1>(0h0)) node _T_1182 = and(io.in.d.valid, _T_1181) when _T_1182 : node _T_1183 = eq(io.in.d.bits.opcode, opcode_1) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_176 node _T_1187 = eq(io.in.d.bits.param, param_1) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_177 node _T_1191 = eq(io.in.d.bits.size, size_1) node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(_T_1191, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_1191, UInt<1>(0h1), "") : assert_178 node _T_1195 = eq(io.in.d.bits.source, source_1) node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(_T_1195, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_1195, UInt<1>(0h1), "") : assert_179 node _T_1199 = eq(io.in.d.bits.sink, sink) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_180 node _T_1203 = eq(io.in.d.bits.denied, denied) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_181 node _T_1207 = and(io.in.d.ready, io.in.d.valid) node _T_1208 = and(_T_1207, d_first) when _T_1208 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_1209 = eq(b_first, UInt<1>(0h0)) node _T_1210 = and(io.in.b.valid, _T_1209) when _T_1210 : node _T_1211 = eq(io.in.b.bits.opcode, opcode_2) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_182 node _T_1215 = eq(io.in.b.bits.param, param_2) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_183 node _T_1219 = eq(io.in.b.bits.size, size_2) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_184 node _T_1223 = eq(io.in.b.bits.source, source_2) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_185 node _T_1227 = eq(io.in.b.bits.address, address_1) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_186 node _T_1231 = and(io.in.b.ready, io.in.b.valid) node _T_1232 = and(_T_1231, b_first) when _T_1232 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_1233 = eq(c_first, UInt<1>(0h0)) node _T_1234 = and(io.in.c.valid, _T_1233) when _T_1234 : node _T_1235 = eq(io.in.c.bits.opcode, opcode_3) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_187 node _T_1239 = eq(io.in.c.bits.param, param_3) node _T_1240 = asUInt(reset) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(_T_1239, UInt<1>(0h0)) when _T_1242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_1239, UInt<1>(0h1), "") : assert_188 node _T_1243 = eq(io.in.c.bits.size, size_3) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_189 node _T_1247 = eq(io.in.c.bits.source, source_3) node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(_T_1247, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_1247, UInt<1>(0h1), "") : assert_190 node _T_1251 = eq(io.in.c.bits.address, address_2) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_191 node _T_1255 = and(io.in.c.ready, io.in.c.valid) node _T_1256 = and(_T_1255, c_first) when _T_1256 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1257 = and(io.in.a.valid, a_first_1) node _T_1258 = and(_T_1257, UInt<1>(0h1)) when _T_1258 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1259 = and(io.in.a.ready, io.in.a.valid) node _T_1260 = and(_T_1259, a_first_1) node _T_1261 = and(_T_1260, UInt<1>(0h1)) when _T_1261 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1262 = dshr(inflight, io.in.a.bits.source) node _T_1263 = bits(_T_1262, 0, 0) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1268 = and(io.in.d.valid, d_first_1) node _T_1269 = and(_T_1268, UInt<1>(0h1)) node _T_1270 = eq(d_release_ack, UInt<1>(0h0)) node _T_1271 = and(_T_1269, _T_1270) when _T_1271 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1272 = and(io.in.d.ready, io.in.d.valid) node _T_1273 = and(_T_1272, d_first_1) node _T_1274 = and(_T_1273, UInt<1>(0h1)) node _T_1275 = eq(d_release_ack, UInt<1>(0h0)) node _T_1276 = and(_T_1274, _T_1275) when _T_1276 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1277 = and(io.in.d.valid, d_first_1) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = eq(d_release_ack, UInt<1>(0h0)) node _T_1280 = and(_T_1278, _T_1279) when _T_1280 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1281 = dshr(inflight, io.in.d.bits.source) node _T_1282 = bits(_T_1281, 0, 0) node _T_1283 = or(_T_1282, same_cycle_resp) node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(_T_1283, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_1283, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_1287 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1288 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_194 node _T_1293 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_195 else : node _T_1297 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1298 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1299 = or(_T_1297, _T_1298) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_196 node _T_1303 = eq(io.in.d.bits.size, a_size_lookup) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_197 node _T_1307 = and(io.in.d.valid, d_first_1) node _T_1308 = and(_T_1307, a_first_1) node _T_1309 = and(_T_1308, io.in.a.valid) node _T_1310 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = eq(d_release_ack, UInt<1>(0h0)) node _T_1313 = and(_T_1311, _T_1312) when _T_1313 : node _T_1314 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1315 = or(_T_1314, io.in.a.ready) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_198 node _T_1319 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1320 = orr(a_set_wo_ready) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) node _T_1322 = or(_T_1319, _T_1321) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_140 node _T_1326 = orr(inflight) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) node _T_1328 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1329 = or(_T_1327, _T_1328) node _T_1330 = lt(watchdog, plusarg_reader.out) node _T_1331 = or(_T_1329, _T_1330) node _T_1332 = asUInt(reset) node _T_1333 = eq(_T_1332, UInt<1>(0h0)) when _T_1333 : node _T_1334 = eq(_T_1331, UInt<1>(0h0)) when _T_1334 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_1331, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1335 = and(io.in.a.ready, io.in.a.valid) node _T_1336 = and(io.in.d.ready, io.in.d.valid) node _T_1337 = or(_T_1335, _T_1336) when _T_1337 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_1338 = and(io.in.c.valid, c_first_1) node _T_1339 = bits(io.in.c.bits.opcode, 2, 2) node _T_1340 = bits(io.in.c.bits.opcode, 1, 1) node _T_1341 = and(_T_1339, _T_1340) node _T_1342 = and(_T_1338, _T_1341) when _T_1342 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_1343 = and(io.in.c.ready, io.in.c.valid) node _T_1344 = and(_T_1343, c_first_1) node _T_1345 = bits(io.in.c.bits.opcode, 2, 2) node _T_1346 = bits(io.in.c.bits.opcode, 1, 1) node _T_1347 = and(_T_1345, _T_1346) node _T_1348 = and(_T_1344, _T_1347) when _T_1348 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_1349 = dshr(inflight_1, io.in.c.bits.source) node _T_1350 = bits(_T_1349, 0, 0) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1355 = and(io.in.d.valid, d_first_2) node _T_1356 = and(_T_1355, UInt<1>(0h1)) node _T_1357 = and(_T_1356, d_release_ack_1) when _T_1357 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1358 = and(io.in.d.ready, io.in.d.valid) node _T_1359 = and(_T_1358, d_first_2) node _T_1360 = and(_T_1359, UInt<1>(0h1)) node _T_1361 = and(_T_1360, d_release_ack_1) when _T_1361 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1362 = and(io.in.d.valid, d_first_2) node _T_1363 = and(_T_1362, UInt<1>(0h1)) node _T_1364 = and(_T_1363, d_release_ack_1) when _T_1364 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1365 = dshr(inflight_1, io.in.d.bits.source) node _T_1366 = bits(_T_1365, 0, 0) node _T_1367 = or(_T_1366, same_cycle_resp_1) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_1371 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_203 else : node _T_1375 = eq(io.in.d.bits.size, c_size_lookup) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_204 node _T_1379 = and(io.in.d.valid, d_first_2) node _T_1380 = and(_T_1379, c_first_1) node _T_1381 = and(_T_1380, io.in.c.valid) node _T_1382 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_1383 = and(_T_1381, _T_1382) node _T_1384 = and(_T_1383, d_release_ack_1) node _T_1385 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1386 = and(_T_1384, _T_1385) when _T_1386 : node _T_1387 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1388 = or(_T_1387, io.in.c.ready) node _T_1389 = asUInt(reset) node _T_1390 = eq(_T_1389, UInt<1>(0h0)) when _T_1390 : node _T_1391 = eq(_T_1388, UInt<1>(0h0)) when _T_1391 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_1388, UInt<1>(0h1), "") : assert_205 node _T_1392 = orr(c_set_wo_ready) when _T_1392 : node _T_1393 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(_T_1393, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_1393, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_141 node _T_1397 = orr(inflight_1) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) node _T_1399 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1400 = or(_T_1398, _T_1399) node _T_1401 = lt(watchdog_1, plusarg_reader_1.out) node _T_1402 = or(_T_1400, _T_1401) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_1406 = and(io.in.c.ready, io.in.c.valid) node _T_1407 = and(io.in.d.ready, io.in.d.valid) node _T_1408 = or(_T_1406, _T_1407) when _T_1408 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_1409 = and(io.in.d.ready, io.in.d.valid) node _T_1410 = and(_T_1409, d_first_3) node _T_1411 = bits(io.in.d.bits.opcode, 2, 2) node _T_1412 = bits(io.in.d.bits.opcode, 1, 1) node _T_1413 = eq(_T_1412, UInt<1>(0h0)) node _T_1414 = and(_T_1411, _T_1413) node _T_1415 = and(_T_1410, _T_1414) when _T_1415 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_1416 = dshr(inflight_2, io.in.d.bits.sink) node _T_1417 = bits(_T_1416, 0, 0) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(_T_1418, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_1418, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_1422 = and(io.in.e.ready, io.in.e.valid) node _T_1423 = and(_T_1422, UInt<1>(0h1)) node _T_1424 = and(_T_1423, UInt<1>(0h1)) when _T_1424 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_1425 = or(d_set, inflight_2) node _T_1426 = dshr(_T_1425, io.in.e.bits.sink) node _T_1427 = bits(_T_1426, 0, 0) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_142 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_143 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor_70( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode = 3'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h0; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_3 = 3'h0; // @[Misc.scala:202:34] wire [2:0] b_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _b_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _b_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire io_in_b_valid = 1'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _address_ok_T_4 = 1'h0; // @[Parameters.scala:137:59] wire _address_ok_T_9 = 1'h0; // @[Parameters.scala:137:59] wire _address_ok_WIRE_0 = 1'h0; // @[Parameters.scala:612:40] wire _address_ok_WIRE_1 = 1'h0; // @[Parameters.scala:612:40] wire address_ok = 1'h0; // @[Parameters.scala:636:64] wire mask_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire mask_sub_sub_bit_1 = 1'h0; // @[Misc.scala:210:26] wire _mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire mask_sub_bit_1 = 1'h0; // @[Misc.scala:210:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_0_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_2_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_2_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_3_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_3_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_bit_1 = 1'h0; // @[Misc.scala:210:26] wire mask_eq_9 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_9 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_10 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_10 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_11 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_11 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_12 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_12 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_13 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_13 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_14 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_14 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_15 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_15 = 1'h0; // @[Misc.scala:215:29] wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_12 = 1'h0; // @[Parameters.scala:54:10] wire _b_first_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_first_beats1_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _b_first_last_T = 1'h0; // @[Edges.scala:232:25] wire b_first_done = 1'h0; // @[Edges.scala:233:22] wire io_in_b_ready = 1'h1; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire is_aligned_1 = 1'h1; // @[Edges.scala:21:24] wire mask_sub_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire mask_sub_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire mask_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire mask_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire mask_eq_8 = 1'h1; // @[Misc.scala:214:27] wire _mask_acc_T_8 = 1'h1; // @[Misc.scala:215:38] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _legal_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _legal_source_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_13 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire b_first_beats1_opdata = 1'h1; // @[Edges.scala:97:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] b_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _b_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [31:0] io_in_b_bits_address = 32'h0; // @[Monitor.scala:36:7] wire [31:0] _is_aligned_T_1 = 32'h0; // @[Edges.scala:21:16] wire [3:0] io_in_b_bits_source = 4'h0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = 4'h0; // @[Parameters.scala:52:29] wire [3:0] uncommonBits_9 = 4'h0; // @[Parameters.scala:52:56] wire [3:0] mask_hi_1 = 4'h0; // @[Misc.scala:222:10] wire [3:0] _legal_source_uncommonBits_T = 4'h0; // @[Parameters.scala:52:29] wire [3:0] legal_source_uncommonBits = 4'h0; // @[Parameters.scala:52:56] wire [1:0] io_in_b_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h0; // @[OneHot.scala:64:49] wire [1:0] mask_lo_hi_1 = 2'h0; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h0; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h0; // @[Misc.scala:222:10] wire [7:0] io_in_b_bits_mask = 8'h0; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] _mask_sizeOH_T_5 = 3'h1; // @[OneHot.scala:65:27] wire [2:0] mask_sizeOH_1 = 3'h1; // @[Misc.scala:202:81] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [5:0] is_aligned_mask_1 = 6'h0; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h3F; // @[package.scala:243:76] wire [5:0] _b_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'h3F; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [7:0] mask_1 = 8'h1; // @[Misc.scala:222:10] wire [3:0] _mask_sizeOH_T_4 = 4'h1; // @[OneHot.scala:65:12] wire [3:0] mask_lo_1 = 4'h1; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h1; // @[Misc.scala:222:10] wire [32:0] _address_ok_T_6 = 33'h80000100; // @[Parameters.scala:137:41] wire [32:0] _address_ok_T_7 = 33'h80000100; // @[Parameters.scala:137:46] wire [32:0] _address_ok_T_8 = 33'h80000100; // @[Parameters.scala:137:46] wire [31:0] _address_ok_T_5 = 32'h80000100; // @[Parameters.scala:137:31] wire [32:0] _address_ok_T_1 = 33'h8000100; // @[Parameters.scala:137:41] wire [32:0] _address_ok_T_2 = 33'h8000100; // @[Parameters.scala:137:46] wire [32:0] _address_ok_T_3 = 33'h8000100; // @[Parameters.scala:137:46] wire [31:0] _address_ok_T = 32'h8000100; // @[Parameters.scala:137:31] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_16 = source_ok_uncommonBits_2 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_17 = _source_ok_T_16; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [12:0] _GEN_0 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_0; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_1 = io_in_c_bits_address_0[27:0] ^ 28'h8000100; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000100; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [3:0] uncommonBits_10 = _uncommonBits_T_10; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_12 = _uncommonBits_T_12; // @[Parameters.scala:52:{29,56}] wire _T_1335 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1335; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1335; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1409 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1409; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1409; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1409; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_1409; // @[Decoupled.scala:51:35] wire [12:0] _GEN_2 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_2; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_2; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_2; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_2; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _T_1406 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_1406; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_1406; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [3:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_3 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_3; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_3; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_3; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_3; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_3; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_4 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1261 = _T_1335 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1261 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1261 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1261 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_5 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_5; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_5; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1261 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1261 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_6 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_6; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_6; // @[Monitor.scala:673:46, :783:46] wire _T_1307 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_7 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1307 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1276 = _T_1409 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1276 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1276 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1276 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] c_set; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [39:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [15:0] _GEN_8 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [15:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_8; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1348 = _T_1406 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_1348 ? _c_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_1348 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_1348 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [6:0] _GEN_9 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [6:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_9; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_9; // @[Monitor.scala:767:79, :768:77] wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_1348 ? _c_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [130:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_1348 ? _c_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1379 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1379 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1361 = _T_1409 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1361 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1361 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1361 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [9:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_1415 = _T_1409 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_10 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_10; // @[OneHot.scala:58:35] assign d_set = _T_1415 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _GEN_11 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_11; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module ConstellationMemoryBus : output auto : { buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_memory_controller_port_named_axi4_axi4yank_out_3 : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}, coupler_to_memory_controller_port_named_axi4_axi4yank_out_2 : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}, coupler_to_memory_controller_port_named_axi4_axi4yank_out_1 : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}, coupler_to_memory_controller_port_named_axi4_axi4yank_out_0 : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip mbus_clock_groups_in : { member : { mbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip bus_xing_in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip bus_xing_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip bus_xing_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst mbus_clock_groups of ClockGroupAggregator_mbus inst clockGroup of ClockGroup_4 inst fixedClockNode of FixedClockBroadcast_3 inst broadcast of BundleBridgeNexus_NoOutput_4 inst memory_bus_noc of TLNoC_2 connect memory_bus_noc.clock, childClock connect memory_bus_noc.reset, childReset inst fixer of TLFIFOFixer_4 connect fixer.clock, childClock connect fixer.reset, childReset inst picker of ProbePicker connect picker.clock, childClock connect picker.reset, childReset inst buffer of TLBuffer_a32d64s4k1z3u connect buffer.clock, childClock connect buffer.reset, childReset inst coupler_to_memory_controller_port_named_tl_mem of TLInterconnectCoupler_mbus_to_memory_controller_port_named_tl_mem connect coupler_to_memory_controller_port_named_tl_mem.clock, childClock connect coupler_to_memory_controller_port_named_tl_mem.reset, childReset inst xbar of TLXbar_i1_o1_a32d64s6k1z3u connect xbar.clock, childClock connect xbar.reset, childReset inst coupler_to_memory_controller_port_named_axi4 of TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 connect coupler_to_memory_controller_port_named_axi4.clock, childClock connect coupler_to_memory_controller_port_named_axi4.reset, childReset inst xbar_1 of TLXbar_i1_o1_a32d64s6k1z3u_1 connect xbar_1.clock, childClock connect xbar_1.reset, childReset inst coupler_to_memory_controller_port_named_axi4_1 of TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4_1 connect coupler_to_memory_controller_port_named_axi4_1.clock, childClock connect coupler_to_memory_controller_port_named_axi4_1.reset, childReset inst xbar_2 of TLXbar_i1_o1_a32d64s6k1z3u_2 connect xbar_2.clock, childClock connect xbar_2.reset, childReset inst coupler_to_memory_controller_port_named_axi4_2 of TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4_2 connect coupler_to_memory_controller_port_named_axi4_2.clock, childClock connect coupler_to_memory_controller_port_named_axi4_2.reset, childReset inst xbar_3 of TLXbar_i1_o1_a32d64s6k1z3u_3 connect xbar_3.clock, childClock connect xbar_3.reset, childReset inst coupler_to_memory_controller_port_named_axi4_3 of TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4_3 connect coupler_to_memory_controller_port_named_axi4_3.clock, childClock connect coupler_to_memory_controller_port_named_axi4_3.reset, childReset inst coupler_to_mbusscratchpad00 of TLInterconnectCoupler_mbus_to_mbusscratchpad00 connect coupler_to_mbusscratchpad00.clock, childClock connect coupler_to_mbusscratchpad00.reset, childReset inst buffer_1 of TLBuffer_a28d64s6k1z3u connect buffer_1.clock, childClock connect buffer_1.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire x1_bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_bus_xingOut.d.bits.corrupt invalidate x1_bus_xingOut.d.bits.data invalidate x1_bus_xingOut.d.bits.denied invalidate x1_bus_xingOut.d.bits.sink invalidate x1_bus_xingOut.d.bits.source invalidate x1_bus_xingOut.d.bits.size invalidate x1_bus_xingOut.d.bits.param invalidate x1_bus_xingOut.d.bits.opcode invalidate x1_bus_xingOut.d.valid invalidate x1_bus_xingOut.d.ready invalidate x1_bus_xingOut.a.bits.corrupt invalidate x1_bus_xingOut.a.bits.data invalidate x1_bus_xingOut.a.bits.mask invalidate x1_bus_xingOut.a.bits.address invalidate x1_bus_xingOut.a.bits.source invalidate x1_bus_xingOut.a.bits.size invalidate x1_bus_xingOut.a.bits.param invalidate x1_bus_xingOut.a.bits.opcode invalidate x1_bus_xingOut.a.valid invalidate x1_bus_xingOut.a.ready wire x1_bus_xingOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_bus_xingOut_1.d.bits.corrupt invalidate x1_bus_xingOut_1.d.bits.data invalidate x1_bus_xingOut_1.d.bits.denied invalidate x1_bus_xingOut_1.d.bits.sink invalidate x1_bus_xingOut_1.d.bits.source invalidate x1_bus_xingOut_1.d.bits.size invalidate x1_bus_xingOut_1.d.bits.param invalidate x1_bus_xingOut_1.d.bits.opcode invalidate x1_bus_xingOut_1.d.valid invalidate x1_bus_xingOut_1.d.ready invalidate x1_bus_xingOut_1.a.bits.corrupt invalidate x1_bus_xingOut_1.a.bits.data invalidate x1_bus_xingOut_1.a.bits.mask invalidate x1_bus_xingOut_1.a.bits.address invalidate x1_bus_xingOut_1.a.bits.source invalidate x1_bus_xingOut_1.a.bits.size invalidate x1_bus_xingOut_1.a.bits.param invalidate x1_bus_xingOut_1.a.bits.opcode invalidate x1_bus_xingOut_1.a.valid invalidate x1_bus_xingOut_1.a.ready wire x1_bus_xingOut_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_bus_xingOut_2.d.bits.corrupt invalidate x1_bus_xingOut_2.d.bits.data invalidate x1_bus_xingOut_2.d.bits.denied invalidate x1_bus_xingOut_2.d.bits.sink invalidate x1_bus_xingOut_2.d.bits.source invalidate x1_bus_xingOut_2.d.bits.size invalidate x1_bus_xingOut_2.d.bits.param invalidate x1_bus_xingOut_2.d.bits.opcode invalidate x1_bus_xingOut_2.d.valid invalidate x1_bus_xingOut_2.d.ready invalidate x1_bus_xingOut_2.a.bits.corrupt invalidate x1_bus_xingOut_2.a.bits.data invalidate x1_bus_xingOut_2.a.bits.mask invalidate x1_bus_xingOut_2.a.bits.address invalidate x1_bus_xingOut_2.a.bits.source invalidate x1_bus_xingOut_2.a.bits.size invalidate x1_bus_xingOut_2.a.bits.param invalidate x1_bus_xingOut_2.a.bits.opcode invalidate x1_bus_xingOut_2.a.valid invalidate x1_bus_xingOut_2.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready wire x1_bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_bus_xingIn.d.bits.corrupt invalidate x1_bus_xingIn.d.bits.data invalidate x1_bus_xingIn.d.bits.denied invalidate x1_bus_xingIn.d.bits.sink invalidate x1_bus_xingIn.d.bits.source invalidate x1_bus_xingIn.d.bits.size invalidate x1_bus_xingIn.d.bits.param invalidate x1_bus_xingIn.d.bits.opcode invalidate x1_bus_xingIn.d.valid invalidate x1_bus_xingIn.d.ready invalidate x1_bus_xingIn.a.bits.corrupt invalidate x1_bus_xingIn.a.bits.data invalidate x1_bus_xingIn.a.bits.mask invalidate x1_bus_xingIn.a.bits.address invalidate x1_bus_xingIn.a.bits.source invalidate x1_bus_xingIn.a.bits.size invalidate x1_bus_xingIn.a.bits.param invalidate x1_bus_xingIn.a.bits.opcode invalidate x1_bus_xingIn.a.valid invalidate x1_bus_xingIn.a.ready wire x1_bus_xingIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_bus_xingIn_1.d.bits.corrupt invalidate x1_bus_xingIn_1.d.bits.data invalidate x1_bus_xingIn_1.d.bits.denied invalidate x1_bus_xingIn_1.d.bits.sink invalidate x1_bus_xingIn_1.d.bits.source invalidate x1_bus_xingIn_1.d.bits.size invalidate x1_bus_xingIn_1.d.bits.param invalidate x1_bus_xingIn_1.d.bits.opcode invalidate x1_bus_xingIn_1.d.valid invalidate x1_bus_xingIn_1.d.ready invalidate x1_bus_xingIn_1.a.bits.corrupt invalidate x1_bus_xingIn_1.a.bits.data invalidate x1_bus_xingIn_1.a.bits.mask invalidate x1_bus_xingIn_1.a.bits.address invalidate x1_bus_xingIn_1.a.bits.source invalidate x1_bus_xingIn_1.a.bits.size invalidate x1_bus_xingIn_1.a.bits.param invalidate x1_bus_xingIn_1.a.bits.opcode invalidate x1_bus_xingIn_1.a.valid invalidate x1_bus_xingIn_1.a.ready wire x1_bus_xingIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_bus_xingIn_2.d.bits.corrupt invalidate x1_bus_xingIn_2.d.bits.data invalidate x1_bus_xingIn_2.d.bits.denied invalidate x1_bus_xingIn_2.d.bits.sink invalidate x1_bus_xingIn_2.d.bits.source invalidate x1_bus_xingIn_2.d.bits.size invalidate x1_bus_xingIn_2.d.bits.param invalidate x1_bus_xingIn_2.d.bits.opcode invalidate x1_bus_xingIn_2.d.valid invalidate x1_bus_xingIn_2.d.ready invalidate x1_bus_xingIn_2.a.bits.corrupt invalidate x1_bus_xingIn_2.a.bits.data invalidate x1_bus_xingIn_2.a.bits.mask invalidate x1_bus_xingIn_2.a.bits.address invalidate x1_bus_xingIn_2.a.bits.source invalidate x1_bus_xingIn_2.a.bits.size invalidate x1_bus_xingIn_2.a.bits.param invalidate x1_bus_xingIn_2.a.bits.opcode invalidate x1_bus_xingIn_2.a.valid invalidate x1_bus_xingIn_2.a.ready connect bus_xingOut, bus_xingIn connect x1_bus_xingOut, x1_bus_xingIn connect x1_bus_xingOut_1, x1_bus_xingIn_1 connect x1_bus_xingOut_2, x1_bus_xingIn_2 connect clockGroup.auto.in, mbus_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect picker.auto.in_0, memory_bus_noc.auto.out_0 connect picker.auto.in_1, memory_bus_noc.auto.out_1 connect picker.auto.in_2, memory_bus_noc.auto.out_2 connect picker.auto.in_3, memory_bus_noc.auto.out_3 connect picker.auto.in_4, memory_bus_noc.auto.out_4 connect memory_bus_noc.auto.in_0, fixer.auto.anon_out_0 connect memory_bus_noc.auto.in_1, fixer.auto.anon_out_1 connect memory_bus_noc.auto.in_2, fixer.auto.anon_out_2 connect memory_bus_noc.auto.in_3, fixer.auto.anon_out_3 connect coupler_to_memory_controller_port_named_axi4.auto.tl_in, picker.auto.out_0 connect coupler_to_memory_controller_port_named_axi4_1.auto.tl_in, picker.auto.out_1 connect coupler_to_memory_controller_port_named_axi4_2.auto.tl_in, picker.auto.out_2 connect coupler_to_memory_controller_port_named_axi4_3.auto.tl_in, picker.auto.out_3 connect coupler_to_mbusscratchpad00.auto.tl_in, picker.auto.out_4 connect fixer.auto.anon_in_0, buffer.auto.out_0 connect fixer.auto.anon_in_1, buffer.auto.out_1 connect fixer.auto.anon_in_2, buffer.auto.out_2 connect fixer.auto.anon_in_3, buffer.auto.out_3 connect buffer.auto.in_0, bus_xingOut connect buffer.auto.in_1, x1_bus_xingOut connect buffer.auto.in_2, x1_bus_xingOut_1 connect buffer.auto.in_3, x1_bus_xingOut_2 connect coupler_to_memory_controller_port_named_axi4.auto.widget_anon_in, xbar.auto.anon_out connect xbar.auto.anon_in, coupler_to_memory_controller_port_named_axi4.auto.tl_out connect coupler_to_memory_controller_port_named_axi4_1.auto.widget_anon_in, xbar_1.auto.anon_out connect xbar_1.auto.anon_in, coupler_to_memory_controller_port_named_axi4_1.auto.tl_out connect coupler_to_memory_controller_port_named_axi4_2.auto.widget_anon_in, xbar_2.auto.anon_out connect xbar_2.auto.anon_in, coupler_to_memory_controller_port_named_axi4_2.auto.tl_out connect coupler_to_memory_controller_port_named_axi4_3.auto.widget_anon_in, xbar_3.auto.anon_out connect xbar_3.auto.anon_in, coupler_to_memory_controller_port_named_axi4_3.auto.tl_out connect buffer_1.auto.in, coupler_to_mbusscratchpad00.auto.tl_out connect bus_xingIn, auto.bus_xing_in_0 connect x1_bus_xingIn, auto.bus_xing_in_1 connect x1_bus_xingIn_1, auto.bus_xing_in_2 connect x1_bus_xingIn_2, auto.bus_xing_in_3 connect mbus_clock_groups.auto.in, auto.mbus_clock_groups_in connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1 connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2 connect coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.r, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_0.r connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_0.ar.bits, coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.ar.bits connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_0.ar.valid, coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.ar.valid connect coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.ar.ready, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_0.ar.ready connect coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.b, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_0.b connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_0.w.bits, coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.w.bits connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_0.w.valid, coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.w.valid connect coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.w.ready, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_0.w.ready connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_0.aw.bits, coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.aw.bits connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_0.aw.valid, coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.aw.valid connect coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.aw.ready, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_0.aw.ready connect coupler_to_memory_controller_port_named_axi4_1.auto.axi4yank_out.r, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_1.r connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_1.ar.bits, coupler_to_memory_controller_port_named_axi4_1.auto.axi4yank_out.ar.bits connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_1.ar.valid, coupler_to_memory_controller_port_named_axi4_1.auto.axi4yank_out.ar.valid connect coupler_to_memory_controller_port_named_axi4_1.auto.axi4yank_out.ar.ready, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_1.ar.ready connect coupler_to_memory_controller_port_named_axi4_1.auto.axi4yank_out.b, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_1.b connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_1.w.bits, coupler_to_memory_controller_port_named_axi4_1.auto.axi4yank_out.w.bits connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_1.w.valid, coupler_to_memory_controller_port_named_axi4_1.auto.axi4yank_out.w.valid connect coupler_to_memory_controller_port_named_axi4_1.auto.axi4yank_out.w.ready, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_1.w.ready connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_1.aw.bits, coupler_to_memory_controller_port_named_axi4_1.auto.axi4yank_out.aw.bits connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_1.aw.valid, coupler_to_memory_controller_port_named_axi4_1.auto.axi4yank_out.aw.valid connect coupler_to_memory_controller_port_named_axi4_1.auto.axi4yank_out.aw.ready, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_1.aw.ready connect coupler_to_memory_controller_port_named_axi4_2.auto.axi4yank_out.r, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_2.r connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_2.ar.bits, coupler_to_memory_controller_port_named_axi4_2.auto.axi4yank_out.ar.bits connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_2.ar.valid, coupler_to_memory_controller_port_named_axi4_2.auto.axi4yank_out.ar.valid connect coupler_to_memory_controller_port_named_axi4_2.auto.axi4yank_out.ar.ready, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_2.ar.ready connect coupler_to_memory_controller_port_named_axi4_2.auto.axi4yank_out.b, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_2.b connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_2.w.bits, coupler_to_memory_controller_port_named_axi4_2.auto.axi4yank_out.w.bits connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_2.w.valid, coupler_to_memory_controller_port_named_axi4_2.auto.axi4yank_out.w.valid connect coupler_to_memory_controller_port_named_axi4_2.auto.axi4yank_out.w.ready, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_2.w.ready connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_2.aw.bits, coupler_to_memory_controller_port_named_axi4_2.auto.axi4yank_out.aw.bits connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_2.aw.valid, coupler_to_memory_controller_port_named_axi4_2.auto.axi4yank_out.aw.valid connect coupler_to_memory_controller_port_named_axi4_2.auto.axi4yank_out.aw.ready, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_2.aw.ready connect coupler_to_memory_controller_port_named_axi4_3.auto.axi4yank_out.r, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_3.r connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_3.ar.bits, coupler_to_memory_controller_port_named_axi4_3.auto.axi4yank_out.ar.bits connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_3.ar.valid, coupler_to_memory_controller_port_named_axi4_3.auto.axi4yank_out.ar.valid connect coupler_to_memory_controller_port_named_axi4_3.auto.axi4yank_out.ar.ready, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_3.ar.ready connect coupler_to_memory_controller_port_named_axi4_3.auto.axi4yank_out.b, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_3.b connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_3.w.bits, coupler_to_memory_controller_port_named_axi4_3.auto.axi4yank_out.w.bits connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_3.w.valid, coupler_to_memory_controller_port_named_axi4_3.auto.axi4yank_out.w.valid connect coupler_to_memory_controller_port_named_axi4_3.auto.axi4yank_out.w.ready, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_3.w.ready connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_3.aw.bits, coupler_to_memory_controller_port_named_axi4_3.auto.axi4yank_out.aw.bits connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_3.aw.valid, coupler_to_memory_controller_port_named_axi4_3.auto.axi4yank_out.aw.valid connect coupler_to_memory_controller_port_named_axi4_3.auto.axi4yank_out.aw.ready, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out_3.aw.ready connect buffer_1.auto.out.d, auto.buffer_out.d connect auto.buffer_out.a.bits, buffer_1.auto.out.a.bits connect auto.buffer_out.a.valid, buffer_1.auto.out.a.valid connect buffer_1.auto.out.a.ready, auto.buffer_out.a.ready connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset
module ConstellationMemoryBus( // @[ClockDomain.scala:14:9] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_w_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_b_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_r_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_r_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_r_bits_last, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_w_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_b_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_r_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_r_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_r_bits_last, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_w_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_b_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_r_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_r_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_r_bits_last, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_w_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_b_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_r_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_r_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_r_bits_last, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25] input auto_mbus_clock_groups_in_member_mbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_mbus_clock_groups_in_member_mbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_3_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_3_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_bus_xing_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_3_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_3_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_2_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_2_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_bus_xing_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_2_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_2_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_bus_xing_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_bus_xing_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _buffer_1_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_1_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_1_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_1_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [5:0] _buffer_1_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_1_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_size; // @[LazyScope.scala:98:27] wire [5:0] _coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [5:0] _coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_size; // @[LazyScope.scala:98:27] wire [5:0] _coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_source; // @[LazyScope.scala:98:27] wire [31:0] _coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_d_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_size; // @[LazyScope.scala:98:27] wire [5:0] _coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [5:0] _coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_size; // @[LazyScope.scala:98:27] wire [5:0] _coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_source; // @[LazyScope.scala:98:27] wire [31:0] _coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_d_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_size; // @[LazyScope.scala:98:27] wire [5:0] _coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [5:0] _coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_size; // @[LazyScope.scala:98:27] wire [5:0] _coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_source; // @[LazyScope.scala:98:27] wire [31:0] _coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_d_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_size; // @[LazyScope.scala:98:27] wire [5:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [5:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_size; // @[LazyScope.scala:98:27] wire [5:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_source; // @[LazyScope.scala:98:27] wire [31:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_out_d_ready; // @[LazyScope.scala:98:27] wire _picker_auto_in_4_a_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_in_4_d_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_4_d_bits_opcode; // @[ProbePicker.scala:69:28] wire [1:0] _picker_auto_in_4_d_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_4_d_bits_size; // @[ProbePicker.scala:69:28] wire [5:0] _picker_auto_in_4_d_bits_source; // @[ProbePicker.scala:69:28] wire _picker_auto_in_4_d_bits_sink; // @[ProbePicker.scala:69:28] wire _picker_auto_in_4_d_bits_denied; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_in_4_d_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_in_4_d_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_in_3_a_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_in_3_d_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_3_d_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_3_d_bits_size; // @[ProbePicker.scala:69:28] wire [5:0] _picker_auto_in_3_d_bits_source; // @[ProbePicker.scala:69:28] wire _picker_auto_in_3_d_bits_denied; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_in_3_d_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_in_3_d_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_in_2_a_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_in_2_d_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_2_d_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_2_d_bits_size; // @[ProbePicker.scala:69:28] wire [5:0] _picker_auto_in_2_d_bits_source; // @[ProbePicker.scala:69:28] wire _picker_auto_in_2_d_bits_denied; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_in_2_d_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_in_2_d_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_a_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_1_d_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_1_d_bits_size; // @[ProbePicker.scala:69:28] wire [5:0] _picker_auto_in_1_d_bits_source; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_bits_denied; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_in_1_d_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_a_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_d_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_0_d_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_0_d_bits_size; // @[ProbePicker.scala:69:28] wire [5:0] _picker_auto_in_0_d_bits_source; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_d_bits_denied; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_in_0_d_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_d_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_4_a_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_4_a_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_4_a_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_4_a_bits_size; // @[ProbePicker.scala:69:28] wire [5:0] _picker_auto_out_4_a_bits_source; // @[ProbePicker.scala:69:28] wire [27:0] _picker_auto_out_4_a_bits_address; // @[ProbePicker.scala:69:28] wire [7:0] _picker_auto_out_4_a_bits_mask; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_out_4_a_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_out_4_a_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_4_d_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_out_3_a_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_3_a_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_3_a_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_3_a_bits_size; // @[ProbePicker.scala:69:28] wire [5:0] _picker_auto_out_3_a_bits_source; // @[ProbePicker.scala:69:28] wire [31:0] _picker_auto_out_3_a_bits_address; // @[ProbePicker.scala:69:28] wire [7:0] _picker_auto_out_3_a_bits_mask; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_out_3_a_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_out_3_a_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_3_d_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_out_2_a_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_2_a_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_2_a_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_2_a_bits_size; // @[ProbePicker.scala:69:28] wire [5:0] _picker_auto_out_2_a_bits_source; // @[ProbePicker.scala:69:28] wire [31:0] _picker_auto_out_2_a_bits_address; // @[ProbePicker.scala:69:28] wire [7:0] _picker_auto_out_2_a_bits_mask; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_out_2_a_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_out_2_a_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_2_d_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_out_1_a_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_1_a_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_1_a_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_1_a_bits_size; // @[ProbePicker.scala:69:28] wire [5:0] _picker_auto_out_1_a_bits_source; // @[ProbePicker.scala:69:28] wire [31:0] _picker_auto_out_1_a_bits_address; // @[ProbePicker.scala:69:28] wire [7:0] _picker_auto_out_1_a_bits_mask; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_out_1_a_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_out_1_a_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_1_d_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_out_0_a_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_0_a_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_0_a_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_0_a_bits_size; // @[ProbePicker.scala:69:28] wire [5:0] _picker_auto_out_0_a_bits_source; // @[ProbePicker.scala:69:28] wire [31:0] _picker_auto_out_0_a_bits_address; // @[ProbePicker.scala:69:28] wire [7:0] _picker_auto_out_0_a_bits_mask; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_out_0_a_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_out_0_a_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_0_d_ready; // @[ProbePicker.scala:69:28] wire _memory_bus_noc_auto_out_4_a_valid; // @[Buses.scala:90:49] wire [2:0] _memory_bus_noc_auto_out_4_a_bits_opcode; // @[Buses.scala:90:49] wire [2:0] _memory_bus_noc_auto_out_4_a_bits_param; // @[Buses.scala:90:49] wire [2:0] _memory_bus_noc_auto_out_4_a_bits_size; // @[Buses.scala:90:49] wire [5:0] _memory_bus_noc_auto_out_4_a_bits_source; // @[Buses.scala:90:49] wire [27:0] _memory_bus_noc_auto_out_4_a_bits_address; // @[Buses.scala:90:49] wire [7:0] _memory_bus_noc_auto_out_4_a_bits_mask; // @[Buses.scala:90:49] wire [63:0] _memory_bus_noc_auto_out_4_a_bits_data; // @[Buses.scala:90:49] wire _memory_bus_noc_auto_out_4_a_bits_corrupt; // @[Buses.scala:90:49] wire _memory_bus_noc_auto_out_4_d_ready; // @[Buses.scala:90:49] wire _memory_bus_noc_auto_out_3_a_valid; // @[Buses.scala:90:49] wire [2:0] _memory_bus_noc_auto_out_3_a_bits_opcode; // @[Buses.scala:90:49] wire [2:0] _memory_bus_noc_auto_out_3_a_bits_param; // @[Buses.scala:90:49] wire [2:0] _memory_bus_noc_auto_out_3_a_bits_size; // @[Buses.scala:90:49] wire [5:0] _memory_bus_noc_auto_out_3_a_bits_source; // @[Buses.scala:90:49] wire [31:0] _memory_bus_noc_auto_out_3_a_bits_address; // @[Buses.scala:90:49] wire [7:0] _memory_bus_noc_auto_out_3_a_bits_mask; // @[Buses.scala:90:49] wire [63:0] _memory_bus_noc_auto_out_3_a_bits_data; // @[Buses.scala:90:49] wire _memory_bus_noc_auto_out_3_a_bits_corrupt; // @[Buses.scala:90:49] wire _memory_bus_noc_auto_out_3_d_ready; // @[Buses.scala:90:49] wire _memory_bus_noc_auto_out_2_a_valid; // @[Buses.scala:90:49] wire [2:0] _memory_bus_noc_auto_out_2_a_bits_opcode; // @[Buses.scala:90:49] wire [2:0] _memory_bus_noc_auto_out_2_a_bits_param; // @[Buses.scala:90:49] wire [2:0] _memory_bus_noc_auto_out_2_a_bits_size; // @[Buses.scala:90:49] wire [5:0] _memory_bus_noc_auto_out_2_a_bits_source; // @[Buses.scala:90:49] wire [31:0] _memory_bus_noc_auto_out_2_a_bits_address; // @[Buses.scala:90:49] wire [7:0] _memory_bus_noc_auto_out_2_a_bits_mask; // @[Buses.scala:90:49] wire [63:0] _memory_bus_noc_auto_out_2_a_bits_data; // @[Buses.scala:90:49] wire _memory_bus_noc_auto_out_2_a_bits_corrupt; // @[Buses.scala:90:49] wire _memory_bus_noc_auto_out_2_d_ready; // @[Buses.scala:90:49] wire _memory_bus_noc_auto_out_1_a_valid; // @[Buses.scala:90:49] wire [2:0] _memory_bus_noc_auto_out_1_a_bits_opcode; // @[Buses.scala:90:49] wire [2:0] _memory_bus_noc_auto_out_1_a_bits_param; // @[Buses.scala:90:49] wire [2:0] _memory_bus_noc_auto_out_1_a_bits_size; // @[Buses.scala:90:49] wire [5:0] _memory_bus_noc_auto_out_1_a_bits_source; // @[Buses.scala:90:49] wire [31:0] _memory_bus_noc_auto_out_1_a_bits_address; // @[Buses.scala:90:49] wire [7:0] _memory_bus_noc_auto_out_1_a_bits_mask; // @[Buses.scala:90:49] wire [63:0] _memory_bus_noc_auto_out_1_a_bits_data; // @[Buses.scala:90:49] wire _memory_bus_noc_auto_out_1_a_bits_corrupt; // @[Buses.scala:90:49] wire _memory_bus_noc_auto_out_1_d_ready; // @[Buses.scala:90:49] wire _memory_bus_noc_auto_out_0_a_valid; // @[Buses.scala:90:49] wire [2:0] _memory_bus_noc_auto_out_0_a_bits_opcode; // @[Buses.scala:90:49] wire [2:0] _memory_bus_noc_auto_out_0_a_bits_param; // @[Buses.scala:90:49] wire [2:0] _memory_bus_noc_auto_out_0_a_bits_size; // @[Buses.scala:90:49] wire [5:0] _memory_bus_noc_auto_out_0_a_bits_source; // @[Buses.scala:90:49] wire [31:0] _memory_bus_noc_auto_out_0_a_bits_address; // @[Buses.scala:90:49] wire [7:0] _memory_bus_noc_auto_out_0_a_bits_mask; // @[Buses.scala:90:49] wire [63:0] _memory_bus_noc_auto_out_0_a_bits_data; // @[Buses.scala:90:49] wire _memory_bus_noc_auto_out_0_a_bits_corrupt; // @[Buses.scala:90:49] wire _memory_bus_noc_auto_out_0_d_ready; // @[Buses.scala:90:49] wire _fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114] wire _fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114] FixedClockBroadcast_3 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (auto_mbus_clock_groups_in_member_mbus_0_clock), .auto_anon_in_reset (auto_mbus_clock_groups_in_member_mbus_0_reset), .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock), .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset), .auto_anon_out_0_clock (_fixedClockNode_auto_anon_out_0_clock), .auto_anon_out_0_reset (_fixedClockNode_auto_anon_out_0_reset) ); // @[ClockGroup.scala:115:114] TLNoC_2 memory_bus_noc ( // @[Buses.scala:90:49] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_in_3_a_ready (auto_bus_xing_in_3_a_ready), .auto_in_3_a_valid (auto_bus_xing_in_3_a_valid), .auto_in_3_a_bits_opcode (auto_bus_xing_in_3_a_bits_opcode), .auto_in_3_a_bits_param (auto_bus_xing_in_3_a_bits_param), .auto_in_3_a_bits_size (auto_bus_xing_in_3_a_bits_size), .auto_in_3_a_bits_source (auto_bus_xing_in_3_a_bits_source), .auto_in_3_a_bits_address (auto_bus_xing_in_3_a_bits_address), .auto_in_3_a_bits_mask (auto_bus_xing_in_3_a_bits_mask), .auto_in_3_a_bits_data (auto_bus_xing_in_3_a_bits_data), .auto_in_3_a_bits_corrupt (auto_bus_xing_in_3_a_bits_corrupt), .auto_in_3_d_ready (auto_bus_xing_in_3_d_ready), .auto_in_3_d_valid (auto_bus_xing_in_3_d_valid), .auto_in_3_d_bits_opcode (auto_bus_xing_in_3_d_bits_opcode), .auto_in_3_d_bits_param (auto_bus_xing_in_3_d_bits_param), .auto_in_3_d_bits_size (auto_bus_xing_in_3_d_bits_size), .auto_in_3_d_bits_source (auto_bus_xing_in_3_d_bits_source), .auto_in_3_d_bits_sink (auto_bus_xing_in_3_d_bits_sink), .auto_in_3_d_bits_denied (auto_bus_xing_in_3_d_bits_denied), .auto_in_3_d_bits_data (auto_bus_xing_in_3_d_bits_data), .auto_in_3_d_bits_corrupt (auto_bus_xing_in_3_d_bits_corrupt), .auto_in_2_a_ready (auto_bus_xing_in_2_a_ready), .auto_in_2_a_valid (auto_bus_xing_in_2_a_valid), .auto_in_2_a_bits_opcode (auto_bus_xing_in_2_a_bits_opcode), .auto_in_2_a_bits_param (auto_bus_xing_in_2_a_bits_param), .auto_in_2_a_bits_size (auto_bus_xing_in_2_a_bits_size), .auto_in_2_a_bits_source (auto_bus_xing_in_2_a_bits_source), .auto_in_2_a_bits_address (auto_bus_xing_in_2_a_bits_address), .auto_in_2_a_bits_mask (auto_bus_xing_in_2_a_bits_mask), .auto_in_2_a_bits_data (auto_bus_xing_in_2_a_bits_data), .auto_in_2_a_bits_corrupt (auto_bus_xing_in_2_a_bits_corrupt), .auto_in_2_d_ready (auto_bus_xing_in_2_d_ready), .auto_in_2_d_valid (auto_bus_xing_in_2_d_valid), .auto_in_2_d_bits_opcode (auto_bus_xing_in_2_d_bits_opcode), .auto_in_2_d_bits_param (auto_bus_xing_in_2_d_bits_param), .auto_in_2_d_bits_size (auto_bus_xing_in_2_d_bits_size), .auto_in_2_d_bits_source (auto_bus_xing_in_2_d_bits_source), .auto_in_2_d_bits_sink (auto_bus_xing_in_2_d_bits_sink), .auto_in_2_d_bits_denied (auto_bus_xing_in_2_d_bits_denied), .auto_in_2_d_bits_data (auto_bus_xing_in_2_d_bits_data), .auto_in_2_d_bits_corrupt (auto_bus_xing_in_2_d_bits_corrupt), .auto_in_1_a_ready (auto_bus_xing_in_1_a_ready), .auto_in_1_a_valid (auto_bus_xing_in_1_a_valid), .auto_in_1_a_bits_opcode (auto_bus_xing_in_1_a_bits_opcode), .auto_in_1_a_bits_param (auto_bus_xing_in_1_a_bits_param), .auto_in_1_a_bits_size (auto_bus_xing_in_1_a_bits_size), .auto_in_1_a_bits_source (auto_bus_xing_in_1_a_bits_source), .auto_in_1_a_bits_address (auto_bus_xing_in_1_a_bits_address), .auto_in_1_a_bits_mask (auto_bus_xing_in_1_a_bits_mask), .auto_in_1_a_bits_data (auto_bus_xing_in_1_a_bits_data), .auto_in_1_a_bits_corrupt (auto_bus_xing_in_1_a_bits_corrupt), .auto_in_1_d_ready (auto_bus_xing_in_1_d_ready), .auto_in_1_d_valid (auto_bus_xing_in_1_d_valid), .auto_in_1_d_bits_opcode (auto_bus_xing_in_1_d_bits_opcode), .auto_in_1_d_bits_param (auto_bus_xing_in_1_d_bits_param), .auto_in_1_d_bits_size (auto_bus_xing_in_1_d_bits_size), .auto_in_1_d_bits_source (auto_bus_xing_in_1_d_bits_source), .auto_in_1_d_bits_sink (auto_bus_xing_in_1_d_bits_sink), .auto_in_1_d_bits_denied (auto_bus_xing_in_1_d_bits_denied), .auto_in_1_d_bits_data (auto_bus_xing_in_1_d_bits_data), .auto_in_1_d_bits_corrupt (auto_bus_xing_in_1_d_bits_corrupt), .auto_in_0_a_ready (auto_bus_xing_in_0_a_ready), .auto_in_0_a_valid (auto_bus_xing_in_0_a_valid), .auto_in_0_a_bits_opcode (auto_bus_xing_in_0_a_bits_opcode), .auto_in_0_a_bits_param (auto_bus_xing_in_0_a_bits_param), .auto_in_0_a_bits_size (auto_bus_xing_in_0_a_bits_size), .auto_in_0_a_bits_source (auto_bus_xing_in_0_a_bits_source), .auto_in_0_a_bits_address (auto_bus_xing_in_0_a_bits_address), .auto_in_0_a_bits_mask (auto_bus_xing_in_0_a_bits_mask), .auto_in_0_a_bits_data (auto_bus_xing_in_0_a_bits_data), .auto_in_0_a_bits_corrupt (auto_bus_xing_in_0_a_bits_corrupt), .auto_in_0_d_ready (auto_bus_xing_in_0_d_ready), .auto_in_0_d_valid (auto_bus_xing_in_0_d_valid), .auto_in_0_d_bits_opcode (auto_bus_xing_in_0_d_bits_opcode), .auto_in_0_d_bits_param (auto_bus_xing_in_0_d_bits_param), .auto_in_0_d_bits_size (auto_bus_xing_in_0_d_bits_size), .auto_in_0_d_bits_source (auto_bus_xing_in_0_d_bits_source), .auto_in_0_d_bits_sink (auto_bus_xing_in_0_d_bits_sink), .auto_in_0_d_bits_denied (auto_bus_xing_in_0_d_bits_denied), .auto_in_0_d_bits_data (auto_bus_xing_in_0_d_bits_data), .auto_in_0_d_bits_corrupt (auto_bus_xing_in_0_d_bits_corrupt), .auto_out_4_a_ready (_picker_auto_in_4_a_ready), // @[ProbePicker.scala:69:28] .auto_out_4_a_valid (_memory_bus_noc_auto_out_4_a_valid), .auto_out_4_a_bits_opcode (_memory_bus_noc_auto_out_4_a_bits_opcode), .auto_out_4_a_bits_param (_memory_bus_noc_auto_out_4_a_bits_param), .auto_out_4_a_bits_size (_memory_bus_noc_auto_out_4_a_bits_size), .auto_out_4_a_bits_source (_memory_bus_noc_auto_out_4_a_bits_source), .auto_out_4_a_bits_address (_memory_bus_noc_auto_out_4_a_bits_address), .auto_out_4_a_bits_mask (_memory_bus_noc_auto_out_4_a_bits_mask), .auto_out_4_a_bits_data (_memory_bus_noc_auto_out_4_a_bits_data), .auto_out_4_a_bits_corrupt (_memory_bus_noc_auto_out_4_a_bits_corrupt), .auto_out_4_d_ready (_memory_bus_noc_auto_out_4_d_ready), .auto_out_4_d_valid (_picker_auto_in_4_d_valid), // @[ProbePicker.scala:69:28] .auto_out_4_d_bits_opcode (_picker_auto_in_4_d_bits_opcode), // @[ProbePicker.scala:69:28] .auto_out_4_d_bits_param (_picker_auto_in_4_d_bits_param), // @[ProbePicker.scala:69:28] .auto_out_4_d_bits_size (_picker_auto_in_4_d_bits_size), // @[ProbePicker.scala:69:28] .auto_out_4_d_bits_source (_picker_auto_in_4_d_bits_source), // @[ProbePicker.scala:69:28] .auto_out_4_d_bits_sink (_picker_auto_in_4_d_bits_sink), // @[ProbePicker.scala:69:28] .auto_out_4_d_bits_denied (_picker_auto_in_4_d_bits_denied), // @[ProbePicker.scala:69:28] .auto_out_4_d_bits_data (_picker_auto_in_4_d_bits_data), // @[ProbePicker.scala:69:28] .auto_out_4_d_bits_corrupt (_picker_auto_in_4_d_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_out_3_a_ready (_picker_auto_in_3_a_ready), // @[ProbePicker.scala:69:28] .auto_out_3_a_valid (_memory_bus_noc_auto_out_3_a_valid), .auto_out_3_a_bits_opcode (_memory_bus_noc_auto_out_3_a_bits_opcode), .auto_out_3_a_bits_param (_memory_bus_noc_auto_out_3_a_bits_param), .auto_out_3_a_bits_size (_memory_bus_noc_auto_out_3_a_bits_size), .auto_out_3_a_bits_source (_memory_bus_noc_auto_out_3_a_bits_source), .auto_out_3_a_bits_address (_memory_bus_noc_auto_out_3_a_bits_address), .auto_out_3_a_bits_mask (_memory_bus_noc_auto_out_3_a_bits_mask), .auto_out_3_a_bits_data (_memory_bus_noc_auto_out_3_a_bits_data), .auto_out_3_a_bits_corrupt (_memory_bus_noc_auto_out_3_a_bits_corrupt), .auto_out_3_d_ready (_memory_bus_noc_auto_out_3_d_ready), .auto_out_3_d_valid (_picker_auto_in_3_d_valid), // @[ProbePicker.scala:69:28] .auto_out_3_d_bits_opcode (_picker_auto_in_3_d_bits_opcode), // @[ProbePicker.scala:69:28] .auto_out_3_d_bits_size (_picker_auto_in_3_d_bits_size), // @[ProbePicker.scala:69:28] .auto_out_3_d_bits_source (_picker_auto_in_3_d_bits_source), // @[ProbePicker.scala:69:28] .auto_out_3_d_bits_denied (_picker_auto_in_3_d_bits_denied), // @[ProbePicker.scala:69:28] .auto_out_3_d_bits_data (_picker_auto_in_3_d_bits_data), // @[ProbePicker.scala:69:28] .auto_out_3_d_bits_corrupt (_picker_auto_in_3_d_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_out_2_a_ready (_picker_auto_in_2_a_ready), // @[ProbePicker.scala:69:28] .auto_out_2_a_valid (_memory_bus_noc_auto_out_2_a_valid), .auto_out_2_a_bits_opcode (_memory_bus_noc_auto_out_2_a_bits_opcode), .auto_out_2_a_bits_param (_memory_bus_noc_auto_out_2_a_bits_param), .auto_out_2_a_bits_size (_memory_bus_noc_auto_out_2_a_bits_size), .auto_out_2_a_bits_source (_memory_bus_noc_auto_out_2_a_bits_source), .auto_out_2_a_bits_address (_memory_bus_noc_auto_out_2_a_bits_address), .auto_out_2_a_bits_mask (_memory_bus_noc_auto_out_2_a_bits_mask), .auto_out_2_a_bits_data (_memory_bus_noc_auto_out_2_a_bits_data), .auto_out_2_a_bits_corrupt (_memory_bus_noc_auto_out_2_a_bits_corrupt), .auto_out_2_d_ready (_memory_bus_noc_auto_out_2_d_ready), .auto_out_2_d_valid (_picker_auto_in_2_d_valid), // @[ProbePicker.scala:69:28] .auto_out_2_d_bits_opcode (_picker_auto_in_2_d_bits_opcode), // @[ProbePicker.scala:69:28] .auto_out_2_d_bits_size (_picker_auto_in_2_d_bits_size), // @[ProbePicker.scala:69:28] .auto_out_2_d_bits_source (_picker_auto_in_2_d_bits_source), // @[ProbePicker.scala:69:28] .auto_out_2_d_bits_denied (_picker_auto_in_2_d_bits_denied), // @[ProbePicker.scala:69:28] .auto_out_2_d_bits_data (_picker_auto_in_2_d_bits_data), // @[ProbePicker.scala:69:28] .auto_out_2_d_bits_corrupt (_picker_auto_in_2_d_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_out_1_a_ready (_picker_auto_in_1_a_ready), // @[ProbePicker.scala:69:28] .auto_out_1_a_valid (_memory_bus_noc_auto_out_1_a_valid), .auto_out_1_a_bits_opcode (_memory_bus_noc_auto_out_1_a_bits_opcode), .auto_out_1_a_bits_param (_memory_bus_noc_auto_out_1_a_bits_param), .auto_out_1_a_bits_size (_memory_bus_noc_auto_out_1_a_bits_size), .auto_out_1_a_bits_source (_memory_bus_noc_auto_out_1_a_bits_source), .auto_out_1_a_bits_address (_memory_bus_noc_auto_out_1_a_bits_address), .auto_out_1_a_bits_mask (_memory_bus_noc_auto_out_1_a_bits_mask), .auto_out_1_a_bits_data (_memory_bus_noc_auto_out_1_a_bits_data), .auto_out_1_a_bits_corrupt (_memory_bus_noc_auto_out_1_a_bits_corrupt), .auto_out_1_d_ready (_memory_bus_noc_auto_out_1_d_ready), .auto_out_1_d_valid (_picker_auto_in_1_d_valid), // @[ProbePicker.scala:69:28] .auto_out_1_d_bits_opcode (_picker_auto_in_1_d_bits_opcode), // @[ProbePicker.scala:69:28] .auto_out_1_d_bits_size (_picker_auto_in_1_d_bits_size), // @[ProbePicker.scala:69:28] .auto_out_1_d_bits_source (_picker_auto_in_1_d_bits_source), // @[ProbePicker.scala:69:28] .auto_out_1_d_bits_denied (_picker_auto_in_1_d_bits_denied), // @[ProbePicker.scala:69:28] .auto_out_1_d_bits_data (_picker_auto_in_1_d_bits_data), // @[ProbePicker.scala:69:28] .auto_out_1_d_bits_corrupt (_picker_auto_in_1_d_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_out_0_a_ready (_picker_auto_in_0_a_ready), // @[ProbePicker.scala:69:28] .auto_out_0_a_valid (_memory_bus_noc_auto_out_0_a_valid), .auto_out_0_a_bits_opcode (_memory_bus_noc_auto_out_0_a_bits_opcode), .auto_out_0_a_bits_param (_memory_bus_noc_auto_out_0_a_bits_param), .auto_out_0_a_bits_size (_memory_bus_noc_auto_out_0_a_bits_size), .auto_out_0_a_bits_source (_memory_bus_noc_auto_out_0_a_bits_source), .auto_out_0_a_bits_address (_memory_bus_noc_auto_out_0_a_bits_address), .auto_out_0_a_bits_mask (_memory_bus_noc_auto_out_0_a_bits_mask), .auto_out_0_a_bits_data (_memory_bus_noc_auto_out_0_a_bits_data), .auto_out_0_a_bits_corrupt (_memory_bus_noc_auto_out_0_a_bits_corrupt), .auto_out_0_d_ready (_memory_bus_noc_auto_out_0_d_ready), .auto_out_0_d_valid (_picker_auto_in_0_d_valid), // @[ProbePicker.scala:69:28] .auto_out_0_d_bits_opcode (_picker_auto_in_0_d_bits_opcode), // @[ProbePicker.scala:69:28] .auto_out_0_d_bits_size (_picker_auto_in_0_d_bits_size), // @[ProbePicker.scala:69:28] .auto_out_0_d_bits_source (_picker_auto_in_0_d_bits_source), // @[ProbePicker.scala:69:28] .auto_out_0_d_bits_denied (_picker_auto_in_0_d_bits_denied), // @[ProbePicker.scala:69:28] .auto_out_0_d_bits_data (_picker_auto_in_0_d_bits_data), // @[ProbePicker.scala:69:28] .auto_out_0_d_bits_corrupt (_picker_auto_in_0_d_bits_corrupt) // @[ProbePicker.scala:69:28] ); // @[Buses.scala:90:49] ProbePicker picker ( // @[ProbePicker.scala:69:28] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_in_4_a_ready (_picker_auto_in_4_a_ready), .auto_in_4_a_valid (_memory_bus_noc_auto_out_4_a_valid), // @[Buses.scala:90:49] .auto_in_4_a_bits_opcode (_memory_bus_noc_auto_out_4_a_bits_opcode), // @[Buses.scala:90:49] .auto_in_4_a_bits_param (_memory_bus_noc_auto_out_4_a_bits_param), // @[Buses.scala:90:49] .auto_in_4_a_bits_size (_memory_bus_noc_auto_out_4_a_bits_size), // @[Buses.scala:90:49] .auto_in_4_a_bits_source (_memory_bus_noc_auto_out_4_a_bits_source), // @[Buses.scala:90:49] .auto_in_4_a_bits_address (_memory_bus_noc_auto_out_4_a_bits_address), // @[Buses.scala:90:49] .auto_in_4_a_bits_mask (_memory_bus_noc_auto_out_4_a_bits_mask), // @[Buses.scala:90:49] .auto_in_4_a_bits_data (_memory_bus_noc_auto_out_4_a_bits_data), // @[Buses.scala:90:49] .auto_in_4_a_bits_corrupt (_memory_bus_noc_auto_out_4_a_bits_corrupt), // @[Buses.scala:90:49] .auto_in_4_d_ready (_memory_bus_noc_auto_out_4_d_ready), // @[Buses.scala:90:49] .auto_in_4_d_valid (_picker_auto_in_4_d_valid), .auto_in_4_d_bits_opcode (_picker_auto_in_4_d_bits_opcode), .auto_in_4_d_bits_param (_picker_auto_in_4_d_bits_param), .auto_in_4_d_bits_size (_picker_auto_in_4_d_bits_size), .auto_in_4_d_bits_source (_picker_auto_in_4_d_bits_source), .auto_in_4_d_bits_sink (_picker_auto_in_4_d_bits_sink), .auto_in_4_d_bits_denied (_picker_auto_in_4_d_bits_denied), .auto_in_4_d_bits_data (_picker_auto_in_4_d_bits_data), .auto_in_4_d_bits_corrupt (_picker_auto_in_4_d_bits_corrupt), .auto_in_3_a_ready (_picker_auto_in_3_a_ready), .auto_in_3_a_valid (_memory_bus_noc_auto_out_3_a_valid), // @[Buses.scala:90:49] .auto_in_3_a_bits_opcode (_memory_bus_noc_auto_out_3_a_bits_opcode), // @[Buses.scala:90:49] .auto_in_3_a_bits_param (_memory_bus_noc_auto_out_3_a_bits_param), // @[Buses.scala:90:49] .auto_in_3_a_bits_size (_memory_bus_noc_auto_out_3_a_bits_size), // @[Buses.scala:90:49] .auto_in_3_a_bits_source (_memory_bus_noc_auto_out_3_a_bits_source), // @[Buses.scala:90:49] .auto_in_3_a_bits_address (_memory_bus_noc_auto_out_3_a_bits_address), // @[Buses.scala:90:49] .auto_in_3_a_bits_mask (_memory_bus_noc_auto_out_3_a_bits_mask), // @[Buses.scala:90:49] .auto_in_3_a_bits_data (_memory_bus_noc_auto_out_3_a_bits_data), // @[Buses.scala:90:49] .auto_in_3_a_bits_corrupt (_memory_bus_noc_auto_out_3_a_bits_corrupt), // @[Buses.scala:90:49] .auto_in_3_d_ready (_memory_bus_noc_auto_out_3_d_ready), // @[Buses.scala:90:49] .auto_in_3_d_valid (_picker_auto_in_3_d_valid), .auto_in_3_d_bits_opcode (_picker_auto_in_3_d_bits_opcode), .auto_in_3_d_bits_size (_picker_auto_in_3_d_bits_size), .auto_in_3_d_bits_source (_picker_auto_in_3_d_bits_source), .auto_in_3_d_bits_denied (_picker_auto_in_3_d_bits_denied), .auto_in_3_d_bits_data (_picker_auto_in_3_d_bits_data), .auto_in_3_d_bits_corrupt (_picker_auto_in_3_d_bits_corrupt), .auto_in_2_a_ready (_picker_auto_in_2_a_ready), .auto_in_2_a_valid (_memory_bus_noc_auto_out_2_a_valid), // @[Buses.scala:90:49] .auto_in_2_a_bits_opcode (_memory_bus_noc_auto_out_2_a_bits_opcode), // @[Buses.scala:90:49] .auto_in_2_a_bits_param (_memory_bus_noc_auto_out_2_a_bits_param), // @[Buses.scala:90:49] .auto_in_2_a_bits_size (_memory_bus_noc_auto_out_2_a_bits_size), // @[Buses.scala:90:49] .auto_in_2_a_bits_source (_memory_bus_noc_auto_out_2_a_bits_source), // @[Buses.scala:90:49] .auto_in_2_a_bits_address (_memory_bus_noc_auto_out_2_a_bits_address), // @[Buses.scala:90:49] .auto_in_2_a_bits_mask (_memory_bus_noc_auto_out_2_a_bits_mask), // @[Buses.scala:90:49] .auto_in_2_a_bits_data (_memory_bus_noc_auto_out_2_a_bits_data), // @[Buses.scala:90:49] .auto_in_2_a_bits_corrupt (_memory_bus_noc_auto_out_2_a_bits_corrupt), // @[Buses.scala:90:49] .auto_in_2_d_ready (_memory_bus_noc_auto_out_2_d_ready), // @[Buses.scala:90:49] .auto_in_2_d_valid (_picker_auto_in_2_d_valid), .auto_in_2_d_bits_opcode (_picker_auto_in_2_d_bits_opcode), .auto_in_2_d_bits_size (_picker_auto_in_2_d_bits_size), .auto_in_2_d_bits_source (_picker_auto_in_2_d_bits_source), .auto_in_2_d_bits_denied (_picker_auto_in_2_d_bits_denied), .auto_in_2_d_bits_data (_picker_auto_in_2_d_bits_data), .auto_in_2_d_bits_corrupt (_picker_auto_in_2_d_bits_corrupt), .auto_in_1_a_ready (_picker_auto_in_1_a_ready), .auto_in_1_a_valid (_memory_bus_noc_auto_out_1_a_valid), // @[Buses.scala:90:49] .auto_in_1_a_bits_opcode (_memory_bus_noc_auto_out_1_a_bits_opcode), // @[Buses.scala:90:49] .auto_in_1_a_bits_param (_memory_bus_noc_auto_out_1_a_bits_param), // @[Buses.scala:90:49] .auto_in_1_a_bits_size (_memory_bus_noc_auto_out_1_a_bits_size), // @[Buses.scala:90:49] .auto_in_1_a_bits_source (_memory_bus_noc_auto_out_1_a_bits_source), // @[Buses.scala:90:49] .auto_in_1_a_bits_address (_memory_bus_noc_auto_out_1_a_bits_address), // @[Buses.scala:90:49] .auto_in_1_a_bits_mask (_memory_bus_noc_auto_out_1_a_bits_mask), // @[Buses.scala:90:49] .auto_in_1_a_bits_data (_memory_bus_noc_auto_out_1_a_bits_data), // @[Buses.scala:90:49] .auto_in_1_a_bits_corrupt (_memory_bus_noc_auto_out_1_a_bits_corrupt), // @[Buses.scala:90:49] .auto_in_1_d_ready (_memory_bus_noc_auto_out_1_d_ready), // @[Buses.scala:90:49] .auto_in_1_d_valid (_picker_auto_in_1_d_valid), .auto_in_1_d_bits_opcode (_picker_auto_in_1_d_bits_opcode), .auto_in_1_d_bits_size (_picker_auto_in_1_d_bits_size), .auto_in_1_d_bits_source (_picker_auto_in_1_d_bits_source), .auto_in_1_d_bits_denied (_picker_auto_in_1_d_bits_denied), .auto_in_1_d_bits_data (_picker_auto_in_1_d_bits_data), .auto_in_1_d_bits_corrupt (_picker_auto_in_1_d_bits_corrupt), .auto_in_0_a_ready (_picker_auto_in_0_a_ready), .auto_in_0_a_valid (_memory_bus_noc_auto_out_0_a_valid), // @[Buses.scala:90:49] .auto_in_0_a_bits_opcode (_memory_bus_noc_auto_out_0_a_bits_opcode), // @[Buses.scala:90:49] .auto_in_0_a_bits_param (_memory_bus_noc_auto_out_0_a_bits_param), // @[Buses.scala:90:49] .auto_in_0_a_bits_size (_memory_bus_noc_auto_out_0_a_bits_size), // @[Buses.scala:90:49] .auto_in_0_a_bits_source (_memory_bus_noc_auto_out_0_a_bits_source), // @[Buses.scala:90:49] .auto_in_0_a_bits_address (_memory_bus_noc_auto_out_0_a_bits_address), // @[Buses.scala:90:49] .auto_in_0_a_bits_mask (_memory_bus_noc_auto_out_0_a_bits_mask), // @[Buses.scala:90:49] .auto_in_0_a_bits_data (_memory_bus_noc_auto_out_0_a_bits_data), // @[Buses.scala:90:49] .auto_in_0_a_bits_corrupt (_memory_bus_noc_auto_out_0_a_bits_corrupt), // @[Buses.scala:90:49] .auto_in_0_d_ready (_memory_bus_noc_auto_out_0_d_ready), // @[Buses.scala:90:49] .auto_in_0_d_valid (_picker_auto_in_0_d_valid), .auto_in_0_d_bits_opcode (_picker_auto_in_0_d_bits_opcode), .auto_in_0_d_bits_size (_picker_auto_in_0_d_bits_size), .auto_in_0_d_bits_source (_picker_auto_in_0_d_bits_source), .auto_in_0_d_bits_denied (_picker_auto_in_0_d_bits_denied), .auto_in_0_d_bits_data (_picker_auto_in_0_d_bits_data), .auto_in_0_d_bits_corrupt (_picker_auto_in_0_d_bits_corrupt), .auto_out_4_a_ready (_buffer_1_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_out_4_a_valid (_picker_auto_out_4_a_valid), .auto_out_4_a_bits_opcode (_picker_auto_out_4_a_bits_opcode), .auto_out_4_a_bits_param (_picker_auto_out_4_a_bits_param), .auto_out_4_a_bits_size (_picker_auto_out_4_a_bits_size), .auto_out_4_a_bits_source (_picker_auto_out_4_a_bits_source), .auto_out_4_a_bits_address (_picker_auto_out_4_a_bits_address), .auto_out_4_a_bits_mask (_picker_auto_out_4_a_bits_mask), .auto_out_4_a_bits_data (_picker_auto_out_4_a_bits_data), .auto_out_4_a_bits_corrupt (_picker_auto_out_4_a_bits_corrupt), .auto_out_4_d_ready (_picker_auto_out_4_d_ready), .auto_out_4_d_valid (_buffer_1_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_out_4_d_bits_opcode (_buffer_1_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_out_4_d_bits_param (_buffer_1_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_out_4_d_bits_size (_buffer_1_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_out_4_d_bits_source (_buffer_1_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_out_4_d_bits_sink (_buffer_1_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_out_4_d_bits_denied (_buffer_1_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_out_4_d_bits_data (_buffer_1_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_out_4_d_bits_corrupt (_buffer_1_auto_in_d_bits_corrupt), // @[Buffer.scala:75:28] .auto_out_3_a_ready (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_out_3_a_valid (_picker_auto_out_3_a_valid), .auto_out_3_a_bits_opcode (_picker_auto_out_3_a_bits_opcode), .auto_out_3_a_bits_param (_picker_auto_out_3_a_bits_param), .auto_out_3_a_bits_size (_picker_auto_out_3_a_bits_size), .auto_out_3_a_bits_source (_picker_auto_out_3_a_bits_source), .auto_out_3_a_bits_address (_picker_auto_out_3_a_bits_address), .auto_out_3_a_bits_mask (_picker_auto_out_3_a_bits_mask), .auto_out_3_a_bits_data (_picker_auto_out_3_a_bits_data), .auto_out_3_a_bits_corrupt (_picker_auto_out_3_a_bits_corrupt), .auto_out_3_d_ready (_picker_auto_out_3_d_ready), .auto_out_3_d_valid (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_out_3_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_out_3_d_bits_size (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_out_3_d_bits_source (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_out_3_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_out_3_d_bits_data (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_out_3_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27] .auto_out_2_a_ready (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_out_2_a_valid (_picker_auto_out_2_a_valid), .auto_out_2_a_bits_opcode (_picker_auto_out_2_a_bits_opcode), .auto_out_2_a_bits_param (_picker_auto_out_2_a_bits_param), .auto_out_2_a_bits_size (_picker_auto_out_2_a_bits_size), .auto_out_2_a_bits_source (_picker_auto_out_2_a_bits_source), .auto_out_2_a_bits_address (_picker_auto_out_2_a_bits_address), .auto_out_2_a_bits_mask (_picker_auto_out_2_a_bits_mask), .auto_out_2_a_bits_data (_picker_auto_out_2_a_bits_data), .auto_out_2_a_bits_corrupt (_picker_auto_out_2_a_bits_corrupt), .auto_out_2_d_ready (_picker_auto_out_2_d_ready), .auto_out_2_d_valid (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_out_2_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_out_2_d_bits_size (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_out_2_d_bits_source (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_out_2_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_out_2_d_bits_data (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_out_2_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27] .auto_out_1_a_ready (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_out_1_a_valid (_picker_auto_out_1_a_valid), .auto_out_1_a_bits_opcode (_picker_auto_out_1_a_bits_opcode), .auto_out_1_a_bits_param (_picker_auto_out_1_a_bits_param), .auto_out_1_a_bits_size (_picker_auto_out_1_a_bits_size), .auto_out_1_a_bits_source (_picker_auto_out_1_a_bits_source), .auto_out_1_a_bits_address (_picker_auto_out_1_a_bits_address), .auto_out_1_a_bits_mask (_picker_auto_out_1_a_bits_mask), .auto_out_1_a_bits_data (_picker_auto_out_1_a_bits_data), .auto_out_1_a_bits_corrupt (_picker_auto_out_1_a_bits_corrupt), .auto_out_1_d_ready (_picker_auto_out_1_d_ready), .auto_out_1_d_valid (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_out_1_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_out_1_d_bits_size (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_out_1_d_bits_source (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_out_1_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_out_1_d_bits_data (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_out_1_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27] .auto_out_0_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_out_0_a_valid (_picker_auto_out_0_a_valid), .auto_out_0_a_bits_opcode (_picker_auto_out_0_a_bits_opcode), .auto_out_0_a_bits_param (_picker_auto_out_0_a_bits_param), .auto_out_0_a_bits_size (_picker_auto_out_0_a_bits_size), .auto_out_0_a_bits_source (_picker_auto_out_0_a_bits_source), .auto_out_0_a_bits_address (_picker_auto_out_0_a_bits_address), .auto_out_0_a_bits_mask (_picker_auto_out_0_a_bits_mask), .auto_out_0_a_bits_data (_picker_auto_out_0_a_bits_data), .auto_out_0_a_bits_corrupt (_picker_auto_out_0_a_bits_corrupt), .auto_out_0_d_ready (_picker_auto_out_0_d_ready), .auto_out_0_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[ProbePicker.scala:69:28] TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 coupler_to_memory_controller_port_named_axi4 ( // @[LazyScope.scala:98:27] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_widget_anon_in_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_a_ready), .auto_widget_anon_in_a_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_valid), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_opcode), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_param (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_param), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_size), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_source), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_address (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_address), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_mask (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_mask), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_data), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_corrupt), // @[LazyScope.scala:98:27] .auto_widget_anon_in_d_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_d_ready), // @[LazyScope.scala:98:27] .auto_widget_anon_in_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_valid), .auto_widget_anon_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_opcode), .auto_widget_anon_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_size), .auto_widget_anon_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_source), .auto_widget_anon_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_denied), .auto_widget_anon_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_data), .auto_widget_anon_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_corrupt), .auto_axi4yank_out_aw_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_ready), .auto_axi4yank_out_aw_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_valid), .auto_axi4yank_out_aw_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_id), .auto_axi4yank_out_aw_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_addr), .auto_axi4yank_out_aw_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_len), .auto_axi4yank_out_aw_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_size), .auto_axi4yank_out_aw_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_burst), .auto_axi4yank_out_aw_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_lock), .auto_axi4yank_out_aw_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_cache), .auto_axi4yank_out_aw_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_prot), .auto_axi4yank_out_aw_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_aw_bits_qos), .auto_axi4yank_out_w_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_w_ready), .auto_axi4yank_out_w_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_w_valid), .auto_axi4yank_out_w_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_w_bits_data), .auto_axi4yank_out_w_bits_strb (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_w_bits_strb), .auto_axi4yank_out_w_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_w_bits_last), .auto_axi4yank_out_b_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_b_ready), .auto_axi4yank_out_b_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_b_valid), .auto_axi4yank_out_b_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_b_bits_id), .auto_axi4yank_out_b_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_b_bits_resp), .auto_axi4yank_out_ar_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_ready), .auto_axi4yank_out_ar_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_valid), .auto_axi4yank_out_ar_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_id), .auto_axi4yank_out_ar_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_addr), .auto_axi4yank_out_ar_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_len), .auto_axi4yank_out_ar_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_size), .auto_axi4yank_out_ar_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_burst), .auto_axi4yank_out_ar_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_lock), .auto_axi4yank_out_ar_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_cache), .auto_axi4yank_out_ar_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_prot), .auto_axi4yank_out_ar_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_ar_bits_qos), .auto_axi4yank_out_r_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_r_ready), .auto_axi4yank_out_r_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_r_valid), .auto_axi4yank_out_r_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_r_bits_id), .auto_axi4yank_out_r_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_r_bits_data), .auto_axi4yank_out_r_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_r_bits_resp), .auto_axi4yank_out_r_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_0_r_bits_last), .auto_tl_in_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready), .auto_tl_in_a_valid (_picker_auto_out_0_a_valid), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_opcode (_picker_auto_out_0_a_bits_opcode), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_param (_picker_auto_out_0_a_bits_param), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_size (_picker_auto_out_0_a_bits_size), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_source (_picker_auto_out_0_a_bits_source), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_address (_picker_auto_out_0_a_bits_address), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_mask (_picker_auto_out_0_a_bits_mask), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_data (_picker_auto_out_0_a_bits_data), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_corrupt (_picker_auto_out_0_a_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_tl_in_d_ready (_picker_auto_out_0_d_ready), // @[ProbePicker.scala:69:28] .auto_tl_in_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt), .auto_tl_out_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_a_ready), // @[LazyScope.scala:98:27] .auto_tl_out_a_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_valid), .auto_tl_out_a_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_opcode), .auto_tl_out_a_bits_param (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_param), .auto_tl_out_a_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_size), .auto_tl_out_a_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_source), .auto_tl_out_a_bits_address (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_address), .auto_tl_out_a_bits_mask (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_mask), .auto_tl_out_a_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_data), .auto_tl_out_a_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_corrupt), .auto_tl_out_d_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_d_ready), .auto_tl_out_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_valid), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4_1 coupler_to_memory_controller_port_named_axi4_1 ( // @[LazyScope.scala:98:27] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_widget_anon_in_a_ready (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_a_ready), .auto_widget_anon_in_a_valid (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_valid), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_opcode (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_opcode), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_param (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_param), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_size (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_size), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_source (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_source), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_address (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_address), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_mask (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_mask), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_data (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_data), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_corrupt), // @[LazyScope.scala:98:27] .auto_widget_anon_in_d_ready (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_d_ready), // @[LazyScope.scala:98:27] .auto_widget_anon_in_d_valid (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_valid), .auto_widget_anon_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_opcode), .auto_widget_anon_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_size), .auto_widget_anon_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_source), .auto_widget_anon_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_denied), .auto_widget_anon_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_data), .auto_widget_anon_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_corrupt), .auto_axi4yank_out_aw_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_ready), .auto_axi4yank_out_aw_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_valid), .auto_axi4yank_out_aw_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_id), .auto_axi4yank_out_aw_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_addr), .auto_axi4yank_out_aw_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_len), .auto_axi4yank_out_aw_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_size), .auto_axi4yank_out_aw_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_burst), .auto_axi4yank_out_aw_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_lock), .auto_axi4yank_out_aw_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_cache), .auto_axi4yank_out_aw_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_prot), .auto_axi4yank_out_aw_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_aw_bits_qos), .auto_axi4yank_out_w_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_w_ready), .auto_axi4yank_out_w_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_w_valid), .auto_axi4yank_out_w_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_w_bits_data), .auto_axi4yank_out_w_bits_strb (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_w_bits_strb), .auto_axi4yank_out_w_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_w_bits_last), .auto_axi4yank_out_b_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_b_ready), .auto_axi4yank_out_b_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_b_valid), .auto_axi4yank_out_b_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_b_bits_id), .auto_axi4yank_out_b_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_b_bits_resp), .auto_axi4yank_out_ar_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_ready), .auto_axi4yank_out_ar_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_valid), .auto_axi4yank_out_ar_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_id), .auto_axi4yank_out_ar_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_addr), .auto_axi4yank_out_ar_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_len), .auto_axi4yank_out_ar_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_size), .auto_axi4yank_out_ar_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_burst), .auto_axi4yank_out_ar_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_lock), .auto_axi4yank_out_ar_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_cache), .auto_axi4yank_out_ar_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_prot), .auto_axi4yank_out_ar_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_ar_bits_qos), .auto_axi4yank_out_r_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_r_ready), .auto_axi4yank_out_r_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_r_valid), .auto_axi4yank_out_r_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_r_bits_id), .auto_axi4yank_out_r_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_r_bits_data), .auto_axi4yank_out_r_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_r_bits_resp), .auto_axi4yank_out_r_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_1_r_bits_last), .auto_tl_in_a_ready (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_a_ready), .auto_tl_in_a_valid (_picker_auto_out_1_a_valid), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_opcode (_picker_auto_out_1_a_bits_opcode), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_param (_picker_auto_out_1_a_bits_param), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_size (_picker_auto_out_1_a_bits_size), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_source (_picker_auto_out_1_a_bits_source), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_address (_picker_auto_out_1_a_bits_address), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_mask (_picker_auto_out_1_a_bits_mask), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_data (_picker_auto_out_1_a_bits_data), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_corrupt (_picker_auto_out_1_a_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_tl_in_d_ready (_picker_auto_out_1_d_ready), // @[ProbePicker.scala:69:28] .auto_tl_in_d_valid (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_in_d_bits_corrupt), .auto_tl_out_a_ready (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_a_ready), // @[LazyScope.scala:98:27] .auto_tl_out_a_valid (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_valid), .auto_tl_out_a_bits_opcode (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_opcode), .auto_tl_out_a_bits_param (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_param), .auto_tl_out_a_bits_size (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_size), .auto_tl_out_a_bits_source (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_source), .auto_tl_out_a_bits_address (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_address), .auto_tl_out_a_bits_mask (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_mask), .auto_tl_out_a_bits_data (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_data), .auto_tl_out_a_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_a_bits_corrupt), .auto_tl_out_d_ready (_coupler_to_memory_controller_port_named_axi4_1_auto_tl_out_d_ready), .auto_tl_out_d_valid (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_valid), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_size (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_source (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_data (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_1_auto_widget_anon_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4_2 coupler_to_memory_controller_port_named_axi4_2 ( // @[LazyScope.scala:98:27] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_widget_anon_in_a_ready (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_a_ready), .auto_widget_anon_in_a_valid (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_valid), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_opcode (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_opcode), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_param (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_param), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_size (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_size), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_source (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_source), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_address (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_address), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_mask (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_mask), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_data (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_data), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_corrupt), // @[LazyScope.scala:98:27] .auto_widget_anon_in_d_ready (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_d_ready), // @[LazyScope.scala:98:27] .auto_widget_anon_in_d_valid (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_valid), .auto_widget_anon_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_opcode), .auto_widget_anon_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_size), .auto_widget_anon_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_source), .auto_widget_anon_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_denied), .auto_widget_anon_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_data), .auto_widget_anon_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_corrupt), .auto_axi4yank_out_aw_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_ready), .auto_axi4yank_out_aw_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_valid), .auto_axi4yank_out_aw_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_id), .auto_axi4yank_out_aw_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_addr), .auto_axi4yank_out_aw_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_len), .auto_axi4yank_out_aw_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_size), .auto_axi4yank_out_aw_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_burst), .auto_axi4yank_out_aw_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_lock), .auto_axi4yank_out_aw_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_cache), .auto_axi4yank_out_aw_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_prot), .auto_axi4yank_out_aw_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_aw_bits_qos), .auto_axi4yank_out_w_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_w_ready), .auto_axi4yank_out_w_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_w_valid), .auto_axi4yank_out_w_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_w_bits_data), .auto_axi4yank_out_w_bits_strb (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_w_bits_strb), .auto_axi4yank_out_w_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_w_bits_last), .auto_axi4yank_out_b_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_b_ready), .auto_axi4yank_out_b_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_b_valid), .auto_axi4yank_out_b_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_b_bits_id), .auto_axi4yank_out_b_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_b_bits_resp), .auto_axi4yank_out_ar_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_ready), .auto_axi4yank_out_ar_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_valid), .auto_axi4yank_out_ar_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_id), .auto_axi4yank_out_ar_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_addr), .auto_axi4yank_out_ar_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_len), .auto_axi4yank_out_ar_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_size), .auto_axi4yank_out_ar_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_burst), .auto_axi4yank_out_ar_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_lock), .auto_axi4yank_out_ar_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_cache), .auto_axi4yank_out_ar_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_prot), .auto_axi4yank_out_ar_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_ar_bits_qos), .auto_axi4yank_out_r_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_r_ready), .auto_axi4yank_out_r_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_r_valid), .auto_axi4yank_out_r_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_r_bits_id), .auto_axi4yank_out_r_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_r_bits_data), .auto_axi4yank_out_r_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_r_bits_resp), .auto_axi4yank_out_r_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_2_r_bits_last), .auto_tl_in_a_ready (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_a_ready), .auto_tl_in_a_valid (_picker_auto_out_2_a_valid), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_opcode (_picker_auto_out_2_a_bits_opcode), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_param (_picker_auto_out_2_a_bits_param), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_size (_picker_auto_out_2_a_bits_size), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_source (_picker_auto_out_2_a_bits_source), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_address (_picker_auto_out_2_a_bits_address), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_mask (_picker_auto_out_2_a_bits_mask), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_data (_picker_auto_out_2_a_bits_data), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_corrupt (_picker_auto_out_2_a_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_tl_in_d_ready (_picker_auto_out_2_d_ready), // @[ProbePicker.scala:69:28] .auto_tl_in_d_valid (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_in_d_bits_corrupt), .auto_tl_out_a_ready (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_a_ready), // @[LazyScope.scala:98:27] .auto_tl_out_a_valid (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_valid), .auto_tl_out_a_bits_opcode (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_opcode), .auto_tl_out_a_bits_param (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_param), .auto_tl_out_a_bits_size (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_size), .auto_tl_out_a_bits_source (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_source), .auto_tl_out_a_bits_address (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_address), .auto_tl_out_a_bits_mask (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_mask), .auto_tl_out_a_bits_data (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_data), .auto_tl_out_a_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_a_bits_corrupt), .auto_tl_out_d_ready (_coupler_to_memory_controller_port_named_axi4_2_auto_tl_out_d_ready), .auto_tl_out_d_valid (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_valid), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_size (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_source (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_data (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_2_auto_widget_anon_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4_3 coupler_to_memory_controller_port_named_axi4_3 ( // @[LazyScope.scala:98:27] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_widget_anon_in_a_ready (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_a_ready), .auto_widget_anon_in_a_valid (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_valid), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_opcode (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_opcode), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_param (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_param), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_size (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_size), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_source (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_source), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_address (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_address), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_mask (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_mask), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_data (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_data), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_corrupt), // @[LazyScope.scala:98:27] .auto_widget_anon_in_d_ready (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_d_ready), // @[LazyScope.scala:98:27] .auto_widget_anon_in_d_valid (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_valid), .auto_widget_anon_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_opcode), .auto_widget_anon_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_size), .auto_widget_anon_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_source), .auto_widget_anon_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_denied), .auto_widget_anon_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_data), .auto_widget_anon_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_corrupt), .auto_axi4yank_out_aw_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_ready), .auto_axi4yank_out_aw_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_valid), .auto_axi4yank_out_aw_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_id), .auto_axi4yank_out_aw_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_addr), .auto_axi4yank_out_aw_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_len), .auto_axi4yank_out_aw_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_size), .auto_axi4yank_out_aw_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_burst), .auto_axi4yank_out_aw_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_lock), .auto_axi4yank_out_aw_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_cache), .auto_axi4yank_out_aw_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_prot), .auto_axi4yank_out_aw_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_aw_bits_qos), .auto_axi4yank_out_w_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_w_ready), .auto_axi4yank_out_w_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_w_valid), .auto_axi4yank_out_w_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_w_bits_data), .auto_axi4yank_out_w_bits_strb (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_w_bits_strb), .auto_axi4yank_out_w_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_w_bits_last), .auto_axi4yank_out_b_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_b_ready), .auto_axi4yank_out_b_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_b_valid), .auto_axi4yank_out_b_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_b_bits_id), .auto_axi4yank_out_b_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_b_bits_resp), .auto_axi4yank_out_ar_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_ready), .auto_axi4yank_out_ar_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_valid), .auto_axi4yank_out_ar_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_id), .auto_axi4yank_out_ar_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_addr), .auto_axi4yank_out_ar_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_len), .auto_axi4yank_out_ar_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_size), .auto_axi4yank_out_ar_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_burst), .auto_axi4yank_out_ar_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_lock), .auto_axi4yank_out_ar_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_cache), .auto_axi4yank_out_ar_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_prot), .auto_axi4yank_out_ar_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_ar_bits_qos), .auto_axi4yank_out_r_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_r_ready), .auto_axi4yank_out_r_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_r_valid), .auto_axi4yank_out_r_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_r_bits_id), .auto_axi4yank_out_r_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_r_bits_data), .auto_axi4yank_out_r_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_r_bits_resp), .auto_axi4yank_out_r_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_3_r_bits_last), .auto_tl_in_a_ready (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_a_ready), .auto_tl_in_a_valid (_picker_auto_out_3_a_valid), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_opcode (_picker_auto_out_3_a_bits_opcode), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_param (_picker_auto_out_3_a_bits_param), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_size (_picker_auto_out_3_a_bits_size), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_source (_picker_auto_out_3_a_bits_source), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_address (_picker_auto_out_3_a_bits_address), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_mask (_picker_auto_out_3_a_bits_mask), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_data (_picker_auto_out_3_a_bits_data), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_corrupt (_picker_auto_out_3_a_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_tl_in_d_ready (_picker_auto_out_3_d_ready), // @[ProbePicker.scala:69:28] .auto_tl_in_d_valid (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_in_d_bits_corrupt), .auto_tl_out_a_ready (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_a_ready), // @[LazyScope.scala:98:27] .auto_tl_out_a_valid (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_valid), .auto_tl_out_a_bits_opcode (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_opcode), .auto_tl_out_a_bits_param (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_param), .auto_tl_out_a_bits_size (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_size), .auto_tl_out_a_bits_source (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_source), .auto_tl_out_a_bits_address (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_address), .auto_tl_out_a_bits_mask (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_mask), .auto_tl_out_a_bits_data (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_data), .auto_tl_out_a_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_a_bits_corrupt), .auto_tl_out_d_ready (_coupler_to_memory_controller_port_named_axi4_3_auto_tl_out_d_ready), .auto_tl_out_d_valid (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_valid), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_size (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_source (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_data (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_3_auto_widget_anon_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[LazyScope.scala:98:27] TLBuffer_a28d64s6k1z3u buffer_1 ( // @[Buffer.scala:75:28] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_in_a_ready (_buffer_1_auto_in_a_ready), .auto_in_a_valid (_picker_auto_out_4_a_valid), // @[ProbePicker.scala:69:28] .auto_in_a_bits_opcode (_picker_auto_out_4_a_bits_opcode), // @[ProbePicker.scala:69:28] .auto_in_a_bits_param (_picker_auto_out_4_a_bits_param), // @[ProbePicker.scala:69:28] .auto_in_a_bits_size (_picker_auto_out_4_a_bits_size), // @[ProbePicker.scala:69:28] .auto_in_a_bits_source (_picker_auto_out_4_a_bits_source), // @[ProbePicker.scala:69:28] .auto_in_a_bits_address (_picker_auto_out_4_a_bits_address), // @[ProbePicker.scala:69:28] .auto_in_a_bits_mask (_picker_auto_out_4_a_bits_mask), // @[ProbePicker.scala:69:28] .auto_in_a_bits_data (_picker_auto_out_4_a_bits_data), // @[ProbePicker.scala:69:28] .auto_in_a_bits_corrupt (_picker_auto_out_4_a_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_in_d_ready (_picker_auto_out_4_d_ready), // @[ProbePicker.scala:69:28] .auto_in_d_valid (_buffer_1_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_1_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_1_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_1_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_1_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_1_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_1_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_1_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_1_auto_in_d_bits_corrupt), .auto_out_a_ready (auto_buffer_out_a_ready), .auto_out_a_valid (auto_buffer_out_a_valid), .auto_out_a_bits_opcode (auto_buffer_out_a_bits_opcode), .auto_out_a_bits_param (auto_buffer_out_a_bits_param), .auto_out_a_bits_size (auto_buffer_out_a_bits_size), .auto_out_a_bits_source (auto_buffer_out_a_bits_source), .auto_out_a_bits_address (auto_buffer_out_a_bits_address), .auto_out_a_bits_mask (auto_buffer_out_a_bits_mask), .auto_out_a_bits_data (auto_buffer_out_a_bits_data), .auto_out_a_bits_corrupt (auto_buffer_out_a_bits_corrupt), .auto_out_d_ready (auto_buffer_out_d_ready), .auto_out_d_valid (auto_buffer_out_d_valid), .auto_out_d_bits_opcode (auto_buffer_out_d_bits_opcode), .auto_out_d_bits_param (auto_buffer_out_d_bits_param), .auto_out_d_bits_size (auto_buffer_out_d_bits_size), .auto_out_d_bits_source (auto_buffer_out_d_bits_source), .auto_out_d_bits_sink (auto_buffer_out_d_bits_sink), .auto_out_d_bits_denied (auto_buffer_out_d_bits_denied), .auto_out_d_bits_data (auto_buffer_out_d_bits_data), .auto_out_d_bits_corrupt (auto_buffer_out_d_bits_corrupt) ); // @[Buffer.scala:75:28] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TageTable_7 : input clock : Clock input reset : Reset output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f3_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<7>, clock, reset, UInt<7>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<7>(0h7f)) when _T : connect doing_reset, UInt<1>(0h0) node _T_1 = shr(io.f1_req_pc, 3) node idx_history = bits(io.f1_req_ghist, 3, 0) node _idx_T = xor(_T_1, idx_history) node s1_hashed_idx = bits(_idx_T, 6, 0) node tag_history = bits(io.f1_req_ghist, 3, 0) node _tag_T = shr(_T_1, 7) node _tag_T_1 = xor(_tag_T, tag_history) node s1_tag = bits(_tag_T_1, 6, 0) smem hi_us : UInt<1>[4] [128] smem lo_us : UInt<1>[4] [128] smem table : UInt<11>[4] [128] reg s2_tag : UInt, clock connect s2_tag, s1_tag wire _s2_req_rtage_WIRE : UInt<7> invalidate _s2_req_rtage_WIRE when io.f1_req_valid : connect _s2_req_rtage_WIRE, s1_hashed_idx read mport s2_req_rtage_MPORT = table[_s2_req_rtage_WIRE], clock wire _s2_req_rtage_WIRE_1 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_2 : UInt<11> connect _s2_req_rtage_WIRE_2, s2_req_rtage_MPORT[0] node _s2_req_rtage_T = bits(_s2_req_rtage_WIRE_2, 2, 0) connect _s2_req_rtage_WIRE_1.ctr, _s2_req_rtage_T node _s2_req_rtage_T_1 = bits(_s2_req_rtage_WIRE_2, 9, 3) connect _s2_req_rtage_WIRE_1.tag, _s2_req_rtage_T_1 node _s2_req_rtage_T_2 = bits(_s2_req_rtage_WIRE_2, 10, 10) connect _s2_req_rtage_WIRE_1.valid, _s2_req_rtage_T_2 wire _s2_req_rtage_WIRE_3 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_4 : UInt<11> connect _s2_req_rtage_WIRE_4, s2_req_rtage_MPORT[1] node _s2_req_rtage_T_3 = bits(_s2_req_rtage_WIRE_4, 2, 0) connect _s2_req_rtage_WIRE_3.ctr, _s2_req_rtage_T_3 node _s2_req_rtage_T_4 = bits(_s2_req_rtage_WIRE_4, 9, 3) connect _s2_req_rtage_WIRE_3.tag, _s2_req_rtage_T_4 node _s2_req_rtage_T_5 = bits(_s2_req_rtage_WIRE_4, 10, 10) connect _s2_req_rtage_WIRE_3.valid, _s2_req_rtage_T_5 wire _s2_req_rtage_WIRE_5 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_6 : UInt<11> connect _s2_req_rtage_WIRE_6, s2_req_rtage_MPORT[2] node _s2_req_rtage_T_6 = bits(_s2_req_rtage_WIRE_6, 2, 0) connect _s2_req_rtage_WIRE_5.ctr, _s2_req_rtage_T_6 node _s2_req_rtage_T_7 = bits(_s2_req_rtage_WIRE_6, 9, 3) connect _s2_req_rtage_WIRE_5.tag, _s2_req_rtage_T_7 node _s2_req_rtage_T_8 = bits(_s2_req_rtage_WIRE_6, 10, 10) connect _s2_req_rtage_WIRE_5.valid, _s2_req_rtage_T_8 wire _s2_req_rtage_WIRE_7 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_8 : UInt<11> connect _s2_req_rtage_WIRE_8, s2_req_rtage_MPORT[3] node _s2_req_rtage_T_9 = bits(_s2_req_rtage_WIRE_8, 2, 0) connect _s2_req_rtage_WIRE_7.ctr, _s2_req_rtage_T_9 node _s2_req_rtage_T_10 = bits(_s2_req_rtage_WIRE_8, 9, 3) connect _s2_req_rtage_WIRE_7.tag, _s2_req_rtage_T_10 node _s2_req_rtage_T_11 = bits(_s2_req_rtage_WIRE_8, 10, 10) connect _s2_req_rtage_WIRE_7.valid, _s2_req_rtage_T_11 wire s2_req_rtage : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}[4] connect s2_req_rtage[0].ctr, _s2_req_rtage_WIRE_1.ctr connect s2_req_rtage[0].tag, _s2_req_rtage_WIRE_1.tag connect s2_req_rtage[0].valid, _s2_req_rtage_WIRE_1.valid connect s2_req_rtage[1].ctr, _s2_req_rtage_WIRE_3.ctr connect s2_req_rtage[1].tag, _s2_req_rtage_WIRE_3.tag connect s2_req_rtage[1].valid, _s2_req_rtage_WIRE_3.valid connect s2_req_rtage[2].ctr, _s2_req_rtage_WIRE_5.ctr connect s2_req_rtage[2].tag, _s2_req_rtage_WIRE_5.tag connect s2_req_rtage[2].valid, _s2_req_rtage_WIRE_5.valid connect s2_req_rtage[3].ctr, _s2_req_rtage_WIRE_7.ctr connect s2_req_rtage[3].tag, _s2_req_rtage_WIRE_7.tag connect s2_req_rtage[3].valid, _s2_req_rtage_WIRE_7.valid wire _s2_req_rhius_WIRE : UInt<7> invalidate _s2_req_rhius_WIRE when io.f1_req_valid : connect _s2_req_rhius_WIRE, s1_hashed_idx read mport s2_req_rhius = hi_us[_s2_req_rhius_WIRE], clock wire _s2_req_rlous_WIRE : UInt<7> invalidate _s2_req_rlous_WIRE when io.f1_req_valid : connect _s2_req_rlous_WIRE, s1_hashed_idx read mport s2_req_rlous = lo_us[_s2_req_rlous_WIRE], clock node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag) node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T) node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2) node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag) node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4) node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6) node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag) node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8) node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10) node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag) node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12) node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14) wire s2_req_rhits : UInt<1>[4] connect s2_req_rhits[0], _s2_req_rhits_T_3 connect s2_req_rhits[1], _s2_req_rhits_T_7 connect s2_req_rhits[2], _s2_req_rhits_T_11 connect s2_req_rhits[3], _s2_req_rhits_T_15 reg io_f3_resp_0_valid_REG : UInt<1>, clock connect io_f3_resp_0_valid_REG, s2_req_rhits[0] connect io.f3_resp[0].valid, io_f3_resp_0_valid_REG node _io_f3_resp_0_bits_u_T = cat(s2_req_rhius[0], s2_req_rlous[0]) reg io_f3_resp_0_bits_u_REG : UInt, clock connect io_f3_resp_0_bits_u_REG, _io_f3_resp_0_bits_u_T connect io.f3_resp[0].bits.u, io_f3_resp_0_bits_u_REG reg io_f3_resp_0_bits_ctr_REG : UInt, clock connect io_f3_resp_0_bits_ctr_REG, s2_req_rtage[0].ctr connect io.f3_resp[0].bits.ctr, io_f3_resp_0_bits_ctr_REG reg io_f3_resp_1_valid_REG : UInt<1>, clock connect io_f3_resp_1_valid_REG, s2_req_rhits[1] connect io.f3_resp[1].valid, io_f3_resp_1_valid_REG node _io_f3_resp_1_bits_u_T = cat(s2_req_rhius[1], s2_req_rlous[1]) reg io_f3_resp_1_bits_u_REG : UInt, clock connect io_f3_resp_1_bits_u_REG, _io_f3_resp_1_bits_u_T connect io.f3_resp[1].bits.u, io_f3_resp_1_bits_u_REG reg io_f3_resp_1_bits_ctr_REG : UInt, clock connect io_f3_resp_1_bits_ctr_REG, s2_req_rtage[1].ctr connect io.f3_resp[1].bits.ctr, io_f3_resp_1_bits_ctr_REG reg io_f3_resp_2_valid_REG : UInt<1>, clock connect io_f3_resp_2_valid_REG, s2_req_rhits[2] connect io.f3_resp[2].valid, io_f3_resp_2_valid_REG node _io_f3_resp_2_bits_u_T = cat(s2_req_rhius[2], s2_req_rlous[2]) reg io_f3_resp_2_bits_u_REG : UInt, clock connect io_f3_resp_2_bits_u_REG, _io_f3_resp_2_bits_u_T connect io.f3_resp[2].bits.u, io_f3_resp_2_bits_u_REG reg io_f3_resp_2_bits_ctr_REG : UInt, clock connect io_f3_resp_2_bits_ctr_REG, s2_req_rtage[2].ctr connect io.f3_resp[2].bits.ctr, io_f3_resp_2_bits_ctr_REG reg io_f3_resp_3_valid_REG : UInt<1>, clock connect io_f3_resp_3_valid_REG, s2_req_rhits[3] connect io.f3_resp[3].valid, io_f3_resp_3_valid_REG node _io_f3_resp_3_bits_u_T = cat(s2_req_rhius[3], s2_req_rlous[3]) reg io_f3_resp_3_bits_u_REG : UInt, clock connect io_f3_resp_3_bits_u_REG, _io_f3_resp_3_bits_u_T connect io.f3_resp[3].bits.u, io_f3_resp_3_bits_u_REG reg io_f3_resp_3_bits_ctr_REG : UInt, clock connect io_f3_resp_3_bits_ctr_REG, s2_req_rtage[3].ctr connect io.f3_resp[3].bits.ctr, io_f3_resp_3_bits_ctr_REG regreset clear_u_ctr : UInt<19>, clock, reset, UInt<19>(0h0) when doing_reset : connect clear_u_ctr, UInt<1>(0h1) else : node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1)) node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1) connect clear_u_ctr, _clear_u_ctr_T_1 node _doing_clear_u_T = bits(clear_u_ctr, 10, 0) node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0)) node _doing_clear_u_hi_T = bits(clear_u_ctr, 18, 18) node _doing_clear_u_hi_T_1 = eq(_doing_clear_u_hi_T, UInt<1>(0h1)) node doing_clear_u_hi = and(doing_clear_u, _doing_clear_u_hi_T_1) node _doing_clear_u_lo_T = bits(clear_u_ctr, 18, 18) node _doing_clear_u_lo_T_1 = eq(_doing_clear_u_lo_T, UInt<1>(0h0)) node doing_clear_u_lo = and(doing_clear_u, _doing_clear_u_lo_T_1) node clear_u_idx = shr(clear_u_ctr, 11) node _T_2 = shr(io.update_pc, 3) node idx_history_1 = bits(io.update_hist, 3, 0) node _idx_T_1 = xor(_T_2, idx_history_1) node update_idx = bits(_idx_T_1, 6, 0) node tag_history_1 = bits(io.update_hist, 3, 0) node _tag_T_2 = shr(_T_2, 7) node _tag_T_3 = xor(_tag_T_2, tag_history_1) node update_tag = bits(_tag_T_3, 6, 0) wire update_wdata : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}[4] node _T_3 = mux(doing_reset, reset_idx, update_idx) wire _WIRE : UInt<11>[4] connect _WIRE[0], UInt<11>(0h0) connect _WIRE[1], UInt<11>(0h0) connect _WIRE[2], UInt<11>(0h0) connect _WIRE[3], UInt<11>(0h0) node hi = cat(update_wdata[0].valid, update_wdata[0].tag) node _T_4 = cat(hi, update_wdata[0].ctr) node hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag) node _T_5 = cat(hi_1, update_wdata[1].ctr) node hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag) node _T_6 = cat(hi_2, update_wdata[2].ctr) node hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag) node _T_7 = cat(hi_3, update_wdata[3].ctr) wire _WIRE_1 : UInt<11>[4] connect _WIRE_1[0], _T_4 connect _WIRE_1[1], _T_5 connect _WIRE_1[2], _T_6 connect _WIRE_1[3], _T_7 node _T_8 = mux(doing_reset, _WIRE, _WIRE_1) node _T_9 = not(UInt<4>(0h0)) node lo = cat(io.update_mask[1], io.update_mask[0]) node hi_4 = cat(io.update_mask[3], io.update_mask[2]) node _T_10 = cat(hi_4, lo) node _T_11 = mux(doing_reset, _T_9, _T_10) node _T_12 = bits(_T_11, 0, 0) node _T_13 = bits(_T_11, 1, 1) node _T_14 = bits(_T_11, 2, 2) node _T_15 = bits(_T_11, 3, 3) write mport MPORT = table[_T_3], clock when _T_12 : connect MPORT[0], _T_8[0] when _T_13 : connect MPORT[1], _T_8[1] when _T_14 : connect MPORT[2], _T_8[2] when _T_15 : connect MPORT[3], _T_8[3] wire update_hi_wdata : UInt<1>[4] node _T_16 = mux(doing_clear_u_hi, clear_u_idx, update_idx) node _T_17 = mux(doing_reset, reset_idx, _T_16) node _T_18 = or(doing_reset, doing_clear_u_hi) wire _WIRE_2 : UInt<1>[4] connect _WIRE_2[0], UInt<1>(0h0) connect _WIRE_2[1], UInt<1>(0h0) connect _WIRE_2[2], UInt<1>(0h0) connect _WIRE_2[3], UInt<1>(0h0) node _T_19 = mux(_T_18, _WIRE_2, update_hi_wdata) node _T_20 = or(doing_reset, doing_clear_u_hi) node _T_21 = not(UInt<4>(0h0)) node lo_1 = cat(io.update_u_mask[1], io.update_u_mask[0]) node hi_5 = cat(io.update_u_mask[3], io.update_u_mask[2]) node _T_22 = cat(hi_5, lo_1) node _T_23 = mux(_T_20, _T_21, _T_22) node _T_24 = bits(_T_23, 0, 0) node _T_25 = bits(_T_23, 1, 1) node _T_26 = bits(_T_23, 2, 2) node _T_27 = bits(_T_23, 3, 3) node _T_28 = bits(_T_17, 6, 0) write mport MPORT_1 = hi_us[_T_28], clock when _T_24 : connect MPORT_1[0], _T_19[0] when _T_25 : connect MPORT_1[1], _T_19[1] when _T_26 : connect MPORT_1[2], _T_19[2] when _T_27 : connect MPORT_1[3], _T_19[3] wire update_lo_wdata : UInt<1>[4] node _T_29 = mux(doing_clear_u_lo, clear_u_idx, update_idx) node _T_30 = mux(doing_reset, reset_idx, _T_29) node _T_31 = or(doing_reset, doing_clear_u_lo) wire _WIRE_3 : UInt<1>[4] connect _WIRE_3[0], UInt<1>(0h0) connect _WIRE_3[1], UInt<1>(0h0) connect _WIRE_3[2], UInt<1>(0h0) connect _WIRE_3[3], UInt<1>(0h0) node _T_32 = mux(_T_31, _WIRE_3, update_lo_wdata) node _T_33 = or(doing_reset, doing_clear_u_lo) node _T_34 = not(UInt<4>(0h0)) node lo_2 = cat(io.update_u_mask[1], io.update_u_mask[0]) node hi_6 = cat(io.update_u_mask[3], io.update_u_mask[2]) node _T_35 = cat(hi_6, lo_2) node _T_36 = mux(_T_33, _T_34, _T_35) node _T_37 = bits(_T_36, 0, 0) node _T_38 = bits(_T_36, 1, 1) node _T_39 = bits(_T_36, 2, 2) node _T_40 = bits(_T_36, 3, 3) node _T_41 = bits(_T_30, 6, 0) write mport MPORT_2 = lo_us[_T_41], clock when _T_37 : connect MPORT_2[0], _T_32[0] when _T_38 : connect MPORT_2[1], _T_32[1] when _T_39 : connect MPORT_2[2], _T_32[2] when _T_40 : connect MPORT_2[3], _T_32[3] reg wrbypass_tags : UInt<7>[2], clock reg wrbypass_idxs : UInt<7>[2], clock reg wrbypass : UInt<3>[4][2], clock regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0) node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag) node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1) node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx) node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3) node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag) node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6) node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx) node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8) wire wrbypass_hits : UInt<1>[2] connect wrbypass_hits[0], _wrbypass_hits_T_4 connect wrbypass_hits[1], _wrbypass_hits_T_9 node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1]) node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1)) node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1) node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4) node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1) node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8) node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9) node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1) node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14) node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1) node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18) node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19) node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20) node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21) connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22 connect update_wdata[0].valid, UInt<1>(0h1) connect update_wdata[0].tag, update_tag node _update_hi_wdata_0_T = bits(io.update_u[0], 1, 1) connect update_hi_wdata[0], _update_hi_wdata_0_T node _update_lo_wdata_0_T = bits(io.update_u[0], 0, 0) connect update_lo_wdata[0], _update_lo_wdata_0_T node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1) node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4) node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1) node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8) node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9) node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1) node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14) node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1) node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18) node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19) node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20) node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21) connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22 connect update_wdata[1].valid, UInt<1>(0h1) connect update_wdata[1].tag, update_tag node _update_hi_wdata_1_T = bits(io.update_u[1], 1, 1) connect update_hi_wdata[1], _update_hi_wdata_1_T node _update_lo_wdata_1_T = bits(io.update_u[1], 0, 0) connect update_lo_wdata[1], _update_lo_wdata_1_T node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1) node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4) node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1) node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8) node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9) node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1) node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14) node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1) node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18) node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19) node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20) node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21) connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22 connect update_wdata[2].valid, UInt<1>(0h1) connect update_wdata[2].tag, update_tag node _update_hi_wdata_2_T = bits(io.update_u[2], 1, 1) connect update_hi_wdata[2], _update_hi_wdata_2_T node _update_lo_wdata_2_T = bits(io.update_u[2], 0, 0) connect update_lo_wdata[2], _update_lo_wdata_2_T node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1) node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4) node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1) node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8) node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9) node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1) node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14) node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1) node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18) node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19) node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20) node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21) connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22 connect update_wdata[3].valid, UInt<1>(0h1) connect update_wdata[3].tag, update_tag node _update_hi_wdata_3_T = bits(io.update_u[3], 1, 1) connect update_hi_wdata[3], _update_hi_wdata_3_T node _update_lo_wdata_3_T = bits(io.update_u[3], 0, 0) connect update_lo_wdata[3], _update_lo_wdata_3_T node _T_42 = or(io.update_mask[0], io.update_mask[1]) node _T_43 = or(_T_42, io.update_mask[2]) node _T_44 = or(_T_43, io.update_mask[3]) when _T_44 : node _T_45 = or(wrbypass_hits[0], wrbypass_hits[1]) when _T_45 : wire _WIRE_4 : UInt<3>[4] connect _WIRE_4[0], update_wdata[0].ctr connect _WIRE_4[1], update_wdata[1].ctr connect _WIRE_4[2], update_wdata[2].ctr connect _WIRE_4[3], update_wdata[3].ctr connect wrbypass[wrbypass_hit_idx], _WIRE_4 else : wire _WIRE_5 : UInt<3>[4] connect _WIRE_5[0], update_wdata[0].ctr connect _WIRE_5[1], update_wdata[1].ctr connect _WIRE_5[2], update_wdata[2].ctr connect _WIRE_5[3], update_wdata[3].ctr connect wrbypass[wrbypass_enq_idx], _WIRE_5 connect wrbypass_tags[wrbypass_enq_idx], update_tag connect wrbypass_idxs[wrbypass_enq_idx], update_idx node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1)) node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1) node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0) connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2
module TageTable_7( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f3_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14] output io_f3_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14] output io_f3_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14] output io_f3_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8] wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8] wire [10:0] table_MPORT_data_3; // @[tage.scala:123:8] wire [10:0] table_MPORT_data_2; // @[tage.scala:123:8] wire [10:0] table_MPORT_data_1; // @[tage.scala:123:8] wire [10:0] table_MPORT_data_0; // @[tage.scala:123:8] wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87] wire [43:0] _table_R0_data; // @[tage.scala:91:27] wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27] wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26] wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [6:0] reset_idx; // @[tage.scala:73:26] wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26] wire [3:0] idx_history = io_f1_req_ghist_0[3:0]; // @[tage.scala:24:7, :53:11] wire [3:0] tag_history = io_f1_req_ghist_0[3:0]; // @[tage.scala:24:7, :53:11] wire [36:0] _idx_T = {io_f1_req_pc_0[39:7], io_f1_req_pc_0[6:3] ^ idx_history}; // @[frontend.scala:162:35] wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}] wire [6:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40] wire [6:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32] wire [6:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32] wire [29:0] _tag_T = io_f1_req_pc_0[39:10]; // @[frontend.scala:162:35] wire [29:0] _tag_T_1 = {_tag_T[29:4], _tag_T[3:0] ^ tag_history}; // @[tage.scala:53:11, :62:{30,50}] wire [6:0] s1_tag = _tag_T_1[6:0]; // @[tage.scala:62:{50,64}] wire [10:0] _s2_req_rtage_WIRE_2 = _table_R0_data[10:0]; // @[tage.scala:91:27, :97:87] wire [10:0] _s2_req_rtage_WIRE_4 = _table_R0_data[21:11]; // @[tage.scala:91:27, :97:87] wire [10:0] _s2_req_rtage_WIRE_6 = _table_R0_data[32:22]; // @[tage.scala:91:27, :97:87] wire [10:0] _s2_req_rtage_WIRE_8 = _table_R0_data[43:33]; // @[tage.scala:91:27, :97:87] reg [6:0] s2_tag; // @[tage.scala:95:29] wire _s2_req_rtage_T_2; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_1; // @[tage.scala:97:87] wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87] assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87] assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87] wire _s2_req_rtage_T_5; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_4; // @[tage.scala:97:87] wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87] assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87] assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87] wire _s2_req_rtage_T_8; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_7; // @[tage.scala:97:87] wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87] assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87] assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87] wire _s2_req_rtage_T_11; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_10; // @[tage.scala:97:87] wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87] assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87] assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg [18:0] clear_u_ctr; // @[tage.scala:109:28] wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85] wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _doing_clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54] wire _doing_clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54, :114:54] wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}] wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}] wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}] wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}] wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33] wire [3:0] idx_history_1 = io_update_hist_0[3:0]; // @[tage.scala:24:7, :53:11] wire [3:0] tag_history_1 = io_update_hist_0[3:0]; // @[tage.scala:24:7, :53:11] wire [36:0] _idx_T_1 = {io_update_pc_0[39:7], io_update_pc_0[6:3] ^ idx_history_1}; // @[frontend.scala:162:35] wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}] wire [29:0] _tag_T_2 = io_update_pc_0[39:10]; // @[frontend.scala:162:35] wire [29:0] _tag_T_3 = {_tag_T_2[29:4], _tag_T_2[3:0] ^ tag_history_1}; // @[tage.scala:53:11, :62:{30,50}] wire [6:0] update_tag = _tag_T_3[6:0]; // @[tage.scala:62:{50,64}] wire [6:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [6:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [6:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [6:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26] wire [7:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102] wire [7:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102] wire [7:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102] wire [7:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102] assign table_MPORT_data_0 = doing_reset ? 11'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_1 = doing_reset ? 11'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_2 = doing_reset ? 11'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_3 = doing_reset ? 11'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90] wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90] wire _update_hi_wdata_0_T; // @[tage.scala:166:44] wire _update_hi_wdata_1_T; // @[tage.scala:166:44] wire _update_hi_wdata_2_T; // @[tage.scala:166:44] wire _update_hi_wdata_3_T; // @[tage.scala:166:44] wire update_hi_wdata_0; // @[tage.scala:127:29] wire update_hi_wdata_1; // @[tage.scala:127:29] wire update_hi_wdata_2; // @[tage.scala:127:29] wire update_hi_wdata_3; // @[tage.scala:127:29] wire _T_20 = doing_reset | doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21] assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}] wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80] wire [1:0] lo_1; // @[tage.scala:131:80] assign lo_1 = _GEN; // @[tage.scala:131:80] wire [1:0] lo_2; // @[tage.scala:138:80] assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80] wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80] wire [1:0] hi_5; // @[tage.scala:131:80] assign hi_5 = _GEN_0; // @[tage.scala:131:80] wire [1:0] hi_6; // @[tage.scala:138:80] assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80] wire _update_lo_wdata_0_T; // @[tage.scala:167:44] wire _update_lo_wdata_1_T; // @[tage.scala:167:44] wire _update_lo_wdata_2_T; // @[tage.scala:167:44] wire _update_lo_wdata_3_T; // @[tage.scala:167:44] wire update_lo_wdata_0; // @[tage.scala:134:29] wire update_lo_wdata_1; // @[tage.scala:134:29] wire update_lo_wdata_2; // @[tage.scala:134:29] wire update_lo_wdata_3; // @[tage.scala:134:29] wire _T_33 = doing_reset | doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21] assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}] reg [6:0] wrbypass_tags_0; // @[tage.scala:141:29] reg [6:0] wrbypass_tags_1; // @[tage.scala:141:29] reg [6:0] wrbypass_idxs_0; // @[tage.scala:142:29] reg [6:0] wrbypass_idxs_1; // @[tage.scala:142:29] reg [2:0] wrbypass_0_0; // @[tage.scala:143:29] reg [2:0] wrbypass_0_1; // @[tage.scala:143:29] reg [2:0] wrbypass_0_2; // @[tage.scala:143:29] reg [2:0] wrbypass_0_3; // @[tage.scala:143:29] reg [2:0] wrbypass_1_0; // @[tage.scala:143:29] reg [2:0] wrbypass_1_1; // @[tage.scala:143:29] reg [2:0] wrbypass_1_2; // @[tage.scala:143:29] reg [2:0] wrbypass_1_3; // @[tage.scala:143:29] reg wrbypass_enq_idx; // @[tage.scala:144:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37] wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:146:33, :151:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}] wire _T_44 = io_update_mask_0_0 | io_update_mask_1_0 | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :170:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_44 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] wire _GEN_15 = ~_T_44 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 7'h0; // @[tage.scala:73:26] clear_u_ctr <= 19'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_44 | wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39] end else // @[tage.scala:144:33, :170:38, :171:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29] io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38] io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38] io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38] io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38] io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38] if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29] if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29] if (~_T_44 | _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] end else begin // @[tage.scala:143:29, :170:38, :171:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end always @(posedge) hi_us_6 hi_us ( // @[tage.scala:89:27] .R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_hi_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}] .W0_clk (clock), .W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8] .W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}] ); // @[tage.scala:89:27] lo_us_6 lo_us ( // @[tage.scala:90:27] .R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_lo_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}] .W0_clk (clock), .W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8] .W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}] ); // @[tage.scala:90:27] table_6 table_0 ( // @[tage.scala:91:27] .R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_table_R0_data), .W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8] .W0_clk (clock), .W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8] .W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}] ); // @[tage.scala:91:27] assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_39 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_39( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_118 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_135 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_118( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_135 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a29d64s7k1z3u_1 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_12 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a29d64s7k1z3u_1 connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a29d64s7k1z3u_1 connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_52 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_53 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLBuffer_a29d64s7k1z3u_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [6:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_12 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a29d64s7k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a29d64s7k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s3k3z4c_3 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_44 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s3k3z4c_1 connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s3k3z4c_1 connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready inst nodeIn_b_q of Queue2_TLBundleB_a32d64s3k3z4c_1 connect nodeIn_b_q.clock, clock connect nodeIn_b_q.reset, reset connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready inst nodeOut_c_q of Queue2_TLBundleC_a32d64s3k3z4c_1 connect nodeOut_c_q.clock, clock connect nodeOut_c_q.reset, reset connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready inst nodeOut_e_q of Queue2_TLBundleE_a32d64s3k3z4c_1 connect nodeOut_e_q.clock, clock connect nodeOut_e_q.reset, reset connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready
module TLBuffer_a32d64s3k3z4c_3( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9] wire [63:0] auto_out_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_44 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s3k3z4c_1 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s3k3z4c_1 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d64s3k3z4c_1 nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d64s3k3z4c_1 nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d64s3k3z4c_1 nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_86 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_86( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_41 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_42 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_43 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_44 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_41 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_42 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_43 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_44 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_6 : input clock : Clock input reset : Reset output io : { flip in_a : { bits : UInt<32>}[1], flip in_b : { bits : UInt<32>}[1], flip in_d : { bits : UInt<32>}[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<4>[1], flip in_last : UInt<1>[1], out_a : { bits : UInt<32>}[1], out_c : { bits : UInt<32>}[1], out_b : { bits : UInt<32>}[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<4>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_22 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a.bits, io.in_a[0].bits connect tile_0_0.io.in_b.bits, io.in_b[0].bits connect tile_0_0.io.in_d.bits, io.in_d[0].bits connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_6( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [31:0] io_in_a_0_bits, // @[Tile.scala:17:14] input [31:0] io_in_b_0_bits, // @[Tile.scala:17:14] input [31:0] io_in_d_0_bits, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [3:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [31:0] io_out_a_0_bits, // @[Tile.scala:17:14] output [31:0] io_out_c_0_bits, // @[Tile.scala:17:14] output [31:0] io_out_b_0_bits, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [3:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [31:0] io_in_a_0_bits_0 = io_in_a_0_bits; // @[Tile.scala:16:7] wire [31:0] io_in_b_0_bits_0 = io_in_b_0_bits; // @[Tile.scala:16:7] wire [31:0] io_in_d_0_bits_0 = io_in_d_0_bits; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [3:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [31:0] io_out_a_0_bits_0; // @[Tile.scala:16:7] wire [31:0] io_out_c_0_bits_0; // @[Tile.scala:16:7] wire [31:0] io_out_b_0_bits_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [3:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_22 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a_bits (io_in_a_0_bits_0), // @[Tile.scala:16:7] .io_in_b_bits (io_in_b_0_bits_0), // @[Tile.scala:16:7] .io_in_d_bits (io_in_d_0_bits_0), // @[Tile.scala:16:7] .io_out_a_bits (io_out_a_0_bits_0), .io_out_b_bits (io_out_b_0_bits_0), .io_out_c_bits (io_out_c_0_bits_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0_bits = io_out_a_0_bits_0; // @[Tile.scala:16:7] assign io_out_c_0_bits = io_out_c_0_bits_0; // @[Tile.scala:16:7] assign io_out_b_0_bits = io_out_b_0_bits_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_268 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_12 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_268( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_12 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget1 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_30 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in node _hasData_opdata_T = bits(anonIn.a.bits.opcode, 2, 2) node hasData = eq(_hasData_opdata_T, UInt<1>(0h0)) node _limit_T = dshl(UInt<3>(0h7), anonIn.a.bits.size) node _limit_T_1 = bits(_limit_T, 2, 0) node _limit_T_2 = not(_limit_T_1) node limit = shr(_limit_T_2, 0) regreset count : UInt<3>, clock, reset, UInt<3>(0h0) node first = eq(count, UInt<1>(0h0)) node _last_T = eq(count, limit) node _last_T_1 = eq(hasData, UInt<1>(0h0)) node last = or(_last_T, _last_T_1) node _enable_T = xor(count, UInt<1>(0h0)) node _enable_T_1 = and(_enable_T, limit) node _enable_T_2 = orr(_enable_T_1) node enable_0 = eq(_enable_T_2, UInt<1>(0h0)) node _enable_T_3 = xor(count, UInt<1>(0h1)) node _enable_T_4 = and(_enable_T_3, limit) node _enable_T_5 = orr(_enable_T_4) node enable_1 = eq(_enable_T_5, UInt<1>(0h0)) node _enable_T_6 = xor(count, UInt<2>(0h2)) node _enable_T_7 = and(_enable_T_6, limit) node _enable_T_8 = orr(_enable_T_7) node enable_2 = eq(_enable_T_8, UInt<1>(0h0)) node _enable_T_9 = xor(count, UInt<2>(0h3)) node _enable_T_10 = and(_enable_T_9, limit) node _enable_T_11 = orr(_enable_T_10) node enable_3 = eq(_enable_T_11, UInt<1>(0h0)) node _enable_T_12 = xor(count, UInt<3>(0h4)) node _enable_T_13 = and(_enable_T_12, limit) node _enable_T_14 = orr(_enable_T_13) node enable_4 = eq(_enable_T_14, UInt<1>(0h0)) node _enable_T_15 = xor(count, UInt<3>(0h5)) node _enable_T_16 = and(_enable_T_15, limit) node _enable_T_17 = orr(_enable_T_16) node enable_5 = eq(_enable_T_17, UInt<1>(0h0)) node _enable_T_18 = xor(count, UInt<3>(0h6)) node _enable_T_19 = and(_enable_T_18, limit) node _enable_T_20 = orr(_enable_T_19) node enable_6 = eq(_enable_T_20, UInt<1>(0h0)) node _enable_T_21 = xor(count, UInt<3>(0h7)) node _enable_T_22 = and(_enable_T_21, limit) node _enable_T_23 = orr(_enable_T_22) node enable_7 = eq(_enable_T_23, UInt<1>(0h0)) regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0) node corrupt_out = or(anonIn.a.bits.corrupt, corrupt_reg) node _T = and(anonIn.a.ready, anonIn.a.valid) when _T : node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 connect corrupt_reg, corrupt_out when last : connect count, UInt<1>(0h0) connect corrupt_reg, UInt<1>(0h0) node _anonIn_a_ready_T = eq(last, UInt<1>(0h0)) node _anonIn_a_ready_T_1 = or(anonOut.a.ready, _anonIn_a_ready_T) connect anonIn.a.ready, _anonIn_a_ready_T_1 node _anonOut_a_valid_T = and(anonIn.a.valid, last) connect anonOut.a.valid, _anonOut_a_valid_T connect anonOut.a.bits, anonIn.a.bits regreset anonOut_a_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonOut_a_bits_data_masked_enable_T = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_0 = or(enable_0, _anonOut_a_bits_data_masked_enable_T) node _anonOut_a_bits_data_masked_enable_T_1 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_1 = or(enable_1, _anonOut_a_bits_data_masked_enable_T_1) node _anonOut_a_bits_data_masked_enable_T_2 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_2 = or(enable_2, _anonOut_a_bits_data_masked_enable_T_2) node _anonOut_a_bits_data_masked_enable_T_3 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_3 = or(enable_3, _anonOut_a_bits_data_masked_enable_T_3) node _anonOut_a_bits_data_masked_enable_T_4 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_4 = or(enable_4, _anonOut_a_bits_data_masked_enable_T_4) node _anonOut_a_bits_data_masked_enable_T_5 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_5 = or(enable_5, _anonOut_a_bits_data_masked_enable_T_5) node _anonOut_a_bits_data_masked_enable_T_6 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_6 = or(enable_6, _anonOut_a_bits_data_masked_enable_T_6) node _anonOut_a_bits_data_masked_enable_T_7 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_7 = or(enable_7, _anonOut_a_bits_data_masked_enable_T_7) wire anonOut_a_bits_data_odata_0 : UInt connect anonOut_a_bits_data_odata_0, anonIn.a.bits.data wire anonOut_a_bits_data_odata_1 : UInt connect anonOut_a_bits_data_odata_1, anonIn.a.bits.data wire anonOut_a_bits_data_odata_2 : UInt connect anonOut_a_bits_data_odata_2, anonIn.a.bits.data wire anonOut_a_bits_data_odata_3 : UInt connect anonOut_a_bits_data_odata_3, anonIn.a.bits.data wire anonOut_a_bits_data_odata_4 : UInt connect anonOut_a_bits_data_odata_4, anonIn.a.bits.data wire anonOut_a_bits_data_odata_5 : UInt connect anonOut_a_bits_data_odata_5, anonIn.a.bits.data wire anonOut_a_bits_data_odata_6 : UInt connect anonOut_a_bits_data_odata_6, anonIn.a.bits.data wire anonOut_a_bits_data_odata_7 : UInt connect anonOut_a_bits_data_odata_7, anonIn.a.bits.data reg anonOut_a_bits_data_rdata : UInt<8>[7], clock node anonOut_a_bits_data_mdata_0 = mux(anonOut_a_bits_data_masked_enable_0, anonOut_a_bits_data_odata_0, anonOut_a_bits_data_rdata[0]) node anonOut_a_bits_data_mdata_1 = mux(anonOut_a_bits_data_masked_enable_1, anonOut_a_bits_data_odata_1, anonOut_a_bits_data_rdata[1]) node anonOut_a_bits_data_mdata_2 = mux(anonOut_a_bits_data_masked_enable_2, anonOut_a_bits_data_odata_2, anonOut_a_bits_data_rdata[2]) node anonOut_a_bits_data_mdata_3 = mux(anonOut_a_bits_data_masked_enable_3, anonOut_a_bits_data_odata_3, anonOut_a_bits_data_rdata[3]) node anonOut_a_bits_data_mdata_4 = mux(anonOut_a_bits_data_masked_enable_4, anonOut_a_bits_data_odata_4, anonOut_a_bits_data_rdata[4]) node anonOut_a_bits_data_mdata_5 = mux(anonOut_a_bits_data_masked_enable_5, anonOut_a_bits_data_odata_5, anonOut_a_bits_data_rdata[5]) node anonOut_a_bits_data_mdata_6 = mux(anonOut_a_bits_data_masked_enable_6, anonOut_a_bits_data_odata_6, anonOut_a_bits_data_rdata[6]) node anonOut_a_bits_data_mdata_7 = mux(anonOut_a_bits_data_masked_enable_7, anonOut_a_bits_data_odata_7, anonIn.a.bits.data) node _anonOut_a_bits_data_T = and(anonIn.a.ready, anonIn.a.valid) node _anonOut_a_bits_data_T_1 = eq(last, UInt<1>(0h0)) node _anonOut_a_bits_data_T_2 = and(_anonOut_a_bits_data_T, _anonOut_a_bits_data_T_1) when _anonOut_a_bits_data_T_2 : connect anonOut_a_bits_data_rdata_written_once, UInt<1>(0h1) connect anonOut_a_bits_data_rdata[0], anonOut_a_bits_data_mdata_0 connect anonOut_a_bits_data_rdata[1], anonOut_a_bits_data_mdata_1 connect anonOut_a_bits_data_rdata[2], anonOut_a_bits_data_mdata_2 connect anonOut_a_bits_data_rdata[3], anonOut_a_bits_data_mdata_3 connect anonOut_a_bits_data_rdata[4], anonOut_a_bits_data_mdata_4 connect anonOut_a_bits_data_rdata[5], anonOut_a_bits_data_mdata_5 connect anonOut_a_bits_data_rdata[6], anonOut_a_bits_data_mdata_6 node anonOut_a_bits_data_lo_lo = cat(anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0) node anonOut_a_bits_data_lo_hi = cat(anonOut_a_bits_data_mdata_3, anonOut_a_bits_data_mdata_2) node anonOut_a_bits_data_lo = cat(anonOut_a_bits_data_lo_hi, anonOut_a_bits_data_lo_lo) node anonOut_a_bits_data_hi_lo = cat(anonOut_a_bits_data_mdata_5, anonOut_a_bits_data_mdata_4) node anonOut_a_bits_data_hi_hi = cat(anonOut_a_bits_data_mdata_7, anonOut_a_bits_data_mdata_6) node anonOut_a_bits_data_hi = cat(anonOut_a_bits_data_hi_hi, anonOut_a_bits_data_hi_lo) node _anonOut_a_bits_data_T_3 = cat(anonOut_a_bits_data_hi, anonOut_a_bits_data_lo) connect anonOut.a.bits.data, _anonOut_a_bits_data_T_3 connect anonOut.a.bits.corrupt, corrupt_out node _anonOut_a_bits_mask_sizeOH_T = or(anonOut.a.bits.size, UInt<3>(0h0)) node anonOut_a_bits_mask_sizeOH_shiftAmount = bits(_anonOut_a_bits_mask_sizeOH_T, 1, 0) node _anonOut_a_bits_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), anonOut_a_bits_mask_sizeOH_shiftAmount) node _anonOut_a_bits_mask_sizeOH_T_2 = bits(_anonOut_a_bits_mask_sizeOH_T_1, 2, 0) node anonOut_a_bits_mask_sizeOH = or(_anonOut_a_bits_mask_sizeOH_T_2, UInt<1>(0h1)) node anonOut_a_bits_mask_sub_sub_sub_0_1 = geq(anonOut.a.bits.size, UInt<2>(0h3)) node anonOut_a_bits_mask_sub_sub_size = bits(anonOut_a_bits_mask_sizeOH, 2, 2) node anonOut_a_bits_mask_sub_sub_bit = bits(anonOut.a.bits.address, 2, 2) node anonOut_a_bits_mask_sub_sub_nbit = eq(anonOut_a_bits_mask_sub_sub_bit, UInt<1>(0h0)) node anonOut_a_bits_mask_sub_sub_0_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_nbit) node _anonOut_a_bits_mask_sub_sub_acc_T = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_0_2) node anonOut_a_bits_mask_sub_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T) node anonOut_a_bits_mask_sub_sub_1_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_bit) node _anonOut_a_bits_mask_sub_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_1_2) node anonOut_a_bits_mask_sub_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T_1) node anonOut_a_bits_mask_sub_size = bits(anonOut_a_bits_mask_sizeOH, 1, 1) node anonOut_a_bits_mask_sub_bit = bits(anonOut.a.bits.address, 1, 1) node anonOut_a_bits_mask_sub_nbit = eq(anonOut_a_bits_mask_sub_bit, UInt<1>(0h0)) node anonOut_a_bits_mask_sub_0_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_nbit) node _anonOut_a_bits_mask_sub_acc_T = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_0_2) node anonOut_a_bits_mask_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T) node anonOut_a_bits_mask_sub_1_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_bit) node _anonOut_a_bits_mask_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_1_2) node anonOut_a_bits_mask_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T_1) node anonOut_a_bits_mask_sub_2_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_nbit) node _anonOut_a_bits_mask_sub_acc_T_2 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_2_2) node anonOut_a_bits_mask_sub_2_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_2) node anonOut_a_bits_mask_sub_3_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_bit) node _anonOut_a_bits_mask_sub_acc_T_3 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_3_2) node anonOut_a_bits_mask_sub_3_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_3) node anonOut_a_bits_mask_size = bits(anonOut_a_bits_mask_sizeOH, 0, 0) node anonOut_a_bits_mask_bit = bits(anonOut.a.bits.address, 0, 0) node anonOut_a_bits_mask_nbit = eq(anonOut_a_bits_mask_bit, UInt<1>(0h0)) node anonOut_a_bits_mask_eq = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq) node anonOut_a_bits_mask_acc = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T) node anonOut_a_bits_mask_eq_1 = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_1 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_1) node anonOut_a_bits_mask_acc_1 = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T_1) node anonOut_a_bits_mask_eq_2 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_2 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_2) node anonOut_a_bits_mask_acc_2 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_2) node anonOut_a_bits_mask_eq_3 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_3 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_3) node anonOut_a_bits_mask_acc_3 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_3) node anonOut_a_bits_mask_eq_4 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_4 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_4) node anonOut_a_bits_mask_acc_4 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_4) node anonOut_a_bits_mask_eq_5 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_5 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_5) node anonOut_a_bits_mask_acc_5 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_5) node anonOut_a_bits_mask_eq_6 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_6 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_6) node anonOut_a_bits_mask_acc_6 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_6) node anonOut_a_bits_mask_eq_7 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_7 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_7) node anonOut_a_bits_mask_acc_7 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_7) node anonOut_a_bits_mask_lo_lo = cat(anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc) node anonOut_a_bits_mask_lo_hi = cat(anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2) node anonOut_a_bits_mask_lo = cat(anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo) node anonOut_a_bits_mask_hi_lo = cat(anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4) node anonOut_a_bits_mask_hi_hi = cat(anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6) node anonOut_a_bits_mask_hi = cat(anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo) node _anonOut_a_bits_mask_T = cat(anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo) regreset anonOut_a_bits_mask_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonOut_a_bits_mask_masked_enable_T = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_0 = or(enable_0, _anonOut_a_bits_mask_masked_enable_T) node _anonOut_a_bits_mask_masked_enable_T_1 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_1 = or(enable_1, _anonOut_a_bits_mask_masked_enable_T_1) node _anonOut_a_bits_mask_masked_enable_T_2 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_2 = or(enable_2, _anonOut_a_bits_mask_masked_enable_T_2) node _anonOut_a_bits_mask_masked_enable_T_3 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_3 = or(enable_3, _anonOut_a_bits_mask_masked_enable_T_3) node _anonOut_a_bits_mask_masked_enable_T_4 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_4 = or(enable_4, _anonOut_a_bits_mask_masked_enable_T_4) node _anonOut_a_bits_mask_masked_enable_T_5 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_5 = or(enable_5, _anonOut_a_bits_mask_masked_enable_T_5) node _anonOut_a_bits_mask_masked_enable_T_6 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_6 = or(enable_6, _anonOut_a_bits_mask_masked_enable_T_6) node _anonOut_a_bits_mask_masked_enable_T_7 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_7 = or(enable_7, _anonOut_a_bits_mask_masked_enable_T_7) wire anonOut_a_bits_mask_odata_0 : UInt connect anonOut_a_bits_mask_odata_0, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_1 : UInt connect anonOut_a_bits_mask_odata_1, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_2 : UInt connect anonOut_a_bits_mask_odata_2, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_3 : UInt connect anonOut_a_bits_mask_odata_3, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_4 : UInt connect anonOut_a_bits_mask_odata_4, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_5 : UInt connect anonOut_a_bits_mask_odata_5, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_6 : UInt connect anonOut_a_bits_mask_odata_6, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_7 : UInt connect anonOut_a_bits_mask_odata_7, anonIn.a.bits.mask reg anonOut_a_bits_mask_rdata : UInt<1>[7], clock node anonOut_a_bits_mask_mdata_0 = mux(anonOut_a_bits_mask_masked_enable_0, anonOut_a_bits_mask_odata_0, anonOut_a_bits_mask_rdata[0]) node anonOut_a_bits_mask_mdata_1 = mux(anonOut_a_bits_mask_masked_enable_1, anonOut_a_bits_mask_odata_1, anonOut_a_bits_mask_rdata[1]) node anonOut_a_bits_mask_mdata_2 = mux(anonOut_a_bits_mask_masked_enable_2, anonOut_a_bits_mask_odata_2, anonOut_a_bits_mask_rdata[2]) node anonOut_a_bits_mask_mdata_3 = mux(anonOut_a_bits_mask_masked_enable_3, anonOut_a_bits_mask_odata_3, anonOut_a_bits_mask_rdata[3]) node anonOut_a_bits_mask_mdata_4 = mux(anonOut_a_bits_mask_masked_enable_4, anonOut_a_bits_mask_odata_4, anonOut_a_bits_mask_rdata[4]) node anonOut_a_bits_mask_mdata_5 = mux(anonOut_a_bits_mask_masked_enable_5, anonOut_a_bits_mask_odata_5, anonOut_a_bits_mask_rdata[5]) node anonOut_a_bits_mask_mdata_6 = mux(anonOut_a_bits_mask_masked_enable_6, anonOut_a_bits_mask_odata_6, anonOut_a_bits_mask_rdata[6]) node anonOut_a_bits_mask_mdata_7 = mux(anonOut_a_bits_mask_masked_enable_7, anonOut_a_bits_mask_odata_7, anonIn.a.bits.mask) node _anonOut_a_bits_mask_T_1 = and(anonIn.a.ready, anonIn.a.valid) node _anonOut_a_bits_mask_T_2 = eq(last, UInt<1>(0h0)) node _anonOut_a_bits_mask_T_3 = and(_anonOut_a_bits_mask_T_1, _anonOut_a_bits_mask_T_2) when _anonOut_a_bits_mask_T_3 : connect anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h1) connect anonOut_a_bits_mask_rdata[0], anonOut_a_bits_mask_mdata_0 connect anonOut_a_bits_mask_rdata[1], anonOut_a_bits_mask_mdata_1 connect anonOut_a_bits_mask_rdata[2], anonOut_a_bits_mask_mdata_2 connect anonOut_a_bits_mask_rdata[3], anonOut_a_bits_mask_mdata_3 connect anonOut_a_bits_mask_rdata[4], anonOut_a_bits_mask_mdata_4 connect anonOut_a_bits_mask_rdata[5], anonOut_a_bits_mask_mdata_5 connect anonOut_a_bits_mask_rdata[6], anonOut_a_bits_mask_mdata_6 node anonOut_a_bits_mask_lo_lo_1 = cat(anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0) node anonOut_a_bits_mask_lo_hi_1 = cat(anonOut_a_bits_mask_mdata_3, anonOut_a_bits_mask_mdata_2) node anonOut_a_bits_mask_lo_1 = cat(anonOut_a_bits_mask_lo_hi_1, anonOut_a_bits_mask_lo_lo_1) node anonOut_a_bits_mask_hi_lo_1 = cat(anonOut_a_bits_mask_mdata_5, anonOut_a_bits_mask_mdata_4) node anonOut_a_bits_mask_hi_hi_1 = cat(anonOut_a_bits_mask_mdata_7, anonOut_a_bits_mask_mdata_6) node anonOut_a_bits_mask_hi_1 = cat(anonOut_a_bits_mask_hi_hi_1, anonOut_a_bits_mask_hi_lo_1) node _anonOut_a_bits_mask_T_4 = cat(anonOut_a_bits_mask_hi_1, anonOut_a_bits_mask_lo_1) node _anonOut_a_bits_mask_T_5 = not(UInt<8>(0h0)) node _anonOut_a_bits_mask_T_6 = mux(hasData, _anonOut_a_bits_mask_T_4, _anonOut_a_bits_mask_T_5) node _anonOut_a_bits_mask_T_7 = and(_anonOut_a_bits_mask_T, _anonOut_a_bits_mask_T_6) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T_7 wire repeat : UInt<1> inst repeated_repeater of Repeater_TLBundleD_a32d64s1k3z4u connect repeated_repeater.clock, clock connect repeated_repeater.reset, reset connect repeated_repeater.io.repeat, repeat connect repeated_repeater.io.enq, anonOut.d wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect cated.bits, repeated_repeater.io.deq.bits connect cated.valid, repeated_repeater.io.deq.valid connect repeated_repeater.io.deq.ready, cated.ready node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 63, 8) node _cated_bits_data_T_1 = bits(anonOut.d.bits.data, 7, 0) node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1) connect cated.bits.data, _cated_bits_data_T_2 node repeat_hasData = bits(cated.bits.opcode, 0, 0) node _repeat_limit_T = dshl(UInt<3>(0h7), cated.bits.size) node _repeat_limit_T_1 = bits(_repeat_limit_T, 2, 0) node _repeat_limit_T_2 = not(_repeat_limit_T_1) node repeat_limit = shr(_repeat_limit_T_2, 0) regreset repeat_count : UInt<3>, clock, reset, UInt<3>(0h0) node repeat_first = eq(repeat_count, UInt<1>(0h0)) node _repeat_last_T = eq(repeat_count, repeat_limit) node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0)) node repeat_last = or(_repeat_last_T, _repeat_last_T_1) node _repeat_T = and(anonIn.d.ready, anonIn.d.valid) when _repeat_T : node _repeat_count_T = add(repeat_count, UInt<1>(0h1)) node _repeat_count_T_1 = tail(_repeat_count_T, 1) connect repeat_count, _repeat_count_T_1 when repeat_last : connect repeat_count, UInt<1>(0h0) reg repeat_sel_sel_sources : UInt<3>[1], clock node repeat_sel_sel_a_sel = bits(anonIn.a.bits.address, 2, 0) node _repeat_sel_sel_T = and(anonIn.a.ready, anonIn.a.valid) when _repeat_sel_sel_T : connect repeat_sel_sel_sources[0], repeat_sel_sel_a_sel node _repeat_sel_sel_bypass_T = eq(anonIn.a.bits.source, UInt<0>(0h0)) node repeat_sel_sel_bypass = and(anonIn.a.valid, _repeat_sel_sel_bypass_T) reg repeat_sel_hold_r : UInt<3>, clock when repeat_first : connect repeat_sel_hold_r, repeat_sel_sel_sources[0] node repeat_sel_hold = mux(repeat_first, repeat_sel_sel_sources[0], repeat_sel_hold_r) node _repeat_sel_T = not(repeat_limit) node repeat_sel = and(repeat_sel_hold, _repeat_sel_T) node repeat_index = or(repeat_sel, repeat_count) connect anonIn.d.bits.corrupt, cated.bits.corrupt connect anonIn.d.bits.data, cated.bits.data connect anonIn.d.bits.denied, cated.bits.denied connect anonIn.d.bits.sink, cated.bits.sink connect anonIn.d.bits.source, cated.bits.source connect anonIn.d.bits.size, cated.bits.size connect anonIn.d.bits.param, cated.bits.param connect anonIn.d.bits.opcode, cated.bits.opcode connect anonIn.d.valid, cated.valid connect cated.ready, anonIn.d.ready node _repeat_anonIn_d_bits_data_mux_T = bits(cated.bits.data, 7, 0) node _repeat_anonIn_d_bits_data_mux_T_1 = bits(cated.bits.data, 15, 8) node _repeat_anonIn_d_bits_data_mux_T_2 = bits(cated.bits.data, 23, 16) node _repeat_anonIn_d_bits_data_mux_T_3 = bits(cated.bits.data, 31, 24) node _repeat_anonIn_d_bits_data_mux_T_4 = bits(cated.bits.data, 39, 32) node _repeat_anonIn_d_bits_data_mux_T_5 = bits(cated.bits.data, 47, 40) node _repeat_anonIn_d_bits_data_mux_T_6 = bits(cated.bits.data, 55, 48) node _repeat_anonIn_d_bits_data_mux_T_7 = bits(cated.bits.data, 63, 56) wire repeat_anonIn_d_bits_data_mux : UInt<8>[8] connect repeat_anonIn_d_bits_data_mux[0], _repeat_anonIn_d_bits_data_mux_T connect repeat_anonIn_d_bits_data_mux[1], _repeat_anonIn_d_bits_data_mux_T_1 connect repeat_anonIn_d_bits_data_mux[2], _repeat_anonIn_d_bits_data_mux_T_2 connect repeat_anonIn_d_bits_data_mux[3], _repeat_anonIn_d_bits_data_mux_T_3 connect repeat_anonIn_d_bits_data_mux[4], _repeat_anonIn_d_bits_data_mux_T_4 connect repeat_anonIn_d_bits_data_mux[5], _repeat_anonIn_d_bits_data_mux_T_5 connect repeat_anonIn_d_bits_data_mux[6], _repeat_anonIn_d_bits_data_mux_T_6 connect repeat_anonIn_d_bits_data_mux[7], _repeat_anonIn_d_bits_data_mux_T_7 connect anonIn.d.bits.data, repeat_anonIn_d_bits_data_mux[repeat_index] node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0)) connect repeat, _repeat_T_1 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<8>(0h0) connect _WIRE.bits.mask, UInt<1>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)
module TLWidthWidget1( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [63:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [7:0] _anonOut_a_bits_mask_T_5 = 8'hFF; // @[WidthWidget.scala:85:119] wire auto_anon_in_a_bits_mask = 1'h1; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_mask = 1'h1; // @[MixedNode.scala:551:17] wire anonOut_a_bits_mask_odata_0 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_1 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_2 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_3 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_4 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_5 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_6 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_7 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_mdata_7 = 1'h1; // @[WidthWidget.scala:68:88] wire _repeat_sel_sel_bypass_T = 1'h1; // @[WidthWidget.scala:200:53] wire [2:0] auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] anonOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire cated_bits_source = 1'h0; // @[WidthWidget.scala:161:25] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [7:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] wire _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire repeat_sel_sel_bypass = anonIn_a_valid; // @[WidthWidget.scala:200:33] assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] anonOut_a_bits_data_odata_0 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_1 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_2 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_3 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_4 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_5 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_6 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_7 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire cated_ready = anonIn_d_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_sink; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] wire cated_bits_denied; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_a_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] _anonOut_a_bits_mask_sizeOH_T = anonOut_a_bits_size; // @[Misc.scala:202:34] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] wire _hasData_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [17:0] _limit_T = 18'h7 << anonIn_a_bits_size; // @[package.scala:243:71] wire [2:0] _limit_T_1 = _limit_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire [2:0] limit = _limit_T_2; // @[package.scala:243:46] reg [2:0] count; // @[WidthWidget.scala:40:27] wire [2:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = count == 3'h0; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire [2:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = |_enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_3 = {count[2:1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = |_enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_6 = {count[2], count[1:0] ^ 2'h2}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_8 = |_enable_T_7; // @[WidthWidget.scala:43:{63,72}] wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_9 = {count[2], ~(count[1:0])}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_11 = |_enable_T_10; // @[WidthWidget.scala:43:{63,72}] wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_12 = count ^ 3'h4; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_13 = _enable_T_12 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_14 = |_enable_T_13; // @[WidthWidget.scala:43:{63,72}] wire enable_4 = ~_enable_T_14; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_15 = count ^ 3'h5; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_16 = _enable_T_15 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_17 = |_enable_T_16; // @[WidthWidget.scala:43:{63,72}] wire enable_5 = ~_enable_T_17; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_18 = count ^ 3'h6; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_19 = _enable_T_18 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_20 = |_enable_T_19; // @[WidthWidget.scala:43:{63,72}] wire enable_6 = ~_enable_T_20; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_21 = ~count; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_22 = _enable_T_21 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_23 = |_enable_T_22; // @[WidthWidget.scala:43:{63,72}] wire enable_7 = ~_enable_T_23; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonOut_a_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _T = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35] wire _anonOut_a_bits_data_T; // @[Decoupled.scala:51:35] assign _anonOut_a_bits_data_T = _T; // @[Decoupled.scala:51:35] wire _anonOut_a_bits_mask_T_1; // @[Decoupled.scala:51:35] assign _anonOut_a_bits_mask_T_1 = _T; // @[Decoupled.scala:51:35] wire _repeat_sel_sel_T; // @[Decoupled.scala:51:35] assign _repeat_sel_sel_T = _T; // @[Decoupled.scala:51:35] wire [3:0] _count_T = {1'h0, count} + 4'h1; // @[WidthWidget.scala:40:27, :50:24] wire [2:0] _count_T_1 = _count_T[2:0]; // @[WidthWidget.scala:50:24] wire _anonIn_a_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonIn_a_ready_T_1 = anonOut_a_ready | _anonIn_a_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonIn_a_ready = _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonOut_a_valid_T = anonIn_a_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonOut_a_valid = _anonOut_a_valid_T; // @[WidthWidget.scala:77:29] reg anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonOut_a_bits_data_masked_enable_T = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_0 = enable_0 | _anonOut_a_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_1 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_1 = enable_1 | _anonOut_a_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_2 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_2 = enable_2 | _anonOut_a_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_3 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_3 = enable_3 | _anonOut_a_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_4 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_4 = enable_4 | _anonOut_a_bits_data_masked_enable_T_4; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_5 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_5 = enable_5 | _anonOut_a_bits_data_masked_enable_T_5; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_6 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_6 = enable_6 | _anonOut_a_bits_data_masked_enable_T_6; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_7 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_7 = enable_7 | _anonOut_a_bits_data_masked_enable_T_7; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [7:0] anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_1; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_2; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_3; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_4; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_5; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_6; // @[WidthWidget.scala:66:24] wire [7:0] anonOut_a_bits_data_mdata_0 = anonOut_a_bits_data_masked_enable_0 ? anonOut_a_bits_data_odata_0 : anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_1 = anonOut_a_bits_data_masked_enable_1 ? anonOut_a_bits_data_odata_1 : anonOut_a_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_2 = anonOut_a_bits_data_masked_enable_2 ? anonOut_a_bits_data_odata_2 : anonOut_a_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_3 = anonOut_a_bits_data_masked_enable_3 ? anonOut_a_bits_data_odata_3 : anonOut_a_bits_data_rdata_3; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_4 = anonOut_a_bits_data_masked_enable_4 ? anonOut_a_bits_data_odata_4 : anonOut_a_bits_data_rdata_4; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_5 = anonOut_a_bits_data_masked_enable_5 ? anonOut_a_bits_data_odata_5 : anonOut_a_bits_data_rdata_5; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_6 = anonOut_a_bits_data_masked_enable_6 ? anonOut_a_bits_data_odata_6 : anonOut_a_bits_data_rdata_6; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_7 = anonOut_a_bits_data_masked_enable_7 ? anonOut_a_bits_data_odata_7 : anonIn_a_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonOut_a_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonOut_a_bits_data_T_2 = _anonOut_a_bits_data_T & _anonOut_a_bits_data_T_1; // @[Decoupled.scala:51:35] wire [15:0] anonOut_a_bits_data_lo_lo = {anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [15:0] anonOut_a_bits_data_lo_hi = {anonOut_a_bits_data_mdata_3, anonOut_a_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] wire [31:0] anonOut_a_bits_data_lo = {anonOut_a_bits_data_lo_hi, anonOut_a_bits_data_lo_lo}; // @[WidthWidget.scala:73:12] wire [15:0] anonOut_a_bits_data_hi_lo = {anonOut_a_bits_data_mdata_5, anonOut_a_bits_data_mdata_4}; // @[WidthWidget.scala:68:88, :73:12] wire [15:0] anonOut_a_bits_data_hi_hi = {anonOut_a_bits_data_mdata_7, anonOut_a_bits_data_mdata_6}; // @[WidthWidget.scala:68:88, :73:12] wire [31:0] anonOut_a_bits_data_hi = {anonOut_a_bits_data_hi_hi, anonOut_a_bits_data_hi_lo}; // @[WidthWidget.scala:73:12] assign _anonOut_a_bits_data_T_3 = {anonOut_a_bits_data_hi, anonOut_a_bits_data_lo}; // @[WidthWidget.scala:73:12] assign anonOut_a_bits_data = _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12] wire [1:0] anonOut_a_bits_mask_sizeOH_shiftAmount = _anonOut_a_bits_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _anonOut_a_bits_mask_sizeOH_T_1 = 4'h1 << anonOut_a_bits_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _anonOut_a_bits_mask_sizeOH_T_2 = _anonOut_a_bits_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] anonOut_a_bits_mask_sizeOH = {_anonOut_a_bits_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire anonOut_a_bits_mask_sub_sub_sub_0_1 = anonOut_a_bits_size > 4'h2; // @[Misc.scala:206:21] wire anonOut_a_bits_mask_sub_sub_size = anonOut_a_bits_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_sub_sub_bit = anonOut_a_bits_address[2]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_sub_sub_1_2 = anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire anonOut_a_bits_mask_sub_sub_nbit = ~anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_sub_sub_0_2 = anonOut_a_bits_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_sub_acc_T = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_0_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _anonOut_a_bits_mask_sub_sub_acc_T_1 = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_1_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire anonOut_a_bits_mask_sub_size = anonOut_a_bits_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_sub_bit = anonOut_a_bits_address[1]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_sub_nbit = ~anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_sub_0_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_acc_T = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_0_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_1_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_1 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_1_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_2_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_2 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_2_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_3_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_3 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_3_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_size = anonOut_a_bits_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_bit = anonOut_a_bits_address[0]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_nbit = ~anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_eq = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_1 = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_1 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_1 = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_2 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_2 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_2 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_3 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_3 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_3 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_4 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_4 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_4 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_5 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_5 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_5 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_6 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_6 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_6 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_7 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_7 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_7 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] anonOut_a_bits_mask_lo_lo = {anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] anonOut_a_bits_mask_lo_hi = {anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] anonOut_a_bits_mask_lo = {anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] anonOut_a_bits_mask_hi_lo = {anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] anonOut_a_bits_mask_hi_hi = {anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] anonOut_a_bits_mask_hi = {anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] _anonOut_a_bits_mask_T = {anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo}; // @[Misc.scala:222:10] reg anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonOut_a_bits_mask_masked_enable_T = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_0 = enable_0 | _anonOut_a_bits_mask_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_1 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_1 = enable_1 | _anonOut_a_bits_mask_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_2 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_2 = enable_2 | _anonOut_a_bits_mask_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_3 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_3 = enable_3 | _anonOut_a_bits_mask_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_4 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_4 = enable_4 | _anonOut_a_bits_mask_masked_enable_T_4; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_5 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_5 = enable_5 | _anonOut_a_bits_mask_masked_enable_T_5; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_6 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_6 = enable_6 | _anonOut_a_bits_mask_masked_enable_T_6; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_7 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_7 = enable_7 | _anonOut_a_bits_mask_masked_enable_T_7; // @[WidthWidget.scala:43:47, :63:{42,45}] reg anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_1; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_2; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_3; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_4; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_5; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_6; // @[WidthWidget.scala:66:24] wire anonOut_a_bits_mask_mdata_0 = anonOut_a_bits_mask_masked_enable_0 | anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_1 = anonOut_a_bits_mask_masked_enable_1 | anonOut_a_bits_mask_rdata_1; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_2 = anonOut_a_bits_mask_masked_enable_2 | anonOut_a_bits_mask_rdata_2; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_3 = anonOut_a_bits_mask_masked_enable_3 | anonOut_a_bits_mask_rdata_3; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_4 = anonOut_a_bits_mask_masked_enable_4 | anonOut_a_bits_mask_rdata_4; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_5 = anonOut_a_bits_mask_masked_enable_5 | anonOut_a_bits_mask_rdata_5; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_6 = anonOut_a_bits_mask_masked_enable_6 | anonOut_a_bits_mask_rdata_6; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire _anonOut_a_bits_mask_T_2 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonOut_a_bits_mask_T_3 = _anonOut_a_bits_mask_T_1 & _anonOut_a_bits_mask_T_2; // @[Decoupled.scala:51:35] wire [1:0] anonOut_a_bits_mask_lo_lo_1 = {anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [1:0] anonOut_a_bits_mask_lo_hi_1 = {anonOut_a_bits_mask_mdata_3, anonOut_a_bits_mask_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] wire [3:0] anonOut_a_bits_mask_lo_1 = {anonOut_a_bits_mask_lo_hi_1, anonOut_a_bits_mask_lo_lo_1}; // @[WidthWidget.scala:73:12] wire [1:0] anonOut_a_bits_mask_hi_lo_1 = {anonOut_a_bits_mask_mdata_5, anonOut_a_bits_mask_mdata_4}; // @[WidthWidget.scala:68:88, :73:12] wire [1:0] anonOut_a_bits_mask_hi_hi_1 = {1'h1, anonOut_a_bits_mask_mdata_6}; // @[WidthWidget.scala:68:88, :73:12] wire [3:0] anonOut_a_bits_mask_hi_1 = {anonOut_a_bits_mask_hi_hi_1, anonOut_a_bits_mask_hi_lo_1}; // @[WidthWidget.scala:73:12] wire [7:0] _anonOut_a_bits_mask_T_4 = {anonOut_a_bits_mask_hi_1, anonOut_a_bits_mask_lo_1}; // @[WidthWidget.scala:73:12] wire [7:0] _anonOut_a_bits_mask_T_6 = hasData ? _anonOut_a_bits_mask_T_4 : 8'hFF; // @[WidthWidget.scala:73:12, :85:93] assign _anonOut_a_bits_mask_T_7 = _anonOut_a_bits_mask_T & _anonOut_a_bits_mask_T_6; // @[Misc.scala:222:10] assign anonOut_a_bits_mask = _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonIn_d_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_sink = cated_bits_sink; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_denied = cated_bits_denied; // @[WidthWidget.scala:161:25] wire [63:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonIn_d_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [63:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [55:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[63:8]; // @[Repeater.scala:36:26] wire [7:0] _cated_bits_data_T_1 = anonOut_d_bits_data[7:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire repeat_hasData = cated_bits_opcode[0]; // @[WidthWidget.scala:161:25] wire [17:0] _repeat_limit_T = 18'h7 << cated_bits_size; // @[package.scala:243:71] wire [2:0] _repeat_limit_T_1 = _repeat_limit_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire [2:0] repeat_limit = _repeat_limit_T_2; // @[package.scala:243:46] reg [2:0] repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = repeat_count == 3'h0; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35] wire [3:0] _repeat_count_T = {1'h0, repeat_count} + 4'h1; // @[WidthWidget.scala:105:26, :110:24] wire [2:0] _repeat_count_T_1 = _repeat_count_T[2:0]; // @[WidthWidget.scala:110:24] reg [2:0] repeat_sel_sel_sources_0; // @[WidthWidget.scala:187:27] wire [2:0] repeat_sel_sel_a_sel = anonIn_a_bits_address[2:0]; // @[WidthWidget.scala:188:38] reg [2:0] repeat_sel_hold_r; // @[WidthWidget.scala:121:47] wire [2:0] repeat_sel_hold = repeat_first ? repeat_sel_sel_sources_0 : repeat_sel_hold_r; // @[WidthWidget.scala:106:25, :121:{25,47}, :187:27] wire [2:0] _repeat_sel_T = ~repeat_limit; // @[WidthWidget.scala:103:47, :122:18] wire [2:0] repeat_sel = repeat_sel_hold & _repeat_sel_T; // @[WidthWidget.scala:121:25, :122:{16,18}] wire [2:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :122:16, :126:24] wire [7:0] _repeat_anonIn_d_bits_data_mux_T = cated_bits_data[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_0 = _repeat_anonIn_d_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_1 = cated_bits_data[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_1 = _repeat_anonIn_d_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_2 = cated_bits_data[23:16]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_2 = _repeat_anonIn_d_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_3 = cated_bits_data[31:24]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_3 = _repeat_anonIn_d_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_4 = cated_bits_data[39:32]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_4 = _repeat_anonIn_d_bits_data_mux_T_4; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_5 = cated_bits_data[47:40]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_5 = _repeat_anonIn_d_bits_data_mux_T_5; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_6 = cated_bits_data[55:48]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_6 = _repeat_anonIn_d_bits_data_mux_T_6; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_7 = cated_bits_data[63:56]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_7 = _repeat_anonIn_d_bits_data_mux_T_7; // @[WidthWidget.scala:128:{43,55}] wire [7:0][7:0] _GEN = {{repeat_anonIn_d_bits_data_mux_7}, {repeat_anonIn_d_bits_data_mux_6}, {repeat_anonIn_d_bits_data_mux_5}, {repeat_anonIn_d_bits_data_mux_4}, {repeat_anonIn_d_bits_data_mux_3}, {repeat_anonIn_d_bits_data_mux_2}, {repeat_anonIn_d_bits_data_mux_1}, {repeat_anonIn_d_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30] assign anonIn_d_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] count <= 3'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonOut_a_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] anonOut_a_bits_mask_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] repeat_count <= 3'h0; // @[WidthWidget.scala:105:26] end else begin // @[WidthWidget.scala:27:9] if (_T) begin // @[Decoupled.scala:51:35] count <= last ? 3'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23] end anonOut_a_bits_data_rdata_written_once <= _anonOut_a_bits_data_T_2 | anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] anonOut_a_bits_mask_rdata_written_once <= _anonOut_a_bits_mask_T_3 | anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= repeat_last ? 3'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] end if (_anonOut_a_bits_data_T_2) begin // @[WidthWidget.scala:69:23] anonOut_a_bits_data_rdata_0 <= anonOut_a_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_1 <= anonOut_a_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_2 <= anonOut_a_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_3 <= anonOut_a_bits_data_mdata_3; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_4 <= anonOut_a_bits_data_mdata_4; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_5 <= anonOut_a_bits_data_mdata_5; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_6 <= anonOut_a_bits_data_mdata_6; // @[WidthWidget.scala:66:24, :68:88] end if (_anonOut_a_bits_mask_T_3) begin // @[WidthWidget.scala:69:23] anonOut_a_bits_mask_rdata_0 <= anonOut_a_bits_mask_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_1 <= anonOut_a_bits_mask_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_2 <= anonOut_a_bits_mask_mdata_2; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_3 <= anonOut_a_bits_mask_mdata_3; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_4 <= anonOut_a_bits_mask_mdata_4; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_5 <= anonOut_a_bits_mask_mdata_5; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_6 <= anonOut_a_bits_mask_mdata_6; // @[WidthWidget.scala:66:24, :68:88] end if (_repeat_sel_sel_T) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_0 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (repeat_first) // @[WidthWidget.scala:106:25] repeat_sel_hold_r <= repeat_sel_sel_sources_0; // @[WidthWidget.scala:121:47, :187:27] always @(posedge) TLMonitor_30 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleD_a32d64s1k3z4u repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonOut_d_ready), .io_enq_valid (anonOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (anonOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (anonOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (anonOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_sink (anonOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (anonOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (anonOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (anonOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_sink (cated_bits_sink), .io_deq_bits_denied (cated_bits_denied), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNPipe_l2_e5_s11_3 : input clock : Clock input reset : Reset output io : { flip validin : UInt<1>, flip op : UInt<2>, flip a : UInt<17>, flip b : UInt<17>, flip c : UInt<17>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>, validout : UInt<1>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e5_s11_3 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e5_s11_3 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) wire valid_stage0 : UInt<1> wire roundingMode_stage0 : UInt<3> wire detectTininess_stage0 : UInt<1> regreset mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b, mulAddRecFNToRaw_preMul.io.toPostMul wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out : { valid : UInt<1>, bits : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}} connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.valid, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isSigNaNAny regreset mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b : UInt<23>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b, mulAddResult wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out : { valid : UInt<1>, bits : UInt<23>} connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.valid, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits regreset mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b : UInt<3>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b, io.roundingMode wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.valid, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b connect mulAddRecFNToRaw_postMul.io.roundingMode, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits regreset roundingMode_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundingMode_stage0_pipe_v, io.validin reg roundingMode_stage0_pipe_b : UInt<3>, clock when io.validin : connect roundingMode_stage0_pipe_b, io.roundingMode wire roundingMode_stage0_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundingMode_stage0_pipe_out.valid, roundingMode_stage0_pipe_v connect roundingMode_stage0_pipe_out.bits, roundingMode_stage0_pipe_b connect roundingMode_stage0, roundingMode_stage0_pipe_out.bits regreset detectTininess_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect detectTininess_stage0_pipe_v, io.validin reg detectTininess_stage0_pipe_b : UInt<1>, clock when io.validin : connect detectTininess_stage0_pipe_b, io.detectTininess wire detectTininess_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect detectTininess_stage0_pipe_out.valid, detectTininess_stage0_pipe_v connect detectTininess_stage0_pipe_out.bits, detectTininess_stage0_pipe_b connect detectTininess_stage0, detectTininess_stage0_pipe_out.bits regreset valid_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect valid_stage0_pipe_v, io.validin reg valid_stage0_pipe_b : UInt<1>, clock when io.validin : connect valid_stage0_pipe_b, UInt<1>(0h0) wire valid_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect valid_stage0_pipe_out.valid, valid_stage0_pipe_v connect valid_stage0_pipe_out.bits, valid_stage0_pipe_b connect valid_stage0, valid_stage0_pipe_out.valid inst roundRawFNToRecFN of RoundRawFNToRecFN_e5_s11_6 regreset roundRawFNToRecFN_io_invalidExc_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_invalidExc_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_invalidExc_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_invalidExc_pipe_b, mulAddRecFNToRaw_postMul.io.invalidExc wire roundRawFNToRecFN_io_invalidExc_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_invalidExc_pipe_out.valid, roundRawFNToRecFN_io_invalidExc_pipe_v connect roundRawFNToRecFN_io_invalidExc_pipe_out.bits, roundRawFNToRecFN_io_invalidExc_pipe_b connect roundRawFNToRecFN.io.invalidExc, roundRawFNToRecFN_io_invalidExc_pipe_out.bits regreset roundRawFNToRecFN_io_in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_in_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_in_pipe_b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, clock when valid_stage0 : connect roundRawFNToRecFN_io_in_pipe_b, mulAddRecFNToRaw_postMul.io.rawOut wire roundRawFNToRecFN_io_in_pipe_out : { valid : UInt<1>, bits : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} connect roundRawFNToRecFN_io_in_pipe_out.valid, roundRawFNToRecFN_io_in_pipe_v connect roundRawFNToRecFN_io_in_pipe_out.bits, roundRawFNToRecFN_io_in_pipe_b connect roundRawFNToRecFN.io.in.sig, roundRawFNToRecFN_io_in_pipe_out.bits.sig connect roundRawFNToRecFN.io.in.sExp, roundRawFNToRecFN_io_in_pipe_out.bits.sExp connect roundRawFNToRecFN.io.in.sign, roundRawFNToRecFN_io_in_pipe_out.bits.sign connect roundRawFNToRecFN.io.in.isZero, roundRawFNToRecFN_io_in_pipe_out.bits.isZero connect roundRawFNToRecFN.io.in.isInf, roundRawFNToRecFN_io_in_pipe_out.bits.isInf connect roundRawFNToRecFN.io.in.isNaN, roundRawFNToRecFN_io_in_pipe_out.bits.isNaN regreset roundRawFNToRecFN_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_roundingMode_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_roundingMode_pipe_b : UInt<3>, clock when valid_stage0 : connect roundRawFNToRecFN_io_roundingMode_pipe_b, roundingMode_stage0 wire roundRawFNToRecFN_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundRawFNToRecFN_io_roundingMode_pipe_out.valid, roundRawFNToRecFN_io_roundingMode_pipe_v connect roundRawFNToRecFN_io_roundingMode_pipe_out.bits, roundRawFNToRecFN_io_roundingMode_pipe_b connect roundRawFNToRecFN.io.roundingMode, roundRawFNToRecFN_io_roundingMode_pipe_out.bits regreset roundRawFNToRecFN_io_detectTininess_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_detectTininess_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_detectTininess_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_detectTininess_pipe_b, detectTininess_stage0 wire roundRawFNToRecFN_io_detectTininess_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_detectTininess_pipe_out.valid, roundRawFNToRecFN_io_detectTininess_pipe_v connect roundRawFNToRecFN_io_detectTininess_pipe_out.bits, roundRawFNToRecFN_io_detectTininess_pipe_b connect roundRawFNToRecFN.io.detectTininess, roundRawFNToRecFN_io_detectTininess_pipe_out.bits regreset io_validout_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_validout_pipe_v, valid_stage0 reg io_validout_pipe_b : UInt<1>, clock when valid_stage0 : connect io_validout_pipe_b, UInt<1>(0h0) wire io_validout_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect io_validout_pipe_out.valid, io_validout_pipe_v connect io_validout_pipe_out.bits, io_validout_pipe_b connect io.validout, io_validout_pipe_out.valid connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags
module MulAddRecFNPipe_l2_e5_s11_3( // @[FPU.scala:633:7] input clock, // @[FPU.scala:633:7] input reset, // @[FPU.scala:633:7] input io_validin, // @[FPU.scala:638:16] input [1:0] io_op, // @[FPU.scala:638:16] input [16:0] io_a, // @[FPU.scala:638:16] input [16:0] io_b, // @[FPU.scala:638:16] input [16:0] io_c, // @[FPU.scala:638:16] input [2:0] io_roundingMode, // @[FPU.scala:638:16] output [16:0] io_out, // @[FPU.scala:638:16] output [4:0] io_exceptionFlags, // @[FPU.scala:638:16] output io_validout // @[FPU.scala:638:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42] wire [6:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42] wire [13:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42] wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41] wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41] wire [21:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41] wire [6:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41] wire [3:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41] wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41] wire io_validin_0 = io_validin; // @[FPU.scala:633:7] wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7] wire [16:0] io_a_0 = io_a; // @[FPU.scala:633:7] wire [16:0] io_b_0 = io_b; // @[FPU.scala:633:7] wire [16:0] io_c_0 = io_c; // @[FPU.scala:633:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7] wire io_detectTininess = 1'h1; // @[FPU.scala:633:7] wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37] wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21] wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_valid; // @[Valid.scala:135:21] wire [16:0] io_out_0; // @[FPU.scala:633:7] wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7] wire io_validout_0; // @[FPU.scala:633:7] wire [21:0] _mulAddResult_T = {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45] wire [22:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50] wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] wire valid_stage0; // @[FPU.scala:667:28] wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26] reg [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26] wire [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26] reg [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26] wire [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26] reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26] wire [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24] reg [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26] wire [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24] wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26] assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26] assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24] wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg valid_stage0_pipe_v; // @[Valid.scala:141:24] assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26] reg [6:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26] wire [6:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26] reg [13:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26] wire [13:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26] reg io_validout_pipe_v; // @[Valid.scala:141:24] assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24] assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:633:7] if (reset) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24] io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24] end if (io_validin_0) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] end if (valid_stage0) begin // @[FPU.scala:667:28] roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26] roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26] end roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 | roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] always @(posedge) MulAddRecFNToRaw_preMul_e5_s11_3 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41] .io_op (io_op_0), // @[FPU.scala:633:7] .io_a (io_a_0), // @[FPU.scala:633:7] .io_b (io_b_0), // @[FPU.scala:633:7] .io_c (io_c_0), // @[FPU.scala:633:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[FPU.scala:654:41] MulAddRecFNToRaw_postMul_e5_s11_3 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42] .io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21] .io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21] .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21] .io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21] .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21] .io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21] .io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21] .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21] .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21] .io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21] .io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21] .io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21] .io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21] .io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21] .io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21] .io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21] .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21] .io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[FPU.scala:655:42] RoundRawFNToRecFN_e5_s11_6 roundRawFNToRecFN ( // @[FPU.scala:682:35] .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21] .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21] .io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21] .io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21] .io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21] .io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21] .io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21] .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[FPU.scala:682:35] assign io_out = io_out_0; // @[FPU.scala:633:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7] assign io_validout = io_validout_0; // @[FPU.scala:633:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_10 : input clock : Clock input reset : Reset output io : { req : { flip `4` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}}, resp : { `4` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `3` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `2` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `1` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `0` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<17> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<12> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_andMatrixInput_2) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node _decoded_orMatrixOutputs_T = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_lo_lo_hi = cat(_decoded_orMatrixOutputs_T_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi = cat(decoded_orMatrixOutputs_lo_hi_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo = cat(decoded_orMatrixOutputs_hi_lo_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs, 9, 9) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs, 10, 10) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs, 11, 11) node decoded_invMatrixOutputs_lo_lo_hi = cat(_decoded_invMatrixOutputs_T_2, _decoded_invMatrixOutputs_T_1) node decoded_invMatrixOutputs_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_hi, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_lo_hi = cat(decoded_invMatrixOutputs_lo_hi_hi, _decoded_invMatrixOutputs_T_3) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo_hi = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_hi_lo = cat(decoded_invMatrixOutputs_hi_lo_hi, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10) node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 7, 0) node _decoded_T_1 = shl(UInt<4>(0hf), 4) node _decoded_T_2 = xor(UInt<8>(0hff), _decoded_T_1) node _decoded_T_3 = shr(_decoded_T, 4) node _decoded_T_4 = and(_decoded_T_3, _decoded_T_2) node _decoded_T_5 = bits(_decoded_T, 3, 0) node _decoded_T_6 = shl(_decoded_T_5, 4) node _decoded_T_7 = not(_decoded_T_2) node _decoded_T_8 = and(_decoded_T_6, _decoded_T_7) node _decoded_T_9 = or(_decoded_T_4, _decoded_T_8) node _decoded_T_10 = bits(_decoded_T_2, 5, 0) node _decoded_T_11 = shl(_decoded_T_10, 2) node _decoded_T_12 = xor(_decoded_T_2, _decoded_T_11) node _decoded_T_13 = shr(_decoded_T_9, 2) node _decoded_T_14 = and(_decoded_T_13, _decoded_T_12) node _decoded_T_15 = bits(_decoded_T_9, 5, 0) node _decoded_T_16 = shl(_decoded_T_15, 2) node _decoded_T_17 = not(_decoded_T_12) node _decoded_T_18 = and(_decoded_T_16, _decoded_T_17) node _decoded_T_19 = or(_decoded_T_14, _decoded_T_18) node _decoded_T_20 = bits(_decoded_T_12, 6, 0) node _decoded_T_21 = shl(_decoded_T_20, 1) node _decoded_T_22 = xor(_decoded_T_12, _decoded_T_21) node _decoded_T_23 = shr(_decoded_T_19, 1) node _decoded_T_24 = and(_decoded_T_23, _decoded_T_22) node _decoded_T_25 = bits(_decoded_T_19, 6, 0) node _decoded_T_26 = shl(_decoded_T_25, 1) node _decoded_T_27 = not(_decoded_T_22) node _decoded_T_28 = and(_decoded_T_26, _decoded_T_27) node _decoded_T_29 = or(_decoded_T_24, _decoded_T_28) node _decoded_T_30 = bits(decoded_plaOutput, 11, 8) node _decoded_T_31 = bits(_decoded_T_30, 1, 0) node _decoded_T_32 = bits(_decoded_T_31, 0, 0) node _decoded_T_33 = bits(_decoded_T_31, 1, 1) node _decoded_T_34 = cat(_decoded_T_32, _decoded_T_33) node _decoded_T_35 = bits(_decoded_T_30, 3, 2) node _decoded_T_36 = bits(_decoded_T_35, 0, 0) node _decoded_T_37 = bits(_decoded_T_35, 1, 1) node _decoded_T_38 = cat(_decoded_T_36, _decoded_T_37) node _decoded_T_39 = cat(_decoded_T_34, _decoded_T_38) node decoded = cat(_decoded_T_29, _decoded_T_39) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_1_0_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`1`[0], _io_resp_0_vc_sel_1_0_T node _io_resp_0_vc_sel_1_1_T = bits(decoded, 4, 4) connect io.resp.`0`.vc_sel.`1`[1], _io_resp_0_vc_sel_1_1_T node _io_resp_0_vc_sel_1_2_T = bits(decoded, 5, 5) connect io.resp.`0`.vc_sel.`1`[2], _io_resp_0_vc_sel_1_2_T node _io_resp_0_vc_sel_2_0_T = bits(decoded, 6, 6) connect io.resp.`0`.vc_sel.`2`[0], _io_resp_0_vc_sel_2_0_T node _io_resp_0_vc_sel_2_1_T = bits(decoded, 7, 7) connect io.resp.`0`.vc_sel.`2`[1], _io_resp_0_vc_sel_2_1_T node _io_resp_0_vc_sel_2_2_T = bits(decoded, 8, 8) connect io.resp.`0`.vc_sel.`2`[2], _io_resp_0_vc_sel_2_2_T node _io_resp_0_vc_sel_3_0_T = bits(decoded, 9, 9) connect io.resp.`0`.vc_sel.`3`[0], _io_resp_0_vc_sel_3_0_T node _io_resp_0_vc_sel_3_1_T = bits(decoded, 10, 10) connect io.resp.`0`.vc_sel.`3`[1], _io_resp_0_vc_sel_3_1_T node _io_resp_0_vc_sel_3_2_T = bits(decoded, 11, 11) connect io.resp.`0`.vc_sel.`3`[2], _io_resp_0_vc_sel_3_2_T connect io.resp.`0`.vc_sel.`4`[0], UInt<1>(0h0) connect io.resp.`0`.vc_sel.`5`[0], UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<17> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<12> node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_plaInput_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_10, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_12) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_7, decoded_andMatrixOutputs_andMatrixInput_8) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_9) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_6) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_plaInput_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_10_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_12_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_1, decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_9_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_4_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_6_1) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_3, decoded_andMatrixOutputs_andMatrixInput_3_1) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_8_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_12_2, decoded_andMatrixOutputs_andMatrixInput_13) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_14) node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_10_2, decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_lo_hi_lo) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_4_2, decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo) node decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_4, decoded_andMatrixOutputs_andMatrixInput_3_2) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_hi_hi_lo_2) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_12_3, decoded_andMatrixOutputs_andMatrixInput_13_1) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_14_1) node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_10_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_lo_hi_lo_1) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_3, decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_4_3, decoded_andMatrixOutputs_andMatrixInput_5_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_hi_lo_lo_1) node decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_2_5, decoded_andMatrixOutputs_andMatrixInput_3_3) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_hi_hi_lo_3) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_7_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_12_4, decoded_andMatrixOutputs_andMatrixInput_13_2) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_14_2) node decoded_andMatrixOutputs_lo_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_10_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_8_4, decoded_andMatrixOutputs_andMatrixInput_9_4) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo_2) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_4_4, decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_hi_lo_lo_2) node decoded_andMatrixOutputs_hi_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_2_6, decoded_andMatrixOutputs_andMatrixInput_3_4) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo_4) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_6) node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_12_5, decoded_andMatrixOutputs_andMatrixInput_13_3) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_14_3) node decoded_andMatrixOutputs_lo_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_10_5, decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_lo_hi_lo_3) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_4_5, decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_3) node decoded_andMatrixOutputs_hi_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_2_7, decoded_andMatrixOutputs_andMatrixInput_3_5) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_hi_hi_lo_5) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_plaInput_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_6) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_9_2 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_plaInput_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_7) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_9) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_andMatrixOutputs_andMatrixInput_10_8) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_lo_lo_hi_8, decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_8_8) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_andMatrixOutputs_andMatrixInput_10_9) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_lo_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_8_9) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_11) node _decoded_orMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_5_2) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_6_2, decoded_andMatrixOutputs_8_2) node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) node _decoded_orMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_7 = orr(_decoded_orMatrixOutputs_T_6) node _decoded_orMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_3_2) node _decoded_orMatrixOutputs_T_9 = orr(_decoded_orMatrixOutputs_T_8) node _decoded_orMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_4_2, decoded_andMatrixOutputs_7_2) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node decoded_orMatrixOutputs_lo_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_3, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_1 = cat(decoded_orMatrixOutputs_lo_lo_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_5, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_1 = cat(decoded_orMatrixOutputs_lo_hi_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_1 = cat(decoded_orMatrixOutputs_hi_lo_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_11, _decoded_orMatrixOutputs_T_9) node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_7) node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_18 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_19 = bits(decoded_orMatrixOutputs_1, 7, 7) node _decoded_invMatrixOutputs_T_20 = bits(decoded_orMatrixOutputs_1, 8, 8) node _decoded_invMatrixOutputs_T_21 = bits(decoded_orMatrixOutputs_1, 9, 9) node _decoded_invMatrixOutputs_T_22 = bits(decoded_orMatrixOutputs_1, 10, 10) node _decoded_invMatrixOutputs_T_23 = bits(decoded_orMatrixOutputs_1, 11, 11) node decoded_invMatrixOutputs_lo_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_1, _decoded_invMatrixOutputs_T_12) node decoded_invMatrixOutputs_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_1, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_20, _decoded_invMatrixOutputs_T_19) node decoded_invMatrixOutputs_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_1, _decoded_invMatrixOutputs_T_18) node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_23, _decoded_invMatrixOutputs_T_22) node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_21) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_40 = bits(decoded_plaOutput_1, 7, 0) node _decoded_T_41 = shl(UInt<4>(0hf), 4) node _decoded_T_42 = xor(UInt<8>(0hff), _decoded_T_41) node _decoded_T_43 = shr(_decoded_T_40, 4) node _decoded_T_44 = and(_decoded_T_43, _decoded_T_42) node _decoded_T_45 = bits(_decoded_T_40, 3, 0) node _decoded_T_46 = shl(_decoded_T_45, 4) node _decoded_T_47 = not(_decoded_T_42) node _decoded_T_48 = and(_decoded_T_46, _decoded_T_47) node _decoded_T_49 = or(_decoded_T_44, _decoded_T_48) node _decoded_T_50 = bits(_decoded_T_42, 5, 0) node _decoded_T_51 = shl(_decoded_T_50, 2) node _decoded_T_52 = xor(_decoded_T_42, _decoded_T_51) node _decoded_T_53 = shr(_decoded_T_49, 2) node _decoded_T_54 = and(_decoded_T_53, _decoded_T_52) node _decoded_T_55 = bits(_decoded_T_49, 5, 0) node _decoded_T_56 = shl(_decoded_T_55, 2) node _decoded_T_57 = not(_decoded_T_52) node _decoded_T_58 = and(_decoded_T_56, _decoded_T_57) node _decoded_T_59 = or(_decoded_T_54, _decoded_T_58) node _decoded_T_60 = bits(_decoded_T_52, 6, 0) node _decoded_T_61 = shl(_decoded_T_60, 1) node _decoded_T_62 = xor(_decoded_T_52, _decoded_T_61) node _decoded_T_63 = shr(_decoded_T_59, 1) node _decoded_T_64 = and(_decoded_T_63, _decoded_T_62) node _decoded_T_65 = bits(_decoded_T_59, 6, 0) node _decoded_T_66 = shl(_decoded_T_65, 1) node _decoded_T_67 = not(_decoded_T_62) node _decoded_T_68 = and(_decoded_T_66, _decoded_T_67) node _decoded_T_69 = or(_decoded_T_64, _decoded_T_68) node _decoded_T_70 = bits(decoded_plaOutput_1, 11, 8) node _decoded_T_71 = bits(_decoded_T_70, 1, 0) node _decoded_T_72 = bits(_decoded_T_71, 0, 0) node _decoded_T_73 = bits(_decoded_T_71, 1, 1) node _decoded_T_74 = cat(_decoded_T_72, _decoded_T_73) node _decoded_T_75 = bits(_decoded_T_70, 3, 2) node _decoded_T_76 = bits(_decoded_T_75, 0, 0) node _decoded_T_77 = bits(_decoded_T_75, 1, 1) node _decoded_T_78 = cat(_decoded_T_76, _decoded_T_77) node _decoded_T_79 = cat(_decoded_T_74, _decoded_T_78) node decoded_1 = cat(_decoded_T_69, _decoded_T_79) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_1_0_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`1`[0], _io_resp_1_vc_sel_1_0_T node _io_resp_1_vc_sel_1_1_T = bits(decoded_1, 4, 4) connect io.resp.`1`.vc_sel.`1`[1], _io_resp_1_vc_sel_1_1_T node _io_resp_1_vc_sel_1_2_T = bits(decoded_1, 5, 5) connect io.resp.`1`.vc_sel.`1`[2], _io_resp_1_vc_sel_1_2_T node _io_resp_1_vc_sel_2_0_T = bits(decoded_1, 6, 6) connect io.resp.`1`.vc_sel.`2`[0], _io_resp_1_vc_sel_2_0_T node _io_resp_1_vc_sel_2_1_T = bits(decoded_1, 7, 7) connect io.resp.`1`.vc_sel.`2`[1], _io_resp_1_vc_sel_2_1_T node _io_resp_1_vc_sel_2_2_T = bits(decoded_1, 8, 8) connect io.resp.`1`.vc_sel.`2`[2], _io_resp_1_vc_sel_2_2_T node _io_resp_1_vc_sel_3_0_T = bits(decoded_1, 9, 9) connect io.resp.`1`.vc_sel.`3`[0], _io_resp_1_vc_sel_3_0_T node _io_resp_1_vc_sel_3_1_T = bits(decoded_1, 10, 10) connect io.resp.`1`.vc_sel.`3`[1], _io_resp_1_vc_sel_3_1_T node _io_resp_1_vc_sel_3_2_T = bits(decoded_1, 11, 11) connect io.resp.`1`.vc_sel.`3`[2], _io_resp_1_vc_sel_3_2_T connect io.resp.`1`.vc_sel.`4`[0], UInt<1>(0h0) connect io.resp.`1`.vc_sel.`5`[0], UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h1) node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id) node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node) node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id) node _addr_T_2 = cat(addr_hi_2, addr_lo_2) node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2) wire decoded_plaInput_2 : UInt<17> node decoded_invInputs_2 = not(decoded_plaInput_2) wire decoded_plaOutput_2 : UInt<12> node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_plaInput_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_plaInput_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_plaInput_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(decoded_invInputs_2, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_11_10, decoded_andMatrixOutputs_andMatrixInput_12_6) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_13_4) node decoded_andMatrixOutputs_lo_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_10) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_4) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_4_10, decoded_andMatrixOutputs_andMatrixInput_5_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_6_10) node decoded_andMatrixOutputs_hi_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_2_12, decoded_andMatrixOutputs_andMatrixInput_3_10) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_6) node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_6_2_1 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_plaInput_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_plaInput_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_plaInput_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(decoded_invInputs_2, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_11_11, decoded_andMatrixOutputs_andMatrixInput_12_7) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_lo_lo_hi_11, decoded_andMatrixOutputs_andMatrixInput_13_5) node decoded_andMatrixOutputs_lo_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_9_11, decoded_andMatrixOutputs_andMatrixInput_10_11) node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_7_11, decoded_andMatrixOutputs_andMatrixInput_8_11) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_lo_hi_lo_5) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_4_11, decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_hi_lo_hi_11, decoded_andMatrixOutputs_andMatrixInput_6_11) node decoded_andMatrixOutputs_hi_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_2_13, decoded_andMatrixOutputs_andMatrixInput_3_11) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_hi_hi_lo_7) node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_5_2_1 = andr(_decoded_andMatrixOutputs_T_13) node decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_plaInput_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_plaInput_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_plaInput_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_plaInput_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(decoded_invInputs_2, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_11_12, decoded_andMatrixOutputs_andMatrixInput_12_8) node decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_andMatrixOutputs_lo_lo_hi_12, decoded_andMatrixOutputs_andMatrixInput_13_6) node decoded_andMatrixOutputs_lo_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_andMatrixOutputs_andMatrixInput_10_12) node decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_7_12, decoded_andMatrixOutputs_andMatrixInput_8_12) node decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_lo_hi_hi_12, decoded_andMatrixOutputs_lo_hi_lo_6) node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12) node decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_4_12, decoded_andMatrixOutputs_andMatrixInput_5_12) node decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_andMatrixOutputs_hi_lo_hi_12, decoded_andMatrixOutputs_andMatrixInput_6_12) node decoded_andMatrixOutputs_hi_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_2_14, decoded_andMatrixOutputs_andMatrixInput_3_12) node decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_hi_hi_lo_8) node decoded_andMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12) node _decoded_andMatrixOutputs_T_14 = cat(decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_12) node decoded_andMatrixOutputs_9_2_1 = andr(_decoded_andMatrixOutputs_T_14) node decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_plaInput_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_plaInput_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_plaInput_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_plaInput_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(decoded_invInputs_2, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_11_13, decoded_andMatrixOutputs_andMatrixInput_12_9) node decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_andMatrixOutputs_lo_lo_hi_13, decoded_andMatrixOutputs_andMatrixInput_13_7) node decoded_andMatrixOutputs_lo_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_andMatrixOutputs_andMatrixInput_10_13) node decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_7_13, decoded_andMatrixOutputs_andMatrixInput_8_13) node decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_lo_hi_hi_13, decoded_andMatrixOutputs_lo_hi_lo_7) node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13) node decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_4_13, decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_andMatrixOutputs_hi_lo_hi_13, decoded_andMatrixOutputs_andMatrixInput_6_13) node decoded_andMatrixOutputs_hi_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_2_15, decoded_andMatrixOutputs_andMatrixInput_3_13) node decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_hi_hi_lo_9) node decoded_andMatrixOutputs_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13) node _decoded_andMatrixOutputs_T_15 = cat(decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_13) node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_15) node decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_invInputs_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_plaInput_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_plaInput_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_plaInput_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(decoded_invInputs_2, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_11_14, decoded_andMatrixOutputs_andMatrixInput_12_10) node decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_andMatrixOutputs_lo_lo_hi_14, decoded_andMatrixOutputs_andMatrixInput_13_8) node decoded_andMatrixOutputs_lo_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_andMatrixOutputs_andMatrixInput_10_14) node decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_7_14, decoded_andMatrixOutputs_andMatrixInput_8_14) node decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_14, decoded_andMatrixOutputs_lo_hi_lo_8) node decoded_andMatrixOutputs_lo_14 = cat(decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14) node decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_4_14, decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_andMatrixOutputs_hi_lo_hi_14, decoded_andMatrixOutputs_andMatrixInput_6_14) node decoded_andMatrixOutputs_hi_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_2_16, decoded_andMatrixOutputs_andMatrixInput_3_14) node decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_14, decoded_andMatrixOutputs_hi_hi_lo_10) node decoded_andMatrixOutputs_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14) node _decoded_andMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_hi_16, decoded_andMatrixOutputs_lo_14) node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_16) node decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_invInputs_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_plaInput_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_plaInput_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_plaInput_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(decoded_invInputs_2, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_11_15, decoded_andMatrixOutputs_andMatrixInput_12_11) node decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_andMatrixOutputs_lo_lo_hi_15, decoded_andMatrixOutputs_andMatrixInput_13_9) node decoded_andMatrixOutputs_lo_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_andMatrixOutputs_andMatrixInput_10_15) node decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_7_15, decoded_andMatrixOutputs_andMatrixInput_8_15) node decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_andMatrixOutputs_lo_hi_hi_15, decoded_andMatrixOutputs_lo_hi_lo_9) node decoded_andMatrixOutputs_lo_15 = cat(decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15) node decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_4_15, decoded_andMatrixOutputs_andMatrixInput_5_15) node decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_andMatrixOutputs_hi_lo_hi_15, decoded_andMatrixOutputs_andMatrixInput_6_15) node decoded_andMatrixOutputs_hi_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_2_17, decoded_andMatrixOutputs_andMatrixInput_3_15) node decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_15, decoded_andMatrixOutputs_hi_hi_lo_11) node decoded_andMatrixOutputs_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15) node _decoded_andMatrixOutputs_T_17 = cat(decoded_andMatrixOutputs_hi_17, decoded_andMatrixOutputs_lo_15) node decoded_andMatrixOutputs_7_2_1 = andr(_decoded_andMatrixOutputs_T_17) node decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_plaInput_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_invInputs_2, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_andMatrixOutputs_andMatrixInput_10_16) node decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_andMatrixOutputs_lo_lo_hi_16, decoded_andMatrixOutputs_andMatrixInput_11_16) node decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_andMatrixOutputs_andMatrixInput_7_16) node decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_andMatrixOutputs_lo_hi_hi_16, decoded_andMatrixOutputs_andMatrixInput_8_16) node decoded_andMatrixOutputs_lo_16 = cat(decoded_andMatrixOutputs_lo_hi_16, decoded_andMatrixOutputs_lo_lo_16) node decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_andMatrixOutputs_andMatrixInput_4_16) node decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_andMatrixOutputs_hi_lo_hi_16, decoded_andMatrixOutputs_andMatrixInput_5_16) node decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_andMatrixOutputs_andMatrixInput_1_18) node decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_hi_16, decoded_andMatrixOutputs_andMatrixInput_2_18) node decoded_andMatrixOutputs_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_16, decoded_andMatrixOutputs_hi_lo_16) node _decoded_andMatrixOutputs_T_18 = cat(decoded_andMatrixOutputs_hi_18, decoded_andMatrixOutputs_lo_16) node decoded_andMatrixOutputs_1_2_2 = andr(_decoded_andMatrixOutputs_T_18) node decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_plaInput_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_invInputs_2, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_andMatrixOutputs_andMatrixInput_10_17) node decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_andMatrixOutputs_lo_lo_hi_17, decoded_andMatrixOutputs_andMatrixInput_11_17) node decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_andMatrixOutputs_andMatrixInput_7_17) node decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_andMatrixOutputs_lo_hi_hi_17, decoded_andMatrixOutputs_andMatrixInput_8_17) node decoded_andMatrixOutputs_lo_17 = cat(decoded_andMatrixOutputs_lo_hi_17, decoded_andMatrixOutputs_lo_lo_17) node decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_andMatrixOutputs_andMatrixInput_4_17) node decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_andMatrixOutputs_hi_lo_hi_17, decoded_andMatrixOutputs_andMatrixInput_5_17) node decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_andMatrixOutputs_andMatrixInput_1_19) node decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_hi_17, decoded_andMatrixOutputs_andMatrixInput_2_19) node decoded_andMatrixOutputs_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_17, decoded_andMatrixOutputs_hi_lo_17) node _decoded_andMatrixOutputs_T_19 = cat(decoded_andMatrixOutputs_hi_19, decoded_andMatrixOutputs_lo_17) node decoded_andMatrixOutputs_4_2_1 = andr(_decoded_andMatrixOutputs_T_19) node decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_plaInput_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_plaInput_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(decoded_plaInput_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(decoded_invInputs_2, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_11_18, decoded_andMatrixOutputs_andMatrixInput_12_12) node decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_andMatrixOutputs_lo_lo_hi_18, decoded_andMatrixOutputs_andMatrixInput_13_10) node decoded_andMatrixOutputs_lo_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_andMatrixOutputs_andMatrixInput_10_18) node decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_7_18, decoded_andMatrixOutputs_andMatrixInput_8_18) node decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_andMatrixOutputs_lo_hi_hi_18, decoded_andMatrixOutputs_lo_hi_lo_10) node decoded_andMatrixOutputs_lo_18 = cat(decoded_andMatrixOutputs_lo_hi_18, decoded_andMatrixOutputs_lo_lo_18) node decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_4_18, decoded_andMatrixOutputs_andMatrixInput_5_18) node decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_andMatrixOutputs_hi_lo_hi_18, decoded_andMatrixOutputs_andMatrixInput_6_18) node decoded_andMatrixOutputs_hi_hi_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_2_20, decoded_andMatrixOutputs_andMatrixInput_3_18) node decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_andMatrixOutputs_andMatrixInput_1_20) node decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_hi_18, decoded_andMatrixOutputs_hi_hi_lo_12) node decoded_andMatrixOutputs_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_18, decoded_andMatrixOutputs_hi_lo_18) node _decoded_andMatrixOutputs_T_20 = cat(decoded_andMatrixOutputs_hi_20, decoded_andMatrixOutputs_lo_18) node decoded_andMatrixOutputs_0_2_2 = andr(_decoded_andMatrixOutputs_T_20) node decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_plaInput_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_plaInput_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(decoded_plaInput_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_11 = bits(decoded_invInputs_2, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_11_19, decoded_andMatrixOutputs_andMatrixInput_12_13) node decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_andMatrixOutputs_lo_lo_hi_19, decoded_andMatrixOutputs_andMatrixInput_13_11) node decoded_andMatrixOutputs_lo_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_andMatrixOutputs_andMatrixInput_10_19) node decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_7_19, decoded_andMatrixOutputs_andMatrixInput_8_19) node decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_andMatrixOutputs_lo_hi_hi_19, decoded_andMatrixOutputs_lo_hi_lo_11) node decoded_andMatrixOutputs_lo_19 = cat(decoded_andMatrixOutputs_lo_hi_19, decoded_andMatrixOutputs_lo_lo_19) node decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_4_19, decoded_andMatrixOutputs_andMatrixInput_5_19) node decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_andMatrixOutputs_hi_lo_hi_19, decoded_andMatrixOutputs_andMatrixInput_6_19) node decoded_andMatrixOutputs_hi_hi_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_2_21, decoded_andMatrixOutputs_andMatrixInput_3_19) node decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_andMatrixOutputs_andMatrixInput_1_21) node decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_hi_19, decoded_andMatrixOutputs_hi_hi_lo_13) node decoded_andMatrixOutputs_hi_21 = cat(decoded_andMatrixOutputs_hi_hi_19, decoded_andMatrixOutputs_hi_lo_19) node _decoded_andMatrixOutputs_T_21 = cat(decoded_andMatrixOutputs_hi_21, decoded_andMatrixOutputs_lo_19) node decoded_andMatrixOutputs_8_2_1 = andr(_decoded_andMatrixOutputs_T_21) node _decoded_orMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_1_2_2, decoded_andMatrixOutputs_4_2_1) node _decoded_orMatrixOutputs_T_13 = orr(_decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_2_2_1, decoded_andMatrixOutputs_7_2_1) node decoded_orMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_6_2_1, decoded_andMatrixOutputs_5_2_1) node _decoded_orMatrixOutputs_T_14 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2) node _decoded_orMatrixOutputs_T_15 = orr(_decoded_orMatrixOutputs_T_14) node _decoded_orMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_8_2_1) node _decoded_orMatrixOutputs_T_17 = orr(_decoded_orMatrixOutputs_T_16) node _decoded_orMatrixOutputs_T_18 = cat(decoded_andMatrixOutputs_9_2_1, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_19 = orr(_decoded_orMatrixOutputs_T_18) node decoded_orMatrixOutputs_lo_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_2 = cat(decoded_orMatrixOutputs_lo_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_2 = cat(decoded_orMatrixOutputs_lo_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_3 = cat(decoded_orMatrixOutputs_lo_hi_2, decoded_orMatrixOutputs_lo_lo_2) node decoded_orMatrixOutputs_hi_lo_hi_2 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_15) node decoded_orMatrixOutputs_hi_lo_2 = cat(decoded_orMatrixOutputs_hi_lo_hi_2, _decoded_orMatrixOutputs_T_13) node decoded_orMatrixOutputs_hi_hi_hi_2 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_19) node decoded_orMatrixOutputs_hi_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_hi_2, _decoded_orMatrixOutputs_T_17) node decoded_orMatrixOutputs_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_2, decoded_orMatrixOutputs_hi_lo_2) node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_3) node _decoded_invMatrixOutputs_T_24 = bits(decoded_orMatrixOutputs_2, 0, 0) node _decoded_invMatrixOutputs_T_25 = bits(decoded_orMatrixOutputs_2, 1, 1) node _decoded_invMatrixOutputs_T_26 = bits(decoded_orMatrixOutputs_2, 2, 2) node _decoded_invMatrixOutputs_T_27 = bits(decoded_orMatrixOutputs_2, 3, 3) node _decoded_invMatrixOutputs_T_28 = bits(decoded_orMatrixOutputs_2, 4, 4) node _decoded_invMatrixOutputs_T_29 = bits(decoded_orMatrixOutputs_2, 5, 5) node _decoded_invMatrixOutputs_T_30 = bits(decoded_orMatrixOutputs_2, 6, 6) node _decoded_invMatrixOutputs_T_31 = bits(decoded_orMatrixOutputs_2, 7, 7) node _decoded_invMatrixOutputs_T_32 = bits(decoded_orMatrixOutputs_2, 8, 8) node _decoded_invMatrixOutputs_T_33 = bits(decoded_orMatrixOutputs_2, 9, 9) node _decoded_invMatrixOutputs_T_34 = bits(decoded_orMatrixOutputs_2, 10, 10) node _decoded_invMatrixOutputs_T_35 = bits(decoded_orMatrixOutputs_2, 11, 11) node decoded_invMatrixOutputs_lo_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_26, _decoded_invMatrixOutputs_T_25) node decoded_invMatrixOutputs_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_2, _decoded_invMatrixOutputs_T_24) node decoded_invMatrixOutputs_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_29, _decoded_invMatrixOutputs_T_28) node decoded_invMatrixOutputs_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_2, _decoded_invMatrixOutputs_T_27) node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2) node decoded_invMatrixOutputs_hi_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_32, _decoded_invMatrixOutputs_T_31) node decoded_invMatrixOutputs_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_2, _decoded_invMatrixOutputs_T_30) node decoded_invMatrixOutputs_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_35, _decoded_invMatrixOutputs_T_34) node decoded_invMatrixOutputs_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_2, _decoded_invMatrixOutputs_T_33) node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2) node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2) connect decoded_plaOutput_2, decoded_invMatrixOutputs_2 connect decoded_plaInput_2, addr_2 node _decoded_T_80 = bits(decoded_plaOutput_2, 7, 0) node _decoded_T_81 = shl(UInt<4>(0hf), 4) node _decoded_T_82 = xor(UInt<8>(0hff), _decoded_T_81) node _decoded_T_83 = shr(_decoded_T_80, 4) node _decoded_T_84 = and(_decoded_T_83, _decoded_T_82) node _decoded_T_85 = bits(_decoded_T_80, 3, 0) node _decoded_T_86 = shl(_decoded_T_85, 4) node _decoded_T_87 = not(_decoded_T_82) node _decoded_T_88 = and(_decoded_T_86, _decoded_T_87) node _decoded_T_89 = or(_decoded_T_84, _decoded_T_88) node _decoded_T_90 = bits(_decoded_T_82, 5, 0) node _decoded_T_91 = shl(_decoded_T_90, 2) node _decoded_T_92 = xor(_decoded_T_82, _decoded_T_91) node _decoded_T_93 = shr(_decoded_T_89, 2) node _decoded_T_94 = and(_decoded_T_93, _decoded_T_92) node _decoded_T_95 = bits(_decoded_T_89, 5, 0) node _decoded_T_96 = shl(_decoded_T_95, 2) node _decoded_T_97 = not(_decoded_T_92) node _decoded_T_98 = and(_decoded_T_96, _decoded_T_97) node _decoded_T_99 = or(_decoded_T_94, _decoded_T_98) node _decoded_T_100 = bits(_decoded_T_92, 6, 0) node _decoded_T_101 = shl(_decoded_T_100, 1) node _decoded_T_102 = xor(_decoded_T_92, _decoded_T_101) node _decoded_T_103 = shr(_decoded_T_99, 1) node _decoded_T_104 = and(_decoded_T_103, _decoded_T_102) node _decoded_T_105 = bits(_decoded_T_99, 6, 0) node _decoded_T_106 = shl(_decoded_T_105, 1) node _decoded_T_107 = not(_decoded_T_102) node _decoded_T_108 = and(_decoded_T_106, _decoded_T_107) node _decoded_T_109 = or(_decoded_T_104, _decoded_T_108) node _decoded_T_110 = bits(decoded_plaOutput_2, 11, 8) node _decoded_T_111 = bits(_decoded_T_110, 1, 0) node _decoded_T_112 = bits(_decoded_T_111, 0, 0) node _decoded_T_113 = bits(_decoded_T_111, 1, 1) node _decoded_T_114 = cat(_decoded_T_112, _decoded_T_113) node _decoded_T_115 = bits(_decoded_T_110, 3, 2) node _decoded_T_116 = bits(_decoded_T_115, 0, 0) node _decoded_T_117 = bits(_decoded_T_115, 1, 1) node _decoded_T_118 = cat(_decoded_T_116, _decoded_T_117) node _decoded_T_119 = cat(_decoded_T_114, _decoded_T_118) node decoded_2 = cat(_decoded_T_109, _decoded_T_119) node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0) connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1) connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T node _io_resp_2_vc_sel_0_2_T = bits(decoded_2, 2, 2) connect io.resp.`2`.vc_sel.`0`[2], _io_resp_2_vc_sel_0_2_T node _io_resp_2_vc_sel_1_0_T = bits(decoded_2, 3, 3) connect io.resp.`2`.vc_sel.`1`[0], _io_resp_2_vc_sel_1_0_T node _io_resp_2_vc_sel_1_1_T = bits(decoded_2, 4, 4) connect io.resp.`2`.vc_sel.`1`[1], _io_resp_2_vc_sel_1_1_T node _io_resp_2_vc_sel_1_2_T = bits(decoded_2, 5, 5) connect io.resp.`2`.vc_sel.`1`[2], _io_resp_2_vc_sel_1_2_T node _io_resp_2_vc_sel_2_0_T = bits(decoded_2, 6, 6) connect io.resp.`2`.vc_sel.`2`[0], _io_resp_2_vc_sel_2_0_T node _io_resp_2_vc_sel_2_1_T = bits(decoded_2, 7, 7) connect io.resp.`2`.vc_sel.`2`[1], _io_resp_2_vc_sel_2_1_T node _io_resp_2_vc_sel_2_2_T = bits(decoded_2, 8, 8) connect io.resp.`2`.vc_sel.`2`[2], _io_resp_2_vc_sel_2_2_T node _io_resp_2_vc_sel_3_0_T = bits(decoded_2, 9, 9) connect io.resp.`2`.vc_sel.`3`[0], _io_resp_2_vc_sel_3_0_T node _io_resp_2_vc_sel_3_1_T = bits(decoded_2, 10, 10) connect io.resp.`2`.vc_sel.`3`[1], _io_resp_2_vc_sel_3_1_T node _io_resp_2_vc_sel_3_2_T = bits(decoded_2, 11, 11) connect io.resp.`2`.vc_sel.`3`[2], _io_resp_2_vc_sel_3_2_T connect io.resp.`2`.vc_sel.`4`[0], UInt<1>(0h0) connect io.resp.`2`.vc_sel.`5`[0], UInt<1>(0h0) connect io.req.`3`.ready, UInt<1>(0h1) node addr_lo_3 = cat(io.req.`3`.bits.flow.egress_node, io.req.`3`.bits.flow.egress_node_id) node addr_hi_hi_3 = cat(io.req.`3`.bits.flow.vnet_id, io.req.`3`.bits.flow.ingress_node) node addr_hi_3 = cat(addr_hi_hi_3, io.req.`3`.bits.flow.ingress_node_id) node _addr_T_3 = cat(addr_hi_3, addr_lo_3) node addr_3 = cat(io.req.`3`.bits.src_virt_id, _addr_T_3) wire decoded_plaInput_3 : UInt<17> node decoded_invInputs_3 = not(decoded_plaInput_3) wire decoded_plaOutput_3 : UInt<12> node decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_plaInput_3, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_invInputs_3, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_invInputs_3, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_invInputs_3, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_plaInput_3, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_invInputs_3, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_invInputs_3, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_plaInput_3, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_plaInput_3, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_plaInput_3, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_invInputs_3, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_invInputs_3, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_andMatrixOutputs_andMatrixInput_10_20) node decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_andMatrixOutputs_lo_lo_hi_20, decoded_andMatrixOutputs_andMatrixInput_11_20) node decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_6_20, decoded_andMatrixOutputs_andMatrixInput_7_20) node decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_andMatrixOutputs_lo_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_8_20) node decoded_andMatrixOutputs_lo_20 = cat(decoded_andMatrixOutputs_lo_hi_20, decoded_andMatrixOutputs_lo_lo_20) node decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_andMatrixOutputs_andMatrixInput_4_20) node decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_andMatrixOutputs_hi_lo_hi_20, decoded_andMatrixOutputs_andMatrixInput_5_20) node decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_andMatrixOutputs_andMatrixInput_1_22) node decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_2_22) node decoded_andMatrixOutputs_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_20, decoded_andMatrixOutputs_hi_lo_20) node _decoded_andMatrixOutputs_T_22 = cat(decoded_andMatrixOutputs_hi_22, decoded_andMatrixOutputs_lo_20) node decoded_andMatrixOutputs_0_2_3 = andr(_decoded_andMatrixOutputs_T_22) node decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_plaInput_3, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_invInputs_3, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_invInputs_3, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_invInputs_3, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_plaInput_3, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_invInputs_3, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_invInputs_3, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_plaInput_3, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_plaInput_3, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_plaInput_3, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoded_invInputs_3, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoded_invInputs_3, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_andMatrixOutputs_andMatrixInput_10_21) node decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_andMatrixOutputs_lo_lo_hi_21, decoded_andMatrixOutputs_andMatrixInput_11_21) node decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_andMatrixOutputs_andMatrixInput_7_21) node decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_andMatrixOutputs_lo_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_8_21) node decoded_andMatrixOutputs_lo_21 = cat(decoded_andMatrixOutputs_lo_hi_21, decoded_andMatrixOutputs_lo_lo_21) node decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_andMatrixOutputs_andMatrixInput_4_21) node decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_andMatrixOutputs_hi_lo_hi_21, decoded_andMatrixOutputs_andMatrixInput_5_21) node decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_andMatrixOutputs_andMatrixInput_1_23) node decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_andMatrixOutputs_hi_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_2_23) node decoded_andMatrixOutputs_hi_23 = cat(decoded_andMatrixOutputs_hi_hi_21, decoded_andMatrixOutputs_hi_lo_21) node _decoded_andMatrixOutputs_T_23 = cat(decoded_andMatrixOutputs_hi_23, decoded_andMatrixOutputs_lo_21) node decoded_andMatrixOutputs_1_2_3 = andr(_decoded_andMatrixOutputs_T_23) node decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_invInputs_3, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_invInputs_3, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_invInputs_3, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_invInputs_3, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_invInputs_3, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_invInputs_3, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_invInputs_3, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_plaInput_3, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_plaInput_3, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_invInputs_3, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoded_plaInput_3, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoded_invInputs_3, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_andMatrixOutputs_andMatrixInput_10_22) node decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_andMatrixOutputs_lo_lo_hi_22, decoded_andMatrixOutputs_andMatrixInput_11_22) node decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_andMatrixOutputs_andMatrixInput_7_22) node decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_andMatrixOutputs_lo_hi_hi_22, decoded_andMatrixOutputs_andMatrixInput_8_22) node decoded_andMatrixOutputs_lo_22 = cat(decoded_andMatrixOutputs_lo_hi_22, decoded_andMatrixOutputs_lo_lo_22) node decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_andMatrixOutputs_andMatrixInput_4_22) node decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_andMatrixOutputs_hi_lo_hi_22, decoded_andMatrixOutputs_andMatrixInput_5_22) node decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_andMatrixOutputs_andMatrixInput_1_24) node decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_hi_22, decoded_andMatrixOutputs_andMatrixInput_2_24) node decoded_andMatrixOutputs_hi_24 = cat(decoded_andMatrixOutputs_hi_hi_22, decoded_andMatrixOutputs_hi_lo_22) node _decoded_andMatrixOutputs_T_24 = cat(decoded_andMatrixOutputs_hi_24, decoded_andMatrixOutputs_lo_22) node decoded_andMatrixOutputs_2_2_2 = andr(_decoded_andMatrixOutputs_T_24) node decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_invInputs_3, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_invInputs_3, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_invInputs_3, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_invInputs_3, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_invInputs_3, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_invInputs_3, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_invInputs_3, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_plaInput_3, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_plaInput_3, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_invInputs_3, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoded_plaInput_3, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoded_invInputs_3, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_andMatrixOutputs_andMatrixInput_10_23) node decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_andMatrixOutputs_lo_lo_hi_23, decoded_andMatrixOutputs_andMatrixInput_11_23) node decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_andMatrixOutputs_andMatrixInput_7_23) node decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_andMatrixOutputs_lo_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_8_23) node decoded_andMatrixOutputs_lo_23 = cat(decoded_andMatrixOutputs_lo_hi_23, decoded_andMatrixOutputs_lo_lo_23) node decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_andMatrixOutputs_andMatrixInput_4_23) node decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_andMatrixOutputs_hi_lo_hi_23, decoded_andMatrixOutputs_andMatrixInput_5_23) node decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_andMatrixOutputs_andMatrixInput_1_25) node decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_andMatrixOutputs_hi_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_2_25) node decoded_andMatrixOutputs_hi_25 = cat(decoded_andMatrixOutputs_hi_hi_23, decoded_andMatrixOutputs_hi_lo_23) node _decoded_andMatrixOutputs_T_25 = cat(decoded_andMatrixOutputs_hi_25, decoded_andMatrixOutputs_lo_23) node decoded_andMatrixOutputs_3_2_2 = andr(_decoded_andMatrixOutputs_T_25) node _decoded_orMatrixOutputs_T_20 = cat(decoded_andMatrixOutputs_2_2_2, decoded_andMatrixOutputs_3_2_2) node _decoded_orMatrixOutputs_T_21 = orr(_decoded_orMatrixOutputs_T_20) node _decoded_orMatrixOutputs_T_22 = cat(decoded_andMatrixOutputs_0_2_3, decoded_andMatrixOutputs_1_2_3) node _decoded_orMatrixOutputs_T_23 = orr(_decoded_orMatrixOutputs_T_22) node decoded_orMatrixOutputs_lo_lo_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_3 = cat(decoded_orMatrixOutputs_lo_lo_hi_3, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_3 = cat(decoded_orMatrixOutputs_lo_hi_hi_3, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_4 = cat(decoded_orMatrixOutputs_lo_hi_3, decoded_orMatrixOutputs_lo_lo_3) node decoded_orMatrixOutputs_hi_lo_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_3 = cat(decoded_orMatrixOutputs_hi_lo_hi_3, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_3 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_23) node decoded_orMatrixOutputs_hi_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_hi_3, _decoded_orMatrixOutputs_T_21) node decoded_orMatrixOutputs_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_3, decoded_orMatrixOutputs_hi_lo_3) node decoded_orMatrixOutputs_3 = cat(decoded_orMatrixOutputs_hi_4, decoded_orMatrixOutputs_lo_4) node _decoded_invMatrixOutputs_T_36 = bits(decoded_orMatrixOutputs_3, 0, 0) node _decoded_invMatrixOutputs_T_37 = bits(decoded_orMatrixOutputs_3, 1, 1) node _decoded_invMatrixOutputs_T_38 = bits(decoded_orMatrixOutputs_3, 2, 2) node _decoded_invMatrixOutputs_T_39 = bits(decoded_orMatrixOutputs_3, 3, 3) node _decoded_invMatrixOutputs_T_40 = bits(decoded_orMatrixOutputs_3, 4, 4) node _decoded_invMatrixOutputs_T_41 = bits(decoded_orMatrixOutputs_3, 5, 5) node _decoded_invMatrixOutputs_T_42 = bits(decoded_orMatrixOutputs_3, 6, 6) node _decoded_invMatrixOutputs_T_43 = bits(decoded_orMatrixOutputs_3, 7, 7) node _decoded_invMatrixOutputs_T_44 = bits(decoded_orMatrixOutputs_3, 8, 8) node _decoded_invMatrixOutputs_T_45 = bits(decoded_orMatrixOutputs_3, 9, 9) node _decoded_invMatrixOutputs_T_46 = bits(decoded_orMatrixOutputs_3, 10, 10) node _decoded_invMatrixOutputs_T_47 = bits(decoded_orMatrixOutputs_3, 11, 11) node decoded_invMatrixOutputs_lo_lo_hi_3 = cat(_decoded_invMatrixOutputs_T_38, _decoded_invMatrixOutputs_T_37) node decoded_invMatrixOutputs_lo_lo_3 = cat(decoded_invMatrixOutputs_lo_lo_hi_3, _decoded_invMatrixOutputs_T_36) node decoded_invMatrixOutputs_lo_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_41, _decoded_invMatrixOutputs_T_40) node decoded_invMatrixOutputs_lo_hi_3 = cat(decoded_invMatrixOutputs_lo_hi_hi_3, _decoded_invMatrixOutputs_T_39) node decoded_invMatrixOutputs_lo_3 = cat(decoded_invMatrixOutputs_lo_hi_3, decoded_invMatrixOutputs_lo_lo_3) node decoded_invMatrixOutputs_hi_lo_hi_3 = cat(_decoded_invMatrixOutputs_T_44, _decoded_invMatrixOutputs_T_43) node decoded_invMatrixOutputs_hi_lo_3 = cat(decoded_invMatrixOutputs_hi_lo_hi_3, _decoded_invMatrixOutputs_T_42) node decoded_invMatrixOutputs_hi_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_47, _decoded_invMatrixOutputs_T_46) node decoded_invMatrixOutputs_hi_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_hi_3, _decoded_invMatrixOutputs_T_45) node decoded_invMatrixOutputs_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_3, decoded_invMatrixOutputs_hi_lo_3) node decoded_invMatrixOutputs_3 = cat(decoded_invMatrixOutputs_hi_3, decoded_invMatrixOutputs_lo_3) connect decoded_plaOutput_3, decoded_invMatrixOutputs_3 connect decoded_plaInput_3, addr_3 node _decoded_T_120 = bits(decoded_plaOutput_3, 7, 0) node _decoded_T_121 = shl(UInt<4>(0hf), 4) node _decoded_T_122 = xor(UInt<8>(0hff), _decoded_T_121) node _decoded_T_123 = shr(_decoded_T_120, 4) node _decoded_T_124 = and(_decoded_T_123, _decoded_T_122) node _decoded_T_125 = bits(_decoded_T_120, 3, 0) node _decoded_T_126 = shl(_decoded_T_125, 4) node _decoded_T_127 = not(_decoded_T_122) node _decoded_T_128 = and(_decoded_T_126, _decoded_T_127) node _decoded_T_129 = or(_decoded_T_124, _decoded_T_128) node _decoded_T_130 = bits(_decoded_T_122, 5, 0) node _decoded_T_131 = shl(_decoded_T_130, 2) node _decoded_T_132 = xor(_decoded_T_122, _decoded_T_131) node _decoded_T_133 = shr(_decoded_T_129, 2) node _decoded_T_134 = and(_decoded_T_133, _decoded_T_132) node _decoded_T_135 = bits(_decoded_T_129, 5, 0) node _decoded_T_136 = shl(_decoded_T_135, 2) node _decoded_T_137 = not(_decoded_T_132) node _decoded_T_138 = and(_decoded_T_136, _decoded_T_137) node _decoded_T_139 = or(_decoded_T_134, _decoded_T_138) node _decoded_T_140 = bits(_decoded_T_132, 6, 0) node _decoded_T_141 = shl(_decoded_T_140, 1) node _decoded_T_142 = xor(_decoded_T_132, _decoded_T_141) node _decoded_T_143 = shr(_decoded_T_139, 1) node _decoded_T_144 = and(_decoded_T_143, _decoded_T_142) node _decoded_T_145 = bits(_decoded_T_139, 6, 0) node _decoded_T_146 = shl(_decoded_T_145, 1) node _decoded_T_147 = not(_decoded_T_142) node _decoded_T_148 = and(_decoded_T_146, _decoded_T_147) node _decoded_T_149 = or(_decoded_T_144, _decoded_T_148) node _decoded_T_150 = bits(decoded_plaOutput_3, 11, 8) node _decoded_T_151 = bits(_decoded_T_150, 1, 0) node _decoded_T_152 = bits(_decoded_T_151, 0, 0) node _decoded_T_153 = bits(_decoded_T_151, 1, 1) node _decoded_T_154 = cat(_decoded_T_152, _decoded_T_153) node _decoded_T_155 = bits(_decoded_T_150, 3, 2) node _decoded_T_156 = bits(_decoded_T_155, 0, 0) node _decoded_T_157 = bits(_decoded_T_155, 1, 1) node _decoded_T_158 = cat(_decoded_T_156, _decoded_T_157) node _decoded_T_159 = cat(_decoded_T_154, _decoded_T_158) node decoded_3 = cat(_decoded_T_149, _decoded_T_159) node _io_resp_3_vc_sel_0_0_T = bits(decoded_3, 0, 0) connect io.resp.`3`.vc_sel.`0`[0], _io_resp_3_vc_sel_0_0_T node _io_resp_3_vc_sel_0_1_T = bits(decoded_3, 1, 1) connect io.resp.`3`.vc_sel.`0`[1], _io_resp_3_vc_sel_0_1_T node _io_resp_3_vc_sel_0_2_T = bits(decoded_3, 2, 2) connect io.resp.`3`.vc_sel.`0`[2], _io_resp_3_vc_sel_0_2_T node _io_resp_3_vc_sel_1_0_T = bits(decoded_3, 3, 3) connect io.resp.`3`.vc_sel.`1`[0], _io_resp_3_vc_sel_1_0_T node _io_resp_3_vc_sel_1_1_T = bits(decoded_3, 4, 4) connect io.resp.`3`.vc_sel.`1`[1], _io_resp_3_vc_sel_1_1_T node _io_resp_3_vc_sel_1_2_T = bits(decoded_3, 5, 5) connect io.resp.`3`.vc_sel.`1`[2], _io_resp_3_vc_sel_1_2_T node _io_resp_3_vc_sel_2_0_T = bits(decoded_3, 6, 6) connect io.resp.`3`.vc_sel.`2`[0], _io_resp_3_vc_sel_2_0_T node _io_resp_3_vc_sel_2_1_T = bits(decoded_3, 7, 7) connect io.resp.`3`.vc_sel.`2`[1], _io_resp_3_vc_sel_2_1_T node _io_resp_3_vc_sel_2_2_T = bits(decoded_3, 8, 8) connect io.resp.`3`.vc_sel.`2`[2], _io_resp_3_vc_sel_2_2_T node _io_resp_3_vc_sel_3_0_T = bits(decoded_3, 9, 9) connect io.resp.`3`.vc_sel.`3`[0], _io_resp_3_vc_sel_3_0_T node _io_resp_3_vc_sel_3_1_T = bits(decoded_3, 10, 10) connect io.resp.`3`.vc_sel.`3`[1], _io_resp_3_vc_sel_3_1_T node _io_resp_3_vc_sel_3_2_T = bits(decoded_3, 11, 11) connect io.resp.`3`.vc_sel.`3`[2], _io_resp_3_vc_sel_3_2_T connect io.resp.`3`.vc_sel.`4`[0], UInt<1>(0h0) connect io.resp.`3`.vc_sel.`5`[0], UInt<1>(0h0) connect io.req.`4`.ready, UInt<1>(0h1) node addr_lo_4 = cat(io.req.`4`.bits.flow.egress_node, io.req.`4`.bits.flow.egress_node_id) node addr_hi_hi_4 = cat(io.req.`4`.bits.flow.vnet_id, io.req.`4`.bits.flow.ingress_node) node addr_hi_4 = cat(addr_hi_hi_4, io.req.`4`.bits.flow.ingress_node_id) node _addr_T_4 = cat(addr_hi_4, addr_lo_4) node addr_4 = cat(io.req.`4`.bits.src_virt_id, _addr_T_4) wire decoded_plaInput_4 : UInt<17> node decoded_invInputs_4 = not(decoded_plaInput_4) wire decoded_plaOutput_4 : UInt<12> node decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_invInputs_4, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_invInputs_4, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_invInputs_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_invInputs_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoded_invInputs_4, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(decoded_invInputs_4, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_12 = bits(decoded_invInputs_4, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_11_24, decoded_andMatrixOutputs_andMatrixInput_12_14) node decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_andMatrixOutputs_lo_lo_hi_24, decoded_andMatrixOutputs_andMatrixInput_13_12) node decoded_andMatrixOutputs_lo_hi_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_andMatrixOutputs_andMatrixInput_10_24) node decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_7_24, decoded_andMatrixOutputs_andMatrixInput_8_24) node decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_andMatrixOutputs_lo_hi_hi_24, decoded_andMatrixOutputs_lo_hi_lo_12) node decoded_andMatrixOutputs_lo_24 = cat(decoded_andMatrixOutputs_lo_hi_24, decoded_andMatrixOutputs_lo_lo_24) node decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_4_24, decoded_andMatrixOutputs_andMatrixInput_5_24) node decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_andMatrixOutputs_hi_lo_hi_24, decoded_andMatrixOutputs_andMatrixInput_6_24) node decoded_andMatrixOutputs_hi_hi_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_2_26, decoded_andMatrixOutputs_andMatrixInput_3_24) node decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_andMatrixOutputs_andMatrixInput_1_26) node decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_andMatrixOutputs_hi_hi_hi_24, decoded_andMatrixOutputs_hi_hi_lo_14) node decoded_andMatrixOutputs_hi_26 = cat(decoded_andMatrixOutputs_hi_hi_24, decoded_andMatrixOutputs_hi_lo_24) node _decoded_andMatrixOutputs_T_26 = cat(decoded_andMatrixOutputs_hi_26, decoded_andMatrixOutputs_lo_24) node decoded_andMatrixOutputs_4_2_2 = andr(_decoded_andMatrixOutputs_T_26) node decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_invInputs_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_invInputs_4, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_invInputs_4, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_invInputs_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoded_invInputs_4, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(decoded_invInputs_4, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_13 = bits(decoded_invInputs_4, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_11_25, decoded_andMatrixOutputs_andMatrixInput_12_15) node decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_andMatrixOutputs_lo_lo_hi_25, decoded_andMatrixOutputs_andMatrixInput_13_13) node decoded_andMatrixOutputs_lo_hi_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_andMatrixOutputs_andMatrixInput_10_25) node decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_7_25, decoded_andMatrixOutputs_andMatrixInput_8_25) node decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_andMatrixOutputs_lo_hi_hi_25, decoded_andMatrixOutputs_lo_hi_lo_13) node decoded_andMatrixOutputs_lo_25 = cat(decoded_andMatrixOutputs_lo_hi_25, decoded_andMatrixOutputs_lo_lo_25) node decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_4_25, decoded_andMatrixOutputs_andMatrixInput_5_25) node decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_andMatrixOutputs_hi_lo_hi_25, decoded_andMatrixOutputs_andMatrixInput_6_25) node decoded_andMatrixOutputs_hi_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_2_27, decoded_andMatrixOutputs_andMatrixInput_3_25) node decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_andMatrixOutputs_andMatrixInput_1_27) node decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_andMatrixOutputs_hi_hi_hi_25, decoded_andMatrixOutputs_hi_hi_lo_15) node decoded_andMatrixOutputs_hi_27 = cat(decoded_andMatrixOutputs_hi_hi_25, decoded_andMatrixOutputs_hi_lo_25) node _decoded_andMatrixOutputs_T_27 = cat(decoded_andMatrixOutputs_hi_27, decoded_andMatrixOutputs_lo_25) node decoded_andMatrixOutputs_2_2_3 = andr(_decoded_andMatrixOutputs_T_27) node decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_invInputs_4, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_plaInput_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_invInputs_4, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_invInputs_4, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_invInputs_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(decoded_invInputs_4, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_14 = bits(decoded_invInputs_4, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(decoded_invInputs_4, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_12_16, decoded_andMatrixOutputs_andMatrixInput_13_14) node decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_andMatrixOutputs_lo_lo_hi_26, decoded_andMatrixOutputs_andMatrixInput_14_4) node decoded_andMatrixOutputs_lo_hi_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_10_26, decoded_andMatrixOutputs_andMatrixInput_11_26) node decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_8_26, decoded_andMatrixOutputs_andMatrixInput_9_26) node decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_andMatrixOutputs_lo_hi_hi_26, decoded_andMatrixOutputs_lo_hi_lo_14) node decoded_andMatrixOutputs_lo_26 = cat(decoded_andMatrixOutputs_lo_hi_26, decoded_andMatrixOutputs_lo_lo_26) node decoded_andMatrixOutputs_hi_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_andMatrixOutputs_andMatrixInput_7_26) node decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_4_26, decoded_andMatrixOutputs_andMatrixInput_5_26) node decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_andMatrixOutputs_hi_lo_hi_26, decoded_andMatrixOutputs_hi_lo_lo_4) node decoded_andMatrixOutputs_hi_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_2_28, decoded_andMatrixOutputs_andMatrixInput_3_26) node decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_andMatrixOutputs_andMatrixInput_1_28) node decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_andMatrixOutputs_hi_hi_hi_26, decoded_andMatrixOutputs_hi_hi_lo_16) node decoded_andMatrixOutputs_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_26, decoded_andMatrixOutputs_hi_lo_26) node _decoded_andMatrixOutputs_T_28 = cat(decoded_andMatrixOutputs_hi_28, decoded_andMatrixOutputs_lo_26) node decoded_andMatrixOutputs_3_2_3 = andr(_decoded_andMatrixOutputs_T_28) node decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_invInputs_4, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_invInputs_4, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_plaInput_4, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_plaInput_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_invInputs_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(decoded_invInputs_4, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_15 = bits(decoded_invInputs_4, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(decoded_invInputs_4, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_12_17, decoded_andMatrixOutputs_andMatrixInput_13_15) node decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_andMatrixOutputs_lo_lo_hi_27, decoded_andMatrixOutputs_andMatrixInput_14_5) node decoded_andMatrixOutputs_lo_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_10_27, decoded_andMatrixOutputs_andMatrixInput_11_27) node decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_8_27, decoded_andMatrixOutputs_andMatrixInput_9_27) node decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_andMatrixOutputs_lo_hi_hi_27, decoded_andMatrixOutputs_lo_hi_lo_15) node decoded_andMatrixOutputs_lo_27 = cat(decoded_andMatrixOutputs_lo_hi_27, decoded_andMatrixOutputs_lo_lo_27) node decoded_andMatrixOutputs_hi_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_andMatrixOutputs_andMatrixInput_7_27) node decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_4_27, decoded_andMatrixOutputs_andMatrixInput_5_27) node decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_andMatrixOutputs_hi_lo_hi_27, decoded_andMatrixOutputs_hi_lo_lo_5) node decoded_andMatrixOutputs_hi_hi_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_2_29, decoded_andMatrixOutputs_andMatrixInput_3_27) node decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_andMatrixOutputs_andMatrixInput_1_29) node decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_andMatrixOutputs_hi_hi_hi_27, decoded_andMatrixOutputs_hi_hi_lo_17) node decoded_andMatrixOutputs_hi_29 = cat(decoded_andMatrixOutputs_hi_hi_27, decoded_andMatrixOutputs_hi_lo_27) node _decoded_andMatrixOutputs_T_29 = cat(decoded_andMatrixOutputs_hi_29, decoded_andMatrixOutputs_lo_27) node decoded_andMatrixOutputs_0_2_4 = andr(_decoded_andMatrixOutputs_T_29) node decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_invInputs_4, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_plaInput_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_plaInput_4, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_plaInput_4, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_invInputs_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(decoded_invInputs_4, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_16 = bits(decoded_invInputs_4, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(decoded_invInputs_4, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_12_18, decoded_andMatrixOutputs_andMatrixInput_13_16) node decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_andMatrixOutputs_lo_lo_hi_28, decoded_andMatrixOutputs_andMatrixInput_14_6) node decoded_andMatrixOutputs_lo_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_10_28, decoded_andMatrixOutputs_andMatrixInput_11_28) node decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_8_28, decoded_andMatrixOutputs_andMatrixInput_9_28) node decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_andMatrixOutputs_lo_hi_hi_28, decoded_andMatrixOutputs_lo_hi_lo_16) node decoded_andMatrixOutputs_lo_28 = cat(decoded_andMatrixOutputs_lo_hi_28, decoded_andMatrixOutputs_lo_lo_28) node decoded_andMatrixOutputs_hi_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_andMatrixOutputs_andMatrixInput_7_28) node decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_4_28, decoded_andMatrixOutputs_andMatrixInput_5_28) node decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_andMatrixOutputs_hi_lo_hi_28, decoded_andMatrixOutputs_hi_lo_lo_6) node decoded_andMatrixOutputs_hi_hi_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_2_30, decoded_andMatrixOutputs_andMatrixInput_3_28) node decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_andMatrixOutputs_andMatrixInput_1_30) node decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_hi_28, decoded_andMatrixOutputs_hi_hi_lo_18) node decoded_andMatrixOutputs_hi_30 = cat(decoded_andMatrixOutputs_hi_hi_28, decoded_andMatrixOutputs_hi_lo_28) node _decoded_andMatrixOutputs_T_30 = cat(decoded_andMatrixOutputs_hi_30, decoded_andMatrixOutputs_lo_28) node decoded_andMatrixOutputs_1_2_4 = andr(_decoded_andMatrixOutputs_T_30) node _decoded_orMatrixOutputs_T_24 = orr(decoded_andMatrixOutputs_1_2_4) node _decoded_orMatrixOutputs_T_25 = orr(decoded_andMatrixOutputs_0_2_4) node _decoded_orMatrixOutputs_T_26 = cat(decoded_andMatrixOutputs_4_2_2, decoded_andMatrixOutputs_2_2_3) node _decoded_orMatrixOutputs_T_27 = orr(_decoded_orMatrixOutputs_T_26) node _decoded_orMatrixOutputs_T_28 = orr(decoded_andMatrixOutputs_3_2_3) node decoded_orMatrixOutputs_lo_lo_hi_4 = cat(_decoded_orMatrixOutputs_T_24, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_4 = cat(decoded_orMatrixOutputs_lo_lo_hi_4, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_4 = cat(_decoded_orMatrixOutputs_T_25, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_4 = cat(decoded_orMatrixOutputs_lo_hi_hi_4, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_5 = cat(decoded_orMatrixOutputs_lo_hi_4, decoded_orMatrixOutputs_lo_lo_4) node decoded_orMatrixOutputs_hi_lo_hi_4 = cat(_decoded_orMatrixOutputs_T_27, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_4 = cat(decoded_orMatrixOutputs_hi_lo_hi_4, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_4 = cat(_decoded_orMatrixOutputs_T_28, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_hi_4, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_5 = cat(decoded_orMatrixOutputs_hi_hi_4, decoded_orMatrixOutputs_hi_lo_4) node decoded_orMatrixOutputs_4 = cat(decoded_orMatrixOutputs_hi_5, decoded_orMatrixOutputs_lo_5) node _decoded_invMatrixOutputs_T_48 = bits(decoded_orMatrixOutputs_4, 0, 0) node _decoded_invMatrixOutputs_T_49 = bits(decoded_orMatrixOutputs_4, 1, 1) node _decoded_invMatrixOutputs_T_50 = bits(decoded_orMatrixOutputs_4, 2, 2) node _decoded_invMatrixOutputs_T_51 = bits(decoded_orMatrixOutputs_4, 3, 3) node _decoded_invMatrixOutputs_T_52 = bits(decoded_orMatrixOutputs_4, 4, 4) node _decoded_invMatrixOutputs_T_53 = bits(decoded_orMatrixOutputs_4, 5, 5) node _decoded_invMatrixOutputs_T_54 = bits(decoded_orMatrixOutputs_4, 6, 6) node _decoded_invMatrixOutputs_T_55 = bits(decoded_orMatrixOutputs_4, 7, 7) node _decoded_invMatrixOutputs_T_56 = bits(decoded_orMatrixOutputs_4, 8, 8) node _decoded_invMatrixOutputs_T_57 = bits(decoded_orMatrixOutputs_4, 9, 9) node _decoded_invMatrixOutputs_T_58 = bits(decoded_orMatrixOutputs_4, 10, 10) node _decoded_invMatrixOutputs_T_59 = bits(decoded_orMatrixOutputs_4, 11, 11) node decoded_invMatrixOutputs_lo_lo_hi_4 = cat(_decoded_invMatrixOutputs_T_50, _decoded_invMatrixOutputs_T_49) node decoded_invMatrixOutputs_lo_lo_4 = cat(decoded_invMatrixOutputs_lo_lo_hi_4, _decoded_invMatrixOutputs_T_48) node decoded_invMatrixOutputs_lo_hi_hi_4 = cat(_decoded_invMatrixOutputs_T_53, _decoded_invMatrixOutputs_T_52) node decoded_invMatrixOutputs_lo_hi_4 = cat(decoded_invMatrixOutputs_lo_hi_hi_4, _decoded_invMatrixOutputs_T_51) node decoded_invMatrixOutputs_lo_4 = cat(decoded_invMatrixOutputs_lo_hi_4, decoded_invMatrixOutputs_lo_lo_4) node decoded_invMatrixOutputs_hi_lo_hi_4 = cat(_decoded_invMatrixOutputs_T_56, _decoded_invMatrixOutputs_T_55) node decoded_invMatrixOutputs_hi_lo_4 = cat(decoded_invMatrixOutputs_hi_lo_hi_4, _decoded_invMatrixOutputs_T_54) node decoded_invMatrixOutputs_hi_hi_hi_4 = cat(_decoded_invMatrixOutputs_T_59, _decoded_invMatrixOutputs_T_58) node decoded_invMatrixOutputs_hi_hi_4 = cat(decoded_invMatrixOutputs_hi_hi_hi_4, _decoded_invMatrixOutputs_T_57) node decoded_invMatrixOutputs_hi_4 = cat(decoded_invMatrixOutputs_hi_hi_4, decoded_invMatrixOutputs_hi_lo_4) node decoded_invMatrixOutputs_4 = cat(decoded_invMatrixOutputs_hi_4, decoded_invMatrixOutputs_lo_4) connect decoded_plaOutput_4, decoded_invMatrixOutputs_4 connect decoded_plaInput_4, addr_4 node _decoded_T_160 = bits(decoded_plaOutput_4, 7, 0) node _decoded_T_161 = shl(UInt<4>(0hf), 4) node _decoded_T_162 = xor(UInt<8>(0hff), _decoded_T_161) node _decoded_T_163 = shr(_decoded_T_160, 4) node _decoded_T_164 = and(_decoded_T_163, _decoded_T_162) node _decoded_T_165 = bits(_decoded_T_160, 3, 0) node _decoded_T_166 = shl(_decoded_T_165, 4) node _decoded_T_167 = not(_decoded_T_162) node _decoded_T_168 = and(_decoded_T_166, _decoded_T_167) node _decoded_T_169 = or(_decoded_T_164, _decoded_T_168) node _decoded_T_170 = bits(_decoded_T_162, 5, 0) node _decoded_T_171 = shl(_decoded_T_170, 2) node _decoded_T_172 = xor(_decoded_T_162, _decoded_T_171) node _decoded_T_173 = shr(_decoded_T_169, 2) node _decoded_T_174 = and(_decoded_T_173, _decoded_T_172) node _decoded_T_175 = bits(_decoded_T_169, 5, 0) node _decoded_T_176 = shl(_decoded_T_175, 2) node _decoded_T_177 = not(_decoded_T_172) node _decoded_T_178 = and(_decoded_T_176, _decoded_T_177) node _decoded_T_179 = or(_decoded_T_174, _decoded_T_178) node _decoded_T_180 = bits(_decoded_T_172, 6, 0) node _decoded_T_181 = shl(_decoded_T_180, 1) node _decoded_T_182 = xor(_decoded_T_172, _decoded_T_181) node _decoded_T_183 = shr(_decoded_T_179, 1) node _decoded_T_184 = and(_decoded_T_183, _decoded_T_182) node _decoded_T_185 = bits(_decoded_T_179, 6, 0) node _decoded_T_186 = shl(_decoded_T_185, 1) node _decoded_T_187 = not(_decoded_T_182) node _decoded_T_188 = and(_decoded_T_186, _decoded_T_187) node _decoded_T_189 = or(_decoded_T_184, _decoded_T_188) node _decoded_T_190 = bits(decoded_plaOutput_4, 11, 8) node _decoded_T_191 = bits(_decoded_T_190, 1, 0) node _decoded_T_192 = bits(_decoded_T_191, 0, 0) node _decoded_T_193 = bits(_decoded_T_191, 1, 1) node _decoded_T_194 = cat(_decoded_T_192, _decoded_T_193) node _decoded_T_195 = bits(_decoded_T_190, 3, 2) node _decoded_T_196 = bits(_decoded_T_195, 0, 0) node _decoded_T_197 = bits(_decoded_T_195, 1, 1) node _decoded_T_198 = cat(_decoded_T_196, _decoded_T_197) node _decoded_T_199 = cat(_decoded_T_194, _decoded_T_198) node decoded_4 = cat(_decoded_T_189, _decoded_T_199) node _io_resp_4_vc_sel_0_0_T = bits(decoded_4, 0, 0) connect io.resp.`4`.vc_sel.`0`[0], _io_resp_4_vc_sel_0_0_T node _io_resp_4_vc_sel_0_1_T = bits(decoded_4, 1, 1) connect io.resp.`4`.vc_sel.`0`[1], _io_resp_4_vc_sel_0_1_T node _io_resp_4_vc_sel_0_2_T = bits(decoded_4, 2, 2) connect io.resp.`4`.vc_sel.`0`[2], _io_resp_4_vc_sel_0_2_T node _io_resp_4_vc_sel_1_0_T = bits(decoded_4, 3, 3) connect io.resp.`4`.vc_sel.`1`[0], _io_resp_4_vc_sel_1_0_T node _io_resp_4_vc_sel_1_1_T = bits(decoded_4, 4, 4) connect io.resp.`4`.vc_sel.`1`[1], _io_resp_4_vc_sel_1_1_T node _io_resp_4_vc_sel_1_2_T = bits(decoded_4, 5, 5) connect io.resp.`4`.vc_sel.`1`[2], _io_resp_4_vc_sel_1_2_T node _io_resp_4_vc_sel_2_0_T = bits(decoded_4, 6, 6) connect io.resp.`4`.vc_sel.`2`[0], _io_resp_4_vc_sel_2_0_T node _io_resp_4_vc_sel_2_1_T = bits(decoded_4, 7, 7) connect io.resp.`4`.vc_sel.`2`[1], _io_resp_4_vc_sel_2_1_T node _io_resp_4_vc_sel_2_2_T = bits(decoded_4, 8, 8) connect io.resp.`4`.vc_sel.`2`[2], _io_resp_4_vc_sel_2_2_T node _io_resp_4_vc_sel_3_0_T = bits(decoded_4, 9, 9) connect io.resp.`4`.vc_sel.`3`[0], _io_resp_4_vc_sel_3_0_T node _io_resp_4_vc_sel_3_1_T = bits(decoded_4, 10, 10) connect io.resp.`4`.vc_sel.`3`[1], _io_resp_4_vc_sel_3_1_T node _io_resp_4_vc_sel_3_2_T = bits(decoded_4, 11, 11) connect io.resp.`4`.vc_sel.`3`[2], _io_resp_4_vc_sel_3_2_T connect io.resp.`4`.vc_sel.`4`[0], UInt<1>(0h0) connect io.resp.`4`.vc_sel.`5`[0], UInt<1>(0h0) extmodule plusarg_reader_36 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20
module RouteComputer_10( // @[RouteComputer.scala:29:7] input [3:0] io_req_4_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_4_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_3_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_3_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_3_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_2 // @[RouteComputer.scala:40:14] ); wire [16:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id, io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [16:0] decoded_invInputs_1 = ~{io_req_1_bits_src_virt_id, io_req_1_bits_flow_vnet_id, io_req_1_bits_flow_ingress_node, io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [16:0] decoded_invInputs_2 = ~{io_req_2_bits_src_virt_id, io_req_2_bits_flow_vnet_id, io_req_2_bits_flow_ingress_node, io_req_2_bits_flow_ingress_node_id, io_req_2_bits_flow_egress_node, io_req_2_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [16:0] decoded_invInputs_3 = ~{io_req_3_bits_src_virt_id, io_req_3_bits_flow_vnet_id, io_req_3_bits_flow_ingress_node, io_req_3_bits_flow_ingress_node_id, io_req_3_bits_flow_egress_node, io_req_3_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [3:0] _GEN = ~io_req_4_bits_flow_egress_node; // @[pla.scala:78:21] wire [1:0] _GEN_0 = ~io_req_4_bits_flow_egress_node_id; // @[pla.scala:78:21] assign io_resp_4_vc_sel_3_0 = &{_GEN[0], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], io_req_4_bits_flow_egress_node[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_4_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_3_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_2_0 = &{_GEN_0[0], _GEN_0[1], io_req_4_bits_flow_egress_node[0], io_req_4_bits_flow_egress_node[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_4_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_2_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_1_0 = |{&{_GEN_0[0], _GEN_0[1], _GEN[1]}, &{_GEN[1], _GEN[2], _GEN[3]}}; // @[pla.scala:78:21, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_0_0 = &{_GEN[0], io_req_4_bits_flow_egress_node[1], _GEN[2], _GEN[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_4_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_3_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_3_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_2_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_0_1 = |{&{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[5], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[2], io_req_3_bits_flow_ingress_node[3], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[14], decoded_invInputs_3[15]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[5], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[2], io_req_3_bits_flow_ingress_node[3], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[14], decoded_invInputs_3[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_2 = |{&{decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[2], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[15]}, &{decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[2], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_3_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_2_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_1_1 = |{&{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[14], decoded_invInputs_2[15]}, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[14], decoded_invInputs_2[16]}, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[14], decoded_invInputs_2[15]}, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[14], decoded_invInputs_2[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_2 = |{&{decoded_invInputs_2[0], decoded_invInputs_2[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[15]}, &{decoded_invInputs_2[0], decoded_invInputs_2[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_0_1 = |{&{io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[14], decoded_invInputs_2[15]}, &{io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[14], decoded_invInputs_2[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_2 = |{&{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[15]}, &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_0 = |{&{decoded_invInputs_1[0], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15]}, &{decoded_invInputs_1[0], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_3_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_2_0 = |{&{decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[0], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15]}, &{decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[0], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_2_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_0 = |{&{decoded_invInputs_1[0], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15]}, &{decoded_invInputs_1[0], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_1 = |{&{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15]}, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_2 = |{&{decoded_invInputs_1[0], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[15]}, &{decoded_invInputs_1[0], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_0 = |{&{decoded_invInputs[0], decoded_invInputs[14], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[14], decoded_invInputs[16]}}; // @[pla.scala:78:21, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_3_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_2_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Router_17 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[2], sa_stall : UInt[2]}, egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}}, flip ingress_nodes_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_17 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire debugNodeOut : { va_stall : UInt[2], sa_stall : UInt[2]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] connect destNodesIn, auto.dest_nodes_in connect auto.source_nodes_out, sourceNodesOut connect ingressNodesIn, auto.ingress_nodes_in connect auto.egress_nodes_out, egressNodesOut connect auto.debug_out, debugNodeOut inst input_unit_0_from_3 of InputUnit_17 connect input_unit_0_from_3.clock, clock connect input_unit_0_from_3.reset, reset inst ingress_unit_1_from_5 of IngressUnit_27 connect ingress_unit_1_from_5.clock, clock connect ingress_unit_1_from_5.reset, reset inst output_unit_0_to_5 of OutputUnit_17 connect output_unit_0_to_5.clock, clock connect output_unit_0_to_5.reset, reset inst egress_unit_1_to_5 of EgressUnit_23 connect egress_unit_1_to_5.clock, clock connect egress_unit_1_to_5.reset, reset inst switch of Switch_17 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_17 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_17 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_17 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_3 = bits(_fires_count_T_2, 1, 0) wire fires_count : UInt connect fires_count, _fires_count_T_3 connect input_unit_0_from_3.io.in, destNodesIn connect ingress_unit_1_from_5.io.in, ingressNodesIn.flit connect output_unit_0_to_5.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_5.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_5.io.out.flit connect egressNodesOut.flit.bits, egress_unit_1_to_5.io.out.bits connect egressNodesOut.flit.valid, egress_unit_1_to_5.io.out.valid connect egress_unit_1_to_5.io.out.ready, egressNodesOut.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_3.io.router_req connect route_computer.io.req.`1`, ingress_unit_1_from_5.io.router_req connect input_unit_0_from_3.io.router_resp, route_computer.io.resp.`0` connect ingress_unit_1_from_5.io.router_resp, route_computer.io.resp.`1` connect vc_allocator.io.req.`0`, input_unit_0_from_3.io.vcalloc_req connect vc_allocator.io.req.`1`, ingress_unit_1_from_5.io.vcalloc_req connect input_unit_0_from_3.io.vcalloc_resp, vc_allocator.io.resp.`0` connect ingress_unit_1_from_5.io.vcalloc_resp, vc_allocator.io.resp.`1` connect output_unit_0_to_5.io.allocs, vc_allocator.io.out_allocs.`0` connect egress_unit_1_to_5.io.allocs, vc_allocator.io.out_allocs.`1` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_5.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_5.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_5.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_5.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_5.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_5.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_5.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_5.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_5.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_5.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_5.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_5.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_5.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_5.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_5.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_5.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_5.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_5.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_5.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_5.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_5.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_5.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_5.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_5.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_5.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_5.io.channel_status[0].occupied connect input_unit_0_from_3.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0] connect input_unit_0_from_3.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1] connect input_unit_0_from_3.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2] connect input_unit_0_from_3.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3] connect input_unit_0_from_3.io.out_credit_available.`1`[0], egress_unit_1_to_5.io.credit_available[0] connect ingress_unit_1_from_5.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0] connect ingress_unit_1_from_5.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1] connect ingress_unit_1_from_5.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2] connect ingress_unit_1_from_5.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3] connect ingress_unit_1_from_5.io.out_credit_available.`1`[0], egress_unit_1_to_5.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_3.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_5.io.salloc_req[0] connect output_unit_0_to_5.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_5.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_5.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_5.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_5.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_5.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_5.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_5.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect egress_unit_1_to_5.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect egress_unit_1_to_5.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_3.io.out[0] connect switch.io.in.`1`[0], ingress_unit_1_from_5.io.out[0] connect output_unit_0_to_5.io.in, switch.io.out.`0` connect egress_unit_1_to_5.io.in, switch.io.out.`1` reg REG : { `1` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect input_unit_0_from_3.io.block, UInt<1>(0h0) connect ingress_unit_1_from_5.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_3.io.debug.va_stall connect debugNodeOut.va_stall[1], ingress_unit_1_from_5.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_3.io.debug.sa_stall connect debugNodeOut.sa_stall[1], ingress_unit_1_from_5.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_35 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 3 4 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, _T_11) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, _T_11) connect fired_1, _fired_T_1 node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_14 = tail(_T_13, 1) node _T_15 = eq(debug_sample, _T_14) node _T_16 = and(_T_12, _T_15) node _T_17 = and(_T_16, fired_1) when _T_17 : node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "nocsample %d i5 4 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, _T_11 node _T_20 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, _T_20) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, _T_20) connect fired_2, _fired_T_2 node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_23 = tail(_T_22, 1) node _T_24 = eq(debug_sample, _T_23) node _T_25 = and(_T_21, _T_24) node _T_26 = and(_T_25, fired_2) when _T_26 : node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "nocsample %d 4 e5 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, _T_20
module Router_17( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [3:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_1_to_5_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_5_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_5_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_5_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _ingress_unit_1_from_5_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [36:0] _ingress_unit_1_from_5_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_5_io_in_ready; // @[Router.scala:116:13] wire [1:0] _input_unit_0_from_3_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_3_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_3_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_0_from_3_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_3_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_3_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_3_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_3_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_5_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_5 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 node _source_ok_T_28 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[2]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[3]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[4]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[5]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_33, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = and(_T_11, _T_24) node _T_89 = and(_T_88, _T_37) node _T_90 = and(_T_89, _T_50) node _T_91 = and(_T_90, _T_63) node _T_92 = and(_T_91, _T_71) node _T_93 = and(_T_92, _T_79) node _T_94 = and(_T_93, _T_87) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_94, UInt<1>(0h1), "") : assert_1 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_103 = shr(io.in.a.bits.source, 2) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_4) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_108 = and(_T_106, _T_107) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_109 = shr(io.in.a.bits.source, 2) node _T_110 = eq(_T_109, UInt<1>(0h1)) node _T_111 = leq(UInt<1>(0h0), uncommonBits_5) node _T_112 = and(_T_110, _T_111) node _T_113 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_114 = and(_T_112, _T_113) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_115 = shr(io.in.a.bits.source, 2) node _T_116 = eq(_T_115, UInt<2>(0h2)) node _T_117 = leq(UInt<1>(0h0), uncommonBits_6) node _T_118 = and(_T_116, _T_117) node _T_119 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_120 = and(_T_118, _T_119) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<2>(0h3)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_7) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_129 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_130 = or(_T_102, _T_108) node _T_131 = or(_T_130, _T_114) node _T_132 = or(_T_131, _T_120) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) node _T_135 = or(_T_134, _T_128) node _T_136 = or(_T_135, _T_129) node _T_137 = and(_T_101, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<13>(0h1000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = or(_T_144, _T_149) node _T_151 = and(_T_139, _T_150) node _T_152 = or(UInt<1>(0h0), _T_151) node _T_153 = and(_T_138, _T_152) node _T_154 = asUInt(reset) node _T_155 = eq(_T_154, UInt<1>(0h0)) when _T_155 : node _T_156 = eq(_T_153, UInt<1>(0h0)) when _T_156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_153, UInt<1>(0h1), "") : assert_2 node _T_157 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_158 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_159 = and(_T_157, _T_158) node _T_160 = or(UInt<1>(0h0), _T_159) node _T_161 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<13>(0h1000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = or(_T_165, _T_170) node _T_172 = and(_T_160, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = and(UInt<1>(0h0), _T_173) node _T_175 = asUInt(reset) node _T_176 = eq(_T_175, UInt<1>(0h0)) when _T_176 : node _T_177 = eq(_T_174, UInt<1>(0h0)) when _T_177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_174, UInt<1>(0h1), "") : assert_3 node _T_178 = asUInt(reset) node _T_179 = eq(_T_178, UInt<1>(0h0)) when _T_179 : node _T_180 = eq(source_ok, UInt<1>(0h0)) when _T_180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_181 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(_T_181, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_181, UInt<1>(0h1), "") : assert_5 node _T_185 = asUInt(reset) node _T_186 = eq(_T_185, UInt<1>(0h0)) when _T_186 : node _T_187 = eq(is_aligned, UInt<1>(0h0)) when _T_187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_188 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_189 = asUInt(reset) node _T_190 = eq(_T_189, UInt<1>(0h0)) when _T_190 : node _T_191 = eq(_T_188, UInt<1>(0h0)) when _T_191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_188, UInt<1>(0h1), "") : assert_7 node _T_192 = not(io.in.a.bits.mask) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_193, UInt<1>(0h1), "") : assert_8 node _T_197 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_197, UInt<1>(0h1), "") : assert_9 node _T_201 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_201 : node _T_202 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_203 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_204 = and(_T_202, _T_203) node _T_205 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_206 = shr(io.in.a.bits.source, 2) node _T_207 = eq(_T_206, UInt<1>(0h0)) node _T_208 = leq(UInt<1>(0h0), uncommonBits_8) node _T_209 = and(_T_207, _T_208) node _T_210 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_211 = and(_T_209, _T_210) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_212 = shr(io.in.a.bits.source, 2) node _T_213 = eq(_T_212, UInt<1>(0h1)) node _T_214 = leq(UInt<1>(0h0), uncommonBits_9) node _T_215 = and(_T_213, _T_214) node _T_216 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_217 = and(_T_215, _T_216) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_218 = shr(io.in.a.bits.source, 2) node _T_219 = eq(_T_218, UInt<2>(0h2)) node _T_220 = leq(UInt<1>(0h0), uncommonBits_10) node _T_221 = and(_T_219, _T_220) node _T_222 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_223 = and(_T_221, _T_222) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_224 = shr(io.in.a.bits.source, 2) node _T_225 = eq(_T_224, UInt<2>(0h3)) node _T_226 = leq(UInt<1>(0h0), uncommonBits_11) node _T_227 = and(_T_225, _T_226) node _T_228 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_229 = and(_T_227, _T_228) node _T_230 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_231 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_232 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_233 = or(_T_205, _T_211) node _T_234 = or(_T_233, _T_217) node _T_235 = or(_T_234, _T_223) node _T_236 = or(_T_235, _T_229) node _T_237 = or(_T_236, _T_230) node _T_238 = or(_T_237, _T_231) node _T_239 = or(_T_238, _T_232) node _T_240 = and(_T_204, _T_239) node _T_241 = or(UInt<1>(0h0), _T_240) node _T_242 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_243 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_244 = cvt(_T_243) node _T_245 = and(_T_244, asSInt(UInt<13>(0h1000))) node _T_246 = asSInt(_T_245) node _T_247 = eq(_T_246, asSInt(UInt<1>(0h0))) node _T_248 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_249 = cvt(_T_248) node _T_250 = and(_T_249, asSInt(UInt<13>(0h1000))) node _T_251 = asSInt(_T_250) node _T_252 = eq(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = or(_T_247, _T_252) node _T_254 = and(_T_242, _T_253) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = and(_T_241, _T_255) node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(_T_256, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_256, UInt<1>(0h1), "") : assert_10 node _T_260 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_261 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_262 = and(_T_260, _T_261) node _T_263 = or(UInt<1>(0h0), _T_262) node _T_264 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<13>(0h1000))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<13>(0h1000))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = or(_T_268, _T_273) node _T_275 = and(_T_263, _T_274) node _T_276 = or(UInt<1>(0h0), _T_275) node _T_277 = and(UInt<1>(0h0), _T_276) node _T_278 = asUInt(reset) node _T_279 = eq(_T_278, UInt<1>(0h0)) when _T_279 : node _T_280 = eq(_T_277, UInt<1>(0h0)) when _T_280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_277, UInt<1>(0h1), "") : assert_11 node _T_281 = asUInt(reset) node _T_282 = eq(_T_281, UInt<1>(0h0)) when _T_282 : node _T_283 = eq(source_ok, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_284 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_284, UInt<1>(0h1), "") : assert_13 node _T_288 = asUInt(reset) node _T_289 = eq(_T_288, UInt<1>(0h0)) when _T_289 : node _T_290 = eq(is_aligned, UInt<1>(0h0)) when _T_290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_291 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_292 = asUInt(reset) node _T_293 = eq(_T_292, UInt<1>(0h0)) when _T_293 : node _T_294 = eq(_T_291, UInt<1>(0h0)) when _T_294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_291, UInt<1>(0h1), "") : assert_15 node _T_295 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_295, UInt<1>(0h1), "") : assert_16 node _T_299 = not(io.in.a.bits.mask) node _T_300 = eq(_T_299, UInt<1>(0h0)) node _T_301 = asUInt(reset) node _T_302 = eq(_T_301, UInt<1>(0h0)) when _T_302 : node _T_303 = eq(_T_300, UInt<1>(0h0)) when _T_303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_300, UInt<1>(0h1), "") : assert_17 node _T_304 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_305 = asUInt(reset) node _T_306 = eq(_T_305, UInt<1>(0h0)) when _T_306 : node _T_307 = eq(_T_304, UInt<1>(0h0)) when _T_307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_304, UInt<1>(0h1), "") : assert_18 node _T_308 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_308 : node _T_309 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_310 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_311 = and(_T_309, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_313 = shr(io.in.a.bits.source, 2) node _T_314 = eq(_T_313, UInt<1>(0h0)) node _T_315 = leq(UInt<1>(0h0), uncommonBits_12) node _T_316 = and(_T_314, _T_315) node _T_317 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_318 = and(_T_316, _T_317) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_319 = shr(io.in.a.bits.source, 2) node _T_320 = eq(_T_319, UInt<1>(0h1)) node _T_321 = leq(UInt<1>(0h0), uncommonBits_13) node _T_322 = and(_T_320, _T_321) node _T_323 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_325 = shr(io.in.a.bits.source, 2) node _T_326 = eq(_T_325, UInt<2>(0h2)) node _T_327 = leq(UInt<1>(0h0), uncommonBits_14) node _T_328 = and(_T_326, _T_327) node _T_329 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_330 = and(_T_328, _T_329) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_331 = shr(io.in.a.bits.source, 2) node _T_332 = eq(_T_331, UInt<2>(0h3)) node _T_333 = leq(UInt<1>(0h0), uncommonBits_15) node _T_334 = and(_T_332, _T_333) node _T_335 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_339 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_340 = or(_T_312, _T_318) node _T_341 = or(_T_340, _T_324) node _T_342 = or(_T_341, _T_330) node _T_343 = or(_T_342, _T_336) node _T_344 = or(_T_343, _T_337) node _T_345 = or(_T_344, _T_338) node _T_346 = or(_T_345, _T_339) node _T_347 = and(_T_311, _T_346) node _T_348 = or(UInt<1>(0h0), _T_347) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_348, UInt<1>(0h1), "") : assert_19 node _T_352 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_353 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_354 = and(_T_352, _T_353) node _T_355 = or(UInt<1>(0h0), _T_354) node _T_356 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_357 = cvt(_T_356) node _T_358 = and(_T_357, asSInt(UInt<13>(0h1000))) node _T_359 = asSInt(_T_358) node _T_360 = eq(_T_359, asSInt(UInt<1>(0h0))) node _T_361 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_362 = cvt(_T_361) node _T_363 = and(_T_362, asSInt(UInt<13>(0h1000))) node _T_364 = asSInt(_T_363) node _T_365 = eq(_T_364, asSInt(UInt<1>(0h0))) node _T_366 = or(_T_360, _T_365) node _T_367 = and(_T_355, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_368, UInt<1>(0h1), "") : assert_20 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(source_ok, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_378 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_378, UInt<1>(0h1), "") : assert_23 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_382, UInt<1>(0h1), "") : assert_24 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_386, UInt<1>(0h1), "") : assert_25 node _T_390 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_390 : node _T_391 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_392 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_395 = shr(io.in.a.bits.source, 2) node _T_396 = eq(_T_395, UInt<1>(0h0)) node _T_397 = leq(UInt<1>(0h0), uncommonBits_16) node _T_398 = and(_T_396, _T_397) node _T_399 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_400 = and(_T_398, _T_399) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_401 = shr(io.in.a.bits.source, 2) node _T_402 = eq(_T_401, UInt<1>(0h1)) node _T_403 = leq(UInt<1>(0h0), uncommonBits_17) node _T_404 = and(_T_402, _T_403) node _T_405 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_406 = and(_T_404, _T_405) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_407 = shr(io.in.a.bits.source, 2) node _T_408 = eq(_T_407, UInt<2>(0h2)) node _T_409 = leq(UInt<1>(0h0), uncommonBits_18) node _T_410 = and(_T_408, _T_409) node _T_411 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_412 = and(_T_410, _T_411) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_413 = shr(io.in.a.bits.source, 2) node _T_414 = eq(_T_413, UInt<2>(0h3)) node _T_415 = leq(UInt<1>(0h0), uncommonBits_19) node _T_416 = and(_T_414, _T_415) node _T_417 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_418 = and(_T_416, _T_417) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_422 = or(_T_394, _T_400) node _T_423 = or(_T_422, _T_406) node _T_424 = or(_T_423, _T_412) node _T_425 = or(_T_424, _T_418) node _T_426 = or(_T_425, _T_419) node _T_427 = or(_T_426, _T_420) node _T_428 = or(_T_427, _T_421) node _T_429 = and(_T_393, _T_428) node _T_430 = or(UInt<1>(0h0), _T_429) node _T_431 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_432 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_433 = and(_T_431, _T_432) node _T_434 = or(UInt<1>(0h0), _T_433) node _T_435 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_436 = cvt(_T_435) node _T_437 = and(_T_436, asSInt(UInt<13>(0h1000))) node _T_438 = asSInt(_T_437) node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0))) node _T_440 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_441 = cvt(_T_440) node _T_442 = and(_T_441, asSInt(UInt<13>(0h1000))) node _T_443 = asSInt(_T_442) node _T_444 = eq(_T_443, asSInt(UInt<1>(0h0))) node _T_445 = or(_T_439, _T_444) node _T_446 = and(_T_434, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = and(_T_430, _T_447) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_448, UInt<1>(0h1), "") : assert_26 node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(source_ok, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(is_aligned, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_458 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_459 = asUInt(reset) node _T_460 = eq(_T_459, UInt<1>(0h0)) when _T_460 : node _T_461 = eq(_T_458, UInt<1>(0h0)) when _T_461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_458, UInt<1>(0h1), "") : assert_29 node _T_462 = eq(io.in.a.bits.mask, mask) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_462, UInt<1>(0h1), "") : assert_30 node _T_466 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_466 : node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_468 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_469 = and(_T_467, _T_468) node _T_470 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_471 = shr(io.in.a.bits.source, 2) node _T_472 = eq(_T_471, UInt<1>(0h0)) node _T_473 = leq(UInt<1>(0h0), uncommonBits_20) node _T_474 = and(_T_472, _T_473) node _T_475 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_476 = and(_T_474, _T_475) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_477 = shr(io.in.a.bits.source, 2) node _T_478 = eq(_T_477, UInt<1>(0h1)) node _T_479 = leq(UInt<1>(0h0), uncommonBits_21) node _T_480 = and(_T_478, _T_479) node _T_481 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_482 = and(_T_480, _T_481) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_483 = shr(io.in.a.bits.source, 2) node _T_484 = eq(_T_483, UInt<2>(0h2)) node _T_485 = leq(UInt<1>(0h0), uncommonBits_22) node _T_486 = and(_T_484, _T_485) node _T_487 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_488 = and(_T_486, _T_487) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_489 = shr(io.in.a.bits.source, 2) node _T_490 = eq(_T_489, UInt<2>(0h3)) node _T_491 = leq(UInt<1>(0h0), uncommonBits_23) node _T_492 = and(_T_490, _T_491) node _T_493 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_496 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_497 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_498 = or(_T_470, _T_476) node _T_499 = or(_T_498, _T_482) node _T_500 = or(_T_499, _T_488) node _T_501 = or(_T_500, _T_494) node _T_502 = or(_T_501, _T_495) node _T_503 = or(_T_502, _T_496) node _T_504 = or(_T_503, _T_497) node _T_505 = and(_T_469, _T_504) node _T_506 = or(UInt<1>(0h0), _T_505) node _T_507 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_508 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_509 = and(_T_507, _T_508) node _T_510 = or(UInt<1>(0h0), _T_509) node _T_511 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<13>(0h1000))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = or(_T_515, _T_520) node _T_522 = and(_T_510, _T_521) node _T_523 = or(UInt<1>(0h0), _T_522) node _T_524 = and(_T_506, _T_523) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_524, UInt<1>(0h1), "") : assert_31 node _T_528 = asUInt(reset) node _T_529 = eq(_T_528, UInt<1>(0h0)) when _T_529 : node _T_530 = eq(source_ok, UInt<1>(0h0)) when _T_530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(is_aligned, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_534 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_534, UInt<1>(0h1), "") : assert_34 node _T_538 = not(mask) node _T_539 = and(io.in.a.bits.mask, _T_538) node _T_540 = eq(_T_539, UInt<1>(0h0)) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_540, UInt<1>(0h1), "") : assert_35 node _T_544 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_544 : node _T_545 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_546 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_547 = and(_T_545, _T_546) node _T_548 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_549 = shr(io.in.a.bits.source, 2) node _T_550 = eq(_T_549, UInt<1>(0h0)) node _T_551 = leq(UInt<1>(0h0), uncommonBits_24) node _T_552 = and(_T_550, _T_551) node _T_553 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_554 = and(_T_552, _T_553) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_555 = shr(io.in.a.bits.source, 2) node _T_556 = eq(_T_555, UInt<1>(0h1)) node _T_557 = leq(UInt<1>(0h0), uncommonBits_25) node _T_558 = and(_T_556, _T_557) node _T_559 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_560 = and(_T_558, _T_559) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_561 = shr(io.in.a.bits.source, 2) node _T_562 = eq(_T_561, UInt<2>(0h2)) node _T_563 = leq(UInt<1>(0h0), uncommonBits_26) node _T_564 = and(_T_562, _T_563) node _T_565 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_566 = and(_T_564, _T_565) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_567 = shr(io.in.a.bits.source, 2) node _T_568 = eq(_T_567, UInt<2>(0h3)) node _T_569 = leq(UInt<1>(0h0), uncommonBits_27) node _T_570 = and(_T_568, _T_569) node _T_571 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_572 = and(_T_570, _T_571) node _T_573 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_574 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_575 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_576 = or(_T_548, _T_554) node _T_577 = or(_T_576, _T_560) node _T_578 = or(_T_577, _T_566) node _T_579 = or(_T_578, _T_572) node _T_580 = or(_T_579, _T_573) node _T_581 = or(_T_580, _T_574) node _T_582 = or(_T_581, _T_575) node _T_583 = and(_T_547, _T_582) node _T_584 = or(UInt<1>(0h0), _T_583) node _T_585 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_586 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _T_588 = or(UInt<1>(0h0), _T_587) node _T_589 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = or(_T_593, _T_598) node _T_600 = and(_T_588, _T_599) node _T_601 = or(UInt<1>(0h0), _T_600) node _T_602 = and(_T_584, _T_601) node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(_T_602, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_602, UInt<1>(0h1), "") : assert_36 node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(source_ok, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(is_aligned, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_612 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_613 = asUInt(reset) node _T_614 = eq(_T_613, UInt<1>(0h0)) when _T_614 : node _T_615 = eq(_T_612, UInt<1>(0h0)) when _T_615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_612, UInt<1>(0h1), "") : assert_39 node _T_616 = eq(io.in.a.bits.mask, mask) node _T_617 = asUInt(reset) node _T_618 = eq(_T_617, UInt<1>(0h0)) when _T_618 : node _T_619 = eq(_T_616, UInt<1>(0h0)) when _T_619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_616, UInt<1>(0h1), "") : assert_40 node _T_620 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_620 : node _T_621 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_622 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_623 = and(_T_621, _T_622) node _T_624 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_625 = shr(io.in.a.bits.source, 2) node _T_626 = eq(_T_625, UInt<1>(0h0)) node _T_627 = leq(UInt<1>(0h0), uncommonBits_28) node _T_628 = and(_T_626, _T_627) node _T_629 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_630 = and(_T_628, _T_629) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_631 = shr(io.in.a.bits.source, 2) node _T_632 = eq(_T_631, UInt<1>(0h1)) node _T_633 = leq(UInt<1>(0h0), uncommonBits_29) node _T_634 = and(_T_632, _T_633) node _T_635 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_636 = and(_T_634, _T_635) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_637 = shr(io.in.a.bits.source, 2) node _T_638 = eq(_T_637, UInt<2>(0h2)) node _T_639 = leq(UInt<1>(0h0), uncommonBits_30) node _T_640 = and(_T_638, _T_639) node _T_641 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_642 = and(_T_640, _T_641) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_643 = shr(io.in.a.bits.source, 2) node _T_644 = eq(_T_643, UInt<2>(0h3)) node _T_645 = leq(UInt<1>(0h0), uncommonBits_31) node _T_646 = and(_T_644, _T_645) node _T_647 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_650 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_651 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_652 = or(_T_624, _T_630) node _T_653 = or(_T_652, _T_636) node _T_654 = or(_T_653, _T_642) node _T_655 = or(_T_654, _T_648) node _T_656 = or(_T_655, _T_649) node _T_657 = or(_T_656, _T_650) node _T_658 = or(_T_657, _T_651) node _T_659 = and(_T_623, _T_658) node _T_660 = or(UInt<1>(0h0), _T_659) node _T_661 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_662 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_663 = and(_T_661, _T_662) node _T_664 = or(UInt<1>(0h0), _T_663) node _T_665 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<13>(0h1000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<13>(0h1000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = or(_T_669, _T_674) node _T_676 = and(_T_664, _T_675) node _T_677 = or(UInt<1>(0h0), _T_676) node _T_678 = and(_T_660, _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_678, UInt<1>(0h1), "") : assert_41 node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(source_ok, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_685 = asUInt(reset) node _T_686 = eq(_T_685, UInt<1>(0h0)) when _T_686 : node _T_687 = eq(is_aligned, UInt<1>(0h0)) when _T_687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_688 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_688, UInt<1>(0h1), "") : assert_44 node _T_692 = eq(io.in.a.bits.mask, mask) node _T_693 = asUInt(reset) node _T_694 = eq(_T_693, UInt<1>(0h0)) when _T_694 : node _T_695 = eq(_T_692, UInt<1>(0h0)) when _T_695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_692, UInt<1>(0h1), "") : assert_45 node _T_696 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_696 : node _T_697 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_698 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_699 = and(_T_697, _T_698) node _T_700 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<1>(0h0)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_32) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<1>(0h1)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_33) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_713 = shr(io.in.a.bits.source, 2) node _T_714 = eq(_T_713, UInt<2>(0h2)) node _T_715 = leq(UInt<1>(0h0), uncommonBits_34) node _T_716 = and(_T_714, _T_715) node _T_717 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_718 = and(_T_716, _T_717) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_719 = shr(io.in.a.bits.source, 2) node _T_720 = eq(_T_719, UInt<2>(0h3)) node _T_721 = leq(UInt<1>(0h0), uncommonBits_35) node _T_722 = and(_T_720, _T_721) node _T_723 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_724 = and(_T_722, _T_723) node _T_725 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_726 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_727 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_728 = or(_T_700, _T_706) node _T_729 = or(_T_728, _T_712) node _T_730 = or(_T_729, _T_718) node _T_731 = or(_T_730, _T_724) node _T_732 = or(_T_731, _T_725) node _T_733 = or(_T_732, _T_726) node _T_734 = or(_T_733, _T_727) node _T_735 = and(_T_699, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_738 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<13>(0h1000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = or(_T_742, _T_747) node _T_749 = and(_T_737, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = and(_T_736, _T_750) node _T_752 = asUInt(reset) node _T_753 = eq(_T_752, UInt<1>(0h0)) when _T_753 : node _T_754 = eq(_T_751, UInt<1>(0h0)) when _T_754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_751, UInt<1>(0h1), "") : assert_46 node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(source_ok, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_758 = asUInt(reset) node _T_759 = eq(_T_758, UInt<1>(0h0)) when _T_759 : node _T_760 = eq(is_aligned, UInt<1>(0h0)) when _T_760 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_761 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_761, UInt<1>(0h1), "") : assert_49 node _T_765 = eq(io.in.a.bits.mask, mask) node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(_T_765, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_765, UInt<1>(0h1), "") : assert_50 node _T_769 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_770 = asUInt(reset) node _T_771 = eq(_T_770, UInt<1>(0h0)) when _T_771 : node _T_772 = eq(_T_769, UInt<1>(0h0)) when _T_772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_769, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_773 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_773, UInt<1>(0h1), "") : assert_52 node _source_ok_T_34 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h0)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h1)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_53 = shr(io.in.d.bits.source, 2) node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3)) node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_34 connect _source_ok_WIRE_1[1], _source_ok_T_40 connect _source_ok_WIRE_1[2], _source_ok_T_46 connect _source_ok_WIRE_1[3], _source_ok_T_52 connect _source_ok_WIRE_1[4], _source_ok_T_58 connect _source_ok_WIRE_1[5], _source_ok_T_59 connect _source_ok_WIRE_1[6], _source_ok_T_60 connect _source_ok_WIRE_1[7], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE_1[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE_1[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_67, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_777 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_777 : node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(source_ok_1, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_781 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_781, UInt<1>(0h1), "") : assert_54 node _T_785 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_785, UInt<1>(0h1), "") : assert_55 node _T_789 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_789, UInt<1>(0h1), "") : assert_56 node _T_793 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_793, UInt<1>(0h1), "") : assert_57 node _T_797 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_797 : node _T_798 = asUInt(reset) node _T_799 = eq(_T_798, UInt<1>(0h0)) when _T_799 : node _T_800 = eq(source_ok_1, UInt<1>(0h0)) when _T_800 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(sink_ok, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_804 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_804, UInt<1>(0h1), "") : assert_60 node _T_808 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_809 = asUInt(reset) node _T_810 = eq(_T_809, UInt<1>(0h0)) when _T_810 : node _T_811 = eq(_T_808, UInt<1>(0h0)) when _T_811 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_808, UInt<1>(0h1), "") : assert_61 node _T_812 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_813 = asUInt(reset) node _T_814 = eq(_T_813, UInt<1>(0h0)) when _T_814 : node _T_815 = eq(_T_812, UInt<1>(0h0)) when _T_815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_812, UInt<1>(0h1), "") : assert_62 node _T_816 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_817 = asUInt(reset) node _T_818 = eq(_T_817, UInt<1>(0h0)) when _T_818 : node _T_819 = eq(_T_816, UInt<1>(0h0)) when _T_819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_816, UInt<1>(0h1), "") : assert_63 node _T_820 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_821 = or(UInt<1>(0h0), _T_820) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_821, UInt<1>(0h1), "") : assert_64 node _T_825 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_825 : node _T_826 = asUInt(reset) node _T_827 = eq(_T_826, UInt<1>(0h0)) when _T_827 : node _T_828 = eq(source_ok_1, UInt<1>(0h0)) when _T_828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(sink_ok, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_832 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_832, UInt<1>(0h1), "") : assert_67 node _T_836 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_836, UInt<1>(0h1), "") : assert_68 node _T_840 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_841 = asUInt(reset) node _T_842 = eq(_T_841, UInt<1>(0h0)) when _T_842 : node _T_843 = eq(_T_840, UInt<1>(0h0)) when _T_843 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_840, UInt<1>(0h1), "") : assert_69 node _T_844 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_845 = or(_T_844, io.in.d.bits.corrupt) node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(_T_845, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_845, UInt<1>(0h1), "") : assert_70 node _T_849 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_850 = or(UInt<1>(0h0), _T_849) node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(_T_850, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_850, UInt<1>(0h1), "") : assert_71 node _T_854 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_854 : node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(source_ok_1, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_858 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_858, UInt<1>(0h1), "") : assert_73 node _T_862 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(_T_862, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_862, UInt<1>(0h1), "") : assert_74 node _T_866 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_867 = or(UInt<1>(0h0), _T_866) node _T_868 = asUInt(reset) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(_T_867, UInt<1>(0h0)) when _T_870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_867, UInt<1>(0h1), "") : assert_75 node _T_871 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_871 : node _T_872 = asUInt(reset) node _T_873 = eq(_T_872, UInt<1>(0h0)) when _T_873 : node _T_874 = eq(source_ok_1, UInt<1>(0h0)) when _T_874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_875 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_876 = asUInt(reset) node _T_877 = eq(_T_876, UInt<1>(0h0)) when _T_877 : node _T_878 = eq(_T_875, UInt<1>(0h0)) when _T_878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_875, UInt<1>(0h1), "") : assert_77 node _T_879 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_880 = or(_T_879, io.in.d.bits.corrupt) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_880, UInt<1>(0h1), "") : assert_78 node _T_884 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_885 = or(UInt<1>(0h0), _T_884) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_885, UInt<1>(0h1), "") : assert_79 node _T_889 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_889 : node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(source_ok_1, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_893 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_893, UInt<1>(0h1), "") : assert_81 node _T_897 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_898 = asUInt(reset) node _T_899 = eq(_T_898, UInt<1>(0h0)) when _T_899 : node _T_900 = eq(_T_897, UInt<1>(0h0)) when _T_900 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_897, UInt<1>(0h1), "") : assert_82 node _T_901 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_902 = or(UInt<1>(0h0), _T_901) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_902, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_906 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(_T_906, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_906, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_910 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_911 = asUInt(reset) node _T_912 = eq(_T_911, UInt<1>(0h0)) when _T_912 : node _T_913 = eq(_T_910, UInt<1>(0h0)) when _T_913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_910, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_914 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_914, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_918 = eq(a_first, UInt<1>(0h0)) node _T_919 = and(io.in.a.valid, _T_918) when _T_919 : node _T_920 = eq(io.in.a.bits.opcode, opcode) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_920, UInt<1>(0h1), "") : assert_87 node _T_924 = eq(io.in.a.bits.param, param) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_924, UInt<1>(0h1), "") : assert_88 node _T_928 = eq(io.in.a.bits.size, size) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_928, UInt<1>(0h1), "") : assert_89 node _T_932 = eq(io.in.a.bits.source, source) node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(_T_932, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_932, UInt<1>(0h1), "") : assert_90 node _T_936 = eq(io.in.a.bits.address, address) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_936, UInt<1>(0h1), "") : assert_91 node _T_940 = and(io.in.a.ready, io.in.a.valid) node _T_941 = and(_T_940, a_first) when _T_941 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_942 = eq(d_first, UInt<1>(0h0)) node _T_943 = and(io.in.d.valid, _T_942) when _T_943 : node _T_944 = eq(io.in.d.bits.opcode, opcode_1) node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(_T_944, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_944, UInt<1>(0h1), "") : assert_92 node _T_948 = eq(io.in.d.bits.param, param_1) node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(_T_948, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_948, UInt<1>(0h1), "") : assert_93 node _T_952 = eq(io.in.d.bits.size, size_1) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_952, UInt<1>(0h1), "") : assert_94 node _T_956 = eq(io.in.d.bits.source, source_1) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_956, UInt<1>(0h1), "") : assert_95 node _T_960 = eq(io.in.d.bits.sink, sink) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_960, UInt<1>(0h1), "") : assert_96 node _T_964 = eq(io.in.d.bits.denied, denied) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_964, UInt<1>(0h1), "") : assert_97 node _T_968 = and(io.in.d.ready, io.in.d.valid) node _T_969 = and(_T_968, d_first) when _T_969 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_970 = and(io.in.a.valid, a_first_1) node _T_971 = and(_T_970, UInt<1>(0h1)) when _T_971 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_972 = and(io.in.a.ready, io.in.a.valid) node _T_973 = and(_T_972, a_first_1) node _T_974 = and(_T_973, UInt<1>(0h1)) when _T_974 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_975 = dshr(inflight, io.in.a.bits.source) node _T_976 = bits(_T_975, 0, 0) node _T_977 = eq(_T_976, UInt<1>(0h0)) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_977, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_981 = and(io.in.d.valid, d_first_1) node _T_982 = and(_T_981, UInt<1>(0h1)) node _T_983 = eq(d_release_ack, UInt<1>(0h0)) node _T_984 = and(_T_982, _T_983) when _T_984 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_985 = and(io.in.d.ready, io.in.d.valid) node _T_986 = and(_T_985, d_first_1) node _T_987 = and(_T_986, UInt<1>(0h1)) node _T_988 = eq(d_release_ack, UInt<1>(0h0)) node _T_989 = and(_T_987, _T_988) when _T_989 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_990 = and(io.in.d.valid, d_first_1) node _T_991 = and(_T_990, UInt<1>(0h1)) node _T_992 = eq(d_release_ack, UInt<1>(0h0)) node _T_993 = and(_T_991, _T_992) when _T_993 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_994 = dshr(inflight, io.in.d.bits.source) node _T_995 = bits(_T_994, 0, 0) node _T_996 = or(_T_995, same_cycle_resp) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_996, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1000 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1001 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1002 = or(_T_1000, _T_1001) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_100 node _T_1006 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_101 else : node _T_1010 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1011 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1012 = or(_T_1010, _T_1011) node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(_T_1012, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1012, UInt<1>(0h1), "") : assert_102 node _T_1016 = eq(io.in.d.bits.size, a_size_lookup) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_103 node _T_1020 = and(io.in.d.valid, d_first_1) node _T_1021 = and(_T_1020, a_first_1) node _T_1022 = and(_T_1021, io.in.a.valid) node _T_1023 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1024 = and(_T_1022, _T_1023) node _T_1025 = eq(d_release_ack, UInt<1>(0h0)) node _T_1026 = and(_T_1024, _T_1025) when _T_1026 : node _T_1027 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1028 = or(_T_1027, io.in.a.ready) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_104 node _T_1032 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1033 = orr(a_set_wo_ready) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) node _T_1035 = or(_T_1032, _T_1034) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_10 node _T_1039 = orr(inflight) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) node _T_1041 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1042 = or(_T_1040, _T_1041) node _T_1043 = lt(watchdog, plusarg_reader.out) node _T_1044 = or(_T_1042, _T_1043) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1048 = and(io.in.a.ready, io.in.a.valid) node _T_1049 = and(io.in.d.ready, io.in.d.valid) node _T_1050 = or(_T_1048, _T_1049) when _T_1050 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1051 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1052 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1053 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1054 = and(_T_1052, _T_1053) node _T_1055 = and(_T_1051, _T_1054) when _T_1055 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1056 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1057 = and(_T_1056, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1058 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1059 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1060 = and(_T_1058, _T_1059) node _T_1061 = and(_T_1057, _T_1060) when _T_1061 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1062 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1063 = bits(_T_1062, 0, 0) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1068 = and(io.in.d.valid, d_first_2) node _T_1069 = and(_T_1068, UInt<1>(0h1)) node _T_1070 = and(_T_1069, d_release_ack_1) when _T_1070 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1071 = and(io.in.d.ready, io.in.d.valid) node _T_1072 = and(_T_1071, d_first_2) node _T_1073 = and(_T_1072, UInt<1>(0h1)) node _T_1074 = and(_T_1073, d_release_ack_1) when _T_1074 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1075 = and(io.in.d.valid, d_first_2) node _T_1076 = and(_T_1075, UInt<1>(0h1)) node _T_1077 = and(_T_1076, d_release_ack_1) when _T_1077 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1078 = dshr(inflight_1, io.in.d.bits.source) node _T_1079 = bits(_T_1078, 0, 0) node _T_1080 = or(_T_1079, same_cycle_resp_1) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1084 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_109 else : node _T_1088 = eq(io.in.d.bits.size, c_size_lookup) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_110 node _T_1092 = and(io.in.d.valid, d_first_2) node _T_1093 = and(_T_1092, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1094 = and(_T_1093, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1095 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1096 = and(_T_1094, _T_1095) node _T_1097 = and(_T_1096, d_release_ack_1) node _T_1098 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1099 = and(_T_1097, _T_1098) when _T_1099 : node _T_1100 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1101 = or(_T_1100, _WIRE_23.ready) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_111 node _T_1105 = orr(c_set_wo_ready) when _T_1105 : node _T_1106 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_11 node _T_1110 = orr(inflight_1) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) node _T_1112 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1113 = or(_T_1111, _T_1112) node _T_1114 = lt(watchdog_1, plusarg_reader_1.out) node _T_1115 = or(_T_1113, _T_1114) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1119 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1120 = and(io.in.d.ready, io.in.d.valid) node _T_1121 = or(_T_1119, _T_1120) when _T_1121 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_5( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1048 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1048; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1048; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1121 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1121; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1121; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1121; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_974 = _T_1048 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_974 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_974 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_974 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_974 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_974 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1020 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1020 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_989 = _T_1121 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_989 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_989 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_989 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1092 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1092 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1074 = _T_1121 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1074 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1074 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1074 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MSHR_5 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h0)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, UInt<1>(0h0), UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, UInt<1>(0h0)) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, UInt<1>(0h0), UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,false,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,false,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,false,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,false,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(_T_81, UInt<1>(0h0)) node _T_83 = asUInt(reset) node _T_84 = eq(_T_83, UInt<1>(0h0)) when _T_84 : node _T_85 = eq(_T_82, UInt<1>(0h0)) when _T_85 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to evicted should be impossible (false,false,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_82, UInt<1>(0h1), "") : assert_12 node _T_86 = eq(before, UInt<3>(0h5)) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to flushed should be impossible (false,false,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_87, UInt<1>(0h1), "") : assert_13 node _T_91 = eq(evict, UInt<3>(0h4)) node _T_92 = eq(_T_91, UInt<1>(0h0)) node _T_93 = asUInt(reset) node _T_94 = eq(_T_93, UInt<1>(0h0)) when _T_94 : node _T_95 = eq(_T_92, UInt<1>(0h0)) when _T_95 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to evicted should be impossible (false,false,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_92, UInt<1>(0h1), "") : assert_14 node _T_96 = eq(before, UInt<3>(0h4)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to flushed should be impossible (false,false,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_97, UInt<1>(0h1), "") : assert_15 node _T_101 = eq(evict, UInt<3>(0h6)) node _T_102 = eq(before, UInt<3>(0h6)) node _T_103 = eq(evict, UInt<2>(0h3)) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to evicted should be impossible (false,false,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_104, UInt<1>(0h1), "") : assert_16 node _T_108 = eq(before, UInt<2>(0h3)) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to flushed should be impossible (false,false,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_109, UInt<1>(0h1), "") : assert_17 node _T_113 = eq(evict, UInt<2>(0h2)) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to evicted should be impossible (false,false,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_114, UInt<1>(0h1), "") : assert_18 node _T_118 = eq(before, UInt<2>(0h2)) node _T_119 = eq(_T_118, UInt<1>(0h0)) node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(_T_119, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to flushed should be impossible (false,false,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_119, UInt<1>(0h1), "") : assert_19 node _T_123 = eq(s_writeback, UInt<1>(0h0)) node _T_124 = and(_T_123, no_wait) node _T_125 = and(_T_124, io.schedule.ready) when _T_125 : node _T_126 = eq(before, UInt<4>(0h8)) node _T_127 = eq(after, UInt<1>(0h1)) node _T_128 = and(_T_126, _T_127) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = asUInt(reset) node _T_131 = eq(_T_130, UInt<1>(0h0)) when _T_131 : node _T_132 = eq(_T_129, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_129, UInt<1>(0h1), "") : assert_20 node _T_133 = eq(before, UInt<4>(0h8)) node _T_134 = eq(after, UInt<1>(0h0)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(_T_135, UInt<1>(0h0)) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_136, UInt<1>(0h1), "") : assert_21 node _T_140 = eq(before, UInt<4>(0h8)) node _T_141 = eq(after, UInt<3>(0h7)) node _T_142 = and(_T_140, _T_141) node _T_143 = eq(before, UInt<4>(0h8)) node _T_144 = eq(after, UInt<3>(0h5)) node _T_145 = and(_T_143, _T_144) node _T_146 = eq(_T_145, UInt<1>(0h0)) node _T_147 = asUInt(reset) node _T_148 = eq(_T_147, UInt<1>(0h0)) when _T_148 : node _T_149 = eq(_T_146, UInt<1>(0h0)) when _T_149 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_146, UInt<1>(0h1), "") : assert_22 node _T_150 = eq(before, UInt<4>(0h8)) node _T_151 = eq(after, UInt<3>(0h4)) node _T_152 = and(_T_150, _T_151) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = asUInt(reset) node _T_155 = eq(_T_154, UInt<1>(0h0)) when _T_155 : node _T_156 = eq(_T_153, UInt<1>(0h0)) when _T_156 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_153, UInt<1>(0h1), "") : assert_23 node _T_157 = eq(before, UInt<4>(0h8)) node _T_158 = eq(after, UInt<3>(0h6)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(before, UInt<4>(0h8)) node _T_161 = eq(after, UInt<2>(0h3)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(_T_162, UInt<1>(0h0)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_163, UInt<1>(0h1), "") : assert_24 node _T_167 = eq(before, UInt<4>(0h8)) node _T_168 = eq(after, UInt<2>(0h2)) node _T_169 = and(_T_167, _T_168) node _T_170 = eq(_T_169, UInt<1>(0h0)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_170, UInt<1>(0h1), "") : assert_25 node _T_174 = eq(before, UInt<1>(0h1)) node _T_175 = eq(after, UInt<4>(0h8)) node _T_176 = and(_T_174, _T_175) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = asUInt(reset) node _T_179 = eq(_T_178, UInt<1>(0h0)) when _T_179 : node _T_180 = eq(_T_177, UInt<1>(0h0)) when _T_180 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_177, UInt<1>(0h1), "") : assert_26 node _T_181 = eq(before, UInt<1>(0h1)) node _T_182 = eq(after, UInt<1>(0h0)) node _T_183 = and(_T_181, _T_182) node _T_184 = eq(_T_183, UInt<1>(0h0)) node _T_185 = asUInt(reset) node _T_186 = eq(_T_185, UInt<1>(0h0)) when _T_186 : node _T_187 = eq(_T_184, UInt<1>(0h0)) when _T_187 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_184, UInt<1>(0h1), "") : assert_27 node _T_188 = eq(before, UInt<1>(0h1)) node _T_189 = eq(after, UInt<3>(0h7)) node _T_190 = and(_T_188, _T_189) node _T_191 = eq(_T_190, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_191, UInt<1>(0h1), "") : assert_28 node _T_195 = eq(before, UInt<1>(0h1)) node _T_196 = eq(after, UInt<3>(0h5)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = asUInt(reset) node _T_200 = eq(_T_199, UInt<1>(0h0)) when _T_200 : node _T_201 = eq(_T_198, UInt<1>(0h0)) when _T_201 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_198, UInt<1>(0h1), "") : assert_29 node _T_202 = eq(before, UInt<1>(0h1)) node _T_203 = eq(after, UInt<3>(0h4)) node _T_204 = and(_T_202, _T_203) node _T_205 = eq(_T_204, UInt<1>(0h0)) node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(_T_205, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_205, UInt<1>(0h1), "") : assert_30 node _T_209 = eq(before, UInt<1>(0h1)) node _T_210 = eq(after, UInt<3>(0h6)) node _T_211 = and(_T_209, _T_210) node _T_212 = eq(_T_211, UInt<1>(0h0)) node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(_T_212, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_212, UInt<1>(0h1), "") : assert_31 node _T_216 = eq(before, UInt<1>(0h1)) node _T_217 = eq(after, UInt<2>(0h3)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(_T_218, UInt<1>(0h0)) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_219, UInt<1>(0h1), "") : assert_32 node _T_223 = eq(before, UInt<1>(0h1)) node _T_224 = eq(after, UInt<2>(0h2)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(_T_225, UInt<1>(0h0)) node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(_T_226, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_226, UInt<1>(0h1), "") : assert_33 node _T_230 = eq(before, UInt<1>(0h0)) node _T_231 = eq(after, UInt<4>(0h8)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_233, UInt<1>(0h1), "") : assert_34 node _T_237 = eq(before, UInt<1>(0h0)) node _T_238 = eq(after, UInt<1>(0h1)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(_T_239, UInt<1>(0h0)) node _T_241 = asUInt(reset) node _T_242 = eq(_T_241, UInt<1>(0h0)) when _T_242 : node _T_243 = eq(_T_240, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_240, UInt<1>(0h1), "") : assert_35 node _T_244 = eq(before, UInt<1>(0h0)) node _T_245 = eq(after, UInt<3>(0h7)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(_T_246, UInt<1>(0h0)) node _T_248 = asUInt(reset) node _T_249 = eq(_T_248, UInt<1>(0h0)) when _T_249 : node _T_250 = eq(_T_247, UInt<1>(0h0)) when _T_250 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_247, UInt<1>(0h1), "") : assert_36 node _T_251 = eq(before, UInt<1>(0h0)) node _T_252 = eq(after, UInt<3>(0h5)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_254, UInt<1>(0h1), "") : assert_37 node _T_258 = eq(before, UInt<1>(0h0)) node _T_259 = eq(after, UInt<3>(0h6)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(_T_260, UInt<1>(0h0)) node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_T_261, UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_261, UInt<1>(0h1), "") : assert_38 node _T_265 = eq(before, UInt<1>(0h0)) node _T_266 = eq(after, UInt<3>(0h4)) node _T_267 = and(_T_265, _T_266) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_268, UInt<1>(0h1), "") : assert_39 node _T_272 = eq(before, UInt<1>(0h0)) node _T_273 = eq(after, UInt<2>(0h3)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_275, UInt<1>(0h1), "") : assert_40 node _T_279 = eq(before, UInt<1>(0h0)) node _T_280 = eq(after, UInt<2>(0h2)) node _T_281 = and(_T_279, _T_280) node _T_282 = eq(_T_281, UInt<1>(0h0)) node _T_283 = asUInt(reset) node _T_284 = eq(_T_283, UInt<1>(0h0)) when _T_284 : node _T_285 = eq(_T_282, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_282, UInt<1>(0h1), "") : assert_41 node _T_286 = eq(before, UInt<3>(0h7)) node _T_287 = eq(after, UInt<4>(0h8)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = asUInt(reset) node _T_291 = eq(_T_290, UInt<1>(0h0)) when _T_291 : node _T_292 = eq(_T_289, UInt<1>(0h0)) when _T_292 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_289, UInt<1>(0h1), "") : assert_42 node _T_293 = eq(before, UInt<3>(0h7)) node _T_294 = eq(after, UInt<1>(0h1)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(_T_295, UInt<1>(0h0)) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_296, UInt<1>(0h1), "") : assert_43 node _T_300 = eq(before, UInt<3>(0h7)) node _T_301 = eq(after, UInt<1>(0h0)) node _T_302 = and(_T_300, _T_301) node _T_303 = eq(_T_302, UInt<1>(0h0)) node _T_304 = asUInt(reset) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(_T_303, UInt<1>(0h0)) when _T_306 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_303, UInt<1>(0h1), "") : assert_44 node _T_307 = eq(before, UInt<3>(0h7)) node _T_308 = eq(after, UInt<3>(0h5)) node _T_309 = and(_T_307, _T_308) node _T_310 = eq(_T_309, UInt<1>(0h0)) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_310, UInt<1>(0h1), "") : assert_45 node _T_314 = eq(before, UInt<3>(0h7)) node _T_315 = eq(after, UInt<3>(0h6)) node _T_316 = and(_T_314, _T_315) node _T_317 = eq(before, UInt<3>(0h7)) node _T_318 = eq(after, UInt<3>(0h4)) node _T_319 = and(_T_317, _T_318) node _T_320 = eq(_T_319, UInt<1>(0h0)) node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(_T_320, UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_320, UInt<1>(0h1), "") : assert_46 node _T_324 = eq(before, UInt<3>(0h7)) node _T_325 = eq(after, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(_T_326, UInt<1>(0h0)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_327, UInt<1>(0h1), "") : assert_47 node _T_331 = eq(before, UInt<3>(0h7)) node _T_332 = eq(after, UInt<2>(0h2)) node _T_333 = and(_T_331, _T_332) node _T_334 = eq(_T_333, UInt<1>(0h0)) node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_T_334, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_334, UInt<1>(0h1), "") : assert_48 node _T_338 = eq(before, UInt<3>(0h5)) node _T_339 = eq(after, UInt<4>(0h8)) node _T_340 = and(_T_338, _T_339) node _T_341 = eq(_T_340, UInt<1>(0h0)) node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : node _T_344 = eq(_T_341, UInt<1>(0h0)) when _T_344 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_341, UInt<1>(0h1), "") : assert_49 node _T_345 = eq(before, UInt<3>(0h5)) node _T_346 = eq(after, UInt<1>(0h1)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(_T_347, UInt<1>(0h0)) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_348, UInt<1>(0h1), "") : assert_50 node _T_352 = eq(before, UInt<3>(0h5)) node _T_353 = eq(after, UInt<1>(0h0)) node _T_354 = and(_T_352, _T_353) node _T_355 = eq(_T_354, UInt<1>(0h0)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_355, UInt<1>(0h1), "") : assert_51 node _T_359 = eq(before, UInt<3>(0h5)) node _T_360 = eq(after, UInt<3>(0h7)) node _T_361 = and(_T_359, _T_360) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_362, UInt<1>(0h1), "") : assert_52 node _T_366 = eq(before, UInt<3>(0h5)) node _T_367 = eq(after, UInt<3>(0h6)) node _T_368 = and(_T_366, _T_367) node _T_369 = eq(_T_368, UInt<1>(0h0)) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_D should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_369, UInt<1>(0h1), "") : assert_53 node _T_373 = eq(before, UInt<3>(0h5)) node _T_374 = eq(after, UInt<3>(0h4)) node _T_375 = and(_T_373, _T_374) node _T_376 = eq(_T_375, UInt<1>(0h0)) node _T_377 = asUInt(reset) node _T_378 = eq(_T_377, UInt<1>(0h0)) when _T_378 : node _T_379 = eq(_T_376, UInt<1>(0h0)) when _T_379 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_376, UInt<1>(0h1), "") : assert_54 node _T_380 = eq(before, UInt<3>(0h5)) node _T_381 = eq(after, UInt<2>(0h3)) node _T_382 = and(_T_380, _T_381) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_383, UInt<1>(0h1), "") : assert_55 node _T_387 = eq(before, UInt<3>(0h5)) node _T_388 = eq(after, UInt<2>(0h2)) node _T_389 = and(_T_387, _T_388) node _T_390 = eq(_T_389, UInt<1>(0h0)) node _T_391 = asUInt(reset) node _T_392 = eq(_T_391, UInt<1>(0h0)) when _T_392 : node _T_393 = eq(_T_390, UInt<1>(0h0)) when _T_393 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_390, UInt<1>(0h1), "") : assert_56 node _T_394 = eq(before, UInt<3>(0h6)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_397, UInt<1>(0h1), "") : assert_57 node _T_401 = eq(before, UInt<3>(0h6)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_404, UInt<1>(0h1), "") : assert_58 node _T_408 = eq(before, UInt<3>(0h6)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_411, UInt<1>(0h1), "") : assert_59 node _T_415 = eq(before, UInt<3>(0h6)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_418, UInt<1>(0h1), "") : assert_60 node _T_422 = eq(before, UInt<3>(0h6)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_425, UInt<1>(0h1), "") : assert_61 node _T_429 = eq(before, UInt<3>(0h6)) node _T_430 = eq(after, UInt<3>(0h4)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(_T_431, UInt<1>(0h0)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_432, UInt<1>(0h1), "") : assert_62 node _T_436 = eq(before, UInt<3>(0h6)) node _T_437 = eq(after, UInt<2>(0h3)) node _T_438 = and(_T_436, _T_437) node _T_439 = eq(_T_438, UInt<1>(0h0)) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_439, UInt<1>(0h1), "") : assert_63 node _T_443 = eq(before, UInt<3>(0h6)) node _T_444 = eq(after, UInt<2>(0h2)) node _T_445 = and(_T_443, _T_444) node _T_446 = eq(_T_445, UInt<1>(0h0)) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_446, UInt<1>(0h1), "") : assert_64 node _T_450 = eq(before, UInt<3>(0h4)) node _T_451 = eq(after, UInt<4>(0h8)) node _T_452 = and(_T_450, _T_451) node _T_453 = eq(_T_452, UInt<1>(0h0)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_453, UInt<1>(0h1), "") : assert_65 node _T_457 = eq(before, UInt<3>(0h4)) node _T_458 = eq(after, UInt<1>(0h1)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(_T_459, UInt<1>(0h0)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_460, UInt<1>(0h1), "") : assert_66 node _T_464 = eq(before, UInt<3>(0h4)) node _T_465 = eq(after, UInt<1>(0h0)) node _T_466 = and(_T_464, _T_465) node _T_467 = eq(_T_466, UInt<1>(0h0)) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_467, UInt<1>(0h1), "") : assert_67 node _T_471 = eq(before, UInt<3>(0h4)) node _T_472 = eq(after, UInt<3>(0h7)) node _T_473 = and(_T_471, _T_472) node _T_474 = eq(_T_473, UInt<1>(0h0)) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_68 assert(clock, _T_474, UInt<1>(0h1), "") : assert_68 node _T_478 = eq(before, UInt<3>(0h4)) node _T_479 = eq(after, UInt<3>(0h5)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_69 assert(clock, _T_481, UInt<1>(0h1), "") : assert_69 node _T_485 = eq(before, UInt<3>(0h4)) node _T_486 = eq(after, UInt<3>(0h6)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_D should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_70 assert(clock, _T_488, UInt<1>(0h1), "") : assert_70 node _T_492 = eq(before, UInt<3>(0h4)) node _T_493 = eq(after, UInt<2>(0h3)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_71 assert(clock, _T_495, UInt<1>(0h1), "") : assert_71 node _T_499 = eq(before, UInt<3>(0h4)) node _T_500 = eq(after, UInt<2>(0h2)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_72 assert(clock, _T_502, UInt<1>(0h1), "") : assert_72 node _T_506 = eq(before, UInt<2>(0h3)) node _T_507 = eq(after, UInt<4>(0h8)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_73 assert(clock, _T_509, UInt<1>(0h1), "") : assert_73 node _T_513 = eq(before, UInt<2>(0h3)) node _T_514 = eq(after, UInt<1>(0h1)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(_T_515, UInt<1>(0h0)) node _T_517 = asUInt(reset) node _T_518 = eq(_T_517, UInt<1>(0h0)) when _T_518 : node _T_519 = eq(_T_516, UInt<1>(0h0)) when _T_519 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_74 assert(clock, _T_516, UInt<1>(0h1), "") : assert_74 node _T_520 = eq(before, UInt<2>(0h3)) node _T_521 = eq(after, UInt<1>(0h0)) node _T_522 = and(_T_520, _T_521) node _T_523 = eq(_T_522, UInt<1>(0h0)) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_75 assert(clock, _T_523, UInt<1>(0h1), "") : assert_75 node _T_527 = eq(before, UInt<2>(0h3)) node _T_528 = eq(after, UInt<3>(0h7)) node _T_529 = and(_T_527, _T_528) node _T_530 = eq(_T_529, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_TIP should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_76 assert(clock, _T_530, UInt<1>(0h1), "") : assert_76 node _T_534 = eq(before, UInt<2>(0h3)) node _T_535 = eq(after, UInt<3>(0h5)) node _T_536 = and(_T_534, _T_535) node _T_537 = eq(_T_536, UInt<1>(0h0)) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_77 assert(clock, _T_537, UInt<1>(0h1), "") : assert_77 node _T_541 = eq(before, UInt<2>(0h3)) node _T_542 = eq(after, UInt<3>(0h6)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(_T_543, UInt<1>(0h0)) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_TIP_D should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_78 assert(clock, _T_544, UInt<1>(0h1), "") : assert_78 node _T_548 = eq(before, UInt<2>(0h3)) node _T_549 = eq(after, UInt<3>(0h4)) node _T_550 = and(_T_548, _T_549) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_79 assert(clock, _T_551, UInt<1>(0h1), "") : assert_79 node _T_555 = eq(before, UInt<2>(0h3)) node _T_556 = eq(after, UInt<2>(0h2)) node _T_557 = and(_T_555, _T_556) node _T_558 = eq(_T_557, UInt<1>(0h0)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_80 assert(clock, _T_558, UInt<1>(0h1), "") : assert_80 node _T_562 = eq(before, UInt<2>(0h2)) node _T_563 = eq(after, UInt<4>(0h8)) node _T_564 = and(_T_562, _T_563) node _T_565 = eq(_T_564, UInt<1>(0h0)) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_81 assert(clock, _T_565, UInt<1>(0h1), "") : assert_81 node _T_569 = eq(before, UInt<2>(0h2)) node _T_570 = eq(after, UInt<1>(0h1)) node _T_571 = and(_T_569, _T_570) node _T_572 = eq(_T_571, UInt<1>(0h0)) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_82 assert(clock, _T_572, UInt<1>(0h1), "") : assert_82 node _T_576 = eq(before, UInt<2>(0h2)) node _T_577 = eq(after, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) node _T_579 = eq(_T_578, UInt<1>(0h0)) node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(_T_579, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_83 assert(clock, _T_579, UInt<1>(0h1), "") : assert_83 node _T_583 = eq(before, UInt<2>(0h2)) node _T_584 = eq(after, UInt<3>(0h7)) node _T_585 = and(_T_583, _T_584) node _T_586 = eq(_T_585, UInt<1>(0h0)) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_84 assert(clock, _T_586, UInt<1>(0h1), "") : assert_84 node _T_590 = eq(before, UInt<2>(0h2)) node _T_591 = eq(after, UInt<3>(0h5)) node _T_592 = and(_T_590, _T_591) node _T_593 = eq(_T_592, UInt<1>(0h0)) node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(_T_593, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_85 assert(clock, _T_593, UInt<1>(0h1), "") : assert_85 node _T_597 = eq(before, UInt<2>(0h2)) node _T_598 = eq(after, UInt<3>(0h6)) node _T_599 = and(_T_597, _T_598) node _T_600 = eq(_T_599, UInt<1>(0h0)) node _T_601 = asUInt(reset) node _T_602 = eq(_T_601, UInt<1>(0h0)) when _T_602 : node _T_603 = eq(_T_600, UInt<1>(0h0)) when _T_603 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_D should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_86 assert(clock, _T_600, UInt<1>(0h1), "") : assert_86 node _T_604 = eq(before, UInt<2>(0h2)) node _T_605 = eq(after, UInt<3>(0h4)) node _T_606 = and(_T_604, _T_605) node _T_607 = eq(_T_606, UInt<1>(0h0)) node _T_608 = asUInt(reset) node _T_609 = eq(_T_608, UInt<1>(0h0)) when _T_609 : node _T_610 = eq(_T_607, UInt<1>(0h0)) when _T_610 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_87 assert(clock, _T_607, UInt<1>(0h1), "") : assert_87 node _T_611 = eq(before, UInt<2>(0h2)) node _T_612 = eq(after, UInt<2>(0h3)) node _T_613 = and(_T_611, _T_612) node _T_614 = eq(_T_613, UInt<1>(0h0)) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_88 assert(clock, _T_614, UInt<1>(0h1), "") : assert_88 node _last_probe_T = or(probes_done, UInt<1>(0h0)) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkd.valid : node _T_618 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_619 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_620 = or(_T_618, _T_619) when _T_620 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_621 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_622 = eq(request.offset, UInt<1>(0h0)) node _T_623 = and(_T_621, _T_622) node _T_624 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_625 = neq(request.offset, UInt<1>(0h0)) node _T_626 = and(_T_624, _T_625) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_627 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_627 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, UInt<1>(0h0), UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_628 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_628 : node _T_629 = eq(prior, UInt<4>(0h8)) node _T_630 = eq(prior, UInt<1>(0h1)) node _T_631 = eq(_T_630, UInt<1>(0h0)) node _T_632 = asUInt(reset) node _T_633 = eq(_T_632, UInt<1>(0h0)) when _T_633 : node _T_634 = eq(_T_631, UInt<1>(0h0)) when _T_634 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_89 assert(clock, _T_631, UInt<1>(0h1), "") : assert_89 node _T_635 = eq(prior, UInt<1>(0h0)) node _T_636 = eq(_T_635, UInt<1>(0h0)) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_90 assert(clock, _T_636, UInt<1>(0h1), "") : assert_90 node _T_640 = eq(prior, UInt<3>(0h7)) node _T_641 = eq(prior, UInt<3>(0h5)) node _T_642 = eq(_T_641, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_91 assert(clock, _T_642, UInt<1>(0h1), "") : assert_91 node _T_646 = eq(prior, UInt<3>(0h4)) node _T_647 = eq(_T_646, UInt<1>(0h0)) node _T_648 = asUInt(reset) node _T_649 = eq(_T_648, UInt<1>(0h0)) when _T_649 : node _T_650 = eq(_T_647, UInt<1>(0h0)) when _T_650 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_92 assert(clock, _T_647, UInt<1>(0h1), "") : assert_92 node _T_651 = eq(prior, UInt<3>(0h6)) node _T_652 = eq(prior, UInt<2>(0h3)) node _T_653 = eq(_T_652, UInt<1>(0h0)) node _T_654 = asUInt(reset) node _T_655 = eq(_T_654, UInt<1>(0h0)) when _T_655 : node _T_656 = eq(_T_653, UInt<1>(0h0)) when _T_656 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_93 assert(clock, _T_653, UInt<1>(0h1), "") : assert_93 node _T_657 = eq(prior, UInt<2>(0h2)) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = asUInt(reset) node _T_660 = eq(_T_659, UInt<1>(0h0)) when _T_660 : node _T_661 = eq(_T_658, UInt<1>(0h0)) when _T_661 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_94 assert(clock, _T_658, UInt<1>(0h1), "") : assert_94 when io.allocate.valid : node _T_662 = eq(request_valid, UInt<1>(0h0)) node _T_663 = and(io.schedule.ready, io.schedule.valid) node _T_664 = and(no_wait, _T_663) node _T_665 = or(_T_662, _T_664) node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_T_665, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_95 assert(clock, _T_665, UInt<1>(0h1), "") : assert_95 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_669 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_670 = or(io.directory.valid, _T_669) when _T_670 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_671 = and(new_request.prio[2], UInt<1>(0h0)) when _T_671 : connect s_execute, UInt<1>(0h0) node _T_672 = bits(new_request.opcode, 0, 0) node _T_673 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_674 = and(_T_672, _T_673) when _T_674 : connect s_writeback, UInt<1>(0h0) node _T_675 = eq(new_request.param, UInt<3>(0h0)) node _T_676 = eq(new_request.param, UInt<3>(0h4)) node _T_677 = or(_T_675, _T_676) node _T_678 = eq(new_meta.state, UInt<2>(0h2)) node _T_679 = and(_T_677, _T_678) when _T_679 : connect s_writeback, UInt<1>(0h0) node _T_680 = eq(new_request.param, UInt<3>(0h1)) node _T_681 = eq(new_request.param, UInt<3>(0h2)) node _T_682 = or(_T_680, _T_681) node _T_683 = eq(new_request.param, UInt<3>(0h5)) node _T_684 = or(_T_682, _T_683) node _T_685 = and(new_meta.clients, UInt<1>(0h0)) node _T_686 = neq(_T_685, UInt<1>(0h0)) node _T_687 = and(_T_684, _T_686) when _T_687 : connect s_writeback, UInt<1>(0h0) node _T_688 = asUInt(reset) node _T_689 = eq(_T_688, UInt<1>(0h0)) when _T_689 : node _T_690 = eq(new_meta.hit, UInt<1>(0h0)) when _T_690 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_96 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_96 else : node _T_691 = and(new_request.control, UInt<1>(0h1)) when _T_691 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_692 = neq(new_meta.clients, UInt<1>(0h0)) node _T_693 = and(UInt<1>(0h0), _T_692) when _T_693 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_694 = eq(new_meta.hit, UInt<1>(0h0)) node _T_695 = neq(new_meta.state, UInt<2>(0h0)) node _T_696 = and(_T_694, _T_695) when _T_696 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_697 = neq(new_meta.clients, UInt<1>(0h0)) node _T_698 = and(UInt<1>(0h0), _T_697) when _T_698 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_699 = eq(new_meta.hit, UInt<1>(0h0)) node _T_700 = eq(new_meta.state, UInt<2>(0h1)) node _T_701 = and(_T_700, new_needT) node _T_702 = or(_T_699, _T_701) when _T_702 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_703 = eq(new_meta.state, UInt<2>(0h2)) node _T_704 = or(new_needT, _T_703) node _T_705 = and(new_meta.hit, _T_704) node _T_706 = not(new_skipProbe) node _T_707 = and(new_meta.clients, _T_706) node _T_708 = neq(_T_707, UInt<1>(0h0)) node _T_709 = and(_T_705, _T_708) node _T_710 = and(UInt<1>(0h0), _T_709) when _T_710 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_711 = eq(new_request.opcode, UInt<3>(0h6)) node _T_712 = eq(new_request.opcode, UInt<3>(0h7)) node _T_713 = or(_T_711, _T_712) when _T_713 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_714 = bits(new_request.opcode, 2, 2) node _T_715 = eq(_T_714, UInt<1>(0h0)) node _T_716 = and(_T_715, new_meta.hit) node _T_717 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_718 = and(_T_716, _T_717) when _T_718 : connect s_writeback, UInt<1>(0h0)
module MSHR_5( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire io_sinkc_valid = 1'h0; // @[MSHR.scala:84:7] wire io_sinkc_bits_last = 1'h0; // @[MSHR.scala:84:7] wire io_sinkc_bits_data = 1'h0; // @[MSHR.scala:84:7] wire io_sinke_valid = 1'h0; // @[MSHR.scala:84:7] wire _io_status_bits_blockB_T_2 = 1'h0; // @[MSHR.scala:168:62] wire _io_status_bits_blockB_T_4 = 1'h0; // @[MSHR.scala:168:82] wire _io_status_bits_nestC_T = 1'h0; // @[MSHR.scala:173:43] wire _io_status_bits_nestC_T_1 = 1'h0; // @[MSHR.scala:173:64] wire _io_status_bits_nestC_T_2 = 1'h0; // @[MSHR.scala:173:61] wire _io_schedule_bits_b_valid_T = 1'h0; // @[MSHR.scala:185:31] wire _io_schedule_bits_b_valid_T_1 = 1'h0; // @[MSHR.scala:185:44] wire _io_schedule_bits_b_valid_T_2 = 1'h0; // @[MSHR.scala:185:41] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire _final_meta_writeback_clients_T_5 = 1'h0; // @[MSHR.scala:226:56] wire _final_meta_writeback_clients_T_13 = 1'h0; // @[MSHR.scala:246:40] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _honour_BtoT_T = 1'h0; // @[MSHR.scala:276:47] wire _honour_BtoT_T_1 = 1'h0; // @[MSHR.scala:276:64] wire honour_BtoT = 1'h0; // @[MSHR.scala:276:30] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire excluded_client = 1'h0; // @[MSHR.scala:279:28] wire _io_schedule_bits_b_bits_param_T = 1'h0; // @[MSHR.scala:286:42] wire _io_schedule_bits_b_bits_tag_T = 1'h0; // @[MSHR.scala:287:42] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _last_probe_T = 1'h0; // @[MSHR.scala:459:33] wire _probe_toN_T = 1'h0; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = 1'h0; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = 1'h0; // @[Parameters.scala:282:34] wire _probe_toN_T_3 = 1'h0; // @[Parameters.scala:282:75] wire probe_toN = 1'h0; // @[Parameters.scala:282:66] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire new_skipProbe = 1'h0; // @[MSHR.scala:509:26] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _final_meta_writeback_clients_T_6 = 1'h1; // @[MSHR.scala:226:52] wire _final_meta_writeback_clients_T_8 = 1'h1; // @[MSHR.scala:232:54] wire _final_meta_writeback_clients_T_10 = 1'h1; // @[MSHR.scala:245:66] wire _final_meta_writeback_clients_T_15 = 1'h1; // @[MSHR.scala:258:54] wire _io_schedule_bits_b_bits_clients_T = 1'h1; // @[MSHR.scala:289:53] wire _last_probe_T_1 = 1'h1; // @[MSHR.scala:459:66] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set = 10'h0; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag = 13'h0; // @[MSHR.scala:84:7] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [5:0] io_sinkc_bits_source = 6'h0; // @[MSHR.scala:84:7] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = 2'h1; // @[MSHR.scala:301:53] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign _io_schedule_bits_b_bits_tag_T_1 = request_tag; // @[MSHR.scala:98:20, :287:41] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire _final_meta_writeback_clients_T_7 = meta_clients; // @[MSHR.scala:100:17, :226:50] wire _final_meta_writeback_clients_T_9 = meta_clients; // @[MSHR.scala:100:17, :232:52] wire _final_meta_writeback_clients_T_11 = meta_clients; // @[MSHR.scala:100:17, :245:64] wire _final_meta_writeback_clients_T_16 = meta_clients; // @[MSHR.scala:100:17, :258:52] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] wire _no_wait_T = w_releaseack; // @[MSHR.scala:125:33, :183:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1; // @[MSHR.scala:168:{45,59}] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3; // @[MSHR.scala:168:{59,79}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T; // @[MSHR.scala:169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1; // @[MSHR.scala:169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1; // @[MSHR.scala:183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1; // @[MSHR.scala:184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T; // @[MSHR.scala:186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T; // @[MSHR.scala:187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T; // @[MSHR.scala:190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12; // @[MSHR.scala:245:{40,84}] assign final_meta_writeback_tag = request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :228:53, :247:30] assign final_meta_writeback_hit = bad_grant ? meta_hit : ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? 3'h1 : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire last_probe = ~_last_probe_T_2; // @[MSHR.scala:459:{46,64}] wire _w_grant_T = request_offset == 6'h0; // @[MSHR.scala:98:20, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_15 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_15; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_15; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_711 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_711; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_711; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_46 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T
module MulAddRecFNToRaw_postMul_e8_s24_46(); // @[MulAddRecFN.scala:169:7] wire [25:0] _sigSum_T_2 = 26'h0; // @[MulAddRecFN.scala:192:16, :193:47] wire [25:0] _sigSum_T_3 = 26'h0; // @[MulAddRecFN.scala:192:16, :193:47] wire [47:0] _sigSum_T_4 = 48'h3FFFFFFFFFFF; // @[MulAddRecFN.scala:196:28] wire [73:0] sigSum_hi = 74'h3FFFFFFFFFFF; // @[MulAddRecFN.scala:192:12] wire [74:0] sigSum = 75'h7FFFFFFFFFFF; // @[MulAddRecFN.scala:192:12] wire [10:0] _CDom_sExp_T_1 = 11'h102; // @[MulAddRecFN.scala:203:43] wire [9:0] _CDom_sExp_T_2 = 10'h102; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = 10'h102; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = 50'h3FFFFF; // @[MulAddRecFN.scala:206:20] wire [2:0] _CDom_absSigSum_T_3 = 3'h3; // @[MulAddRecFN.scala:207:22] wire [46:0] _CDom_absSigSum_T_4 = 47'h1FFFFF; // @[MulAddRecFN.scala:210:23] wire [49:0] _CDom_absSigSum_T_5 = 50'h18000001FFFFF; // @[MulAddRecFN.scala:209:71] wire [49:0] _CDom_absSigSum_T_1 = 50'h3FFFFFFC00000; // @[MulAddRecFN.scala:205:12, :206:13] wire [49:0] CDom_absSigSum = 50'h3FFFFFFC00000; // @[MulAddRecFN.scala:205:12, :206:13] wire [23:0] _CDom_absSigSumExtra_T = 24'hFFFFFF; // @[MulAddRecFN.scala:215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = 24'h0; // @[MulAddRecFN.scala:215:14] wire [24:0] _CDom_absSigSumExtra_T_3 = 25'h1FFFFFF; // @[MulAddRecFN.scala:216:19] wire [80:0] _CDom_mainSig_T = 81'hFFFFFFF00000000; // @[MulAddRecFN.scala:219:24] wire [28:0] CDom_mainSig = 29'h1FFFF800; // @[MulAddRecFN.scala:219:56] wire [23:0] _CDom_reduced4SigExtra_T = 24'hC00000; // @[MulAddRecFN.scala:222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = 27'h6000000; // @[MulAddRecFN.scala:222:53] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = 3'h6; // @[primitives.scala:123:15] wire [3:0] CDom_reduced4SigExtra_hi = 4'h8; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = 7'h40; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = 3'h2; // @[MulAddRecFN.scala:223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = 3'h5; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = 9'h1F8; // @[primitives.scala:76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = 6'h3C; // @[primitives.scala:78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = 4'hC; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = 4'h3; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = 6'hF; // @[primitives.scala:77:20] wire [25:0] _CDom_sig_T = 26'h3FFFF00; // @[MulAddRecFN.scala:225:25] wire [26:0] CDom_sig = 27'h7FFFE00; // @[MulAddRecFN.scala:225:12] wire [50:0] _notCDom_absSigSum_T_1 = 51'h7800000000000; // @[MulAddRecFN.scala:235:13] wire [50:0] _notCDom_absSigSum_T = 51'h7FFFFFFFFFFF; // @[MulAddRecFN.scala:235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_2 = 51'h7FFFFFFFFFFF; // @[MulAddRecFN.scala:235:20, :236:19] wire [51:0] _notCDom_absSigSum_T_3 = 52'h800000000000; // @[MulAddRecFN.scala:236:41] wire [50:0] _notCDom_absSigSum_T_4 = 51'h800000000000; // @[MulAddRecFN.scala:234:12, :236:41] wire [50:0] notCDom_absSigSum = 51'h800000000000; // @[MulAddRecFN.scala:234:12, :236:41] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = 6'h0; // @[primitives.scala:107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = 6'h0; // @[primitives.scala:107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = 4'h2; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = 7'h10; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = 13'h400; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = 26'h800000; // @[primitives.scala:107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = 5'h19; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = 5'h2; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = 5'h2; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = 5'h2; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = 6'h4; // @[MulAddRecFN.scala:240:56] wire [6:0] _notCDom_sExp_T = 7'h4; // @[MulAddRecFN.scala:241:76] wire [10:0] _notCDom_sExp_T_1 = 11'hFF; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = 114'h8000000000000; // @[MulAddRecFN.scala:243:27] wire [28:0] notCDom_mainSig = 29'h10000000; // @[MulAddRecFN.scala:243:50] wire [12:0] notCDom_reduced2AbsSigSum_lo = 13'h0; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T = 13'h0; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = 13'h0; // @[primitives.scala:107:20] wire [1:0] CDom_reduced4SigExtra_lo_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _CDom_reduced4SigExtra_T_7 = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] notCDom_reduced4SigExtra_lo_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:107:20, :120:33] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:107:20, :120:33] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:107:20, :120:33] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:107:20, :120:33] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:107:20, :120:33] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:107:20, :120:33] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = 4'h0; // @[primitives.scala:107:20, :120:33] wire [3:0] notCDom_reduced4SigExtra_hi = 4'h0; // @[primitives.scala:107:20, :120:33] wire [3:0] _notCDom_reduced4SigExtra_T_3 = 4'h1; // @[MulAddRecFN.scala:248:46] wire [16:0] notCDom_reduced4SigExtra_shift = 17'h1FFFC; // @[primitives.scala:76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = 6'h3E; // @[primitives.scala:78:22] wire [3:0] _notCDom_reduced4SigExtra_T_4 = 4'hE; // @[primitives.scala:52:21, :77:20] wire [3:0] _notCDom_reduced4SigExtra_T_6 = 4'hE; // @[primitives.scala:52:21, :77:20] wire [1:0] _CDom_sExp_T = 2'h1; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = 2'h1; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = 4'h7; // @[primitives.scala:77:20] wire [1:0] _CDom_absSigSum_T_2 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = 2'h3; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = 6'h1F; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = 7'h0; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = 7'h0; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = 7'h0; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = 7'h0; // @[primitives.scala:107:20] wire [25:0] _notCDom_sig_T = 26'h2000000; // @[MulAddRecFN.scala:251:28] wire [1:0] CDom_reduced4SigExtra_hi_hi = 2'h2; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = 2'h2; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = 2'h2; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_reduced4SigExtra_T_7 = 2'h2; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [1:0] _notCDom_completeCancellation_T = 2'h2; // @[primitives.scala:77:20, :103:33, :107:20, :124:20] wire [26:0] io_rawOut_sig = 27'h4000000; // @[MulAddRecFN.scala:169:7, :172:16, :193:47, :251:12, :294:25] wire [26:0] _sigSum_T_1 = 27'h4000000; // @[MulAddRecFN.scala:169:7, :172:16, :193:47, :251:12, :294:25] wire [26:0] notCDom_sig = 27'h4000000; // @[MulAddRecFN.scala:169:7, :172:16, :193:47, :251:12, :294:25] wire [26:0] _io_rawOut_sig_T = 27'h4000000; // @[MulAddRecFN.scala:169:7, :172:16, :193:47, :251:12, :294:25] wire [9:0] io_rawOut_sExp = 10'hFF; // @[MulAddRecFN.scala:169:7, :172:16, :241:46, :293:26] wire [9:0] _notCDom_sExp_T_2 = 10'hFF; // @[MulAddRecFN.scala:169:7, :172:16, :241:46, :293:26] wire [9:0] notCDom_sExp = 10'hFF; // @[MulAddRecFN.scala:169:7, :172:16, :241:46, :293:26] wire [9:0] _io_rawOut_sExp_T = 10'hFF; // @[MulAddRecFN.scala:169:7, :172:16, :241:46, :293:26] wire [2:0] io_roundingMode = 3'h0; // @[primitives.scala:107:20, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = 3'h0; // @[primitives.scala:107:20, :124:20] wire [2:0] _CDom_sig_T_1 = 3'h0; // @[primitives.scala:107:20, :124:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = 3'h0; // @[primitives.scala:107:20, :124:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = 3'h0; // @[primitives.scala:107:20, :124:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = 3'h0; // @[primitives.scala:107:20, :124:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = 3'h0; // @[primitives.scala:107:20, :124:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = 3'h0; // @[primitives.scala:107:20, :124:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = 3'h0; // @[primitives.scala:107:20, :124:20] wire [2:0] notCDom_reduced4SigExtra_lo = 3'h0; // @[primitives.scala:107:20, :124:20] wire [2:0] _notCDom_sig_T_1 = 3'h0; // @[primitives.scala:107:20, :124:20] wire [48:0] io_mulAddResult = 49'h13FFFFFFFFFFF; // @[MulAddRecFN.scala:169:7, :172:16] wire [25:0] io_fromPreMul_highAlignedSigC = 26'h3FFFFFF; // @[MulAddRecFN.scala:169:7, :172:16] wire [4:0] io_fromPreMul_CDom_CAlignDist = 5'hA; // @[MulAddRecFN.scala:169:7, :172:16] wire [9:0] io_fromPreMul_sExpSum = 10'h103; // @[MulAddRecFN.scala:169:7, :172:16] wire io_fromPreMul_signProd = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire io_fromPreMul_isZeroC = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire io_fromPreMul_doSubMags = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire io_fromPreMul_bit0AlignedSigC = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire io_rawOut_sign = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _sigSum_T = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _CDom_absSigSumExtra_T_4 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire CDom_reduced4SigExtra_reducedVec_6 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _CDom_reduced4SigExtra_reducedVec_6_T_1 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _CDom_reduced4SigExtra_T_12 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _CDom_reduced4SigExtra_T_13 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _CDom_reduced4SigExtra_T_17 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _CDom_reduced4SigExtra_T_18 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire notCDom_reduced2AbsSigSum_reducedVec_23 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _notCDom_normDistReduced2_T_23 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _notCDom_reduced4SigExtra_T_9 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _notCDom_reduced4SigExtra_T_12 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _notCDom_reduced4SigExtra_T_13 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _notCDom_reduced4SigExtra_T_17 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _notCDom_reduced4SigExtra_T_18 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _notCDom_sign_T = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire notCDom_sign = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _io_invalidExc_T_4 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _io_rawOut_isZero_T = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _io_rawOut_sign_T_3 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _io_rawOut_sign_T_9 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _io_rawOut_sign_T_12 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _io_rawOut_sign_T_13 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _io_rawOut_sign_T_14 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _io_rawOut_sign_T_15 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _io_rawOut_sign_T_16 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire _io_rawOut_sign_T_17 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57] wire io_fromPreMul_isSigNaNAny = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire io_fromPreMul_isNaNAOrB = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire io_fromPreMul_isInfA = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire io_fromPreMul_isZeroA = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire io_fromPreMul_isInfB = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire io_fromPreMul_isZeroB = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire io_fromPreMul_isNaNC = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire io_fromPreMul_isInfC = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire io_fromPreMul_CIsDominant = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire io_invalidExc = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire io_rawOut_isNaN = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire io_rawOut_isInf = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire io_rawOut_isZero = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire roundingMode_min = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire opSignC = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _CDom_absSigSumExtra_T_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire CDom_absSigSumExtra = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire CDom_reduced4SigExtra_reducedVec_0 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire CDom_reduced4SigExtra_reducedVec_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire CDom_reduced4SigExtra_reducedVec_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire CDom_reduced4SigExtra_reducedVec_3 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire CDom_reduced4SigExtra_reducedVec_4 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire CDom_reduced4SigExtra_reducedVec_5 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _CDom_reduced4SigExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _CDom_reduced4SigExtra_T_8 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _CDom_reduced4SigExtra_T_9 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire CDom_reduced4SigExtra = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _CDom_sig_T_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _CDom_sig_T_3 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _CDom_sig_T_4 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_signSigSum = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_0 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_3 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_4 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_5 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_6 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_7 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_8 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_9 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_10 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_11 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_12 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_13 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_14 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_15 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_16 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_17 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_18 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_19 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_20 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_21 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_22 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_24 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced2AbsSigSum_reducedVec_25 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_3 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_4 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_5 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_6 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_7 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_8 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_9 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_10 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_11 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_12 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_13 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_14 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_15 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_16 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_17 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_18 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_19 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_20 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_21 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_22 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_24 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_normDistReduced2_T_25 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced4SigExtra_reducedVec_0 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced4SigExtra_reducedVec_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced4SigExtra_reducedVec_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced4SigExtra_reducedVec_3 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced4SigExtra_reducedVec_4 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced4SigExtra_reducedVec_5 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced4SigExtra_reducedVec_6 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_reduced4SigExtra_T_8 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_reduced4SigExtra = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_sig_T_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notCDom_sig_T_3 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notCDom_completeCancellation = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notNaN_isInfProd = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notNaN_isInfOut = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _notNaN_addZeros_T = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire notNaN_addZeros = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_invalidExc_T = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_invalidExc_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_invalidExc_T_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_invalidExc_T_3 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_invalidExc_T_5 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_invalidExc_T_6 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_invalidExc_T_7 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_invalidExc_T_8 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_invalidExc_T_9 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_rawOut_isNaN_T = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_rawOut_isZero_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_rawOut_isZero_T_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_rawOut_sign_T = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_rawOut_sign_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_rawOut_sign_T_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_rawOut_sign_T_4 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_rawOut_sign_T_5 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_rawOut_sign_T_6 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_rawOut_sign_T_7 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_rawOut_sign_T_8 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_rawOut_sign_T_10 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] wire _io_rawOut_sign_T_11 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PLICClockSinkDomain : output auto : { flip plic_int_in : UInt<1>[1], flip plic_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out_15 : { sync : UInt<1>[1]}, int_in_clock_xing_out_14 : { sync : UInt<1>[1]}, int_in_clock_xing_out_13 : { sync : UInt<1>[1]}, int_in_clock_xing_out_12 : { sync : UInt<1>[1]}, int_in_clock_xing_out_11 : { sync : UInt<1>[1]}, int_in_clock_xing_out_10 : { sync : UInt<1>[1]}, int_in_clock_xing_out_9 : { sync : UInt<1>[1]}, int_in_clock_xing_out_8 : { sync : UInt<1>[1]}, int_in_clock_xing_out_7 : { sync : UInt<1>[1]}, int_in_clock_xing_out_6 : { sync : UInt<1>[1]}, int_in_clock_xing_out_5 : { sync : UInt<1>[1]}, int_in_clock_xing_out_4 : { sync : UInt<1>[1]}, int_in_clock_xing_out_3 : { sync : UInt<1>[1]}, int_in_clock_xing_out_2 : { sync : UInt<1>[1]}, int_in_clock_xing_out_1 : { sync : UInt<1>[1]}, int_in_clock_xing_out_0 : { sync : UInt<1>[1]}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst plic of TLPLIC connect plic.clock, childClock connect plic.reset, childReset inst intsource of IntSyncCrossingSource_n1x1_40 connect intsource.clock, childClock connect intsource.reset, childReset inst intsource_1 of IntSyncCrossingSource_n1x1_41 connect intsource_1.clock, childClock connect intsource_1.reset, childReset inst intsource_2 of IntSyncCrossingSource_n1x1_42 connect intsource_2.clock, childClock connect intsource_2.reset, childReset inst intsource_3 of IntSyncCrossingSource_n1x1_43 connect intsource_3.clock, childClock connect intsource_3.reset, childReset inst intsource_4 of IntSyncCrossingSource_n1x1_44 connect intsource_4.clock, childClock connect intsource_4.reset, childReset inst intsource_5 of IntSyncCrossingSource_n1x1_45 connect intsource_5.clock, childClock connect intsource_5.reset, childReset inst intsource_6 of IntSyncCrossingSource_n1x1_46 connect intsource_6.clock, childClock connect intsource_6.reset, childReset inst intsource_7 of IntSyncCrossingSource_n1x1_47 connect intsource_7.clock, childClock connect intsource_7.reset, childReset inst intsource_8 of IntSyncCrossingSource_n1x1_48 connect intsource_8.clock, childClock connect intsource_8.reset, childReset inst intsource_9 of IntSyncCrossingSource_n1x1_49 connect intsource_9.clock, childClock connect intsource_9.reset, childReset inst intsource_10 of IntSyncCrossingSource_n1x1_50 connect intsource_10.clock, childClock connect intsource_10.reset, childReset inst intsource_11 of IntSyncCrossingSource_n1x1_51 connect intsource_11.clock, childClock connect intsource_11.reset, childReset inst intsource_12 of IntSyncCrossingSource_n1x1_52 connect intsource_12.clock, childClock connect intsource_12.reset, childReset inst intsource_13 of IntSyncCrossingSource_n1x1_53 connect intsource_13.clock, childClock connect intsource_13.reset, childReset inst intsource_14 of IntSyncCrossingSource_n1x1_54 connect intsource_14.clock, childClock connect intsource_14.reset, childReset inst intsource_15 of IntSyncCrossingSource_n1x1_55 connect intsource_15.clock, childClock connect intsource_15.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock wire intInClockXingOut : { sync : UInt<1>[1]} invalidate intInClockXingOut.sync[0] wire intInClockXingIn : { sync : UInt<1>[1]} invalidate intInClockXingIn.sync[0] connect intInClockXingOut, intInClockXingIn wire intInClockXingOut_1 : { sync : UInt<1>[1]} invalidate intInClockXingOut_1.sync[0] wire intInClockXingIn_1 : { sync : UInt<1>[1]} invalidate intInClockXingIn_1.sync[0] connect intInClockXingOut_1, intInClockXingIn_1 wire intInClockXingOut_2 : { sync : UInt<1>[1]} invalidate intInClockXingOut_2.sync[0] wire intInClockXingIn_2 : { sync : UInt<1>[1]} invalidate intInClockXingIn_2.sync[0] connect intInClockXingOut_2, intInClockXingIn_2 wire intInClockXingOut_3 : { sync : UInt<1>[1]} invalidate intInClockXingOut_3.sync[0] wire intInClockXingIn_3 : { sync : UInt<1>[1]} invalidate intInClockXingIn_3.sync[0] connect intInClockXingOut_3, intInClockXingIn_3 wire intInClockXingOut_4 : { sync : UInt<1>[1]} invalidate intInClockXingOut_4.sync[0] wire intInClockXingIn_4 : { sync : UInt<1>[1]} invalidate intInClockXingIn_4.sync[0] connect intInClockXingOut_4, intInClockXingIn_4 wire intInClockXingOut_5 : { sync : UInt<1>[1]} invalidate intInClockXingOut_5.sync[0] wire intInClockXingIn_5 : { sync : UInt<1>[1]} invalidate intInClockXingIn_5.sync[0] connect intInClockXingOut_5, intInClockXingIn_5 wire intInClockXingOut_6 : { sync : UInt<1>[1]} invalidate intInClockXingOut_6.sync[0] wire intInClockXingIn_6 : { sync : UInt<1>[1]} invalidate intInClockXingIn_6.sync[0] connect intInClockXingOut_6, intInClockXingIn_6 wire intInClockXingOut_7 : { sync : UInt<1>[1]} invalidate intInClockXingOut_7.sync[0] wire intInClockXingIn_7 : { sync : UInt<1>[1]} invalidate intInClockXingIn_7.sync[0] connect intInClockXingOut_7, intInClockXingIn_7 wire intInClockXingOut_8 : { sync : UInt<1>[1]} invalidate intInClockXingOut_8.sync[0] wire intInClockXingIn_8 : { sync : UInt<1>[1]} invalidate intInClockXingIn_8.sync[0] connect intInClockXingOut_8, intInClockXingIn_8 wire intInClockXingOut_9 : { sync : UInt<1>[1]} invalidate intInClockXingOut_9.sync[0] wire intInClockXingIn_9 : { sync : UInt<1>[1]} invalidate intInClockXingIn_9.sync[0] connect intInClockXingOut_9, intInClockXingIn_9 wire intInClockXingOut_10 : { sync : UInt<1>[1]} invalidate intInClockXingOut_10.sync[0] wire intInClockXingIn_10 : { sync : UInt<1>[1]} invalidate intInClockXingIn_10.sync[0] connect intInClockXingOut_10, intInClockXingIn_10 wire intInClockXingOut_11 : { sync : UInt<1>[1]} invalidate intInClockXingOut_11.sync[0] wire intInClockXingIn_11 : { sync : UInt<1>[1]} invalidate intInClockXingIn_11.sync[0] connect intInClockXingOut_11, intInClockXingIn_11 wire intInClockXingOut_12 : { sync : UInt<1>[1]} invalidate intInClockXingOut_12.sync[0] wire intInClockXingIn_12 : { sync : UInt<1>[1]} invalidate intInClockXingIn_12.sync[0] connect intInClockXingOut_12, intInClockXingIn_12 wire intInClockXingOut_13 : { sync : UInt<1>[1]} invalidate intInClockXingOut_13.sync[0] wire intInClockXingIn_13 : { sync : UInt<1>[1]} invalidate intInClockXingIn_13.sync[0] connect intInClockXingOut_13, intInClockXingIn_13 wire intInClockXingOut_14 : { sync : UInt<1>[1]} invalidate intInClockXingOut_14.sync[0] wire intInClockXingIn_14 : { sync : UInt<1>[1]} invalidate intInClockXingIn_14.sync[0] connect intInClockXingOut_14, intInClockXingIn_14 wire intInClockXingOut_15 : { sync : UInt<1>[1]} invalidate intInClockXingOut_15.sync[0] wire intInClockXingIn_15 : { sync : UInt<1>[1]} invalidate intInClockXingIn_15.sync[0] connect intInClockXingOut_15, intInClockXingIn_15 connect intsource.auto.in[0], plic.auto.int_out_0[0] connect intsource_4.auto.in[0], plic.auto.int_out_1[0] connect intsource_1.auto.in[0], plic.auto.int_out_2[0] connect intsource_5.auto.in[0], plic.auto.int_out_3[0] connect intsource_2.auto.in[0], plic.auto.int_out_4[0] connect intsource_6.auto.in[0], plic.auto.int_out_5[0] connect intsource_3.auto.in[0], plic.auto.int_out_6[0] connect intsource_7.auto.in[0], plic.auto.int_out_7[0] connect intsource_8.auto.in[0], plic.auto.int_out_8[0] connect intsource_12.auto.in[0], plic.auto.int_out_9[0] connect intsource_9.auto.in[0], plic.auto.int_out_10[0] connect intsource_13.auto.in[0], plic.auto.int_out_11[0] connect intsource_10.auto.in[0], plic.auto.int_out_12[0] connect intsource_14.auto.in[0], plic.auto.int_out_13[0] connect intsource_11.auto.in[0], plic.auto.int_out_14[0] connect intsource_15.auto.in[0], plic.auto.int_out_15[0] connect intInClockXingIn, intsource.auto.out connect intInClockXingIn_1, intsource_1.auto.out connect intInClockXingIn_2, intsource_2.auto.out connect intInClockXingIn_3, intsource_3.auto.out connect intInClockXingIn_4, intsource_4.auto.out connect intInClockXingIn_5, intsource_5.auto.out connect intInClockXingIn_6, intsource_6.auto.out connect intInClockXingIn_7, intsource_7.auto.out connect intInClockXingIn_8, intsource_8.auto.out connect intInClockXingIn_9, intsource_9.auto.out connect intInClockXingIn_10, intsource_10.auto.out connect intInClockXingIn_11, intsource_11.auto.out connect intInClockXingIn_12, intsource_12.auto.out connect intInClockXingIn_13, intsource_13.auto.out connect intInClockXingIn_14, intsource_14.auto.out connect intInClockXingIn_15, intsource_15.auto.out connect clockNodeIn, auto.clock_in connect auto.int_in_clock_xing_out_0, intInClockXingOut connect auto.int_in_clock_xing_out_1, intInClockXingOut_1 connect auto.int_in_clock_xing_out_2, intInClockXingOut_2 connect auto.int_in_clock_xing_out_3, intInClockXingOut_3 connect auto.int_in_clock_xing_out_4, intInClockXingOut_4 connect auto.int_in_clock_xing_out_5, intInClockXingOut_5 connect auto.int_in_clock_xing_out_6, intInClockXingOut_6 connect auto.int_in_clock_xing_out_7, intInClockXingOut_7 connect auto.int_in_clock_xing_out_8, intInClockXingOut_8 connect auto.int_in_clock_xing_out_9, intInClockXingOut_9 connect auto.int_in_clock_xing_out_10, intInClockXingOut_10 connect auto.int_in_clock_xing_out_11, intInClockXingOut_11 connect auto.int_in_clock_xing_out_12, intInClockXingOut_12 connect auto.int_in_clock_xing_out_13, intInClockXingOut_13 connect auto.int_in_clock_xing_out_14, intInClockXingOut_14 connect auto.int_in_clock_xing_out_15, intInClockXingOut_15 connect plic.auto.in, auto.plic_in connect plic.auto.int_in[0], auto.plic_int_in[0] connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset extmodule plusarg_reader_158 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_159 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module PLICClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_plic_int_in_0, // @[LazyModuleImp.scala:107:25] output auto_plic_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_plic_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_plic_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_plic_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_plic_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_plic_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_plic_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_plic_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_plic_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_plic_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_plic_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_plic_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_plic_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_plic_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_plic_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_plic_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_15_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_14_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_13_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_12_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_11_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_10_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_9_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_8_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_7_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_6_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_5_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_4_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_3_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_2_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_1_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_0_sync_0, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _plic_auto_int_out_15_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_14_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_13_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_12_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_11_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_10_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_9_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_8_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_7_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_6_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_5_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_4_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_3_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_2_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_1_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_0_0; // @[Plic.scala:367:46] wire auto_plic_int_in_0_0 = auto_plic_int_in_0; // @[ClockDomain.scala:14:9] wire auto_plic_in_a_valid_0 = auto_plic_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_plic_in_a_bits_opcode_0 = auto_plic_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_plic_in_a_bits_param_0 = auto_plic_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [1:0] auto_plic_in_a_bits_size_0 = auto_plic_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_plic_in_a_bits_source_0 = auto_plic_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [27:0] auto_plic_in_a_bits_address_0 = auto_plic_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_plic_in_a_bits_mask_0 = auto_plic_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_plic_in_a_bits_data_0 = auto_plic_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_plic_in_a_bits_corrupt_0 = auto_plic_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_ready_0 = auto_plic_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire [1:0] auto_plic_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire intInClockXingOut_15_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_14_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_13_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_12_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_11_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_10_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_9_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_8_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_7_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_6_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_5_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_4_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_3_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_2_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_plic_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_plic_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_plic_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_plic_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_plic_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_15_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_14_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_13_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_12_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_11_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_10_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_9_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_8_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_7_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_6_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_5_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_4_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_3_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_2_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_1_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_0_sync_0_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] wire intInClockXingIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_0_sync_0_0 = intInClockXingOut_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_1_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_1_sync_0_0 = intInClockXingOut_1_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_2_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_2_sync_0_0 = intInClockXingOut_2_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_2_sync_0 = intInClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_3_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_3_sync_0_0 = intInClockXingOut_3_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_3_sync_0 = intInClockXingIn_3_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_4_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_4_sync_0_0 = intInClockXingOut_4_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_4_sync_0 = intInClockXingIn_4_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_5_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_5_sync_0_0 = intInClockXingOut_5_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_5_sync_0 = intInClockXingIn_5_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_6_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_6_sync_0_0 = intInClockXingOut_6_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_6_sync_0 = intInClockXingIn_6_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_7_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_7_sync_0_0 = intInClockXingOut_7_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_7_sync_0 = intInClockXingIn_7_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_8_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_8_sync_0_0 = intInClockXingOut_8_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_8_sync_0 = intInClockXingIn_8_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_9_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_9_sync_0_0 = intInClockXingOut_9_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_9_sync_0 = intInClockXingIn_9_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_10_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_10_sync_0_0 = intInClockXingOut_10_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_10_sync_0 = intInClockXingIn_10_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_11_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_11_sync_0_0 = intInClockXingOut_11_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_11_sync_0 = intInClockXingIn_11_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_12_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_12_sync_0_0 = intInClockXingOut_12_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_12_sync_0 = intInClockXingIn_12_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_13_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_13_sync_0_0 = intInClockXingOut_13_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_13_sync_0 = intInClockXingIn_13_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_14_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_14_sync_0_0 = intInClockXingOut_14_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_14_sync_0 = intInClockXingIn_14_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_15_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_15_sync_0_0 = intInClockXingOut_15_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_15_sync_0 = intInClockXingIn_15_sync_0; // @[MixedNode.scala:542:17, :551:17] TLPLIC plic ( // @[Plic.scala:367:46] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_int_in_0 (auto_plic_int_in_0_0), // @[ClockDomain.scala:14:9] .auto_int_out_15_0 (_plic_auto_int_out_15_0), .auto_int_out_14_0 (_plic_auto_int_out_14_0), .auto_int_out_13_0 (_plic_auto_int_out_13_0), .auto_int_out_12_0 (_plic_auto_int_out_12_0), .auto_int_out_11_0 (_plic_auto_int_out_11_0), .auto_int_out_10_0 (_plic_auto_int_out_10_0), .auto_int_out_9_0 (_plic_auto_int_out_9_0), .auto_int_out_8_0 (_plic_auto_int_out_8_0), .auto_int_out_7_0 (_plic_auto_int_out_7_0), .auto_int_out_6_0 (_plic_auto_int_out_6_0), .auto_int_out_5_0 (_plic_auto_int_out_5_0), .auto_int_out_4_0 (_plic_auto_int_out_4_0), .auto_int_out_3_0 (_plic_auto_int_out_3_0), .auto_int_out_2_0 (_plic_auto_int_out_2_0), .auto_int_out_1_0 (_plic_auto_int_out_1_0), .auto_int_out_0_0 (_plic_auto_int_out_0_0), .auto_in_a_ready (auto_plic_in_a_ready_0), .auto_in_a_valid (auto_plic_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_opcode (auto_plic_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_param (auto_plic_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_size (auto_plic_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_source (auto_plic_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_address (auto_plic_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_mask (auto_plic_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_data (auto_plic_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_corrupt (auto_plic_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_in_d_ready (auto_plic_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_in_d_valid (auto_plic_in_d_valid_0), .auto_in_d_bits_opcode (auto_plic_in_d_bits_opcode_0), .auto_in_d_bits_size (auto_plic_in_d_bits_size_0), .auto_in_d_bits_source (auto_plic_in_d_bits_source_0), .auto_in_d_bits_data (auto_plic_in_d_bits_data_0) ); // @[Plic.scala:367:46] IntSyncCrossingSource_n1x1_40 intsource ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_0_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_41 intsource_1 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_2_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_1_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_42 intsource_2 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_4_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_2_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_43 intsource_3 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_6_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_3_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_44 intsource_4 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_1_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_4_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_45 intsource_5 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_3_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_5_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_46 intsource_6 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_5_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_6_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_47 intsource_7 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_7_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_7_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_48 intsource_8 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_8_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_8_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_49 intsource_9 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_10_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_9_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_50 intsource_10 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_12_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_10_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_51 intsource_11 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_14_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_11_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_52 intsource_12 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_9_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_12_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_53 intsource_13 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_11_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_13_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_54 intsource_14 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_13_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_14_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_55 intsource_15 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_15_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_15_sync_0) ); // @[Crossing.scala:29:31] assign auto_plic_in_a_ready = auto_plic_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_valid = auto_plic_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_opcode = auto_plic_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_size = auto_plic_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_source = auto_plic_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_data = auto_plic_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_15_sync_0 = auto_int_in_clock_xing_out_15_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_14_sync_0 = auto_int_in_clock_xing_out_14_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_13_sync_0 = auto_int_in_clock_xing_out_13_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_12_sync_0 = auto_int_in_clock_xing_out_12_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_11_sync_0 = auto_int_in_clock_xing_out_11_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_10_sync_0 = auto_int_in_clock_xing_out_10_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_9_sync_0 = auto_int_in_clock_xing_out_9_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_8_sync_0 = auto_int_in_clock_xing_out_8_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_7_sync_0 = auto_int_in_clock_xing_out_7_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_6_sync_0 = auto_int_in_clock_xing_out_6_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_5_sync_0 = auto_int_in_clock_xing_out_5_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_4_sync_0 = auto_int_in_clock_xing_out_4_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_3_sync_0 = auto_int_in_clock_xing_out_3_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_2_sync_0 = auto_int_in_clock_xing_out_2_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_1_sync_0 = auto_int_in_clock_xing_out_1_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_0_sync_0 = auto_int_in_clock_xing_out_0_sync_0_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_138 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_153 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_138( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_153 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_26 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<6>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<4>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<6>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state
module IssueSlot_26( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [5:0] io_spec_ld_wakeup_0_bits = 6'h0; // @[issue-slot.scala:69:7] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_62 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<5>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 2, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 4, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h5)) node mask_sub_sub_sub_sub_size = bits(mask_sizeOH, 4, 4) node mask_sub_sub_sub_sub_bit = bits(io.in.a.bits.address, 4, 4) node mask_sub_sub_sub_sub_nbit = eq(mask_sub_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_nbit) node _mask_sub_sub_sub_sub_acc_T = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_0_2) node mask_sub_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T) node mask_sub_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_bit) node _mask_sub_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_1_2) node mask_sub_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T_1) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_sub_2_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_2_2) node mask_sub_sub_sub_2_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_3_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_3_2) node mask_sub_sub_sub_3_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_sub_4_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size, mask_sub_sub_4_2) node mask_sub_sub_4_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_5_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size, mask_sub_sub_5_2) node mask_sub_sub_5_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_6_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size, mask_sub_sub_6_2) node mask_sub_sub_6_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_7_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size, mask_sub_sub_7_2) node mask_sub_sub_7_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_7) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_sub_8_2 = and(mask_sub_sub_4_2, mask_sub_nbit) node _mask_sub_acc_T_8 = and(mask_sub_size, mask_sub_8_2) node mask_sub_8_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_8) node mask_sub_9_2 = and(mask_sub_sub_4_2, mask_sub_bit) node _mask_sub_acc_T_9 = and(mask_sub_size, mask_sub_9_2) node mask_sub_9_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_9) node mask_sub_10_2 = and(mask_sub_sub_5_2, mask_sub_nbit) node _mask_sub_acc_T_10 = and(mask_sub_size, mask_sub_10_2) node mask_sub_10_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_10) node mask_sub_11_2 = and(mask_sub_sub_5_2, mask_sub_bit) node _mask_sub_acc_T_11 = and(mask_sub_size, mask_sub_11_2) node mask_sub_11_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_11) node mask_sub_12_2 = and(mask_sub_sub_6_2, mask_sub_nbit) node _mask_sub_acc_T_12 = and(mask_sub_size, mask_sub_12_2) node mask_sub_12_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_12) node mask_sub_13_2 = and(mask_sub_sub_6_2, mask_sub_bit) node _mask_sub_acc_T_13 = and(mask_sub_size, mask_sub_13_2) node mask_sub_13_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_13) node mask_sub_14_2 = and(mask_sub_sub_7_2, mask_sub_nbit) node _mask_sub_acc_T_14 = and(mask_sub_size, mask_sub_14_2) node mask_sub_14_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_14) node mask_sub_15_2 = and(mask_sub_sub_7_2, mask_sub_bit) node _mask_sub_acc_T_15 = and(mask_sub_size, mask_sub_15_2) node mask_sub_15_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_15) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_eq_16 = and(mask_sub_8_2, mask_nbit) node _mask_acc_T_16 = and(mask_size, mask_eq_16) node mask_acc_16 = or(mask_sub_8_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_8_2, mask_bit) node _mask_acc_T_17 = and(mask_size, mask_eq_17) node mask_acc_17 = or(mask_sub_8_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_9_2, mask_nbit) node _mask_acc_T_18 = and(mask_size, mask_eq_18) node mask_acc_18 = or(mask_sub_9_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_9_2, mask_bit) node _mask_acc_T_19 = and(mask_size, mask_eq_19) node mask_acc_19 = or(mask_sub_9_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_10_2, mask_nbit) node _mask_acc_T_20 = and(mask_size, mask_eq_20) node mask_acc_20 = or(mask_sub_10_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_10_2, mask_bit) node _mask_acc_T_21 = and(mask_size, mask_eq_21) node mask_acc_21 = or(mask_sub_10_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_11_2, mask_nbit) node _mask_acc_T_22 = and(mask_size, mask_eq_22) node mask_acc_22 = or(mask_sub_11_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_11_2, mask_bit) node _mask_acc_T_23 = and(mask_size, mask_eq_23) node mask_acc_23 = or(mask_sub_11_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_12_2, mask_nbit) node _mask_acc_T_24 = and(mask_size, mask_eq_24) node mask_acc_24 = or(mask_sub_12_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_12_2, mask_bit) node _mask_acc_T_25 = and(mask_size, mask_eq_25) node mask_acc_25 = or(mask_sub_12_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_13_2, mask_nbit) node _mask_acc_T_26 = and(mask_size, mask_eq_26) node mask_acc_26 = or(mask_sub_13_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_13_2, mask_bit) node _mask_acc_T_27 = and(mask_size, mask_eq_27) node mask_acc_27 = or(mask_sub_13_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_14_2, mask_nbit) node _mask_acc_T_28 = and(mask_size, mask_eq_28) node mask_acc_28 = or(mask_sub_14_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_14_2, mask_bit) node _mask_acc_T_29 = and(mask_size, mask_eq_29) node mask_acc_29 = or(mask_sub_14_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_15_2, mask_nbit) node _mask_acc_T_30 = and(mask_size, mask_eq_30) node mask_acc_30 = or(mask_sub_15_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_15_2, mask_bit) node _mask_acc_T_31 = and(mask_size, mask_eq_31) node mask_acc_31 = or(mask_sub_15_1, _mask_acc_T_31) node mask_lo_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo_lo = cat(mask_lo_lo_lo_hi, mask_lo_lo_lo_lo) node mask_lo_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_lo_hi = cat(mask_lo_lo_hi_hi, mask_lo_lo_hi_lo) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_lo_hi_lo = cat(mask_lo_hi_lo_hi, mask_lo_hi_lo_lo) node mask_lo_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_lo_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_lo_hi_hi = cat(mask_lo_hi_hi_hi, mask_lo_hi_hi_lo) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo_lo = cat(mask_acc_17, mask_acc_16) node mask_hi_lo_lo_hi = cat(mask_acc_19, mask_acc_18) node mask_hi_lo_lo = cat(mask_hi_lo_lo_hi, mask_hi_lo_lo_lo) node mask_hi_lo_hi_lo = cat(mask_acc_21, mask_acc_20) node mask_hi_lo_hi_hi = cat(mask_acc_23, mask_acc_22) node mask_hi_lo_hi = cat(mask_hi_lo_hi_hi, mask_hi_lo_hi_lo) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo_lo = cat(mask_acc_25, mask_acc_24) node mask_hi_hi_lo_hi = cat(mask_acc_27, mask_acc_26) node mask_hi_hi_lo = cat(mask_hi_hi_lo_hi, mask_hi_hi_lo_lo) node mask_hi_hi_hi_lo = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_hi = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_hi = cat(mask_hi_hi_hi_hi, mask_hi_hi_hi_lo) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h1f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h1f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<3>(0h5)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_197 = shr(io.in.a.bits.source, 5) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<5>(0h1f)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<3>(0h5)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_374 = shr(io.in.a.bits.source, 5) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<5>(0h1f)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_480 = shr(io.in.a.bits.source, 5) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_582 = shr(io.in.a.bits.source, 5) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_686 = shr(io.in.a.bits.source, 5) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_702, _T_707) node _T_744 = or(_T_743, _T_712) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_722) node _T_747 = or(_T_746, _T_727) node _T_748 = or(_T_747, _T_732) node _T_749 = or(_T_748, _T_737) node _T_750 = or(_T_749, _T_742) node _T_751 = and(_T_697, _T_750) node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = and(_T_752, _T_757) node _T_759 = or(UInt<1>(0h0), _T_751) node _T_760 = or(_T_759, _T_758) node _T_761 = and(_T_693, _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_761, UInt<1>(0h1), "") : assert_36 node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(is_aligned, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_771, UInt<1>(0h1), "") : assert_39 node _T_775 = eq(io.in.a.bits.mask, mask) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_775, UInt<1>(0h1), "") : assert_40 node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_779 : node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_783 = shr(io.in.a.bits.source, 5) node _T_784 = eq(_T_783, UInt<1>(0h0)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_7) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_788 = and(_T_786, _T_787) node _T_789 = and(_T_782, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = or(_T_799, _T_804) node _T_841 = or(_T_840, _T_809) node _T_842 = or(_T_841, _T_814) node _T_843 = or(_T_842, _T_819) node _T_844 = or(_T_843, _T_824) node _T_845 = or(_T_844, _T_829) node _T_846 = or(_T_845, _T_834) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_794, _T_847) node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = and(_T_849, _T_854) node _T_856 = or(UInt<1>(0h0), _T_848) node _T_857 = or(_T_856, _T_855) node _T_858 = and(_T_790, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_858, UInt<1>(0h1), "") : assert_41 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_868, UInt<1>(0h1), "") : assert_44 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_872, UInt<1>(0h1), "") : assert_45 node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_880 = shr(io.in.a.bits.source, 5) node _T_881 = eq(_T_880, UInt<1>(0h0)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_8) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_885 = and(_T_883, _T_884) node _T_886 = and(_T_879, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_943 = and(_T_941, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = or(_T_949, _T_954) node _T_956 = and(_T_944, _T_955) node _T_957 = or(UInt<1>(0h0), _T_897) node _T_958 = or(_T_957, _T_940) node _T_959 = or(_T_958, _T_956) node _T_960 = and(_T_887, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_960, UInt<1>(0h1), "") : assert_46 node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(is_aligned, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_970, UInt<1>(0h1), "") : assert_49 node _T_974 = eq(io.in.a.bits.mask, mask) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_974, UInt<1>(0h1), "") : assert_50 node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_978, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_982, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_986 : node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_990 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_990, UInt<1>(0h1), "") : assert_54 node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_994, UInt<1>(0h1), "") : assert_55 node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_998, UInt<1>(0h1), "") : assert_56 node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57 node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(sink_ok, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1013 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60 node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61 node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64 node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1034 : node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(sink_ok, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1041 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67 node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68 node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71 node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75 node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1080 : node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77 node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1089 = or(_T_1088, io.in.d.bits.corrupt) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78 node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1094 = or(UInt<1>(0h1), _T_1093) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79 node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1098 : node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81 node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82 node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1111 = or(UInt<1>(0h1), _T_1110) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<256>(0h0) connect _WIRE.bits.mask, UInt<32>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<256>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 5) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1127 = eq(a_first, UInt<1>(0h0)) node _T_1128 = and(io.in.a.valid, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.a.bits.opcode, opcode) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87 node _T_1133 = eq(io.in.a.bits.param, param) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88 node _T_1137 = eq(io.in.a.bits.size, size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89 node _T_1141 = eq(io.in.a.bits.source, source) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90 node _T_1145 = eq(io.in.a.bits.address, address) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(_T_1149, a_first) when _T_1150 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 5) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1151 = eq(d_first, UInt<1>(0h0)) node _T_1152 = and(io.in.d.valid, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.bits.opcode, opcode_1) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92 node _T_1157 = eq(io.in.d.bits.param, param_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93 node _T_1161 = eq(io.in.d.bits.size, size_1) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94 node _T_1165 = eq(io.in.d.bits.source, source_1) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95 node _T_1169 = eq(io.in.d.bits.sink, sink) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96 node _T_1173 = eq(io.in.d.bits.denied, denied) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97 node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = and(_T_1177, d_first) when _T_1178 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 5) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 5) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<32> connect a_set, UInt<32>(0h0) wire a_set_wo_ready : UInt<32> connect a_set_wo_ready, UInt<32>(0h0) wire a_opcodes_set : UInt<128> connect a_opcodes_set, UInt<128>(0h0) wire a_sizes_set : UInt<256> connect a_sizes_set, UInt<256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1179 = and(io.in.a.valid, a_first_1) node _T_1180 = and(_T_1179, UInt<1>(0h1)) when _T_1180 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1181 = and(io.in.a.ready, io.in.a.valid) node _T_1182 = and(_T_1181, a_first_1) node _T_1183 = and(_T_1182, UInt<1>(0h1)) when _T_1183 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1184 = dshr(inflight, io.in.a.bits.source) node _T_1185 = bits(_T_1184, 0, 0) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<32> connect d_clr, UInt<32>(0h0) wire d_clr_wo_ready : UInt<32> connect d_clr_wo_ready, UInt<32>(0h0) wire d_opcodes_clr : UInt<128> connect d_opcodes_clr, UInt<128>(0h0) wire d_sizes_clr : UInt<256> connect d_sizes_clr, UInt<256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1190 = and(io.in.d.valid, d_first_1) node _T_1191 = and(_T_1190, UInt<1>(0h1)) node _T_1192 = eq(d_release_ack, UInt<1>(0h0)) node _T_1193 = and(_T_1191, _T_1192) when _T_1193 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1194 = and(io.in.d.ready, io.in.d.valid) node _T_1195 = and(_T_1194, d_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) node _T_1197 = eq(d_release_ack, UInt<1>(0h0)) node _T_1198 = and(_T_1196, _T_1197) when _T_1198 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1203 = dshr(inflight, io.in.d.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = or(_T_1204, same_cycle_resp) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100 node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101 else : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102 node _T_1225 = eq(io.in.d.bits.size, a_size_lookup) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103 node _T_1229 = and(io.in.d.valid, d_first_1) node _T_1230 = and(_T_1229, a_first_1) node _T_1231 = and(_T_1230, io.in.a.valid) node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = eq(d_release_ack, UInt<1>(0h0)) node _T_1235 = and(_T_1233, _T_1234) when _T_1235 : node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.a.ready) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104 node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1242 = orr(a_set_wo_ready) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_124 node _T_1248 = orr(inflight) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = lt(watchdog, plusarg_reader.out) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1257 = and(io.in.a.ready, io.in.a.valid) node _T_1258 = and(io.in.d.ready, io.in.d.valid) node _T_1259 = or(_T_1257, _T_1258) when _T_1259 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<256>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<256>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 5) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 5) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<32> connect c_set, UInt<32>(0h0) wire c_set_wo_ready : UInt<32> connect c_set_wo_ready, UInt<32>(0h0) wire c_opcodes_set : UInt<128> connect c_opcodes_set, UInt<128>(0h0) wire c_sizes_set : UInt<256> connect c_sizes_set, UInt<256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<256>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1260 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<256>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = and(_T_1260, _T_1263) when _T_1264 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<256>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<256>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1266 = and(_T_1265, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<256>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = and(_T_1266, _T_1269) when _T_1270 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<256>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<256>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<256>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<256>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<256>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<256>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1272 = bits(_T_1271, 0, 0) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<256>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<256>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<32> connect d_clr_1, UInt<32>(0h0) wire d_clr_wo_ready_1 : UInt<32> connect d_clr_wo_ready_1, UInt<32>(0h0) wire d_opcodes_clr_1 : UInt<128> connect d_opcodes_clr_1, UInt<128>(0h0) wire d_sizes_clr_1 : UInt<256> connect d_sizes_clr_1, UInt<256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1277 = and(io.in.d.valid, d_first_2) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = and(_T_1278, d_release_ack_1) when _T_1279 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1280 = and(io.in.d.ready, io.in.d.valid) node _T_1281 = and(_T_1280, d_first_2) node _T_1282 = and(_T_1281, UInt<1>(0h1)) node _T_1283 = and(_T_1282, d_release_ack_1) when _T_1283 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1284 = and(io.in.d.valid, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1287 = dshr(inflight_1, io.in.d.bits.source) node _T_1288 = bits(_T_1287, 0, 0) node _T_1289 = or(_T_1288, same_cycle_resp_1) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<256>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109 else : node _T_1297 = eq(io.in.d.bits.size, c_size_lookup) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110 node _T_1301 = and(io.in.d.valid, d_first_2) node _T_1302 = and(_T_1301, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<256>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1303 = and(_T_1302, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<256>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = and(_T_1305, d_release_ack_1) node _T_1307 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1308 = and(_T_1306, _T_1307) when _T_1308 : node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<256>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1310 = or(_T_1309, _WIRE_23.ready) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111 node _T_1314 = orr(c_set_wo_ready) when _T_1314 : node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_125 node _T_1319 = orr(inflight_1) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog_1, plusarg_reader_1.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:53:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<256>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_62( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [255:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [255:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [255:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [255:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [6:0] c_first_beats1_decode = 7'h0; // @[Edges.scala:220:59] wire [6:0] c_first_beats1 = 7'h0; // @[Edges.scala:221:14] wire [6:0] _c_first_count_T = 7'h0; // @[Edges.scala:234:27] wire [6:0] c_first_count = 7'h0; // @[Edges.scala:234:25] wire [6:0] _c_first_counter_T = 7'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [6:0] c_first_counter1 = 7'h7F; // @[Edges.scala:230:28] wire [7:0] _c_first_counter1_T = 8'hFF; // @[Edges.scala:230:28] wire [255:0] _c_first_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_first_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_first_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_first_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34] wire [255:0] _c_set_wo_ready_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_set_wo_ready_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_opcodes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_opcodes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_sizes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_sizes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_opcodes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_opcodes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_sizes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_sizes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_probe_ack_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_probe_ack_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_probe_ack_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_probe_ack_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_4_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_5_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34] wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [4:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [2:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[2:0]; // @[OneHot.scala:64:49] wire [7:0] _mask_sizeOH_T_1 = 8'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [4:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] mask_sizeOH = {_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h4; // @[Misc.scala:206:21] wire mask_sub_sub_sub_sub_size = mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size & mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size & mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size & mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_4_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size & mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_5_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size & mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_6_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size & mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_7_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size & mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_8_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size & mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_9_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size & mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_10_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size & mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_11_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size & mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_12_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size & mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_13_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size & mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_14_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size & mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_15_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_8_1 | _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_8_1 | _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_9_1 | _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_9_1 | _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_10_1 | _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_10_1 | _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_11_1 | _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_11_1 | _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_12_1 | _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_12_1 | _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_13_1 | _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_13_1 | _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_14_1 | _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_14_1 | _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_15_1 | _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_15_1 | _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo = {mask_lo_lo_lo_hi, mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi = {mask_lo_lo_hi_hi, mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo = {mask_lo_hi_lo_hi, mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi = {mask_lo_hi_hi_hi, mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_hi = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo = {mask_hi_lo_lo_hi, mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_hi = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi = {mask_hi_lo_hi_hi, mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_hi = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo = {mask_hi_hi_lo_hi, mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_hi = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi = {mask_hi_hi_hi_hi, mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [31:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [6:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [6:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [6:0] a_first_counter; // @[Edges.scala:229:27] wire [7:0] _a_first_counter1_T = {1'h0, a_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] a_first_counter1 = _a_first_counter1_T[6:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [6:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [6:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [6:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T = {1'h0, d_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1 = _d_first_counter1_T[6:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [6:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [6:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [6:0] a_first_counter_1; // @[Edges.scala:229:27] wire [7:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] a_first_counter1_1 = _a_first_counter1_T_1[6:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [6:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [6:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46] wire [6:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter_1; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1_1 = _d_first_counter1_T_1[6:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [31:0] a_set; // @[Monitor.scala:626:34] wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [31:0] d_clr; // @[Monitor.scala:664:34] wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [31:0] inflight_1; // @[Monitor.scala:726:35] wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:5]; // @[package.scala:243:46] wire [6:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter_2; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1_2 = _d_first_counter1_T_2[6:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [31:0] d_clr_1; // @[Monitor.scala:774:34] wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module BIMBranchPredictorBank : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}} connect io.resp, io.resp_in[0] connect io.f3_meta, UInt<1>(0h0) node s0_idx = shr(io.f0_pc, 3) reg s1_idx : UInt, clock connect s1_idx, s0_idx reg s2_idx : UInt, clock connect s2_idx, s1_idx reg s3_idx : UInt, clock connect s3_idx, s2_idx reg s1_valid : UInt<1>, clock connect s1_valid, io.f0_valid reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid reg s3_valid : UInt<1>, clock connect s3_valid, s2_valid reg s1_mask : UInt, clock connect s1_mask, io.f0_mask reg s2_mask : UInt, clock connect s2_mask, s1_mask reg s3_mask : UInt, clock connect s3_mask, s2_mask node _s0_pc_T = not(io.f0_pc) node _s0_pc_T_1 = or(_s0_pc_T, UInt<3>(0h7)) node s0_pc = not(_s0_pc_T_1) reg s1_pc : UInt, clock connect s1_pc, s0_pc reg s2_pc : UInt, clock connect s2_pc, s1_pc node s0_update_idx = shr(io.update.bits.pc, 3) reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock connect s1_update.bits.meta, io.update.bits.meta connect s1_update.bits.target, io.update.bits.target connect s1_update.bits.lhist, io.update.bits.lhist connect s1_update.bits.ghist, io.update.bits.ghist connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect s1_update.bits.br_mask, io.update.bits.br_mask connect s1_update.bits.pc, io.update.bits.pc connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect s1_update.valid, io.update.valid node _s1_update_bits_pc_T = not(io.update.bits.pc) node _s1_update_bits_pc_T_1 = or(_s1_update_bits_pc_T, UInt<3>(0h7)) node _s1_update_bits_pc_T_2 = not(_s1_update_bits_pc_T_1) connect s1_update.bits.pc, _s1_update_bits_pc_T_2 reg s1_update_idx : UInt, clock connect s1_update_idx, s0_update_idx reg s1_update_valid : UInt<1>, clock connect s1_update_valid, io.update.valid wire s2_meta : { bims : UInt<2>[4]} node lo = cat(s2_meta.bims[1], s2_meta.bims[0]) node hi = cat(s2_meta.bims[3], s2_meta.bims[2]) node _T = cat(hi, lo) regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<8>, clock, reset, UInt<8>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T_1 = eq(reset_idx, UInt<8>(0hff)) when _T_1 : connect doing_reset, UInt<1>(0h0) node _s0_col_mask_T = bits(s0_idx, 2, 0) node _s0_col_mask_T_1 = dshl(UInt<1>(0h1), _s0_col_mask_T) node _s0_col_mask_T_2 = mux(io.f0_valid, UInt<8>(0hff), UInt<8>(0h0)) node s0_col_mask = and(_s0_col_mask_T_1, _s0_col_mask_T_2) reg s1_col_mask : UInt, clock connect s1_col_mask, s0_col_mask node s0_col_idx = shr(s0_idx, 3) reg s1_col_idx : UInt, clock connect s1_col_idx, s0_col_idx wire s2_req_rdata_all : UInt<2>[4][8] reg s2_req_rdata_REG : UInt, clock connect s2_req_rdata_REG, s1_col_mask node _s2_req_rdata_T = bits(s2_req_rdata_REG, 0, 0) node _s2_req_rdata_T_1 = bits(s2_req_rdata_REG, 1, 1) node _s2_req_rdata_T_2 = bits(s2_req_rdata_REG, 2, 2) node _s2_req_rdata_T_3 = bits(s2_req_rdata_REG, 3, 3) node _s2_req_rdata_T_4 = bits(s2_req_rdata_REG, 4, 4) node _s2_req_rdata_T_5 = bits(s2_req_rdata_REG, 5, 5) node _s2_req_rdata_T_6 = bits(s2_req_rdata_REG, 6, 6) node _s2_req_rdata_T_7 = bits(s2_req_rdata_REG, 7, 7) wire s2_req_rdata : UInt<2>[4] node _s2_req_rdata_T_8 = mux(_s2_req_rdata_T, s2_req_rdata_all[0][0], UInt<1>(0h0)) node _s2_req_rdata_T_9 = mux(_s2_req_rdata_T_1, s2_req_rdata_all[1][0], UInt<1>(0h0)) node _s2_req_rdata_T_10 = mux(_s2_req_rdata_T_2, s2_req_rdata_all[2][0], UInt<1>(0h0)) node _s2_req_rdata_T_11 = mux(_s2_req_rdata_T_3, s2_req_rdata_all[3][0], UInt<1>(0h0)) node _s2_req_rdata_T_12 = mux(_s2_req_rdata_T_4, s2_req_rdata_all[4][0], UInt<1>(0h0)) node _s2_req_rdata_T_13 = mux(_s2_req_rdata_T_5, s2_req_rdata_all[5][0], UInt<1>(0h0)) node _s2_req_rdata_T_14 = mux(_s2_req_rdata_T_6, s2_req_rdata_all[6][0], UInt<1>(0h0)) node _s2_req_rdata_T_15 = mux(_s2_req_rdata_T_7, s2_req_rdata_all[7][0], UInt<1>(0h0)) node _s2_req_rdata_T_16 = or(_s2_req_rdata_T_8, _s2_req_rdata_T_9) node _s2_req_rdata_T_17 = or(_s2_req_rdata_T_16, _s2_req_rdata_T_10) node _s2_req_rdata_T_18 = or(_s2_req_rdata_T_17, _s2_req_rdata_T_11) node _s2_req_rdata_T_19 = or(_s2_req_rdata_T_18, _s2_req_rdata_T_12) node _s2_req_rdata_T_20 = or(_s2_req_rdata_T_19, _s2_req_rdata_T_13) node _s2_req_rdata_T_21 = or(_s2_req_rdata_T_20, _s2_req_rdata_T_14) node _s2_req_rdata_T_22 = or(_s2_req_rdata_T_21, _s2_req_rdata_T_15) wire _s2_req_rdata_WIRE : UInt<2> connect _s2_req_rdata_WIRE, _s2_req_rdata_T_22 connect s2_req_rdata[0], _s2_req_rdata_WIRE node _s2_req_rdata_T_23 = mux(_s2_req_rdata_T, s2_req_rdata_all[0][1], UInt<1>(0h0)) node _s2_req_rdata_T_24 = mux(_s2_req_rdata_T_1, s2_req_rdata_all[1][1], UInt<1>(0h0)) node _s2_req_rdata_T_25 = mux(_s2_req_rdata_T_2, s2_req_rdata_all[2][1], UInt<1>(0h0)) node _s2_req_rdata_T_26 = mux(_s2_req_rdata_T_3, s2_req_rdata_all[3][1], UInt<1>(0h0)) node _s2_req_rdata_T_27 = mux(_s2_req_rdata_T_4, s2_req_rdata_all[4][1], UInt<1>(0h0)) node _s2_req_rdata_T_28 = mux(_s2_req_rdata_T_5, s2_req_rdata_all[5][1], UInt<1>(0h0)) node _s2_req_rdata_T_29 = mux(_s2_req_rdata_T_6, s2_req_rdata_all[6][1], UInt<1>(0h0)) node _s2_req_rdata_T_30 = mux(_s2_req_rdata_T_7, s2_req_rdata_all[7][1], UInt<1>(0h0)) node _s2_req_rdata_T_31 = or(_s2_req_rdata_T_23, _s2_req_rdata_T_24) node _s2_req_rdata_T_32 = or(_s2_req_rdata_T_31, _s2_req_rdata_T_25) node _s2_req_rdata_T_33 = or(_s2_req_rdata_T_32, _s2_req_rdata_T_26) node _s2_req_rdata_T_34 = or(_s2_req_rdata_T_33, _s2_req_rdata_T_27) node _s2_req_rdata_T_35 = or(_s2_req_rdata_T_34, _s2_req_rdata_T_28) node _s2_req_rdata_T_36 = or(_s2_req_rdata_T_35, _s2_req_rdata_T_29) node _s2_req_rdata_T_37 = or(_s2_req_rdata_T_36, _s2_req_rdata_T_30) wire _s2_req_rdata_WIRE_1 : UInt<2> connect _s2_req_rdata_WIRE_1, _s2_req_rdata_T_37 connect s2_req_rdata[1], _s2_req_rdata_WIRE_1 node _s2_req_rdata_T_38 = mux(_s2_req_rdata_T, s2_req_rdata_all[0][2], UInt<1>(0h0)) node _s2_req_rdata_T_39 = mux(_s2_req_rdata_T_1, s2_req_rdata_all[1][2], UInt<1>(0h0)) node _s2_req_rdata_T_40 = mux(_s2_req_rdata_T_2, s2_req_rdata_all[2][2], UInt<1>(0h0)) node _s2_req_rdata_T_41 = mux(_s2_req_rdata_T_3, s2_req_rdata_all[3][2], UInt<1>(0h0)) node _s2_req_rdata_T_42 = mux(_s2_req_rdata_T_4, s2_req_rdata_all[4][2], UInt<1>(0h0)) node _s2_req_rdata_T_43 = mux(_s2_req_rdata_T_5, s2_req_rdata_all[5][2], UInt<1>(0h0)) node _s2_req_rdata_T_44 = mux(_s2_req_rdata_T_6, s2_req_rdata_all[6][2], UInt<1>(0h0)) node _s2_req_rdata_T_45 = mux(_s2_req_rdata_T_7, s2_req_rdata_all[7][2], UInt<1>(0h0)) node _s2_req_rdata_T_46 = or(_s2_req_rdata_T_38, _s2_req_rdata_T_39) node _s2_req_rdata_T_47 = or(_s2_req_rdata_T_46, _s2_req_rdata_T_40) node _s2_req_rdata_T_48 = or(_s2_req_rdata_T_47, _s2_req_rdata_T_41) node _s2_req_rdata_T_49 = or(_s2_req_rdata_T_48, _s2_req_rdata_T_42) node _s2_req_rdata_T_50 = or(_s2_req_rdata_T_49, _s2_req_rdata_T_43) node _s2_req_rdata_T_51 = or(_s2_req_rdata_T_50, _s2_req_rdata_T_44) node _s2_req_rdata_T_52 = or(_s2_req_rdata_T_51, _s2_req_rdata_T_45) wire _s2_req_rdata_WIRE_2 : UInt<2> connect _s2_req_rdata_WIRE_2, _s2_req_rdata_T_52 connect s2_req_rdata[2], _s2_req_rdata_WIRE_2 node _s2_req_rdata_T_53 = mux(_s2_req_rdata_T, s2_req_rdata_all[0][3], UInt<1>(0h0)) node _s2_req_rdata_T_54 = mux(_s2_req_rdata_T_1, s2_req_rdata_all[1][3], UInt<1>(0h0)) node _s2_req_rdata_T_55 = mux(_s2_req_rdata_T_2, s2_req_rdata_all[2][3], UInt<1>(0h0)) node _s2_req_rdata_T_56 = mux(_s2_req_rdata_T_3, s2_req_rdata_all[3][3], UInt<1>(0h0)) node _s2_req_rdata_T_57 = mux(_s2_req_rdata_T_4, s2_req_rdata_all[4][3], UInt<1>(0h0)) node _s2_req_rdata_T_58 = mux(_s2_req_rdata_T_5, s2_req_rdata_all[5][3], UInt<1>(0h0)) node _s2_req_rdata_T_59 = mux(_s2_req_rdata_T_6, s2_req_rdata_all[6][3], UInt<1>(0h0)) node _s2_req_rdata_T_60 = mux(_s2_req_rdata_T_7, s2_req_rdata_all[7][3], UInt<1>(0h0)) node _s2_req_rdata_T_61 = or(_s2_req_rdata_T_53, _s2_req_rdata_T_54) node _s2_req_rdata_T_62 = or(_s2_req_rdata_T_61, _s2_req_rdata_T_55) node _s2_req_rdata_T_63 = or(_s2_req_rdata_T_62, _s2_req_rdata_T_56) node _s2_req_rdata_T_64 = or(_s2_req_rdata_T_63, _s2_req_rdata_T_57) node _s2_req_rdata_T_65 = or(_s2_req_rdata_T_64, _s2_req_rdata_T_58) node _s2_req_rdata_T_66 = or(_s2_req_rdata_T_65, _s2_req_rdata_T_59) node _s2_req_rdata_T_67 = or(_s2_req_rdata_T_66, _s2_req_rdata_T_60) wire _s2_req_rdata_WIRE_3 : UInt<2> connect _s2_req_rdata_WIRE_3, _s2_req_rdata_T_67 connect s2_req_rdata[3], _s2_req_rdata_WIRE_3 wire s2_resp : UInt<1>[4] node _s2_resp_0_T = bits(s2_req_rdata[0], 1, 1) node _s2_resp_0_T_1 = and(s2_valid, _s2_resp_0_T) node _s2_resp_0_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_resp_0_T_3 = and(_s2_resp_0_T_1, _s2_resp_0_T_2) connect s2_resp[0], _s2_resp_0_T_3 connect s2_meta.bims[0], s2_req_rdata[0] connect io.resp.f2[0].taken, s2_resp[0] reg io_resp_f3_0_taken_REG : UInt<1>, clock connect io_resp_f3_0_taken_REG, s2_resp[0] connect io.resp.f3[0].taken, io_resp_f3_0_taken_REG node _s2_resp_1_T = bits(s2_req_rdata[1], 1, 1) node _s2_resp_1_T_1 = and(s2_valid, _s2_resp_1_T) node _s2_resp_1_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_resp_1_T_3 = and(_s2_resp_1_T_1, _s2_resp_1_T_2) connect s2_resp[1], _s2_resp_1_T_3 connect s2_meta.bims[1], s2_req_rdata[1] connect io.resp.f2[1].taken, s2_resp[1] reg io_resp_f3_1_taken_REG : UInt<1>, clock connect io_resp_f3_1_taken_REG, s2_resp[1] connect io.resp.f3[1].taken, io_resp_f3_1_taken_REG node _s2_resp_2_T = bits(s2_req_rdata[2], 1, 1) node _s2_resp_2_T_1 = and(s2_valid, _s2_resp_2_T) node _s2_resp_2_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_resp_2_T_3 = and(_s2_resp_2_T_1, _s2_resp_2_T_2) connect s2_resp[2], _s2_resp_2_T_3 connect s2_meta.bims[2], s2_req_rdata[2] connect io.resp.f2[2].taken, s2_resp[2] reg io_resp_f3_2_taken_REG : UInt<1>, clock connect io_resp_f3_2_taken_REG, s2_resp[2] connect io.resp.f3[2].taken, io_resp_f3_2_taken_REG node _s2_resp_3_T = bits(s2_req_rdata[3], 1, 1) node _s2_resp_3_T_1 = and(s2_valid, _s2_resp_3_T) node _s2_resp_3_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_resp_3_T_3 = and(_s2_resp_3_T_1, _s2_resp_3_T_2) connect s2_resp[3], _s2_resp_3_T_3 connect s2_meta.bims[3], s2_req_rdata[3] connect io.resp.f2[3].taken, s2_resp[3] reg io_resp_f3_3_taken_REG : UInt<1>, clock connect io_resp_f3_3_taken_REG, s2_resp[3] connect io.resp.f3[3].taken, io_resp_f3_3_taken_REG node io_f3_meta_lo = cat(s2_meta.bims[1], s2_meta.bims[0]) node io_f3_meta_hi = cat(s2_meta.bims[3], s2_meta.bims[2]) node _io_f3_meta_T = cat(io_f3_meta_hi, io_f3_meta_lo) reg io_f3_meta_REG : UInt, clock connect io_f3_meta_REG, _io_f3_meta_T connect io.f3_meta, io_f3_meta_REG wire s1_update_wdata : UInt<2>[4] wire s1_update_wmask : UInt<1>[4] wire s1_update_meta : { bims : UInt<2>[4]} wire _s1_update_meta_WIRE : UInt<8> connect _s1_update_meta_WIRE, s1_update.bits.meta node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 1, 0) connect s1_update_meta.bims[0], _s1_update_meta_T node _s1_update_meta_T_1 = bits(_s1_update_meta_WIRE, 3, 2) connect s1_update_meta.bims[1], _s1_update_meta_T_1 node _s1_update_meta_T_2 = bits(_s1_update_meta_WIRE, 5, 4) connect s1_update_meta.bims[2], _s1_update_meta_T_2 node _s1_update_meta_T_3 = bits(_s1_update_meta_WIRE, 7, 6) connect s1_update_meta.bims[3], _s1_update_meta_T_3 node _s1_update_col_mask_T = bits(s1_update_idx, 2, 0) node s1_update_col_mask = dshl(UInt<1>(0h1), _s1_update_col_mask_T) node s1_update_col_idx = shr(s1_update_idx, 3) reg wrbypass_idxs : UInt<11>[2], clock reg wrbypass : UInt<2>[4][2], clock regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0) node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_1 = bits(s1_update_idx, 10, 0) node _wrbypass_hits_T_2 = eq(wrbypass_idxs[0], _wrbypass_hits_T_1) node _wrbypass_hits_T_3 = and(_wrbypass_hits_T, _wrbypass_hits_T_2) node _wrbypass_hits_T_4 = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_5 = bits(s1_update_idx, 10, 0) node _wrbypass_hits_T_6 = eq(wrbypass_idxs[1], _wrbypass_hits_T_5) node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_4, _wrbypass_hits_T_6) wire wrbypass_hits : UInt<1>[2] connect wrbypass_hits[0], _wrbypass_hits_T_3 connect wrbypass_hits[1], _wrbypass_hits_T_7 node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1]) node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1)) connect s1_update_wmask[0], UInt<1>(0h0) invalidate s1_update_wdata[0] node _update_pc_T = add(s1_update.bits.pc, UInt<1>(0h0)) node update_pc = tail(_update_pc_T, 1) node _T_2 = bits(s1_update.bits.br_mask, 0, 0) node _T_3 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h0)) node _T_4 = and(s1_update.bits.cfi_idx.valid, _T_3) node _T_5 = or(_T_2, _T_4) when _T_5 : node _was_taken_T = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h0)) node _was_taken_T_1 = and(s1_update.bits.cfi_idx.valid, _was_taken_T) node _was_taken_T_2 = bits(s1_update.bits.br_mask, 0, 0) node _was_taken_T_3 = and(s1_update.bits.cfi_is_br, _was_taken_T_2) node _was_taken_T_4 = and(_was_taken_T_3, s1_update.bits.cfi_taken) node _was_taken_T_5 = or(_was_taken_T_4, s1_update.bits.cfi_is_jal) node was_taken = and(_was_taken_T_1, _was_taken_T_5) node old_bim_value = mux(wrbypass_hit, wrbypass[wrbypass_hit_idx][0], s1_update_meta.bims[0]) connect s1_update_wmask[0], UInt<1>(0h1) node s1_update_wdata_0_old_bim_sat_taken = eq(old_bim_value, UInt<2>(0h3)) node s1_update_wdata_0_old_bim_sat_ntaken = eq(old_bim_value, UInt<1>(0h0)) node _s1_update_wdata_0_T = and(s1_update_wdata_0_old_bim_sat_taken, was_taken) node _s1_update_wdata_0_T_1 = eq(was_taken, UInt<1>(0h0)) node _s1_update_wdata_0_T_2 = and(s1_update_wdata_0_old_bim_sat_ntaken, _s1_update_wdata_0_T_1) node _s1_update_wdata_0_T_3 = add(old_bim_value, UInt<1>(0h1)) node _s1_update_wdata_0_T_4 = tail(_s1_update_wdata_0_T_3, 1) node _s1_update_wdata_0_T_5 = sub(old_bim_value, UInt<1>(0h1)) node _s1_update_wdata_0_T_6 = tail(_s1_update_wdata_0_T_5, 1) node _s1_update_wdata_0_T_7 = mux(was_taken, _s1_update_wdata_0_T_4, _s1_update_wdata_0_T_6) node _s1_update_wdata_0_T_8 = mux(_s1_update_wdata_0_T_2, UInt<1>(0h0), _s1_update_wdata_0_T_7) node _s1_update_wdata_0_T_9 = mux(_s1_update_wdata_0_T, UInt<2>(0h3), _s1_update_wdata_0_T_8) connect s1_update_wdata[0], _s1_update_wdata_0_T_9 connect s1_update_wmask[1], UInt<1>(0h0) invalidate s1_update_wdata[1] node _update_pc_T_1 = add(s1_update.bits.pc, UInt<2>(0h2)) node update_pc_1 = tail(_update_pc_T_1, 1) node _T_6 = bits(s1_update.bits.br_mask, 1, 1) node _T_7 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h1)) node _T_8 = and(s1_update.bits.cfi_idx.valid, _T_7) node _T_9 = or(_T_6, _T_8) when _T_9 : node _was_taken_T_6 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h1)) node _was_taken_T_7 = and(s1_update.bits.cfi_idx.valid, _was_taken_T_6) node _was_taken_T_8 = bits(s1_update.bits.br_mask, 1, 1) node _was_taken_T_9 = and(s1_update.bits.cfi_is_br, _was_taken_T_8) node _was_taken_T_10 = and(_was_taken_T_9, s1_update.bits.cfi_taken) node _was_taken_T_11 = or(_was_taken_T_10, s1_update.bits.cfi_is_jal) node was_taken_1 = and(_was_taken_T_7, _was_taken_T_11) node old_bim_value_1 = mux(wrbypass_hit, wrbypass[wrbypass_hit_idx][1], s1_update_meta.bims[1]) connect s1_update_wmask[1], UInt<1>(0h1) node s1_update_wdata_1_old_bim_sat_taken = eq(old_bim_value_1, UInt<2>(0h3)) node s1_update_wdata_1_old_bim_sat_ntaken = eq(old_bim_value_1, UInt<1>(0h0)) node _s1_update_wdata_1_T = and(s1_update_wdata_1_old_bim_sat_taken, was_taken_1) node _s1_update_wdata_1_T_1 = eq(was_taken_1, UInt<1>(0h0)) node _s1_update_wdata_1_T_2 = and(s1_update_wdata_1_old_bim_sat_ntaken, _s1_update_wdata_1_T_1) node _s1_update_wdata_1_T_3 = add(old_bim_value_1, UInt<1>(0h1)) node _s1_update_wdata_1_T_4 = tail(_s1_update_wdata_1_T_3, 1) node _s1_update_wdata_1_T_5 = sub(old_bim_value_1, UInt<1>(0h1)) node _s1_update_wdata_1_T_6 = tail(_s1_update_wdata_1_T_5, 1) node _s1_update_wdata_1_T_7 = mux(was_taken_1, _s1_update_wdata_1_T_4, _s1_update_wdata_1_T_6) node _s1_update_wdata_1_T_8 = mux(_s1_update_wdata_1_T_2, UInt<1>(0h0), _s1_update_wdata_1_T_7) node _s1_update_wdata_1_T_9 = mux(_s1_update_wdata_1_T, UInt<2>(0h3), _s1_update_wdata_1_T_8) connect s1_update_wdata[1], _s1_update_wdata_1_T_9 connect s1_update_wmask[2], UInt<1>(0h0) invalidate s1_update_wdata[2] node _update_pc_T_2 = add(s1_update.bits.pc, UInt<3>(0h4)) node update_pc_2 = tail(_update_pc_T_2, 1) node _T_10 = bits(s1_update.bits.br_mask, 2, 2) node _T_11 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h2)) node _T_12 = and(s1_update.bits.cfi_idx.valid, _T_11) node _T_13 = or(_T_10, _T_12) when _T_13 : node _was_taken_T_12 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h2)) node _was_taken_T_13 = and(s1_update.bits.cfi_idx.valid, _was_taken_T_12) node _was_taken_T_14 = bits(s1_update.bits.br_mask, 2, 2) node _was_taken_T_15 = and(s1_update.bits.cfi_is_br, _was_taken_T_14) node _was_taken_T_16 = and(_was_taken_T_15, s1_update.bits.cfi_taken) node _was_taken_T_17 = or(_was_taken_T_16, s1_update.bits.cfi_is_jal) node was_taken_2 = and(_was_taken_T_13, _was_taken_T_17) node old_bim_value_2 = mux(wrbypass_hit, wrbypass[wrbypass_hit_idx][2], s1_update_meta.bims[2]) connect s1_update_wmask[2], UInt<1>(0h1) node s1_update_wdata_2_old_bim_sat_taken = eq(old_bim_value_2, UInt<2>(0h3)) node s1_update_wdata_2_old_bim_sat_ntaken = eq(old_bim_value_2, UInt<1>(0h0)) node _s1_update_wdata_2_T = and(s1_update_wdata_2_old_bim_sat_taken, was_taken_2) node _s1_update_wdata_2_T_1 = eq(was_taken_2, UInt<1>(0h0)) node _s1_update_wdata_2_T_2 = and(s1_update_wdata_2_old_bim_sat_ntaken, _s1_update_wdata_2_T_1) node _s1_update_wdata_2_T_3 = add(old_bim_value_2, UInt<1>(0h1)) node _s1_update_wdata_2_T_4 = tail(_s1_update_wdata_2_T_3, 1) node _s1_update_wdata_2_T_5 = sub(old_bim_value_2, UInt<1>(0h1)) node _s1_update_wdata_2_T_6 = tail(_s1_update_wdata_2_T_5, 1) node _s1_update_wdata_2_T_7 = mux(was_taken_2, _s1_update_wdata_2_T_4, _s1_update_wdata_2_T_6) node _s1_update_wdata_2_T_8 = mux(_s1_update_wdata_2_T_2, UInt<1>(0h0), _s1_update_wdata_2_T_7) node _s1_update_wdata_2_T_9 = mux(_s1_update_wdata_2_T, UInt<2>(0h3), _s1_update_wdata_2_T_8) connect s1_update_wdata[2], _s1_update_wdata_2_T_9 connect s1_update_wmask[3], UInt<1>(0h0) invalidate s1_update_wdata[3] node _update_pc_T_3 = add(s1_update.bits.pc, UInt<3>(0h6)) node update_pc_3 = tail(_update_pc_T_3, 1) node _T_14 = bits(s1_update.bits.br_mask, 3, 3) node _T_15 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h3)) node _T_16 = and(s1_update.bits.cfi_idx.valid, _T_15) node _T_17 = or(_T_14, _T_16) when _T_17 : node _was_taken_T_18 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h3)) node _was_taken_T_19 = and(s1_update.bits.cfi_idx.valid, _was_taken_T_18) node _was_taken_T_20 = bits(s1_update.bits.br_mask, 3, 3) node _was_taken_T_21 = and(s1_update.bits.cfi_is_br, _was_taken_T_20) node _was_taken_T_22 = and(_was_taken_T_21, s1_update.bits.cfi_taken) node _was_taken_T_23 = or(_was_taken_T_22, s1_update.bits.cfi_is_jal) node was_taken_3 = and(_was_taken_T_19, _was_taken_T_23) node old_bim_value_3 = mux(wrbypass_hit, wrbypass[wrbypass_hit_idx][3], s1_update_meta.bims[3]) connect s1_update_wmask[3], UInt<1>(0h1) node s1_update_wdata_3_old_bim_sat_taken = eq(old_bim_value_3, UInt<2>(0h3)) node s1_update_wdata_3_old_bim_sat_ntaken = eq(old_bim_value_3, UInt<1>(0h0)) node _s1_update_wdata_3_T = and(s1_update_wdata_3_old_bim_sat_taken, was_taken_3) node _s1_update_wdata_3_T_1 = eq(was_taken_3, UInt<1>(0h0)) node _s1_update_wdata_3_T_2 = and(s1_update_wdata_3_old_bim_sat_ntaken, _s1_update_wdata_3_T_1) node _s1_update_wdata_3_T_3 = add(old_bim_value_3, UInt<1>(0h1)) node _s1_update_wdata_3_T_4 = tail(_s1_update_wdata_3_T_3, 1) node _s1_update_wdata_3_T_5 = sub(old_bim_value_3, UInt<1>(0h1)) node _s1_update_wdata_3_T_6 = tail(_s1_update_wdata_3_T_5, 1) node _s1_update_wdata_3_T_7 = mux(was_taken_3, _s1_update_wdata_3_T_4, _s1_update_wdata_3_T_6) node _s1_update_wdata_3_T_8 = mux(_s1_update_wdata_3_T_2, UInt<1>(0h0), _s1_update_wdata_3_T_7) node _s1_update_wdata_3_T_9 = mux(_s1_update_wdata_3_T, UInt<2>(0h3), _s1_update_wdata_3_T_8) connect s1_update_wdata[3], _s1_update_wdata_3_T_9 wire rdata : UInt<2>[4] invalidate rdata[0] invalidate rdata[1] invalidate rdata[2] invalidate rdata[3] node ren = bits(s0_col_mask, 0, 0) node _wen_T = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _wen_T_1 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _wen_T_2 = or(_wen_T, _wen_T_1) node _wen_T_3 = eq(_wen_T_2, UInt<1>(0h0)) node _wen_T_4 = and(s1_update.valid, _wen_T_3) node _wen_T_5 = bits(s1_update_col_mask, 0, 0) node _wen_T_6 = and(_wen_T_4, _wen_T_5) node _wen_T_7 = eq(ren, UInt<1>(0h0)) node _wen_T_8 = and(_wen_T_6, _wen_T_7) node _wen_T_9 = or(doing_reset, _wen_T_8) wire wen : UInt<1> connect wen, _wen_T_9 reg REG : UInt<2>[4], clock connect REG, rdata connect s2_req_rdata_all[0], REG smem bim_col_0 : UInt<2>[4] [256] node _r_T = eq(wen, UInt<1>(0h0)) node _r_T_1 = and(ren, _r_T) wire _r_WIRE : UInt<34> invalidate _r_WIRE when _r_T_1 : connect _r_WIRE, s0_col_idx node _r_T_2 = bits(_r_WIRE, 7, 0) read mport r = bim_col_0[_r_T_2], clock connect rdata, r when wen : node widx = mux(doing_reset, reset_idx, s1_update_col_idx) wire _wdata_WIRE : UInt<2>[4] connect _wdata_WIRE[0], UInt<2>(0h2) connect _wdata_WIRE[1], UInt<2>(0h2) connect _wdata_WIRE[2], UInt<2>(0h2) connect _wdata_WIRE[3], UInt<2>(0h2) node wdata = mux(doing_reset, _wdata_WIRE, s1_update_wdata) node _wmask_T = not(UInt<4>(0h0)) node wmask_lo = cat(s1_update_wmask[1], s1_update_wmask[0]) node wmask_hi = cat(s1_update_wmask[3], s1_update_wmask[2]) node _wmask_T_1 = cat(wmask_hi, wmask_lo) node wmask = mux(doing_reset, _wmask_T, _wmask_T_1) node _T_18 = bits(wmask, 0, 0) node _T_19 = bits(wmask, 1, 1) node _T_20 = bits(wmask, 2, 2) node _T_21 = bits(wmask, 3, 3) node _T_22 = or(widx, UInt<8>(0h0)) node _T_23 = bits(_T_22, 7, 0) write mport MPORT = bim_col_0[_T_23], clock when _T_18 : connect MPORT[0], wdata[0] when _T_19 : connect MPORT[1], wdata[1] when _T_20 : connect MPORT[2], wdata[2] when _T_21 : connect MPORT[3], wdata[3] wire rdata_1 : UInt<2>[4] invalidate rdata_1[0] invalidate rdata_1[1] invalidate rdata_1[2] invalidate rdata_1[3] node ren_1 = bits(s0_col_mask, 1, 1) node _wen_T_10 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _wen_T_11 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _wen_T_12 = or(_wen_T_10, _wen_T_11) node _wen_T_13 = eq(_wen_T_12, UInt<1>(0h0)) node _wen_T_14 = and(s1_update.valid, _wen_T_13) node _wen_T_15 = bits(s1_update_col_mask, 1, 1) node _wen_T_16 = and(_wen_T_14, _wen_T_15) node _wen_T_17 = eq(ren_1, UInt<1>(0h0)) node _wen_T_18 = and(_wen_T_16, _wen_T_17) node _wen_T_19 = or(doing_reset, _wen_T_18) wire wen_1 : UInt<1> connect wen_1, _wen_T_19 reg REG_1 : UInt<2>[4], clock connect REG_1, rdata_1 connect s2_req_rdata_all[1], REG_1 smem bim_col_1 : UInt<2>[4] [256] node _r_T_3 = eq(wen_1, UInt<1>(0h0)) node _r_T_4 = and(ren_1, _r_T_3) wire _r_WIRE_1 : UInt<34> invalidate _r_WIRE_1 when _r_T_4 : connect _r_WIRE_1, s0_col_idx node _r_T_5 = bits(_r_WIRE_1, 7, 0) read mport r_1 = bim_col_1[_r_T_5], clock connect rdata_1, r_1 when wen_1 : node widx_1 = mux(doing_reset, reset_idx, s1_update_col_idx) wire _wdata_WIRE_1 : UInt<2>[4] connect _wdata_WIRE_1[0], UInt<2>(0h2) connect _wdata_WIRE_1[1], UInt<2>(0h2) connect _wdata_WIRE_1[2], UInt<2>(0h2) connect _wdata_WIRE_1[3], UInt<2>(0h2) node wdata_1 = mux(doing_reset, _wdata_WIRE_1, s1_update_wdata) node _wmask_T_2 = not(UInt<4>(0h0)) node wmask_lo_1 = cat(s1_update_wmask[1], s1_update_wmask[0]) node wmask_hi_1 = cat(s1_update_wmask[3], s1_update_wmask[2]) node _wmask_T_3 = cat(wmask_hi_1, wmask_lo_1) node wmask_1 = mux(doing_reset, _wmask_T_2, _wmask_T_3) node _T_24 = bits(wmask_1, 0, 0) node _T_25 = bits(wmask_1, 1, 1) node _T_26 = bits(wmask_1, 2, 2) node _T_27 = bits(wmask_1, 3, 3) node _T_28 = or(widx_1, UInt<8>(0h0)) node _T_29 = bits(_T_28, 7, 0) write mport MPORT_1 = bim_col_1[_T_29], clock when _T_24 : connect MPORT_1[0], wdata_1[0] when _T_25 : connect MPORT_1[1], wdata_1[1] when _T_26 : connect MPORT_1[2], wdata_1[2] when _T_27 : connect MPORT_1[3], wdata_1[3] wire rdata_2 : UInt<2>[4] invalidate rdata_2[0] invalidate rdata_2[1] invalidate rdata_2[2] invalidate rdata_2[3] node ren_2 = bits(s0_col_mask, 2, 2) node _wen_T_20 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _wen_T_21 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _wen_T_22 = or(_wen_T_20, _wen_T_21) node _wen_T_23 = eq(_wen_T_22, UInt<1>(0h0)) node _wen_T_24 = and(s1_update.valid, _wen_T_23) node _wen_T_25 = bits(s1_update_col_mask, 2, 2) node _wen_T_26 = and(_wen_T_24, _wen_T_25) node _wen_T_27 = eq(ren_2, UInt<1>(0h0)) node _wen_T_28 = and(_wen_T_26, _wen_T_27) node _wen_T_29 = or(doing_reset, _wen_T_28) wire wen_2 : UInt<1> connect wen_2, _wen_T_29 reg REG_2 : UInt<2>[4], clock connect REG_2, rdata_2 connect s2_req_rdata_all[2], REG_2 smem bim_col_2 : UInt<2>[4] [256] node _r_T_6 = eq(wen_2, UInt<1>(0h0)) node _r_T_7 = and(ren_2, _r_T_6) wire _r_WIRE_2 : UInt<34> invalidate _r_WIRE_2 when _r_T_7 : connect _r_WIRE_2, s0_col_idx node _r_T_8 = bits(_r_WIRE_2, 7, 0) read mport r_2 = bim_col_2[_r_T_8], clock connect rdata_2, r_2 when wen_2 : node widx_2 = mux(doing_reset, reset_idx, s1_update_col_idx) wire _wdata_WIRE_2 : UInt<2>[4] connect _wdata_WIRE_2[0], UInt<2>(0h2) connect _wdata_WIRE_2[1], UInt<2>(0h2) connect _wdata_WIRE_2[2], UInt<2>(0h2) connect _wdata_WIRE_2[3], UInt<2>(0h2) node wdata_2 = mux(doing_reset, _wdata_WIRE_2, s1_update_wdata) node _wmask_T_4 = not(UInt<4>(0h0)) node wmask_lo_2 = cat(s1_update_wmask[1], s1_update_wmask[0]) node wmask_hi_2 = cat(s1_update_wmask[3], s1_update_wmask[2]) node _wmask_T_5 = cat(wmask_hi_2, wmask_lo_2) node wmask_2 = mux(doing_reset, _wmask_T_4, _wmask_T_5) node _T_30 = bits(wmask_2, 0, 0) node _T_31 = bits(wmask_2, 1, 1) node _T_32 = bits(wmask_2, 2, 2) node _T_33 = bits(wmask_2, 3, 3) node _T_34 = or(widx_2, UInt<8>(0h0)) node _T_35 = bits(_T_34, 7, 0) write mport MPORT_2 = bim_col_2[_T_35], clock when _T_30 : connect MPORT_2[0], wdata_2[0] when _T_31 : connect MPORT_2[1], wdata_2[1] when _T_32 : connect MPORT_2[2], wdata_2[2] when _T_33 : connect MPORT_2[3], wdata_2[3] wire rdata_3 : UInt<2>[4] invalidate rdata_3[0] invalidate rdata_3[1] invalidate rdata_3[2] invalidate rdata_3[3] node ren_3 = bits(s0_col_mask, 3, 3) node _wen_T_30 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _wen_T_31 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _wen_T_32 = or(_wen_T_30, _wen_T_31) node _wen_T_33 = eq(_wen_T_32, UInt<1>(0h0)) node _wen_T_34 = and(s1_update.valid, _wen_T_33) node _wen_T_35 = bits(s1_update_col_mask, 3, 3) node _wen_T_36 = and(_wen_T_34, _wen_T_35) node _wen_T_37 = eq(ren_3, UInt<1>(0h0)) node _wen_T_38 = and(_wen_T_36, _wen_T_37) node _wen_T_39 = or(doing_reset, _wen_T_38) wire wen_3 : UInt<1> connect wen_3, _wen_T_39 reg REG_3 : UInt<2>[4], clock connect REG_3, rdata_3 connect s2_req_rdata_all[3], REG_3 smem bim_col_3 : UInt<2>[4] [256] node _r_T_9 = eq(wen_3, UInt<1>(0h0)) node _r_T_10 = and(ren_3, _r_T_9) wire _r_WIRE_3 : UInt<34> invalidate _r_WIRE_3 when _r_T_10 : connect _r_WIRE_3, s0_col_idx node _r_T_11 = bits(_r_WIRE_3, 7, 0) read mport r_3 = bim_col_3[_r_T_11], clock connect rdata_3, r_3 when wen_3 : node widx_3 = mux(doing_reset, reset_idx, s1_update_col_idx) wire _wdata_WIRE_3 : UInt<2>[4] connect _wdata_WIRE_3[0], UInt<2>(0h2) connect _wdata_WIRE_3[1], UInt<2>(0h2) connect _wdata_WIRE_3[2], UInt<2>(0h2) connect _wdata_WIRE_3[3], UInt<2>(0h2) node wdata_3 = mux(doing_reset, _wdata_WIRE_3, s1_update_wdata) node _wmask_T_6 = not(UInt<4>(0h0)) node wmask_lo_3 = cat(s1_update_wmask[1], s1_update_wmask[0]) node wmask_hi_3 = cat(s1_update_wmask[3], s1_update_wmask[2]) node _wmask_T_7 = cat(wmask_hi_3, wmask_lo_3) node wmask_3 = mux(doing_reset, _wmask_T_6, _wmask_T_7) node _T_36 = bits(wmask_3, 0, 0) node _T_37 = bits(wmask_3, 1, 1) node _T_38 = bits(wmask_3, 2, 2) node _T_39 = bits(wmask_3, 3, 3) node _T_40 = or(widx_3, UInt<8>(0h0)) node _T_41 = bits(_T_40, 7, 0) write mport MPORT_3 = bim_col_3[_T_41], clock when _T_36 : connect MPORT_3[0], wdata_3[0] when _T_37 : connect MPORT_3[1], wdata_3[1] when _T_38 : connect MPORT_3[2], wdata_3[2] when _T_39 : connect MPORT_3[3], wdata_3[3] wire rdata_4 : UInt<2>[4] invalidate rdata_4[0] invalidate rdata_4[1] invalidate rdata_4[2] invalidate rdata_4[3] node ren_4 = bits(s0_col_mask, 4, 4) node _wen_T_40 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _wen_T_41 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _wen_T_42 = or(_wen_T_40, _wen_T_41) node _wen_T_43 = eq(_wen_T_42, UInt<1>(0h0)) node _wen_T_44 = and(s1_update.valid, _wen_T_43) node _wen_T_45 = bits(s1_update_col_mask, 4, 4) node _wen_T_46 = and(_wen_T_44, _wen_T_45) node _wen_T_47 = eq(ren_4, UInt<1>(0h0)) node _wen_T_48 = and(_wen_T_46, _wen_T_47) node _wen_T_49 = or(doing_reset, _wen_T_48) wire wen_4 : UInt<1> connect wen_4, _wen_T_49 reg REG_4 : UInt<2>[4], clock connect REG_4, rdata_4 connect s2_req_rdata_all[4], REG_4 smem bim_col_4 : UInt<2>[4] [256] node _r_T_12 = eq(wen_4, UInt<1>(0h0)) node _r_T_13 = and(ren_4, _r_T_12) wire _r_WIRE_4 : UInt<34> invalidate _r_WIRE_4 when _r_T_13 : connect _r_WIRE_4, s0_col_idx node _r_T_14 = bits(_r_WIRE_4, 7, 0) read mport r_4 = bim_col_4[_r_T_14], clock connect rdata_4, r_4 when wen_4 : node widx_4 = mux(doing_reset, reset_idx, s1_update_col_idx) wire _wdata_WIRE_4 : UInt<2>[4] connect _wdata_WIRE_4[0], UInt<2>(0h2) connect _wdata_WIRE_4[1], UInt<2>(0h2) connect _wdata_WIRE_4[2], UInt<2>(0h2) connect _wdata_WIRE_4[3], UInt<2>(0h2) node wdata_4 = mux(doing_reset, _wdata_WIRE_4, s1_update_wdata) node _wmask_T_8 = not(UInt<4>(0h0)) node wmask_lo_4 = cat(s1_update_wmask[1], s1_update_wmask[0]) node wmask_hi_4 = cat(s1_update_wmask[3], s1_update_wmask[2]) node _wmask_T_9 = cat(wmask_hi_4, wmask_lo_4) node wmask_4 = mux(doing_reset, _wmask_T_8, _wmask_T_9) node _T_42 = bits(wmask_4, 0, 0) node _T_43 = bits(wmask_4, 1, 1) node _T_44 = bits(wmask_4, 2, 2) node _T_45 = bits(wmask_4, 3, 3) node _T_46 = or(widx_4, UInt<8>(0h0)) node _T_47 = bits(_T_46, 7, 0) write mport MPORT_4 = bim_col_4[_T_47], clock when _T_42 : connect MPORT_4[0], wdata_4[0] when _T_43 : connect MPORT_4[1], wdata_4[1] when _T_44 : connect MPORT_4[2], wdata_4[2] when _T_45 : connect MPORT_4[3], wdata_4[3] wire rdata_5 : UInt<2>[4] invalidate rdata_5[0] invalidate rdata_5[1] invalidate rdata_5[2] invalidate rdata_5[3] node ren_5 = bits(s0_col_mask, 5, 5) node _wen_T_50 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _wen_T_51 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _wen_T_52 = or(_wen_T_50, _wen_T_51) node _wen_T_53 = eq(_wen_T_52, UInt<1>(0h0)) node _wen_T_54 = and(s1_update.valid, _wen_T_53) node _wen_T_55 = bits(s1_update_col_mask, 5, 5) node _wen_T_56 = and(_wen_T_54, _wen_T_55) node _wen_T_57 = eq(ren_5, UInt<1>(0h0)) node _wen_T_58 = and(_wen_T_56, _wen_T_57) node _wen_T_59 = or(doing_reset, _wen_T_58) wire wen_5 : UInt<1> connect wen_5, _wen_T_59 reg REG_5 : UInt<2>[4], clock connect REG_5, rdata_5 connect s2_req_rdata_all[5], REG_5 smem bim_col_5 : UInt<2>[4] [256] node _r_T_15 = eq(wen_5, UInt<1>(0h0)) node _r_T_16 = and(ren_5, _r_T_15) wire _r_WIRE_5 : UInt<34> invalidate _r_WIRE_5 when _r_T_16 : connect _r_WIRE_5, s0_col_idx node _r_T_17 = bits(_r_WIRE_5, 7, 0) read mport r_5 = bim_col_5[_r_T_17], clock connect rdata_5, r_5 when wen_5 : node widx_5 = mux(doing_reset, reset_idx, s1_update_col_idx) wire _wdata_WIRE_5 : UInt<2>[4] connect _wdata_WIRE_5[0], UInt<2>(0h2) connect _wdata_WIRE_5[1], UInt<2>(0h2) connect _wdata_WIRE_5[2], UInt<2>(0h2) connect _wdata_WIRE_5[3], UInt<2>(0h2) node wdata_5 = mux(doing_reset, _wdata_WIRE_5, s1_update_wdata) node _wmask_T_10 = not(UInt<4>(0h0)) node wmask_lo_5 = cat(s1_update_wmask[1], s1_update_wmask[0]) node wmask_hi_5 = cat(s1_update_wmask[3], s1_update_wmask[2]) node _wmask_T_11 = cat(wmask_hi_5, wmask_lo_5) node wmask_5 = mux(doing_reset, _wmask_T_10, _wmask_T_11) node _T_48 = bits(wmask_5, 0, 0) node _T_49 = bits(wmask_5, 1, 1) node _T_50 = bits(wmask_5, 2, 2) node _T_51 = bits(wmask_5, 3, 3) node _T_52 = or(widx_5, UInt<8>(0h0)) node _T_53 = bits(_T_52, 7, 0) write mport MPORT_5 = bim_col_5[_T_53], clock when _T_48 : connect MPORT_5[0], wdata_5[0] when _T_49 : connect MPORT_5[1], wdata_5[1] when _T_50 : connect MPORT_5[2], wdata_5[2] when _T_51 : connect MPORT_5[3], wdata_5[3] wire rdata_6 : UInt<2>[4] invalidate rdata_6[0] invalidate rdata_6[1] invalidate rdata_6[2] invalidate rdata_6[3] node ren_6 = bits(s0_col_mask, 6, 6) node _wen_T_60 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _wen_T_61 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _wen_T_62 = or(_wen_T_60, _wen_T_61) node _wen_T_63 = eq(_wen_T_62, UInt<1>(0h0)) node _wen_T_64 = and(s1_update.valid, _wen_T_63) node _wen_T_65 = bits(s1_update_col_mask, 6, 6) node _wen_T_66 = and(_wen_T_64, _wen_T_65) node _wen_T_67 = eq(ren_6, UInt<1>(0h0)) node _wen_T_68 = and(_wen_T_66, _wen_T_67) node _wen_T_69 = or(doing_reset, _wen_T_68) wire wen_6 : UInt<1> connect wen_6, _wen_T_69 reg REG_6 : UInt<2>[4], clock connect REG_6, rdata_6 connect s2_req_rdata_all[6], REG_6 smem bim_col_6 : UInt<2>[4] [256] node _r_T_18 = eq(wen_6, UInt<1>(0h0)) node _r_T_19 = and(ren_6, _r_T_18) wire _r_WIRE_6 : UInt<34> invalidate _r_WIRE_6 when _r_T_19 : connect _r_WIRE_6, s0_col_idx node _r_T_20 = bits(_r_WIRE_6, 7, 0) read mport r_6 = bim_col_6[_r_T_20], clock connect rdata_6, r_6 when wen_6 : node widx_6 = mux(doing_reset, reset_idx, s1_update_col_idx) wire _wdata_WIRE_6 : UInt<2>[4] connect _wdata_WIRE_6[0], UInt<2>(0h2) connect _wdata_WIRE_6[1], UInt<2>(0h2) connect _wdata_WIRE_6[2], UInt<2>(0h2) connect _wdata_WIRE_6[3], UInt<2>(0h2) node wdata_6 = mux(doing_reset, _wdata_WIRE_6, s1_update_wdata) node _wmask_T_12 = not(UInt<4>(0h0)) node wmask_lo_6 = cat(s1_update_wmask[1], s1_update_wmask[0]) node wmask_hi_6 = cat(s1_update_wmask[3], s1_update_wmask[2]) node _wmask_T_13 = cat(wmask_hi_6, wmask_lo_6) node wmask_6 = mux(doing_reset, _wmask_T_12, _wmask_T_13) node _T_54 = bits(wmask_6, 0, 0) node _T_55 = bits(wmask_6, 1, 1) node _T_56 = bits(wmask_6, 2, 2) node _T_57 = bits(wmask_6, 3, 3) node _T_58 = or(widx_6, UInt<8>(0h0)) node _T_59 = bits(_T_58, 7, 0) write mport MPORT_6 = bim_col_6[_T_59], clock when _T_54 : connect MPORT_6[0], wdata_6[0] when _T_55 : connect MPORT_6[1], wdata_6[1] when _T_56 : connect MPORT_6[2], wdata_6[2] when _T_57 : connect MPORT_6[3], wdata_6[3] wire rdata_7 : UInt<2>[4] invalidate rdata_7[0] invalidate rdata_7[1] invalidate rdata_7[2] invalidate rdata_7[3] node ren_7 = bits(s0_col_mask, 7, 7) node _wen_T_70 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _wen_T_71 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _wen_T_72 = or(_wen_T_70, _wen_T_71) node _wen_T_73 = eq(_wen_T_72, UInt<1>(0h0)) node _wen_T_74 = and(s1_update.valid, _wen_T_73) node _wen_T_75 = bits(s1_update_col_mask, 7, 7) node _wen_T_76 = and(_wen_T_74, _wen_T_75) node _wen_T_77 = eq(ren_7, UInt<1>(0h0)) node _wen_T_78 = and(_wen_T_76, _wen_T_77) node _wen_T_79 = or(doing_reset, _wen_T_78) wire wen_7 : UInt<1> connect wen_7, _wen_T_79 reg REG_7 : UInt<2>[4], clock connect REG_7, rdata_7 connect s2_req_rdata_all[7], REG_7 smem bim_col_7 : UInt<2>[4] [256] node _r_T_21 = eq(wen_7, UInt<1>(0h0)) node _r_T_22 = and(ren_7, _r_T_21) wire _r_WIRE_7 : UInt<34> invalidate _r_WIRE_7 when _r_T_22 : connect _r_WIRE_7, s0_col_idx node _r_T_23 = bits(_r_WIRE_7, 7, 0) read mport r_7 = bim_col_7[_r_T_23], clock connect rdata_7, r_7 when wen_7 : node widx_7 = mux(doing_reset, reset_idx, s1_update_col_idx) wire _wdata_WIRE_7 : UInt<2>[4] connect _wdata_WIRE_7[0], UInt<2>(0h2) connect _wdata_WIRE_7[1], UInt<2>(0h2) connect _wdata_WIRE_7[2], UInt<2>(0h2) connect _wdata_WIRE_7[3], UInt<2>(0h2) node wdata_7 = mux(doing_reset, _wdata_WIRE_7, s1_update_wdata) node _wmask_T_14 = not(UInt<4>(0h0)) node wmask_lo_7 = cat(s1_update_wmask[1], s1_update_wmask[0]) node wmask_hi_7 = cat(s1_update_wmask[3], s1_update_wmask[2]) node _wmask_T_15 = cat(wmask_hi_7, wmask_lo_7) node wmask_7 = mux(doing_reset, _wmask_T_14, _wmask_T_15) node _T_60 = bits(wmask_7, 0, 0) node _T_61 = bits(wmask_7, 1, 1) node _T_62 = bits(wmask_7, 2, 2) node _T_63 = bits(wmask_7, 3, 3) node _T_64 = or(widx_7, UInt<8>(0h0)) node _T_65 = bits(_T_64, 7, 0) write mport MPORT_7 = bim_col_7[_T_65], clock when _T_60 : connect MPORT_7[0], wdata_7[0] when _T_61 : connect MPORT_7[1], wdata_7[1] when _T_62 : connect MPORT_7[2], wdata_7[2] when _T_63 : connect MPORT_7[3], wdata_7[3] node _T_66 = or(s1_update_wmask[0], s1_update_wmask[1]) node _T_67 = or(_T_66, s1_update_wmask[2]) node _T_68 = or(_T_67, s1_update_wmask[3]) node _T_69 = and(_T_68, s1_update.valid) node _T_70 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_71 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_72 = or(_T_70, _T_71) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = and(_T_69, _T_73) when _T_74 : when wrbypass_hit : connect wrbypass[wrbypass_hit_idx], s1_update_wdata else : connect wrbypass[wrbypass_enq_idx], s1_update_wdata connect wrbypass_idxs[wrbypass_enq_idx], s1_update_idx node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1)) node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1) node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0) connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2
module BIMBranchPredictorBank( // @[bim.scala:30:7] input clock, // @[bim.scala:30:7] input reset, // @[bim.scala:30:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire [7:0] bim_col_7_MPORT_7_addr; // @[bim.scala:165:19] wire [7:0] bim_col_6_MPORT_6_addr; // @[bim.scala:165:19] wire [7:0] bim_col_5_MPORT_5_addr; // @[bim.scala:165:19] wire [7:0] bim_col_4_MPORT_4_addr; // @[bim.scala:165:19] wire [7:0] bim_col_3_MPORT_3_addr; // @[bim.scala:165:19] wire [7:0] bim_col_2_MPORT_2_addr; // @[bim.scala:165:19] wire [7:0] bim_col_1_MPORT_1_addr; // @[bim.scala:165:19] wire [7:0] bim_col_0_MPORT_addr; // @[bim.scala:165:19] wire [7:0] _bim_col_7_RW0_rdata; // @[bim.scala:157:29] wire [7:0] _bim_col_6_RW0_rdata; // @[bim.scala:157:29] wire [7:0] _bim_col_5_RW0_rdata; // @[bim.scala:157:29] wire [7:0] _bim_col_4_RW0_rdata; // @[bim.scala:157:29] wire [7:0] _bim_col_3_RW0_rdata; // @[bim.scala:157:29] wire [7:0] _bim_col_2_RW0_rdata; // @[bim.scala:157:29] wire [7:0] _bim_col_1_RW0_rdata; // @[bim.scala:157:29] wire [7:0] _bim_col_0_RW0_rdata; // @[bim.scala:157:29] wire io_f0_valid_0 = io_f0_valid; // @[bim.scala:30:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[bim.scala:30:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[bim.scala:30:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[bim.scala:30:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[bim.scala:30:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[bim.scala:30:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[bim.scala:30:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[bim.scala:30:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[bim.scala:30:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[bim.scala:30:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[bim.scala:30:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[bim.scala:30:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[bim.scala:30:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[bim.scala:30:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[bim.scala:30:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[bim.scala:30:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[bim.scala:30:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[bim.scala:30:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[bim.scala:30:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[bim.scala:30:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[bim.scala:30:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[bim.scala:30:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[bim.scala:30:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[bim.scala:30:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[bim.scala:30:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[bim.scala:30:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[bim.scala:30:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[bim.scala:30:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[bim.scala:30:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[bim.scala:30:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[bim.scala:30:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[bim.scala:30:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[bim.scala:30:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[bim.scala:30:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[bim.scala:30:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[bim.scala:30:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[bim.scala:30:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[bim.scala:30:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[bim.scala:30:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[bim.scala:30:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[bim.scala:30:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[bim.scala:30:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[bim.scala:30:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[bim.scala:30:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[bim.scala:30:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[bim.scala:30:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[bim.scala:30:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[bim.scala:30:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[bim.scala:30:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[bim.scala:30:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[bim.scala:30:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[bim.scala:30:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[bim.scala:30:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[bim.scala:30:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[bim.scala:30:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[bim.scala:30:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[bim.scala:30:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[bim.scala:30:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[bim.scala:30:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[bim.scala:30:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[bim.scala:30:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[bim.scala:30:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[bim.scala:30:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[bim.scala:30:7] wire io_f3_fire_0 = io_f3_fire; // @[bim.scala:30:7] wire io_update_valid_0 = io_update_valid; // @[bim.scala:30:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[bim.scala:30:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[bim.scala:30:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[bim.scala:30:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[bim.scala:30:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[bim.scala:30:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[bim.scala:30:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[bim.scala:30:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[bim.scala:30:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[bim.scala:30:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[bim.scala:30:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[bim.scala:30:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[bim.scala:30:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[bim.scala:30:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[bim.scala:30:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[bim.scala:30:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[bim.scala:30:7] wire [1:0] _wdata_WIRE_0 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_1 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_2 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_3 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_1_0 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_1_1 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_1_2 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_1_3 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_2_0 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_2_1 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_2_2 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_2_3 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_3_0 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_3_1 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_3_2 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_3_3 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_4_0 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_4_1 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_4_2 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_4_3 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_5_0 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_5_1 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_5_2 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_5_3 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_6_0 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_6_1 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_6_2 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_6_3 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_7_0 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_7_1 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_7_2 = 2'h2; // @[bim.scala:163:45] wire [1:0] _wdata_WIRE_7_3 = 2'h2; // @[bim.scala:163:45] wire [3:0] _wmask_T = 4'hF; // @[bim.scala:164:39] wire [3:0] _wmask_T_2 = 4'hF; // @[bim.scala:164:39] wire [3:0] _wmask_T_4 = 4'hF; // @[bim.scala:164:39] wire [3:0] _wmask_T_6 = 4'hF; // @[bim.scala:164:39] wire [3:0] _wmask_T_8 = 4'hF; // @[bim.scala:164:39] wire [3:0] _wmask_T_10 = 4'hF; // @[bim.scala:164:39] wire [3:0] _wmask_T_12 = 4'hF; // @[bim.scala:164:39] wire [3:0] _wmask_T_14 = 4'hF; // @[bim.scala:164:39] wire io_f1_lhist = 1'h0; // @[bim.scala:30:7] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[bim.scala:30:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[bim.scala:30:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[bim.scala:30:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[bim.scala:30:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[bim.scala:30:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[bim.scala:30:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[bim.scala:30:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[bim.scala:30:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[bim.scala:30:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[bim.scala:30:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[bim.scala:30:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[bim.scala:30:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[bim.scala:30:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[bim.scala:30:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[bim.scala:30:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[bim.scala:30:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[bim.scala:30:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[bim.scala:30:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[bim.scala:30:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[bim.scala:30:7] wire io_resp_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br_0; // @[bim.scala:30:7] wire io_resp_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal_0; // @[bim.scala:30:7] wire io_resp_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid_0; // @[bim.scala:30:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits_0; // @[bim.scala:30:7] wire io_resp_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br_0; // @[bim.scala:30:7] wire io_resp_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal_0; // @[bim.scala:30:7] wire io_resp_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid_0; // @[bim.scala:30:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits_0; // @[bim.scala:30:7] wire io_resp_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br_0; // @[bim.scala:30:7] wire io_resp_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal_0; // @[bim.scala:30:7] wire io_resp_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid_0; // @[bim.scala:30:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits_0; // @[bim.scala:30:7] wire io_resp_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br_0; // @[bim.scala:30:7] wire io_resp_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal_0; // @[bim.scala:30:7] wire io_resp_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid_0; // @[bim.scala:30:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits_0; // @[bim.scala:30:7] wire io_resp_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br_0; // @[bim.scala:30:7] wire io_resp_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal_0; // @[bim.scala:30:7] wire io_resp_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid_0; // @[bim.scala:30:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits_0; // @[bim.scala:30:7] wire io_resp_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br_0; // @[bim.scala:30:7] wire io_resp_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal_0; // @[bim.scala:30:7] wire io_resp_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid_0; // @[bim.scala:30:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits_0; // @[bim.scala:30:7] wire io_resp_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br_0; // @[bim.scala:30:7] wire io_resp_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal_0; // @[bim.scala:30:7] wire io_resp_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid_0; // @[bim.scala:30:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits_0; // @[bim.scala:30:7] wire io_resp_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br_0; // @[bim.scala:30:7] wire io_resp_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal_0; // @[bim.scala:30:7] wire io_resp_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid_0; // @[bim.scala:30:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits_0; // @[bim.scala:30:7] wire s2_resp_0; // @[bim.scala:71:29] wire s2_resp_1; // @[bim.scala:71:29] wire s2_resp_2; // @[bim.scala:71:29] wire s2_resp_3; // @[bim.scala:71:29] wire io_resp_f2_0_taken_0; // @[bim.scala:30:7] wire io_resp_f2_1_taken_0; // @[bim.scala:30:7] wire io_resp_f2_2_taken_0; // @[bim.scala:30:7] wire io_resp_f2_3_taken_0; // @[bim.scala:30:7] wire io_resp_f3_0_taken_0; // @[bim.scala:30:7] wire io_resp_f3_1_taken_0; // @[bim.scala:30:7] wire io_resp_f3_2_taken_0; // @[bim.scala:30:7] wire io_resp_f3_3_taken_0; // @[bim.scala:30:7] wire [119:0] io_f3_meta_0; // @[bim.scala:30:7] wire [36:0] s0_idx = io_f0_pc_0[39:3]; // @[frontend.scala:149:35] reg [36:0] s1_idx; // @[predictor.scala:163:29] reg [36:0] s2_idx; // @[predictor.scala:164:29] reg [36:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] wire [39:0] _s0_pc_T = ~io_f0_pc_0; // @[frontend.scala:147:33] wire [39:0] _s0_pc_T_1 = {_s0_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] s0_pc = ~_s0_pc_T_1; // @[frontend.scala:147:{31,39}] reg [39:0] s1_pc; // @[predictor.scala:178:22] reg [39:0] s2_pc; // @[predictor.scala:179:22] wire [36:0] s0_update_idx = io_update_bits_pc_0[39:3]; // @[frontend.scala:149:35] reg s1_update_valid; // @[predictor.scala:185:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:185:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:185:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:185:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:185:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:185:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:185:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:185:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:185:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:185:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:185:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:185:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:185:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:185:30] reg s1_update_bits_lhist; // @[predictor.scala:185:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:185:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:185:30] wire [39:0] _s1_update_bits_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _s1_update_bits_pc_T_1 = {_s1_update_bits_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _s1_update_bits_pc_T_2 = ~_s1_update_bits_pc_T_1; // @[frontend.scala:147:{31,39}] reg [36:0] s1_update_idx; // @[predictor.scala:187:30] reg s1_update_valid_0; // @[predictor.scala:188:32] wire [1:0] s2_req_rdata_0; // @[Mux.scala:30:73] wire [1:0] s2_req_rdata_1; // @[Mux.scala:30:73] wire [1:0] s2_req_rdata_2; // @[Mux.scala:30:73] wire [1:0] s2_req_rdata_3; // @[Mux.scala:30:73] wire [1:0] s2_meta_bims_0; // @[bim.scala:50:31] wire [1:0] s2_meta_bims_1; // @[bim.scala:50:31] wire [1:0] s2_meta_bims_2; // @[bim.scala:50:31] wire [1:0] s2_meta_bims_3; // @[bim.scala:50:31] wire [3:0] _GEN = {s2_meta_bims_1, s2_meta_bims_0}; // @[bim.scala:50:31, :51:35] wire [3:0] lo; // @[bim.scala:51:35] assign lo = _GEN; // @[bim.scala:51:35] wire [3:0] io_f3_meta_lo; // @[bim.scala:83:33] assign io_f3_meta_lo = _GEN; // @[bim.scala:51:35, :83:33] wire [3:0] _GEN_0 = {s2_meta_bims_3, s2_meta_bims_2}; // @[bim.scala:50:31, :51:35] wire [3:0] hi; // @[bim.scala:51:35] assign hi = _GEN_0; // @[bim.scala:51:35] wire [3:0] io_f3_meta_hi; // @[bim.scala:83:33] assign io_f3_meta_hi = _GEN_0; // @[bim.scala:51:35, :83:33] reg doing_reset; // @[bim.scala:53:28] reg [7:0] reset_idx; // @[bim.scala:54:26] wire [8:0] _reset_idx_T = {1'h0, reset_idx} + {8'h0, doing_reset}; // @[bim.scala:53:28, :54:26, :55:26] wire [7:0] _reset_idx_T_1 = _reset_idx_T[7:0]; // @[bim.scala:55:26] wire [2:0] _s0_col_mask_T = s0_idx[2:0]; // @[frontend.scala:149:35] wire [7:0] _s0_col_mask_T_1 = 8'h1 << _s0_col_mask_T; // @[OneHot.scala:58:35] wire [7:0] _s0_col_mask_T_2 = {8{io_f0_valid_0}}; // @[bim.scala:30:7, :63:65] wire [7:0] s0_col_mask = _s0_col_mask_T_1 & _s0_col_mask_T_2; // @[OneHot.scala:58:35] reg [7:0] s1_col_mask; // @[bim.scala:64:28] wire [33:0] s0_col_idx = s0_idx[36:3]; // @[frontend.scala:149:35] wire [33:0] _r_WIRE = s0_col_idx; // @[bim.scala:65:28, :159:49] wire [33:0] _r_WIRE_1 = s0_col_idx; // @[bim.scala:65:28, :159:49] wire [33:0] _r_WIRE_2 = s0_col_idx; // @[bim.scala:65:28, :159:49] wire [33:0] _r_WIRE_3 = s0_col_idx; // @[bim.scala:65:28, :159:49] wire [33:0] _r_WIRE_4 = s0_col_idx; // @[bim.scala:65:28, :159:49] wire [33:0] _r_WIRE_5 = s0_col_idx; // @[bim.scala:65:28, :159:49] wire [33:0] _r_WIRE_6 = s0_col_idx; // @[bim.scala:65:28, :159:49] wire [33:0] _r_WIRE_7 = s0_col_idx; // @[bim.scala:65:28, :159:49] reg [33:0] s1_col_idx; // @[bim.scala:66:28] wire [1:0] s2_req_rdata_all_0_0; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_0_1; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_0_2; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_0_3; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_1_0; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_1_1; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_1_2; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_1_3; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_2_0; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_2_1; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_2_2; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_2_3; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_3_0; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_3_1; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_3_2; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_3_3; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_4_0; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_4_1; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_4_2; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_4_3; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_5_0; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_5_1; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_5_2; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_5_3; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_6_0; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_6_1; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_6_2; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_6_3; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_7_0; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_7_1; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_7_2; // @[bim.scala:68:30] wire [1:0] s2_req_rdata_all_7_3; // @[bim.scala:68:30] reg [7:0] s2_req_rdata_REG; // @[bim.scala:69:35] wire _s2_req_rdata_T = s2_req_rdata_REG[0]; // @[Mux.scala:32:36] wire _s2_req_rdata_T_1 = s2_req_rdata_REG[1]; // @[Mux.scala:32:36] wire _s2_req_rdata_T_2 = s2_req_rdata_REG[2]; // @[Mux.scala:32:36] wire _s2_req_rdata_T_3 = s2_req_rdata_REG[3]; // @[Mux.scala:32:36] wire _s2_req_rdata_T_4 = s2_req_rdata_REG[4]; // @[Mux.scala:32:36] wire _s2_req_rdata_T_5 = s2_req_rdata_REG[5]; // @[Mux.scala:32:36] wire _s2_req_rdata_T_6 = s2_req_rdata_REG[6]; // @[Mux.scala:32:36] wire _s2_req_rdata_T_7 = s2_req_rdata_REG[7]; // @[Mux.scala:32:36] wire [1:0] _s2_req_rdata_WIRE; // @[Mux.scala:30:73] assign s2_meta_bims_0 = s2_req_rdata_0; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_WIRE_1; // @[Mux.scala:30:73] assign s2_meta_bims_1 = s2_req_rdata_1; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_WIRE_2; // @[Mux.scala:30:73] assign s2_meta_bims_2 = s2_req_rdata_2; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_WIRE_3; // @[Mux.scala:30:73] assign s2_meta_bims_3 = s2_req_rdata_3; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_8 = _s2_req_rdata_T ? s2_req_rdata_all_0_0 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_9 = _s2_req_rdata_T_1 ? s2_req_rdata_all_1_0 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_10 = _s2_req_rdata_T_2 ? s2_req_rdata_all_2_0 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_11 = _s2_req_rdata_T_3 ? s2_req_rdata_all_3_0 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_12 = _s2_req_rdata_T_4 ? s2_req_rdata_all_4_0 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_13 = _s2_req_rdata_T_5 ? s2_req_rdata_all_5_0 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_14 = _s2_req_rdata_T_6 ? s2_req_rdata_all_6_0 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_15 = _s2_req_rdata_T_7 ? s2_req_rdata_all_7_0 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_16 = _s2_req_rdata_T_8 | _s2_req_rdata_T_9; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_17 = _s2_req_rdata_T_16 | _s2_req_rdata_T_10; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_18 = _s2_req_rdata_T_17 | _s2_req_rdata_T_11; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_19 = _s2_req_rdata_T_18 | _s2_req_rdata_T_12; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_20 = _s2_req_rdata_T_19 | _s2_req_rdata_T_13; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_21 = _s2_req_rdata_T_20 | _s2_req_rdata_T_14; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_22 = _s2_req_rdata_T_21 | _s2_req_rdata_T_15; // @[Mux.scala:30:73] assign _s2_req_rdata_WIRE = _s2_req_rdata_T_22; // @[Mux.scala:30:73] assign s2_req_rdata_0 = _s2_req_rdata_WIRE; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_23 = _s2_req_rdata_T ? s2_req_rdata_all_0_1 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_24 = _s2_req_rdata_T_1 ? s2_req_rdata_all_1_1 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_25 = _s2_req_rdata_T_2 ? s2_req_rdata_all_2_1 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_26 = _s2_req_rdata_T_3 ? s2_req_rdata_all_3_1 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_27 = _s2_req_rdata_T_4 ? s2_req_rdata_all_4_1 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_28 = _s2_req_rdata_T_5 ? s2_req_rdata_all_5_1 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_29 = _s2_req_rdata_T_6 ? s2_req_rdata_all_6_1 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_30 = _s2_req_rdata_T_7 ? s2_req_rdata_all_7_1 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_31 = _s2_req_rdata_T_23 | _s2_req_rdata_T_24; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_32 = _s2_req_rdata_T_31 | _s2_req_rdata_T_25; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_33 = _s2_req_rdata_T_32 | _s2_req_rdata_T_26; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_34 = _s2_req_rdata_T_33 | _s2_req_rdata_T_27; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_35 = _s2_req_rdata_T_34 | _s2_req_rdata_T_28; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_36 = _s2_req_rdata_T_35 | _s2_req_rdata_T_29; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_37 = _s2_req_rdata_T_36 | _s2_req_rdata_T_30; // @[Mux.scala:30:73] assign _s2_req_rdata_WIRE_1 = _s2_req_rdata_T_37; // @[Mux.scala:30:73] assign s2_req_rdata_1 = _s2_req_rdata_WIRE_1; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_38 = _s2_req_rdata_T ? s2_req_rdata_all_0_2 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_39 = _s2_req_rdata_T_1 ? s2_req_rdata_all_1_2 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_40 = _s2_req_rdata_T_2 ? s2_req_rdata_all_2_2 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_41 = _s2_req_rdata_T_3 ? s2_req_rdata_all_3_2 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_42 = _s2_req_rdata_T_4 ? s2_req_rdata_all_4_2 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_43 = _s2_req_rdata_T_5 ? s2_req_rdata_all_5_2 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_44 = _s2_req_rdata_T_6 ? s2_req_rdata_all_6_2 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_45 = _s2_req_rdata_T_7 ? s2_req_rdata_all_7_2 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_46 = _s2_req_rdata_T_38 | _s2_req_rdata_T_39; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_47 = _s2_req_rdata_T_46 | _s2_req_rdata_T_40; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_48 = _s2_req_rdata_T_47 | _s2_req_rdata_T_41; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_49 = _s2_req_rdata_T_48 | _s2_req_rdata_T_42; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_50 = _s2_req_rdata_T_49 | _s2_req_rdata_T_43; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_51 = _s2_req_rdata_T_50 | _s2_req_rdata_T_44; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_52 = _s2_req_rdata_T_51 | _s2_req_rdata_T_45; // @[Mux.scala:30:73] assign _s2_req_rdata_WIRE_2 = _s2_req_rdata_T_52; // @[Mux.scala:30:73] assign s2_req_rdata_2 = _s2_req_rdata_WIRE_2; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_53 = _s2_req_rdata_T ? s2_req_rdata_all_0_3 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_54 = _s2_req_rdata_T_1 ? s2_req_rdata_all_1_3 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_55 = _s2_req_rdata_T_2 ? s2_req_rdata_all_2_3 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_56 = _s2_req_rdata_T_3 ? s2_req_rdata_all_3_3 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_57 = _s2_req_rdata_T_4 ? s2_req_rdata_all_4_3 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_58 = _s2_req_rdata_T_5 ? s2_req_rdata_all_5_3 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_59 = _s2_req_rdata_T_6 ? s2_req_rdata_all_6_3 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_60 = _s2_req_rdata_T_7 ? s2_req_rdata_all_7_3 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_req_rdata_T_61 = _s2_req_rdata_T_53 | _s2_req_rdata_T_54; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_62 = _s2_req_rdata_T_61 | _s2_req_rdata_T_55; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_63 = _s2_req_rdata_T_62 | _s2_req_rdata_T_56; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_64 = _s2_req_rdata_T_63 | _s2_req_rdata_T_57; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_65 = _s2_req_rdata_T_64 | _s2_req_rdata_T_58; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_66 = _s2_req_rdata_T_65 | _s2_req_rdata_T_59; // @[Mux.scala:30:73] wire [1:0] _s2_req_rdata_T_67 = _s2_req_rdata_T_66 | _s2_req_rdata_T_60; // @[Mux.scala:30:73] assign _s2_req_rdata_WIRE_3 = _s2_req_rdata_T_67; // @[Mux.scala:30:73] assign s2_req_rdata_3 = _s2_req_rdata_WIRE_3; // @[Mux.scala:30:73] wire _s2_resp_0_T_3; // @[bim.scala:75:57] assign io_resp_f2_0_taken_0 = s2_resp_0; // @[bim.scala:30:7, :71:29] wire _s2_resp_1_T_3; // @[bim.scala:75:57] assign io_resp_f2_1_taken_0 = s2_resp_1; // @[bim.scala:30:7, :71:29] wire _s2_resp_2_T_3; // @[bim.scala:75:57] assign io_resp_f2_2_taken_0 = s2_resp_2; // @[bim.scala:30:7, :71:29] wire _s2_resp_3_T_3; // @[bim.scala:75:57] assign io_resp_f2_3_taken_0 = s2_resp_3; // @[bim.scala:30:7, :71:29] wire _s2_resp_0_T = s2_req_rdata_0[1]; // @[Mux.scala:30:73] wire _s2_resp_0_T_1 = s2_valid & _s2_resp_0_T; // @[predictor.scala:169:25] wire _s2_resp_0_T_2 = ~doing_reset; // @[bim.scala:53:28, :75:60] assign _s2_resp_0_T_3 = _s2_resp_0_T_1 & _s2_resp_0_T_2; // @[bim.scala:75:{35,57,60}] assign s2_resp_0 = _s2_resp_0_T_3; // @[bim.scala:71:29, :75:57] reg io_resp_f3_0_taken_REG; // @[bim.scala:81:35] assign io_resp_f3_0_taken_0 = io_resp_f3_0_taken_REG; // @[bim.scala:30:7, :81:35] wire _s2_resp_1_T = s2_req_rdata_1[1]; // @[Mux.scala:30:73] wire _s2_resp_1_T_1 = s2_valid & _s2_resp_1_T; // @[predictor.scala:169:25] wire _s2_resp_1_T_2 = ~doing_reset; // @[bim.scala:53:28, :75:60] assign _s2_resp_1_T_3 = _s2_resp_1_T_1 & _s2_resp_1_T_2; // @[bim.scala:75:{35,57,60}] assign s2_resp_1 = _s2_resp_1_T_3; // @[bim.scala:71:29, :75:57] reg io_resp_f3_1_taken_REG; // @[bim.scala:81:35] assign io_resp_f3_1_taken_0 = io_resp_f3_1_taken_REG; // @[bim.scala:30:7, :81:35] wire _s2_resp_2_T = s2_req_rdata_2[1]; // @[Mux.scala:30:73] wire _s2_resp_2_T_1 = s2_valid & _s2_resp_2_T; // @[predictor.scala:169:25] wire _s2_resp_2_T_2 = ~doing_reset; // @[bim.scala:53:28, :75:60] assign _s2_resp_2_T_3 = _s2_resp_2_T_1 & _s2_resp_2_T_2; // @[bim.scala:75:{35,57,60}] assign s2_resp_2 = _s2_resp_2_T_3; // @[bim.scala:71:29, :75:57] reg io_resp_f3_2_taken_REG; // @[bim.scala:81:35] assign io_resp_f3_2_taken_0 = io_resp_f3_2_taken_REG; // @[bim.scala:30:7, :81:35] wire _s2_resp_3_T = s2_req_rdata_3[1]; // @[Mux.scala:30:73] wire _s2_resp_3_T_1 = s2_valid & _s2_resp_3_T; // @[predictor.scala:169:25] wire _s2_resp_3_T_2 = ~doing_reset; // @[bim.scala:53:28, :75:60] assign _s2_resp_3_T_3 = _s2_resp_3_T_1 & _s2_resp_3_T_2; // @[bim.scala:75:{35,57,60}] assign s2_resp_3 = _s2_resp_3_T_3; // @[bim.scala:71:29, :75:57] reg io_resp_f3_3_taken_REG; // @[bim.scala:81:35] assign io_resp_f3_3_taken_0 = io_resp_f3_3_taken_REG; // @[bim.scala:30:7, :81:35] wire [7:0] _io_f3_meta_T = {io_f3_meta_hi, io_f3_meta_lo}; // @[bim.scala:83:33] reg [7:0] io_f3_meta_REG; // @[bim.scala:83:24] assign io_f3_meta_0 = {112'h0, io_f3_meta_REG}; // @[bim.scala:30:7, :83:{14,24}] wire [1:0] _s1_update_wdata_0_T_9; // @[bim.scala:46:8] wire [1:0] _s1_update_wdata_1_T_9; // @[bim.scala:46:8] wire [1:0] _s1_update_wdata_2_T_9; // @[bim.scala:46:8] wire [1:0] _s1_update_wdata_3_T_9; // @[bim.scala:46:8] wire [1:0] s1_update_wdata_0; // @[bim.scala:85:31] wire [1:0] s1_update_wdata_1; // @[bim.scala:85:31] wire [1:0] s1_update_wdata_2; // @[bim.scala:85:31] wire [1:0] s1_update_wdata_3; // @[bim.scala:85:31] wire s1_update_wmask_0; // @[bim.scala:86:31] wire s1_update_wmask_1; // @[bim.scala:86:31] wire s1_update_wmask_2; // @[bim.scala:86:31] wire s1_update_wmask_3; // @[bim.scala:86:31] wire [1:0] _s1_update_meta_T; // @[bim.scala:87:55] wire [1:0] _s1_update_meta_T_1; // @[bim.scala:87:55] wire [1:0] _s1_update_meta_T_2; // @[bim.scala:87:55] wire [1:0] _s1_update_meta_T_3; // @[bim.scala:87:55] wire [1:0] s1_update_meta_bims_0; // @[bim.scala:87:55] wire [1:0] s1_update_meta_bims_1; // @[bim.scala:87:55] wire [1:0] s1_update_meta_bims_2; // @[bim.scala:87:55] wire [1:0] s1_update_meta_bims_3; // @[bim.scala:87:55] wire [7:0] _s1_update_meta_WIRE = s1_update_bits_meta[7:0]; // @[predictor.scala:185:30] assign _s1_update_meta_T = _s1_update_meta_WIRE[1:0]; // @[bim.scala:87:55] assign s1_update_meta_bims_0 = _s1_update_meta_T; // @[bim.scala:87:55] assign _s1_update_meta_T_1 = _s1_update_meta_WIRE[3:2]; // @[bim.scala:87:55] assign s1_update_meta_bims_1 = _s1_update_meta_T_1; // @[bim.scala:87:55] assign _s1_update_meta_T_2 = _s1_update_meta_WIRE[5:4]; // @[bim.scala:87:55] assign s1_update_meta_bims_2 = _s1_update_meta_T_2; // @[bim.scala:87:55] assign _s1_update_meta_T_3 = _s1_update_meta_WIRE[7:6]; // @[bim.scala:87:55] assign s1_update_meta_bims_3 = _s1_update_meta_T_3; // @[bim.scala:87:55] wire [2:0] _s1_update_col_mask_T = s1_update_idx[2:0]; // @[predictor.scala:187:30] wire [7:0] s1_update_col_mask = 8'h1 << _s1_update_col_mask_T; // @[OneHot.scala:58:35] wire [33:0] s1_update_col_idx = s1_update_idx[36:3]; // @[predictor.scala:187:30] reg [10:0] wrbypass_idxs_0; // @[bim.scala:91:26] reg [10:0] wrbypass_idxs_1; // @[bim.scala:91:26] reg [1:0] wrbypass_0_0; // @[bim.scala:92:26] reg [1:0] wrbypass_0_1; // @[bim.scala:92:26] reg [1:0] wrbypass_0_2; // @[bim.scala:92:26] reg [1:0] wrbypass_0_3; // @[bim.scala:92:26] reg [1:0] wrbypass_1_0; // @[bim.scala:92:26] reg [1:0] wrbypass_1_1; // @[bim.scala:92:26] reg [1:0] wrbypass_1_2; // @[bim.scala:92:26] reg [1:0] wrbypass_1_3; // @[bim.scala:92:26] reg wrbypass_enq_idx; // @[bim.scala:93:33] wire _wrbypass_hits_T = ~doing_reset; // @[bim.scala:53:28, :75:60, :96:5] wire [10:0] _wrbypass_hits_T_1 = s1_update_idx[10:0]; // @[predictor.scala:187:30] wire [10:0] _wrbypass_hits_T_5 = s1_update_idx[10:0]; // @[predictor.scala:187:30] wire _wrbypass_hits_T_2 = wrbypass_idxs_0 == _wrbypass_hits_T_1; // @[bim.scala:91:26, :97:{22,39}] wire _wrbypass_hits_T_3 = _wrbypass_hits_T & _wrbypass_hits_T_2; // @[bim.scala:96:{5,18}, :97:22] wire wrbypass_hits_0 = _wrbypass_hits_T_3; // @[bim.scala:95:30, :96:18] wire _wrbypass_hits_T_4 = ~doing_reset; // @[bim.scala:53:28, :75:60, :96:5] wire _wrbypass_hits_T_6 = wrbypass_idxs_1 == _wrbypass_hits_T_5; // @[bim.scala:91:26, :97:{22,39}] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_4 & _wrbypass_hits_T_6; // @[bim.scala:96:{5,18}, :97:22] wire wrbypass_hits_1 = _wrbypass_hits_T_7; // @[bim.scala:95:30, :96:18] wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[bim.scala:95:30, :99:44] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [40:0] _update_pc_T = {1'h0, s1_update_bits_pc}; // @[predictor.scala:185:30] wire [39:0] update_pc = _update_pc_T[39:0]; // @[bim.scala:108:39] wire _was_taken_T_2 = s1_update_bits_br_mask[0]; // @[predictor.scala:185:30] wire _was_taken_T = s1_update_bits_cfi_idx_bits == 2'h0; // @[predictor.scala:185:30] assign s1_update_wmask_0 = _was_taken_T_2 | s1_update_bits_cfi_idx_valid & _was_taken_T; // @[predictor.scala:185:30] wire _was_taken_T_1 = s1_update_bits_cfi_idx_valid & _was_taken_T; // @[predictor.scala:185:30] wire _was_taken_T_3 = s1_update_bits_cfi_is_br & _was_taken_T_2; // @[predictor.scala:185:30] wire _was_taken_T_4 = _was_taken_T_3 & s1_update_bits_cfi_taken; // @[predictor.scala:185:30] wire _was_taken_T_5 = _was_taken_T_4 | s1_update_bits_cfi_is_jal; // @[predictor.scala:185:30] wire was_taken = _was_taken_T_1 & _was_taken_T_5; // @[bim.scala:113:38, :114:47, :116:95] wire [1:0] old_bim_value = wrbypass_hit ? (wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0) : s1_update_meta_bims_0; // @[Mux.scala:50:70] wire s1_update_wdata_0_old_bim_sat_taken = &old_bim_value; // @[bim.scala:44:32, :120:30] wire s1_update_wdata_0_old_bim_sat_ntaken = old_bim_value == 2'h0; // @[bim.scala:45:32, :120:30] wire _s1_update_wdata_0_T = s1_update_wdata_0_old_bim_sat_taken & was_taken; // @[bim.scala:44:32, :46:28, :114:47] wire _s1_update_wdata_0_T_1 = ~was_taken; // @[bim.scala:47:33, :114:47] wire _s1_update_wdata_0_T_2 = s1_update_wdata_0_old_bim_sat_ntaken & _s1_update_wdata_0_T_1; // @[bim.scala:45:32, :47:{30,33}] wire [2:0] _GEN_1 = {1'h0, old_bim_value}; // @[bim.scala:48:20, :120:30] wire [2:0] _s1_update_wdata_0_T_3 = _GEN_1 + 3'h1; // @[bim.scala:48:20] wire [1:0] _s1_update_wdata_0_T_4 = _s1_update_wdata_0_T_3[1:0]; // @[bim.scala:48:20] wire [2:0] _s1_update_wdata_0_T_5 = _GEN_1 - 3'h1; // @[bim.scala:48:{20,29}] wire [1:0] _s1_update_wdata_0_T_6 = _s1_update_wdata_0_T_5[1:0]; // @[bim.scala:48:29] wire [1:0] _s1_update_wdata_0_T_7 = was_taken ? _s1_update_wdata_0_T_4 : _s1_update_wdata_0_T_6; // @[bim.scala:48:{10,20,29}, :114:47] wire [1:0] _s1_update_wdata_0_T_8 = _s1_update_wdata_0_T_2 ? 2'h0 : _s1_update_wdata_0_T_7; // @[bim.scala:47:{10,30}, :48:10] assign _s1_update_wdata_0_T_9 = _s1_update_wdata_0_T ? 2'h3 : _s1_update_wdata_0_T_8; // @[bim.scala:46:{8,28}, :47:10] assign s1_update_wdata_0 = _s1_update_wdata_0_T_9; // @[bim.scala:46:8, :85:31] wire [40:0] _update_pc_T_1 = _update_pc_T + 41'h2; // @[bim.scala:108:39] wire [39:0] update_pc_1 = _update_pc_T_1[39:0]; // @[bim.scala:108:39] wire _was_taken_T_8 = s1_update_bits_br_mask[1]; // @[predictor.scala:185:30] wire _was_taken_T_6 = s1_update_bits_cfi_idx_bits == 2'h1; // @[predictor.scala:185:30] assign s1_update_wmask_1 = _was_taken_T_8 | s1_update_bits_cfi_idx_valid & _was_taken_T_6; // @[predictor.scala:185:30] wire _was_taken_T_7 = s1_update_bits_cfi_idx_valid & _was_taken_T_6; // @[predictor.scala:185:30] wire _was_taken_T_9 = s1_update_bits_cfi_is_br & _was_taken_T_8; // @[predictor.scala:185:30] wire _was_taken_T_10 = _was_taken_T_9 & s1_update_bits_cfi_taken; // @[predictor.scala:185:30] wire _was_taken_T_11 = _was_taken_T_10 | s1_update_bits_cfi_is_jal; // @[predictor.scala:185:30] wire was_taken_1 = _was_taken_T_7 & _was_taken_T_11; // @[bim.scala:113:38, :114:47, :116:95] wire [1:0] old_bim_value_1 = wrbypass_hit ? (wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1) : s1_update_meta_bims_1; // @[Mux.scala:50:70] wire s1_update_wdata_1_old_bim_sat_taken = &old_bim_value_1; // @[bim.scala:44:32, :120:30] wire s1_update_wdata_1_old_bim_sat_ntaken = old_bim_value_1 == 2'h0; // @[bim.scala:45:32, :120:30] wire _s1_update_wdata_1_T = s1_update_wdata_1_old_bim_sat_taken & was_taken_1; // @[bim.scala:44:32, :46:28, :114:47] wire _s1_update_wdata_1_T_1 = ~was_taken_1; // @[bim.scala:47:33, :114:47] wire _s1_update_wdata_1_T_2 = s1_update_wdata_1_old_bim_sat_ntaken & _s1_update_wdata_1_T_1; // @[bim.scala:45:32, :47:{30,33}] wire [2:0] _GEN_2 = {1'h0, old_bim_value_1}; // @[bim.scala:48:20, :120:30] wire [2:0] _s1_update_wdata_1_T_3 = _GEN_2 + 3'h1; // @[bim.scala:48:20] wire [1:0] _s1_update_wdata_1_T_4 = _s1_update_wdata_1_T_3[1:0]; // @[bim.scala:48:20] wire [2:0] _s1_update_wdata_1_T_5 = _GEN_2 - 3'h1; // @[bim.scala:48:{20,29}] wire [1:0] _s1_update_wdata_1_T_6 = _s1_update_wdata_1_T_5[1:0]; // @[bim.scala:48:29] wire [1:0] _s1_update_wdata_1_T_7 = was_taken_1 ? _s1_update_wdata_1_T_4 : _s1_update_wdata_1_T_6; // @[bim.scala:48:{10,20,29}, :114:47] wire [1:0] _s1_update_wdata_1_T_8 = _s1_update_wdata_1_T_2 ? 2'h0 : _s1_update_wdata_1_T_7; // @[bim.scala:47:{10,30}, :48:10] assign _s1_update_wdata_1_T_9 = _s1_update_wdata_1_T ? 2'h3 : _s1_update_wdata_1_T_8; // @[bim.scala:46:{8,28}, :47:10] assign s1_update_wdata_1 = _s1_update_wdata_1_T_9; // @[bim.scala:46:8, :85:31] wire [40:0] _update_pc_T_2 = _update_pc_T + 41'h4; // @[bim.scala:108:39] wire [39:0] update_pc_2 = _update_pc_T_2[39:0]; // @[bim.scala:108:39] wire _was_taken_T_14 = s1_update_bits_br_mask[2]; // @[predictor.scala:185:30] wire _was_taken_T_12 = s1_update_bits_cfi_idx_bits == 2'h2; // @[predictor.scala:185:30] assign s1_update_wmask_2 = _was_taken_T_14 | s1_update_bits_cfi_idx_valid & _was_taken_T_12; // @[predictor.scala:185:30] wire _was_taken_T_13 = s1_update_bits_cfi_idx_valid & _was_taken_T_12; // @[predictor.scala:185:30] wire _was_taken_T_15 = s1_update_bits_cfi_is_br & _was_taken_T_14; // @[predictor.scala:185:30] wire _was_taken_T_16 = _was_taken_T_15 & s1_update_bits_cfi_taken; // @[predictor.scala:185:30] wire _was_taken_T_17 = _was_taken_T_16 | s1_update_bits_cfi_is_jal; // @[predictor.scala:185:30] wire was_taken_2 = _was_taken_T_13 & _was_taken_T_17; // @[bim.scala:113:38, :114:47, :116:95] wire [1:0] old_bim_value_2 = wrbypass_hit ? (wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2) : s1_update_meta_bims_2; // @[Mux.scala:50:70] wire s1_update_wdata_2_old_bim_sat_taken = &old_bim_value_2; // @[bim.scala:44:32, :120:30] wire s1_update_wdata_2_old_bim_sat_ntaken = old_bim_value_2 == 2'h0; // @[bim.scala:45:32, :120:30] wire _s1_update_wdata_2_T = s1_update_wdata_2_old_bim_sat_taken & was_taken_2; // @[bim.scala:44:32, :46:28, :114:47] wire _s1_update_wdata_2_T_1 = ~was_taken_2; // @[bim.scala:47:33, :114:47] wire _s1_update_wdata_2_T_2 = s1_update_wdata_2_old_bim_sat_ntaken & _s1_update_wdata_2_T_1; // @[bim.scala:45:32, :47:{30,33}] wire [2:0] _GEN_3 = {1'h0, old_bim_value_2}; // @[bim.scala:48:20, :120:30] wire [2:0] _s1_update_wdata_2_T_3 = _GEN_3 + 3'h1; // @[bim.scala:48:20] wire [1:0] _s1_update_wdata_2_T_4 = _s1_update_wdata_2_T_3[1:0]; // @[bim.scala:48:20] wire [2:0] _s1_update_wdata_2_T_5 = _GEN_3 - 3'h1; // @[bim.scala:48:{20,29}] wire [1:0] _s1_update_wdata_2_T_6 = _s1_update_wdata_2_T_5[1:0]; // @[bim.scala:48:29] wire [1:0] _s1_update_wdata_2_T_7 = was_taken_2 ? _s1_update_wdata_2_T_4 : _s1_update_wdata_2_T_6; // @[bim.scala:48:{10,20,29}, :114:47] wire [1:0] _s1_update_wdata_2_T_8 = _s1_update_wdata_2_T_2 ? 2'h0 : _s1_update_wdata_2_T_7; // @[bim.scala:47:{10,30}, :48:10] assign _s1_update_wdata_2_T_9 = _s1_update_wdata_2_T ? 2'h3 : _s1_update_wdata_2_T_8; // @[bim.scala:46:{8,28}, :47:10] assign s1_update_wdata_2 = _s1_update_wdata_2_T_9; // @[bim.scala:46:8, :85:31] wire [40:0] _update_pc_T_3 = _update_pc_T + 41'h6; // @[bim.scala:108:39] wire [39:0] update_pc_3 = _update_pc_T_3[39:0]; // @[bim.scala:108:39] wire _was_taken_T_20 = s1_update_bits_br_mask[3]; // @[predictor.scala:185:30] assign s1_update_wmask_3 = _was_taken_T_20 | s1_update_bits_cfi_idx_valid & (&s1_update_bits_cfi_idx_bits); // @[predictor.scala:185:30] wire _was_taken_T_18 = &s1_update_bits_cfi_idx_bits; // @[predictor.scala:185:30] wire _was_taken_T_19 = s1_update_bits_cfi_idx_valid & _was_taken_T_18; // @[predictor.scala:185:30] wire _was_taken_T_21 = s1_update_bits_cfi_is_br & _was_taken_T_20; // @[predictor.scala:185:30] wire _was_taken_T_22 = _was_taken_T_21 & s1_update_bits_cfi_taken; // @[predictor.scala:185:30] wire _was_taken_T_23 = _was_taken_T_22 | s1_update_bits_cfi_is_jal; // @[predictor.scala:185:30] wire was_taken_3 = _was_taken_T_19 & _was_taken_T_23; // @[bim.scala:113:38, :114:47, :116:95] wire [1:0] old_bim_value_3 = wrbypass_hit ? (wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3) : s1_update_meta_bims_3; // @[Mux.scala:50:70] wire s1_update_wdata_3_old_bim_sat_taken = &old_bim_value_3; // @[bim.scala:44:32, :120:30] wire s1_update_wdata_3_old_bim_sat_ntaken = old_bim_value_3 == 2'h0; // @[bim.scala:45:32, :120:30] wire _s1_update_wdata_3_T = s1_update_wdata_3_old_bim_sat_taken & was_taken_3; // @[bim.scala:44:32, :46:28, :114:47] wire _s1_update_wdata_3_T_1 = ~was_taken_3; // @[bim.scala:47:33, :114:47] wire _s1_update_wdata_3_T_2 = s1_update_wdata_3_old_bim_sat_ntaken & _s1_update_wdata_3_T_1; // @[bim.scala:45:32, :47:{30,33}] wire [2:0] _GEN_4 = {1'h0, old_bim_value_3}; // @[bim.scala:48:20, :120:30] wire [2:0] _s1_update_wdata_3_T_3 = _GEN_4 + 3'h1; // @[bim.scala:48:20] wire [1:0] _s1_update_wdata_3_T_4 = _s1_update_wdata_3_T_3[1:0]; // @[bim.scala:48:20] wire [2:0] _s1_update_wdata_3_T_5 = _GEN_4 - 3'h1; // @[bim.scala:48:{20,29}] wire [1:0] _s1_update_wdata_3_T_6 = _s1_update_wdata_3_T_5[1:0]; // @[bim.scala:48:29] wire [1:0] _s1_update_wdata_3_T_7 = was_taken_3 ? _s1_update_wdata_3_T_4 : _s1_update_wdata_3_T_6; // @[bim.scala:48:{10,20,29}, :114:47] wire [1:0] _s1_update_wdata_3_T_8 = _s1_update_wdata_3_T_2 ? 2'h0 : _s1_update_wdata_3_T_7; // @[bim.scala:47:{10,30}, :48:10] assign _s1_update_wdata_3_T_9 = _s1_update_wdata_3_T ? 2'h3 : _s1_update_wdata_3_T_8; // @[bim.scala:46:{8,28}, :47:10] assign s1_update_wdata_3 = _s1_update_wdata_3_T_9; // @[bim.scala:46:8, :85:31] wire [1:0] rdata_0; // @[bim.scala:133:21] wire [1:0] rdata_1; // @[bim.scala:133:21] wire [1:0] rdata_2; // @[bim.scala:133:21] wire [1:0] rdata_3; // @[bim.scala:133:21] wire ren = s0_col_mask[0]; // @[bim.scala:63:59, :135:86] wire _T_70 = s1_update_bits_is_mispredict_update | s1_update_bits_is_repair_update; // @[predictor.scala:96:49, :185:30] wire _wen_T; // @[predictor.scala:96:49] assign _wen_T = _T_70; // @[predictor.scala:96:49] wire _wen_T_10; // @[predictor.scala:96:49] assign _wen_T_10 = _T_70; // @[predictor.scala:96:49] wire _wen_T_20; // @[predictor.scala:96:49] assign _wen_T_20 = _T_70; // @[predictor.scala:96:49] wire _wen_T_30; // @[predictor.scala:96:49] assign _wen_T_30 = _T_70; // @[predictor.scala:96:49] wire _wen_T_40; // @[predictor.scala:96:49] assign _wen_T_40 = _T_70; // @[predictor.scala:96:49] wire _wen_T_50; // @[predictor.scala:96:49] assign _wen_T_50 = _T_70; // @[predictor.scala:96:49] wire _wen_T_60; // @[predictor.scala:96:49] assign _wen_T_60 = _T_70; // @[predictor.scala:96:49] wire _wen_T_70; // @[predictor.scala:96:49] assign _wen_T_70 = _T_70; // @[predictor.scala:96:49] wire _wen_T_1 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _wen_T_2 = _wen_T | _wen_T_1; // @[predictor.scala:94:50, :96:{49,69}] wire _wen_T_3 = ~_wen_T_2; // @[predictor.scala:96:{26,69}] wire _wen_T_4 = s1_update_valid & _wen_T_3; // @[predictor.scala:96:26, :185:30] wire _wen_T_5 = s1_update_col_mask[0]; // @[OneHot.scala:58:35] wire _wen_T_6 = _wen_T_4 & _wen_T_5; // @[bim.scala:136:{56,91,112}] wire _wen_T_7 = ~ren; // @[bim.scala:135:86, :136:119] wire _wen_T_8 = _wen_T_6 & _wen_T_7; // @[bim.scala:136:{91,116,119}] wire _wen_T_9 = doing_reset | _wen_T_8; // @[bim.scala:53:28, :136:{36,116}] wire wen = _wen_T_9; // @[bim.scala:136:{23,36}] reg [1:0] REG_0; // @[bim.scala:140:37] assign s2_req_rdata_all_0_0 = REG_0; // @[bim.scala:68:30, :140:37] reg [1:0] REG_1; // @[bim.scala:140:37] assign s2_req_rdata_all_0_1 = REG_1; // @[bim.scala:68:30, :140:37] reg [1:0] REG_2; // @[bim.scala:140:37] assign s2_req_rdata_all_0_2 = REG_2; // @[bim.scala:68:30, :140:37] reg [1:0] REG_3; // @[bim.scala:140:37] assign s2_req_rdata_all_0_3 = REG_3; // @[bim.scala:68:30, :140:37] wire [7:0] _r_T_2; // @[bim.scala:159:49] wire _r_T_1; // @[bim.scala:159:60] wire [1:0] wdata_0; // @[bim.scala:163:24] wire [1:0] wdata_1; // @[bim.scala:163:24] wire [1:0] wdata_2; // @[bim.scala:163:24] wire [1:0] wdata_3; // @[bim.scala:163:24] assign rdata_0 = _bim_col_0_RW0_rdata[1:0]; // @[bim.scala:133:21, :157:29] assign rdata_1 = _bim_col_0_RW0_rdata[3:2]; // @[bim.scala:133:21, :157:29] assign rdata_2 = _bim_col_0_RW0_rdata[5:4]; // @[bim.scala:133:21, :157:29] assign rdata_3 = _bim_col_0_RW0_rdata[7:6]; // @[bim.scala:133:21, :157:29] wire _r_T = ~wen; // @[bim.scala:136:23, :159:63] assign _r_T_1 = ren & _r_T; // @[bim.scala:135:86, :159:{60,63}] assign _r_T_2 = _r_WIRE[7:0]; // @[bim.scala:159:49] wire [33:0] _GEN_5 = doing_reset ? {26'h0, reset_idx} : s1_update_col_idx; // @[bim.scala:53:28, :54:26, :89:41, :162:23] wire [33:0] widx; // @[bim.scala:162:23] assign widx = _GEN_5; // @[bim.scala:162:23] wire [33:0] widx_1; // @[bim.scala:162:23] assign widx_1 = _GEN_5; // @[bim.scala:162:23] wire [33:0] widx_2; // @[bim.scala:162:23] assign widx_2 = _GEN_5; // @[bim.scala:162:23] wire [33:0] widx_3; // @[bim.scala:162:23] assign widx_3 = _GEN_5; // @[bim.scala:162:23] wire [33:0] widx_4; // @[bim.scala:162:23] assign widx_4 = _GEN_5; // @[bim.scala:162:23] wire [33:0] widx_5; // @[bim.scala:162:23] assign widx_5 = _GEN_5; // @[bim.scala:162:23] wire [33:0] widx_6; // @[bim.scala:162:23] assign widx_6 = _GEN_5; // @[bim.scala:162:23] wire [33:0] widx_7; // @[bim.scala:162:23] assign widx_7 = _GEN_5; // @[bim.scala:162:23] wire [1:0] _GEN_6 = doing_reset ? 2'h2 : s1_update_wdata_0; // @[bim.scala:53:28, :85:31, :163:24] assign wdata_0 = _GEN_6; // @[bim.scala:163:24] wire [1:0] wdata_1_0; // @[bim.scala:163:24] assign wdata_1_0 = _GEN_6; // @[bim.scala:163:24] wire [1:0] wdata_2_0; // @[bim.scala:163:24] assign wdata_2_0 = _GEN_6; // @[bim.scala:163:24] wire [1:0] wdata_3_0; // @[bim.scala:163:24] assign wdata_3_0 = _GEN_6; // @[bim.scala:163:24] wire [1:0] wdata_4_0; // @[bim.scala:163:24] assign wdata_4_0 = _GEN_6; // @[bim.scala:163:24] wire [1:0] wdata_5_0; // @[bim.scala:163:24] assign wdata_5_0 = _GEN_6; // @[bim.scala:163:24] wire [1:0] wdata_6_0; // @[bim.scala:163:24] assign wdata_6_0 = _GEN_6; // @[bim.scala:163:24] wire [1:0] wdata_7_0; // @[bim.scala:163:24] assign wdata_7_0 = _GEN_6; // @[bim.scala:163:24] wire [1:0] _GEN_7 = doing_reset ? 2'h2 : s1_update_wdata_1; // @[bim.scala:53:28, :85:31, :163:24] assign wdata_1 = _GEN_7; // @[bim.scala:163:24] wire [1:0] wdata_1_1; // @[bim.scala:163:24] assign wdata_1_1 = _GEN_7; // @[bim.scala:163:24] wire [1:0] wdata_2_1; // @[bim.scala:163:24] assign wdata_2_1 = _GEN_7; // @[bim.scala:163:24] wire [1:0] wdata_3_1; // @[bim.scala:163:24] assign wdata_3_1 = _GEN_7; // @[bim.scala:163:24] wire [1:0] wdata_4_1; // @[bim.scala:163:24] assign wdata_4_1 = _GEN_7; // @[bim.scala:163:24] wire [1:0] wdata_5_1; // @[bim.scala:163:24] assign wdata_5_1 = _GEN_7; // @[bim.scala:163:24] wire [1:0] wdata_6_1; // @[bim.scala:163:24] assign wdata_6_1 = _GEN_7; // @[bim.scala:163:24] wire [1:0] wdata_7_1; // @[bim.scala:163:24] assign wdata_7_1 = _GEN_7; // @[bim.scala:163:24] wire [1:0] _GEN_8 = doing_reset ? 2'h2 : s1_update_wdata_2; // @[bim.scala:53:28, :85:31, :163:24] assign wdata_2 = _GEN_8; // @[bim.scala:163:24] wire [1:0] wdata_1_2; // @[bim.scala:163:24] assign wdata_1_2 = _GEN_8; // @[bim.scala:163:24] wire [1:0] wdata_2_2; // @[bim.scala:163:24] assign wdata_2_2 = _GEN_8; // @[bim.scala:163:24] wire [1:0] wdata_3_2; // @[bim.scala:163:24] assign wdata_3_2 = _GEN_8; // @[bim.scala:163:24] wire [1:0] wdata_4_2; // @[bim.scala:163:24] assign wdata_4_2 = _GEN_8; // @[bim.scala:163:24] wire [1:0] wdata_5_2; // @[bim.scala:163:24] assign wdata_5_2 = _GEN_8; // @[bim.scala:163:24] wire [1:0] wdata_6_2; // @[bim.scala:163:24] assign wdata_6_2 = _GEN_8; // @[bim.scala:163:24] wire [1:0] wdata_7_2; // @[bim.scala:163:24] assign wdata_7_2 = _GEN_8; // @[bim.scala:163:24] wire [1:0] _GEN_9 = doing_reset ? 2'h2 : s1_update_wdata_3; // @[bim.scala:53:28, :85:31, :163:24] assign wdata_3 = _GEN_9; // @[bim.scala:163:24] wire [1:0] wdata_1_3; // @[bim.scala:163:24] assign wdata_1_3 = _GEN_9; // @[bim.scala:163:24] wire [1:0] wdata_2_3; // @[bim.scala:163:24] assign wdata_2_3 = _GEN_9; // @[bim.scala:163:24] wire [1:0] wdata_3_3; // @[bim.scala:163:24] assign wdata_3_3 = _GEN_9; // @[bim.scala:163:24] wire [1:0] wdata_4_3; // @[bim.scala:163:24] assign wdata_4_3 = _GEN_9; // @[bim.scala:163:24] wire [1:0] wdata_5_3; // @[bim.scala:163:24] assign wdata_5_3 = _GEN_9; // @[bim.scala:163:24] wire [1:0] wdata_6_3; // @[bim.scala:163:24] assign wdata_6_3 = _GEN_9; // @[bim.scala:163:24] wire [1:0] wdata_7_3; // @[bim.scala:163:24] assign wdata_7_3 = _GEN_9; // @[bim.scala:163:24] wire [1:0] _GEN_10 = {s1_update_wmask_1, s1_update_wmask_0}; // @[bim.scala:86:31, :164:77] wire [1:0] wmask_lo; // @[bim.scala:164:77] assign wmask_lo = _GEN_10; // @[bim.scala:164:77] wire [1:0] wmask_lo_1; // @[bim.scala:164:77] assign wmask_lo_1 = _GEN_10; // @[bim.scala:164:77] wire [1:0] wmask_lo_2; // @[bim.scala:164:77] assign wmask_lo_2 = _GEN_10; // @[bim.scala:164:77] wire [1:0] wmask_lo_3; // @[bim.scala:164:77] assign wmask_lo_3 = _GEN_10; // @[bim.scala:164:77] wire [1:0] wmask_lo_4; // @[bim.scala:164:77] assign wmask_lo_4 = _GEN_10; // @[bim.scala:164:77] wire [1:0] wmask_lo_5; // @[bim.scala:164:77] assign wmask_lo_5 = _GEN_10; // @[bim.scala:164:77] wire [1:0] wmask_lo_6; // @[bim.scala:164:77] assign wmask_lo_6 = _GEN_10; // @[bim.scala:164:77] wire [1:0] wmask_lo_7; // @[bim.scala:164:77] assign wmask_lo_7 = _GEN_10; // @[bim.scala:164:77] wire [1:0] _GEN_11 = {s1_update_wmask_3, s1_update_wmask_2}; // @[bim.scala:86:31, :164:77] wire [1:0] wmask_hi; // @[bim.scala:164:77] assign wmask_hi = _GEN_11; // @[bim.scala:164:77] wire [1:0] wmask_hi_1; // @[bim.scala:164:77] assign wmask_hi_1 = _GEN_11; // @[bim.scala:164:77] wire [1:0] wmask_hi_2; // @[bim.scala:164:77] assign wmask_hi_2 = _GEN_11; // @[bim.scala:164:77] wire [1:0] wmask_hi_3; // @[bim.scala:164:77] assign wmask_hi_3 = _GEN_11; // @[bim.scala:164:77] wire [1:0] wmask_hi_4; // @[bim.scala:164:77] assign wmask_hi_4 = _GEN_11; // @[bim.scala:164:77] wire [1:0] wmask_hi_5; // @[bim.scala:164:77] assign wmask_hi_5 = _GEN_11; // @[bim.scala:164:77] wire [1:0] wmask_hi_6; // @[bim.scala:164:77] assign wmask_hi_6 = _GEN_11; // @[bim.scala:164:77] wire [1:0] wmask_hi_7; // @[bim.scala:164:77] assign wmask_hi_7 = _GEN_11; // @[bim.scala:164:77] wire [3:0] _wmask_T_1 = {wmask_hi, wmask_lo}; // @[bim.scala:164:77] wire [3:0] wmask = doing_reset ? 4'hF : _wmask_T_1; // @[bim.scala:53:28, :164:{24,77}] assign bim_col_0_MPORT_addr = widx[7:0]; // @[bim.scala:162:23, :165:19] wire [1:0] rdata_1_0; // @[bim.scala:133:21] wire [1:0] rdata_1_1; // @[bim.scala:133:21] wire [1:0] rdata_1_2; // @[bim.scala:133:21] wire [1:0] rdata_1_3; // @[bim.scala:133:21] wire ren_1 = s0_col_mask[1]; // @[bim.scala:63:59, :135:86] wire _wen_T_11 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _wen_T_12 = _wen_T_10 | _wen_T_11; // @[predictor.scala:94:50, :96:{49,69}] wire _wen_T_13 = ~_wen_T_12; // @[predictor.scala:96:{26,69}] wire _wen_T_14 = s1_update_valid & _wen_T_13; // @[predictor.scala:96:26, :185:30] wire _wen_T_15 = s1_update_col_mask[1]; // @[OneHot.scala:58:35] wire _wen_T_16 = _wen_T_14 & _wen_T_15; // @[bim.scala:136:{56,91,112}] wire _wen_T_17 = ~ren_1; // @[bim.scala:135:86, :136:119] wire _wen_T_18 = _wen_T_16 & _wen_T_17; // @[bim.scala:136:{91,116,119}] wire _wen_T_19 = doing_reset | _wen_T_18; // @[bim.scala:53:28, :136:{36,116}] wire wen_1 = _wen_T_19; // @[bim.scala:136:{23,36}] reg [1:0] REG_1_0; // @[bim.scala:140:37] assign s2_req_rdata_all_1_0 = REG_1_0; // @[bim.scala:68:30, :140:37] reg [1:0] REG_1_1; // @[bim.scala:140:37] assign s2_req_rdata_all_1_1 = REG_1_1; // @[bim.scala:68:30, :140:37] reg [1:0] REG_1_2; // @[bim.scala:140:37] assign s2_req_rdata_all_1_2 = REG_1_2; // @[bim.scala:68:30, :140:37] reg [1:0] REG_1_3; // @[bim.scala:140:37] assign s2_req_rdata_all_1_3 = REG_1_3; // @[bim.scala:68:30, :140:37] wire [7:0] _r_T_5; // @[bim.scala:159:49] wire _r_T_4; // @[bim.scala:159:60] assign rdata_1_0 = _bim_col_1_RW0_rdata[1:0]; // @[bim.scala:133:21, :157:29] assign rdata_1_1 = _bim_col_1_RW0_rdata[3:2]; // @[bim.scala:133:21, :157:29] assign rdata_1_2 = _bim_col_1_RW0_rdata[5:4]; // @[bim.scala:133:21, :157:29] assign rdata_1_3 = _bim_col_1_RW0_rdata[7:6]; // @[bim.scala:133:21, :157:29] wire _r_T_3 = ~wen_1; // @[bim.scala:136:23, :159:63] assign _r_T_4 = ren_1 & _r_T_3; // @[bim.scala:135:86, :159:{60,63}] assign _r_T_5 = _r_WIRE_1[7:0]; // @[bim.scala:159:49] wire [3:0] _wmask_T_3 = {wmask_hi_1, wmask_lo_1}; // @[bim.scala:164:77] wire [3:0] wmask_1 = doing_reset ? 4'hF : _wmask_T_3; // @[bim.scala:53:28, :164:{24,77}] assign bim_col_1_MPORT_1_addr = widx_1[7:0]; // @[bim.scala:162:23, :165:19] wire [1:0] rdata_2_0; // @[bim.scala:133:21] wire [1:0] rdata_2_1; // @[bim.scala:133:21] wire [1:0] rdata_2_2; // @[bim.scala:133:21] wire [1:0] rdata_2_3; // @[bim.scala:133:21] wire ren_2 = s0_col_mask[2]; // @[bim.scala:63:59, :135:86] wire _wen_T_21 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _wen_T_22 = _wen_T_20 | _wen_T_21; // @[predictor.scala:94:50, :96:{49,69}] wire _wen_T_23 = ~_wen_T_22; // @[predictor.scala:96:{26,69}] wire _wen_T_24 = s1_update_valid & _wen_T_23; // @[predictor.scala:96:26, :185:30] wire _wen_T_25 = s1_update_col_mask[2]; // @[OneHot.scala:58:35] wire _wen_T_26 = _wen_T_24 & _wen_T_25; // @[bim.scala:136:{56,91,112}] wire _wen_T_27 = ~ren_2; // @[bim.scala:135:86, :136:119] wire _wen_T_28 = _wen_T_26 & _wen_T_27; // @[bim.scala:136:{91,116,119}] wire _wen_T_29 = doing_reset | _wen_T_28; // @[bim.scala:53:28, :136:{36,116}] wire wen_2 = _wen_T_29; // @[bim.scala:136:{23,36}] reg [1:0] REG_2_0; // @[bim.scala:140:37] assign s2_req_rdata_all_2_0 = REG_2_0; // @[bim.scala:68:30, :140:37] reg [1:0] REG_2_1; // @[bim.scala:140:37] assign s2_req_rdata_all_2_1 = REG_2_1; // @[bim.scala:68:30, :140:37] reg [1:0] REG_2_2; // @[bim.scala:140:37] assign s2_req_rdata_all_2_2 = REG_2_2; // @[bim.scala:68:30, :140:37] reg [1:0] REG_2_3; // @[bim.scala:140:37] assign s2_req_rdata_all_2_3 = REG_2_3; // @[bim.scala:68:30, :140:37] wire [7:0] _r_T_8; // @[bim.scala:159:49] wire _r_T_7; // @[bim.scala:159:60] assign rdata_2_0 = _bim_col_2_RW0_rdata[1:0]; // @[bim.scala:133:21, :157:29] assign rdata_2_1 = _bim_col_2_RW0_rdata[3:2]; // @[bim.scala:133:21, :157:29] assign rdata_2_2 = _bim_col_2_RW0_rdata[5:4]; // @[bim.scala:133:21, :157:29] assign rdata_2_3 = _bim_col_2_RW0_rdata[7:6]; // @[bim.scala:133:21, :157:29] wire _r_T_6 = ~wen_2; // @[bim.scala:136:23, :159:63] assign _r_T_7 = ren_2 & _r_T_6; // @[bim.scala:135:86, :159:{60,63}] assign _r_T_8 = _r_WIRE_2[7:0]; // @[bim.scala:159:49] wire [3:0] _wmask_T_5 = {wmask_hi_2, wmask_lo_2}; // @[bim.scala:164:77] wire [3:0] wmask_2 = doing_reset ? 4'hF : _wmask_T_5; // @[bim.scala:53:28, :164:{24,77}] assign bim_col_2_MPORT_2_addr = widx_2[7:0]; // @[bim.scala:162:23, :165:19] wire [1:0] rdata_3_0; // @[bim.scala:133:21] wire [1:0] rdata_3_1; // @[bim.scala:133:21] wire [1:0] rdata_3_2; // @[bim.scala:133:21] wire [1:0] rdata_3_3; // @[bim.scala:133:21] wire ren_3 = s0_col_mask[3]; // @[bim.scala:63:59, :135:86] wire _wen_T_31 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _wen_T_32 = _wen_T_30 | _wen_T_31; // @[predictor.scala:94:50, :96:{49,69}] wire _wen_T_33 = ~_wen_T_32; // @[predictor.scala:96:{26,69}] wire _wen_T_34 = s1_update_valid & _wen_T_33; // @[predictor.scala:96:26, :185:30] wire _wen_T_35 = s1_update_col_mask[3]; // @[OneHot.scala:58:35] wire _wen_T_36 = _wen_T_34 & _wen_T_35; // @[bim.scala:136:{56,91,112}] wire _wen_T_37 = ~ren_3; // @[bim.scala:135:86, :136:119] wire _wen_T_38 = _wen_T_36 & _wen_T_37; // @[bim.scala:136:{91,116,119}] wire _wen_T_39 = doing_reset | _wen_T_38; // @[bim.scala:53:28, :136:{36,116}] wire wen_3 = _wen_T_39; // @[bim.scala:136:{23,36}] reg [1:0] REG_3_0; // @[bim.scala:140:37] assign s2_req_rdata_all_3_0 = REG_3_0; // @[bim.scala:68:30, :140:37] reg [1:0] REG_3_1; // @[bim.scala:140:37] assign s2_req_rdata_all_3_1 = REG_3_1; // @[bim.scala:68:30, :140:37] reg [1:0] REG_3_2; // @[bim.scala:140:37] assign s2_req_rdata_all_3_2 = REG_3_2; // @[bim.scala:68:30, :140:37] reg [1:0] REG_3_3; // @[bim.scala:140:37] assign s2_req_rdata_all_3_3 = REG_3_3; // @[bim.scala:68:30, :140:37] wire [7:0] _r_T_11; // @[bim.scala:159:49] wire _r_T_10; // @[bim.scala:159:60] assign rdata_3_0 = _bim_col_3_RW0_rdata[1:0]; // @[bim.scala:133:21, :157:29] assign rdata_3_1 = _bim_col_3_RW0_rdata[3:2]; // @[bim.scala:133:21, :157:29] assign rdata_3_2 = _bim_col_3_RW0_rdata[5:4]; // @[bim.scala:133:21, :157:29] assign rdata_3_3 = _bim_col_3_RW0_rdata[7:6]; // @[bim.scala:133:21, :157:29] wire _r_T_9 = ~wen_3; // @[bim.scala:136:23, :159:63] assign _r_T_10 = ren_3 & _r_T_9; // @[bim.scala:135:86, :159:{60,63}] assign _r_T_11 = _r_WIRE_3[7:0]; // @[bim.scala:159:49] wire [3:0] _wmask_T_7 = {wmask_hi_3, wmask_lo_3}; // @[bim.scala:164:77] wire [3:0] wmask_3 = doing_reset ? 4'hF : _wmask_T_7; // @[bim.scala:53:28, :164:{24,77}] assign bim_col_3_MPORT_3_addr = widx_3[7:0]; // @[bim.scala:162:23, :165:19] wire [1:0] rdata_4_0; // @[bim.scala:133:21] wire [1:0] rdata_4_1; // @[bim.scala:133:21] wire [1:0] rdata_4_2; // @[bim.scala:133:21] wire [1:0] rdata_4_3; // @[bim.scala:133:21] wire ren_4 = s0_col_mask[4]; // @[bim.scala:63:59, :135:86] wire _wen_T_41 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _wen_T_42 = _wen_T_40 | _wen_T_41; // @[predictor.scala:94:50, :96:{49,69}] wire _wen_T_43 = ~_wen_T_42; // @[predictor.scala:96:{26,69}] wire _wen_T_44 = s1_update_valid & _wen_T_43; // @[predictor.scala:96:26, :185:30] wire _wen_T_45 = s1_update_col_mask[4]; // @[OneHot.scala:58:35] wire _wen_T_46 = _wen_T_44 & _wen_T_45; // @[bim.scala:136:{56,91,112}] wire _wen_T_47 = ~ren_4; // @[bim.scala:135:86, :136:119] wire _wen_T_48 = _wen_T_46 & _wen_T_47; // @[bim.scala:136:{91,116,119}] wire _wen_T_49 = doing_reset | _wen_T_48; // @[bim.scala:53:28, :136:{36,116}] wire wen_4 = _wen_T_49; // @[bim.scala:136:{23,36}] reg [1:0] REG_4_0; // @[bim.scala:140:37] assign s2_req_rdata_all_4_0 = REG_4_0; // @[bim.scala:68:30, :140:37] reg [1:0] REG_4_1; // @[bim.scala:140:37] assign s2_req_rdata_all_4_1 = REG_4_1; // @[bim.scala:68:30, :140:37] reg [1:0] REG_4_2; // @[bim.scala:140:37] assign s2_req_rdata_all_4_2 = REG_4_2; // @[bim.scala:68:30, :140:37] reg [1:0] REG_4_3; // @[bim.scala:140:37] assign s2_req_rdata_all_4_3 = REG_4_3; // @[bim.scala:68:30, :140:37] wire [7:0] _r_T_14; // @[bim.scala:159:49] wire _r_T_13; // @[bim.scala:159:60] assign rdata_4_0 = _bim_col_4_RW0_rdata[1:0]; // @[bim.scala:133:21, :157:29] assign rdata_4_1 = _bim_col_4_RW0_rdata[3:2]; // @[bim.scala:133:21, :157:29] assign rdata_4_2 = _bim_col_4_RW0_rdata[5:4]; // @[bim.scala:133:21, :157:29] assign rdata_4_3 = _bim_col_4_RW0_rdata[7:6]; // @[bim.scala:133:21, :157:29] wire _r_T_12 = ~wen_4; // @[bim.scala:136:23, :159:63] assign _r_T_13 = ren_4 & _r_T_12; // @[bim.scala:135:86, :159:{60,63}] assign _r_T_14 = _r_WIRE_4[7:0]; // @[bim.scala:159:49] wire [3:0] _wmask_T_9 = {wmask_hi_4, wmask_lo_4}; // @[bim.scala:164:77] wire [3:0] wmask_4 = doing_reset ? 4'hF : _wmask_T_9; // @[bim.scala:53:28, :164:{24,77}] assign bim_col_4_MPORT_4_addr = widx_4[7:0]; // @[bim.scala:162:23, :165:19] wire [1:0] rdata_5_0; // @[bim.scala:133:21] wire [1:0] rdata_5_1; // @[bim.scala:133:21] wire [1:0] rdata_5_2; // @[bim.scala:133:21] wire [1:0] rdata_5_3; // @[bim.scala:133:21] wire ren_5 = s0_col_mask[5]; // @[bim.scala:63:59, :135:86] wire _wen_T_51 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _wen_T_52 = _wen_T_50 | _wen_T_51; // @[predictor.scala:94:50, :96:{49,69}] wire _wen_T_53 = ~_wen_T_52; // @[predictor.scala:96:{26,69}] wire _wen_T_54 = s1_update_valid & _wen_T_53; // @[predictor.scala:96:26, :185:30] wire _wen_T_55 = s1_update_col_mask[5]; // @[OneHot.scala:58:35] wire _wen_T_56 = _wen_T_54 & _wen_T_55; // @[bim.scala:136:{56,91,112}] wire _wen_T_57 = ~ren_5; // @[bim.scala:135:86, :136:119] wire _wen_T_58 = _wen_T_56 & _wen_T_57; // @[bim.scala:136:{91,116,119}] wire _wen_T_59 = doing_reset | _wen_T_58; // @[bim.scala:53:28, :136:{36,116}] wire wen_5 = _wen_T_59; // @[bim.scala:136:{23,36}] reg [1:0] REG_5_0; // @[bim.scala:140:37] assign s2_req_rdata_all_5_0 = REG_5_0; // @[bim.scala:68:30, :140:37] reg [1:0] REG_5_1; // @[bim.scala:140:37] assign s2_req_rdata_all_5_1 = REG_5_1; // @[bim.scala:68:30, :140:37] reg [1:0] REG_5_2; // @[bim.scala:140:37] assign s2_req_rdata_all_5_2 = REG_5_2; // @[bim.scala:68:30, :140:37] reg [1:0] REG_5_3; // @[bim.scala:140:37] assign s2_req_rdata_all_5_3 = REG_5_3; // @[bim.scala:68:30, :140:37] wire [7:0] _r_T_17; // @[bim.scala:159:49] wire _r_T_16; // @[bim.scala:159:60] assign rdata_5_0 = _bim_col_5_RW0_rdata[1:0]; // @[bim.scala:133:21, :157:29] assign rdata_5_1 = _bim_col_5_RW0_rdata[3:2]; // @[bim.scala:133:21, :157:29] assign rdata_5_2 = _bim_col_5_RW0_rdata[5:4]; // @[bim.scala:133:21, :157:29] assign rdata_5_3 = _bim_col_5_RW0_rdata[7:6]; // @[bim.scala:133:21, :157:29] wire _r_T_15 = ~wen_5; // @[bim.scala:136:23, :159:63] assign _r_T_16 = ren_5 & _r_T_15; // @[bim.scala:135:86, :159:{60,63}] assign _r_T_17 = _r_WIRE_5[7:0]; // @[bim.scala:159:49] wire [3:0] _wmask_T_11 = {wmask_hi_5, wmask_lo_5}; // @[bim.scala:164:77] wire [3:0] wmask_5 = doing_reset ? 4'hF : _wmask_T_11; // @[bim.scala:53:28, :164:{24,77}] assign bim_col_5_MPORT_5_addr = widx_5[7:0]; // @[bim.scala:162:23, :165:19] wire [1:0] rdata_6_0; // @[bim.scala:133:21] wire [1:0] rdata_6_1; // @[bim.scala:133:21] wire [1:0] rdata_6_2; // @[bim.scala:133:21] wire [1:0] rdata_6_3; // @[bim.scala:133:21] wire ren_6 = s0_col_mask[6]; // @[bim.scala:63:59, :135:86] wire _wen_T_61 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _wen_T_62 = _wen_T_60 | _wen_T_61; // @[predictor.scala:94:50, :96:{49,69}] wire _wen_T_63 = ~_wen_T_62; // @[predictor.scala:96:{26,69}] wire _wen_T_64 = s1_update_valid & _wen_T_63; // @[predictor.scala:96:26, :185:30] wire _wen_T_65 = s1_update_col_mask[6]; // @[OneHot.scala:58:35] wire _wen_T_66 = _wen_T_64 & _wen_T_65; // @[bim.scala:136:{56,91,112}] wire _wen_T_67 = ~ren_6; // @[bim.scala:135:86, :136:119] wire _wen_T_68 = _wen_T_66 & _wen_T_67; // @[bim.scala:136:{91,116,119}] wire _wen_T_69 = doing_reset | _wen_T_68; // @[bim.scala:53:28, :136:{36,116}] wire wen_6 = _wen_T_69; // @[bim.scala:136:{23,36}] reg [1:0] REG_6_0; // @[bim.scala:140:37] assign s2_req_rdata_all_6_0 = REG_6_0; // @[bim.scala:68:30, :140:37] reg [1:0] REG_6_1; // @[bim.scala:140:37] assign s2_req_rdata_all_6_1 = REG_6_1; // @[bim.scala:68:30, :140:37] reg [1:0] REG_6_2; // @[bim.scala:140:37] assign s2_req_rdata_all_6_2 = REG_6_2; // @[bim.scala:68:30, :140:37] reg [1:0] REG_6_3; // @[bim.scala:140:37] assign s2_req_rdata_all_6_3 = REG_6_3; // @[bim.scala:68:30, :140:37] wire [7:0] _r_T_20; // @[bim.scala:159:49] wire _r_T_19; // @[bim.scala:159:60] assign rdata_6_0 = _bim_col_6_RW0_rdata[1:0]; // @[bim.scala:133:21, :157:29] assign rdata_6_1 = _bim_col_6_RW0_rdata[3:2]; // @[bim.scala:133:21, :157:29] assign rdata_6_2 = _bim_col_6_RW0_rdata[5:4]; // @[bim.scala:133:21, :157:29] assign rdata_6_3 = _bim_col_6_RW0_rdata[7:6]; // @[bim.scala:133:21, :157:29] wire _r_T_18 = ~wen_6; // @[bim.scala:136:23, :159:63] assign _r_T_19 = ren_6 & _r_T_18; // @[bim.scala:135:86, :159:{60,63}] assign _r_T_20 = _r_WIRE_6[7:0]; // @[bim.scala:159:49] wire [3:0] _wmask_T_13 = {wmask_hi_6, wmask_lo_6}; // @[bim.scala:164:77] wire [3:0] wmask_6 = doing_reset ? 4'hF : _wmask_T_13; // @[bim.scala:53:28, :164:{24,77}] assign bim_col_6_MPORT_6_addr = widx_6[7:0]; // @[bim.scala:162:23, :165:19] wire [1:0] rdata_7_0; // @[bim.scala:133:21] wire [1:0] rdata_7_1; // @[bim.scala:133:21] wire [1:0] rdata_7_2; // @[bim.scala:133:21] wire [1:0] rdata_7_3; // @[bim.scala:133:21] wire ren_7 = s0_col_mask[7]; // @[bim.scala:63:59, :135:86] wire _wen_T_71 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _wen_T_72 = _wen_T_70 | _wen_T_71; // @[predictor.scala:94:50, :96:{49,69}] wire _wen_T_73 = ~_wen_T_72; // @[predictor.scala:96:{26,69}] wire _wen_T_74 = s1_update_valid & _wen_T_73; // @[predictor.scala:96:26, :185:30] wire _wen_T_75 = s1_update_col_mask[7]; // @[OneHot.scala:58:35] wire _wen_T_76 = _wen_T_74 & _wen_T_75; // @[bim.scala:136:{56,91,112}] wire _wen_T_77 = ~ren_7; // @[bim.scala:135:86, :136:119] wire _wen_T_78 = _wen_T_76 & _wen_T_77; // @[bim.scala:136:{91,116,119}] wire _wen_T_79 = doing_reset | _wen_T_78; // @[bim.scala:53:28, :136:{36,116}] wire wen_7 = _wen_T_79; // @[bim.scala:136:{23,36}] reg [1:0] REG_7_0; // @[bim.scala:140:37] assign s2_req_rdata_all_7_0 = REG_7_0; // @[bim.scala:68:30, :140:37] reg [1:0] REG_7_1; // @[bim.scala:140:37] assign s2_req_rdata_all_7_1 = REG_7_1; // @[bim.scala:68:30, :140:37] reg [1:0] REG_7_2; // @[bim.scala:140:37] assign s2_req_rdata_all_7_2 = REG_7_2; // @[bim.scala:68:30, :140:37] reg [1:0] REG_7_3; // @[bim.scala:140:37] assign s2_req_rdata_all_7_3 = REG_7_3; // @[bim.scala:68:30, :140:37] wire [7:0] _r_T_23; // @[bim.scala:159:49] wire _r_T_22; // @[bim.scala:159:60] assign rdata_7_0 = _bim_col_7_RW0_rdata[1:0]; // @[bim.scala:133:21, :157:29] assign rdata_7_1 = _bim_col_7_RW0_rdata[3:2]; // @[bim.scala:133:21, :157:29] assign rdata_7_2 = _bim_col_7_RW0_rdata[5:4]; // @[bim.scala:133:21, :157:29] assign rdata_7_3 = _bim_col_7_RW0_rdata[7:6]; // @[bim.scala:133:21, :157:29] wire _r_T_21 = ~wen_7; // @[bim.scala:136:23, :159:63] assign _r_T_22 = ren_7 & _r_T_21; // @[bim.scala:135:86, :159:{60,63}] assign _r_T_23 = _r_WIRE_7[7:0]; // @[bim.scala:159:49] wire [3:0] _wmask_T_15 = {wmask_hi_7, wmask_lo_7}; // @[bim.scala:164:77] wire [3:0] wmask_7 = doing_reset ? 4'hF : _wmask_T_15; // @[bim.scala:53:28, :164:{24,77}] assign bim_col_7_MPORT_7_addr = widx_7[7:0]; // @[bim.scala:162:23, :165:19] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:211:{14,20}] wire _T_74 = (s1_update_wmask_0 | s1_update_wmask_1 | s1_update_wmask_2 | s1_update_wmask_3) & s1_update_valid & {_T_70, s1_update_bits_btb_mispredicts} == 5'h0; // @[OneHot.scala:58:35] wire _GEN_12 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] always @(posedge clock) begin // @[bim.scala:30:7] s1_idx <= s0_idx; // @[frontend.scala:149:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= s0_pc; // @[frontend.scala:147:31] s2_pc <= s1_pc; // @[predictor.scala:178:22, :179:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:185:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:185:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:185:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:185:30] s1_update_bits_pc <= _s1_update_bits_pc_T_2; // @[frontend.scala:147:31] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:185:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:185:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:185:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:185:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:185:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:185:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:185:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:185:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:185:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:185:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:185:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:185:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:149:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:188:32] s1_col_mask <= s0_col_mask; // @[bim.scala:63:59, :64:28] s1_col_idx <= s0_col_idx; // @[bim.scala:65:28, :66:28] s2_req_rdata_REG <= s1_col_mask; // @[bim.scala:64:28, :69:35] io_resp_f3_0_taken_REG <= s2_resp_0; // @[bim.scala:71:29, :81:35] io_resp_f3_1_taken_REG <= s2_resp_1; // @[bim.scala:71:29, :81:35] io_resp_f3_2_taken_REG <= s2_resp_2; // @[bim.scala:71:29, :81:35] io_resp_f3_3_taken_REG <= s2_resp_3; // @[bim.scala:71:29, :81:35] io_f3_meta_REG <= _io_f3_meta_T; // @[bim.scala:83:{24,33}] if (~_T_74 | wrbypass_hit | wrbypass_enq_idx) begin // @[bim.scala:91:26, :92:26, :93:33, :99:44, :169:{38,57,93}, :170:25, :174:39] end else // @[bim.scala:91:26, :169:93, :170:25, :174:39] wrbypass_idxs_0 <= s1_update_idx[10:0]; // @[predictor.scala:187:30] if (~_T_74 | wrbypass_hit | ~wrbypass_enq_idx) begin // @[bim.scala:91:26, :92:26, :93:33, :99:44, :169:{38,57,93}, :170:25, :174:39] end else // @[bim.scala:91:26, :169:93, :170:25, :174:39] wrbypass_idxs_1 <= s1_update_idx[10:0]; // @[predictor.scala:187:30] if (~_T_74 | _GEN_12) begin // @[bim.scala:92:26, :169:{38,57,93}, :170:25, :171:34, :173:39] end else begin // @[bim.scala:92:26, :169:93, :170:25] wrbypass_0_0 <= s1_update_wdata_0; // @[bim.scala:85:31, :92:26] wrbypass_0_1 <= s1_update_wdata_1; // @[bim.scala:85:31, :92:26] wrbypass_0_2 <= s1_update_wdata_2; // @[bim.scala:85:31, :92:26] wrbypass_0_3 <= s1_update_wdata_3; // @[bim.scala:85:31, :92:26] end if (_T_74 & _GEN_12) begin // @[bim.scala:92:26, :169:{38,57,93}, :170:25, :171:34, :173:39] wrbypass_1_0 <= s1_update_wdata_0; // @[bim.scala:85:31, :92:26] wrbypass_1_1 <= s1_update_wdata_1; // @[bim.scala:85:31, :92:26] wrbypass_1_2 <= s1_update_wdata_2; // @[bim.scala:85:31, :92:26] wrbypass_1_3 <= s1_update_wdata_3; // @[bim.scala:85:31, :92:26] end REG_0 <= rdata_0; // @[bim.scala:133:21, :140:37] REG_1 <= rdata_1; // @[bim.scala:133:21, :140:37] REG_2 <= rdata_2; // @[bim.scala:133:21, :140:37] REG_3 <= rdata_3; // @[bim.scala:133:21, :140:37] REG_1_0 <= rdata_1_0; // @[bim.scala:133:21, :140:37] REG_1_1 <= rdata_1_1; // @[bim.scala:133:21, :140:37] REG_1_2 <= rdata_1_2; // @[bim.scala:133:21, :140:37] REG_1_3 <= rdata_1_3; // @[bim.scala:133:21, :140:37] REG_2_0 <= rdata_2_0; // @[bim.scala:133:21, :140:37] REG_2_1 <= rdata_2_1; // @[bim.scala:133:21, :140:37] REG_2_2 <= rdata_2_2; // @[bim.scala:133:21, :140:37] REG_2_3 <= rdata_2_3; // @[bim.scala:133:21, :140:37] REG_3_0 <= rdata_3_0; // @[bim.scala:133:21, :140:37] REG_3_1 <= rdata_3_1; // @[bim.scala:133:21, :140:37] REG_3_2 <= rdata_3_2; // @[bim.scala:133:21, :140:37] REG_3_3 <= rdata_3_3; // @[bim.scala:133:21, :140:37] REG_4_0 <= rdata_4_0; // @[bim.scala:133:21, :140:37] REG_4_1 <= rdata_4_1; // @[bim.scala:133:21, :140:37] REG_4_2 <= rdata_4_2; // @[bim.scala:133:21, :140:37] REG_4_3 <= rdata_4_3; // @[bim.scala:133:21, :140:37] REG_5_0 <= rdata_5_0; // @[bim.scala:133:21, :140:37] REG_5_1 <= rdata_5_1; // @[bim.scala:133:21, :140:37] REG_5_2 <= rdata_5_2; // @[bim.scala:133:21, :140:37] REG_5_3 <= rdata_5_3; // @[bim.scala:133:21, :140:37] REG_6_0 <= rdata_6_0; // @[bim.scala:133:21, :140:37] REG_6_1 <= rdata_6_1; // @[bim.scala:133:21, :140:37] REG_6_2 <= rdata_6_2; // @[bim.scala:133:21, :140:37] REG_6_3 <= rdata_6_3; // @[bim.scala:133:21, :140:37] REG_7_0 <= rdata_7_0; // @[bim.scala:133:21, :140:37] REG_7_1 <= rdata_7_1; // @[bim.scala:133:21, :140:37] REG_7_2 <= rdata_7_2; // @[bim.scala:133:21, :140:37] REG_7_3 <= rdata_7_3; // @[bim.scala:133:21, :140:37] if (reset) begin // @[bim.scala:30:7] doing_reset <= 1'h1; // @[bim.scala:53:28] reset_idx <= 8'h0; // @[bim.scala:54:26] wrbypass_enq_idx <= 1'h0; // @[bim.scala:93:33] end else begin // @[bim.scala:30:7] doing_reset <= reset_idx != 8'hFF & doing_reset; // @[bim.scala:53:28, :54:26, :56:{19,42,56}] reset_idx <= _reset_idx_T_1; // @[bim.scala:54:26, :55:26] if (~_T_74 | wrbypass_hit) begin // @[bim.scala:92:26, :93:33, :99:44, :169:{38,57,93}, :170:25] end else // @[bim.scala:93:33, :169:93, :170:25] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:211:20] end always @(posedge) bim_col_0 bim_col_0 ( // @[bim.scala:157:29] .RW0_addr (wen ? bim_col_0_MPORT_addr : _r_T_2), // @[bim.scala:136:23, :157:29, :159:49, :165:19] .RW0_en (_r_T_1 | wen), // @[bim.scala:136:23, :157:29, :159:60] .RW0_clk (clock), .RW0_wmode (wen), // @[bim.scala:136:23] .RW0_wdata ({wdata_3, wdata_2, wdata_1, wdata_0}), // @[bim.scala:157:29, :163:24] .RW0_rdata (_bim_col_0_RW0_rdata), .RW0_wmask (wmask) // @[bim.scala:164:24] ); // @[bim.scala:157:29] bim_col_1 bim_col_1 ( // @[bim.scala:157:29] .RW0_addr (wen_1 ? bim_col_1_MPORT_1_addr : _r_T_5), // @[bim.scala:136:23, :157:29, :159:49, :165:19] .RW0_en (_r_T_4 | wen_1), // @[bim.scala:136:23, :157:29, :159:60] .RW0_clk (clock), .RW0_wmode (wen_1), // @[bim.scala:136:23] .RW0_wdata ({wdata_1_3, wdata_1_2, wdata_1_1, wdata_1_0}), // @[bim.scala:157:29, :163:24] .RW0_rdata (_bim_col_1_RW0_rdata), .RW0_wmask (wmask_1) // @[bim.scala:164:24] ); // @[bim.scala:157:29] bim_col_2 bim_col_2 ( // @[bim.scala:157:29] .RW0_addr (wen_2 ? bim_col_2_MPORT_2_addr : _r_T_8), // @[bim.scala:136:23, :157:29, :159:49, :165:19] .RW0_en (_r_T_7 | wen_2), // @[bim.scala:136:23, :157:29, :159:60] .RW0_clk (clock), .RW0_wmode (wen_2), // @[bim.scala:136:23] .RW0_wdata ({wdata_2_3, wdata_2_2, wdata_2_1, wdata_2_0}), // @[bim.scala:157:29, :163:24] .RW0_rdata (_bim_col_2_RW0_rdata), .RW0_wmask (wmask_2) // @[bim.scala:164:24] ); // @[bim.scala:157:29] bim_col_3 bim_col_3 ( // @[bim.scala:157:29] .RW0_addr (wen_3 ? bim_col_3_MPORT_3_addr : _r_T_11), // @[bim.scala:136:23, :157:29, :159:49, :165:19] .RW0_en (_r_T_10 | wen_3), // @[bim.scala:136:23, :157:29, :159:60] .RW0_clk (clock), .RW0_wmode (wen_3), // @[bim.scala:136:23] .RW0_wdata ({wdata_3_3, wdata_3_2, wdata_3_1, wdata_3_0}), // @[bim.scala:157:29, :163:24] .RW0_rdata (_bim_col_3_RW0_rdata), .RW0_wmask (wmask_3) // @[bim.scala:164:24] ); // @[bim.scala:157:29] bim_col_4 bim_col_4 ( // @[bim.scala:157:29] .RW0_addr (wen_4 ? bim_col_4_MPORT_4_addr : _r_T_14), // @[bim.scala:136:23, :157:29, :159:49, :165:19] .RW0_en (_r_T_13 | wen_4), // @[bim.scala:136:23, :157:29, :159:60] .RW0_clk (clock), .RW0_wmode (wen_4), // @[bim.scala:136:23] .RW0_wdata ({wdata_4_3, wdata_4_2, wdata_4_1, wdata_4_0}), // @[bim.scala:157:29, :163:24] .RW0_rdata (_bim_col_4_RW0_rdata), .RW0_wmask (wmask_4) // @[bim.scala:164:24] ); // @[bim.scala:157:29] bim_col_5 bim_col_5 ( // @[bim.scala:157:29] .RW0_addr (wen_5 ? bim_col_5_MPORT_5_addr : _r_T_17), // @[bim.scala:136:23, :157:29, :159:49, :165:19] .RW0_en (_r_T_16 | wen_5), // @[bim.scala:136:23, :157:29, :159:60] .RW0_clk (clock), .RW0_wmode (wen_5), // @[bim.scala:136:23] .RW0_wdata ({wdata_5_3, wdata_5_2, wdata_5_1, wdata_5_0}), // @[bim.scala:157:29, :163:24] .RW0_rdata (_bim_col_5_RW0_rdata), .RW0_wmask (wmask_5) // @[bim.scala:164:24] ); // @[bim.scala:157:29] bim_col_6 bim_col_6 ( // @[bim.scala:157:29] .RW0_addr (wen_6 ? bim_col_6_MPORT_6_addr : _r_T_20), // @[bim.scala:136:23, :157:29, :159:49, :165:19] .RW0_en (_r_T_19 | wen_6), // @[bim.scala:136:23, :157:29, :159:60] .RW0_clk (clock), .RW0_wmode (wen_6), // @[bim.scala:136:23] .RW0_wdata ({wdata_6_3, wdata_6_2, wdata_6_1, wdata_6_0}), // @[bim.scala:157:29, :163:24] .RW0_rdata (_bim_col_6_RW0_rdata), .RW0_wmask (wmask_6) // @[bim.scala:164:24] ); // @[bim.scala:157:29] bim_col_7 bim_col_7 ( // @[bim.scala:157:29] .RW0_addr (wen_7 ? bim_col_7_MPORT_7_addr : _r_T_23), // @[bim.scala:136:23, :157:29, :159:49, :165:19] .RW0_en (_r_T_22 | wen_7), // @[bim.scala:136:23, :157:29, :159:60] .RW0_clk (clock), .RW0_wmode (wen_7), // @[bim.scala:136:23] .RW0_wdata ({wdata_7_3, wdata_7_2, wdata_7_1, wdata_7_0}), // @[bim.scala:157:29, :163:24] .RW0_rdata (_bim_col_7_RW0_rdata), .RW0_wmask (wmask_7) // @[bim.scala:164:24] ); // @[bim.scala:157:29] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[bim.scala:30:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[bim.scala:30:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[bim.scala:30:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[bim.scala:30:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[bim.scala:30:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[bim.scala:30:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[bim.scala:30:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[bim.scala:30:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[bim.scala:30:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[bim.scala:30:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[bim.scala:30:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[bim.scala:30:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[bim.scala:30:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[bim.scala:30:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[bim.scala:30:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[bim.scala:30:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[bim.scala:30:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[bim.scala:30:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[bim.scala:30:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[bim.scala:30:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[bim.scala:30:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[bim.scala:30:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[bim.scala:30:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[bim.scala:30:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[bim.scala:30:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[bim.scala:30:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[bim.scala:30:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[bim.scala:30:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[bim.scala:30:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[bim.scala:30:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[bim.scala:30:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[bim.scala:30:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[bim.scala:30:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[bim.scala:30:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[bim.scala:30:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[bim.scala:30:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[bim.scala:30:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[bim.scala:30:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[bim.scala:30:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[bim.scala:30:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[bim.scala:30:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[bim.scala:30:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[bim.scala:30:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[bim.scala:30:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[bim.scala:30:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[bim.scala:30:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[bim.scala:30:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[bim.scala:30:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[bim.scala:30:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[bim.scala:30:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[bim.scala:30:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[bim.scala:30:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[bim.scala:30:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[bim.scala:30:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[bim.scala:30:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[bim.scala:30:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[bim.scala:30:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[bim.scala:30:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[bim.scala:30:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[bim.scala:30:7] assign io_f3_meta = io_f3_meta_0; // @[bim.scala:30:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_50 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) when io.en : connect reg, io.d connect io.q, reg
module AsyncResetRegVec_w1_i0_50( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module Router_59 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[2], sa_stall : UInt[2]}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_125 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate destNodesIn_1.vc_free invalidate destNodesIn_1.credit_return invalidate destNodesIn_1.flit[0].bits.virt_channel_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_1.flit[0].bits.flow.ingress_node invalidate destNodesIn_1.flit[0].bits.flow.vnet_id invalidate destNodesIn_1.flit[0].bits.payload invalidate destNodesIn_1.flit[0].bits.tail invalidate destNodesIn_1.flit[0].bits.head invalidate destNodesIn_1.flit[0].valid inst monitor_1 of NoCMonitor_126 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate sourceNodesOut_1.vc_free invalidate sourceNodesOut_1.credit_return invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_1.flit[0].bits.payload invalidate sourceNodesOut_1.flit[0].bits.tail invalidate sourceNodesOut_1.flit[0].bits.head invalidate sourceNodesOut_1.flit[0].valid wire debugNodeOut : { va_stall : UInt[2], sa_stall : UInt[2]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] connect destNodesIn, auto.dest_nodes_in_0 connect destNodesIn_1, auto.dest_nodes_in_1 connect auto.source_nodes_out_0, sourceNodesOut connect auto.source_nodes_out_1, sourceNodesOut_1 connect auto.debug_out, debugNodeOut inst input_unit_0_from_4 of InputUnit_125 connect input_unit_0_from_4.clock, clock connect input_unit_0_from_4.reset, reset inst input_unit_1_from_13 of InputUnit_126 connect input_unit_1_from_13.clock, clock connect input_unit_1_from_13.reset, reset inst output_unit_0_to_4 of OutputUnit_125 connect output_unit_0_to_4.clock, clock connect output_unit_0_to_4.reset, reset inst output_unit_1_to_13 of OutputUnit_126 connect output_unit_1_to_13.clock, clock connect output_unit_1_to_13.reset, reset inst switch of Switch_59 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_59 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_59 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_59 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_3 = bits(_fires_count_T_2, 1, 0) wire fires_count : UInt connect fires_count, _fires_count_T_3 connect input_unit_0_from_4.io.in, destNodesIn connect input_unit_1_from_13.io.in, destNodesIn_1 connect output_unit_0_to_4.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_4.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_4.io.out.flit connect output_unit_1_to_13.io.out.vc_free, sourceNodesOut_1.vc_free connect output_unit_1_to_13.io.out.credit_return, sourceNodesOut_1.credit_return connect sourceNodesOut_1.flit, output_unit_1_to_13.io.out.flit connect route_computer.io.req.`0`, input_unit_0_from_4.io.router_req connect route_computer.io.req.`1`, input_unit_1_from_13.io.router_req connect input_unit_0_from_4.io.router_resp, route_computer.io.resp.`0` connect input_unit_1_from_13.io.router_resp, route_computer.io.resp.`1` connect vc_allocator.io.req.`0`, input_unit_0_from_4.io.vcalloc_req connect vc_allocator.io.req.`1`, input_unit_1_from_13.io.vcalloc_req connect input_unit_0_from_4.io.vcalloc_resp, vc_allocator.io.resp.`0` connect input_unit_1_from_13.io.vcalloc_resp, vc_allocator.io.resp.`1` connect output_unit_0_to_4.io.allocs, vc_allocator.io.out_allocs.`0` connect output_unit_1_to_13.io.allocs, vc_allocator.io.out_allocs.`1` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_4.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_4.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_4.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_4.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_4.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_4.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_4.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_4.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_4.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_4.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_4.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_4.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_4.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_4.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_4.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_4.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_4.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_4.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_4.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_4.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_4.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_4.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_4.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_4.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_4.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_4.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_4.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_4.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_4.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_4.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_4.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_4.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_4.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_4.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_4.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_4.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_4.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_4.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_4.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_4.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`0`[8].flow.egress_node_id, output_unit_0_to_4.io.channel_status[8].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[8].flow.egress_node, output_unit_0_to_4.io.channel_status[8].flow.egress_node connect vc_allocator.io.channel_status.`0`[8].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[8].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[8].flow.ingress_node, output_unit_0_to_4.io.channel_status[8].flow.ingress_node connect vc_allocator.io.channel_status.`0`[8].flow.vnet_id, output_unit_0_to_4.io.channel_status[8].flow.vnet_id connect vc_allocator.io.channel_status.`0`[8].occupied, output_unit_0_to_4.io.channel_status[8].occupied connect vc_allocator.io.channel_status.`0`[9].flow.egress_node_id, output_unit_0_to_4.io.channel_status[9].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[9].flow.egress_node, output_unit_0_to_4.io.channel_status[9].flow.egress_node connect vc_allocator.io.channel_status.`0`[9].flow.ingress_node_id, output_unit_0_to_4.io.channel_status[9].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[9].flow.ingress_node, output_unit_0_to_4.io.channel_status[9].flow.ingress_node connect vc_allocator.io.channel_status.`0`[9].flow.vnet_id, output_unit_0_to_4.io.channel_status[9].flow.vnet_id connect vc_allocator.io.channel_status.`0`[9].occupied, output_unit_0_to_4.io.channel_status[9].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_13.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_13.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_13.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_13.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_13.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_13.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_13.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_13.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_13.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_13.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_13.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_13.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_13.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_13.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_13.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_13.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_13.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_13.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`1`[3].flow.egress_node_id, output_unit_1_to_13.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[3].flow.egress_node, output_unit_1_to_13.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node_id, output_unit_1_to_13.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node, output_unit_1_to_13.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`1`[3].flow.vnet_id, output_unit_1_to_13.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`1`[3].occupied, output_unit_1_to_13.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`1`[4].flow.egress_node_id, output_unit_1_to_13.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[4].flow.egress_node, output_unit_1_to_13.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node_id, output_unit_1_to_13.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node, output_unit_1_to_13.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`1`[4].flow.vnet_id, output_unit_1_to_13.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`1`[4].occupied, output_unit_1_to_13.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`1`[5].flow.egress_node_id, output_unit_1_to_13.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[5].flow.egress_node, output_unit_1_to_13.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`1`[5].flow.ingress_node_id, output_unit_1_to_13.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[5].flow.ingress_node, output_unit_1_to_13.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`1`[5].flow.vnet_id, output_unit_1_to_13.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`1`[5].occupied, output_unit_1_to_13.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`1`[6].flow.egress_node_id, output_unit_1_to_13.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[6].flow.egress_node, output_unit_1_to_13.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`1`[6].flow.ingress_node_id, output_unit_1_to_13.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[6].flow.ingress_node, output_unit_1_to_13.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`1`[6].flow.vnet_id, output_unit_1_to_13.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`1`[6].occupied, output_unit_1_to_13.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`1`[7].flow.egress_node_id, output_unit_1_to_13.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[7].flow.egress_node, output_unit_1_to_13.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`1`[7].flow.ingress_node_id, output_unit_1_to_13.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[7].flow.ingress_node, output_unit_1_to_13.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`1`[7].flow.vnet_id, output_unit_1_to_13.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`1`[7].occupied, output_unit_1_to_13.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`1`[8].flow.egress_node_id, output_unit_1_to_13.io.channel_status[8].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[8].flow.egress_node, output_unit_1_to_13.io.channel_status[8].flow.egress_node connect vc_allocator.io.channel_status.`1`[8].flow.ingress_node_id, output_unit_1_to_13.io.channel_status[8].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[8].flow.ingress_node, output_unit_1_to_13.io.channel_status[8].flow.ingress_node connect vc_allocator.io.channel_status.`1`[8].flow.vnet_id, output_unit_1_to_13.io.channel_status[8].flow.vnet_id connect vc_allocator.io.channel_status.`1`[8].occupied, output_unit_1_to_13.io.channel_status[8].occupied connect vc_allocator.io.channel_status.`1`[9].flow.egress_node_id, output_unit_1_to_13.io.channel_status[9].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[9].flow.egress_node, output_unit_1_to_13.io.channel_status[9].flow.egress_node connect vc_allocator.io.channel_status.`1`[9].flow.ingress_node_id, output_unit_1_to_13.io.channel_status[9].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[9].flow.ingress_node, output_unit_1_to_13.io.channel_status[9].flow.ingress_node connect vc_allocator.io.channel_status.`1`[9].flow.vnet_id, output_unit_1_to_13.io.channel_status[9].flow.vnet_id connect vc_allocator.io.channel_status.`1`[9].occupied, output_unit_1_to_13.io.channel_status[9].occupied connect input_unit_0_from_4.io.out_credit_available.`0`[0], output_unit_0_to_4.io.credit_available[0] connect input_unit_0_from_4.io.out_credit_available.`0`[1], output_unit_0_to_4.io.credit_available[1] connect input_unit_0_from_4.io.out_credit_available.`0`[2], output_unit_0_to_4.io.credit_available[2] connect input_unit_0_from_4.io.out_credit_available.`0`[3], output_unit_0_to_4.io.credit_available[3] connect input_unit_0_from_4.io.out_credit_available.`0`[4], output_unit_0_to_4.io.credit_available[4] connect input_unit_0_from_4.io.out_credit_available.`0`[5], output_unit_0_to_4.io.credit_available[5] connect input_unit_0_from_4.io.out_credit_available.`0`[6], output_unit_0_to_4.io.credit_available[6] connect input_unit_0_from_4.io.out_credit_available.`0`[7], output_unit_0_to_4.io.credit_available[7] connect input_unit_0_from_4.io.out_credit_available.`0`[8], output_unit_0_to_4.io.credit_available[8] connect input_unit_0_from_4.io.out_credit_available.`0`[9], output_unit_0_to_4.io.credit_available[9] connect input_unit_0_from_4.io.out_credit_available.`1`[0], output_unit_1_to_13.io.credit_available[0] connect input_unit_0_from_4.io.out_credit_available.`1`[1], output_unit_1_to_13.io.credit_available[1] connect input_unit_0_from_4.io.out_credit_available.`1`[2], output_unit_1_to_13.io.credit_available[2] connect input_unit_0_from_4.io.out_credit_available.`1`[3], output_unit_1_to_13.io.credit_available[3] connect input_unit_0_from_4.io.out_credit_available.`1`[4], output_unit_1_to_13.io.credit_available[4] connect input_unit_0_from_4.io.out_credit_available.`1`[5], output_unit_1_to_13.io.credit_available[5] connect input_unit_0_from_4.io.out_credit_available.`1`[6], output_unit_1_to_13.io.credit_available[6] connect input_unit_0_from_4.io.out_credit_available.`1`[7], output_unit_1_to_13.io.credit_available[7] connect input_unit_0_from_4.io.out_credit_available.`1`[8], output_unit_1_to_13.io.credit_available[8] connect input_unit_0_from_4.io.out_credit_available.`1`[9], output_unit_1_to_13.io.credit_available[9] connect input_unit_1_from_13.io.out_credit_available.`0`[0], output_unit_0_to_4.io.credit_available[0] connect input_unit_1_from_13.io.out_credit_available.`0`[1], output_unit_0_to_4.io.credit_available[1] connect input_unit_1_from_13.io.out_credit_available.`0`[2], output_unit_0_to_4.io.credit_available[2] connect input_unit_1_from_13.io.out_credit_available.`0`[3], output_unit_0_to_4.io.credit_available[3] connect input_unit_1_from_13.io.out_credit_available.`0`[4], output_unit_0_to_4.io.credit_available[4] connect input_unit_1_from_13.io.out_credit_available.`0`[5], output_unit_0_to_4.io.credit_available[5] connect input_unit_1_from_13.io.out_credit_available.`0`[6], output_unit_0_to_4.io.credit_available[6] connect input_unit_1_from_13.io.out_credit_available.`0`[7], output_unit_0_to_4.io.credit_available[7] connect input_unit_1_from_13.io.out_credit_available.`0`[8], output_unit_0_to_4.io.credit_available[8] connect input_unit_1_from_13.io.out_credit_available.`0`[9], output_unit_0_to_4.io.credit_available[9] connect input_unit_1_from_13.io.out_credit_available.`1`[0], output_unit_1_to_13.io.credit_available[0] connect input_unit_1_from_13.io.out_credit_available.`1`[1], output_unit_1_to_13.io.credit_available[1] connect input_unit_1_from_13.io.out_credit_available.`1`[2], output_unit_1_to_13.io.credit_available[2] connect input_unit_1_from_13.io.out_credit_available.`1`[3], output_unit_1_to_13.io.credit_available[3] connect input_unit_1_from_13.io.out_credit_available.`1`[4], output_unit_1_to_13.io.credit_available[4] connect input_unit_1_from_13.io.out_credit_available.`1`[5], output_unit_1_to_13.io.credit_available[5] connect input_unit_1_from_13.io.out_credit_available.`1`[6], output_unit_1_to_13.io.credit_available[6] connect input_unit_1_from_13.io.out_credit_available.`1`[7], output_unit_1_to_13.io.credit_available[7] connect input_unit_1_from_13.io.out_credit_available.`1`[8], output_unit_1_to_13.io.credit_available[8] connect input_unit_1_from_13.io.out_credit_available.`1`[9], output_unit_1_to_13.io.credit_available[9] connect switch_allocator.io.req.`0`[0], input_unit_0_from_4.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], input_unit_1_from_13.io.salloc_req[0] connect output_unit_0_to_4.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_4.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_4.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_4.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_4.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_4.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_4.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_4.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect output_unit_0_to_4.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail connect output_unit_0_to_4.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc connect output_unit_0_to_4.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail connect output_unit_0_to_4.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc connect output_unit_0_to_4.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail connect output_unit_0_to_4.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc connect output_unit_0_to_4.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail connect output_unit_0_to_4.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc connect output_unit_0_to_4.io.credit_alloc[8].tail, switch_allocator.io.credit_alloc.`0`[8].tail connect output_unit_0_to_4.io.credit_alloc[8].alloc, switch_allocator.io.credit_alloc.`0`[8].alloc connect output_unit_0_to_4.io.credit_alloc[9].tail, switch_allocator.io.credit_alloc.`0`[9].tail connect output_unit_0_to_4.io.credit_alloc[9].alloc, switch_allocator.io.credit_alloc.`0`[9].alloc connect output_unit_1_to_13.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect output_unit_1_to_13.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect output_unit_1_to_13.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail connect output_unit_1_to_13.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc connect output_unit_1_to_13.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail connect output_unit_1_to_13.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc connect output_unit_1_to_13.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`1`[3].tail connect output_unit_1_to_13.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`1`[3].alloc connect output_unit_1_to_13.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`1`[4].tail connect output_unit_1_to_13.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`1`[4].alloc connect output_unit_1_to_13.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`1`[5].tail connect output_unit_1_to_13.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`1`[5].alloc connect output_unit_1_to_13.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`1`[6].tail connect output_unit_1_to_13.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`1`[6].alloc connect output_unit_1_to_13.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`1`[7].tail connect output_unit_1_to_13.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`1`[7].alloc connect output_unit_1_to_13.io.credit_alloc[8].tail, switch_allocator.io.credit_alloc.`1`[8].tail connect output_unit_1_to_13.io.credit_alloc[8].alloc, switch_allocator.io.credit_alloc.`1`[8].alloc connect output_unit_1_to_13.io.credit_alloc[9].tail, switch_allocator.io.credit_alloc.`1`[9].tail connect output_unit_1_to_13.io.credit_alloc[9].alloc, switch_allocator.io.credit_alloc.`1`[9].alloc connect switch.io.in.`0`[0], input_unit_0_from_4.io.out[0] connect switch.io.in.`1`[0], input_unit_1_from_13.io.out[0] connect output_unit_0_to_4.io.in, switch.io.out.`0` connect output_unit_1_to_13.io.in, switch.io.out.`1` reg REG : { `1` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect input_unit_0_from_4.io.block, UInt<1>(0h0) connect input_unit_1_from_13.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_4.io.debug.va_stall connect debugNodeOut.va_stall[1], input_unit_1_from_13.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_4.io.debug.sa_stall connect debugNodeOut.sa_stall[1], input_unit_1_from_13.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_137 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 4 12 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid) connect fired_1, _fired_T_1 node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_13 = tail(_T_12, 1) node _T_14 = eq(debug_sample, _T_13) node _T_15 = and(_T_11, _T_14) node _T_16 = and(_T_15, fired_1) when _T_16 : node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "nocsample %d 13 12 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, destNodesIn_1.flit[0].valid
module Router_59( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [3:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_1_vc_sel_0_8; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_9; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_8; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_9; // @[Router.scala:136:32] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_8; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_9; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_8; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_9; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_8_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_9_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_8_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_9_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_8_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_8_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_1_to_13_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_1_to_13_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_1_to_13_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_1_to_13_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_1_to_13_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_1_to_13_io_credit_available_8; // @[Router.scala:122:13] wire _output_unit_1_to_13_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_1_to_13_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_13_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_13_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_13_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_13_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_13_io_channel_status_8_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_13_io_channel_status_9_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_4_io_credit_available_8; // @[Router.scala:122:13] wire _output_unit_0_to_4_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_0_to_4_io_channel_status_8_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_4_io_channel_status_9_occupied; // @[Router.scala:122:13] wire [3:0] _input_unit_1_from_13_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_13_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_13_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_13_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_13_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_13_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_13_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_13_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_13_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_13_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_13_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_13_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_13_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_13_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_4_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_4_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_4_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_4_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_13_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_321 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_321( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d128s5k4z4u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_47 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d128s5k4z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d128s5k4z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.mask, UInt<16>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<128>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_10.bits.sink, UInt<4>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)
module TLBuffer_a32d128s5k4z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_47 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d128s5k4z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d128s5k4z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_144 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_400 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_144( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_400 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_19 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) when _T_6 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_2 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_2 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_7 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_8 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_9 = neq(_T_8, UInt<1>(0h0)) node _T_10 = or(_T_7, _T_9) node _T_11 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_12 = and(_T_10, _T_11) when _T_12 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_13 = or(prs2_wakeups_0, prs2_wakeups_1) when _T_13 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_2 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_2 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_14 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_15 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_16 = neq(_T_15, UInt<1>(0h0)) node _T_17 = or(_T_14, _T_16) node _T_18 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_19 = and(_T_17, _T_18) when _T_19 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_20 = or(prs3_wakeups_0, prs3_wakeups_1) when _T_20 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_2 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_21 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_22 = and(io.pred_wakeup_port.valid, _T_21) when _T_22 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h1)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_23 = eq(io.squash_grant, UInt<1>(0h0)) node _T_24 = and(io.grant, _T_23) when _T_24 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_25 = and(slot_valid, slot_uop.iw_issued) when _T_25 : connect next_valid, rebusied
module IssueSlot_19( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire rebusied_prs1 = 1'h0; // @[issue-slot.scala:92:31] wire rebusied_prs2 = 1'h0; // @[issue-slot.scala:93:31] wire rebusied = 1'h0; // @[issue-slot.scala:94:32] wire prs1_rebusys_0 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_0 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] next_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] _next_uop_iw_p1_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] wire _iss_ready_T_6 = slot_uop_prs3_busy; // @[issue-slot.scala:56:21, :136:131] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_224 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_224( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_7 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T
module MulAddRecFNToRaw_postMul_e8_s24_7( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_80 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T
module MulAddRecFNToRaw_preMul_e8_s24_80( // @[MulAddRecFN.scala:71:7] input [1:0] io_op, // @[MulAddRecFN.scala:74:16] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [1:0] io_op_0 = io_op; // @[MulAddRecFN.scala:71:7] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _signProd_T_1 = io_op_0[1]; // @[MulAddRecFN.scala:71:7, :97:49] assign signProd = _signProd_T ^ _signProd_T_1; // @[MulAddRecFN.scala:97:{30,42,49}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire _doSubMags_T_1 = io_op_0[0]; // @[MulAddRecFN.scala:71:7, :102:49] assign doSubMags = _doSubMags_T ^ _doSubMags_T_1; // @[MulAddRecFN.scala:102:{30,42,49}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCacheBankScheduler : input clock : Clock input reset : Reset output io : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip ways : UInt<8>[8], flip divs : UInt<11>[8], flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { address : UInt<32>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { fail : UInt<1>}}} inst sourceA of SourceA connect sourceA.clock, clock connect sourceA.reset, reset inst sourceB of SourceB connect sourceB.clock, clock connect sourceB.reset, reset inst sourceC of SourceC connect sourceC.clock, clock connect sourceC.reset, reset inst sourceD of SourceD connect sourceD.clock, clock connect sourceD.reset, reset inst sourceE of SourceE connect sourceE.clock, clock connect sourceE.reset, reset inst sourceX of SourceX connect sourceX.clock, clock connect sourceX.reset, reset connect io.out.a.bits, sourceA.io.a.bits connect io.out.a.valid, sourceA.io.a.valid connect sourceA.io.a.ready, io.out.a.ready connect io.out.c.bits, sourceC.io.c.bits connect io.out.c.valid, sourceC.io.c.valid connect sourceC.io.c.ready, io.out.c.ready connect io.out.e.bits, sourceE.io.e.bits connect io.out.e.valid, sourceE.io.e.valid connect sourceE.io.e.ready, io.out.e.ready connect io.in.b.bits, sourceB.io.b.bits connect io.in.b.valid, sourceB.io.b.valid connect sourceB.io.b.ready, io.in.b.ready connect io.in.d.bits, sourceD.io.d.bits connect io.in.d.valid, sourceD.io.d.valid connect sourceD.io.d.ready, io.in.d.ready connect io.resp.bits, sourceX.io.x.bits connect io.resp.valid, sourceX.io.x.valid connect sourceX.io.x.ready, io.resp.ready inst sinkA of SinkA connect sinkA.clock, clock connect sinkA.reset, reset inst sinkC of SinkC connect sinkC.clock, clock connect sinkC.reset, reset inst sinkD of SinkD connect sinkD.clock, clock connect sinkD.reset, reset inst sinkE of SinkE connect sinkE.clock, clock connect sinkE.reset, reset inst sinkX of SinkX connect sinkX.clock, clock connect sinkX.reset, reset connect sinkA.io.a, io.in.a connect sinkC.io.c, io.in.c connect sinkE.io.e, io.in.e connect sinkD.io.d, io.out.d connect sinkX.io.x, io.req connect io.out.b.ready, UInt<1>(0h1) inst directory of Directory connect directory.clock, clock connect directory.reset, reset inst bankedStore of BankedStore connect bankedStore.clock, clock connect bankedStore.reset, reset inst requests of ListBuffer_QueuedRequest_q21_e33 connect requests.clock, clock connect requests.reset, reset inst mshrs_0 of MSHR connect mshrs_0.clock, clock connect mshrs_0.reset, reset inst mshrs_1 of MSHR_1 connect mshrs_1.clock, clock connect mshrs_1.reset, reset inst mshrs_2 of MSHR_2 connect mshrs_2.clock, clock connect mshrs_2.reset, reset inst mshrs_3 of MSHR_3 connect mshrs_3.clock, clock connect mshrs_3.reset, reset inst mshrs_4 of MSHR_4 connect mshrs_4.clock, clock connect mshrs_4.reset, reset inst mshrs_5 of MSHR_5 connect mshrs_5.clock, clock connect mshrs_5.reset, reset inst mshrs_6 of MSHR_6 connect mshrs_6.clock, clock connect mshrs_6.reset, reset wire nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>} node _mshrs_0_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_0.io.status.bits.set) node _mshrs_0_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_0_io_sinkc_valid_T) connect mshrs_0.io.sinkc.valid, _mshrs_0_io_sinkc_valid_T_1 node _mshrs_0_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h0)) node _mshrs_0_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_0_io_sinkd_valid_T) connect mshrs_0.io.sinkd.valid, _mshrs_0_io_sinkd_valid_T_1 node _mshrs_0_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h0)) node _mshrs_0_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_0_io_sinke_valid_T) connect mshrs_0.io.sinke.valid, _mshrs_0_io_sinke_valid_T_1 connect mshrs_0.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_0.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_0.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_0.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_0.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_0.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_0.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_0.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_0.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_0.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_0.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_0.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_0.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_0.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_0.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_0.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_0.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_0.io.nestedwb.tag, nestedwb.tag connect mshrs_0.io.nestedwb.set, nestedwb.set node _mshrs_1_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_1.io.status.bits.set) node _mshrs_1_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_1_io_sinkc_valid_T) connect mshrs_1.io.sinkc.valid, _mshrs_1_io_sinkc_valid_T_1 node _mshrs_1_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h1)) node _mshrs_1_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_1_io_sinkd_valid_T) connect mshrs_1.io.sinkd.valid, _mshrs_1_io_sinkd_valid_T_1 node _mshrs_1_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h1)) node _mshrs_1_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_1_io_sinke_valid_T) connect mshrs_1.io.sinke.valid, _mshrs_1_io_sinke_valid_T_1 connect mshrs_1.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_1.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_1.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_1.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_1.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_1.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_1.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_1.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_1.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_1.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_1.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_1.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_1.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_1.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_1.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_1.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_1.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_1.io.nestedwb.tag, nestedwb.tag connect mshrs_1.io.nestedwb.set, nestedwb.set node _mshrs_2_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_2.io.status.bits.set) node _mshrs_2_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_2_io_sinkc_valid_T) connect mshrs_2.io.sinkc.valid, _mshrs_2_io_sinkc_valid_T_1 node _mshrs_2_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h2)) node _mshrs_2_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_2_io_sinkd_valid_T) connect mshrs_2.io.sinkd.valid, _mshrs_2_io_sinkd_valid_T_1 node _mshrs_2_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h2)) node _mshrs_2_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_2_io_sinke_valid_T) connect mshrs_2.io.sinke.valid, _mshrs_2_io_sinke_valid_T_1 connect mshrs_2.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_2.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_2.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_2.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_2.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_2.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_2.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_2.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_2.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_2.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_2.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_2.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_2.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_2.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_2.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_2.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_2.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_2.io.nestedwb.tag, nestedwb.tag connect mshrs_2.io.nestedwb.set, nestedwb.set node _mshrs_3_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_3.io.status.bits.set) node _mshrs_3_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_3_io_sinkc_valid_T) connect mshrs_3.io.sinkc.valid, _mshrs_3_io_sinkc_valid_T_1 node _mshrs_3_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h3)) node _mshrs_3_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_3_io_sinkd_valid_T) connect mshrs_3.io.sinkd.valid, _mshrs_3_io_sinkd_valid_T_1 node _mshrs_3_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h3)) node _mshrs_3_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_3_io_sinke_valid_T) connect mshrs_3.io.sinke.valid, _mshrs_3_io_sinke_valid_T_1 connect mshrs_3.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_3.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_3.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_3.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_3.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_3.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_3.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_3.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_3.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_3.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_3.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_3.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_3.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_3.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_3.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_3.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_3.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_3.io.nestedwb.tag, nestedwb.tag connect mshrs_3.io.nestedwb.set, nestedwb.set node _mshrs_4_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_4.io.status.bits.set) node _mshrs_4_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_4_io_sinkc_valid_T) connect mshrs_4.io.sinkc.valid, _mshrs_4_io_sinkc_valid_T_1 node _mshrs_4_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h4)) node _mshrs_4_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_4_io_sinkd_valid_T) connect mshrs_4.io.sinkd.valid, _mshrs_4_io_sinkd_valid_T_1 node _mshrs_4_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h4)) node _mshrs_4_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_4_io_sinke_valid_T) connect mshrs_4.io.sinke.valid, _mshrs_4_io_sinke_valid_T_1 connect mshrs_4.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_4.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_4.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_4.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_4.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_4.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_4.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_4.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_4.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_4.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_4.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_4.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_4.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_4.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_4.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_4.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_4.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_4.io.nestedwb.tag, nestedwb.tag connect mshrs_4.io.nestedwb.set, nestedwb.set node _mshrs_5_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_5.io.status.bits.set) node _mshrs_5_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_5_io_sinkc_valid_T) connect mshrs_5.io.sinkc.valid, _mshrs_5_io_sinkc_valid_T_1 node _mshrs_5_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h5)) node _mshrs_5_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_5_io_sinkd_valid_T) connect mshrs_5.io.sinkd.valid, _mshrs_5_io_sinkd_valid_T_1 node _mshrs_5_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h5)) node _mshrs_5_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_5_io_sinke_valid_T) connect mshrs_5.io.sinke.valid, _mshrs_5_io_sinke_valid_T_1 connect mshrs_5.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_5.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_5.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_5.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_5.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_5.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_5.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_5.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_5.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_5.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_5.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_5.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_5.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_5.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_5.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_5.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_5.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_5.io.nestedwb.tag, nestedwb.tag connect mshrs_5.io.nestedwb.set, nestedwb.set node _mshrs_6_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_6.io.status.bits.set) node _mshrs_6_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_6_io_sinkc_valid_T) connect mshrs_6.io.sinkc.valid, _mshrs_6_io_sinkc_valid_T_1 node _mshrs_6_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h6)) node _mshrs_6_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_6_io_sinkd_valid_T) connect mshrs_6.io.sinkd.valid, _mshrs_6_io_sinkd_valid_T_1 node _mshrs_6_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h6)) node _mshrs_6_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_6_io_sinke_valid_T) connect mshrs_6.io.sinke.valid, _mshrs_6_io_sinke_valid_T_1 connect mshrs_6.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_6.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_6.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_6.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_6.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_6.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_6.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_6.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_6.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_6.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_6.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_6.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_6.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_6.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_6.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_6.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_6.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_6.io.nestedwb.tag, nestedwb.tag connect mshrs_6.io.nestedwb.set, nestedwb.set node _mshr_stall_abc_T = eq(mshrs_0.io.status.bits.set, mshrs_5.io.status.bits.set) node _mshr_stall_abc_T_1 = and(mshrs_5.io.status.valid, _mshr_stall_abc_T) node _mshr_stall_abc_T_2 = eq(mshrs_0.io.status.bits.set, mshrs_6.io.status.bits.set) node _mshr_stall_abc_T_3 = and(mshrs_6.io.status.valid, _mshr_stall_abc_T_2) node mshr_stall_abc_0 = or(_mshr_stall_abc_T_1, _mshr_stall_abc_T_3) node _mshr_stall_abc_T_4 = eq(mshrs_1.io.status.bits.set, mshrs_5.io.status.bits.set) node _mshr_stall_abc_T_5 = and(mshrs_5.io.status.valid, _mshr_stall_abc_T_4) node _mshr_stall_abc_T_6 = eq(mshrs_1.io.status.bits.set, mshrs_6.io.status.bits.set) node _mshr_stall_abc_T_7 = and(mshrs_6.io.status.valid, _mshr_stall_abc_T_6) node mshr_stall_abc_1 = or(_mshr_stall_abc_T_5, _mshr_stall_abc_T_7) node _mshr_stall_abc_T_8 = eq(mshrs_2.io.status.bits.set, mshrs_5.io.status.bits.set) node _mshr_stall_abc_T_9 = and(mshrs_5.io.status.valid, _mshr_stall_abc_T_8) node _mshr_stall_abc_T_10 = eq(mshrs_2.io.status.bits.set, mshrs_6.io.status.bits.set) node _mshr_stall_abc_T_11 = and(mshrs_6.io.status.valid, _mshr_stall_abc_T_10) node mshr_stall_abc_2 = or(_mshr_stall_abc_T_9, _mshr_stall_abc_T_11) node _mshr_stall_abc_T_12 = eq(mshrs_3.io.status.bits.set, mshrs_5.io.status.bits.set) node _mshr_stall_abc_T_13 = and(mshrs_5.io.status.valid, _mshr_stall_abc_T_12) node _mshr_stall_abc_T_14 = eq(mshrs_3.io.status.bits.set, mshrs_6.io.status.bits.set) node _mshr_stall_abc_T_15 = and(mshrs_6.io.status.valid, _mshr_stall_abc_T_14) node mshr_stall_abc_3 = or(_mshr_stall_abc_T_13, _mshr_stall_abc_T_15) node _mshr_stall_abc_T_16 = eq(mshrs_4.io.status.bits.set, mshrs_5.io.status.bits.set) node _mshr_stall_abc_T_17 = and(mshrs_5.io.status.valid, _mshr_stall_abc_T_16) node _mshr_stall_abc_T_18 = eq(mshrs_4.io.status.bits.set, mshrs_6.io.status.bits.set) node _mshr_stall_abc_T_19 = and(mshrs_6.io.status.valid, _mshr_stall_abc_T_18) node mshr_stall_abc_4 = or(_mshr_stall_abc_T_17, _mshr_stall_abc_T_19) node _mshr_stall_bc_T = eq(mshrs_5.io.status.bits.set, mshrs_6.io.status.bits.set) node mshr_stall_bc = and(mshrs_6.io.status.valid, _mshr_stall_bc_T) node stall_abc_0 = and(mshr_stall_abc_0, mshrs_0.io.status.valid) node stall_abc_1 = and(mshr_stall_abc_1, mshrs_1.io.status.valid) node stall_abc_2 = and(mshr_stall_abc_2, mshrs_2.io.status.valid) node stall_abc_3 = and(mshr_stall_abc_3, mshrs_3.io.status.valid) node stall_abc_4 = and(mshr_stall_abc_4, mshrs_4.io.status.valid) node _T = or(stall_abc_0, stall_abc_1) node _T_1 = or(_T, stall_abc_2) node _T_2 = or(_T_1, stall_abc_3) node _T_3 = or(_T_2, stall_abc_4) node _mshr_request_T = eq(mshr_stall_abc_0, UInt<1>(0h0)) node _mshr_request_T_1 = and(mshrs_0.io.schedule.valid, _mshr_request_T) node _mshr_request_T_2 = eq(mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_3 = or(sourceA.io.req.ready, _mshr_request_T_2) node _mshr_request_T_4 = and(_mshr_request_T_1, _mshr_request_T_3) node _mshr_request_T_5 = eq(mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_6 = or(sourceB.io.req.ready, _mshr_request_T_5) node _mshr_request_T_7 = and(_mshr_request_T_4, _mshr_request_T_6) node _mshr_request_T_8 = eq(mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_9 = or(sourceC.io.req.ready, _mshr_request_T_8) node _mshr_request_T_10 = and(_mshr_request_T_7, _mshr_request_T_9) node _mshr_request_T_11 = eq(mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_12 = or(sourceD.io.req.ready, _mshr_request_T_11) node _mshr_request_T_13 = and(_mshr_request_T_10, _mshr_request_T_12) node _mshr_request_T_14 = eq(mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_15 = or(sourceE.io.req.ready, _mshr_request_T_14) node _mshr_request_T_16 = and(_mshr_request_T_13, _mshr_request_T_15) node _mshr_request_T_17 = eq(mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_18 = or(sourceX.io.req.ready, _mshr_request_T_17) node _mshr_request_T_19 = and(_mshr_request_T_16, _mshr_request_T_18) node _mshr_request_T_20 = eq(mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_21 = or(directory.io.write.ready, _mshr_request_T_20) node _mshr_request_T_22 = and(_mshr_request_T_19, _mshr_request_T_21) node _mshr_request_T_23 = eq(mshr_stall_abc_1, UInt<1>(0h0)) node _mshr_request_T_24 = and(mshrs_1.io.schedule.valid, _mshr_request_T_23) node _mshr_request_T_25 = eq(mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_26 = or(sourceA.io.req.ready, _mshr_request_T_25) node _mshr_request_T_27 = and(_mshr_request_T_24, _mshr_request_T_26) node _mshr_request_T_28 = eq(mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_29 = or(sourceB.io.req.ready, _mshr_request_T_28) node _mshr_request_T_30 = and(_mshr_request_T_27, _mshr_request_T_29) node _mshr_request_T_31 = eq(mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_32 = or(sourceC.io.req.ready, _mshr_request_T_31) node _mshr_request_T_33 = and(_mshr_request_T_30, _mshr_request_T_32) node _mshr_request_T_34 = eq(mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_35 = or(sourceD.io.req.ready, _mshr_request_T_34) node _mshr_request_T_36 = and(_mshr_request_T_33, _mshr_request_T_35) node _mshr_request_T_37 = eq(mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_38 = or(sourceE.io.req.ready, _mshr_request_T_37) node _mshr_request_T_39 = and(_mshr_request_T_36, _mshr_request_T_38) node _mshr_request_T_40 = eq(mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_41 = or(sourceX.io.req.ready, _mshr_request_T_40) node _mshr_request_T_42 = and(_mshr_request_T_39, _mshr_request_T_41) node _mshr_request_T_43 = eq(mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_44 = or(directory.io.write.ready, _mshr_request_T_43) node _mshr_request_T_45 = and(_mshr_request_T_42, _mshr_request_T_44) node _mshr_request_T_46 = eq(mshr_stall_abc_2, UInt<1>(0h0)) node _mshr_request_T_47 = and(mshrs_2.io.schedule.valid, _mshr_request_T_46) node _mshr_request_T_48 = eq(mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_49 = or(sourceA.io.req.ready, _mshr_request_T_48) node _mshr_request_T_50 = and(_mshr_request_T_47, _mshr_request_T_49) node _mshr_request_T_51 = eq(mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_52 = or(sourceB.io.req.ready, _mshr_request_T_51) node _mshr_request_T_53 = and(_mshr_request_T_50, _mshr_request_T_52) node _mshr_request_T_54 = eq(mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_55 = or(sourceC.io.req.ready, _mshr_request_T_54) node _mshr_request_T_56 = and(_mshr_request_T_53, _mshr_request_T_55) node _mshr_request_T_57 = eq(mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_58 = or(sourceD.io.req.ready, _mshr_request_T_57) node _mshr_request_T_59 = and(_mshr_request_T_56, _mshr_request_T_58) node _mshr_request_T_60 = eq(mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_61 = or(sourceE.io.req.ready, _mshr_request_T_60) node _mshr_request_T_62 = and(_mshr_request_T_59, _mshr_request_T_61) node _mshr_request_T_63 = eq(mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_64 = or(sourceX.io.req.ready, _mshr_request_T_63) node _mshr_request_T_65 = and(_mshr_request_T_62, _mshr_request_T_64) node _mshr_request_T_66 = eq(mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_67 = or(directory.io.write.ready, _mshr_request_T_66) node _mshr_request_T_68 = and(_mshr_request_T_65, _mshr_request_T_67) node _mshr_request_T_69 = eq(mshr_stall_abc_3, UInt<1>(0h0)) node _mshr_request_T_70 = and(mshrs_3.io.schedule.valid, _mshr_request_T_69) node _mshr_request_T_71 = eq(mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_72 = or(sourceA.io.req.ready, _mshr_request_T_71) node _mshr_request_T_73 = and(_mshr_request_T_70, _mshr_request_T_72) node _mshr_request_T_74 = eq(mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_75 = or(sourceB.io.req.ready, _mshr_request_T_74) node _mshr_request_T_76 = and(_mshr_request_T_73, _mshr_request_T_75) node _mshr_request_T_77 = eq(mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_78 = or(sourceC.io.req.ready, _mshr_request_T_77) node _mshr_request_T_79 = and(_mshr_request_T_76, _mshr_request_T_78) node _mshr_request_T_80 = eq(mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_81 = or(sourceD.io.req.ready, _mshr_request_T_80) node _mshr_request_T_82 = and(_mshr_request_T_79, _mshr_request_T_81) node _mshr_request_T_83 = eq(mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_84 = or(sourceE.io.req.ready, _mshr_request_T_83) node _mshr_request_T_85 = and(_mshr_request_T_82, _mshr_request_T_84) node _mshr_request_T_86 = eq(mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_87 = or(sourceX.io.req.ready, _mshr_request_T_86) node _mshr_request_T_88 = and(_mshr_request_T_85, _mshr_request_T_87) node _mshr_request_T_89 = eq(mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_90 = or(directory.io.write.ready, _mshr_request_T_89) node _mshr_request_T_91 = and(_mshr_request_T_88, _mshr_request_T_90) node _mshr_request_T_92 = eq(mshr_stall_abc_4, UInt<1>(0h0)) node _mshr_request_T_93 = and(mshrs_4.io.schedule.valid, _mshr_request_T_92) node _mshr_request_T_94 = eq(mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_95 = or(sourceA.io.req.ready, _mshr_request_T_94) node _mshr_request_T_96 = and(_mshr_request_T_93, _mshr_request_T_95) node _mshr_request_T_97 = eq(mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_98 = or(sourceB.io.req.ready, _mshr_request_T_97) node _mshr_request_T_99 = and(_mshr_request_T_96, _mshr_request_T_98) node _mshr_request_T_100 = eq(mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_101 = or(sourceC.io.req.ready, _mshr_request_T_100) node _mshr_request_T_102 = and(_mshr_request_T_99, _mshr_request_T_101) node _mshr_request_T_103 = eq(mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_104 = or(sourceD.io.req.ready, _mshr_request_T_103) node _mshr_request_T_105 = and(_mshr_request_T_102, _mshr_request_T_104) node _mshr_request_T_106 = eq(mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_107 = or(sourceE.io.req.ready, _mshr_request_T_106) node _mshr_request_T_108 = and(_mshr_request_T_105, _mshr_request_T_107) node _mshr_request_T_109 = eq(mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_110 = or(sourceX.io.req.ready, _mshr_request_T_109) node _mshr_request_T_111 = and(_mshr_request_T_108, _mshr_request_T_110) node _mshr_request_T_112 = eq(mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_113 = or(directory.io.write.ready, _mshr_request_T_112) node _mshr_request_T_114 = and(_mshr_request_T_111, _mshr_request_T_113) node _mshr_request_T_115 = eq(mshr_stall_bc, UInt<1>(0h0)) node _mshr_request_T_116 = and(mshrs_5.io.schedule.valid, _mshr_request_T_115) node _mshr_request_T_117 = eq(mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_118 = or(sourceA.io.req.ready, _mshr_request_T_117) node _mshr_request_T_119 = and(_mshr_request_T_116, _mshr_request_T_118) node _mshr_request_T_120 = eq(mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_121 = or(sourceB.io.req.ready, _mshr_request_T_120) node _mshr_request_T_122 = and(_mshr_request_T_119, _mshr_request_T_121) node _mshr_request_T_123 = eq(mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_124 = or(sourceC.io.req.ready, _mshr_request_T_123) node _mshr_request_T_125 = and(_mshr_request_T_122, _mshr_request_T_124) node _mshr_request_T_126 = eq(mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_127 = or(sourceD.io.req.ready, _mshr_request_T_126) node _mshr_request_T_128 = and(_mshr_request_T_125, _mshr_request_T_127) node _mshr_request_T_129 = eq(mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_130 = or(sourceE.io.req.ready, _mshr_request_T_129) node _mshr_request_T_131 = and(_mshr_request_T_128, _mshr_request_T_130) node _mshr_request_T_132 = eq(mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_133 = or(sourceX.io.req.ready, _mshr_request_T_132) node _mshr_request_T_134 = and(_mshr_request_T_131, _mshr_request_T_133) node _mshr_request_T_135 = eq(mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_136 = or(directory.io.write.ready, _mshr_request_T_135) node _mshr_request_T_137 = and(_mshr_request_T_134, _mshr_request_T_136) node _mshr_request_T_138 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _mshr_request_T_139 = and(mshrs_6.io.schedule.valid, _mshr_request_T_138) node _mshr_request_T_140 = eq(mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_141 = or(sourceA.io.req.ready, _mshr_request_T_140) node _mshr_request_T_142 = and(_mshr_request_T_139, _mshr_request_T_141) node _mshr_request_T_143 = eq(mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_144 = or(sourceB.io.req.ready, _mshr_request_T_143) node _mshr_request_T_145 = and(_mshr_request_T_142, _mshr_request_T_144) node _mshr_request_T_146 = eq(mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_147 = or(sourceC.io.req.ready, _mshr_request_T_146) node _mshr_request_T_148 = and(_mshr_request_T_145, _mshr_request_T_147) node _mshr_request_T_149 = eq(mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_150 = or(sourceD.io.req.ready, _mshr_request_T_149) node _mshr_request_T_151 = and(_mshr_request_T_148, _mshr_request_T_150) node _mshr_request_T_152 = eq(mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_153 = or(sourceE.io.req.ready, _mshr_request_T_152) node _mshr_request_T_154 = and(_mshr_request_T_151, _mshr_request_T_153) node _mshr_request_T_155 = eq(mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_156 = or(sourceX.io.req.ready, _mshr_request_T_155) node _mshr_request_T_157 = and(_mshr_request_T_154, _mshr_request_T_156) node _mshr_request_T_158 = eq(mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_159 = or(directory.io.write.ready, _mshr_request_T_158) node _mshr_request_T_160 = and(_mshr_request_T_157, _mshr_request_T_159) node mshr_request_lo_hi = cat(_mshr_request_T_68, _mshr_request_T_45) node mshr_request_lo = cat(mshr_request_lo_hi, _mshr_request_T_22) node mshr_request_hi_lo = cat(_mshr_request_T_114, _mshr_request_T_91) node mshr_request_hi_hi = cat(_mshr_request_T_160, _mshr_request_T_137) node mshr_request_hi = cat(mshr_request_hi_hi, mshr_request_hi_lo) node mshr_request = cat(mshr_request_hi, mshr_request_lo) regreset robin_filter : UInt<7>, clock, reset, UInt<7>(0h0) node _robin_request_T = and(mshr_request, robin_filter) node robin_request = cat(mshr_request, _robin_request_T) node _mshr_selectOH2_T = shl(robin_request, 1) node _mshr_selectOH2_T_1 = bits(_mshr_selectOH2_T, 13, 0) node _mshr_selectOH2_T_2 = or(robin_request, _mshr_selectOH2_T_1) node _mshr_selectOH2_T_3 = shl(_mshr_selectOH2_T_2, 2) node _mshr_selectOH2_T_4 = bits(_mshr_selectOH2_T_3, 13, 0) node _mshr_selectOH2_T_5 = or(_mshr_selectOH2_T_2, _mshr_selectOH2_T_4) node _mshr_selectOH2_T_6 = shl(_mshr_selectOH2_T_5, 4) node _mshr_selectOH2_T_7 = bits(_mshr_selectOH2_T_6, 13, 0) node _mshr_selectOH2_T_8 = or(_mshr_selectOH2_T_5, _mshr_selectOH2_T_7) node _mshr_selectOH2_T_9 = shl(_mshr_selectOH2_T_8, 8) node _mshr_selectOH2_T_10 = bits(_mshr_selectOH2_T_9, 13, 0) node _mshr_selectOH2_T_11 = or(_mshr_selectOH2_T_8, _mshr_selectOH2_T_10) node _mshr_selectOH2_T_12 = bits(_mshr_selectOH2_T_11, 13, 0) node _mshr_selectOH2_T_13 = shl(_mshr_selectOH2_T_12, 1) node _mshr_selectOH2_T_14 = not(_mshr_selectOH2_T_13) node mshr_selectOH2 = and(_mshr_selectOH2_T_14, robin_request) node _mshr_selectOH_T = bits(mshr_selectOH2, 13, 7) node _mshr_selectOH_T_1 = bits(mshr_selectOH2, 6, 0) node mshr_selectOH = or(_mshr_selectOH_T, _mshr_selectOH_T_1) node mshr_select_hi = bits(mshr_selectOH, 6, 4) node mshr_select_lo = bits(mshr_selectOH, 3, 0) node _mshr_select_T = orr(mshr_select_hi) node _mshr_select_T_1 = or(mshr_select_hi, mshr_select_lo) node mshr_select_hi_1 = bits(_mshr_select_T_1, 3, 2) node mshr_select_lo_1 = bits(_mshr_select_T_1, 1, 0) node _mshr_select_T_2 = orr(mshr_select_hi_1) node _mshr_select_T_3 = or(mshr_select_hi_1, mshr_select_lo_1) node _mshr_select_T_4 = bits(_mshr_select_T_3, 1, 1) node _mshr_select_T_5 = cat(_mshr_select_T_2, _mshr_select_T_4) node mshr_select = cat(_mshr_select_T, _mshr_select_T_5) node _schedule_T = bits(mshr_selectOH, 0, 0) node _schedule_T_1 = bits(mshr_selectOH, 1, 1) node _schedule_T_2 = bits(mshr_selectOH, 2, 2) node _schedule_T_3 = bits(mshr_selectOH, 3, 3) node _schedule_T_4 = bits(mshr_selectOH, 4, 4) node _schedule_T_5 = bits(mshr_selectOH, 5, 5) node _schedule_T_6 = bits(mshr_selectOH, 6, 6) wire schedule : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>} node _schedule_T_7 = mux(_schedule_T, mshrs_0.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_8 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_9 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_10 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_11 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_12 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_13 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_14 = or(_schedule_T_7, _schedule_T_8) node _schedule_T_15 = or(_schedule_T_14, _schedule_T_9) node _schedule_T_16 = or(_schedule_T_15, _schedule_T_10) node _schedule_T_17 = or(_schedule_T_16, _schedule_T_11) node _schedule_T_18 = or(_schedule_T_17, _schedule_T_12) node _schedule_T_19 = or(_schedule_T_18, _schedule_T_13) wire _schedule_WIRE : UInt<1> connect _schedule_WIRE, _schedule_T_19 connect schedule.reload, _schedule_WIRE wire _schedule_WIRE_1 : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}} wire _schedule_WIRE_2 : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}} wire _schedule_WIRE_3 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} node _schedule_T_20 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_21 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_22 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_23 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_24 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_25 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_26 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_27 = or(_schedule_T_20, _schedule_T_21) node _schedule_T_28 = or(_schedule_T_27, _schedule_T_22) node _schedule_T_29 = or(_schedule_T_28, _schedule_T_23) node _schedule_T_30 = or(_schedule_T_29, _schedule_T_24) node _schedule_T_31 = or(_schedule_T_30, _schedule_T_25) node _schedule_T_32 = or(_schedule_T_31, _schedule_T_26) wire _schedule_WIRE_4 : UInt<13> connect _schedule_WIRE_4, _schedule_T_32 connect _schedule_WIRE_3.tag, _schedule_WIRE_4 node _schedule_T_33 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_34 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_35 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_36 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_37 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_38 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_39 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_40 = or(_schedule_T_33, _schedule_T_34) node _schedule_T_41 = or(_schedule_T_40, _schedule_T_35) node _schedule_T_42 = or(_schedule_T_41, _schedule_T_36) node _schedule_T_43 = or(_schedule_T_42, _schedule_T_37) node _schedule_T_44 = or(_schedule_T_43, _schedule_T_38) node _schedule_T_45 = or(_schedule_T_44, _schedule_T_39) wire _schedule_WIRE_5 : UInt<1> connect _schedule_WIRE_5, _schedule_T_45 connect _schedule_WIRE_3.clients, _schedule_WIRE_5 node _schedule_T_46 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_47 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_48 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_49 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_50 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_51 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_52 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_53 = or(_schedule_T_46, _schedule_T_47) node _schedule_T_54 = or(_schedule_T_53, _schedule_T_48) node _schedule_T_55 = or(_schedule_T_54, _schedule_T_49) node _schedule_T_56 = or(_schedule_T_55, _schedule_T_50) node _schedule_T_57 = or(_schedule_T_56, _schedule_T_51) node _schedule_T_58 = or(_schedule_T_57, _schedule_T_52) wire _schedule_WIRE_6 : UInt<2> connect _schedule_WIRE_6, _schedule_T_58 connect _schedule_WIRE_3.state, _schedule_WIRE_6 node _schedule_T_59 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_60 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_61 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_62 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_63 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_64 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_65 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_66 = or(_schedule_T_59, _schedule_T_60) node _schedule_T_67 = or(_schedule_T_66, _schedule_T_61) node _schedule_T_68 = or(_schedule_T_67, _schedule_T_62) node _schedule_T_69 = or(_schedule_T_68, _schedule_T_63) node _schedule_T_70 = or(_schedule_T_69, _schedule_T_64) node _schedule_T_71 = or(_schedule_T_70, _schedule_T_65) wire _schedule_WIRE_7 : UInt<1> connect _schedule_WIRE_7, _schedule_T_71 connect _schedule_WIRE_3.dirty, _schedule_WIRE_7 connect _schedule_WIRE_2.data, _schedule_WIRE_3 node _schedule_T_72 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_73 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_74 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_75 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_76 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_77 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_78 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_79 = or(_schedule_T_72, _schedule_T_73) node _schedule_T_80 = or(_schedule_T_79, _schedule_T_74) node _schedule_T_81 = or(_schedule_T_80, _schedule_T_75) node _schedule_T_82 = or(_schedule_T_81, _schedule_T_76) node _schedule_T_83 = or(_schedule_T_82, _schedule_T_77) node _schedule_T_84 = or(_schedule_T_83, _schedule_T_78) wire _schedule_WIRE_8 : UInt<3> connect _schedule_WIRE_8, _schedule_T_84 connect _schedule_WIRE_2.way, _schedule_WIRE_8 node _schedule_T_85 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_86 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_87 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_88 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_89 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_90 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_91 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_92 = or(_schedule_T_85, _schedule_T_86) node _schedule_T_93 = or(_schedule_T_92, _schedule_T_87) node _schedule_T_94 = or(_schedule_T_93, _schedule_T_88) node _schedule_T_95 = or(_schedule_T_94, _schedule_T_89) node _schedule_T_96 = or(_schedule_T_95, _schedule_T_90) node _schedule_T_97 = or(_schedule_T_96, _schedule_T_91) wire _schedule_WIRE_9 : UInt<10> connect _schedule_WIRE_9, _schedule_T_97 connect _schedule_WIRE_2.set, _schedule_WIRE_9 connect _schedule_WIRE_1.bits, _schedule_WIRE_2 node _schedule_T_98 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_99 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_100 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_101 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_102 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_103 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_104 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_105 = or(_schedule_T_98, _schedule_T_99) node _schedule_T_106 = or(_schedule_T_105, _schedule_T_100) node _schedule_T_107 = or(_schedule_T_106, _schedule_T_101) node _schedule_T_108 = or(_schedule_T_107, _schedule_T_102) node _schedule_T_109 = or(_schedule_T_108, _schedule_T_103) node _schedule_T_110 = or(_schedule_T_109, _schedule_T_104) wire _schedule_WIRE_10 : UInt<1> connect _schedule_WIRE_10, _schedule_T_110 connect _schedule_WIRE_1.valid, _schedule_WIRE_10 connect schedule.dir, _schedule_WIRE_1 wire _schedule_WIRE_11 : { valid : UInt<1>, bits : { fail : UInt<1>}} wire _schedule_WIRE_12 : { fail : UInt<1>} node _schedule_T_111 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_112 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_113 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_114 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_115 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_116 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_117 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_118 = or(_schedule_T_111, _schedule_T_112) node _schedule_T_119 = or(_schedule_T_118, _schedule_T_113) node _schedule_T_120 = or(_schedule_T_119, _schedule_T_114) node _schedule_T_121 = or(_schedule_T_120, _schedule_T_115) node _schedule_T_122 = or(_schedule_T_121, _schedule_T_116) node _schedule_T_123 = or(_schedule_T_122, _schedule_T_117) wire _schedule_WIRE_13 : UInt<1> connect _schedule_WIRE_13, _schedule_T_123 connect _schedule_WIRE_12.fail, _schedule_WIRE_13 connect _schedule_WIRE_11.bits, _schedule_WIRE_12 node _schedule_T_124 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_125 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_126 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_127 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_128 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_129 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_130 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_131 = or(_schedule_T_124, _schedule_T_125) node _schedule_T_132 = or(_schedule_T_131, _schedule_T_126) node _schedule_T_133 = or(_schedule_T_132, _schedule_T_127) node _schedule_T_134 = or(_schedule_T_133, _schedule_T_128) node _schedule_T_135 = or(_schedule_T_134, _schedule_T_129) node _schedule_T_136 = or(_schedule_T_135, _schedule_T_130) wire _schedule_WIRE_14 : UInt<1> connect _schedule_WIRE_14, _schedule_T_136 connect _schedule_WIRE_11.valid, _schedule_WIRE_14 connect schedule.x, _schedule_WIRE_11 wire _schedule_WIRE_15 : { valid : UInt<1>, bits : { sink : UInt<3>}} wire _schedule_WIRE_16 : { sink : UInt<3>} node _schedule_T_137 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_138 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_139 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_140 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_141 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_142 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_143 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_144 = or(_schedule_T_137, _schedule_T_138) node _schedule_T_145 = or(_schedule_T_144, _schedule_T_139) node _schedule_T_146 = or(_schedule_T_145, _schedule_T_140) node _schedule_T_147 = or(_schedule_T_146, _schedule_T_141) node _schedule_T_148 = or(_schedule_T_147, _schedule_T_142) node _schedule_T_149 = or(_schedule_T_148, _schedule_T_143) wire _schedule_WIRE_17 : UInt<3> connect _schedule_WIRE_17, _schedule_T_149 connect _schedule_WIRE_16.sink, _schedule_WIRE_17 connect _schedule_WIRE_15.bits, _schedule_WIRE_16 node _schedule_T_150 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_151 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_152 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_153 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_154 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_155 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_156 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_157 = or(_schedule_T_150, _schedule_T_151) node _schedule_T_158 = or(_schedule_T_157, _schedule_T_152) node _schedule_T_159 = or(_schedule_T_158, _schedule_T_153) node _schedule_T_160 = or(_schedule_T_159, _schedule_T_154) node _schedule_T_161 = or(_schedule_T_160, _schedule_T_155) node _schedule_T_162 = or(_schedule_T_161, _schedule_T_156) wire _schedule_WIRE_18 : UInt<1> connect _schedule_WIRE_18, _schedule_T_162 connect _schedule_WIRE_15.valid, _schedule_WIRE_18 connect schedule.e, _schedule_WIRE_15 wire _schedule_WIRE_19 : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}} wire _schedule_WIRE_20 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>} node _schedule_T_163 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_164 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_165 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_166 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_167 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_168 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_169 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_170 = or(_schedule_T_163, _schedule_T_164) node _schedule_T_171 = or(_schedule_T_170, _schedule_T_165) node _schedule_T_172 = or(_schedule_T_171, _schedule_T_166) node _schedule_T_173 = or(_schedule_T_172, _schedule_T_167) node _schedule_T_174 = or(_schedule_T_173, _schedule_T_168) node _schedule_T_175 = or(_schedule_T_174, _schedule_T_169) wire _schedule_WIRE_21 : UInt<1> connect _schedule_WIRE_21, _schedule_T_175 connect _schedule_WIRE_20.bad, _schedule_WIRE_21 node _schedule_T_176 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_177 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_178 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_179 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_180 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_181 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_182 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_183 = or(_schedule_T_176, _schedule_T_177) node _schedule_T_184 = or(_schedule_T_183, _schedule_T_178) node _schedule_T_185 = or(_schedule_T_184, _schedule_T_179) node _schedule_T_186 = or(_schedule_T_185, _schedule_T_180) node _schedule_T_187 = or(_schedule_T_186, _schedule_T_181) node _schedule_T_188 = or(_schedule_T_187, _schedule_T_182) wire _schedule_WIRE_22 : UInt<3> connect _schedule_WIRE_22, _schedule_T_188 connect _schedule_WIRE_20.way, _schedule_WIRE_22 node _schedule_T_189 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_190 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_191 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_192 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_193 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_194 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_195 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_196 = or(_schedule_T_189, _schedule_T_190) node _schedule_T_197 = or(_schedule_T_196, _schedule_T_191) node _schedule_T_198 = or(_schedule_T_197, _schedule_T_192) node _schedule_T_199 = or(_schedule_T_198, _schedule_T_193) node _schedule_T_200 = or(_schedule_T_199, _schedule_T_194) node _schedule_T_201 = or(_schedule_T_200, _schedule_T_195) wire _schedule_WIRE_23 : UInt<3> connect _schedule_WIRE_23, _schedule_T_201 connect _schedule_WIRE_20.sink, _schedule_WIRE_23 node _schedule_T_202 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_203 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_204 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_205 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_206 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_207 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_208 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_209 = or(_schedule_T_202, _schedule_T_203) node _schedule_T_210 = or(_schedule_T_209, _schedule_T_204) node _schedule_T_211 = or(_schedule_T_210, _schedule_T_205) node _schedule_T_212 = or(_schedule_T_211, _schedule_T_206) node _schedule_T_213 = or(_schedule_T_212, _schedule_T_207) node _schedule_T_214 = or(_schedule_T_213, _schedule_T_208) wire _schedule_WIRE_24 : UInt<10> connect _schedule_WIRE_24, _schedule_T_214 connect _schedule_WIRE_20.set, _schedule_WIRE_24 node _schedule_T_215 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_216 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_217 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_218 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_219 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_220 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_221 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_222 = or(_schedule_T_215, _schedule_T_216) node _schedule_T_223 = or(_schedule_T_222, _schedule_T_217) node _schedule_T_224 = or(_schedule_T_223, _schedule_T_218) node _schedule_T_225 = or(_schedule_T_224, _schedule_T_219) node _schedule_T_226 = or(_schedule_T_225, _schedule_T_220) node _schedule_T_227 = or(_schedule_T_226, _schedule_T_221) wire _schedule_WIRE_25 : UInt<6> connect _schedule_WIRE_25, _schedule_T_227 connect _schedule_WIRE_20.put, _schedule_WIRE_25 node _schedule_T_228 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_229 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_230 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_231 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_232 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_233 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_234 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_235 = or(_schedule_T_228, _schedule_T_229) node _schedule_T_236 = or(_schedule_T_235, _schedule_T_230) node _schedule_T_237 = or(_schedule_T_236, _schedule_T_231) node _schedule_T_238 = or(_schedule_T_237, _schedule_T_232) node _schedule_T_239 = or(_schedule_T_238, _schedule_T_233) node _schedule_T_240 = or(_schedule_T_239, _schedule_T_234) wire _schedule_WIRE_26 : UInt<6> connect _schedule_WIRE_26, _schedule_T_240 connect _schedule_WIRE_20.offset, _schedule_WIRE_26 node _schedule_T_241 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_242 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_243 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_244 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_245 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_246 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_247 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_248 = or(_schedule_T_241, _schedule_T_242) node _schedule_T_249 = or(_schedule_T_248, _schedule_T_243) node _schedule_T_250 = or(_schedule_T_249, _schedule_T_244) node _schedule_T_251 = or(_schedule_T_250, _schedule_T_245) node _schedule_T_252 = or(_schedule_T_251, _schedule_T_246) node _schedule_T_253 = or(_schedule_T_252, _schedule_T_247) wire _schedule_WIRE_27 : UInt<13> connect _schedule_WIRE_27, _schedule_T_253 connect _schedule_WIRE_20.tag, _schedule_WIRE_27 node _schedule_T_254 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_255 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_256 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_257 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_258 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_259 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_260 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_261 = or(_schedule_T_254, _schedule_T_255) node _schedule_T_262 = or(_schedule_T_261, _schedule_T_256) node _schedule_T_263 = or(_schedule_T_262, _schedule_T_257) node _schedule_T_264 = or(_schedule_T_263, _schedule_T_258) node _schedule_T_265 = or(_schedule_T_264, _schedule_T_259) node _schedule_T_266 = or(_schedule_T_265, _schedule_T_260) wire _schedule_WIRE_28 : UInt<6> connect _schedule_WIRE_28, _schedule_T_266 connect _schedule_WIRE_20.source, _schedule_WIRE_28 node _schedule_T_267 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_268 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_269 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_270 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_271 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_272 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_273 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_274 = or(_schedule_T_267, _schedule_T_268) node _schedule_T_275 = or(_schedule_T_274, _schedule_T_269) node _schedule_T_276 = or(_schedule_T_275, _schedule_T_270) node _schedule_T_277 = or(_schedule_T_276, _schedule_T_271) node _schedule_T_278 = or(_schedule_T_277, _schedule_T_272) node _schedule_T_279 = or(_schedule_T_278, _schedule_T_273) wire _schedule_WIRE_29 : UInt<3> connect _schedule_WIRE_29, _schedule_T_279 connect _schedule_WIRE_20.size, _schedule_WIRE_29 node _schedule_T_280 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_281 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_282 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_283 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_284 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_285 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_286 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_287 = or(_schedule_T_280, _schedule_T_281) node _schedule_T_288 = or(_schedule_T_287, _schedule_T_282) node _schedule_T_289 = or(_schedule_T_288, _schedule_T_283) node _schedule_T_290 = or(_schedule_T_289, _schedule_T_284) node _schedule_T_291 = or(_schedule_T_290, _schedule_T_285) node _schedule_T_292 = or(_schedule_T_291, _schedule_T_286) wire _schedule_WIRE_30 : UInt<3> connect _schedule_WIRE_30, _schedule_T_292 connect _schedule_WIRE_20.param, _schedule_WIRE_30 node _schedule_T_293 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_294 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_295 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_296 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_297 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_298 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_299 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_300 = or(_schedule_T_293, _schedule_T_294) node _schedule_T_301 = or(_schedule_T_300, _schedule_T_295) node _schedule_T_302 = or(_schedule_T_301, _schedule_T_296) node _schedule_T_303 = or(_schedule_T_302, _schedule_T_297) node _schedule_T_304 = or(_schedule_T_303, _schedule_T_298) node _schedule_T_305 = or(_schedule_T_304, _schedule_T_299) wire _schedule_WIRE_31 : UInt<3> connect _schedule_WIRE_31, _schedule_T_305 connect _schedule_WIRE_20.opcode, _schedule_WIRE_31 node _schedule_T_306 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_307 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_308 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_309 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_310 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_311 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_312 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_313 = or(_schedule_T_306, _schedule_T_307) node _schedule_T_314 = or(_schedule_T_313, _schedule_T_308) node _schedule_T_315 = or(_schedule_T_314, _schedule_T_309) node _schedule_T_316 = or(_schedule_T_315, _schedule_T_310) node _schedule_T_317 = or(_schedule_T_316, _schedule_T_311) node _schedule_T_318 = or(_schedule_T_317, _schedule_T_312) wire _schedule_WIRE_32 : UInt<1> connect _schedule_WIRE_32, _schedule_T_318 connect _schedule_WIRE_20.control, _schedule_WIRE_32 wire _schedule_WIRE_33 : UInt<1>[3] node _schedule_T_319 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_320 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_321 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_322 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_323 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_324 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_325 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_326 = or(_schedule_T_319, _schedule_T_320) node _schedule_T_327 = or(_schedule_T_326, _schedule_T_321) node _schedule_T_328 = or(_schedule_T_327, _schedule_T_322) node _schedule_T_329 = or(_schedule_T_328, _schedule_T_323) node _schedule_T_330 = or(_schedule_T_329, _schedule_T_324) node _schedule_T_331 = or(_schedule_T_330, _schedule_T_325) wire _schedule_WIRE_34 : UInt<1> connect _schedule_WIRE_34, _schedule_T_331 connect _schedule_WIRE_33[0], _schedule_WIRE_34 node _schedule_T_332 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_333 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_334 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_335 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_336 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_337 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_338 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_339 = or(_schedule_T_332, _schedule_T_333) node _schedule_T_340 = or(_schedule_T_339, _schedule_T_334) node _schedule_T_341 = or(_schedule_T_340, _schedule_T_335) node _schedule_T_342 = or(_schedule_T_341, _schedule_T_336) node _schedule_T_343 = or(_schedule_T_342, _schedule_T_337) node _schedule_T_344 = or(_schedule_T_343, _schedule_T_338) wire _schedule_WIRE_35 : UInt<1> connect _schedule_WIRE_35, _schedule_T_344 connect _schedule_WIRE_33[1], _schedule_WIRE_35 node _schedule_T_345 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_346 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_347 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_348 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_349 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_350 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_351 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_352 = or(_schedule_T_345, _schedule_T_346) node _schedule_T_353 = or(_schedule_T_352, _schedule_T_347) node _schedule_T_354 = or(_schedule_T_353, _schedule_T_348) node _schedule_T_355 = or(_schedule_T_354, _schedule_T_349) node _schedule_T_356 = or(_schedule_T_355, _schedule_T_350) node _schedule_T_357 = or(_schedule_T_356, _schedule_T_351) wire _schedule_WIRE_36 : UInt<1> connect _schedule_WIRE_36, _schedule_T_357 connect _schedule_WIRE_33[2], _schedule_WIRE_36 connect _schedule_WIRE_20.prio, _schedule_WIRE_33 connect _schedule_WIRE_19.bits, _schedule_WIRE_20 node _schedule_T_358 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_359 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_360 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_361 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_362 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_363 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_364 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_365 = or(_schedule_T_358, _schedule_T_359) node _schedule_T_366 = or(_schedule_T_365, _schedule_T_360) node _schedule_T_367 = or(_schedule_T_366, _schedule_T_361) node _schedule_T_368 = or(_schedule_T_367, _schedule_T_362) node _schedule_T_369 = or(_schedule_T_368, _schedule_T_363) node _schedule_T_370 = or(_schedule_T_369, _schedule_T_364) wire _schedule_WIRE_37 : UInt<1> connect _schedule_WIRE_37, _schedule_T_370 connect _schedule_WIRE_19.valid, _schedule_WIRE_37 connect schedule.d, _schedule_WIRE_19 wire _schedule_WIRE_38 : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}} wire _schedule_WIRE_39 : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>} node _schedule_T_371 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_372 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_373 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_374 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_375 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_376 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_377 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_378 = or(_schedule_T_371, _schedule_T_372) node _schedule_T_379 = or(_schedule_T_378, _schedule_T_373) node _schedule_T_380 = or(_schedule_T_379, _schedule_T_374) node _schedule_T_381 = or(_schedule_T_380, _schedule_T_375) node _schedule_T_382 = or(_schedule_T_381, _schedule_T_376) node _schedule_T_383 = or(_schedule_T_382, _schedule_T_377) wire _schedule_WIRE_40 : UInt<1> connect _schedule_WIRE_40, _schedule_T_383 connect _schedule_WIRE_39.dirty, _schedule_WIRE_40 node _schedule_T_384 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_385 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_386 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_387 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_388 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_389 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_390 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_391 = or(_schedule_T_384, _schedule_T_385) node _schedule_T_392 = or(_schedule_T_391, _schedule_T_386) node _schedule_T_393 = or(_schedule_T_392, _schedule_T_387) node _schedule_T_394 = or(_schedule_T_393, _schedule_T_388) node _schedule_T_395 = or(_schedule_T_394, _schedule_T_389) node _schedule_T_396 = or(_schedule_T_395, _schedule_T_390) wire _schedule_WIRE_41 : UInt<3> connect _schedule_WIRE_41, _schedule_T_396 connect _schedule_WIRE_39.way, _schedule_WIRE_41 node _schedule_T_397 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_398 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_399 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_400 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_401 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_402 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_403 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_404 = or(_schedule_T_397, _schedule_T_398) node _schedule_T_405 = or(_schedule_T_404, _schedule_T_399) node _schedule_T_406 = or(_schedule_T_405, _schedule_T_400) node _schedule_T_407 = or(_schedule_T_406, _schedule_T_401) node _schedule_T_408 = or(_schedule_T_407, _schedule_T_402) node _schedule_T_409 = or(_schedule_T_408, _schedule_T_403) wire _schedule_WIRE_42 : UInt<10> connect _schedule_WIRE_42, _schedule_T_409 connect _schedule_WIRE_39.set, _schedule_WIRE_42 node _schedule_T_410 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_411 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_412 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_413 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_414 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_415 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_416 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_417 = or(_schedule_T_410, _schedule_T_411) node _schedule_T_418 = or(_schedule_T_417, _schedule_T_412) node _schedule_T_419 = or(_schedule_T_418, _schedule_T_413) node _schedule_T_420 = or(_schedule_T_419, _schedule_T_414) node _schedule_T_421 = or(_schedule_T_420, _schedule_T_415) node _schedule_T_422 = or(_schedule_T_421, _schedule_T_416) wire _schedule_WIRE_43 : UInt<13> connect _schedule_WIRE_43, _schedule_T_422 connect _schedule_WIRE_39.tag, _schedule_WIRE_43 node _schedule_T_423 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_424 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_425 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_426 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_427 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_428 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_429 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_430 = or(_schedule_T_423, _schedule_T_424) node _schedule_T_431 = or(_schedule_T_430, _schedule_T_425) node _schedule_T_432 = or(_schedule_T_431, _schedule_T_426) node _schedule_T_433 = or(_schedule_T_432, _schedule_T_427) node _schedule_T_434 = or(_schedule_T_433, _schedule_T_428) node _schedule_T_435 = or(_schedule_T_434, _schedule_T_429) wire _schedule_WIRE_44 : UInt<3> connect _schedule_WIRE_44, _schedule_T_435 connect _schedule_WIRE_39.source, _schedule_WIRE_44 node _schedule_T_436 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_437 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_438 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_439 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_440 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_441 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_442 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_443 = or(_schedule_T_436, _schedule_T_437) node _schedule_T_444 = or(_schedule_T_443, _schedule_T_438) node _schedule_T_445 = or(_schedule_T_444, _schedule_T_439) node _schedule_T_446 = or(_schedule_T_445, _schedule_T_440) node _schedule_T_447 = or(_schedule_T_446, _schedule_T_441) node _schedule_T_448 = or(_schedule_T_447, _schedule_T_442) wire _schedule_WIRE_45 : UInt<3> connect _schedule_WIRE_45, _schedule_T_448 connect _schedule_WIRE_39.param, _schedule_WIRE_45 node _schedule_T_449 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_450 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_451 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_452 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_453 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_454 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_455 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_456 = or(_schedule_T_449, _schedule_T_450) node _schedule_T_457 = or(_schedule_T_456, _schedule_T_451) node _schedule_T_458 = or(_schedule_T_457, _schedule_T_452) node _schedule_T_459 = or(_schedule_T_458, _schedule_T_453) node _schedule_T_460 = or(_schedule_T_459, _schedule_T_454) node _schedule_T_461 = or(_schedule_T_460, _schedule_T_455) wire _schedule_WIRE_46 : UInt<3> connect _schedule_WIRE_46, _schedule_T_461 connect _schedule_WIRE_39.opcode, _schedule_WIRE_46 connect _schedule_WIRE_38.bits, _schedule_WIRE_39 node _schedule_T_462 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_463 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_464 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_465 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_466 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_467 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_468 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_469 = or(_schedule_T_462, _schedule_T_463) node _schedule_T_470 = or(_schedule_T_469, _schedule_T_464) node _schedule_T_471 = or(_schedule_T_470, _schedule_T_465) node _schedule_T_472 = or(_schedule_T_471, _schedule_T_466) node _schedule_T_473 = or(_schedule_T_472, _schedule_T_467) node _schedule_T_474 = or(_schedule_T_473, _schedule_T_468) wire _schedule_WIRE_47 : UInt<1> connect _schedule_WIRE_47, _schedule_T_474 connect _schedule_WIRE_38.valid, _schedule_WIRE_47 connect schedule.c, _schedule_WIRE_38 wire _schedule_WIRE_48 : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}} wire _schedule_WIRE_49 : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>} node _schedule_T_475 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_476 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_477 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_478 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_479 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_480 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_481 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_482 = or(_schedule_T_475, _schedule_T_476) node _schedule_T_483 = or(_schedule_T_482, _schedule_T_477) node _schedule_T_484 = or(_schedule_T_483, _schedule_T_478) node _schedule_T_485 = or(_schedule_T_484, _schedule_T_479) node _schedule_T_486 = or(_schedule_T_485, _schedule_T_480) node _schedule_T_487 = or(_schedule_T_486, _schedule_T_481) wire _schedule_WIRE_50 : UInt<1> connect _schedule_WIRE_50, _schedule_T_487 connect _schedule_WIRE_49.clients, _schedule_WIRE_50 node _schedule_T_488 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_489 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_490 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_491 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_492 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_493 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_494 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_495 = or(_schedule_T_488, _schedule_T_489) node _schedule_T_496 = or(_schedule_T_495, _schedule_T_490) node _schedule_T_497 = or(_schedule_T_496, _schedule_T_491) node _schedule_T_498 = or(_schedule_T_497, _schedule_T_492) node _schedule_T_499 = or(_schedule_T_498, _schedule_T_493) node _schedule_T_500 = or(_schedule_T_499, _schedule_T_494) wire _schedule_WIRE_51 : UInt<10> connect _schedule_WIRE_51, _schedule_T_500 connect _schedule_WIRE_49.set, _schedule_WIRE_51 node _schedule_T_501 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_502 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_503 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_504 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_505 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_506 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_507 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_508 = or(_schedule_T_501, _schedule_T_502) node _schedule_T_509 = or(_schedule_T_508, _schedule_T_503) node _schedule_T_510 = or(_schedule_T_509, _schedule_T_504) node _schedule_T_511 = or(_schedule_T_510, _schedule_T_505) node _schedule_T_512 = or(_schedule_T_511, _schedule_T_506) node _schedule_T_513 = or(_schedule_T_512, _schedule_T_507) wire _schedule_WIRE_52 : UInt<13> connect _schedule_WIRE_52, _schedule_T_513 connect _schedule_WIRE_49.tag, _schedule_WIRE_52 node _schedule_T_514 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_515 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_516 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_517 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_518 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_519 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_520 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_521 = or(_schedule_T_514, _schedule_T_515) node _schedule_T_522 = or(_schedule_T_521, _schedule_T_516) node _schedule_T_523 = or(_schedule_T_522, _schedule_T_517) node _schedule_T_524 = or(_schedule_T_523, _schedule_T_518) node _schedule_T_525 = or(_schedule_T_524, _schedule_T_519) node _schedule_T_526 = or(_schedule_T_525, _schedule_T_520) wire _schedule_WIRE_53 : UInt<3> connect _schedule_WIRE_53, _schedule_T_526 connect _schedule_WIRE_49.param, _schedule_WIRE_53 connect _schedule_WIRE_48.bits, _schedule_WIRE_49 node _schedule_T_527 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_528 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_529 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_530 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_531 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_532 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_533 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_534 = or(_schedule_T_527, _schedule_T_528) node _schedule_T_535 = or(_schedule_T_534, _schedule_T_529) node _schedule_T_536 = or(_schedule_T_535, _schedule_T_530) node _schedule_T_537 = or(_schedule_T_536, _schedule_T_531) node _schedule_T_538 = or(_schedule_T_537, _schedule_T_532) node _schedule_T_539 = or(_schedule_T_538, _schedule_T_533) wire _schedule_WIRE_54 : UInt<1> connect _schedule_WIRE_54, _schedule_T_539 connect _schedule_WIRE_48.valid, _schedule_WIRE_54 connect schedule.b, _schedule_WIRE_48 wire _schedule_WIRE_55 : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}} wire _schedule_WIRE_56 : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>} node _schedule_T_540 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_541 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_542 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_543 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_544 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_545 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_546 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_547 = or(_schedule_T_540, _schedule_T_541) node _schedule_T_548 = or(_schedule_T_547, _schedule_T_542) node _schedule_T_549 = or(_schedule_T_548, _schedule_T_543) node _schedule_T_550 = or(_schedule_T_549, _schedule_T_544) node _schedule_T_551 = or(_schedule_T_550, _schedule_T_545) node _schedule_T_552 = or(_schedule_T_551, _schedule_T_546) wire _schedule_WIRE_57 : UInt<1> connect _schedule_WIRE_57, _schedule_T_552 connect _schedule_WIRE_56.block, _schedule_WIRE_57 node _schedule_T_553 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_554 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_555 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_556 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_557 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_558 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_559 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_560 = or(_schedule_T_553, _schedule_T_554) node _schedule_T_561 = or(_schedule_T_560, _schedule_T_555) node _schedule_T_562 = or(_schedule_T_561, _schedule_T_556) node _schedule_T_563 = or(_schedule_T_562, _schedule_T_557) node _schedule_T_564 = or(_schedule_T_563, _schedule_T_558) node _schedule_T_565 = or(_schedule_T_564, _schedule_T_559) wire _schedule_WIRE_58 : UInt<3> connect _schedule_WIRE_58, _schedule_T_565 connect _schedule_WIRE_56.source, _schedule_WIRE_58 node _schedule_T_566 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_567 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_568 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_569 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_570 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_571 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_572 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_573 = or(_schedule_T_566, _schedule_T_567) node _schedule_T_574 = or(_schedule_T_573, _schedule_T_568) node _schedule_T_575 = or(_schedule_T_574, _schedule_T_569) node _schedule_T_576 = or(_schedule_T_575, _schedule_T_570) node _schedule_T_577 = or(_schedule_T_576, _schedule_T_571) node _schedule_T_578 = or(_schedule_T_577, _schedule_T_572) wire _schedule_WIRE_59 : UInt<3> connect _schedule_WIRE_59, _schedule_T_578 connect _schedule_WIRE_56.param, _schedule_WIRE_59 node _schedule_T_579 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_580 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_581 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_582 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_583 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_584 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_585 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_586 = or(_schedule_T_579, _schedule_T_580) node _schedule_T_587 = or(_schedule_T_586, _schedule_T_581) node _schedule_T_588 = or(_schedule_T_587, _schedule_T_582) node _schedule_T_589 = or(_schedule_T_588, _schedule_T_583) node _schedule_T_590 = or(_schedule_T_589, _schedule_T_584) node _schedule_T_591 = or(_schedule_T_590, _schedule_T_585) wire _schedule_WIRE_60 : UInt<10> connect _schedule_WIRE_60, _schedule_T_591 connect _schedule_WIRE_56.set, _schedule_WIRE_60 node _schedule_T_592 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_593 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_594 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_595 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_596 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_597 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_598 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_599 = or(_schedule_T_592, _schedule_T_593) node _schedule_T_600 = or(_schedule_T_599, _schedule_T_594) node _schedule_T_601 = or(_schedule_T_600, _schedule_T_595) node _schedule_T_602 = or(_schedule_T_601, _schedule_T_596) node _schedule_T_603 = or(_schedule_T_602, _schedule_T_597) node _schedule_T_604 = or(_schedule_T_603, _schedule_T_598) wire _schedule_WIRE_61 : UInt<13> connect _schedule_WIRE_61, _schedule_T_604 connect _schedule_WIRE_56.tag, _schedule_WIRE_61 connect _schedule_WIRE_55.bits, _schedule_WIRE_56 node _schedule_T_605 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_606 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_607 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_608 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_609 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_610 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_611 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_612 = or(_schedule_T_605, _schedule_T_606) node _schedule_T_613 = or(_schedule_T_612, _schedule_T_607) node _schedule_T_614 = or(_schedule_T_613, _schedule_T_608) node _schedule_T_615 = or(_schedule_T_614, _schedule_T_609) node _schedule_T_616 = or(_schedule_T_615, _schedule_T_610) node _schedule_T_617 = or(_schedule_T_616, _schedule_T_611) wire _schedule_WIRE_62 : UInt<1> connect _schedule_WIRE_62, _schedule_T_617 connect _schedule_WIRE_55.valid, _schedule_WIRE_62 connect schedule.a, _schedule_WIRE_55 node _scheduleTag_T = bits(mshr_selectOH, 0, 0) node _scheduleTag_T_1 = bits(mshr_selectOH, 1, 1) node _scheduleTag_T_2 = bits(mshr_selectOH, 2, 2) node _scheduleTag_T_3 = bits(mshr_selectOH, 3, 3) node _scheduleTag_T_4 = bits(mshr_selectOH, 4, 4) node _scheduleTag_T_5 = bits(mshr_selectOH, 5, 5) node _scheduleTag_T_6 = bits(mshr_selectOH, 6, 6) node _scheduleTag_T_7 = mux(_scheduleTag_T, mshrs_0.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_8 = mux(_scheduleTag_T_1, mshrs_1.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_9 = mux(_scheduleTag_T_2, mshrs_2.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_10 = mux(_scheduleTag_T_3, mshrs_3.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_11 = mux(_scheduleTag_T_4, mshrs_4.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_12 = mux(_scheduleTag_T_5, mshrs_5.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_13 = mux(_scheduleTag_T_6, mshrs_6.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_14 = or(_scheduleTag_T_7, _scheduleTag_T_8) node _scheduleTag_T_15 = or(_scheduleTag_T_14, _scheduleTag_T_9) node _scheduleTag_T_16 = or(_scheduleTag_T_15, _scheduleTag_T_10) node _scheduleTag_T_17 = or(_scheduleTag_T_16, _scheduleTag_T_11) node _scheduleTag_T_18 = or(_scheduleTag_T_17, _scheduleTag_T_12) node _scheduleTag_T_19 = or(_scheduleTag_T_18, _scheduleTag_T_13) wire scheduleTag : UInt<13> connect scheduleTag, _scheduleTag_T_19 node _scheduleSet_T = bits(mshr_selectOH, 0, 0) node _scheduleSet_T_1 = bits(mshr_selectOH, 1, 1) node _scheduleSet_T_2 = bits(mshr_selectOH, 2, 2) node _scheduleSet_T_3 = bits(mshr_selectOH, 3, 3) node _scheduleSet_T_4 = bits(mshr_selectOH, 4, 4) node _scheduleSet_T_5 = bits(mshr_selectOH, 5, 5) node _scheduleSet_T_6 = bits(mshr_selectOH, 6, 6) node _scheduleSet_T_7 = mux(_scheduleSet_T, mshrs_0.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_8 = mux(_scheduleSet_T_1, mshrs_1.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_9 = mux(_scheduleSet_T_2, mshrs_2.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_10 = mux(_scheduleSet_T_3, mshrs_3.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_11 = mux(_scheduleSet_T_4, mshrs_4.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_12 = mux(_scheduleSet_T_5, mshrs_5.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_13 = mux(_scheduleSet_T_6, mshrs_6.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_14 = or(_scheduleSet_T_7, _scheduleSet_T_8) node _scheduleSet_T_15 = or(_scheduleSet_T_14, _scheduleSet_T_9) node _scheduleSet_T_16 = or(_scheduleSet_T_15, _scheduleSet_T_10) node _scheduleSet_T_17 = or(_scheduleSet_T_16, _scheduleSet_T_11) node _scheduleSet_T_18 = or(_scheduleSet_T_17, _scheduleSet_T_12) node _scheduleSet_T_19 = or(_scheduleSet_T_18, _scheduleSet_T_13) wire scheduleSet : UInt<10> connect scheduleSet, _scheduleSet_T_19 node _T_4 = orr(mshr_request) when _T_4 : node _robin_filter_T = shr(mshr_selectOH, 1) node _robin_filter_T_1 = or(mshr_selectOH, _robin_filter_T) node _robin_filter_T_2 = shr(_robin_filter_T_1, 2) node _robin_filter_T_3 = or(_robin_filter_T_1, _robin_filter_T_2) node _robin_filter_T_4 = shr(_robin_filter_T_3, 4) node _robin_filter_T_5 = or(_robin_filter_T_3, _robin_filter_T_4) node _robin_filter_T_6 = bits(_robin_filter_T_5, 6, 0) node _robin_filter_T_7 = not(_robin_filter_T_6) connect robin_filter, _robin_filter_T_7 connect schedule.a.bits.source, mshr_select node _schedule_c_bits_source_T = bits(schedule.c.bits.opcode, 1, 1) node _schedule_c_bits_source_T_1 = mux(_schedule_c_bits_source_T, mshr_select, UInt<1>(0h0)) connect schedule.c.bits.source, _schedule_c_bits_source_T_1 connect schedule.d.bits.sink, mshr_select connect sourceA.io.req.valid, schedule.a.valid connect sourceB.io.req.valid, schedule.b.valid connect sourceC.io.req.valid, schedule.c.valid connect sourceD.io.req.valid, schedule.d.valid connect sourceE.io.req.valid, schedule.e.valid connect sourceX.io.req.valid, schedule.x.valid connect sourceA.io.req.bits.block, schedule.a.bits.block connect sourceA.io.req.bits.source, schedule.a.bits.source connect sourceA.io.req.bits.param, schedule.a.bits.param connect sourceA.io.req.bits.set, schedule.a.bits.set connect sourceA.io.req.bits.tag, schedule.a.bits.tag connect sourceB.io.req.bits.clients, schedule.b.bits.clients connect sourceB.io.req.bits.set, schedule.b.bits.set connect sourceB.io.req.bits.tag, schedule.b.bits.tag connect sourceB.io.req.bits.param, schedule.b.bits.param connect sourceC.io.req.bits.dirty, schedule.c.bits.dirty connect sourceC.io.req.bits.way, schedule.c.bits.way connect sourceC.io.req.bits.set, schedule.c.bits.set connect sourceC.io.req.bits.tag, schedule.c.bits.tag connect sourceC.io.req.bits.source, schedule.c.bits.source connect sourceC.io.req.bits.param, schedule.c.bits.param connect sourceC.io.req.bits.opcode, schedule.c.bits.opcode connect sourceD.io.req.bits.bad, schedule.d.bits.bad connect sourceD.io.req.bits.way, schedule.d.bits.way connect sourceD.io.req.bits.sink, schedule.d.bits.sink connect sourceD.io.req.bits.set, schedule.d.bits.set connect sourceD.io.req.bits.put, schedule.d.bits.put connect sourceD.io.req.bits.offset, schedule.d.bits.offset connect sourceD.io.req.bits.tag, schedule.d.bits.tag connect sourceD.io.req.bits.source, schedule.d.bits.source connect sourceD.io.req.bits.size, schedule.d.bits.size connect sourceD.io.req.bits.param, schedule.d.bits.param connect sourceD.io.req.bits.opcode, schedule.d.bits.opcode connect sourceD.io.req.bits.control, schedule.d.bits.control connect sourceD.io.req.bits.prio[0], schedule.d.bits.prio[0] connect sourceD.io.req.bits.prio[1], schedule.d.bits.prio[1] connect sourceD.io.req.bits.prio[2], schedule.d.bits.prio[2] connect sourceE.io.req.bits.sink, schedule.e.bits.sink connect sourceX.io.req.bits.fail, schedule.x.bits.fail connect directory.io.write.valid, schedule.dir.valid connect directory.io.write.bits.data.tag, schedule.dir.bits.data.tag connect directory.io.write.bits.data.clients, schedule.dir.bits.data.clients connect directory.io.write.bits.data.state, schedule.dir.bits.data.state connect directory.io.write.bits.data.dirty, schedule.dir.bits.data.dirty connect directory.io.write.bits.way, schedule.dir.bits.way connect directory.io.write.bits.set, schedule.dir.bits.set node select_c = bits(mshr_selectOH, 6, 6) node select_bc = bits(mshr_selectOH, 5, 5) node _nestedwb_set_T = mux(select_c, mshrs_6.io.status.bits.set, mshrs_5.io.status.bits.set) connect nestedwb.set, _nestedwb_set_T node _nestedwb_tag_T = mux(select_c, mshrs_6.io.status.bits.tag, mshrs_5.io.status.bits.tag) connect nestedwb.tag, _nestedwb_tag_T node _nestedwb_b_toN_T = and(select_bc, mshrs_5.io.schedule.bits.dir.valid) node _nestedwb_b_toN_T_1 = eq(mshrs_5.io.schedule.bits.dir.bits.data.state, UInt<2>(0h0)) node _nestedwb_b_toN_T_2 = and(_nestedwb_b_toN_T, _nestedwb_b_toN_T_1) connect nestedwb.b_toN, _nestedwb_b_toN_T_2 node _nestedwb_b_toB_T = and(select_bc, mshrs_5.io.schedule.bits.dir.valid) node _nestedwb_b_toB_T_1 = eq(mshrs_5.io.schedule.bits.dir.bits.data.state, UInt<2>(0h1)) node _nestedwb_b_toB_T_2 = and(_nestedwb_b_toB_T, _nestedwb_b_toB_T_1) connect nestedwb.b_toB, _nestedwb_b_toB_T_2 node _nestedwb_b_clr_dirty_T = and(select_bc, mshrs_5.io.schedule.bits.dir.valid) connect nestedwb.b_clr_dirty, _nestedwb_b_clr_dirty_T node _nestedwb_c_set_dirty_T = and(select_c, mshrs_6.io.schedule.bits.dir.valid) node _nestedwb_c_set_dirty_T_1 = and(_nestedwb_c_set_dirty_T, mshrs_6.io.schedule.bits.dir.bits.data.dirty) connect nestedwb.c_set_dirty, _nestedwb_c_set_dirty_T_1 wire request : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}} node _request_valid_T = or(sinkA.io.req.valid, sinkX.io.req.valid) node _request_valid_T_1 = or(_request_valid_T, sinkC.io.req.valid) node _request_valid_T_2 = and(directory.io.ready, _request_valid_T_1) connect request.valid, _request_valid_T_2 node _request_bits_T = mux(sinkX.io.req.valid, sinkX.io.req.bits, sinkA.io.req.bits) node _request_bits_T_1 = mux(sinkC.io.req.valid, sinkC.io.req.bits, _request_bits_T) connect request.bits, _request_bits_T_1 node _sinkC_io_req_ready_T = and(directory.io.ready, request.ready) connect sinkC.io.req.ready, _sinkC_io_req_ready_T node _sinkX_io_req_ready_T = and(directory.io.ready, request.ready) node _sinkX_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0)) node _sinkX_io_req_ready_T_2 = and(_sinkX_io_req_ready_T, _sinkX_io_req_ready_T_1) connect sinkX.io.req.ready, _sinkX_io_req_ready_T_2 node _sinkA_io_req_ready_T = and(directory.io.ready, request.ready) node _sinkA_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0)) node _sinkA_io_req_ready_T_2 = and(_sinkA_io_req_ready_T, _sinkA_io_req_ready_T_1) node _sinkA_io_req_ready_T_3 = eq(sinkX.io.req.valid, UInt<1>(0h0)) node _sinkA_io_req_ready_T_4 = and(_sinkA_io_req_ready_T_2, _sinkA_io_req_ready_T_3) connect sinkA.io.req.ready, _sinkA_io_req_ready_T_4 node _setMatches_T = eq(mshrs_0.io.status.bits.set, request.bits.set) node _setMatches_T_1 = and(mshrs_0.io.status.valid, _setMatches_T) node _setMatches_T_2 = eq(mshrs_1.io.status.bits.set, request.bits.set) node _setMatches_T_3 = and(mshrs_1.io.status.valid, _setMatches_T_2) node _setMatches_T_4 = eq(mshrs_2.io.status.bits.set, request.bits.set) node _setMatches_T_5 = and(mshrs_2.io.status.valid, _setMatches_T_4) node _setMatches_T_6 = eq(mshrs_3.io.status.bits.set, request.bits.set) node _setMatches_T_7 = and(mshrs_3.io.status.valid, _setMatches_T_6) node _setMatches_T_8 = eq(mshrs_4.io.status.bits.set, request.bits.set) node _setMatches_T_9 = and(mshrs_4.io.status.valid, _setMatches_T_8) node _setMatches_T_10 = eq(mshrs_5.io.status.bits.set, request.bits.set) node _setMatches_T_11 = and(mshrs_5.io.status.valid, _setMatches_T_10) node _setMatches_T_12 = eq(mshrs_6.io.status.bits.set, request.bits.set) node _setMatches_T_13 = and(mshrs_6.io.status.valid, _setMatches_T_12) node setMatches_lo_hi = cat(_setMatches_T_5, _setMatches_T_3) node setMatches_lo = cat(setMatches_lo_hi, _setMatches_T_1) node setMatches_hi_lo = cat(_setMatches_T_9, _setMatches_T_7) node setMatches_hi_hi = cat(_setMatches_T_13, _setMatches_T_11) node setMatches_hi = cat(setMatches_hi_hi, setMatches_hi_lo) node setMatches = cat(setMatches_hi, setMatches_lo) node _alloc_T = orr(setMatches) node alloc = eq(_alloc_T, UInt<1>(0h0)) node _blockB_T = bits(setMatches, 0, 0) node _blockB_T_1 = bits(setMatches, 1, 1) node _blockB_T_2 = bits(setMatches, 2, 2) node _blockB_T_3 = bits(setMatches, 3, 3) node _blockB_T_4 = bits(setMatches, 4, 4) node _blockB_T_5 = bits(setMatches, 5, 5) node _blockB_T_6 = bits(setMatches, 6, 6) node _blockB_T_7 = mux(_blockB_T, mshrs_0.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_8 = mux(_blockB_T_1, mshrs_1.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_9 = mux(_blockB_T_2, mshrs_2.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_10 = mux(_blockB_T_3, mshrs_3.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_11 = mux(_blockB_T_4, mshrs_4.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_12 = mux(_blockB_T_5, mshrs_5.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_13 = mux(_blockB_T_6, mshrs_6.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_14 = or(_blockB_T_7, _blockB_T_8) node _blockB_T_15 = or(_blockB_T_14, _blockB_T_9) node _blockB_T_16 = or(_blockB_T_15, _blockB_T_10) node _blockB_T_17 = or(_blockB_T_16, _blockB_T_11) node _blockB_T_18 = or(_blockB_T_17, _blockB_T_12) node _blockB_T_19 = or(_blockB_T_18, _blockB_T_13) wire _blockB_WIRE : UInt<1> connect _blockB_WIRE, _blockB_T_19 node blockB = and(_blockB_WIRE, request.bits.prio[1]) node _blockC_T = bits(setMatches, 0, 0) node _blockC_T_1 = bits(setMatches, 1, 1) node _blockC_T_2 = bits(setMatches, 2, 2) node _blockC_T_3 = bits(setMatches, 3, 3) node _blockC_T_4 = bits(setMatches, 4, 4) node _blockC_T_5 = bits(setMatches, 5, 5) node _blockC_T_6 = bits(setMatches, 6, 6) node _blockC_T_7 = mux(_blockC_T, mshrs_0.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_8 = mux(_blockC_T_1, mshrs_1.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_9 = mux(_blockC_T_2, mshrs_2.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_10 = mux(_blockC_T_3, mshrs_3.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_11 = mux(_blockC_T_4, mshrs_4.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_12 = mux(_blockC_T_5, mshrs_5.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_13 = mux(_blockC_T_6, mshrs_6.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_14 = or(_blockC_T_7, _blockC_T_8) node _blockC_T_15 = or(_blockC_T_14, _blockC_T_9) node _blockC_T_16 = or(_blockC_T_15, _blockC_T_10) node _blockC_T_17 = or(_blockC_T_16, _blockC_T_11) node _blockC_T_18 = or(_blockC_T_17, _blockC_T_12) node _blockC_T_19 = or(_blockC_T_18, _blockC_T_13) wire _blockC_WIRE : UInt<1> connect _blockC_WIRE, _blockC_T_19 node blockC = and(_blockC_WIRE, request.bits.prio[2]) node _nestB_T = bits(setMatches, 0, 0) node _nestB_T_1 = bits(setMatches, 1, 1) node _nestB_T_2 = bits(setMatches, 2, 2) node _nestB_T_3 = bits(setMatches, 3, 3) node _nestB_T_4 = bits(setMatches, 4, 4) node _nestB_T_5 = bits(setMatches, 5, 5) node _nestB_T_6 = bits(setMatches, 6, 6) node _nestB_T_7 = mux(_nestB_T, mshrs_0.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_8 = mux(_nestB_T_1, mshrs_1.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_9 = mux(_nestB_T_2, mshrs_2.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_10 = mux(_nestB_T_3, mshrs_3.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_11 = mux(_nestB_T_4, mshrs_4.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_12 = mux(_nestB_T_5, mshrs_5.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_13 = mux(_nestB_T_6, mshrs_6.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_14 = or(_nestB_T_7, _nestB_T_8) node _nestB_T_15 = or(_nestB_T_14, _nestB_T_9) node _nestB_T_16 = or(_nestB_T_15, _nestB_T_10) node _nestB_T_17 = or(_nestB_T_16, _nestB_T_11) node _nestB_T_18 = or(_nestB_T_17, _nestB_T_12) node _nestB_T_19 = or(_nestB_T_18, _nestB_T_13) wire _nestB_WIRE : UInt<1> connect _nestB_WIRE, _nestB_T_19 node nestB = and(_nestB_WIRE, request.bits.prio[1]) node _nestC_T = bits(setMatches, 0, 0) node _nestC_T_1 = bits(setMatches, 1, 1) node _nestC_T_2 = bits(setMatches, 2, 2) node _nestC_T_3 = bits(setMatches, 3, 3) node _nestC_T_4 = bits(setMatches, 4, 4) node _nestC_T_5 = bits(setMatches, 5, 5) node _nestC_T_6 = bits(setMatches, 6, 6) node _nestC_T_7 = mux(_nestC_T, mshrs_0.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_8 = mux(_nestC_T_1, mshrs_1.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_9 = mux(_nestC_T_2, mshrs_2.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_10 = mux(_nestC_T_3, mshrs_3.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_11 = mux(_nestC_T_4, mshrs_4.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_12 = mux(_nestC_T_5, mshrs_5.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_13 = mux(_nestC_T_6, mshrs_6.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_14 = or(_nestC_T_7, _nestC_T_8) node _nestC_T_15 = or(_nestC_T_14, _nestC_T_9) node _nestC_T_16 = or(_nestC_T_15, _nestC_T_10) node _nestC_T_17 = or(_nestC_T_16, _nestC_T_11) node _nestC_T_18 = or(_nestC_T_17, _nestC_T_12) node _nestC_T_19 = or(_nestC_T_18, _nestC_T_13) wire _nestC_WIRE : UInt<1> connect _nestC_WIRE, _nestC_T_19 node nestC = and(_nestC_WIRE, request.bits.prio[2]) node _prioFilter_T = eq(request.bits.prio[0], UInt<1>(0h0)) node _prioFilter_T_1 = not(UInt<5>(0h0)) node prioFilter_hi = cat(request.bits.prio[2], _prioFilter_T) node prioFilter = cat(prioFilter_hi, _prioFilter_T_1) node lowerMatches = and(setMatches, prioFilter) node _queue_T = orr(lowerMatches) node _queue_T_1 = eq(nestB, UInt<1>(0h0)) node _queue_T_2 = and(_queue_T, _queue_T_1) node _queue_T_3 = eq(nestC, UInt<1>(0h0)) node _queue_T_4 = and(_queue_T_2, _queue_T_3) node _queue_T_5 = eq(blockB, UInt<1>(0h0)) node _queue_T_6 = and(_queue_T_4, _queue_T_5) node _queue_T_7 = eq(blockC, UInt<1>(0h0)) node queue = and(_queue_T_6, _queue_T_7) node _T_5 = and(request.valid, blockC) node _T_6 = and(request.valid, nestC) node _T_7 = and(request.valid, queue) node _lowerMatches1_T = bits(lowerMatches, 6, 6) node _lowerMatches1_T_1 = shl(UInt<1>(0h1), 6) node _lowerMatches1_T_2 = bits(lowerMatches, 5, 5) node _lowerMatches1_T_3 = shl(UInt<1>(0h1), 5) node _lowerMatches1_T_4 = mux(_lowerMatches1_T_2, _lowerMatches1_T_3, lowerMatches) node lowerMatches1 = mux(_lowerMatches1_T, _lowerMatches1_T_1, _lowerMatches1_T_4) node selected_requests_hi = cat(mshr_selectOH, mshr_selectOH) node _selected_requests_T = cat(selected_requests_hi, mshr_selectOH) node selected_requests = and(_selected_requests_T, requests.io.valid) node _a_pop_T = bits(selected_requests, 6, 0) node a_pop = orr(_a_pop_T) node _b_pop_T = bits(selected_requests, 13, 7) node b_pop = orr(_b_pop_T) node _c_pop_T = bits(selected_requests, 20, 14) node c_pop = orr(_c_pop_T) node _bypassMatches_T = and(mshr_selectOH, lowerMatches1) node _bypassMatches_T_1 = orr(_bypassMatches_T) node _bypassMatches_T_2 = or(c_pop, request.bits.prio[2]) node _bypassMatches_T_3 = eq(c_pop, UInt<1>(0h0)) node _bypassMatches_T_4 = or(b_pop, request.bits.prio[1]) node _bypassMatches_T_5 = eq(b_pop, UInt<1>(0h0)) node _bypassMatches_T_6 = eq(a_pop, UInt<1>(0h0)) node _bypassMatches_T_7 = mux(_bypassMatches_T_4, _bypassMatches_T_5, _bypassMatches_T_6) node _bypassMatches_T_8 = mux(_bypassMatches_T_2, _bypassMatches_T_3, _bypassMatches_T_7) node bypassMatches = and(_bypassMatches_T_1, _bypassMatches_T_8) node _may_pop_T = or(a_pop, b_pop) node may_pop = or(_may_pop_T, c_pop) node _bypass_T = and(request.valid, queue) node bypass = and(_bypass_T, bypassMatches) node _will_reload_T = or(may_pop, bypass) node will_reload = and(schedule.reload, _will_reload_T) node _will_pop_T = and(schedule.reload, may_pop) node _will_pop_T_1 = eq(bypass, UInt<1>(0h0)) node will_pop = and(_will_pop_T, _will_pop_T_1) node _T_8 = orr(mshr_selectOH) node _T_9 = and(_T_8, bypass) node _T_10 = orr(mshr_selectOH) node _T_11 = and(_T_10, will_reload) node _T_12 = orr(mshr_selectOH) node _T_13 = and(_T_12, will_pop) node sel = bits(mshr_selectOH, 0, 0) connect mshrs_0.io.schedule.ready, sel node a_pop_1 = bits(requests.io.valid, 0, 0) node b_pop_1 = bits(requests.io.valid, 7, 7) node c_pop_1 = bits(requests.io.valid, 14, 14) node _bypassMatches_T_9 = bits(lowerMatches1, 0, 0) node _bypassMatches_T_10 = or(c_pop_1, request.bits.prio[2]) node _bypassMatches_T_11 = eq(c_pop_1, UInt<1>(0h0)) node _bypassMatches_T_12 = or(b_pop_1, request.bits.prio[1]) node _bypassMatches_T_13 = eq(b_pop_1, UInt<1>(0h0)) node _bypassMatches_T_14 = eq(a_pop_1, UInt<1>(0h0)) node _bypassMatches_T_15 = mux(_bypassMatches_T_12, _bypassMatches_T_13, _bypassMatches_T_14) node _bypassMatches_T_16 = mux(_bypassMatches_T_10, _bypassMatches_T_11, _bypassMatches_T_15) node bypassMatches_1 = and(_bypassMatches_T_9, _bypassMatches_T_16) node _may_pop_T_1 = or(a_pop_1, b_pop_1) node may_pop_1 = or(_may_pop_T_1, c_pop_1) node _bypass_T_1 = and(request.valid, queue) node bypass_1 = and(_bypass_T_1, bypassMatches_1) node _will_reload_T_1 = or(may_pop_1, bypass_1) node will_reload_1 = and(mshrs_0.io.schedule.bits.reload, _will_reload_T_1) wire _view__WIRE : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE.put, request.bits.put connect _view__WIRE.offset, request.bits.offset connect _view__WIRE.tag, request.bits.tag connect _view__WIRE.source, request.bits.source connect _view__WIRE.size, request.bits.size connect _view__WIRE.param, request.bits.param connect _view__WIRE.opcode, request.bits.opcode connect _view__WIRE.control, request.bits.control connect _view__WIRE.prio, request.bits.prio node _view__T = mux(bypass_1, _view__WIRE, requests.io.data) connect mshrs_0.io.allocate.bits.put, _view__T.put connect mshrs_0.io.allocate.bits.offset, _view__T.offset connect mshrs_0.io.allocate.bits.tag, _view__T.tag connect mshrs_0.io.allocate.bits.source, _view__T.source connect mshrs_0.io.allocate.bits.size, _view__T.size connect mshrs_0.io.allocate.bits.param, _view__T.param connect mshrs_0.io.allocate.bits.opcode, _view__T.opcode connect mshrs_0.io.allocate.bits.control, _view__T.control connect mshrs_0.io.allocate.bits.prio[0], _view__T.prio[0] connect mshrs_0.io.allocate.bits.prio[1], _view__T.prio[1] connect mshrs_0.io.allocate.bits.prio[2], _view__T.prio[2] connect mshrs_0.io.allocate.bits.set, mshrs_0.io.status.bits.set node _mshrs_0_io_allocate_bits_repeat_T = eq(mshrs_0.io.allocate.bits.tag, mshrs_0.io.status.bits.tag) connect mshrs_0.io.allocate.bits.repeat, _mshrs_0_io_allocate_bits_repeat_T node _mshrs_0_io_allocate_valid_T = and(sel, will_reload_1) connect mshrs_0.io.allocate.valid, _mshrs_0_io_allocate_valid_T node sel_1 = bits(mshr_selectOH, 1, 1) connect mshrs_1.io.schedule.ready, sel_1 node a_pop_2 = bits(requests.io.valid, 1, 1) node b_pop_2 = bits(requests.io.valid, 8, 8) node c_pop_2 = bits(requests.io.valid, 15, 15) node _bypassMatches_T_17 = bits(lowerMatches1, 1, 1) node _bypassMatches_T_18 = or(c_pop_2, request.bits.prio[2]) node _bypassMatches_T_19 = eq(c_pop_2, UInt<1>(0h0)) node _bypassMatches_T_20 = or(b_pop_2, request.bits.prio[1]) node _bypassMatches_T_21 = eq(b_pop_2, UInt<1>(0h0)) node _bypassMatches_T_22 = eq(a_pop_2, UInt<1>(0h0)) node _bypassMatches_T_23 = mux(_bypassMatches_T_20, _bypassMatches_T_21, _bypassMatches_T_22) node _bypassMatches_T_24 = mux(_bypassMatches_T_18, _bypassMatches_T_19, _bypassMatches_T_23) node bypassMatches_2 = and(_bypassMatches_T_17, _bypassMatches_T_24) node _may_pop_T_2 = or(a_pop_2, b_pop_2) node may_pop_2 = or(_may_pop_T_2, c_pop_2) node _bypass_T_2 = and(request.valid, queue) node bypass_2 = and(_bypass_T_2, bypassMatches_2) node _will_reload_T_2 = or(may_pop_2, bypass_2) node will_reload_2 = and(mshrs_1.io.schedule.bits.reload, _will_reload_T_2) wire _view__WIRE_1 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_1.put, request.bits.put connect _view__WIRE_1.offset, request.bits.offset connect _view__WIRE_1.tag, request.bits.tag connect _view__WIRE_1.source, request.bits.source connect _view__WIRE_1.size, request.bits.size connect _view__WIRE_1.param, request.bits.param connect _view__WIRE_1.opcode, request.bits.opcode connect _view__WIRE_1.control, request.bits.control connect _view__WIRE_1.prio, request.bits.prio node _view__T_1 = mux(bypass_2, _view__WIRE_1, requests.io.data) connect mshrs_1.io.allocate.bits.put, _view__T_1.put connect mshrs_1.io.allocate.bits.offset, _view__T_1.offset connect mshrs_1.io.allocate.bits.tag, _view__T_1.tag connect mshrs_1.io.allocate.bits.source, _view__T_1.source connect mshrs_1.io.allocate.bits.size, _view__T_1.size connect mshrs_1.io.allocate.bits.param, _view__T_1.param connect mshrs_1.io.allocate.bits.opcode, _view__T_1.opcode connect mshrs_1.io.allocate.bits.control, _view__T_1.control connect mshrs_1.io.allocate.bits.prio[0], _view__T_1.prio[0] connect mshrs_1.io.allocate.bits.prio[1], _view__T_1.prio[1] connect mshrs_1.io.allocate.bits.prio[2], _view__T_1.prio[2] connect mshrs_1.io.allocate.bits.set, mshrs_1.io.status.bits.set node _mshrs_1_io_allocate_bits_repeat_T = eq(mshrs_1.io.allocate.bits.tag, mshrs_1.io.status.bits.tag) connect mshrs_1.io.allocate.bits.repeat, _mshrs_1_io_allocate_bits_repeat_T node _mshrs_1_io_allocate_valid_T = and(sel_1, will_reload_2) connect mshrs_1.io.allocate.valid, _mshrs_1_io_allocate_valid_T node sel_2 = bits(mshr_selectOH, 2, 2) connect mshrs_2.io.schedule.ready, sel_2 node a_pop_3 = bits(requests.io.valid, 2, 2) node b_pop_3 = bits(requests.io.valid, 9, 9) node c_pop_3 = bits(requests.io.valid, 16, 16) node _bypassMatches_T_25 = bits(lowerMatches1, 2, 2) node _bypassMatches_T_26 = or(c_pop_3, request.bits.prio[2]) node _bypassMatches_T_27 = eq(c_pop_3, UInt<1>(0h0)) node _bypassMatches_T_28 = or(b_pop_3, request.bits.prio[1]) node _bypassMatches_T_29 = eq(b_pop_3, UInt<1>(0h0)) node _bypassMatches_T_30 = eq(a_pop_3, UInt<1>(0h0)) node _bypassMatches_T_31 = mux(_bypassMatches_T_28, _bypassMatches_T_29, _bypassMatches_T_30) node _bypassMatches_T_32 = mux(_bypassMatches_T_26, _bypassMatches_T_27, _bypassMatches_T_31) node bypassMatches_3 = and(_bypassMatches_T_25, _bypassMatches_T_32) node _may_pop_T_3 = or(a_pop_3, b_pop_3) node may_pop_3 = or(_may_pop_T_3, c_pop_3) node _bypass_T_3 = and(request.valid, queue) node bypass_3 = and(_bypass_T_3, bypassMatches_3) node _will_reload_T_3 = or(may_pop_3, bypass_3) node will_reload_3 = and(mshrs_2.io.schedule.bits.reload, _will_reload_T_3) wire _view__WIRE_2 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_2.put, request.bits.put connect _view__WIRE_2.offset, request.bits.offset connect _view__WIRE_2.tag, request.bits.tag connect _view__WIRE_2.source, request.bits.source connect _view__WIRE_2.size, request.bits.size connect _view__WIRE_2.param, request.bits.param connect _view__WIRE_2.opcode, request.bits.opcode connect _view__WIRE_2.control, request.bits.control connect _view__WIRE_2.prio, request.bits.prio node _view__T_2 = mux(bypass_3, _view__WIRE_2, requests.io.data) connect mshrs_2.io.allocate.bits.put, _view__T_2.put connect mshrs_2.io.allocate.bits.offset, _view__T_2.offset connect mshrs_2.io.allocate.bits.tag, _view__T_2.tag connect mshrs_2.io.allocate.bits.source, _view__T_2.source connect mshrs_2.io.allocate.bits.size, _view__T_2.size connect mshrs_2.io.allocate.bits.param, _view__T_2.param connect mshrs_2.io.allocate.bits.opcode, _view__T_2.opcode connect mshrs_2.io.allocate.bits.control, _view__T_2.control connect mshrs_2.io.allocate.bits.prio[0], _view__T_2.prio[0] connect mshrs_2.io.allocate.bits.prio[1], _view__T_2.prio[1] connect mshrs_2.io.allocate.bits.prio[2], _view__T_2.prio[2] connect mshrs_2.io.allocate.bits.set, mshrs_2.io.status.bits.set node _mshrs_2_io_allocate_bits_repeat_T = eq(mshrs_2.io.allocate.bits.tag, mshrs_2.io.status.bits.tag) connect mshrs_2.io.allocate.bits.repeat, _mshrs_2_io_allocate_bits_repeat_T node _mshrs_2_io_allocate_valid_T = and(sel_2, will_reload_3) connect mshrs_2.io.allocate.valid, _mshrs_2_io_allocate_valid_T node sel_3 = bits(mshr_selectOH, 3, 3) connect mshrs_3.io.schedule.ready, sel_3 node a_pop_4 = bits(requests.io.valid, 3, 3) node b_pop_4 = bits(requests.io.valid, 10, 10) node c_pop_4 = bits(requests.io.valid, 17, 17) node _bypassMatches_T_33 = bits(lowerMatches1, 3, 3) node _bypassMatches_T_34 = or(c_pop_4, request.bits.prio[2]) node _bypassMatches_T_35 = eq(c_pop_4, UInt<1>(0h0)) node _bypassMatches_T_36 = or(b_pop_4, request.bits.prio[1]) node _bypassMatches_T_37 = eq(b_pop_4, UInt<1>(0h0)) node _bypassMatches_T_38 = eq(a_pop_4, UInt<1>(0h0)) node _bypassMatches_T_39 = mux(_bypassMatches_T_36, _bypassMatches_T_37, _bypassMatches_T_38) node _bypassMatches_T_40 = mux(_bypassMatches_T_34, _bypassMatches_T_35, _bypassMatches_T_39) node bypassMatches_4 = and(_bypassMatches_T_33, _bypassMatches_T_40) node _may_pop_T_4 = or(a_pop_4, b_pop_4) node may_pop_4 = or(_may_pop_T_4, c_pop_4) node _bypass_T_4 = and(request.valid, queue) node bypass_4 = and(_bypass_T_4, bypassMatches_4) node _will_reload_T_4 = or(may_pop_4, bypass_4) node will_reload_4 = and(mshrs_3.io.schedule.bits.reload, _will_reload_T_4) wire _view__WIRE_3 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_3.put, request.bits.put connect _view__WIRE_3.offset, request.bits.offset connect _view__WIRE_3.tag, request.bits.tag connect _view__WIRE_3.source, request.bits.source connect _view__WIRE_3.size, request.bits.size connect _view__WIRE_3.param, request.bits.param connect _view__WIRE_3.opcode, request.bits.opcode connect _view__WIRE_3.control, request.bits.control connect _view__WIRE_3.prio, request.bits.prio node _view__T_3 = mux(bypass_4, _view__WIRE_3, requests.io.data) connect mshrs_3.io.allocate.bits.put, _view__T_3.put connect mshrs_3.io.allocate.bits.offset, _view__T_3.offset connect mshrs_3.io.allocate.bits.tag, _view__T_3.tag connect mshrs_3.io.allocate.bits.source, _view__T_3.source connect mshrs_3.io.allocate.bits.size, _view__T_3.size connect mshrs_3.io.allocate.bits.param, _view__T_3.param connect mshrs_3.io.allocate.bits.opcode, _view__T_3.opcode connect mshrs_3.io.allocate.bits.control, _view__T_3.control connect mshrs_3.io.allocate.bits.prio[0], _view__T_3.prio[0] connect mshrs_3.io.allocate.bits.prio[1], _view__T_3.prio[1] connect mshrs_3.io.allocate.bits.prio[2], _view__T_3.prio[2] connect mshrs_3.io.allocate.bits.set, mshrs_3.io.status.bits.set node _mshrs_3_io_allocate_bits_repeat_T = eq(mshrs_3.io.allocate.bits.tag, mshrs_3.io.status.bits.tag) connect mshrs_3.io.allocate.bits.repeat, _mshrs_3_io_allocate_bits_repeat_T node _mshrs_3_io_allocate_valid_T = and(sel_3, will_reload_4) connect mshrs_3.io.allocate.valid, _mshrs_3_io_allocate_valid_T node sel_4 = bits(mshr_selectOH, 4, 4) connect mshrs_4.io.schedule.ready, sel_4 node a_pop_5 = bits(requests.io.valid, 4, 4) node b_pop_5 = bits(requests.io.valid, 11, 11) node c_pop_5 = bits(requests.io.valid, 18, 18) node _bypassMatches_T_41 = bits(lowerMatches1, 4, 4) node _bypassMatches_T_42 = or(c_pop_5, request.bits.prio[2]) node _bypassMatches_T_43 = eq(c_pop_5, UInt<1>(0h0)) node _bypassMatches_T_44 = or(b_pop_5, request.bits.prio[1]) node _bypassMatches_T_45 = eq(b_pop_5, UInt<1>(0h0)) node _bypassMatches_T_46 = eq(a_pop_5, UInt<1>(0h0)) node _bypassMatches_T_47 = mux(_bypassMatches_T_44, _bypassMatches_T_45, _bypassMatches_T_46) node _bypassMatches_T_48 = mux(_bypassMatches_T_42, _bypassMatches_T_43, _bypassMatches_T_47) node bypassMatches_5 = and(_bypassMatches_T_41, _bypassMatches_T_48) node _may_pop_T_5 = or(a_pop_5, b_pop_5) node may_pop_5 = or(_may_pop_T_5, c_pop_5) node _bypass_T_5 = and(request.valid, queue) node bypass_5 = and(_bypass_T_5, bypassMatches_5) node _will_reload_T_5 = or(may_pop_5, bypass_5) node will_reload_5 = and(mshrs_4.io.schedule.bits.reload, _will_reload_T_5) wire _view__WIRE_4 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_4.put, request.bits.put connect _view__WIRE_4.offset, request.bits.offset connect _view__WIRE_4.tag, request.bits.tag connect _view__WIRE_4.source, request.bits.source connect _view__WIRE_4.size, request.bits.size connect _view__WIRE_4.param, request.bits.param connect _view__WIRE_4.opcode, request.bits.opcode connect _view__WIRE_4.control, request.bits.control connect _view__WIRE_4.prio, request.bits.prio node _view__T_4 = mux(bypass_5, _view__WIRE_4, requests.io.data) connect mshrs_4.io.allocate.bits.put, _view__T_4.put connect mshrs_4.io.allocate.bits.offset, _view__T_4.offset connect mshrs_4.io.allocate.bits.tag, _view__T_4.tag connect mshrs_4.io.allocate.bits.source, _view__T_4.source connect mshrs_4.io.allocate.bits.size, _view__T_4.size connect mshrs_4.io.allocate.bits.param, _view__T_4.param connect mshrs_4.io.allocate.bits.opcode, _view__T_4.opcode connect mshrs_4.io.allocate.bits.control, _view__T_4.control connect mshrs_4.io.allocate.bits.prio[0], _view__T_4.prio[0] connect mshrs_4.io.allocate.bits.prio[1], _view__T_4.prio[1] connect mshrs_4.io.allocate.bits.prio[2], _view__T_4.prio[2] connect mshrs_4.io.allocate.bits.set, mshrs_4.io.status.bits.set node _mshrs_4_io_allocate_bits_repeat_T = eq(mshrs_4.io.allocate.bits.tag, mshrs_4.io.status.bits.tag) connect mshrs_4.io.allocate.bits.repeat, _mshrs_4_io_allocate_bits_repeat_T node _mshrs_4_io_allocate_valid_T = and(sel_4, will_reload_5) connect mshrs_4.io.allocate.valid, _mshrs_4_io_allocate_valid_T node sel_5 = bits(mshr_selectOH, 5, 5) connect mshrs_5.io.schedule.ready, sel_5 node a_pop_6 = bits(requests.io.valid, 5, 5) node b_pop_6 = bits(requests.io.valid, 12, 12) node c_pop_6 = bits(requests.io.valid, 19, 19) node _bypassMatches_T_49 = bits(lowerMatches1, 5, 5) node _bypassMatches_T_50 = or(c_pop_6, request.bits.prio[2]) node _bypassMatches_T_51 = eq(c_pop_6, UInt<1>(0h0)) node _bypassMatches_T_52 = or(b_pop_6, request.bits.prio[1]) node _bypassMatches_T_53 = eq(b_pop_6, UInt<1>(0h0)) node _bypassMatches_T_54 = eq(a_pop_6, UInt<1>(0h0)) node _bypassMatches_T_55 = mux(_bypassMatches_T_52, _bypassMatches_T_53, _bypassMatches_T_54) node _bypassMatches_T_56 = mux(_bypassMatches_T_50, _bypassMatches_T_51, _bypassMatches_T_55) node bypassMatches_6 = and(_bypassMatches_T_49, _bypassMatches_T_56) node _may_pop_T_6 = or(a_pop_6, b_pop_6) node may_pop_6 = or(_may_pop_T_6, c_pop_6) node _bypass_T_6 = and(request.valid, queue) node bypass_6 = and(_bypass_T_6, bypassMatches_6) node _will_reload_T_6 = or(may_pop_6, bypass_6) node will_reload_6 = and(mshrs_5.io.schedule.bits.reload, _will_reload_T_6) wire _view__WIRE_5 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_5.put, request.bits.put connect _view__WIRE_5.offset, request.bits.offset connect _view__WIRE_5.tag, request.bits.tag connect _view__WIRE_5.source, request.bits.source connect _view__WIRE_5.size, request.bits.size connect _view__WIRE_5.param, request.bits.param connect _view__WIRE_5.opcode, request.bits.opcode connect _view__WIRE_5.control, request.bits.control connect _view__WIRE_5.prio, request.bits.prio node _view__T_5 = mux(bypass_6, _view__WIRE_5, requests.io.data) connect mshrs_5.io.allocate.bits.put, _view__T_5.put connect mshrs_5.io.allocate.bits.offset, _view__T_5.offset connect mshrs_5.io.allocate.bits.tag, _view__T_5.tag connect mshrs_5.io.allocate.bits.source, _view__T_5.source connect mshrs_5.io.allocate.bits.size, _view__T_5.size connect mshrs_5.io.allocate.bits.param, _view__T_5.param connect mshrs_5.io.allocate.bits.opcode, _view__T_5.opcode connect mshrs_5.io.allocate.bits.control, _view__T_5.control connect mshrs_5.io.allocate.bits.prio[0], _view__T_5.prio[0] connect mshrs_5.io.allocate.bits.prio[1], _view__T_5.prio[1] connect mshrs_5.io.allocate.bits.prio[2], _view__T_5.prio[2] connect mshrs_5.io.allocate.bits.set, mshrs_5.io.status.bits.set node _mshrs_5_io_allocate_bits_repeat_T = eq(mshrs_5.io.allocate.bits.tag, mshrs_5.io.status.bits.tag) connect mshrs_5.io.allocate.bits.repeat, _mshrs_5_io_allocate_bits_repeat_T node _mshrs_5_io_allocate_valid_T = and(sel_5, will_reload_6) connect mshrs_5.io.allocate.valid, _mshrs_5_io_allocate_valid_T node sel_6 = bits(mshr_selectOH, 6, 6) connect mshrs_6.io.schedule.ready, sel_6 node a_pop_7 = bits(requests.io.valid, 6, 6) node b_pop_7 = bits(requests.io.valid, 13, 13) node c_pop_7 = bits(requests.io.valid, 20, 20) node _bypassMatches_T_57 = bits(lowerMatches1, 6, 6) node _bypassMatches_T_58 = or(c_pop_7, request.bits.prio[2]) node _bypassMatches_T_59 = eq(c_pop_7, UInt<1>(0h0)) node _bypassMatches_T_60 = or(b_pop_7, request.bits.prio[1]) node _bypassMatches_T_61 = eq(b_pop_7, UInt<1>(0h0)) node _bypassMatches_T_62 = eq(a_pop_7, UInt<1>(0h0)) node _bypassMatches_T_63 = mux(_bypassMatches_T_60, _bypassMatches_T_61, _bypassMatches_T_62) node _bypassMatches_T_64 = mux(_bypassMatches_T_58, _bypassMatches_T_59, _bypassMatches_T_63) node bypassMatches_7 = and(_bypassMatches_T_57, _bypassMatches_T_64) node _may_pop_T_7 = or(a_pop_7, b_pop_7) node may_pop_7 = or(_may_pop_T_7, c_pop_7) node _bypass_T_7 = and(request.valid, queue) node bypass_7 = and(_bypass_T_7, bypassMatches_7) node _will_reload_T_7 = or(may_pop_7, bypass_7) node will_reload_7 = and(mshrs_6.io.schedule.bits.reload, _will_reload_T_7) wire _view__WIRE_6 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_6.put, request.bits.put connect _view__WIRE_6.offset, request.bits.offset connect _view__WIRE_6.tag, request.bits.tag connect _view__WIRE_6.source, request.bits.source connect _view__WIRE_6.size, request.bits.size connect _view__WIRE_6.param, request.bits.param connect _view__WIRE_6.opcode, request.bits.opcode connect _view__WIRE_6.control, request.bits.control connect _view__WIRE_6.prio, request.bits.prio node _view__T_6 = mux(bypass_7, _view__WIRE_6, requests.io.data) connect mshrs_6.io.allocate.bits.put, _view__T_6.put connect mshrs_6.io.allocate.bits.offset, _view__T_6.offset connect mshrs_6.io.allocate.bits.tag, _view__T_6.tag connect mshrs_6.io.allocate.bits.source, _view__T_6.source connect mshrs_6.io.allocate.bits.size, _view__T_6.size connect mshrs_6.io.allocate.bits.param, _view__T_6.param connect mshrs_6.io.allocate.bits.opcode, _view__T_6.opcode connect mshrs_6.io.allocate.bits.control, _view__T_6.control connect mshrs_6.io.allocate.bits.prio[0], _view__T_6.prio[0] connect mshrs_6.io.allocate.bits.prio[1], _view__T_6.prio[1] connect mshrs_6.io.allocate.bits.prio[2], _view__T_6.prio[2] connect mshrs_6.io.allocate.bits.set, mshrs_6.io.status.bits.set node _mshrs_6_io_allocate_bits_repeat_T = eq(mshrs_6.io.allocate.bits.tag, mshrs_6.io.status.bits.tag) connect mshrs_6.io.allocate.bits.repeat, _mshrs_6_io_allocate_bits_repeat_T node _mshrs_6_io_allocate_valid_T = and(sel_6, will_reload_7) connect mshrs_6.io.allocate.valid, _mshrs_6_io_allocate_valid_T node _prio_requests_T = not(requests.io.valid) node _prio_requests_T_1 = shr(requests.io.valid, 7) node _prio_requests_T_2 = or(_prio_requests_T, _prio_requests_T_1) node _prio_requests_T_3 = shr(requests.io.valid, 14) node _prio_requests_T_4 = or(_prio_requests_T_2, _prio_requests_T_3) node prio_requests = not(_prio_requests_T_4) node pop_index_hi = cat(mshr_selectOH, mshr_selectOH) node _pop_index_T = cat(pop_index_hi, mshr_selectOH) node _pop_index_T_1 = and(_pop_index_T, prio_requests) node pop_index_hi_1 = bits(_pop_index_T_1, 20, 16) node pop_index_lo = bits(_pop_index_T_1, 15, 0) node _pop_index_T_2 = orr(pop_index_hi_1) node _pop_index_T_3 = or(pop_index_hi_1, pop_index_lo) node pop_index_hi_2 = bits(_pop_index_T_3, 15, 8) node pop_index_lo_1 = bits(_pop_index_T_3, 7, 0) node _pop_index_T_4 = orr(pop_index_hi_2) node _pop_index_T_5 = or(pop_index_hi_2, pop_index_lo_1) node pop_index_hi_3 = bits(_pop_index_T_5, 7, 4) node pop_index_lo_2 = bits(_pop_index_T_5, 3, 0) node _pop_index_T_6 = orr(pop_index_hi_3) node _pop_index_T_7 = or(pop_index_hi_3, pop_index_lo_2) node pop_index_hi_4 = bits(_pop_index_T_7, 3, 2) node pop_index_lo_3 = bits(_pop_index_T_7, 1, 0) node _pop_index_T_8 = orr(pop_index_hi_4) node _pop_index_T_9 = or(pop_index_hi_4, pop_index_lo_3) node _pop_index_T_10 = bits(_pop_index_T_9, 1, 1) node _pop_index_T_11 = cat(_pop_index_T_8, _pop_index_T_10) node _pop_index_T_12 = cat(_pop_index_T_6, _pop_index_T_11) node _pop_index_T_13 = cat(_pop_index_T_4, _pop_index_T_12) node pop_index = cat(_pop_index_T_2, _pop_index_T_13) connect requests.io.pop.valid, will_pop connect requests.io.pop.bits, pop_index node lb_tag_mismatch = neq(scheduleTag, requests.io.data.tag) node _mshr_uses_directory_assuming_no_bypass_T = and(schedule.reload, may_pop) node mshr_uses_directory_assuming_no_bypass = and(_mshr_uses_directory_assuming_no_bypass_T, lb_tag_mismatch) node mshr_uses_directory_for_lb = and(will_pop, lb_tag_mismatch) node _mshr_uses_directory_T = mux(bypass, request.bits.tag, requests.io.data.tag) node _mshr_uses_directory_T_1 = neq(scheduleTag, _mshr_uses_directory_T) node mshr_uses_directory = and(will_reload, _mshr_uses_directory_T_1) node mshr_validOH_lo_hi = cat(mshrs_2.io.status.valid, mshrs_1.io.status.valid) node mshr_validOH_lo = cat(mshr_validOH_lo_hi, mshrs_0.io.status.valid) node mshr_validOH_hi_lo = cat(mshrs_4.io.status.valid, mshrs_3.io.status.valid) node mshr_validOH_hi_hi = cat(mshrs_6.io.status.valid, mshrs_5.io.status.valid) node mshr_validOH_hi = cat(mshr_validOH_hi_hi, mshr_validOH_hi_lo) node mshr_validOH = cat(mshr_validOH_hi, mshr_validOH_lo) node _mshr_free_T = not(mshr_validOH) node _mshr_free_T_1 = and(_mshr_free_T, prioFilter) node mshr_free = orr(_mshr_free_T_1) node bypassQueue = and(schedule.reload, bypassMatches) node _request_alloc_cases_T = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _request_alloc_cases_T_1 = and(alloc, _request_alloc_cases_T) node _request_alloc_cases_T_2 = and(_request_alloc_cases_T_1, mshr_free) node _request_alloc_cases_T_3 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _request_alloc_cases_T_4 = and(nestB, _request_alloc_cases_T_3) node _request_alloc_cases_T_5 = eq(mshrs_5.io.status.valid, UInt<1>(0h0)) node _request_alloc_cases_T_6 = and(_request_alloc_cases_T_4, _request_alloc_cases_T_5) node _request_alloc_cases_T_7 = eq(mshrs_6.io.status.valid, UInt<1>(0h0)) node _request_alloc_cases_T_8 = and(_request_alloc_cases_T_6, _request_alloc_cases_T_7) node _request_alloc_cases_T_9 = or(_request_alloc_cases_T_2, _request_alloc_cases_T_8) node _request_alloc_cases_T_10 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _request_alloc_cases_T_11 = and(nestC, _request_alloc_cases_T_10) node _request_alloc_cases_T_12 = eq(mshrs_6.io.status.valid, UInt<1>(0h0)) node _request_alloc_cases_T_13 = and(_request_alloc_cases_T_11, _request_alloc_cases_T_12) node request_alloc_cases = or(_request_alloc_cases_T_9, _request_alloc_cases_T_13) node _request_ready_T = or(bypassQueue, requests.io.push.ready) node _request_ready_T_1 = and(queue, _request_ready_T) node _request_ready_T_2 = or(request_alloc_cases, _request_ready_T_1) connect request.ready, _request_ready_T_2 node alloc_uses_directory = and(request.valid, request_alloc_cases) node _directory_io_read_valid_T = or(mshr_uses_directory, alloc_uses_directory) connect directory.io.read.valid, _directory_io_read_valid_T node _directory_io_read_bits_set_T = mux(mshr_uses_directory_for_lb, scheduleSet, request.bits.set) connect directory.io.read.bits.set, _directory_io_read_bits_set_T node _directory_io_read_bits_tag_T = mux(mshr_uses_directory_for_lb, requests.io.data.tag, request.bits.tag) connect directory.io.read.bits.tag, _directory_io_read_bits_tag_T node _requests_io_push_valid_T = and(request.valid, queue) node _requests_io_push_valid_T_1 = eq(bypassQueue, UInt<1>(0h0)) node _requests_io_push_valid_T_2 = and(_requests_io_push_valid_T, _requests_io_push_valid_T_1) connect requests.io.push.valid, _requests_io_push_valid_T_2 connect requests.io.push.bits.data.put, request.bits.put connect requests.io.push.bits.data.offset, request.bits.offset connect requests.io.push.bits.data.tag, request.bits.tag connect requests.io.push.bits.data.source, request.bits.source connect requests.io.push.bits.data.size, request.bits.size connect requests.io.push.bits.data.param, request.bits.param connect requests.io.push.bits.data.opcode, request.bits.opcode connect requests.io.push.bits.data.control, request.bits.control connect requests.io.push.bits.data.prio[0], request.bits.prio[0] connect requests.io.push.bits.data.prio[1], request.bits.prio[1] connect requests.io.push.bits.data.prio[2], request.bits.prio[2] node _requests_io_push_bits_index_T = shl(lowerMatches1, 0) node requests_io_push_bits_index_hi = bits(_requests_io_push_bits_index_T, 6, 4) node requests_io_push_bits_index_lo = bits(_requests_io_push_bits_index_T, 3, 0) node _requests_io_push_bits_index_T_1 = orr(requests_io_push_bits_index_hi) node _requests_io_push_bits_index_T_2 = or(requests_io_push_bits_index_hi, requests_io_push_bits_index_lo) node requests_io_push_bits_index_hi_1 = bits(_requests_io_push_bits_index_T_2, 3, 2) node requests_io_push_bits_index_lo_1 = bits(_requests_io_push_bits_index_T_2, 1, 0) node _requests_io_push_bits_index_T_3 = orr(requests_io_push_bits_index_hi_1) node _requests_io_push_bits_index_T_4 = or(requests_io_push_bits_index_hi_1, requests_io_push_bits_index_lo_1) node _requests_io_push_bits_index_T_5 = bits(_requests_io_push_bits_index_T_4, 1, 1) node _requests_io_push_bits_index_T_6 = cat(_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_5) node _requests_io_push_bits_index_T_7 = cat(_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_6) node _requests_io_push_bits_index_T_8 = shl(lowerMatches1, 7) node requests_io_push_bits_index_hi_2 = bits(_requests_io_push_bits_index_T_8, 13, 8) node requests_io_push_bits_index_lo_2 = bits(_requests_io_push_bits_index_T_8, 7, 0) node _requests_io_push_bits_index_T_9 = orr(requests_io_push_bits_index_hi_2) node _requests_io_push_bits_index_T_10 = or(requests_io_push_bits_index_hi_2, requests_io_push_bits_index_lo_2) node requests_io_push_bits_index_hi_3 = bits(_requests_io_push_bits_index_T_10, 7, 4) node requests_io_push_bits_index_lo_3 = bits(_requests_io_push_bits_index_T_10, 3, 0) node _requests_io_push_bits_index_T_11 = orr(requests_io_push_bits_index_hi_3) node _requests_io_push_bits_index_T_12 = or(requests_io_push_bits_index_hi_3, requests_io_push_bits_index_lo_3) node requests_io_push_bits_index_hi_4 = bits(_requests_io_push_bits_index_T_12, 3, 2) node requests_io_push_bits_index_lo_4 = bits(_requests_io_push_bits_index_T_12, 1, 0) node _requests_io_push_bits_index_T_13 = orr(requests_io_push_bits_index_hi_4) node _requests_io_push_bits_index_T_14 = or(requests_io_push_bits_index_hi_4, requests_io_push_bits_index_lo_4) node _requests_io_push_bits_index_T_15 = bits(_requests_io_push_bits_index_T_14, 1, 1) node _requests_io_push_bits_index_T_16 = cat(_requests_io_push_bits_index_T_13, _requests_io_push_bits_index_T_15) node _requests_io_push_bits_index_T_17 = cat(_requests_io_push_bits_index_T_11, _requests_io_push_bits_index_T_16) node _requests_io_push_bits_index_T_18 = cat(_requests_io_push_bits_index_T_9, _requests_io_push_bits_index_T_17) node _requests_io_push_bits_index_T_19 = shl(lowerMatches1, 14) node requests_io_push_bits_index_hi_5 = bits(_requests_io_push_bits_index_T_19, 20, 16) node requests_io_push_bits_index_lo_5 = bits(_requests_io_push_bits_index_T_19, 15, 0) node _requests_io_push_bits_index_T_20 = orr(requests_io_push_bits_index_hi_5) node _requests_io_push_bits_index_T_21 = or(requests_io_push_bits_index_hi_5, requests_io_push_bits_index_lo_5) node requests_io_push_bits_index_hi_6 = bits(_requests_io_push_bits_index_T_21, 15, 8) node requests_io_push_bits_index_lo_6 = bits(_requests_io_push_bits_index_T_21, 7, 0) node _requests_io_push_bits_index_T_22 = orr(requests_io_push_bits_index_hi_6) node _requests_io_push_bits_index_T_23 = or(requests_io_push_bits_index_hi_6, requests_io_push_bits_index_lo_6) node requests_io_push_bits_index_hi_7 = bits(_requests_io_push_bits_index_T_23, 7, 4) node requests_io_push_bits_index_lo_7 = bits(_requests_io_push_bits_index_T_23, 3, 0) node _requests_io_push_bits_index_T_24 = orr(requests_io_push_bits_index_hi_7) node _requests_io_push_bits_index_T_25 = or(requests_io_push_bits_index_hi_7, requests_io_push_bits_index_lo_7) node requests_io_push_bits_index_hi_8 = bits(_requests_io_push_bits_index_T_25, 3, 2) node requests_io_push_bits_index_lo_8 = bits(_requests_io_push_bits_index_T_25, 1, 0) node _requests_io_push_bits_index_T_26 = orr(requests_io_push_bits_index_hi_8) node _requests_io_push_bits_index_T_27 = or(requests_io_push_bits_index_hi_8, requests_io_push_bits_index_lo_8) node _requests_io_push_bits_index_T_28 = bits(_requests_io_push_bits_index_T_27, 1, 1) node _requests_io_push_bits_index_T_29 = cat(_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_28) node _requests_io_push_bits_index_T_30 = cat(_requests_io_push_bits_index_T_24, _requests_io_push_bits_index_T_29) node _requests_io_push_bits_index_T_31 = cat(_requests_io_push_bits_index_T_22, _requests_io_push_bits_index_T_30) node _requests_io_push_bits_index_T_32 = cat(_requests_io_push_bits_index_T_20, _requests_io_push_bits_index_T_31) node _requests_io_push_bits_index_T_33 = mux(request.bits.prio[0], _requests_io_push_bits_index_T_7, UInt<1>(0h0)) node _requests_io_push_bits_index_T_34 = mux(request.bits.prio[1], _requests_io_push_bits_index_T_18, UInt<1>(0h0)) node _requests_io_push_bits_index_T_35 = mux(request.bits.prio[2], _requests_io_push_bits_index_T_32, UInt<1>(0h0)) node _requests_io_push_bits_index_T_36 = or(_requests_io_push_bits_index_T_33, _requests_io_push_bits_index_T_34) node _requests_io_push_bits_index_T_37 = or(_requests_io_push_bits_index_T_36, _requests_io_push_bits_index_T_35) wire _requests_io_push_bits_index_WIRE : UInt<5> connect _requests_io_push_bits_index_WIRE, _requests_io_push_bits_index_T_37 connect requests.io.push.bits.index, _requests_io_push_bits_index_WIRE node _mshr_insertOH_T = not(mshr_validOH) node _mshr_insertOH_T_1 = shl(_mshr_insertOH_T, 1) node _mshr_insertOH_T_2 = bits(_mshr_insertOH_T_1, 6, 0) node _mshr_insertOH_T_3 = or(_mshr_insertOH_T, _mshr_insertOH_T_2) node _mshr_insertOH_T_4 = shl(_mshr_insertOH_T_3, 2) node _mshr_insertOH_T_5 = bits(_mshr_insertOH_T_4, 6, 0) node _mshr_insertOH_T_6 = or(_mshr_insertOH_T_3, _mshr_insertOH_T_5) node _mshr_insertOH_T_7 = shl(_mshr_insertOH_T_6, 4) node _mshr_insertOH_T_8 = bits(_mshr_insertOH_T_7, 6, 0) node _mshr_insertOH_T_9 = or(_mshr_insertOH_T_6, _mshr_insertOH_T_8) node _mshr_insertOH_T_10 = bits(_mshr_insertOH_T_9, 6, 0) node _mshr_insertOH_T_11 = shl(_mshr_insertOH_T_10, 1) node _mshr_insertOH_T_12 = not(_mshr_insertOH_T_11) node _mshr_insertOH_T_13 = not(mshr_validOH) node _mshr_insertOH_T_14 = and(_mshr_insertOH_T_12, _mshr_insertOH_T_13) node mshr_insertOH = and(_mshr_insertOH_T_14, prioFilter) node _T_14 = bits(mshr_insertOH, 0, 0) node _T_15 = bits(mshr_insertOH, 1, 1) node _T_16 = bits(mshr_insertOH, 2, 2) node _T_17 = bits(mshr_insertOH, 3, 3) node _T_18 = bits(mshr_insertOH, 4, 4) node _T_19 = bits(mshr_insertOH, 5, 5) node _T_20 = bits(mshr_insertOH, 6, 6) node _T_21 = bits(mshr_insertOH, 7, 7) node _T_22 = and(request.valid, alloc) node _T_23 = and(_T_22, _T_14) node _T_24 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_25 = and(_T_23, _T_24) when _T_25 : connect mshrs_0.io.allocate.valid, UInt<1>(0h1) connect mshrs_0.io.allocate.bits.set, request.bits.set connect mshrs_0.io.allocate.bits.put, request.bits.put connect mshrs_0.io.allocate.bits.offset, request.bits.offset connect mshrs_0.io.allocate.bits.tag, request.bits.tag connect mshrs_0.io.allocate.bits.source, request.bits.source connect mshrs_0.io.allocate.bits.size, request.bits.size connect mshrs_0.io.allocate.bits.param, request.bits.param connect mshrs_0.io.allocate.bits.opcode, request.bits.opcode connect mshrs_0.io.allocate.bits.control, request.bits.control connect mshrs_0.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_0.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_0.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_0.io.allocate.bits.repeat, UInt<1>(0h0) node _T_26 = and(request.valid, alloc) node _T_27 = and(_T_26, _T_15) node _T_28 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_29 = and(_T_27, _T_28) when _T_29 : connect mshrs_1.io.allocate.valid, UInt<1>(0h1) connect mshrs_1.io.allocate.bits.set, request.bits.set connect mshrs_1.io.allocate.bits.put, request.bits.put connect mshrs_1.io.allocate.bits.offset, request.bits.offset connect mshrs_1.io.allocate.bits.tag, request.bits.tag connect mshrs_1.io.allocate.bits.source, request.bits.source connect mshrs_1.io.allocate.bits.size, request.bits.size connect mshrs_1.io.allocate.bits.param, request.bits.param connect mshrs_1.io.allocate.bits.opcode, request.bits.opcode connect mshrs_1.io.allocate.bits.control, request.bits.control connect mshrs_1.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_1.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_1.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_1.io.allocate.bits.repeat, UInt<1>(0h0) node _T_30 = and(request.valid, alloc) node _T_31 = and(_T_30, _T_16) node _T_32 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_33 = and(_T_31, _T_32) when _T_33 : connect mshrs_2.io.allocate.valid, UInt<1>(0h1) connect mshrs_2.io.allocate.bits.set, request.bits.set connect mshrs_2.io.allocate.bits.put, request.bits.put connect mshrs_2.io.allocate.bits.offset, request.bits.offset connect mshrs_2.io.allocate.bits.tag, request.bits.tag connect mshrs_2.io.allocate.bits.source, request.bits.source connect mshrs_2.io.allocate.bits.size, request.bits.size connect mshrs_2.io.allocate.bits.param, request.bits.param connect mshrs_2.io.allocate.bits.opcode, request.bits.opcode connect mshrs_2.io.allocate.bits.control, request.bits.control connect mshrs_2.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_2.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_2.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_2.io.allocate.bits.repeat, UInt<1>(0h0) node _T_34 = and(request.valid, alloc) node _T_35 = and(_T_34, _T_17) node _T_36 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_37 = and(_T_35, _T_36) when _T_37 : connect mshrs_3.io.allocate.valid, UInt<1>(0h1) connect mshrs_3.io.allocate.bits.set, request.bits.set connect mshrs_3.io.allocate.bits.put, request.bits.put connect mshrs_3.io.allocate.bits.offset, request.bits.offset connect mshrs_3.io.allocate.bits.tag, request.bits.tag connect mshrs_3.io.allocate.bits.source, request.bits.source connect mshrs_3.io.allocate.bits.size, request.bits.size connect mshrs_3.io.allocate.bits.param, request.bits.param connect mshrs_3.io.allocate.bits.opcode, request.bits.opcode connect mshrs_3.io.allocate.bits.control, request.bits.control connect mshrs_3.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_3.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_3.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_3.io.allocate.bits.repeat, UInt<1>(0h0) node _T_38 = and(request.valid, alloc) node _T_39 = and(_T_38, _T_18) node _T_40 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_41 = and(_T_39, _T_40) when _T_41 : connect mshrs_4.io.allocate.valid, UInt<1>(0h1) connect mshrs_4.io.allocate.bits.set, request.bits.set connect mshrs_4.io.allocate.bits.put, request.bits.put connect mshrs_4.io.allocate.bits.offset, request.bits.offset connect mshrs_4.io.allocate.bits.tag, request.bits.tag connect mshrs_4.io.allocate.bits.source, request.bits.source connect mshrs_4.io.allocate.bits.size, request.bits.size connect mshrs_4.io.allocate.bits.param, request.bits.param connect mshrs_4.io.allocate.bits.opcode, request.bits.opcode connect mshrs_4.io.allocate.bits.control, request.bits.control connect mshrs_4.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_4.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_4.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_4.io.allocate.bits.repeat, UInt<1>(0h0) node _T_42 = and(request.valid, alloc) node _T_43 = and(_T_42, _T_19) node _T_44 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_45 = and(_T_43, _T_44) when _T_45 : connect mshrs_5.io.allocate.valid, UInt<1>(0h1) connect mshrs_5.io.allocate.bits.set, request.bits.set connect mshrs_5.io.allocate.bits.put, request.bits.put connect mshrs_5.io.allocate.bits.offset, request.bits.offset connect mshrs_5.io.allocate.bits.tag, request.bits.tag connect mshrs_5.io.allocate.bits.source, request.bits.source connect mshrs_5.io.allocate.bits.size, request.bits.size connect mshrs_5.io.allocate.bits.param, request.bits.param connect mshrs_5.io.allocate.bits.opcode, request.bits.opcode connect mshrs_5.io.allocate.bits.control, request.bits.control connect mshrs_5.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_5.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_5.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_5.io.allocate.bits.repeat, UInt<1>(0h0) node _T_46 = and(request.valid, alloc) node _T_47 = and(_T_46, _T_20) node _T_48 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_49 = and(_T_47, _T_48) when _T_49 : connect mshrs_6.io.allocate.valid, UInt<1>(0h1) connect mshrs_6.io.allocate.bits.set, request.bits.set connect mshrs_6.io.allocate.bits.put, request.bits.put connect mshrs_6.io.allocate.bits.offset, request.bits.offset connect mshrs_6.io.allocate.bits.tag, request.bits.tag connect mshrs_6.io.allocate.bits.source, request.bits.source connect mshrs_6.io.allocate.bits.size, request.bits.size connect mshrs_6.io.allocate.bits.param, request.bits.param connect mshrs_6.io.allocate.bits.opcode, request.bits.opcode connect mshrs_6.io.allocate.bits.control, request.bits.control connect mshrs_6.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_6.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_6.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_6.io.allocate.bits.repeat, UInt<1>(0h0) node _T_50 = and(request.valid, nestB) node _T_51 = eq(mshrs_5.io.status.valid, UInt<1>(0h0)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(mshrs_6.io.status.valid, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) node _T_55 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_56 = and(_T_54, _T_55) when _T_56 : connect mshrs_5.io.allocate.valid, UInt<1>(0h1) connect mshrs_5.io.allocate.bits.set, request.bits.set connect mshrs_5.io.allocate.bits.put, request.bits.put connect mshrs_5.io.allocate.bits.offset, request.bits.offset connect mshrs_5.io.allocate.bits.tag, request.bits.tag connect mshrs_5.io.allocate.bits.source, request.bits.source connect mshrs_5.io.allocate.bits.size, request.bits.size connect mshrs_5.io.allocate.bits.param, request.bits.param connect mshrs_5.io.allocate.bits.opcode, request.bits.opcode connect mshrs_5.io.allocate.bits.control, request.bits.control connect mshrs_5.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_5.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_5.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_5.io.allocate.bits.repeat, UInt<1>(0h0) node _T_57 = eq(request.bits.prio[0], UInt<1>(0h0)) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:291 assert (!request.bits.prio(0))\n") : printf assert(clock, _T_57, UInt<1>(0h1), "") : assert connect mshrs_5.io.allocate.bits.prio[0], UInt<1>(0h0) node _T_61 = and(request.valid, nestC) node _T_62 = eq(mshrs_6.io.status.valid, UInt<1>(0h0)) node _T_63 = and(_T_61, _T_62) node _T_64 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_65 = and(_T_63, _T_64) when _T_65 : connect mshrs_6.io.allocate.valid, UInt<1>(0h1) connect mshrs_6.io.allocate.bits.set, request.bits.set connect mshrs_6.io.allocate.bits.put, request.bits.put connect mshrs_6.io.allocate.bits.offset, request.bits.offset connect mshrs_6.io.allocate.bits.tag, request.bits.tag connect mshrs_6.io.allocate.bits.source, request.bits.source connect mshrs_6.io.allocate.bits.size, request.bits.size connect mshrs_6.io.allocate.bits.param, request.bits.param connect mshrs_6.io.allocate.bits.opcode, request.bits.opcode connect mshrs_6.io.allocate.bits.control, request.bits.control connect mshrs_6.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_6.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_6.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_6.io.allocate.bits.repeat, UInt<1>(0h0) node _T_66 = eq(request.bits.prio[0], UInt<1>(0h0)) node _T_67 = asUInt(reset) node _T_68 = eq(_T_67, UInt<1>(0h0)) when _T_68 : node _T_69 = eq(_T_66, UInt<1>(0h0)) when _T_69 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:299 assert (!request.bits.prio(0))\n") : printf_1 assert(clock, _T_66, UInt<1>(0h1), "") : assert_1 node _T_70 = eq(request.bits.prio[1], UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:300 assert (!request.bits.prio(1))\n") : printf_2 assert(clock, _T_70, UInt<1>(0h1), "") : assert_2 connect mshrs_6.io.allocate.bits.prio[0], UInt<1>(0h0) connect mshrs_6.io.allocate.bits.prio[1], UInt<1>(0h0) node _dirTarget_T = mux(nestB, UInt<6>(0h20), UInt<7>(0h40)) node dirTarget = mux(alloc, mshr_insertOH, _dirTarget_T) node _directoryFanout_T = mux(alloc_uses_directory, dirTarget, UInt<1>(0h0)) node _directoryFanout_T_1 = mux(mshr_uses_directory, mshr_selectOH, _directoryFanout_T) reg directoryFanout : UInt, clock connect directoryFanout, _directoryFanout_T_1 node _mshrs_0_io_directory_valid_T = bits(directoryFanout, 0, 0) connect mshrs_0.io.directory.valid, _mshrs_0_io_directory_valid_T connect mshrs_0.io.directory.bits.way, directory.io.result.bits.way connect mshrs_0.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_0.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_0.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_0.io.directory.bits.state, directory.io.result.bits.state connect mshrs_0.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_1_io_directory_valid_T = bits(directoryFanout, 1, 1) connect mshrs_1.io.directory.valid, _mshrs_1_io_directory_valid_T connect mshrs_1.io.directory.bits.way, directory.io.result.bits.way connect mshrs_1.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_1.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_1.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_1.io.directory.bits.state, directory.io.result.bits.state connect mshrs_1.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_2_io_directory_valid_T = bits(directoryFanout, 2, 2) connect mshrs_2.io.directory.valid, _mshrs_2_io_directory_valid_T connect mshrs_2.io.directory.bits.way, directory.io.result.bits.way connect mshrs_2.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_2.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_2.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_2.io.directory.bits.state, directory.io.result.bits.state connect mshrs_2.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_3_io_directory_valid_T = bits(directoryFanout, 3, 3) connect mshrs_3.io.directory.valid, _mshrs_3_io_directory_valid_T connect mshrs_3.io.directory.bits.way, directory.io.result.bits.way connect mshrs_3.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_3.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_3.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_3.io.directory.bits.state, directory.io.result.bits.state connect mshrs_3.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_4_io_directory_valid_T = bits(directoryFanout, 4, 4) connect mshrs_4.io.directory.valid, _mshrs_4_io_directory_valid_T connect mshrs_4.io.directory.bits.way, directory.io.result.bits.way connect mshrs_4.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_4.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_4.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_4.io.directory.bits.state, directory.io.result.bits.state connect mshrs_4.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_5_io_directory_valid_T = bits(directoryFanout, 5, 5) connect mshrs_5.io.directory.valid, _mshrs_5_io_directory_valid_T connect mshrs_5.io.directory.bits.way, directory.io.result.bits.way connect mshrs_5.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_5.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_5.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_5.io.directory.bits.state, directory.io.result.bits.state connect mshrs_5.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_6_io_directory_valid_T = bits(directoryFanout, 6, 6) connect mshrs_6.io.directory.valid, _mshrs_6_io_directory_valid_T connect mshrs_6.io.directory.bits.way, directory.io.result.bits.way connect mshrs_6.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_6.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_6.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_6.io.directory.bits.state, directory.io.result.bits.state connect mshrs_6.io.directory.bits.dirty, directory.io.result.bits.dirty node _sinkC_io_way_T = eq(mshrs_5.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_1 = and(mshrs_5.io.status.valid, _sinkC_io_way_T) node _sinkC_io_way_T_2 = eq(mshrs_0.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_3 = and(mshrs_0.io.status.valid, _sinkC_io_way_T_2) node _sinkC_io_way_T_4 = eq(mshrs_1.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_5 = and(mshrs_1.io.status.valid, _sinkC_io_way_T_4) node _sinkC_io_way_T_6 = eq(mshrs_2.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_7 = and(mshrs_2.io.status.valid, _sinkC_io_way_T_6) node _sinkC_io_way_T_8 = eq(mshrs_3.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_9 = and(mshrs_3.io.status.valid, _sinkC_io_way_T_8) node _sinkC_io_way_T_10 = eq(mshrs_4.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_11 = and(mshrs_4.io.status.valid, _sinkC_io_way_T_10) node _sinkC_io_way_T_12 = mux(_sinkC_io_way_T_3, mshrs_0.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_13 = mux(_sinkC_io_way_T_5, mshrs_1.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_14 = mux(_sinkC_io_way_T_7, mshrs_2.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_15 = mux(_sinkC_io_way_T_9, mshrs_3.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_16 = mux(_sinkC_io_way_T_11, mshrs_4.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_17 = or(_sinkC_io_way_T_12, _sinkC_io_way_T_13) node _sinkC_io_way_T_18 = or(_sinkC_io_way_T_17, _sinkC_io_way_T_14) node _sinkC_io_way_T_19 = or(_sinkC_io_way_T_18, _sinkC_io_way_T_15) node _sinkC_io_way_T_20 = or(_sinkC_io_way_T_19, _sinkC_io_way_T_16) wire _sinkC_io_way_WIRE : UInt<3> connect _sinkC_io_way_WIRE, _sinkC_io_way_T_20 node _sinkC_io_way_T_21 = mux(_sinkC_io_way_T_1, mshrs_5.io.status.bits.way, _sinkC_io_way_WIRE) connect sinkC.io.way, _sinkC_io_way_T_21 wire _sinkD_io_way_WIRE : UInt<3>[7] connect _sinkD_io_way_WIRE[0], mshrs_0.io.status.bits.way connect _sinkD_io_way_WIRE[1], mshrs_1.io.status.bits.way connect _sinkD_io_way_WIRE[2], mshrs_2.io.status.bits.way connect _sinkD_io_way_WIRE[3], mshrs_3.io.status.bits.way connect _sinkD_io_way_WIRE[4], mshrs_4.io.status.bits.way connect _sinkD_io_way_WIRE[5], mshrs_5.io.status.bits.way connect _sinkD_io_way_WIRE[6], mshrs_6.io.status.bits.way connect sinkD.io.way, _sinkD_io_way_WIRE[sinkD.io.source] wire _sinkD_io_set_WIRE : UInt<10>[7] connect _sinkD_io_set_WIRE[0], mshrs_0.io.status.bits.set connect _sinkD_io_set_WIRE[1], mshrs_1.io.status.bits.set connect _sinkD_io_set_WIRE[2], mshrs_2.io.status.bits.set connect _sinkD_io_set_WIRE[3], mshrs_3.io.status.bits.set connect _sinkD_io_set_WIRE[4], mshrs_4.io.status.bits.set connect _sinkD_io_set_WIRE[5], mshrs_5.io.status.bits.set connect _sinkD_io_set_WIRE[6], mshrs_6.io.status.bits.set connect sinkD.io.set, _sinkD_io_set_WIRE[sinkD.io.source] connect sinkA.io.pb_pop, sourceD.io.pb_pop connect sourceD.io.pb_beat.corrupt, sinkA.io.pb_beat.corrupt connect sourceD.io.pb_beat.mask, sinkA.io.pb_beat.mask connect sourceD.io.pb_beat.data, sinkA.io.pb_beat.data connect sinkC.io.rel_pop, sourceD.io.rel_pop connect sourceD.io.rel_beat.corrupt, sinkC.io.rel_beat.corrupt connect sourceD.io.rel_beat.data, sinkC.io.rel_beat.data connect bankedStore.io.sinkC_adr, sinkC.io.bs_adr connect bankedStore.io.sinkC_dat.data, sinkC.io.bs_dat.data connect bankedStore.io.sinkD_adr, sinkD.io.bs_adr connect bankedStore.io.sinkD_dat.data, sinkD.io.bs_dat.data connect bankedStore.io.sourceC_adr, sourceC.io.bs_adr connect bankedStore.io.sourceD_radr, sourceD.io.bs_radr connect bankedStore.io.sourceD_wadr, sourceD.io.bs_wadr connect bankedStore.io.sourceD_wdat.data, sourceD.io.bs_wdat.data connect sourceC.io.bs_dat.data, bankedStore.io.sourceC_dat.data connect sourceD.io.bs_rdat.data, bankedStore.io.sourceD_rdat.data connect sourceD.io.evict_req.way, sourceC.io.evict_req.way connect sourceD.io.evict_req.set, sourceC.io.evict_req.set connect sourceD.io.grant_req.way, sinkD.io.grant_req.way connect sourceD.io.grant_req.set, sinkD.io.grant_req.set connect sourceC.io.evict_safe, sourceD.io.evict_safe connect sinkD.io.grant_safe, sourceD.io.grant_safe
module InclusiveCacheBankScheduler( // @[Scheduler.scala:27:7] input clock, // @[Scheduler.scala:27:7] input reset, // @[Scheduler.scala:27:7] output io_in_a_ready, // @[Scheduler.scala:29:14] input io_in_a_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_opcode, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_size, // @[Scheduler.scala:29:14] input [5:0] io_in_a_bits_source, // @[Scheduler.scala:29:14] input [31:0] io_in_a_bits_address, // @[Scheduler.scala:29:14] input [7:0] io_in_a_bits_mask, // @[Scheduler.scala:29:14] input [63:0] io_in_a_bits_data, // @[Scheduler.scala:29:14] input io_in_a_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_b_ready, // @[Scheduler.scala:29:14] output io_in_b_valid, // @[Scheduler.scala:29:14] output [1:0] io_in_b_bits_param, // @[Scheduler.scala:29:14] output [31:0] io_in_b_bits_address, // @[Scheduler.scala:29:14] output io_in_c_ready, // @[Scheduler.scala:29:14] input io_in_c_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_opcode, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_size, // @[Scheduler.scala:29:14] input [5:0] io_in_c_bits_source, // @[Scheduler.scala:29:14] input [31:0] io_in_c_bits_address, // @[Scheduler.scala:29:14] input [63:0] io_in_c_bits_data, // @[Scheduler.scala:29:14] input io_in_c_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_d_ready, // @[Scheduler.scala:29:14] output io_in_d_valid, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_opcode, // @[Scheduler.scala:29:14] output [1:0] io_in_d_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_size, // @[Scheduler.scala:29:14] output [5:0] io_in_d_bits_source, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_sink, // @[Scheduler.scala:29:14] output io_in_d_bits_denied, // @[Scheduler.scala:29:14] output [63:0] io_in_d_bits_data, // @[Scheduler.scala:29:14] output io_in_d_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_e_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_e_bits_sink, // @[Scheduler.scala:29:14] input io_out_a_ready, // @[Scheduler.scala:29:14] output io_out_a_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_opcode, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_size, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_out_a_bits_address, // @[Scheduler.scala:29:14] output [7:0] io_out_a_bits_mask, // @[Scheduler.scala:29:14] output [63:0] io_out_a_bits_data, // @[Scheduler.scala:29:14] output io_out_a_bits_corrupt, // @[Scheduler.scala:29:14] input io_out_c_ready, // @[Scheduler.scala:29:14] output io_out_c_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_opcode, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_size, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_out_c_bits_address, // @[Scheduler.scala:29:14] output [63:0] io_out_c_bits_data, // @[Scheduler.scala:29:14] output io_out_c_bits_corrupt, // @[Scheduler.scala:29:14] output io_out_d_ready, // @[Scheduler.scala:29:14] input io_out_d_valid, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_opcode, // @[Scheduler.scala:29:14] input [1:0] io_out_d_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_size, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_source, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_sink, // @[Scheduler.scala:29:14] input io_out_d_bits_denied, // @[Scheduler.scala:29:14] input [63:0] io_out_d_bits_data, // @[Scheduler.scala:29:14] input io_out_d_bits_corrupt, // @[Scheduler.scala:29:14] output io_out_e_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_e_bits_sink, // @[Scheduler.scala:29:14] output io_req_ready, // @[Scheduler.scala:29:14] input io_req_valid, // @[Scheduler.scala:29:14] input [31:0] io_req_bits_address, // @[Scheduler.scala:29:14] output io_resp_valid // @[Scheduler.scala:29:14] ); wire [12:0] mshrs_6_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :295:103, :297:73] wire [12:0] mshrs_5_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :287:131, :289:74] wire [12:0] mshrs_4_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_3_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_2_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_1_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_0_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [5:0] request_bits_put; // @[Scheduler.scala:163:21] wire [5:0] request_bits_offset; // @[Scheduler.scala:163:21] wire [12:0] request_bits_tag; // @[Scheduler.scala:163:21] wire [5:0] request_bits_source; // @[Scheduler.scala:163:21] wire [2:0] request_bits_size; // @[Scheduler.scala:163:21] wire [2:0] request_bits_param; // @[Scheduler.scala:163:21] wire [2:0] request_bits_opcode; // @[Scheduler.scala:163:21] wire request_bits_control; // @[Scheduler.scala:163:21] wire request_bits_prio_2; // @[Scheduler.scala:163:21] wire request_bits_prio_0; // @[Scheduler.scala:163:21] wire _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_6_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_5_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_4_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_3_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_2_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_1_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_0_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _requests_io_push_ready; // @[Scheduler.scala:70:24] wire [20:0] _requests_io_valid; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_0; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_1; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_2; // @[Scheduler.scala:70:24] wire _requests_io_data_control; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_opcode; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_param; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_size; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_source; // @[Scheduler.scala:70:24] wire [12:0] _requests_io_data_tag; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_offset; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_put; // @[Scheduler.scala:70:24] wire _bankedStore_io_sinkC_adr_ready; // @[Scheduler.scala:69:27] wire _bankedStore_io_sinkD_adr_ready; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceC_adr_ready; // @[Scheduler.scala:69:27] wire [63:0] _bankedStore_io_sourceC_dat_data; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceD_radr_ready; // @[Scheduler.scala:69:27] wire [63:0] _bankedStore_io_sourceD_rdat_data; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceD_wadr_ready; // @[Scheduler.scala:69:27] wire _directory_io_write_ready; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_dirty; // @[Scheduler.scala:68:25] wire [1:0] _directory_io_result_bits_state; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_clients; // @[Scheduler.scala:68:25] wire [12:0] _directory_io_result_bits_tag; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_hit; // @[Scheduler.scala:68:25] wire [2:0] _directory_io_result_bits_way; // @[Scheduler.scala:68:25] wire _directory_io_ready; // @[Scheduler.scala:68:25] wire _sinkX_io_req_valid; // @[Scheduler.scala:58:21] wire [12:0] _sinkX_io_req_bits_tag; // @[Scheduler.scala:58:21] wire [9:0] _sinkX_io_req_bits_set; // @[Scheduler.scala:58:21] wire _sinkE_io_resp_valid; // @[Scheduler.scala:57:21] wire [2:0] _sinkE_io_resp_bits_sink; // @[Scheduler.scala:57:21] wire _sinkD_io_resp_valid; // @[Scheduler.scala:56:21] wire _sinkD_io_resp_bits_last; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_opcode; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_param; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_source; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_sink; // @[Scheduler.scala:56:21] wire _sinkD_io_resp_bits_denied; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_source; // @[Scheduler.scala:56:21] wire _sinkD_io_bs_adr_valid; // @[Scheduler.scala:56:21] wire _sinkD_io_bs_adr_bits_noop; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_bs_adr_bits_way; // @[Scheduler.scala:56:21] wire [9:0] _sinkD_io_bs_adr_bits_set; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_bs_adr_bits_beat; // @[Scheduler.scala:56:21] wire [63:0] _sinkD_io_bs_dat_data; // @[Scheduler.scala:56:21] wire [9:0] _sinkD_io_grant_req_set; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_grant_req_way; // @[Scheduler.scala:56:21] wire _sinkC_io_req_valid; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_opcode; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_param; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_size; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_source; // @[Scheduler.scala:55:21] wire [12:0] _sinkC_io_req_bits_tag; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_offset; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_put; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_req_bits_set; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_valid; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_bits_last; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_resp_bits_set; // @[Scheduler.scala:55:21] wire [12:0] _sinkC_io_resp_bits_tag; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_resp_bits_source; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_resp_bits_param; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_bits_data; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_set; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_valid; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_bits_noop; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_bs_adr_bits_way; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_bs_adr_bits_set; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_bs_adr_bits_beat; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_bits_mask; // @[Scheduler.scala:55:21] wire [63:0] _sinkC_io_bs_dat_data; // @[Scheduler.scala:55:21] wire _sinkC_io_rel_pop_ready; // @[Scheduler.scala:55:21] wire [63:0] _sinkC_io_rel_beat_data; // @[Scheduler.scala:55:21] wire _sinkC_io_rel_beat_corrupt; // @[Scheduler.scala:55:21] wire _sinkA_io_req_valid; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21] wire [12:0] _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21] wire [9:0] _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21] wire _sinkA_io_pb_pop_ready; // @[Scheduler.scala:54:21] wire [63:0] _sinkA_io_pb_beat_data; // @[Scheduler.scala:54:21] wire [7:0] _sinkA_io_pb_beat_mask; // @[Scheduler.scala:54:21] wire _sinkA_io_pb_beat_corrupt; // @[Scheduler.scala:54:21] wire _sourceX_io_req_ready; // @[Scheduler.scala:45:23] wire _sourceE_io_req_ready; // @[Scheduler.scala:44:23] wire _sourceD_io_req_ready; // @[Scheduler.scala:43:23] wire _sourceD_io_pb_pop_valid; // @[Scheduler.scala:43:23] wire [5:0] _sourceD_io_pb_pop_bits_index; // @[Scheduler.scala:43:23] wire _sourceD_io_pb_pop_bits_last; // @[Scheduler.scala:43:23] wire _sourceD_io_rel_pop_valid; // @[Scheduler.scala:43:23] wire [5:0] _sourceD_io_rel_pop_bits_index; // @[Scheduler.scala:43:23] wire _sourceD_io_rel_pop_bits_last; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_radr_valid; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_radr_bits_way; // @[Scheduler.scala:43:23] wire [9:0] _sourceD_io_bs_radr_bits_set; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_radr_bits_beat; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_radr_bits_mask; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_wadr_valid; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_wadr_bits_way; // @[Scheduler.scala:43:23] wire [9:0] _sourceD_io_bs_wadr_bits_set; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_wadr_bits_beat; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_wadr_bits_mask; // @[Scheduler.scala:43:23] wire [63:0] _sourceD_io_bs_wdat_data; // @[Scheduler.scala:43:23] wire _sourceD_io_evict_safe; // @[Scheduler.scala:43:23] wire _sourceD_io_grant_safe; // @[Scheduler.scala:43:23] wire _sourceC_io_req_ready; // @[Scheduler.scala:42:23] wire _sourceC_io_bs_adr_valid; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_bs_adr_bits_way; // @[Scheduler.scala:42:23] wire [9:0] _sourceC_io_bs_adr_bits_set; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_bs_adr_bits_beat; // @[Scheduler.scala:42:23] wire [9:0] _sourceC_io_evict_req_set; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_evict_req_way; // @[Scheduler.scala:42:23] wire _sourceB_io_req_ready; // @[Scheduler.scala:41:23] wire _sourceA_io_req_ready; // @[Scheduler.scala:40:23] wire io_in_a_valid_0 = io_in_a_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Scheduler.scala:27:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Scheduler.scala:27:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Scheduler.scala:27:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Scheduler.scala:27:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Scheduler.scala:27:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Scheduler.scala:27:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Scheduler.scala:27:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Scheduler.scala:27:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Scheduler.scala:27:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Scheduler.scala:27:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Scheduler.scala:27:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Scheduler.scala:27:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Scheduler.scala:27:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Scheduler.scala:27:7] wire io_out_a_ready_0 = io_out_a_ready; // @[Scheduler.scala:27:7] wire io_out_c_ready_0 = io_out_c_ready; // @[Scheduler.scala:27:7] wire io_out_d_valid_0 = io_out_d_valid; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_opcode_0 = io_out_d_bits_opcode; // @[Scheduler.scala:27:7] wire [1:0] io_out_d_bits_param_0 = io_out_d_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_size_0 = io_out_d_bits_size; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_source_0 = io_out_d_bits_source; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_sink_0 = io_out_d_bits_sink; // @[Scheduler.scala:27:7] wire io_out_d_bits_denied_0 = io_out_d_bits_denied; // @[Scheduler.scala:27:7] wire [63:0] io_out_d_bits_data_0 = io_out_d_bits_data; // @[Scheduler.scala:27:7] wire io_out_d_bits_corrupt_0 = io_out_d_bits_corrupt; // @[Scheduler.scala:27:7] wire io_req_valid_0 = io_req_valid; // @[Scheduler.scala:27:7] wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[Scheduler.scala:27:7] wire io_in_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7] wire io_out_b_valid = 1'h0; // @[Scheduler.scala:27:7] wire io_out_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7] wire io_resp_bits_fail = 1'h0; // @[Scheduler.scala:27:7] wire schedule_x_bits_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_11_bits_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_12_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_111 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_112 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_113 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_114 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_115 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_116 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_117 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_118 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_119 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_120 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_121 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_122 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_123 = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_13 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_324 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_325 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_338 = 1'h0; // @[Mux.scala:30:73] wire request_bits_prio_1 = 1'h0; // @[Scheduler.scala:163:21] wire _request_bits_T_prio_1 = 1'h0; // @[Scheduler.scala:166:22] wire _request_bits_T_prio_2 = 1'h0; // @[Scheduler.scala:166:22] wire _request_bits_T_1_prio_1 = 1'h0; // @[Scheduler.scala:165:22] wire blockB = 1'h0; // @[Scheduler.scala:175:70] wire nestB = 1'h0; // @[Scheduler.scala:179:70] wire _view__WIRE_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_1_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_2_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_3_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_4_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_5_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_6_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _request_alloc_cases_T_4 = 1'h0; // @[Scheduler.scala:259:13] wire _request_alloc_cases_T_6 = 1'h0; // @[Scheduler.scala:259:56] wire _request_alloc_cases_T_8 = 1'h0; // @[Scheduler.scala:259:84] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Scheduler.scala:27:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Scheduler.scala:27:7] wire [5:0] io_in_b_bits_source = 6'h10; // @[Scheduler.scala:27:7] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Scheduler.scala:27:7] wire [63:0] io_in_b_bits_data = 64'h0; // @[Scheduler.scala:27:7] wire [63:0] io_out_b_bits_data = 64'h0; // @[Scheduler.scala:27:7] wire io_in_e_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_out_b_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_out_e_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_resp_ready = 1'h1; // @[Scheduler.scala:27:7] wire _mshr_request_T_138 = 1'h1; // @[Scheduler.scala:107:28] wire _request_bits_T_prio_0 = 1'h1; // @[Scheduler.scala:166:22] wire _queue_T_1 = 1'h1; // @[Scheduler.scala:185:35] wire _queue_T_5 = 1'h1; // @[Scheduler.scala:185:55] wire [2:0] io_out_b_bits_opcode = 3'h0; // @[Scheduler.scala:27:7] wire [2:0] io_out_b_bits_size = 3'h0; // @[Scheduler.scala:27:7] wire [2:0] io_out_b_bits_source = 3'h0; // @[Scheduler.scala:27:7] wire [2:0] _schedule_WIRE_19_bits_sink = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_sink = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_189 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_190 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_191 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_192 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_193 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_194 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_195 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_196 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_197 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_198 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_199 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_200 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_201 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_23 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_423 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_424 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_425 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_426 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_427 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_428 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_429 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_430 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_431 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_432 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_433 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_434 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_435 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_44 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_55_bits_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_56_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_553 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_554 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_555 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_556 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_557 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_558 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_559 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_560 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_561 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_562 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_563 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_564 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_565 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_58 = 3'h0; // @[Mux.scala:30:73] wire [1:0] io_out_b_bits_param = 2'h0; // @[Scheduler.scala:27:7] wire [31:0] io_out_b_bits_address = 32'h0; // @[Scheduler.scala:27:7] wire [7:0] io_out_b_bits_mask = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_0 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_1 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_2 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_3 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_4 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_5 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_6 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_7 = 8'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_0 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_1 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_2 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_3 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_4 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_5 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_6 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_7 = 11'h0; // @[Scheduler.scala:27:7] wire [6:0] _lowerMatches1_T_1 = 7'h40; // @[Scheduler.scala:200:43] wire [6:0] _dirTarget_T = 7'h40; // @[Scheduler.scala:306:48] wire [3:0] _requests_io_push_bits_index_T_34 = 4'h0; // @[Mux.scala:30:73] wire [4:0] _prioFilter_T_1 = 5'h1F; // @[Scheduler.scala:182:69] wire [5:0] _lowerMatches1_T_3 = 6'h20; // @[Scheduler.scala:201:43] wire io_in_a_ready_0; // @[Scheduler.scala:27:7] wire [1:0] io_in_b_bits_param_0; // @[Scheduler.scala:27:7] wire [31:0] io_in_b_bits_address_0; // @[Scheduler.scala:27:7] wire io_in_b_valid_0; // @[Scheduler.scala:27:7] wire io_in_c_ready_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_opcode_0; // @[Scheduler.scala:27:7] wire [1:0] io_in_d_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_size_0; // @[Scheduler.scala:27:7] wire [5:0] io_in_d_bits_source_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_sink_0; // @[Scheduler.scala:27:7] wire io_in_d_bits_denied_0; // @[Scheduler.scala:27:7] wire [63:0] io_in_d_bits_data_0; // @[Scheduler.scala:27:7] wire io_in_d_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_in_d_valid_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_opcode_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_size_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_source_0; // @[Scheduler.scala:27:7] wire [31:0] io_out_a_bits_address_0; // @[Scheduler.scala:27:7] wire [7:0] io_out_a_bits_mask_0; // @[Scheduler.scala:27:7] wire [63:0] io_out_a_bits_data_0; // @[Scheduler.scala:27:7] wire io_out_a_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_out_a_valid_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_opcode_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_size_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_source_0; // @[Scheduler.scala:27:7] wire [31:0] io_out_c_bits_address_0; // @[Scheduler.scala:27:7] wire [63:0] io_out_c_bits_data_0; // @[Scheduler.scala:27:7] wire io_out_c_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_out_c_valid_0; // @[Scheduler.scala:27:7] wire io_out_d_ready_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_e_bits_sink_0; // @[Scheduler.scala:27:7] wire io_out_e_valid_0; // @[Scheduler.scala:27:7] wire io_req_ready_0; // @[Scheduler.scala:27:7] wire io_resp_valid_0; // @[Scheduler.scala:27:7] wire [9:0] _nestedwb_set_T; // @[Scheduler.scala:155:24] wire [12:0] _nestedwb_tag_T; // @[Scheduler.scala:156:24] wire _nestedwb_b_toN_T_2; // @[Scheduler.scala:157:75] wire _nestedwb_b_toB_T_2; // @[Scheduler.scala:158:75] wire _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:159:37] wire _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:160:75] wire [9:0] nestedwb_set; // @[Scheduler.scala:75:22] wire [12:0] nestedwb_tag; // @[Scheduler.scala:75:22] wire nestedwb_b_toN; // @[Scheduler.scala:75:22] wire nestedwb_b_toB; // @[Scheduler.scala:75:22] wire nestedwb_b_clr_dirty; // @[Scheduler.scala:75:22] wire nestedwb_c_set_dirty; // @[Scheduler.scala:75:22] wire _mshrs_0_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_0_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_0_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_0_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_0_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h0; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_0_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_0_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_0_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h0; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_0_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_0_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_1_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_1_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_1_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_1_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_1_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h1; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_1_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_1_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_1_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h1; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_1_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_1_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_2_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_2_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_2_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_2_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_2_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h2; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_2_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_2_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_2_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h2; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_2_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_2_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_3_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_3_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_3_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_3_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_3_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h3; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_3_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_3_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_3_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h3; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_3_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_3_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_4_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_4_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_4_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_4_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_4_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h4; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_4_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_4_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_4_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h4; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_4_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_4_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_5_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_5_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_5_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_5_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h5; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_5_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_5_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_5_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h5; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_5_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_5_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_6_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_6_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_6_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_6_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h6; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_6_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_6_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_6_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h6; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_6_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_6_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshr_stall_abc_T = _mshrs_0_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_1 = _mshrs_5_io_status_valid & _mshr_stall_abc_T; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_2 = _mshrs_0_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_3 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_2; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_0 = _mshr_stall_abc_T_1 | _mshr_stall_abc_T_3; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_4 = _mshrs_1_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_5 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_4; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_6 = _mshrs_1_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_7 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_6; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_1 = _mshr_stall_abc_T_5 | _mshr_stall_abc_T_7; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_8 = _mshrs_2_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_9 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_8; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_10 = _mshrs_2_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_11 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_10; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_2 = _mshr_stall_abc_T_9 | _mshr_stall_abc_T_11; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_12 = _mshrs_3_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_13 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_12; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_14 = _mshrs_3_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_15 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_14; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_3 = _mshr_stall_abc_T_13 | _mshr_stall_abc_T_15; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_16 = _mshrs_4_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_17 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_16; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_18 = _mshrs_4_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_19 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_18; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_4 = _mshr_stall_abc_T_17 | _mshr_stall_abc_T_19; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_bc_T = _mshrs_5_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :94:58] wire mshr_stall_bc = _mshrs_6_io_status_valid & _mshr_stall_bc_T; // @[Scheduler.scala:71:46, :94:{28,58}] wire stall_abc_0 = mshr_stall_abc_0 & _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_1 = mshr_stall_abc_1 & _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_2 = mshr_stall_abc_2 & _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_3 = mshr_stall_abc_3 & _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_4 = mshr_stall_abc_4 & _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire _mshr_request_T = ~mshr_stall_abc_0; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_1 = _mshrs_0_io_schedule_valid & _mshr_request_T; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_2 = ~_mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_3 = _sourceA_io_req_ready | _mshr_request_T_2; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_4 = _mshr_request_T_1 & _mshr_request_T_3; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_5 = ~_mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_6 = _sourceB_io_req_ready | _mshr_request_T_5; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_7 = _mshr_request_T_4 & _mshr_request_T_6; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_8 = ~_mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_9 = _sourceC_io_req_ready | _mshr_request_T_8; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_10 = _mshr_request_T_7 & _mshr_request_T_9; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_11 = ~_mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_12 = _sourceD_io_req_ready | _mshr_request_T_11; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_13 = _mshr_request_T_10 & _mshr_request_T_12; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_14 = ~_mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_15 = _sourceE_io_req_ready | _mshr_request_T_14; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_16 = _mshr_request_T_13 & _mshr_request_T_15; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_17 = ~_mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_18 = _sourceX_io_req_ready | _mshr_request_T_17; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_19 = _mshr_request_T_16 & _mshr_request_T_18; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_20 = ~_mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_21 = _directory_io_write_ready | _mshr_request_T_20; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_22 = _mshr_request_T_19 & _mshr_request_T_21; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_23 = ~mshr_stall_abc_1; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_24 = _mshrs_1_io_schedule_valid & _mshr_request_T_23; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_25 = ~_mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_26 = _sourceA_io_req_ready | _mshr_request_T_25; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_27 = _mshr_request_T_24 & _mshr_request_T_26; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_28 = ~_mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_29 = _sourceB_io_req_ready | _mshr_request_T_28; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_30 = _mshr_request_T_27 & _mshr_request_T_29; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_31 = ~_mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_32 = _sourceC_io_req_ready | _mshr_request_T_31; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_33 = _mshr_request_T_30 & _mshr_request_T_32; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_34 = ~_mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_35 = _sourceD_io_req_ready | _mshr_request_T_34; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_36 = _mshr_request_T_33 & _mshr_request_T_35; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_37 = ~_mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_38 = _sourceE_io_req_ready | _mshr_request_T_37; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_39 = _mshr_request_T_36 & _mshr_request_T_38; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_40 = ~_mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_41 = _sourceX_io_req_ready | _mshr_request_T_40; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_42 = _mshr_request_T_39 & _mshr_request_T_41; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_43 = ~_mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_44 = _directory_io_write_ready | _mshr_request_T_43; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_45 = _mshr_request_T_42 & _mshr_request_T_44; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_46 = ~mshr_stall_abc_2; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_47 = _mshrs_2_io_schedule_valid & _mshr_request_T_46; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_48 = ~_mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_49 = _sourceA_io_req_ready | _mshr_request_T_48; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_50 = _mshr_request_T_47 & _mshr_request_T_49; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_51 = ~_mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_52 = _sourceB_io_req_ready | _mshr_request_T_51; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_53 = _mshr_request_T_50 & _mshr_request_T_52; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_54 = ~_mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_55 = _sourceC_io_req_ready | _mshr_request_T_54; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_56 = _mshr_request_T_53 & _mshr_request_T_55; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_57 = ~_mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_58 = _sourceD_io_req_ready | _mshr_request_T_57; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_59 = _mshr_request_T_56 & _mshr_request_T_58; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_60 = ~_mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_61 = _sourceE_io_req_ready | _mshr_request_T_60; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_62 = _mshr_request_T_59 & _mshr_request_T_61; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_63 = ~_mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_64 = _sourceX_io_req_ready | _mshr_request_T_63; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_65 = _mshr_request_T_62 & _mshr_request_T_64; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_66 = ~_mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_67 = _directory_io_write_ready | _mshr_request_T_66; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_68 = _mshr_request_T_65 & _mshr_request_T_67; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_69 = ~mshr_stall_abc_3; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_70 = _mshrs_3_io_schedule_valid & _mshr_request_T_69; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_71 = ~_mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_72 = _sourceA_io_req_ready | _mshr_request_T_71; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_73 = _mshr_request_T_70 & _mshr_request_T_72; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_74 = ~_mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_75 = _sourceB_io_req_ready | _mshr_request_T_74; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_76 = _mshr_request_T_73 & _mshr_request_T_75; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_77 = ~_mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_78 = _sourceC_io_req_ready | _mshr_request_T_77; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_79 = _mshr_request_T_76 & _mshr_request_T_78; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_80 = ~_mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_81 = _sourceD_io_req_ready | _mshr_request_T_80; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_82 = _mshr_request_T_79 & _mshr_request_T_81; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_83 = ~_mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_84 = _sourceE_io_req_ready | _mshr_request_T_83; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_85 = _mshr_request_T_82 & _mshr_request_T_84; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_86 = ~_mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_87 = _sourceX_io_req_ready | _mshr_request_T_86; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_88 = _mshr_request_T_85 & _mshr_request_T_87; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_89 = ~_mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_90 = _directory_io_write_ready | _mshr_request_T_89; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_91 = _mshr_request_T_88 & _mshr_request_T_90; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_92 = ~mshr_stall_abc_4; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_93 = _mshrs_4_io_schedule_valid & _mshr_request_T_92; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_94 = ~_mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_95 = _sourceA_io_req_ready | _mshr_request_T_94; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_96 = _mshr_request_T_93 & _mshr_request_T_95; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_97 = ~_mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_98 = _sourceB_io_req_ready | _mshr_request_T_97; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_99 = _mshr_request_T_96 & _mshr_request_T_98; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_100 = ~_mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_101 = _sourceC_io_req_ready | _mshr_request_T_100; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_102 = _mshr_request_T_99 & _mshr_request_T_101; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_103 = ~_mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_104 = _sourceD_io_req_ready | _mshr_request_T_103; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_105 = _mshr_request_T_102 & _mshr_request_T_104; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_106 = ~_mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_107 = _sourceE_io_req_ready | _mshr_request_T_106; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_108 = _mshr_request_T_105 & _mshr_request_T_107; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_109 = ~_mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_110 = _sourceX_io_req_ready | _mshr_request_T_109; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_111 = _mshr_request_T_108 & _mshr_request_T_110; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_112 = ~_mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_113 = _directory_io_write_ready | _mshr_request_T_112; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_114 = _mshr_request_T_111 & _mshr_request_T_113; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_115 = ~mshr_stall_bc; // @[Scheduler.scala:94:28, :107:28] wire _mshr_request_T_116 = _mshrs_5_io_schedule_valid & _mshr_request_T_115; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_117 = ~_mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_118 = _sourceA_io_req_ready | _mshr_request_T_117; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_119 = _mshr_request_T_116 & _mshr_request_T_118; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_120 = ~_mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_121 = _sourceB_io_req_ready | _mshr_request_T_120; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_122 = _mshr_request_T_119 & _mshr_request_T_121; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_123 = ~_mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_124 = _sourceC_io_req_ready | _mshr_request_T_123; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_125 = _mshr_request_T_122 & _mshr_request_T_124; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_126 = ~_mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_127 = _sourceD_io_req_ready | _mshr_request_T_126; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_128 = _mshr_request_T_125 & _mshr_request_T_127; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_129 = ~_mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_130 = _sourceE_io_req_ready | _mshr_request_T_129; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_131 = _mshr_request_T_128 & _mshr_request_T_130; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_132 = ~_mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_133 = _sourceX_io_req_ready | _mshr_request_T_132; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_134 = _mshr_request_T_131 & _mshr_request_T_133; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_135 = ~_mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_136 = _directory_io_write_ready | _mshr_request_T_135; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_137 = _mshr_request_T_134 & _mshr_request_T_136; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_140 = ~_mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_141 = _sourceA_io_req_ready | _mshr_request_T_140; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_139; // @[Scheduler.scala:107:25] wire _mshr_request_T_142 = _mshr_request_T_139 & _mshr_request_T_141; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_143 = ~_mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_144 = _sourceB_io_req_ready | _mshr_request_T_143; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_145 = _mshr_request_T_142 & _mshr_request_T_144; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_146 = ~_mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_147 = _sourceC_io_req_ready | _mshr_request_T_146; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_148 = _mshr_request_T_145 & _mshr_request_T_147; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_149 = ~_mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_150 = _sourceD_io_req_ready | _mshr_request_T_149; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_151 = _mshr_request_T_148 & _mshr_request_T_150; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_152 = ~_mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_153 = _sourceE_io_req_ready | _mshr_request_T_152; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_154 = _mshr_request_T_151 & _mshr_request_T_153; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_155 = ~_mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_156 = _sourceX_io_req_ready | _mshr_request_T_155; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_157 = _mshr_request_T_154 & _mshr_request_T_156; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_158 = ~_mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_159 = _directory_io_write_ready | _mshr_request_T_158; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_160 = _mshr_request_T_157 & _mshr_request_T_159; // @[Scheduler.scala:112:61, :113:61, :114:33] wire [1:0] mshr_request_lo_hi = {_mshr_request_T_68, _mshr_request_T_45}; // @[Scheduler.scala:106:25, :113:61] wire [2:0] mshr_request_lo = {mshr_request_lo_hi, _mshr_request_T_22}; // @[Scheduler.scala:106:25, :113:61] wire [1:0] mshr_request_hi_lo = {_mshr_request_T_114, _mshr_request_T_91}; // @[Scheduler.scala:106:25, :113:61] wire [1:0] mshr_request_hi_hi = {_mshr_request_T_160, _mshr_request_T_137}; // @[Scheduler.scala:106:25, :113:61] wire [3:0] mshr_request_hi = {mshr_request_hi_hi, mshr_request_hi_lo}; // @[Scheduler.scala:106:25] wire [6:0] mshr_request = {mshr_request_hi, mshr_request_lo}; // @[Scheduler.scala:106:25] reg [6:0] robin_filter; // @[Scheduler.scala:118:29] wire [6:0] _robin_request_T = mshr_request & robin_filter; // @[Scheduler.scala:106:25, :118:29, :119:54] wire [13:0] robin_request = {mshr_request, _robin_request_T}; // @[Scheduler.scala:106:25, :119:{26,54}] wire [14:0] _mshr_selectOH2_T = {robin_request, 1'h0}; // @[package.scala:253:48] wire [13:0] _mshr_selectOH2_T_1 = _mshr_selectOH2_T[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_2 = robin_request | _mshr_selectOH2_T_1; // @[package.scala:253:{43,53}] wire [15:0] _mshr_selectOH2_T_3 = {_mshr_selectOH2_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [13:0] _mshr_selectOH2_T_4 = _mshr_selectOH2_T_3[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_5 = _mshr_selectOH2_T_2 | _mshr_selectOH2_T_4; // @[package.scala:253:{43,53}] wire [17:0] _mshr_selectOH2_T_6 = {_mshr_selectOH2_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [13:0] _mshr_selectOH2_T_7 = _mshr_selectOH2_T_6[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_8 = _mshr_selectOH2_T_5 | _mshr_selectOH2_T_7; // @[package.scala:253:{43,53}] wire [21:0] _mshr_selectOH2_T_9 = {_mshr_selectOH2_T_8, 8'h0}; // @[package.scala:253:{43,48}] wire [13:0] _mshr_selectOH2_T_10 = _mshr_selectOH2_T_9[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_11 = _mshr_selectOH2_T_8 | _mshr_selectOH2_T_10; // @[package.scala:253:{43,53}] wire [13:0] _mshr_selectOH2_T_12 = _mshr_selectOH2_T_11; // @[package.scala:253:43, :254:17] wire [14:0] _mshr_selectOH2_T_13 = {_mshr_selectOH2_T_12, 1'h0}; // @[package.scala:254:17] wire [14:0] _mshr_selectOH2_T_14 = ~_mshr_selectOH2_T_13; // @[Scheduler.scala:120:{24,48}] wire [14:0] mshr_selectOH2 = {1'h0, _mshr_selectOH2_T_14[13:0] & robin_request}; // @[Scheduler.scala:119:26, :120:{24,54}] wire [6:0] _mshr_selectOH_T = mshr_selectOH2[13:7]; // @[Scheduler.scala:120:54, :121:37] wire [6:0] _mshr_selectOH_T_1 = mshr_selectOH2[6:0]; // @[Scheduler.scala:120:54, :121:86] wire [6:0] mshr_selectOH = _mshr_selectOH_T | _mshr_selectOH_T_1; // @[Scheduler.scala:121:{37,70,86}] wire [2:0] mshr_select_hi = mshr_selectOH[6:4]; // @[OneHot.scala:30:18] wire [3:0] mshr_select_lo = mshr_selectOH[3:0]; // @[OneHot.scala:31:18] wire _mshr_select_T = |mshr_select_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _mshr_select_T_1 = {1'h0, mshr_select_hi} | mshr_select_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] mshr_select_hi_1 = _mshr_select_T_1[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] mshr_select_lo_1 = _mshr_select_T_1[1:0]; // @[OneHot.scala:31:18, :32:28] wire _mshr_select_T_2 = |mshr_select_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _mshr_select_T_3 = mshr_select_hi_1 | mshr_select_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _mshr_select_T_4 = _mshr_select_T_3[1]; // @[OneHot.scala:32:28] wire [1:0] _mshr_select_T_5 = {_mshr_select_T_2, _mshr_select_T_4}; // @[OneHot.scala:32:{10,14}] wire [2:0] mshr_select = {_mshr_select_T, _mshr_select_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] schedule_a_bits_source = mshr_select; // @[OneHot.scala:32:10] wire [2:0] schedule_d_bits_sink = mshr_select; // @[OneHot.scala:32:10] wire _schedule_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _scheduleTag_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _scheduleSet_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire sel = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _schedule_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _scheduleTag_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _scheduleSet_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire sel_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _schedule_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _scheduleTag_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _scheduleSet_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire sel_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _schedule_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _scheduleTag_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _scheduleSet_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire sel_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _schedule_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _scheduleTag_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _scheduleSet_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire sel_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _schedule_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _scheduleTag_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _scheduleSet_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire select_bc = mshr_selectOH[5]; // @[Mux.scala:32:36] wire sel_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _schedule_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _scheduleTag_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _scheduleSet_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire select_c = mshr_selectOH[6]; // @[Mux.scala:32:36] wire sel_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _schedule_WIRE_55_valid; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73] wire _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73] wire _schedule_WIRE_48_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73] wire _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73] wire _schedule_WIRE_38_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_c_bits_source_T_1; // @[Scheduler.scala:132:32] wire [12:0] _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73] wire _schedule_WIRE_19_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73] wire _schedule_WIRE_15_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73] wire _schedule_WIRE_11_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_1_valid; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73] wire _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73] wire _schedule_WIRE; // @[Mux.scala:30:73] wire [12:0] schedule_a_bits_tag; // @[Mux.scala:30:73] wire [9:0] schedule_a_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_a_bits_param; // @[Mux.scala:30:73] wire schedule_a_bits_block; // @[Mux.scala:30:73] wire schedule_a_valid; // @[Mux.scala:30:73] wire [2:0] schedule_b_bits_param; // @[Mux.scala:30:73] wire [12:0] schedule_b_bits_tag; // @[Mux.scala:30:73] wire [9:0] schedule_b_bits_set; // @[Mux.scala:30:73] wire schedule_b_bits_clients; // @[Mux.scala:30:73] wire schedule_b_valid; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_opcode; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_param; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_source; // @[Mux.scala:30:73] wire [12:0] schedule_c_bits_tag; // @[Mux.scala:30:73] wire [9:0] schedule_c_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_way; // @[Mux.scala:30:73] wire schedule_c_bits_dirty; // @[Mux.scala:30:73] wire schedule_c_valid; // @[Mux.scala:30:73] wire schedule_d_bits_prio_0; // @[Mux.scala:30:73] wire schedule_d_bits_prio_1; // @[Mux.scala:30:73] wire schedule_d_bits_prio_2; // @[Mux.scala:30:73] wire schedule_d_bits_control; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_opcode; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_param; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_size; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_source; // @[Mux.scala:30:73] wire [12:0] schedule_d_bits_tag; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_offset; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_put; // @[Mux.scala:30:73] wire [9:0] schedule_d_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_way; // @[Mux.scala:30:73] wire schedule_d_bits_bad; // @[Mux.scala:30:73] wire schedule_d_valid; // @[Mux.scala:30:73] wire [2:0] schedule_e_bits_sink; // @[Mux.scala:30:73] wire schedule_e_valid; // @[Mux.scala:30:73] wire schedule_x_valid; // @[Mux.scala:30:73] wire schedule_dir_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] schedule_dir_bits_data_state; // @[Mux.scala:30:73] wire schedule_dir_bits_data_clients; // @[Mux.scala:30:73] wire [12:0] schedule_dir_bits_data_tag; // @[Mux.scala:30:73] wire [9:0] schedule_dir_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_dir_bits_way; // @[Mux.scala:30:73] wire schedule_dir_valid; // @[Mux.scala:30:73] wire schedule_reload; // @[Mux.scala:30:73] wire _schedule_T_7 = _schedule_T & _mshrs_0_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_8 = _schedule_T_1 & _mshrs_1_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_9 = _schedule_T_2 & _mshrs_2_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_10 = _schedule_T_3 & _mshrs_3_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_11 = _schedule_T_4 & _mshrs_4_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_12 = _schedule_T_5 & _mshrs_5_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_13 = _schedule_T_6 & _mshrs_6_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_14 = _schedule_T_7 | _schedule_T_8; // @[Mux.scala:30:73] wire _schedule_T_15 = _schedule_T_14 | _schedule_T_9; // @[Mux.scala:30:73] wire _schedule_T_16 = _schedule_T_15 | _schedule_T_10; // @[Mux.scala:30:73] wire _schedule_T_17 = _schedule_T_16 | _schedule_T_11; // @[Mux.scala:30:73] wire _schedule_T_18 = _schedule_T_17 | _schedule_T_12; // @[Mux.scala:30:73] wire _schedule_T_19 = _schedule_T_18 | _schedule_T_13; // @[Mux.scala:30:73] assign _schedule_WIRE = _schedule_T_19; // @[Mux.scala:30:73] assign schedule_reload = _schedule_WIRE; // @[Mux.scala:30:73] wire _schedule_WIRE_10; // @[Mux.scala:30:73] assign schedule_dir_valid = _schedule_WIRE_1_valid; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_2_set; // @[Mux.scala:30:73] assign schedule_dir_bits_set = _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_2_way; // @[Mux.scala:30:73] assign schedule_dir_bits_way = _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73] assign schedule_dir_bits_data_dirty = _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_2_data_state; // @[Mux.scala:30:73] assign schedule_dir_bits_data_state = _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73] wire _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73] assign schedule_dir_bits_data_clients = _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73] assign schedule_dir_bits_data_tag = _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_9; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_set = _schedule_WIRE_2_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_8; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_way = _schedule_WIRE_2_way; // @[Mux.scala:30:73] wire _schedule_WIRE_3_dirty; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_dirty = _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_3_state; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_state = _schedule_WIRE_2_data_state; // @[Mux.scala:30:73] wire _schedule_WIRE_3_clients; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_clients = _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_3_tag; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_tag = _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73] wire _schedule_WIRE_7; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_dirty = _schedule_WIRE_3_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_6; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_state = _schedule_WIRE_3_state; // @[Mux.scala:30:73] wire _schedule_WIRE_5; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_clients = _schedule_WIRE_3_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_4; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_tag = _schedule_WIRE_3_tag; // @[Mux.scala:30:73] wire [12:0] _schedule_T_20 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_21 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_22 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_23 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_24 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_25 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_26 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_27 = _schedule_T_20 | _schedule_T_21; // @[Mux.scala:30:73] wire [12:0] _schedule_T_28 = _schedule_T_27 | _schedule_T_22; // @[Mux.scala:30:73] wire [12:0] _schedule_T_29 = _schedule_T_28 | _schedule_T_23; // @[Mux.scala:30:73] wire [12:0] _schedule_T_30 = _schedule_T_29 | _schedule_T_24; // @[Mux.scala:30:73] wire [12:0] _schedule_T_31 = _schedule_T_30 | _schedule_T_25; // @[Mux.scala:30:73] wire [12:0] _schedule_T_32 = _schedule_T_31 | _schedule_T_26; // @[Mux.scala:30:73] assign _schedule_WIRE_4 = _schedule_T_32; // @[Mux.scala:30:73] assign _schedule_WIRE_3_tag = _schedule_WIRE_4; // @[Mux.scala:30:73] wire _schedule_T_33 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_34 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_35 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_36 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_37 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_38 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_39 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_40 = _schedule_T_33 | _schedule_T_34; // @[Mux.scala:30:73] wire _schedule_T_41 = _schedule_T_40 | _schedule_T_35; // @[Mux.scala:30:73] wire _schedule_T_42 = _schedule_T_41 | _schedule_T_36; // @[Mux.scala:30:73] wire _schedule_T_43 = _schedule_T_42 | _schedule_T_37; // @[Mux.scala:30:73] wire _schedule_T_44 = _schedule_T_43 | _schedule_T_38; // @[Mux.scala:30:73] wire _schedule_T_45 = _schedule_T_44 | _schedule_T_39; // @[Mux.scala:30:73] assign _schedule_WIRE_5 = _schedule_T_45; // @[Mux.scala:30:73] assign _schedule_WIRE_3_clients = _schedule_WIRE_5; // @[Mux.scala:30:73] wire [1:0] _schedule_T_46 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_47 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_48 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_49 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_50 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_51 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_52 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_53 = _schedule_T_46 | _schedule_T_47; // @[Mux.scala:30:73] wire [1:0] _schedule_T_54 = _schedule_T_53 | _schedule_T_48; // @[Mux.scala:30:73] wire [1:0] _schedule_T_55 = _schedule_T_54 | _schedule_T_49; // @[Mux.scala:30:73] wire [1:0] _schedule_T_56 = _schedule_T_55 | _schedule_T_50; // @[Mux.scala:30:73] wire [1:0] _schedule_T_57 = _schedule_T_56 | _schedule_T_51; // @[Mux.scala:30:73] wire [1:0] _schedule_T_58 = _schedule_T_57 | _schedule_T_52; // @[Mux.scala:30:73] assign _schedule_WIRE_6 = _schedule_T_58; // @[Mux.scala:30:73] assign _schedule_WIRE_3_state = _schedule_WIRE_6; // @[Mux.scala:30:73] wire _schedule_T_59 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_60 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_61 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_62 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_63 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_64 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_65 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_66 = _schedule_T_59 | _schedule_T_60; // @[Mux.scala:30:73] wire _schedule_T_67 = _schedule_T_66 | _schedule_T_61; // @[Mux.scala:30:73] wire _schedule_T_68 = _schedule_T_67 | _schedule_T_62; // @[Mux.scala:30:73] wire _schedule_T_69 = _schedule_T_68 | _schedule_T_63; // @[Mux.scala:30:73] wire _schedule_T_70 = _schedule_T_69 | _schedule_T_64; // @[Mux.scala:30:73] wire _schedule_T_71 = _schedule_T_70 | _schedule_T_65; // @[Mux.scala:30:73] assign _schedule_WIRE_7 = _schedule_T_71; // @[Mux.scala:30:73] assign _schedule_WIRE_3_dirty = _schedule_WIRE_7; // @[Mux.scala:30:73] wire [2:0] _schedule_T_72 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_73 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_74 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_75 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_76 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_77 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_78 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_79 = _schedule_T_72 | _schedule_T_73; // @[Mux.scala:30:73] wire [2:0] _schedule_T_80 = _schedule_T_79 | _schedule_T_74; // @[Mux.scala:30:73] wire [2:0] _schedule_T_81 = _schedule_T_80 | _schedule_T_75; // @[Mux.scala:30:73] wire [2:0] _schedule_T_82 = _schedule_T_81 | _schedule_T_76; // @[Mux.scala:30:73] wire [2:0] _schedule_T_83 = _schedule_T_82 | _schedule_T_77; // @[Mux.scala:30:73] wire [2:0] _schedule_T_84 = _schedule_T_83 | _schedule_T_78; // @[Mux.scala:30:73] assign _schedule_WIRE_8 = _schedule_T_84; // @[Mux.scala:30:73] assign _schedule_WIRE_2_way = _schedule_WIRE_8; // @[Mux.scala:30:73] wire [9:0] _schedule_T_85 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_86 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_87 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_88 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_89 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_90 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_91 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_92 = _schedule_T_85 | _schedule_T_86; // @[Mux.scala:30:73] wire [9:0] _schedule_T_93 = _schedule_T_92 | _schedule_T_87; // @[Mux.scala:30:73] wire [9:0] _schedule_T_94 = _schedule_T_93 | _schedule_T_88; // @[Mux.scala:30:73] wire [9:0] _schedule_T_95 = _schedule_T_94 | _schedule_T_89; // @[Mux.scala:30:73] wire [9:0] _schedule_T_96 = _schedule_T_95 | _schedule_T_90; // @[Mux.scala:30:73] wire [9:0] _schedule_T_97 = _schedule_T_96 | _schedule_T_91; // @[Mux.scala:30:73] assign _schedule_WIRE_9 = _schedule_T_97; // @[Mux.scala:30:73] assign _schedule_WIRE_2_set = _schedule_WIRE_9; // @[Mux.scala:30:73] wire _schedule_T_98 = _schedule_T & _mshrs_0_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_99 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_100 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_101 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_102 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_103 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_104 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_105 = _schedule_T_98 | _schedule_T_99; // @[Mux.scala:30:73] wire _schedule_T_106 = _schedule_T_105 | _schedule_T_100; // @[Mux.scala:30:73] wire _schedule_T_107 = _schedule_T_106 | _schedule_T_101; // @[Mux.scala:30:73] wire _schedule_T_108 = _schedule_T_107 | _schedule_T_102; // @[Mux.scala:30:73] wire _schedule_T_109 = _schedule_T_108 | _schedule_T_103; // @[Mux.scala:30:73] wire _schedule_T_110 = _schedule_T_109 | _schedule_T_104; // @[Mux.scala:30:73] assign _schedule_WIRE_10 = _schedule_T_110; // @[Mux.scala:30:73] assign _schedule_WIRE_1_valid = _schedule_WIRE_10; // @[Mux.scala:30:73] wire _schedule_WIRE_14; // @[Mux.scala:30:73] assign schedule_x_valid = _schedule_WIRE_11_valid; // @[Mux.scala:30:73] wire _schedule_T_124 = _schedule_T & _mshrs_0_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_125 = _schedule_T_1 & _mshrs_1_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_126 = _schedule_T_2 & _mshrs_2_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_127 = _schedule_T_3 & _mshrs_3_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_128 = _schedule_T_4 & _mshrs_4_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_129 = _schedule_T_5 & _mshrs_5_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_130 = _schedule_T_6 & _mshrs_6_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_131 = _schedule_T_124 | _schedule_T_125; // @[Mux.scala:30:73] wire _schedule_T_132 = _schedule_T_131 | _schedule_T_126; // @[Mux.scala:30:73] wire _schedule_T_133 = _schedule_T_132 | _schedule_T_127; // @[Mux.scala:30:73] wire _schedule_T_134 = _schedule_T_133 | _schedule_T_128; // @[Mux.scala:30:73] wire _schedule_T_135 = _schedule_T_134 | _schedule_T_129; // @[Mux.scala:30:73] wire _schedule_T_136 = _schedule_T_135 | _schedule_T_130; // @[Mux.scala:30:73] assign _schedule_WIRE_14 = _schedule_T_136; // @[Mux.scala:30:73] assign _schedule_WIRE_11_valid = _schedule_WIRE_14; // @[Mux.scala:30:73] wire _schedule_WIRE_18; // @[Mux.scala:30:73] assign schedule_e_valid = _schedule_WIRE_15_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_16_sink; // @[Mux.scala:30:73] assign schedule_e_bits_sink = _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_17; // @[Mux.scala:30:73] assign _schedule_WIRE_15_bits_sink = _schedule_WIRE_16_sink; // @[Mux.scala:30:73] wire [2:0] _schedule_T_137 = _schedule_T ? _mshrs_0_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_138 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_139 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_140 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_141 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_142 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_143 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_144 = _schedule_T_137 | _schedule_T_138; // @[Mux.scala:30:73] wire [2:0] _schedule_T_145 = _schedule_T_144 | _schedule_T_139; // @[Mux.scala:30:73] wire [2:0] _schedule_T_146 = _schedule_T_145 | _schedule_T_140; // @[Mux.scala:30:73] wire [2:0] _schedule_T_147 = _schedule_T_146 | _schedule_T_141; // @[Mux.scala:30:73] wire [2:0] _schedule_T_148 = _schedule_T_147 | _schedule_T_142; // @[Mux.scala:30:73] wire [2:0] _schedule_T_149 = _schedule_T_148 | _schedule_T_143; // @[Mux.scala:30:73] assign _schedule_WIRE_17 = _schedule_T_149; // @[Mux.scala:30:73] assign _schedule_WIRE_16_sink = _schedule_WIRE_17; // @[Mux.scala:30:73] wire _schedule_T_150 = _schedule_T & _mshrs_0_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_151 = _schedule_T_1 & _mshrs_1_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_152 = _schedule_T_2 & _mshrs_2_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_153 = _schedule_T_3 & _mshrs_3_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_154 = _schedule_T_4 & _mshrs_4_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_155 = _schedule_T_5 & _mshrs_5_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_156 = _schedule_T_6 & _mshrs_6_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_157 = _schedule_T_150 | _schedule_T_151; // @[Mux.scala:30:73] wire _schedule_T_158 = _schedule_T_157 | _schedule_T_152; // @[Mux.scala:30:73] wire _schedule_T_159 = _schedule_T_158 | _schedule_T_153; // @[Mux.scala:30:73] wire _schedule_T_160 = _schedule_T_159 | _schedule_T_154; // @[Mux.scala:30:73] wire _schedule_T_161 = _schedule_T_160 | _schedule_T_155; // @[Mux.scala:30:73] wire _schedule_T_162 = _schedule_T_161 | _schedule_T_156; // @[Mux.scala:30:73] assign _schedule_WIRE_18 = _schedule_T_162; // @[Mux.scala:30:73] assign _schedule_WIRE_15_valid = _schedule_WIRE_18; // @[Mux.scala:30:73] wire _schedule_WIRE_37; // @[Mux.scala:30:73] assign schedule_d_valid = _schedule_WIRE_19_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73] assign schedule_d_bits_prio_0 = _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73] assign schedule_d_bits_prio_1 = _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73] assign schedule_d_bits_prio_2 = _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_20_control; // @[Mux.scala:30:73] assign schedule_d_bits_control = _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_opcode; // @[Mux.scala:30:73] assign schedule_d_bits_opcode = _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_param; // @[Mux.scala:30:73] assign schedule_d_bits_param = _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_size; // @[Mux.scala:30:73] assign schedule_d_bits_size = _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_source; // @[Mux.scala:30:73] assign schedule_d_bits_source = _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_20_tag; // @[Mux.scala:30:73] assign schedule_d_bits_tag = _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_offset; // @[Mux.scala:30:73] assign schedule_d_bits_offset = _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_put; // @[Mux.scala:30:73] assign schedule_d_bits_put = _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_20_set; // @[Mux.scala:30:73] assign schedule_d_bits_set = _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_way; // @[Mux.scala:30:73] assign schedule_d_bits_way = _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_20_bad; // @[Mux.scala:30:73] assign schedule_d_bits_bad = _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73] wire _schedule_WIRE_33_0; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_0 = _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_33_1; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_1 = _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_33_2; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_2 = _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_32; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_control = _schedule_WIRE_20_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_31; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_opcode = _schedule_WIRE_20_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_30; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_param = _schedule_WIRE_20_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_29; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_size = _schedule_WIRE_20_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_28; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_source = _schedule_WIRE_20_source; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_27; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_tag = _schedule_WIRE_20_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_26; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_offset = _schedule_WIRE_20_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_25; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_put = _schedule_WIRE_20_put; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_24; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_set = _schedule_WIRE_20_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_22; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_way = _schedule_WIRE_20_way; // @[Mux.scala:30:73] wire _schedule_WIRE_21; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_bad = _schedule_WIRE_20_bad; // @[Mux.scala:30:73] wire _schedule_T_163 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_164 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_165 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_166 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_167 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_168 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_169 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_170 = _schedule_T_163 | _schedule_T_164; // @[Mux.scala:30:73] wire _schedule_T_171 = _schedule_T_170 | _schedule_T_165; // @[Mux.scala:30:73] wire _schedule_T_172 = _schedule_T_171 | _schedule_T_166; // @[Mux.scala:30:73] wire _schedule_T_173 = _schedule_T_172 | _schedule_T_167; // @[Mux.scala:30:73] wire _schedule_T_174 = _schedule_T_173 | _schedule_T_168; // @[Mux.scala:30:73] wire _schedule_T_175 = _schedule_T_174 | _schedule_T_169; // @[Mux.scala:30:73] assign _schedule_WIRE_21 = _schedule_T_175; // @[Mux.scala:30:73] assign _schedule_WIRE_20_bad = _schedule_WIRE_21; // @[Mux.scala:30:73] wire [2:0] _schedule_T_176 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_177 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_178 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_179 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_180 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_181 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_182 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_183 = _schedule_T_176 | _schedule_T_177; // @[Mux.scala:30:73] wire [2:0] _schedule_T_184 = _schedule_T_183 | _schedule_T_178; // @[Mux.scala:30:73] wire [2:0] _schedule_T_185 = _schedule_T_184 | _schedule_T_179; // @[Mux.scala:30:73] wire [2:0] _schedule_T_186 = _schedule_T_185 | _schedule_T_180; // @[Mux.scala:30:73] wire [2:0] _schedule_T_187 = _schedule_T_186 | _schedule_T_181; // @[Mux.scala:30:73] wire [2:0] _schedule_T_188 = _schedule_T_187 | _schedule_T_182; // @[Mux.scala:30:73] assign _schedule_WIRE_22 = _schedule_T_188; // @[Mux.scala:30:73] assign _schedule_WIRE_20_way = _schedule_WIRE_22; // @[Mux.scala:30:73] wire [9:0] _schedule_T_202 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_203 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_204 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_205 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_206 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_207 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_208 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_209 = _schedule_T_202 | _schedule_T_203; // @[Mux.scala:30:73] wire [9:0] _schedule_T_210 = _schedule_T_209 | _schedule_T_204; // @[Mux.scala:30:73] wire [9:0] _schedule_T_211 = _schedule_T_210 | _schedule_T_205; // @[Mux.scala:30:73] wire [9:0] _schedule_T_212 = _schedule_T_211 | _schedule_T_206; // @[Mux.scala:30:73] wire [9:0] _schedule_T_213 = _schedule_T_212 | _schedule_T_207; // @[Mux.scala:30:73] wire [9:0] _schedule_T_214 = _schedule_T_213 | _schedule_T_208; // @[Mux.scala:30:73] assign _schedule_WIRE_24 = _schedule_T_214; // @[Mux.scala:30:73] assign _schedule_WIRE_20_set = _schedule_WIRE_24; // @[Mux.scala:30:73] wire [5:0] _schedule_T_215 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_216 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_217 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_218 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_219 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_220 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_221 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_222 = _schedule_T_215 | _schedule_T_216; // @[Mux.scala:30:73] wire [5:0] _schedule_T_223 = _schedule_T_222 | _schedule_T_217; // @[Mux.scala:30:73] wire [5:0] _schedule_T_224 = _schedule_T_223 | _schedule_T_218; // @[Mux.scala:30:73] wire [5:0] _schedule_T_225 = _schedule_T_224 | _schedule_T_219; // @[Mux.scala:30:73] wire [5:0] _schedule_T_226 = _schedule_T_225 | _schedule_T_220; // @[Mux.scala:30:73] wire [5:0] _schedule_T_227 = _schedule_T_226 | _schedule_T_221; // @[Mux.scala:30:73] assign _schedule_WIRE_25 = _schedule_T_227; // @[Mux.scala:30:73] assign _schedule_WIRE_20_put = _schedule_WIRE_25; // @[Mux.scala:30:73] wire [5:0] _schedule_T_228 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_229 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_230 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_231 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_232 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_233 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_234 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_235 = _schedule_T_228 | _schedule_T_229; // @[Mux.scala:30:73] wire [5:0] _schedule_T_236 = _schedule_T_235 | _schedule_T_230; // @[Mux.scala:30:73] wire [5:0] _schedule_T_237 = _schedule_T_236 | _schedule_T_231; // @[Mux.scala:30:73] wire [5:0] _schedule_T_238 = _schedule_T_237 | _schedule_T_232; // @[Mux.scala:30:73] wire [5:0] _schedule_T_239 = _schedule_T_238 | _schedule_T_233; // @[Mux.scala:30:73] wire [5:0] _schedule_T_240 = _schedule_T_239 | _schedule_T_234; // @[Mux.scala:30:73] assign _schedule_WIRE_26 = _schedule_T_240; // @[Mux.scala:30:73] assign _schedule_WIRE_20_offset = _schedule_WIRE_26; // @[Mux.scala:30:73] wire [12:0] _schedule_T_241 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_242 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_243 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_244 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_245 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_246 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_247 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_248 = _schedule_T_241 | _schedule_T_242; // @[Mux.scala:30:73] wire [12:0] _schedule_T_249 = _schedule_T_248 | _schedule_T_243; // @[Mux.scala:30:73] wire [12:0] _schedule_T_250 = _schedule_T_249 | _schedule_T_244; // @[Mux.scala:30:73] wire [12:0] _schedule_T_251 = _schedule_T_250 | _schedule_T_245; // @[Mux.scala:30:73] wire [12:0] _schedule_T_252 = _schedule_T_251 | _schedule_T_246; // @[Mux.scala:30:73] wire [12:0] _schedule_T_253 = _schedule_T_252 | _schedule_T_247; // @[Mux.scala:30:73] assign _schedule_WIRE_27 = _schedule_T_253; // @[Mux.scala:30:73] assign _schedule_WIRE_20_tag = _schedule_WIRE_27; // @[Mux.scala:30:73] wire [5:0] _schedule_T_254 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_255 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_256 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_257 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_258 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_259 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_260 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_261 = _schedule_T_254 | _schedule_T_255; // @[Mux.scala:30:73] wire [5:0] _schedule_T_262 = _schedule_T_261 | _schedule_T_256; // @[Mux.scala:30:73] wire [5:0] _schedule_T_263 = _schedule_T_262 | _schedule_T_257; // @[Mux.scala:30:73] wire [5:0] _schedule_T_264 = _schedule_T_263 | _schedule_T_258; // @[Mux.scala:30:73] wire [5:0] _schedule_T_265 = _schedule_T_264 | _schedule_T_259; // @[Mux.scala:30:73] wire [5:0] _schedule_T_266 = _schedule_T_265 | _schedule_T_260; // @[Mux.scala:30:73] assign _schedule_WIRE_28 = _schedule_T_266; // @[Mux.scala:30:73] assign _schedule_WIRE_20_source = _schedule_WIRE_28; // @[Mux.scala:30:73] wire [2:0] _schedule_T_267 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_268 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_269 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_270 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_271 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_272 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_273 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_274 = _schedule_T_267 | _schedule_T_268; // @[Mux.scala:30:73] wire [2:0] _schedule_T_275 = _schedule_T_274 | _schedule_T_269; // @[Mux.scala:30:73] wire [2:0] _schedule_T_276 = _schedule_T_275 | _schedule_T_270; // @[Mux.scala:30:73] wire [2:0] _schedule_T_277 = _schedule_T_276 | _schedule_T_271; // @[Mux.scala:30:73] wire [2:0] _schedule_T_278 = _schedule_T_277 | _schedule_T_272; // @[Mux.scala:30:73] wire [2:0] _schedule_T_279 = _schedule_T_278 | _schedule_T_273; // @[Mux.scala:30:73] assign _schedule_WIRE_29 = _schedule_T_279; // @[Mux.scala:30:73] assign _schedule_WIRE_20_size = _schedule_WIRE_29; // @[Mux.scala:30:73] wire [2:0] _schedule_T_280 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_281 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_282 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_283 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_284 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_285 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_286 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_287 = _schedule_T_280 | _schedule_T_281; // @[Mux.scala:30:73] wire [2:0] _schedule_T_288 = _schedule_T_287 | _schedule_T_282; // @[Mux.scala:30:73] wire [2:0] _schedule_T_289 = _schedule_T_288 | _schedule_T_283; // @[Mux.scala:30:73] wire [2:0] _schedule_T_290 = _schedule_T_289 | _schedule_T_284; // @[Mux.scala:30:73] wire [2:0] _schedule_T_291 = _schedule_T_290 | _schedule_T_285; // @[Mux.scala:30:73] wire [2:0] _schedule_T_292 = _schedule_T_291 | _schedule_T_286; // @[Mux.scala:30:73] assign _schedule_WIRE_30 = _schedule_T_292; // @[Mux.scala:30:73] assign _schedule_WIRE_20_param = _schedule_WIRE_30; // @[Mux.scala:30:73] wire [2:0] _schedule_T_293 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_294 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_295 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_296 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_297 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_298 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_299 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_300 = _schedule_T_293 | _schedule_T_294; // @[Mux.scala:30:73] wire [2:0] _schedule_T_301 = _schedule_T_300 | _schedule_T_295; // @[Mux.scala:30:73] wire [2:0] _schedule_T_302 = _schedule_T_301 | _schedule_T_296; // @[Mux.scala:30:73] wire [2:0] _schedule_T_303 = _schedule_T_302 | _schedule_T_297; // @[Mux.scala:30:73] wire [2:0] _schedule_T_304 = _schedule_T_303 | _schedule_T_298; // @[Mux.scala:30:73] wire [2:0] _schedule_T_305 = _schedule_T_304 | _schedule_T_299; // @[Mux.scala:30:73] assign _schedule_WIRE_31 = _schedule_T_305; // @[Mux.scala:30:73] assign _schedule_WIRE_20_opcode = _schedule_WIRE_31; // @[Mux.scala:30:73] wire _schedule_T_306 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_307 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_308 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_309 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_310 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_311 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_312 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_313 = _schedule_T_306 | _schedule_T_307; // @[Mux.scala:30:73] wire _schedule_T_314 = _schedule_T_313 | _schedule_T_308; // @[Mux.scala:30:73] wire _schedule_T_315 = _schedule_T_314 | _schedule_T_309; // @[Mux.scala:30:73] wire _schedule_T_316 = _schedule_T_315 | _schedule_T_310; // @[Mux.scala:30:73] wire _schedule_T_317 = _schedule_T_316 | _schedule_T_311; // @[Mux.scala:30:73] wire _schedule_T_318 = _schedule_T_317 | _schedule_T_312; // @[Mux.scala:30:73] assign _schedule_WIRE_32 = _schedule_T_318; // @[Mux.scala:30:73] assign _schedule_WIRE_20_control = _schedule_WIRE_32; // @[Mux.scala:30:73] wire _schedule_WIRE_34; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_0 = _schedule_WIRE_33_0; // @[Mux.scala:30:73] wire _schedule_WIRE_35; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_1 = _schedule_WIRE_33_1; // @[Mux.scala:30:73] wire _schedule_WIRE_36; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_2 = _schedule_WIRE_33_2; // @[Mux.scala:30:73] wire _schedule_T_319 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_320 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_321 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_322 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_323 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_326 = _schedule_T_319 | _schedule_T_320; // @[Mux.scala:30:73] wire _schedule_T_327 = _schedule_T_326 | _schedule_T_321; // @[Mux.scala:30:73] wire _schedule_T_328 = _schedule_T_327 | _schedule_T_322; // @[Mux.scala:30:73] wire _schedule_T_329 = _schedule_T_328 | _schedule_T_323; // @[Mux.scala:30:73] wire _schedule_T_330 = _schedule_T_329; // @[Mux.scala:30:73] wire _schedule_T_331 = _schedule_T_330; // @[Mux.scala:30:73] assign _schedule_WIRE_34 = _schedule_T_331; // @[Mux.scala:30:73] assign _schedule_WIRE_33_0 = _schedule_WIRE_34; // @[Mux.scala:30:73] wire _schedule_T_332 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_333 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_334 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_335 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_336 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_337 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_339 = _schedule_T_332 | _schedule_T_333; // @[Mux.scala:30:73] wire _schedule_T_340 = _schedule_T_339 | _schedule_T_334; // @[Mux.scala:30:73] wire _schedule_T_341 = _schedule_T_340 | _schedule_T_335; // @[Mux.scala:30:73] wire _schedule_T_342 = _schedule_T_341 | _schedule_T_336; // @[Mux.scala:30:73] wire _schedule_T_343 = _schedule_T_342 | _schedule_T_337; // @[Mux.scala:30:73] wire _schedule_T_344 = _schedule_T_343; // @[Mux.scala:30:73] assign _schedule_WIRE_35 = _schedule_T_344; // @[Mux.scala:30:73] assign _schedule_WIRE_33_1 = _schedule_WIRE_35; // @[Mux.scala:30:73] wire _schedule_T_345 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_346 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_347 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_348 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_349 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_350 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_351 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_352 = _schedule_T_345 | _schedule_T_346; // @[Mux.scala:30:73] wire _schedule_T_353 = _schedule_T_352 | _schedule_T_347; // @[Mux.scala:30:73] wire _schedule_T_354 = _schedule_T_353 | _schedule_T_348; // @[Mux.scala:30:73] wire _schedule_T_355 = _schedule_T_354 | _schedule_T_349; // @[Mux.scala:30:73] wire _schedule_T_356 = _schedule_T_355 | _schedule_T_350; // @[Mux.scala:30:73] wire _schedule_T_357 = _schedule_T_356 | _schedule_T_351; // @[Mux.scala:30:73] assign _schedule_WIRE_36 = _schedule_T_357; // @[Mux.scala:30:73] assign _schedule_WIRE_33_2 = _schedule_WIRE_36; // @[Mux.scala:30:73] wire _schedule_T_358 = _schedule_T & _mshrs_0_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_359 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_360 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_361 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_362 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_363 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_364 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_365 = _schedule_T_358 | _schedule_T_359; // @[Mux.scala:30:73] wire _schedule_T_366 = _schedule_T_365 | _schedule_T_360; // @[Mux.scala:30:73] wire _schedule_T_367 = _schedule_T_366 | _schedule_T_361; // @[Mux.scala:30:73] wire _schedule_T_368 = _schedule_T_367 | _schedule_T_362; // @[Mux.scala:30:73] wire _schedule_T_369 = _schedule_T_368 | _schedule_T_363; // @[Mux.scala:30:73] wire _schedule_T_370 = _schedule_T_369 | _schedule_T_364; // @[Mux.scala:30:73] assign _schedule_WIRE_37 = _schedule_T_370; // @[Mux.scala:30:73] assign _schedule_WIRE_19_valid = _schedule_WIRE_37; // @[Mux.scala:30:73] wire _schedule_WIRE_47; // @[Mux.scala:30:73] assign schedule_c_valid = _schedule_WIRE_38_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_opcode; // @[Mux.scala:30:73] assign schedule_c_bits_opcode = _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_param; // @[Mux.scala:30:73] assign schedule_c_bits_param = _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_39_tag; // @[Mux.scala:30:73] assign schedule_c_bits_tag = _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_39_set; // @[Mux.scala:30:73] assign schedule_c_bits_set = _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_way; // @[Mux.scala:30:73] assign schedule_c_bits_way = _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_39_dirty; // @[Mux.scala:30:73] assign schedule_c_bits_dirty = _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_46; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_opcode = _schedule_WIRE_39_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_45; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_param = _schedule_WIRE_39_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_43; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_tag = _schedule_WIRE_39_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_42; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_set = _schedule_WIRE_39_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_41; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_way = _schedule_WIRE_39_way; // @[Mux.scala:30:73] wire _schedule_WIRE_40; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_dirty = _schedule_WIRE_39_dirty; // @[Mux.scala:30:73] wire _schedule_T_371 = _schedule_T & _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_372 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_373 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_374 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_375 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_376 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_377 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_378 = _schedule_T_371 | _schedule_T_372; // @[Mux.scala:30:73] wire _schedule_T_379 = _schedule_T_378 | _schedule_T_373; // @[Mux.scala:30:73] wire _schedule_T_380 = _schedule_T_379 | _schedule_T_374; // @[Mux.scala:30:73] wire _schedule_T_381 = _schedule_T_380 | _schedule_T_375; // @[Mux.scala:30:73] wire _schedule_T_382 = _schedule_T_381 | _schedule_T_376; // @[Mux.scala:30:73] wire _schedule_T_383 = _schedule_T_382 | _schedule_T_377; // @[Mux.scala:30:73] assign _schedule_WIRE_40 = _schedule_T_383; // @[Mux.scala:30:73] assign _schedule_WIRE_39_dirty = _schedule_WIRE_40; // @[Mux.scala:30:73] wire [2:0] _schedule_T_384 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_385 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_386 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_387 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_388 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_389 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_390 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_391 = _schedule_T_384 | _schedule_T_385; // @[Mux.scala:30:73] wire [2:0] _schedule_T_392 = _schedule_T_391 | _schedule_T_386; // @[Mux.scala:30:73] wire [2:0] _schedule_T_393 = _schedule_T_392 | _schedule_T_387; // @[Mux.scala:30:73] wire [2:0] _schedule_T_394 = _schedule_T_393 | _schedule_T_388; // @[Mux.scala:30:73] wire [2:0] _schedule_T_395 = _schedule_T_394 | _schedule_T_389; // @[Mux.scala:30:73] wire [2:0] _schedule_T_396 = _schedule_T_395 | _schedule_T_390; // @[Mux.scala:30:73] assign _schedule_WIRE_41 = _schedule_T_396; // @[Mux.scala:30:73] assign _schedule_WIRE_39_way = _schedule_WIRE_41; // @[Mux.scala:30:73] wire [9:0] _schedule_T_397 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_398 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_399 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_400 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_401 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_402 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_403 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_404 = _schedule_T_397 | _schedule_T_398; // @[Mux.scala:30:73] wire [9:0] _schedule_T_405 = _schedule_T_404 | _schedule_T_399; // @[Mux.scala:30:73] wire [9:0] _schedule_T_406 = _schedule_T_405 | _schedule_T_400; // @[Mux.scala:30:73] wire [9:0] _schedule_T_407 = _schedule_T_406 | _schedule_T_401; // @[Mux.scala:30:73] wire [9:0] _schedule_T_408 = _schedule_T_407 | _schedule_T_402; // @[Mux.scala:30:73] wire [9:0] _schedule_T_409 = _schedule_T_408 | _schedule_T_403; // @[Mux.scala:30:73] assign _schedule_WIRE_42 = _schedule_T_409; // @[Mux.scala:30:73] assign _schedule_WIRE_39_set = _schedule_WIRE_42; // @[Mux.scala:30:73] wire [12:0] _schedule_T_410 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_411 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_412 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_413 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_414 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_415 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_416 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_417 = _schedule_T_410 | _schedule_T_411; // @[Mux.scala:30:73] wire [12:0] _schedule_T_418 = _schedule_T_417 | _schedule_T_412; // @[Mux.scala:30:73] wire [12:0] _schedule_T_419 = _schedule_T_418 | _schedule_T_413; // @[Mux.scala:30:73] wire [12:0] _schedule_T_420 = _schedule_T_419 | _schedule_T_414; // @[Mux.scala:30:73] wire [12:0] _schedule_T_421 = _schedule_T_420 | _schedule_T_415; // @[Mux.scala:30:73] wire [12:0] _schedule_T_422 = _schedule_T_421 | _schedule_T_416; // @[Mux.scala:30:73] assign _schedule_WIRE_43 = _schedule_T_422; // @[Mux.scala:30:73] assign _schedule_WIRE_39_tag = _schedule_WIRE_43; // @[Mux.scala:30:73] wire [2:0] _schedule_T_436 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_437 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_438 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_439 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_440 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_441 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_442 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_443 = _schedule_T_436 | _schedule_T_437; // @[Mux.scala:30:73] wire [2:0] _schedule_T_444 = _schedule_T_443 | _schedule_T_438; // @[Mux.scala:30:73] wire [2:0] _schedule_T_445 = _schedule_T_444 | _schedule_T_439; // @[Mux.scala:30:73] wire [2:0] _schedule_T_446 = _schedule_T_445 | _schedule_T_440; // @[Mux.scala:30:73] wire [2:0] _schedule_T_447 = _schedule_T_446 | _schedule_T_441; // @[Mux.scala:30:73] wire [2:0] _schedule_T_448 = _schedule_T_447 | _schedule_T_442; // @[Mux.scala:30:73] assign _schedule_WIRE_45 = _schedule_T_448; // @[Mux.scala:30:73] assign _schedule_WIRE_39_param = _schedule_WIRE_45; // @[Mux.scala:30:73] wire [2:0] _schedule_T_449 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_450 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_451 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_452 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_453 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_454 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_455 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_456 = _schedule_T_449 | _schedule_T_450; // @[Mux.scala:30:73] wire [2:0] _schedule_T_457 = _schedule_T_456 | _schedule_T_451; // @[Mux.scala:30:73] wire [2:0] _schedule_T_458 = _schedule_T_457 | _schedule_T_452; // @[Mux.scala:30:73] wire [2:0] _schedule_T_459 = _schedule_T_458 | _schedule_T_453; // @[Mux.scala:30:73] wire [2:0] _schedule_T_460 = _schedule_T_459 | _schedule_T_454; // @[Mux.scala:30:73] wire [2:0] _schedule_T_461 = _schedule_T_460 | _schedule_T_455; // @[Mux.scala:30:73] assign _schedule_WIRE_46 = _schedule_T_461; // @[Mux.scala:30:73] assign _schedule_WIRE_39_opcode = _schedule_WIRE_46; // @[Mux.scala:30:73] wire _schedule_T_462 = _schedule_T & _mshrs_0_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_463 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_464 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_465 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_466 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_467 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_468 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_469 = _schedule_T_462 | _schedule_T_463; // @[Mux.scala:30:73] wire _schedule_T_470 = _schedule_T_469 | _schedule_T_464; // @[Mux.scala:30:73] wire _schedule_T_471 = _schedule_T_470 | _schedule_T_465; // @[Mux.scala:30:73] wire _schedule_T_472 = _schedule_T_471 | _schedule_T_466; // @[Mux.scala:30:73] wire _schedule_T_473 = _schedule_T_472 | _schedule_T_467; // @[Mux.scala:30:73] wire _schedule_T_474 = _schedule_T_473 | _schedule_T_468; // @[Mux.scala:30:73] assign _schedule_WIRE_47 = _schedule_T_474; // @[Mux.scala:30:73] assign _schedule_WIRE_38_valid = _schedule_WIRE_47; // @[Mux.scala:30:73] wire _schedule_WIRE_54; // @[Mux.scala:30:73] assign schedule_b_valid = _schedule_WIRE_48_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_49_param; // @[Mux.scala:30:73] assign schedule_b_bits_param = _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_49_tag; // @[Mux.scala:30:73] assign schedule_b_bits_tag = _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_49_set; // @[Mux.scala:30:73] assign schedule_b_bits_set = _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73] wire _schedule_WIRE_49_clients; // @[Mux.scala:30:73] assign schedule_b_bits_clients = _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_53; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_param = _schedule_WIRE_49_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_52; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_tag = _schedule_WIRE_49_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_51; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_set = _schedule_WIRE_49_set; // @[Mux.scala:30:73] wire _schedule_WIRE_50; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_clients = _schedule_WIRE_49_clients; // @[Mux.scala:30:73] wire _schedule_T_475 = _schedule_T & _mshrs_0_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_476 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_477 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_478 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_479 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_480 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_481 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_482 = _schedule_T_475 | _schedule_T_476; // @[Mux.scala:30:73] wire _schedule_T_483 = _schedule_T_482 | _schedule_T_477; // @[Mux.scala:30:73] wire _schedule_T_484 = _schedule_T_483 | _schedule_T_478; // @[Mux.scala:30:73] wire _schedule_T_485 = _schedule_T_484 | _schedule_T_479; // @[Mux.scala:30:73] wire _schedule_T_486 = _schedule_T_485 | _schedule_T_480; // @[Mux.scala:30:73] wire _schedule_T_487 = _schedule_T_486 | _schedule_T_481; // @[Mux.scala:30:73] assign _schedule_WIRE_50 = _schedule_T_487; // @[Mux.scala:30:73] assign _schedule_WIRE_49_clients = _schedule_WIRE_50; // @[Mux.scala:30:73] wire [9:0] _schedule_T_488 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_489 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_490 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_491 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_492 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_493 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_494 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_495 = _schedule_T_488 | _schedule_T_489; // @[Mux.scala:30:73] wire [9:0] _schedule_T_496 = _schedule_T_495 | _schedule_T_490; // @[Mux.scala:30:73] wire [9:0] _schedule_T_497 = _schedule_T_496 | _schedule_T_491; // @[Mux.scala:30:73] wire [9:0] _schedule_T_498 = _schedule_T_497 | _schedule_T_492; // @[Mux.scala:30:73] wire [9:0] _schedule_T_499 = _schedule_T_498 | _schedule_T_493; // @[Mux.scala:30:73] wire [9:0] _schedule_T_500 = _schedule_T_499 | _schedule_T_494; // @[Mux.scala:30:73] assign _schedule_WIRE_51 = _schedule_T_500; // @[Mux.scala:30:73] assign _schedule_WIRE_49_set = _schedule_WIRE_51; // @[Mux.scala:30:73] wire [12:0] _schedule_T_501 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_502 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_503 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_504 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_505 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_506 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_507 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_508 = _schedule_T_501 | _schedule_T_502; // @[Mux.scala:30:73] wire [12:0] _schedule_T_509 = _schedule_T_508 | _schedule_T_503; // @[Mux.scala:30:73] wire [12:0] _schedule_T_510 = _schedule_T_509 | _schedule_T_504; // @[Mux.scala:30:73] wire [12:0] _schedule_T_511 = _schedule_T_510 | _schedule_T_505; // @[Mux.scala:30:73] wire [12:0] _schedule_T_512 = _schedule_T_511 | _schedule_T_506; // @[Mux.scala:30:73] wire [12:0] _schedule_T_513 = _schedule_T_512 | _schedule_T_507; // @[Mux.scala:30:73] assign _schedule_WIRE_52 = _schedule_T_513; // @[Mux.scala:30:73] assign _schedule_WIRE_49_tag = _schedule_WIRE_52; // @[Mux.scala:30:73] wire [2:0] _schedule_T_514 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_515 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_516 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_517 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_518 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_519 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_520 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_521 = _schedule_T_514 | _schedule_T_515; // @[Mux.scala:30:73] wire [2:0] _schedule_T_522 = _schedule_T_521 | _schedule_T_516; // @[Mux.scala:30:73] wire [2:0] _schedule_T_523 = _schedule_T_522 | _schedule_T_517; // @[Mux.scala:30:73] wire [2:0] _schedule_T_524 = _schedule_T_523 | _schedule_T_518; // @[Mux.scala:30:73] wire [2:0] _schedule_T_525 = _schedule_T_524 | _schedule_T_519; // @[Mux.scala:30:73] wire [2:0] _schedule_T_526 = _schedule_T_525 | _schedule_T_520; // @[Mux.scala:30:73] assign _schedule_WIRE_53 = _schedule_T_526; // @[Mux.scala:30:73] assign _schedule_WIRE_49_param = _schedule_WIRE_53; // @[Mux.scala:30:73] wire _schedule_T_527 = _schedule_T & _mshrs_0_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_528 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_529 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_530 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_531 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_532 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_533 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_534 = _schedule_T_527 | _schedule_T_528; // @[Mux.scala:30:73] wire _schedule_T_535 = _schedule_T_534 | _schedule_T_529; // @[Mux.scala:30:73] wire _schedule_T_536 = _schedule_T_535 | _schedule_T_530; // @[Mux.scala:30:73] wire _schedule_T_537 = _schedule_T_536 | _schedule_T_531; // @[Mux.scala:30:73] wire _schedule_T_538 = _schedule_T_537 | _schedule_T_532; // @[Mux.scala:30:73] wire _schedule_T_539 = _schedule_T_538 | _schedule_T_533; // @[Mux.scala:30:73] assign _schedule_WIRE_54 = _schedule_T_539; // @[Mux.scala:30:73] assign _schedule_WIRE_48_valid = _schedule_WIRE_54; // @[Mux.scala:30:73] wire _schedule_WIRE_62; // @[Mux.scala:30:73] assign schedule_a_valid = _schedule_WIRE_55_valid; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_56_tag; // @[Mux.scala:30:73] assign schedule_a_bits_tag = _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_56_set; // @[Mux.scala:30:73] assign schedule_a_bits_set = _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_56_param; // @[Mux.scala:30:73] assign schedule_a_bits_param = _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73] wire _schedule_WIRE_56_block; // @[Mux.scala:30:73] assign schedule_a_bits_block = _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_61; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_tag = _schedule_WIRE_56_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_60; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_set = _schedule_WIRE_56_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_59; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_param = _schedule_WIRE_56_param; // @[Mux.scala:30:73] wire _schedule_WIRE_57; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_block = _schedule_WIRE_56_block; // @[Mux.scala:30:73] wire _schedule_T_540 = _schedule_T & _mshrs_0_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_541 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_542 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_543 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_544 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_545 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_546 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_547 = _schedule_T_540 | _schedule_T_541; // @[Mux.scala:30:73] wire _schedule_T_548 = _schedule_T_547 | _schedule_T_542; // @[Mux.scala:30:73] wire _schedule_T_549 = _schedule_T_548 | _schedule_T_543; // @[Mux.scala:30:73] wire _schedule_T_550 = _schedule_T_549 | _schedule_T_544; // @[Mux.scala:30:73] wire _schedule_T_551 = _schedule_T_550 | _schedule_T_545; // @[Mux.scala:30:73] wire _schedule_T_552 = _schedule_T_551 | _schedule_T_546; // @[Mux.scala:30:73] assign _schedule_WIRE_57 = _schedule_T_552; // @[Mux.scala:30:73] assign _schedule_WIRE_56_block = _schedule_WIRE_57; // @[Mux.scala:30:73] wire [2:0] _schedule_T_566 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_567 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_568 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_569 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_570 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_571 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_572 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_573 = _schedule_T_566 | _schedule_T_567; // @[Mux.scala:30:73] wire [2:0] _schedule_T_574 = _schedule_T_573 | _schedule_T_568; // @[Mux.scala:30:73] wire [2:0] _schedule_T_575 = _schedule_T_574 | _schedule_T_569; // @[Mux.scala:30:73] wire [2:0] _schedule_T_576 = _schedule_T_575 | _schedule_T_570; // @[Mux.scala:30:73] wire [2:0] _schedule_T_577 = _schedule_T_576 | _schedule_T_571; // @[Mux.scala:30:73] wire [2:0] _schedule_T_578 = _schedule_T_577 | _schedule_T_572; // @[Mux.scala:30:73] assign _schedule_WIRE_59 = _schedule_T_578; // @[Mux.scala:30:73] assign _schedule_WIRE_56_param = _schedule_WIRE_59; // @[Mux.scala:30:73] wire [9:0] _schedule_T_579 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_580 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_581 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_582 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_583 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_584 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_585 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_586 = _schedule_T_579 | _schedule_T_580; // @[Mux.scala:30:73] wire [9:0] _schedule_T_587 = _schedule_T_586 | _schedule_T_581; // @[Mux.scala:30:73] wire [9:0] _schedule_T_588 = _schedule_T_587 | _schedule_T_582; // @[Mux.scala:30:73] wire [9:0] _schedule_T_589 = _schedule_T_588 | _schedule_T_583; // @[Mux.scala:30:73] wire [9:0] _schedule_T_590 = _schedule_T_589 | _schedule_T_584; // @[Mux.scala:30:73] wire [9:0] _schedule_T_591 = _schedule_T_590 | _schedule_T_585; // @[Mux.scala:30:73] assign _schedule_WIRE_60 = _schedule_T_591; // @[Mux.scala:30:73] assign _schedule_WIRE_56_set = _schedule_WIRE_60; // @[Mux.scala:30:73] wire [12:0] _schedule_T_592 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_593 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_594 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_595 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_596 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_597 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_598 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_599 = _schedule_T_592 | _schedule_T_593; // @[Mux.scala:30:73] wire [12:0] _schedule_T_600 = _schedule_T_599 | _schedule_T_594; // @[Mux.scala:30:73] wire [12:0] _schedule_T_601 = _schedule_T_600 | _schedule_T_595; // @[Mux.scala:30:73] wire [12:0] _schedule_T_602 = _schedule_T_601 | _schedule_T_596; // @[Mux.scala:30:73] wire [12:0] _schedule_T_603 = _schedule_T_602 | _schedule_T_597; // @[Mux.scala:30:73] wire [12:0] _schedule_T_604 = _schedule_T_603 | _schedule_T_598; // @[Mux.scala:30:73] assign _schedule_WIRE_61 = _schedule_T_604; // @[Mux.scala:30:73] assign _schedule_WIRE_56_tag = _schedule_WIRE_61; // @[Mux.scala:30:73] wire _schedule_T_605 = _schedule_T & _mshrs_0_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_606 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_607 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_608 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_609 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_610 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_611 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_612 = _schedule_T_605 | _schedule_T_606; // @[Mux.scala:30:73] wire _schedule_T_613 = _schedule_T_612 | _schedule_T_607; // @[Mux.scala:30:73] wire _schedule_T_614 = _schedule_T_613 | _schedule_T_608; // @[Mux.scala:30:73] wire _schedule_T_615 = _schedule_T_614 | _schedule_T_609; // @[Mux.scala:30:73] wire _schedule_T_616 = _schedule_T_615 | _schedule_T_610; // @[Mux.scala:30:73] wire _schedule_T_617 = _schedule_T_616 | _schedule_T_611; // @[Mux.scala:30:73] assign _schedule_WIRE_62 = _schedule_T_617; // @[Mux.scala:30:73] assign _schedule_WIRE_55_valid = _schedule_WIRE_62; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_7 = _scheduleTag_T ? _mshrs_0_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_8 = _scheduleTag_T_1 ? _mshrs_1_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_9 = _scheduleTag_T_2 ? _mshrs_2_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_10 = _scheduleTag_T_3 ? _mshrs_3_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_11 = _scheduleTag_T_4 ? _mshrs_4_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_12 = _scheduleTag_T_5 ? _mshrs_5_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_13 = _scheduleTag_T_6 ? _mshrs_6_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_14 = _scheduleTag_T_7 | _scheduleTag_T_8; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_15 = _scheduleTag_T_14 | _scheduleTag_T_9; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_16 = _scheduleTag_T_15 | _scheduleTag_T_10; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_17 = _scheduleTag_T_16 | _scheduleTag_T_11; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_18 = _scheduleTag_T_17 | _scheduleTag_T_12; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_19 = _scheduleTag_T_18 | _scheduleTag_T_13; // @[Mux.scala:30:73] wire [12:0] scheduleTag = _scheduleTag_T_19; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_7 = _scheduleSet_T ? _mshrs_0_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_8 = _scheduleSet_T_1 ? _mshrs_1_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_9 = _scheduleSet_T_2 ? _mshrs_2_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_10 = _scheduleSet_T_3 ? _mshrs_3_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_11 = _scheduleSet_T_4 ? _mshrs_4_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_12 = _scheduleSet_T_5 ? _mshrs_5_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_13 = _scheduleSet_T_6 ? _mshrs_6_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_14 = _scheduleSet_T_7 | _scheduleSet_T_8; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_15 = _scheduleSet_T_14 | _scheduleSet_T_9; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_16 = _scheduleSet_T_15 | _scheduleSet_T_10; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_17 = _scheduleSet_T_16 | _scheduleSet_T_11; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_18 = _scheduleSet_T_17 | _scheduleSet_T_12; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_19 = _scheduleSet_T_18 | _scheduleSet_T_13; // @[Mux.scala:30:73] wire [9:0] scheduleSet = _scheduleSet_T_19; // @[Mux.scala:30:73] wire [5:0] _robin_filter_T = mshr_selectOH[6:1]; // @[package.scala:262:48] wire [6:0] _robin_filter_T_1 = {mshr_selectOH[6], mshr_selectOH[5:0] | _robin_filter_T}; // @[Mux.scala:32:36] wire [4:0] _robin_filter_T_2 = _robin_filter_T_1[6:2]; // @[package.scala:262:{43,48}] wire [6:0] _robin_filter_T_3 = {_robin_filter_T_1[6:5], _robin_filter_T_1[4:0] | _robin_filter_T_2}; // @[package.scala:262:{43,48}] wire [2:0] _robin_filter_T_4 = _robin_filter_T_3[6:4]; // @[package.scala:262:{43,48}] wire [6:0] _robin_filter_T_5 = {_robin_filter_T_3[6:3], _robin_filter_T_3[2:0] | _robin_filter_T_4}; // @[package.scala:262:{43,48}] wire [6:0] _robin_filter_T_6 = _robin_filter_T_5; // @[package.scala:262:43, :263:17] wire [6:0] _robin_filter_T_7 = ~_robin_filter_T_6; // @[package.scala:263:17] wire _schedule_c_bits_source_T = schedule_c_bits_opcode[1]; // @[Mux.scala:30:73] assign _schedule_c_bits_source_T_1 = _schedule_c_bits_source_T ? mshr_select : 3'h0; // @[OneHot.scala:32:10] assign schedule_c_bits_source = _schedule_c_bits_source_T_1; // @[Mux.scala:30:73] assign _nestedwb_set_T = select_c ? _mshrs_6_io_status_bits_set : _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :153:32, :155:24] assign nestedwb_set = _nestedwb_set_T; // @[Scheduler.scala:75:22, :155:24] assign _nestedwb_tag_T = select_c ? _mshrs_6_io_status_bits_tag : _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :153:32, :156:24] assign nestedwb_tag = _nestedwb_tag_T; // @[Scheduler.scala:75:22, :156:24] wire _GEN = select_bc & _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :154:32, :157:37] wire _nestedwb_b_toN_T; // @[Scheduler.scala:157:37] assign _nestedwb_b_toN_T = _GEN; // @[Scheduler.scala:157:37] wire _nestedwb_b_toB_T; // @[Scheduler.scala:158:37] assign _nestedwb_b_toB_T = _GEN; // @[Scheduler.scala:157:37, :158:37] assign _nestedwb_b_clr_dirty_T = _GEN; // @[Scheduler.scala:157:37, :159:37] wire _nestedwb_b_toN_T_1 = _mshrs_5_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala:71:46, :157:123] assign _nestedwb_b_toN_T_2 = _nestedwb_b_toN_T & _nestedwb_b_toN_T_1; // @[Scheduler.scala:157:{37,75,123}] assign nestedwb_b_toN = _nestedwb_b_toN_T_2; // @[Scheduler.scala:75:22, :157:75] wire _nestedwb_b_toB_T_1 = _mshrs_5_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala:71:46, :158:123] assign _nestedwb_b_toB_T_2 = _nestedwb_b_toB_T & _nestedwb_b_toB_T_1; // @[Scheduler.scala:158:{37,75,123}] assign nestedwb_b_toB = _nestedwb_b_toB_T_2; // @[Scheduler.scala:75:22, :158:75] assign nestedwb_b_clr_dirty = _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:75:22, :159:37] wire _nestedwb_c_set_dirty_T = select_c & _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :153:32, :160:37] assign _nestedwb_c_set_dirty_T_1 = _nestedwb_c_set_dirty_T & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46, :160:{37,75}] assign nestedwb_c_set_dirty = _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:75:22, :160:75] wire _request_ready_T_2; // @[Scheduler.scala:261:40] wire _request_valid_T_2; // @[Scheduler.scala:164:39] wire _request_bits_T_1_prio_0; // @[Scheduler.scala:165:22] wire _view__WIRE_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _request_bits_T_1_prio_2; // @[Scheduler.scala:165:22] wire _request_bits_T_1_control; // @[Scheduler.scala:165:22] wire _view__WIRE_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_opcode; // @[Scheduler.scala:165:22] wire _view__WIRE_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_param; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_size; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_source; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _request_bits_T_1_tag; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_offset; // @[Scheduler.scala:165:22] wire [12:0] _view__WIRE_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_1_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_2_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_3_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_4_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_5_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_6_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_put; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [9:0] _request_bits_T_1_set; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [9:0] request_bits_set; // @[Scheduler.scala:163:21] wire request_ready; // @[Scheduler.scala:163:21] wire request_valid; // @[Scheduler.scala:163:21] wire _request_valid_T = _sinkA_io_req_valid | _sinkX_io_req_valid; // @[Scheduler.scala:54:21, :58:21, :164:62] wire _request_valid_T_1 = _request_valid_T | _sinkC_io_req_valid; // @[Scheduler.scala:55:21, :164:{62,84}] assign _request_valid_T_2 = _directory_io_ready & _request_valid_T_1; // @[Scheduler.scala:68:25, :164:{39,84}] assign request_valid = _request_valid_T_2; // @[Scheduler.scala:163:21, :164:39] wire [2:0] _request_bits_T_opcode = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [2:0] _request_bits_T_param = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [2:0] _request_bits_T_size = _sinkX_io_req_valid ? 3'h6 : _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_source = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [12:0] _request_bits_T_tag = _sinkX_io_req_valid ? _sinkX_io_req_bits_tag : _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_offset = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_put = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [9:0] _request_bits_T_set = _sinkX_io_req_valid ? _sinkX_io_req_bits_set : _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21, :58:21, :166:22] wire _request_bits_T_control; // @[Scheduler.scala:166:22] assign _request_bits_T_1_control = ~_sinkC_io_req_valid & _request_bits_T_control; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_opcode = _sinkC_io_req_valid ? _sinkC_io_req_bits_opcode : _request_bits_T_opcode; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_param = _sinkC_io_req_valid ? _sinkC_io_req_bits_param : _request_bits_T_param; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_size = _sinkC_io_req_valid ? _sinkC_io_req_bits_size : _request_bits_T_size; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_source = _sinkC_io_req_valid ? _sinkC_io_req_bits_source : _request_bits_T_source; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_tag = _sinkC_io_req_valid ? _sinkC_io_req_bits_tag : _request_bits_T_tag; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_offset = _sinkC_io_req_valid ? _sinkC_io_req_bits_offset : _request_bits_T_offset; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_put = _sinkC_io_req_valid ? _sinkC_io_req_bits_put : _request_bits_T_put; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_set = _sinkC_io_req_valid ? _sinkC_io_req_bits_set : _request_bits_T_set; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_prio_0 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22] assign request_bits_prio_0 = _request_bits_T_1_prio_0; // @[Scheduler.scala:163:21, :165:22] assign request_bits_prio_2 = _request_bits_T_1_prio_2; // @[Scheduler.scala:163:21, :165:22] assign request_bits_control = _request_bits_T_1_control; // @[Scheduler.scala:163:21, :165:22] assign request_bits_opcode = _request_bits_T_1_opcode; // @[Scheduler.scala:163:21, :165:22] assign request_bits_param = _request_bits_T_1_param; // @[Scheduler.scala:163:21, :165:22] assign request_bits_size = _request_bits_T_1_size; // @[Scheduler.scala:163:21, :165:22] assign request_bits_source = _request_bits_T_1_source; // @[Scheduler.scala:163:21, :165:22] assign request_bits_tag = _request_bits_T_1_tag; // @[Scheduler.scala:163:21, :165:22] assign request_bits_offset = _request_bits_T_1_offset; // @[Scheduler.scala:163:21, :165:22] assign request_bits_put = _request_bits_T_1_put; // @[Scheduler.scala:163:21, :165:22] assign request_bits_set = _request_bits_T_1_set; // @[Scheduler.scala:163:21, :165:22] wire _GEN_0 = _directory_io_ready & request_ready; // @[Scheduler.scala:68:25, :163:21, :167:44] wire _sinkC_io_req_ready_T; // @[Scheduler.scala:167:44] assign _sinkC_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44] wire _sinkX_io_req_ready_T; // @[Scheduler.scala:168:44] assign _sinkX_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :168:44] wire _sinkA_io_req_ready_T; // @[Scheduler.scala:169:44] assign _sinkA_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :169:44] wire _sinkX_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :168:64] wire _sinkX_io_req_ready_T_2 = _sinkX_io_req_ready_T & _sinkX_io_req_ready_T_1; // @[Scheduler.scala:168:{44,61,64}] wire _sinkA_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :169:64] wire _sinkA_io_req_ready_T_2 = _sinkA_io_req_ready_T & _sinkA_io_req_ready_T_1; // @[Scheduler.scala:169:{44,61,64}] wire _sinkA_io_req_ready_T_3 = ~_sinkX_io_req_valid; // @[Scheduler.scala:58:21, :169:87] wire _sinkA_io_req_ready_T_4 = _sinkA_io_req_ready_T_2 & _sinkA_io_req_ready_T_3; // @[Scheduler.scala:169:{61,84,87}] wire _setMatches_T = _mshrs_0_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_1 = _mshrs_0_io_status_valid & _setMatches_T; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_2 = _mshrs_1_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_3 = _mshrs_1_io_status_valid & _setMatches_T_2; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_4 = _mshrs_2_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_5 = _mshrs_2_io_status_valid & _setMatches_T_4; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_6 = _mshrs_3_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_7 = _mshrs_3_io_status_valid & _setMatches_T_6; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_8 = _mshrs_4_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_9 = _mshrs_4_io_status_valid & _setMatches_T_8; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_10 = _mshrs_5_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_11 = _mshrs_5_io_status_valid & _setMatches_T_10; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_12 = _mshrs_6_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_13 = _mshrs_6_io_status_valid & _setMatches_T_12; // @[Scheduler.scala:71:46, :172:{59,83}] wire [1:0] setMatches_lo_hi = {_setMatches_T_5, _setMatches_T_3}; // @[Scheduler.scala:172:{23,59}] wire [2:0] setMatches_lo = {setMatches_lo_hi, _setMatches_T_1}; // @[Scheduler.scala:172:{23,59}] wire [1:0] setMatches_hi_lo = {_setMatches_T_9, _setMatches_T_7}; // @[Scheduler.scala:172:{23,59}] wire [1:0] setMatches_hi_hi = {_setMatches_T_13, _setMatches_T_11}; // @[Scheduler.scala:172:{23,59}] wire [3:0] setMatches_hi = {setMatches_hi_hi, setMatches_hi_lo}; // @[Scheduler.scala:172:23] wire [6:0] setMatches = {setMatches_hi, setMatches_lo}; // @[Scheduler.scala:172:23] wire _alloc_T = |setMatches; // @[Scheduler.scala:172:23, :173:27] wire alloc = ~_alloc_T; // @[Scheduler.scala:173:{15,27}] wire _blockB_T = setMatches[0]; // @[Mux.scala:32:36] wire _blockC_T = setMatches[0]; // @[Mux.scala:32:36] wire _nestB_T = setMatches[0]; // @[Mux.scala:32:36] wire _nestC_T = setMatches[0]; // @[Mux.scala:32:36] wire _blockB_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _blockC_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _nestB_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _nestC_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _blockB_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _blockC_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _nestB_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _nestC_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _blockB_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _blockC_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _nestB_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _nestC_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _blockB_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _blockC_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _nestB_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _nestC_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _blockB_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _blockC_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _nestB_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _nestC_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _blockB_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _blockC_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _nestB_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _nestC_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _blockB_T_7 = _blockB_T & _mshrs_0_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_8 = _blockB_T_1 & _mshrs_1_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_9 = _blockB_T_2 & _mshrs_2_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_10 = _blockB_T_3 & _mshrs_3_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_11 = _blockB_T_4 & _mshrs_4_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_12 = _blockB_T_5 & _mshrs_5_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_13 = _blockB_T_6 & _mshrs_6_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_14 = _blockB_T_7 | _blockB_T_8; // @[Mux.scala:30:73] wire _blockB_T_15 = _blockB_T_14 | _blockB_T_9; // @[Mux.scala:30:73] wire _blockB_T_16 = _blockB_T_15 | _blockB_T_10; // @[Mux.scala:30:73] wire _blockB_T_17 = _blockB_T_16 | _blockB_T_11; // @[Mux.scala:30:73] wire _blockB_T_18 = _blockB_T_17 | _blockB_T_12; // @[Mux.scala:30:73] wire _blockB_T_19 = _blockB_T_18 | _blockB_T_13; // @[Mux.scala:30:73] wire _blockB_WIRE = _blockB_T_19; // @[Mux.scala:30:73] wire _blockC_T_7 = _blockC_T & _mshrs_0_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_8 = _blockC_T_1 & _mshrs_1_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_9 = _blockC_T_2 & _mshrs_2_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_10 = _blockC_T_3 & _mshrs_3_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_11 = _blockC_T_4 & _mshrs_4_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_12 = _blockC_T_5 & _mshrs_5_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_13 = _blockC_T_6 & _mshrs_6_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_14 = _blockC_T_7 | _blockC_T_8; // @[Mux.scala:30:73] wire _blockC_T_15 = _blockC_T_14 | _blockC_T_9; // @[Mux.scala:30:73] wire _blockC_T_16 = _blockC_T_15 | _blockC_T_10; // @[Mux.scala:30:73] wire _blockC_T_17 = _blockC_T_16 | _blockC_T_11; // @[Mux.scala:30:73] wire _blockC_T_18 = _blockC_T_17 | _blockC_T_12; // @[Mux.scala:30:73] wire _blockC_T_19 = _blockC_T_18 | _blockC_T_13; // @[Mux.scala:30:73] wire _blockC_WIRE = _blockC_T_19; // @[Mux.scala:30:73] wire blockC = _blockC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73] wire _nestB_T_7 = _nestB_T & _mshrs_0_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_8 = _nestB_T_1 & _mshrs_1_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_9 = _nestB_T_2 & _mshrs_2_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_10 = _nestB_T_3 & _mshrs_3_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_11 = _nestB_T_4 & _mshrs_4_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_12 = _nestB_T_5 & _mshrs_5_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_13 = _nestB_T_6 & _mshrs_6_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_14 = _nestB_T_7 | _nestB_T_8; // @[Mux.scala:30:73] wire _nestB_T_15 = _nestB_T_14 | _nestB_T_9; // @[Mux.scala:30:73] wire _nestB_T_16 = _nestB_T_15 | _nestB_T_10; // @[Mux.scala:30:73] wire _nestB_T_17 = _nestB_T_16 | _nestB_T_11; // @[Mux.scala:30:73] wire _nestB_T_18 = _nestB_T_17 | _nestB_T_12; // @[Mux.scala:30:73] wire _nestB_T_19 = _nestB_T_18 | _nestB_T_13; // @[Mux.scala:30:73] wire _nestB_WIRE = _nestB_T_19; // @[Mux.scala:30:73] wire _nestC_T_7 = _nestC_T & _mshrs_0_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_8 = _nestC_T_1 & _mshrs_1_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_9 = _nestC_T_2 & _mshrs_2_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_10 = _nestC_T_3 & _mshrs_3_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_11 = _nestC_T_4 & _mshrs_4_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_12 = _nestC_T_5 & _mshrs_5_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_13 = _nestC_T_6 & _mshrs_6_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_14 = _nestC_T_7 | _nestC_T_8; // @[Mux.scala:30:73] wire _nestC_T_15 = _nestC_T_14 | _nestC_T_9; // @[Mux.scala:30:73] wire _nestC_T_16 = _nestC_T_15 | _nestC_T_10; // @[Mux.scala:30:73] wire _nestC_T_17 = _nestC_T_16 | _nestC_T_11; // @[Mux.scala:30:73] wire _nestC_T_18 = _nestC_T_17 | _nestC_T_12; // @[Mux.scala:30:73] wire _nestC_T_19 = _nestC_T_18 | _nestC_T_13; // @[Mux.scala:30:73] wire _nestC_WIRE = _nestC_T_19; // @[Mux.scala:30:73] wire nestC = _nestC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73] wire _prioFilter_T = ~request_bits_prio_0; // @[Scheduler.scala:163:21, :182:46] wire [1:0] prioFilter_hi = {request_bits_prio_2, _prioFilter_T}; // @[Scheduler.scala:163:21, :182:{23,46}] wire [6:0] prioFilter = {prioFilter_hi, 5'h1F}; // @[Scheduler.scala:182:23] wire [6:0] lowerMatches = setMatches & prioFilter; // @[Scheduler.scala:172:23, :182:23, :183:33] wire _queue_T = |lowerMatches; // @[Scheduler.scala:183:33, :185:28] wire _queue_T_2 = _queue_T; // @[Scheduler.scala:185:{28,32}] wire _queue_T_3 = ~nestC; // @[Scheduler.scala:180:70, :185:45] wire _queue_T_4 = _queue_T_2 & _queue_T_3; // @[Scheduler.scala:185:{32,42,45}] wire _queue_T_6 = _queue_T_4; // @[Scheduler.scala:185:{42,52}] wire _queue_T_7 = ~blockC; // @[Scheduler.scala:176:70, :185:66] wire queue = _queue_T_6 & _queue_T_7; // @[Scheduler.scala:185:{52,63,66}] wire _T_7 = request_valid & queue; // @[Scheduler.scala:163:21, :185:63, :195:31] wire _bypass_T; // @[Scheduler.scala:213:30] assign _bypass_T = _T_7; // @[Scheduler.scala:195:31, :213:30] wire _bypass_T_1; // @[Scheduler.scala:231:32] assign _bypass_T_1 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_2; // @[Scheduler.scala:231:32] assign _bypass_T_2 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_3; // @[Scheduler.scala:231:32] assign _bypass_T_3 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_4; // @[Scheduler.scala:231:32] assign _bypass_T_4 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_5; // @[Scheduler.scala:231:32] assign _bypass_T_5 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_6; // @[Scheduler.scala:231:32] assign _bypass_T_6 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_7; // @[Scheduler.scala:231:32] assign _bypass_T_7 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _requests_io_push_valid_T; // @[Scheduler.scala:270:43] assign _requests_io_push_valid_T = _T_7; // @[Scheduler.scala:195:31, :270:43] wire _lowerMatches1_T = lowerMatches[6]; // @[Scheduler.scala:183:33, :200:21] wire _lowerMatches1_T_2 = lowerMatches[5]; // @[Scheduler.scala:183:33, :201:21] wire [6:0] _lowerMatches1_T_4 = _lowerMatches1_T_2 ? 7'h20 : lowerMatches; // @[Scheduler.scala:183:33, :201:{8,21}] wire [6:0] lowerMatches1 = _lowerMatches1_T ? 7'h40 : _lowerMatches1_T_4; // @[Scheduler.scala:200:{8,21}, :201:8] wire [6:0] _requests_io_push_bits_index_T = lowerMatches1; // @[Scheduler.scala:200:8, :274:30] wire [13:0] _GEN_1 = {2{mshr_selectOH}}; // @[Scheduler.scala:121:70, :206:30] wire [13:0] selected_requests_hi; // @[Scheduler.scala:206:30] assign selected_requests_hi = _GEN_1; // @[Scheduler.scala:206:30] wire [13:0] pop_index_hi; // @[Scheduler.scala:241:31] assign pop_index_hi = _GEN_1; // @[Scheduler.scala:206:30, :241:31] wire [20:0] _selected_requests_T = {selected_requests_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :206:30] wire [20:0] selected_requests = _selected_requests_T & _requests_io_valid; // @[Scheduler.scala:70:24, :206:{30,76}] wire [6:0] _a_pop_T = selected_requests[6:0]; // @[Scheduler.scala:206:76, :207:32] wire a_pop = |_a_pop_T; // @[Scheduler.scala:207:{32,79}] wire [6:0] _b_pop_T = selected_requests[13:7]; // @[Scheduler.scala:206:76, :208:32] wire b_pop = |_b_pop_T; // @[Scheduler.scala:208:{32,79}] wire _bypassMatches_T_4 = b_pop; // @[Scheduler.scala:208:79, :211:76] wire [6:0] _c_pop_T = selected_requests[20:14]; // @[Scheduler.scala:206:76, :209:32] wire c_pop = |_c_pop_T; // @[Scheduler.scala:209:{32,79}] wire [6:0] _bypassMatches_T = mshr_selectOH & lowerMatches1; // @[Scheduler.scala:121:70, :200:8, :210:38] wire _bypassMatches_T_1 = |_bypassMatches_T; // @[Scheduler.scala:210:{38,55}] wire _bypassMatches_T_2 = c_pop | request_bits_prio_2; // @[Scheduler.scala:163:21, :209:79, :211:33] wire _bypassMatches_T_3 = ~c_pop; // @[Scheduler.scala:209:79, :211:58] wire _bypassMatches_T_5 = ~b_pop; // @[Scheduler.scala:208:79, :211:101] wire _bypassMatches_T_6 = ~a_pop; // @[Scheduler.scala:207:79, :211:109] wire _bypassMatches_T_7 = _bypassMatches_T_4 ? _bypassMatches_T_5 : _bypassMatches_T_6; // @[Scheduler.scala:211:{69,76,101,109}] wire _bypassMatches_T_8 = _bypassMatches_T_2 ? _bypassMatches_T_3 : _bypassMatches_T_7; // @[Scheduler.scala:211:{26,33,58,69}] wire bypassMatches = _bypassMatches_T_1 & _bypassMatches_T_8; // @[Scheduler.scala:210:{55,59}, :211:26] wire _may_pop_T = a_pop | b_pop; // @[Scheduler.scala:207:79, :208:79, :212:23] wire may_pop = _may_pop_T | c_pop; // @[Scheduler.scala:209:79, :212:{23,32}] wire bypass = _bypass_T & bypassMatches; // @[Scheduler.scala:210:59, :213:{30,39}] wire _will_reload_T = may_pop | bypass; // @[Scheduler.scala:212:32, :213:39, :214:49] wire will_reload = schedule_reload & _will_reload_T; // @[Mux.scala:30:73] wire _GEN_2 = schedule_reload & may_pop; // @[Mux.scala:30:73] wire _will_pop_T; // @[Scheduler.scala:215:34] assign _will_pop_T = _GEN_2; // @[Scheduler.scala:215:34] wire _mshr_uses_directory_assuming_no_bypass_T; // @[Scheduler.scala:247:64] assign _mshr_uses_directory_assuming_no_bypass_T = _GEN_2; // @[Scheduler.scala:215:34, :247:64] wire _will_pop_T_1 = ~bypass; // @[Scheduler.scala:213:39, :215:48] wire will_pop = _will_pop_T & _will_pop_T_1; // @[Scheduler.scala:215:{34,45,48}] wire a_pop_1 = _requests_io_valid[0]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_1 = _requests_io_valid[7]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_12 = b_pop_1; // @[Scheduler.scala:226:34, :229:78] wire c_pop_1 = _requests_io_valid[14]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_9 = lowerMatches1[0]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_10 = c_pop_1 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_11 = ~c_pop_1; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_13 = ~b_pop_1; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_14 = ~a_pop_1; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_15 = _bypassMatches_T_12 ? _bypassMatches_T_13 : _bypassMatches_T_14; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_16 = _bypassMatches_T_10 ? _bypassMatches_T_11 : _bypassMatches_T_15; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_1 = _bypassMatches_T_9 & _bypassMatches_T_16; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_1 = a_pop_1 | b_pop_1; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_1 = _may_pop_T_1 | c_pop_1; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_1 = _bypass_T_1 & bypassMatches_1; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_1 = may_pop_1 | bypass_1; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_1 = _mshrs_0_io_schedule_bits_reload & _will_reload_T_1; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_prio_0 = bypass_1 ? _view__WIRE_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_prio_1 = ~bypass_1 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_prio_2 = bypass_1 ? _view__WIRE_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_control = bypass_1 ? _view__WIRE_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_opcode = bypass_1 ? _view__WIRE_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_param = bypass_1 ? _view__WIRE_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_size = bypass_1 ? _view__WIRE_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_source = bypass_1 ? _view__WIRE_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_tag = bypass_1 ? _view__WIRE_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_offset = bypass_1 ? _view__WIRE_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_put = bypass_1 ? _view__WIRE_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_0_io_allocate_bits_repeat_T = mshrs_0_io_allocate_bits_tag == _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_0_io_allocate_valid_T = sel & will_reload_1; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_2 = _requests_io_valid[1]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_2 = _requests_io_valid[8]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_20 = b_pop_2; // @[Scheduler.scala:226:34, :229:78] wire c_pop_2 = _requests_io_valid[15]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_17 = lowerMatches1[1]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_18 = c_pop_2 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_19 = ~c_pop_2; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_21 = ~b_pop_2; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_22 = ~a_pop_2; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_23 = _bypassMatches_T_20 ? _bypassMatches_T_21 : _bypassMatches_T_22; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_24 = _bypassMatches_T_18 ? _bypassMatches_T_19 : _bypassMatches_T_23; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_2 = _bypassMatches_T_17 & _bypassMatches_T_24; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_2 = a_pop_2 | b_pop_2; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_2 = _may_pop_T_2 | c_pop_2; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_2 = _bypass_T_2 & bypassMatches_2; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_2 = may_pop_2 | bypass_2; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_2 = _mshrs_1_io_schedule_bits_reload & _will_reload_T_2; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_1_prio_0 = bypass_2 ? _view__WIRE_1_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_1_prio_1 = ~bypass_2 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_1_prio_2 = bypass_2 ? _view__WIRE_1_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_1_control = bypass_2 ? _view__WIRE_1_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_opcode = bypass_2 ? _view__WIRE_1_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_param = bypass_2 ? _view__WIRE_1_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_size = bypass_2 ? _view__WIRE_1_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_source = bypass_2 ? _view__WIRE_1_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_1_tag = bypass_2 ? _view__WIRE_1_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_offset = bypass_2 ? _view__WIRE_1_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_put = bypass_2 ? _view__WIRE_1_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_1_io_allocate_bits_repeat_T = mshrs_1_io_allocate_bits_tag == _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_1_io_allocate_valid_T = sel_1 & will_reload_2; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_3 = _requests_io_valid[2]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_3 = _requests_io_valid[9]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_28 = b_pop_3; // @[Scheduler.scala:226:34, :229:78] wire c_pop_3 = _requests_io_valid[16]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_25 = lowerMatches1[2]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_26 = c_pop_3 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_27 = ~c_pop_3; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_29 = ~b_pop_3; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_30 = ~a_pop_3; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_31 = _bypassMatches_T_28 ? _bypassMatches_T_29 : _bypassMatches_T_30; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_32 = _bypassMatches_T_26 ? _bypassMatches_T_27 : _bypassMatches_T_31; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_3 = _bypassMatches_T_25 & _bypassMatches_T_32; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_3 = a_pop_3 | b_pop_3; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_3 = _may_pop_T_3 | c_pop_3; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_3 = _bypass_T_3 & bypassMatches_3; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_3 = may_pop_3 | bypass_3; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_3 = _mshrs_2_io_schedule_bits_reload & _will_reload_T_3; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_2_prio_0 = bypass_3 ? _view__WIRE_2_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_2_prio_1 = ~bypass_3 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_2_prio_2 = bypass_3 ? _view__WIRE_2_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_2_control = bypass_3 ? _view__WIRE_2_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_opcode = bypass_3 ? _view__WIRE_2_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_param = bypass_3 ? _view__WIRE_2_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_size = bypass_3 ? _view__WIRE_2_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_source = bypass_3 ? _view__WIRE_2_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_2_tag = bypass_3 ? _view__WIRE_2_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_offset = bypass_3 ? _view__WIRE_2_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_put = bypass_3 ? _view__WIRE_2_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_2_io_allocate_bits_repeat_T = mshrs_2_io_allocate_bits_tag == _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_2_io_allocate_valid_T = sel_2 & will_reload_3; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_4 = _requests_io_valid[3]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_4 = _requests_io_valid[10]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_36 = b_pop_4; // @[Scheduler.scala:226:34, :229:78] wire c_pop_4 = _requests_io_valid[17]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_33 = lowerMatches1[3]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_34 = c_pop_4 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_35 = ~c_pop_4; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_37 = ~b_pop_4; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_38 = ~a_pop_4; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_39 = _bypassMatches_T_36 ? _bypassMatches_T_37 : _bypassMatches_T_38; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_40 = _bypassMatches_T_34 ? _bypassMatches_T_35 : _bypassMatches_T_39; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_4 = _bypassMatches_T_33 & _bypassMatches_T_40; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_4 = a_pop_4 | b_pop_4; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_4 = _may_pop_T_4 | c_pop_4; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_4 = _bypass_T_4 & bypassMatches_4; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_4 = may_pop_4 | bypass_4; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_4 = _mshrs_3_io_schedule_bits_reload & _will_reload_T_4; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_3_prio_0 = bypass_4 ? _view__WIRE_3_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_3_prio_1 = ~bypass_4 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_3_prio_2 = bypass_4 ? _view__WIRE_3_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_3_control = bypass_4 ? _view__WIRE_3_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_opcode = bypass_4 ? _view__WIRE_3_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_param = bypass_4 ? _view__WIRE_3_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_size = bypass_4 ? _view__WIRE_3_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_source = bypass_4 ? _view__WIRE_3_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_3_tag = bypass_4 ? _view__WIRE_3_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_offset = bypass_4 ? _view__WIRE_3_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_put = bypass_4 ? _view__WIRE_3_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_3_io_allocate_bits_repeat_T = mshrs_3_io_allocate_bits_tag == _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_3_io_allocate_valid_T = sel_3 & will_reload_4; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_5 = _requests_io_valid[4]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_5 = _requests_io_valid[11]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_44 = b_pop_5; // @[Scheduler.scala:226:34, :229:78] wire c_pop_5 = _requests_io_valid[18]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_41 = lowerMatches1[4]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_42 = c_pop_5 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_43 = ~c_pop_5; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_45 = ~b_pop_5; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_46 = ~a_pop_5; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_47 = _bypassMatches_T_44 ? _bypassMatches_T_45 : _bypassMatches_T_46; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_48 = _bypassMatches_T_42 ? _bypassMatches_T_43 : _bypassMatches_T_47; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_5 = _bypassMatches_T_41 & _bypassMatches_T_48; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_5 = a_pop_5 | b_pop_5; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_5 = _may_pop_T_5 | c_pop_5; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_5 = _bypass_T_5 & bypassMatches_5; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_5 = may_pop_5 | bypass_5; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_5 = _mshrs_4_io_schedule_bits_reload & _will_reload_T_5; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_4_prio_0 = bypass_5 ? _view__WIRE_4_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_4_prio_1 = ~bypass_5 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_4_prio_2 = bypass_5 ? _view__WIRE_4_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_4_control = bypass_5 ? _view__WIRE_4_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_opcode = bypass_5 ? _view__WIRE_4_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_param = bypass_5 ? _view__WIRE_4_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_size = bypass_5 ? _view__WIRE_4_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_source = bypass_5 ? _view__WIRE_4_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_4_tag = bypass_5 ? _view__WIRE_4_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_offset = bypass_5 ? _view__WIRE_4_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_put = bypass_5 ? _view__WIRE_4_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_4_io_allocate_bits_repeat_T = mshrs_4_io_allocate_bits_tag == _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_4_io_allocate_valid_T = sel_4 & will_reload_5; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_6 = _requests_io_valid[5]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_6 = _requests_io_valid[12]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_52 = b_pop_6; // @[Scheduler.scala:226:34, :229:78] wire c_pop_6 = _requests_io_valid[19]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_49 = lowerMatches1[5]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_50 = c_pop_6 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_51 = ~c_pop_6; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_53 = ~b_pop_6; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_54 = ~a_pop_6; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_55 = _bypassMatches_T_52 ? _bypassMatches_T_53 : _bypassMatches_T_54; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_56 = _bypassMatches_T_50 ? _bypassMatches_T_51 : _bypassMatches_T_55; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_6 = _bypassMatches_T_49 & _bypassMatches_T_56; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_6 = a_pop_6 | b_pop_6; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_6 = _may_pop_T_6 | c_pop_6; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_6 = _bypass_T_6 & bypassMatches_6; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_6 = may_pop_6 | bypass_6; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_6 = _mshrs_5_io_schedule_bits_reload & _will_reload_T_6; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_5_prio_0 = bypass_6 ? _view__WIRE_5_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_5_prio_1 = ~bypass_6 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_5_prio_2 = bypass_6 ? _view__WIRE_5_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_5_control = bypass_6 ? _view__WIRE_5_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_opcode = bypass_6 ? _view__WIRE_5_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_param = bypass_6 ? _view__WIRE_5_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_size = bypass_6 ? _view__WIRE_5_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_source = bypass_6 ? _view__WIRE_5_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_5_tag = bypass_6 ? _view__WIRE_5_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_offset = bypass_6 ? _view__WIRE_5_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_put = bypass_6 ? _view__WIRE_5_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_5_io_allocate_bits_repeat_T = mshrs_5_io_allocate_bits_tag == _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :287:131, :289:74] wire _mshrs_5_io_allocate_valid_T = sel_5 & will_reload_6; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_7 = _requests_io_valid[6]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_7 = _requests_io_valid[13]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_60 = b_pop_7; // @[Scheduler.scala:226:34, :229:78] wire c_pop_7 = _requests_io_valid[20]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_57 = lowerMatches1[6]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_58 = c_pop_7 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_59 = ~c_pop_7; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_61 = ~b_pop_7; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_62 = ~a_pop_7; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_63 = _bypassMatches_T_60 ? _bypassMatches_T_61 : _bypassMatches_T_62; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_64 = _bypassMatches_T_58 ? _bypassMatches_T_59 : _bypassMatches_T_63; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_7 = _bypassMatches_T_57 & _bypassMatches_T_64; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_7 = a_pop_7 | b_pop_7; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_7 = _may_pop_T_7 | c_pop_7; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_7 = _bypass_T_7 & bypassMatches_7; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_7 = may_pop_7 | bypass_7; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_7 = _mshrs_6_io_schedule_bits_reload & _will_reload_T_7; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_6_prio_0 = bypass_7 ? _view__WIRE_6_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_6_prio_1 = ~bypass_7 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_6_prio_2 = bypass_7 ? _view__WIRE_6_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_6_control = bypass_7 ? _view__WIRE_6_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_opcode = bypass_7 ? _view__WIRE_6_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_param = bypass_7 ? _view__WIRE_6_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_size = bypass_7 ? _view__WIRE_6_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_source = bypass_7 ? _view__WIRE_6_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_6_tag = bypass_7 ? _view__WIRE_6_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_offset = bypass_7 ? _view__WIRE_6_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_put = bypass_7 ? _view__WIRE_6_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_6_io_allocate_bits_repeat_T = mshrs_6_io_allocate_bits_tag == _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :295:103, :297:73] wire _mshrs_6_io_allocate_valid_T = sel_6 & will_reload_7; // @[Scheduler.scala:223:28, :232:49, :236:32] wire [20:0] _prio_requests_T = ~_requests_io_valid; // @[Scheduler.scala:70:24, :240:25] wire [13:0] _prio_requests_T_1 = _requests_io_valid[20:7]; // @[Scheduler.scala:70:24, :240:65] wire [20:0] _prio_requests_T_2 = {_prio_requests_T[20:14], _prio_requests_T[13:0] | _prio_requests_T_1}; // @[Scheduler.scala:240:{25,44,65}] wire [6:0] _prio_requests_T_3 = _requests_io_valid[20:14]; // @[Scheduler.scala:70:24, :240:103] wire [20:0] _prio_requests_T_4 = {_prio_requests_T_2[20:7], _prio_requests_T_2[6:0] | _prio_requests_T_3}; // @[Scheduler.scala:240:{44,82,103}] wire [20:0] prio_requests = ~_prio_requests_T_4; // @[Scheduler.scala:240:{23,82}] wire [20:0] _pop_index_T = {pop_index_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :241:31] wire [20:0] _pop_index_T_1 = _pop_index_T & prio_requests; // @[Scheduler.scala:240:23, :241:{31,77}] wire [4:0] pop_index_hi_1 = _pop_index_T_1[20:16]; // @[OneHot.scala:30:18] wire [15:0] pop_index_lo = _pop_index_T_1[15:0]; // @[OneHot.scala:31:18] wire _pop_index_T_2 = |pop_index_hi_1; // @[OneHot.scala:30:18, :32:14] wire [15:0] _pop_index_T_3 = {11'h0, pop_index_hi_1} | pop_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] pop_index_hi_2 = _pop_index_T_3[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] pop_index_lo_1 = _pop_index_T_3[7:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_4 = |pop_index_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _pop_index_T_5 = pop_index_hi_2 | pop_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] pop_index_hi_3 = _pop_index_T_5[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] pop_index_lo_2 = _pop_index_T_5[3:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_6 = |pop_index_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _pop_index_T_7 = pop_index_hi_3 | pop_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] pop_index_hi_4 = _pop_index_T_7[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] pop_index_lo_3 = _pop_index_T_7[1:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_8 = |pop_index_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _pop_index_T_9 = pop_index_hi_4 | pop_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire _pop_index_T_10 = _pop_index_T_9[1]; // @[OneHot.scala:32:28] wire [1:0] _pop_index_T_11 = {_pop_index_T_8, _pop_index_T_10}; // @[OneHot.scala:32:{10,14}] wire [2:0] _pop_index_T_12 = {_pop_index_T_6, _pop_index_T_11}; // @[OneHot.scala:32:{10,14}] wire [3:0] _pop_index_T_13 = {_pop_index_T_4, _pop_index_T_12}; // @[OneHot.scala:32:{10,14}] wire [4:0] pop_index = {_pop_index_T_2, _pop_index_T_13}; // @[OneHot.scala:32:{10,14}] wire lb_tag_mismatch = scheduleTag != _requests_io_data_tag; // @[Mux.scala:30:73] wire mshr_uses_directory_assuming_no_bypass = _mshr_uses_directory_assuming_no_bypass_T & lb_tag_mismatch; // @[Scheduler.scala:246:37, :247:{64,75}] wire mshr_uses_directory_for_lb = will_pop & lb_tag_mismatch; // @[Scheduler.scala:215:45, :246:37, :248:45] wire [12:0] _mshr_uses_directory_T = bypass ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :163:21, :213:39, :249:63] wire _mshr_uses_directory_T_1 = scheduleTag != _mshr_uses_directory_T; // @[Mux.scala:30:73] wire mshr_uses_directory = will_reload & _mshr_uses_directory_T_1; // @[Scheduler.scala:214:37, :249:{41,56}] wire [1:0] mshr_validOH_lo_hi = {_mshrs_2_io_status_valid, _mshrs_1_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [2:0] mshr_validOH_lo = {mshr_validOH_lo_hi, _mshrs_0_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [1:0] mshr_validOH_hi_lo = {_mshrs_4_io_status_valid, _mshrs_3_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [1:0] mshr_validOH_hi_hi = {_mshrs_6_io_status_valid, _mshrs_5_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [3:0] mshr_validOH_hi = {mshr_validOH_hi_hi, mshr_validOH_hi_lo}; // @[Scheduler.scala:252:25] wire [6:0] mshr_validOH = {mshr_validOH_hi, mshr_validOH_lo}; // @[Scheduler.scala:252:25] wire [6:0] _mshr_free_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20] wire [6:0] _mshr_free_T_1 = _mshr_free_T & prioFilter; // @[Scheduler.scala:182:23, :253:{20,34}] wire mshr_free = |_mshr_free_T_1; // @[Scheduler.scala:253:{34,48}] wire bypassQueue = schedule_reload & bypassMatches; // @[Mux.scala:30:73] wire _request_alloc_cases_T = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16] wire _request_alloc_cases_T_1 = alloc & _request_alloc_cases_T; // @[Scheduler.scala:173:15, :258:{13,16}] wire _request_alloc_cases_T_2 = _request_alloc_cases_T_1 & mshr_free; // @[Scheduler.scala:253:48, :258:{13,56}] wire _request_alloc_cases_T_9 = _request_alloc_cases_T_2; // @[Scheduler.scala:258:{56,70}] wire _request_alloc_cases_T_3 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :259:16] wire _request_alloc_cases_T_5 = ~_mshrs_5_io_status_valid; // @[Scheduler.scala:71:46, :259:59] wire _request_alloc_cases_T_7 = ~_mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :259:87] wire _request_alloc_cases_T_10 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :260:16] wire _request_alloc_cases_T_11 = nestC & _request_alloc_cases_T_10; // @[Scheduler.scala:180:70, :260:{13,16}] wire _request_alloc_cases_T_12 = ~_mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :259:87, :260:59] wire _request_alloc_cases_T_13 = _request_alloc_cases_T_11 & _request_alloc_cases_T_12; // @[Scheduler.scala:260:{13,56,59}] wire request_alloc_cases = _request_alloc_cases_T_9 | _request_alloc_cases_T_13; // @[Scheduler.scala:258:70, :259:112, :260:56] wire _request_ready_T = bypassQueue | _requests_io_push_ready; // @[Scheduler.scala:70:24, :256:37, :261:66] wire _request_ready_T_1 = queue & _request_ready_T; // @[Scheduler.scala:185:63, :261:{50,66}] assign _request_ready_T_2 = request_alloc_cases | _request_ready_T_1; // @[Scheduler.scala:259:112, :261:{40,50}] assign request_ready = _request_ready_T_2; // @[Scheduler.scala:163:21, :261:40] wire alloc_uses_directory = request_valid & request_alloc_cases; // @[Scheduler.scala:163:21, :259:112, :262:44] wire _directory_io_read_valid_T = mshr_uses_directory | alloc_uses_directory; // @[Scheduler.scala:249:41, :262:44, :265:50] wire [9:0] _directory_io_read_bits_set_T = mshr_uses_directory_for_lb ? scheduleSet : request_bits_set; // @[Mux.scala:30:73] wire [12:0] _directory_io_read_bits_tag_T = mshr_uses_directory_for_lb ? _requests_io_data_tag : request_bits_tag; // @[Scheduler.scala:70:24, :163:21, :248:45, :267:36] wire _requests_io_push_valid_T_1 = ~bypassQueue; // @[Scheduler.scala:256:37, :270:55] wire _requests_io_push_valid_T_2 = _requests_io_push_valid_T & _requests_io_push_valid_T_1; // @[Scheduler.scala:270:{43,52,55}] wire [2:0] requests_io_push_bits_index_hi = _requests_io_push_bits_index_T[6:4]; // @[OneHot.scala:30:18] wire [3:0] requests_io_push_bits_index_lo = _requests_io_push_bits_index_T[3:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_1 = |requests_io_push_bits_index_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_2 = {1'h0, requests_io_push_bits_index_hi} | requests_io_push_bits_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_1 = _requests_io_push_bits_index_T_2[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_1 = _requests_io_push_bits_index_T_2[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_3 = |requests_io_push_bits_index_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_4 = requests_io_push_bits_index_hi_1 | requests_io_push_bits_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_5 = _requests_io_push_bits_index_T_4[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_6 = {_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_7 = {_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_6}; // @[OneHot.scala:32:{10,14}] wire [13:0] _requests_io_push_bits_index_T_8 = {lowerMatches1, 7'h0}; // @[Scheduler.scala:200:8, :275:30] wire [5:0] requests_io_push_bits_index_hi_2 = _requests_io_push_bits_index_T_8[13:8]; // @[OneHot.scala:30:18] wire [7:0] requests_io_push_bits_index_lo_2 = _requests_io_push_bits_index_T_8[7:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_9 = |requests_io_push_bits_index_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _requests_io_push_bits_index_T_10 = {2'h0, requests_io_push_bits_index_hi_2} | requests_io_push_bits_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] requests_io_push_bits_index_hi_3 = _requests_io_push_bits_index_T_10[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] requests_io_push_bits_index_lo_3 = _requests_io_push_bits_index_T_10[3:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_11 = |requests_io_push_bits_index_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_12 = requests_io_push_bits_index_hi_3 | requests_io_push_bits_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_4 = _requests_io_push_bits_index_T_12[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_4 = _requests_io_push_bits_index_T_12[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_13 = |requests_io_push_bits_index_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_14 = requests_io_push_bits_index_hi_4 | requests_io_push_bits_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_15 = _requests_io_push_bits_index_T_14[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_16 = {_requests_io_push_bits_index_T_13, _requests_io_push_bits_index_T_15}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_17 = {_requests_io_push_bits_index_T_11, _requests_io_push_bits_index_T_16}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_18 = {_requests_io_push_bits_index_T_9, _requests_io_push_bits_index_T_17}; // @[OneHot.scala:32:{10,14}] wire [20:0] _requests_io_push_bits_index_T_19 = {lowerMatches1, 14'h0}; // @[Scheduler.scala:200:8, :276:30] wire [4:0] requests_io_push_bits_index_hi_5 = _requests_io_push_bits_index_T_19[20:16]; // @[OneHot.scala:30:18] wire [15:0] requests_io_push_bits_index_lo_5 = _requests_io_push_bits_index_T_19[15:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_20 = |requests_io_push_bits_index_hi_5; // @[OneHot.scala:30:18, :32:14] wire [15:0] _requests_io_push_bits_index_T_21 = {11'h0, requests_io_push_bits_index_hi_5} | requests_io_push_bits_index_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] requests_io_push_bits_index_hi_6 = _requests_io_push_bits_index_T_21[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] requests_io_push_bits_index_lo_6 = _requests_io_push_bits_index_T_21[7:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_22 = |requests_io_push_bits_index_hi_6; // @[OneHot.scala:30:18, :32:14] wire [7:0] _requests_io_push_bits_index_T_23 = requests_io_push_bits_index_hi_6 | requests_io_push_bits_index_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] requests_io_push_bits_index_hi_7 = _requests_io_push_bits_index_T_23[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] requests_io_push_bits_index_lo_7 = _requests_io_push_bits_index_T_23[3:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_24 = |requests_io_push_bits_index_hi_7; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_25 = requests_io_push_bits_index_hi_7 | requests_io_push_bits_index_lo_7; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_8 = _requests_io_push_bits_index_T_25[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_8 = _requests_io_push_bits_index_T_25[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_26 = |requests_io_push_bits_index_hi_8; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_27 = requests_io_push_bits_index_hi_8 | requests_io_push_bits_index_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_28 = _requests_io_push_bits_index_T_27[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_29 = {_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_28}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_30 = {_requests_io_push_bits_index_T_24, _requests_io_push_bits_index_T_29}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_31 = {_requests_io_push_bits_index_T_22, _requests_io_push_bits_index_T_30}; // @[OneHot.scala:32:{10,14}] wire [4:0] _requests_io_push_bits_index_T_32 = {_requests_io_push_bits_index_T_20, _requests_io_push_bits_index_T_31}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_33 = request_bits_prio_0 ? _requests_io_push_bits_index_T_7 : 3'h0; // @[OneHot.scala:32:10] wire [4:0] _requests_io_push_bits_index_T_35 = request_bits_prio_2 ? _requests_io_push_bits_index_T_32 : 5'h0; // @[OneHot.scala:32:10] wire [3:0] _requests_io_push_bits_index_T_36 = {1'h0, _requests_io_push_bits_index_T_33}; // @[Mux.scala:30:73] wire [4:0] _requests_io_push_bits_index_T_37 = {1'h0, _requests_io_push_bits_index_T_36} | _requests_io_push_bits_index_T_35; // @[Mux.scala:30:73] wire [4:0] _requests_io_push_bits_index_WIRE = _requests_io_push_bits_index_T_37; // @[Mux.scala:30:73] wire [6:0] _mshr_insertOH_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:32] wire [7:0] _mshr_insertOH_T_1 = {_mshr_insertOH_T, 1'h0}; // @[package.scala:253:48] wire [6:0] _mshr_insertOH_T_2 = _mshr_insertOH_T_1[6:0]; // @[package.scala:253:{48,53}] wire [6:0] _mshr_insertOH_T_3 = _mshr_insertOH_T | _mshr_insertOH_T_2; // @[package.scala:253:{43,53}] wire [8:0] _mshr_insertOH_T_4 = {_mshr_insertOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [6:0] _mshr_insertOH_T_5 = _mshr_insertOH_T_4[6:0]; // @[package.scala:253:{48,53}] wire [6:0] _mshr_insertOH_T_6 = _mshr_insertOH_T_3 | _mshr_insertOH_T_5; // @[package.scala:253:{43,53}] wire [10:0] _mshr_insertOH_T_7 = {_mshr_insertOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [6:0] _mshr_insertOH_T_8 = _mshr_insertOH_T_7[6:0]; // @[package.scala:253:{48,53}] wire [6:0] _mshr_insertOH_T_9 = _mshr_insertOH_T_6 | _mshr_insertOH_T_8; // @[package.scala:253:{43,53}] wire [6:0] _mshr_insertOH_T_10 = _mshr_insertOH_T_9; // @[package.scala:253:43, :254:17] wire [7:0] _mshr_insertOH_T_11 = {_mshr_insertOH_T_10, 1'h0}; // @[package.scala:254:17] wire [7:0] _mshr_insertOH_T_12 = ~_mshr_insertOH_T_11; // @[Scheduler.scala:278:{23,47}] wire [6:0] _mshr_insertOH_T_13 = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:55] wire [7:0] _mshr_insertOH_T_14 = {1'h0, _mshr_insertOH_T_12[6:0] & _mshr_insertOH_T_13}; // @[Scheduler.scala:278:{23,53,55}] wire [7:0] mshr_insertOH = {1'h0, _mshr_insertOH_T_14[6:0] & prioFilter}; // @[Scheduler.scala:182:23, :278:{53,69}] wire _T_46 = request_valid & alloc; // @[Scheduler.scala:163:21, :173:15, :280:25] wire _T_25 = _T_46 & mshr_insertOH[0] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_0_io_allocate_bits_tag = _T_25 ? request_bits_tag : _view__T_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_29 = _T_46 & mshr_insertOH[1] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_1_io_allocate_bits_tag = _T_29 ? request_bits_tag : _view__T_1_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_33 = _T_46 & mshr_insertOH[2] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_2_io_allocate_bits_tag = _T_33 ? request_bits_tag : _view__T_2_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_37 = _T_46 & mshr_insertOH[3] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_3_io_allocate_bits_tag = _T_37 ? request_bits_tag : _view__T_3_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_41 = _T_46 & mshr_insertOH[4] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_4_io_allocate_bits_tag = _T_41 ? request_bits_tag : _view__T_4_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_45 = _T_46 & mshr_insertOH[5] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_5_io_allocate_bits_tag = _T_45 ? request_bits_tag : _view__T_5_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70, :287:131, :289:74] wire _T_65 = request_valid & nestC & ~_mshrs_6_io_status_valid & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:71:46, :163:21, :180:70, :193:33, :247:75, :258:16, :259:87, :295:{32,59}] wire _GEN_3 = _T_65 | _T_46 & mshr_insertOH[6] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:193:33, :236:25, :247:75, :258:16, :278:69, :279:18, :280:{25,34,39,83}, :281:27, :295:{32,59,103}, :296:30] assign mshrs_6_io_allocate_bits_tag = _GEN_3 ? request_bits_tag : _view__T_6_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :236:25, :280:83, :281:27, :282:70, :295:103, :296:30, :297:73]
Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn_13 : input clock : Clock input reset : Reset output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<4>(0hf)) when _T : connect doing_reset, UInt<1>(0h0) reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0)) node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0) wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect f2_entry, entries[_f2_entry_T_1] node _T_1 = eq(io.update_idx, io.f2_req_idx) node _T_2 = and(io.update_repair, _T_1) when _T_2 : connect f2_entry.s_cnt, io.update_meta.s_cnt else : node _T_3 = eq(io.update_idx, io.f2_req_idx) node _T_4 = and(io.update_mispredict, _T_3) when _T_4 : connect f2_entry.s_cnt, UInt<1>(0h0) reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock connect f3_entry, f2_entry reg f3_scnt_REG : UInt, clock connect f3_scnt_REG, io.f2_req_idx node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG) node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T) node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt) node _f3_tag_T = bits(io.f2_req_idx, 13, 4) reg f3_tag : UInt, clock connect f3_tag, _f3_tag_T connect io.f3_pred, io.f3_pred_in connect io.f3_meta.s_cnt, f3_scnt node _T_5 = eq(f3_entry.tag, f3_tag) when _T_5 : node _T_6 = eq(f3_scnt, f3_entry.p_cnt) node _T_7 = eq(f3_entry.conf, UInt<3>(0h7)) node _T_8 = and(_T_6, _T_7) when _T_8 : node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0)) connect io.f3_pred, _io_f3_pred_T reg f4_fire : UInt<1>, clock connect f4_fire, io.f3_req_fire reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock connect f4_entry, f3_entry reg f4_tag : UInt, clock connect f4_tag, f3_tag reg f4_scnt : UInt, clock connect f4_scnt, f3_scnt reg f4_idx_REG : UInt, clock connect f4_idx_REG, io.f2_req_idx reg f4_idx : UInt, clock connect f4_idx, f4_idx_REG when f4_fire : node _T_9 = eq(f4_entry.tag, f4_tag) when _T_9 : node _T_10 = eq(f4_scnt, f4_entry.p_cnt) node _T_11 = eq(f4_entry.conf, UInt<3>(0h7)) node _T_12 = and(_T_10, _T_11) when _T_12 : node _T_13 = or(f4_idx, UInt<4>(0h0)) node _T_14 = bits(_T_13, 3, 0) connect entries[_T_14].age, UInt<3>(0h7) node _T_15 = or(f4_idx, UInt<4>(0h0)) node _T_16 = bits(_T_15, 3, 0) connect entries[_T_16].s_cnt, UInt<1>(0h0) else : node _T_17 = or(f4_idx, UInt<4>(0h0)) node _T_18 = bits(_T_17, 3, 0) node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1)) node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1) connect entries[_T_18].s_cnt, _entries_s_cnt_T_1 node _T_19 = or(f4_idx, UInt<4>(0h0)) node _T_20 = bits(_T_19, 3, 0) node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7)) node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1)) node _entries_age_T_2 = tail(_entries_age_T_1, 1) node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2) connect entries[_T_20].age, _entries_age_T_3 node _entry_T = or(io.update_idx, UInt<4>(0h0)) node _entry_T_1 = bits(_entry_T, 3, 0) node tag = bits(io.update_idx, 13, 4) node tag_match = eq(entries[_entry_T_1].tag, tag) node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt) wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect wentry, entries[_entry_T_1] node _T_21 = eq(doing_reset, UInt<1>(0h0)) node _T_22 = and(io.update_mispredict, _T_21) when _T_22 : node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) node _T_24 = and(_T_23, tag_match) when _T_24 : connect wentry.s_cnt, UInt<1>(0h0) connect wentry.conf, UInt<1>(0h0) else : node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) node _T_26 = eq(tag_match, UInt<1>(0h0)) node _T_27 = and(_T_25, _T_26) when _T_27 : skip else : node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_29 = and(_T_28, tag_match) node _T_30 = and(_T_29, ctr_match) when _T_30 : node _wentry_conf_T = add(entries[_entry_T_1].conf, UInt<1>(0h1)) node _wentry_conf_T_1 = tail(_wentry_conf_T, 1) connect wentry.conf, _wentry_conf_T_1 connect wentry.s_cnt, UInt<1>(0h0) else : node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_32 = and(_T_31, tag_match) node _T_33 = eq(ctr_match, UInt<1>(0h0)) node _T_34 = and(_T_32, _T_33) when _T_34 : connect wentry.conf, UInt<1>(0h0) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt else : node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_36 = eq(tag_match, UInt<1>(0h0)) node _T_37 = and(_T_35, _T_36) node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0)) node _T_39 = and(_T_37, _T_38) when _T_39 : connect wentry.tag, tag connect wentry.conf, UInt<1>(0h1) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt else : node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_41 = eq(tag_match, UInt<1>(0h0)) node _T_42 = and(_T_40, _T_41) node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0)) node _T_44 = and(_T_42, _T_43) when _T_44 : node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1)) node _wentry_age_T_1 = tail(_wentry_age_T, 1) connect wentry.age, _wentry_age_T_1 else : node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_46 = and(_T_45, tag_match) node _T_47 = and(_T_46, ctr_match) when _T_47 : connect wentry.conf, UInt<1>(0h1) connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) else : node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_49 = and(_T_48, tag_match) node _T_50 = eq(ctr_match, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) when _T_51 : connect wentry.p_cnt, io.update_meta.s_cnt connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) else : node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_53 = eq(tag_match, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) when _T_54 : connect wentry.tag, tag connect wentry.conf, UInt<1>(0h1) connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt node _T_55 = or(io.update_idx, UInt<4>(0h0)) node _T_56 = bits(_T_55, 3, 0) connect entries[_T_56], wentry else : node _T_57 = eq(doing_reset, UInt<1>(0h0)) node _T_58 = and(io.update_repair, _T_57) when _T_58 : node _T_59 = eq(io.update_idx, f4_idx) node _T_60 = and(f4_fire, _T_59) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = and(tag_match, _T_61) when _T_62 : connect wentry.s_cnt, io.update_meta.s_cnt node _T_63 = or(io.update_idx, UInt<4>(0h0)) node _T_64 = bits(_T_63, 3, 0) connect entries[_T_64], wentry when doing_reset : wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect _entries_WIRE.s_cnt, UInt<10>(0h0) connect _entries_WIRE.p_cnt, UInt<10>(0h0) connect _entries_WIRE.age, UInt<3>(0h0) connect _entries_WIRE.conf, UInt<3>(0h0) connect _entries_WIRE.tag, UInt<10>(0h0) connect entries[reset_idx], _entries_WIRE
module LoopBranchPredictorColumn_13( // @[loop.scala:39:9] input clock, // @[loop.scala:39:9] input reset, // @[loop.scala:39:9] input io_f2_req_valid, // @[loop.scala:43:16] input [35:0] io_f2_req_idx, // @[loop.scala:43:16] input io_f3_req_fire, // @[loop.scala:43:16] input io_f3_pred_in, // @[loop.scala:43:16] output io_f3_pred, // @[loop.scala:43:16] output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16] input io_update_mispredict, // @[loop.scala:43:16] input io_update_repair, // @[loop.scala:43:16] input [35:0] io_update_idx, // @[loop.scala:43:16] input io_update_resolve_dir, // @[loop.scala:43:16] input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16] ); wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9] wire [35:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9] wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9] wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9] wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9] wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9] wire [35:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9] wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9] wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9] wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43] wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43] wire [35:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9] wire [9:0] f3_scnt; // @[loop.scala:73:23] wire [35:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9] wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9] wire io_f3_pred_0; // @[loop.scala:39:9] reg doing_reset; // @[loop.scala:59:30] reg [3:0] reset_idx; // @[loop.scala:60:28] wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28] wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28] reg [9:0] entries_0_tag; // @[loop.scala:65:22] reg [2:0] entries_0_conf; // @[loop.scala:65:22] reg [2:0] entries_0_age; // @[loop.scala:65:22] reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_tag; // @[loop.scala:65:22] reg [2:0] entries_1_conf; // @[loop.scala:65:22] reg [2:0] entries_1_age; // @[loop.scala:65:22] reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_tag; // @[loop.scala:65:22] reg [2:0] entries_2_conf; // @[loop.scala:65:22] reg [2:0] entries_2_age; // @[loop.scala:65:22] reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_tag; // @[loop.scala:65:22] reg [2:0] entries_3_conf; // @[loop.scala:65:22] reg [2:0] entries_3_age; // @[loop.scala:65:22] reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_tag; // @[loop.scala:65:22] reg [2:0] entries_4_conf; // @[loop.scala:65:22] reg [2:0] entries_4_age; // @[loop.scala:65:22] reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_tag; // @[loop.scala:65:22] reg [2:0] entries_5_conf; // @[loop.scala:65:22] reg [2:0] entries_5_age; // @[loop.scala:65:22] reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_tag; // @[loop.scala:65:22] reg [2:0] entries_6_conf; // @[loop.scala:65:22] reg [2:0] entries_6_age; // @[loop.scala:65:22] reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_tag; // @[loop.scala:65:22] reg [2:0] entries_7_conf; // @[loop.scala:65:22] reg [2:0] entries_7_age; // @[loop.scala:65:22] reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_tag; // @[loop.scala:65:22] reg [2:0] entries_8_conf; // @[loop.scala:65:22] reg [2:0] entries_8_age; // @[loop.scala:65:22] reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_tag; // @[loop.scala:65:22] reg [2:0] entries_9_conf; // @[loop.scala:65:22] reg [2:0] entries_9_age; // @[loop.scala:65:22] reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_tag; // @[loop.scala:65:22] reg [2:0] entries_10_conf; // @[loop.scala:65:22] reg [2:0] entries_10_age; // @[loop.scala:65:22] reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_tag; // @[loop.scala:65:22] reg [2:0] entries_11_conf; // @[loop.scala:65:22] reg [2:0] entries_11_age; // @[loop.scala:65:22] reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_tag; // @[loop.scala:65:22] reg [2:0] entries_12_conf; // @[loop.scala:65:22] reg [2:0] entries_12_age; // @[loop.scala:65:22] reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_tag; // @[loop.scala:65:22] reg [2:0] entries_13_conf; // @[loop.scala:65:22] reg [2:0] entries_13_age; // @[loop.scala:65:22] reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_tag; // @[loop.scala:65:22] reg [2:0] entries_14_conf; // @[loop.scala:65:22] reg [2:0] entries_14_age; // @[loop.scala:65:22] reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_tag; // @[loop.scala:65:22] reg [2:0] entries_15_conf; // @[loop.scala:65:22] reg [2:0] entries_15_age; // @[loop.scala:65:22] reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22] wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0]; wire [9:0] f2_entry_tag; // @[loop.scala:66:28] wire [2:0] f2_entry_conf; // @[loop.scala:66:28] wire [2:0] f2_entry_age; // @[loop.scala:66:28] wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28] wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28] wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28] assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28] assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28] assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28] assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28] wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45] assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22] reg [9:0] f3_entry_tag; // @[loop.scala:72:27] reg [2:0] f3_entry_conf; // @[loop.scala:72:27] reg [2:0] f3_entry_age; // @[loop.scala:72:27] reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27] reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27] reg [35:0] f3_scnt_REG; // @[loop.scala:73:69] wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}] wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}] assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}] assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23] wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41] reg [9:0] f3_tag; // @[loop.scala:76:27] wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23] assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}] reg f4_fire; // @[loop.scala:88:27] reg [9:0] f4_entry_tag; // @[loop.scala:89:27] reg [2:0] f4_entry_conf; // @[loop.scala:89:27] reg [2:0] f4_entry_age; // @[loop.scala:89:27] reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27] reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27] reg [9:0] f4_tag; // @[loop.scala:90:27] reg [9:0] f4_scnt; // @[loop.scala:91:27] reg [35:0] f4_idx_REG; // @[loop.scala:92:35] reg [35:0] f4_idx; // @[loop.scala:92:27] wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44] wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44] wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53] wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80] wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80] wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}] wire [3:0] _entry_T_1 = _entry_T[3:0]; wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28] wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31] wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33] wire [9:0] wentry_tag; // @[loop.scala:112:26] wire [2:0] wentry_conf; // @[loop.scala:112:26] wire [2:0] wentry_age; // @[loop.scala:112:26] wire [9:0] wentry_p_cnt; // @[loop.scala:112:26] wire [9:0] wentry_s_cnt; // @[loop.scala:112:26] wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}] wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}] wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}] wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}] wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1; // @[loop.scala:66:28, :102:80, :110:31, :126:36] wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:126:36] wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}] wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}] wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}] wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33] wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33] wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31] wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}] wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}] wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39] wire _GEN_4 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54] wire _GEN_5 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75] assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_5 | ~(_T_39 | ~(_T_44 | _GEN_4 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}] assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}] wire _GEN_6 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22] wire _GEN_7 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75] assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22] assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_7 | ~(_T_44 | _T_47 | ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22] wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35] wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}] assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_5 | _T_39 | ~(_T_44 | ~(_GEN_4 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22] wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}] wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68] always @(posedge clock) begin // @[loop.scala:39:9] if (reset) begin // @[loop.scala:39:9] doing_reset <= 1'h1; // @[loop.scala:59:30] reset_idx <= 4'h0; // @[loop.scala:60:28] end else begin // @[loop.scala:39:9] doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}] reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28] end if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_0_tag <= 10'h0; // @[loop.scala:65:22] entries_0_conf <= 3'h0; // @[loop.scala:65:22] entries_0_age <= 3'h0; // @[loop.scala:65:22] entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33] entries_0_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33] entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33] entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26] entries_1_tag <= 10'h0; // @[loop.scala:65:22] entries_1_conf <= 3'h0; // @[loop.scala:65:22] entries_1_age <= 3'h0; // @[loop.scala:65:22] entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80] entries_1_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}] entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80] entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_2_tag <= 10'h0; // @[loop.scala:65:22] entries_2_conf <= 3'h0; // @[loop.scala:65:22] entries_2_age <= 3'h0; // @[loop.scala:65:22] entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33] entries_2_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33] entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33] entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_3_tag <= 10'h0; // @[loop.scala:65:22] entries_3_conf <= 3'h0; // @[loop.scala:65:22] entries_3_age <= 3'h0; // @[loop.scala:65:22] entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33] entries_3_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33] entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33] entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_4_tag <= 10'h0; // @[loop.scala:65:22] entries_4_conf <= 3'h0; // @[loop.scala:65:22] entries_4_age <= 3'h0; // @[loop.scala:65:22] entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33] entries_4_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33] entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33] entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_5_tag <= 10'h0; // @[loop.scala:65:22] entries_5_conf <= 3'h0; // @[loop.scala:65:22] entries_5_age <= 3'h0; // @[loop.scala:65:22] entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33] entries_5_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33] entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33] entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_6_tag <= 10'h0; // @[loop.scala:65:22] entries_6_conf <= 3'h0; // @[loop.scala:65:22] entries_6_age <= 3'h0; // @[loop.scala:65:22] entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33] entries_6_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33] entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33] entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_7_tag <= 10'h0; // @[loop.scala:65:22] entries_7_conf <= 3'h0; // @[loop.scala:65:22] entries_7_age <= 3'h0; // @[loop.scala:65:22] entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33] entries_7_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33] entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33] entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_8_tag <= 10'h0; // @[loop.scala:65:22] entries_8_conf <= 3'h0; // @[loop.scala:65:22] entries_8_age <= 3'h0; // @[loop.scala:65:22] entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33] entries_8_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33] entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33] entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_9_tag <= 10'h0; // @[loop.scala:65:22] entries_9_conf <= 3'h0; // @[loop.scala:65:22] entries_9_age <= 3'h0; // @[loop.scala:65:22] entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33] entries_9_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33] entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33] entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_10_tag <= 10'h0; // @[loop.scala:65:22] entries_10_conf <= 3'h0; // @[loop.scala:65:22] entries_10_age <= 3'h0; // @[loop.scala:65:22] entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33] entries_10_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33] entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33] entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_11_tag <= 10'h0; // @[loop.scala:65:22] entries_11_conf <= 3'h0; // @[loop.scala:65:22] entries_11_age <= 3'h0; // @[loop.scala:65:22] entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33] entries_11_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33] entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33] entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_12_tag <= 10'h0; // @[loop.scala:65:22] entries_12_conf <= 3'h0; // @[loop.scala:65:22] entries_12_age <= 3'h0; // @[loop.scala:65:22] entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33] entries_12_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33] entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33] entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_13_tag <= 10'h0; // @[loop.scala:65:22] entries_13_conf <= 3'h0; // @[loop.scala:65:22] entries_13_age <= 3'h0; // @[loop.scala:65:22] entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33] entries_13_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33] entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33] entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_14_tag <= 10'h0; // @[loop.scala:65:22] entries_14_conf <= 3'h0; // @[loop.scala:65:22] entries_14_age <= 3'h0; // @[loop.scala:65:22] entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33] entries_14_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33] entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33] entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_15_tag <= 10'h0; // @[loop.scala:65:22] entries_15_conf <= 3'h0; // @[loop.scala:65:22] entries_15_age <= 3'h0; // @[loop.scala:65:22] entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33] entries_15_age <= 3'h7; // @[loop.scala:65:22] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33] entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33] entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27] f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27] f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27] f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27] f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27] f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69] f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}] f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27] f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27] f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27] f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27] f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27] f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27] f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27] f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27] f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35] f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}] always @(posedge) assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9] assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_12 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T
module MulAddRecFNToRaw_postMul_e8_s24_12( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61] wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35] wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17] wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_84 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg
module PE_84( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ListBuffer_QueuedRequest_q36_e28 : input clock : Clock input reset : Reset output io : { flip push : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<11>, offset : UInt<6>, put : UInt<6>}}}, valid : UInt<36>, flip pop : { valid : UInt<1>, bits : UInt<6>}, data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<11>, offset : UInt<6>, put : UInt<6>}} regreset valid : UInt<36>, clock, reset, UInt<36>(0h0) cmem head : UInt<5> [36] cmem tail : UInt<5> [36] regreset used : UInt<28>, clock, reset, UInt<28>(0h0) cmem next : UInt<5> [28] cmem data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<11>, offset : UInt<6>, put : UInt<6>} [28] node _freeOH_T = not(used) node _freeOH_T_1 = shl(_freeOH_T, 1) node _freeOH_T_2 = bits(_freeOH_T_1, 27, 0) node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2) node _freeOH_T_4 = shl(_freeOH_T_3, 2) node _freeOH_T_5 = bits(_freeOH_T_4, 27, 0) node _freeOH_T_6 = or(_freeOH_T_3, _freeOH_T_5) node _freeOH_T_7 = shl(_freeOH_T_6, 4) node _freeOH_T_8 = bits(_freeOH_T_7, 27, 0) node _freeOH_T_9 = or(_freeOH_T_6, _freeOH_T_8) node _freeOH_T_10 = shl(_freeOH_T_9, 8) node _freeOH_T_11 = bits(_freeOH_T_10, 27, 0) node _freeOH_T_12 = or(_freeOH_T_9, _freeOH_T_11) node _freeOH_T_13 = shl(_freeOH_T_12, 16) node _freeOH_T_14 = bits(_freeOH_T_13, 27, 0) node _freeOH_T_15 = or(_freeOH_T_12, _freeOH_T_14) node _freeOH_T_16 = bits(_freeOH_T_15, 27, 0) node _freeOH_T_17 = shl(_freeOH_T_16, 1) node _freeOH_T_18 = not(_freeOH_T_17) node _freeOH_T_19 = not(used) node freeOH = and(_freeOH_T_18, _freeOH_T_19) node freeIdx_hi = bits(freeOH, 28, 16) node freeIdx_lo = bits(freeOH, 15, 0) node _freeIdx_T = orr(freeIdx_hi) node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo) node freeIdx_hi_1 = bits(_freeIdx_T_1, 15, 8) node freeIdx_lo_1 = bits(_freeIdx_T_1, 7, 0) node _freeIdx_T_2 = orr(freeIdx_hi_1) node _freeIdx_T_3 = or(freeIdx_hi_1, freeIdx_lo_1) node freeIdx_hi_2 = bits(_freeIdx_T_3, 7, 4) node freeIdx_lo_2 = bits(_freeIdx_T_3, 3, 0) node _freeIdx_T_4 = orr(freeIdx_hi_2) node _freeIdx_T_5 = or(freeIdx_hi_2, freeIdx_lo_2) node freeIdx_hi_3 = bits(_freeIdx_T_5, 3, 2) node freeIdx_lo_3 = bits(_freeIdx_T_5, 1, 0) node _freeIdx_T_6 = orr(freeIdx_hi_3) node _freeIdx_T_7 = or(freeIdx_hi_3, freeIdx_lo_3) node _freeIdx_T_8 = bits(_freeIdx_T_7, 1, 1) node _freeIdx_T_9 = cat(_freeIdx_T_6, _freeIdx_T_8) node _freeIdx_T_10 = cat(_freeIdx_T_4, _freeIdx_T_9) node _freeIdx_T_11 = cat(_freeIdx_T_2, _freeIdx_T_10) node freeIdx = cat(_freeIdx_T, _freeIdx_T_11) wire valid_set : UInt<36> connect valid_set, UInt<36>(0h0) wire valid_clr : UInt<36> connect valid_clr, UInt<36>(0h0) wire used_set : UInt<28> connect used_set, UInt<28>(0h0) wire used_clr : UInt<28> connect used_clr, UInt<28>(0h0) read mport push_tail = tail[io.push.bits.index], clock node _push_valid_T = dshr(valid, io.push.bits.index) node push_valid = bits(_push_valid_T, 0, 0) node _io_push_ready_T = andr(used) node _io_push_ready_T_1 = eq(_io_push_ready_T, UInt<1>(0h0)) connect io.push.ready, _io_push_ready_T_1 node _T = and(io.push.ready, io.push.valid) when _T : node valid_set_shiftAmount = bits(io.push.bits.index, 5, 0) node _valid_set_T = dshl(UInt<1>(0h1), valid_set_shiftAmount) node _valid_set_T_1 = bits(_valid_set_T, 35, 0) connect valid_set, _valid_set_T_1 connect used_set, freeOH write mport MPORT = data[freeIdx], clock connect MPORT, io.push.bits.data when push_valid : write mport MPORT_1 = next[push_tail], clock connect MPORT_1, freeIdx else : write mport MPORT_2 = head[io.push.bits.index], clock connect MPORT_2, freeIdx write mport MPORT_3 = tail[io.push.bits.index], clock connect MPORT_3, freeIdx read mport pop_head = head[io.pop.bits], clock node _pop_valid_T = dshr(valid, io.pop.bits) node pop_valid = bits(_pop_valid_T, 0, 0) read mport io_data_MPORT = data[pop_head], clock connect io.data, io_data_MPORT connect io.valid, valid node _T_1 = eq(io.pop.valid, UInt<1>(0h0)) node _T_2 = dshr(io.valid, io.pop.bits) node _T_3 = bits(_T_2, 0, 0) node _T_4 = or(_T_1, _T_3) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ListBuffer.scala:86 assert (!io.pop.fire || (io.valid)(io.pop.bits))\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert when io.pop.valid : node used_clr_shiftAmount = bits(pop_head, 4, 0) node _used_clr_T = dshl(UInt<1>(0h1), used_clr_shiftAmount) node _used_clr_T_1 = bits(_used_clr_T, 27, 0) connect used_clr, _used_clr_T_1 read mport MPORT_4 = tail[io.pop.bits], clock node _T_8 = eq(pop_head, MPORT_4) when _T_8 : node valid_clr_shiftAmount = bits(io.pop.bits, 5, 0) node _valid_clr_T = dshl(UInt<1>(0h1), valid_clr_shiftAmount) node _valid_clr_T_1 = bits(_valid_clr_T, 35, 0) connect valid_clr, _valid_clr_T_1 node _T_9 = and(io.push.ready, io.push.valid) node _T_10 = and(_T_9, push_valid) node _T_11 = eq(push_tail, pop_head) node _T_12 = and(_T_10, _T_11) read mport MPORT_5 = next[pop_head], clock node _T_13 = mux(_T_12, freeIdx, MPORT_5) write mport MPORT_6 = head[io.pop.bits], clock connect MPORT_6, _T_13 node _T_14 = eq(io.pop.valid, UInt<1>(0h0)) node _T_15 = or(UInt<1>(0h1), _T_14) node _T_16 = or(_T_15, pop_valid) when _T_16 : node _used_T = not(used_clr) node _used_T_1 = and(used, _used_T) node _used_T_2 = or(_used_T_1, used_set) connect used, _used_T_2 node _valid_T = not(valid_clr) node _valid_T_1 = and(valid, _valid_T) node _valid_T_2 = or(_valid_T_1, valid_set) connect valid, _valid_T_2
module ListBuffer_QueuedRequest_q36_e28( // @[ListBuffer.scala:36:7] input clock, // @[ListBuffer.scala:36:7] input reset, // @[ListBuffer.scala:36:7] output io_push_ready, // @[ListBuffer.scala:39:14] input io_push_valid, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_index, // @[ListBuffer.scala:39:14] input io_push_bits_data_prio_0, // @[ListBuffer.scala:39:14] input io_push_bits_data_prio_2, // @[ListBuffer.scala:39:14] input io_push_bits_data_control, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_opcode, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_param, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_size, // @[ListBuffer.scala:39:14] input [6:0] io_push_bits_data_source, // @[ListBuffer.scala:39:14] input [10:0] io_push_bits_data_tag, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_data_offset, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_data_put, // @[ListBuffer.scala:39:14] output [35:0] io_valid, // @[ListBuffer.scala:39:14] input io_pop_valid, // @[ListBuffer.scala:39:14] input [5:0] io_pop_bits, // @[ListBuffer.scala:39:14] output io_data_prio_0, // @[ListBuffer.scala:39:14] output io_data_prio_1, // @[ListBuffer.scala:39:14] output io_data_prio_2, // @[ListBuffer.scala:39:14] output io_data_control, // @[ListBuffer.scala:39:14] output [2:0] io_data_opcode, // @[ListBuffer.scala:39:14] output [2:0] io_data_param, // @[ListBuffer.scala:39:14] output [2:0] io_data_size, // @[ListBuffer.scala:39:14] output [6:0] io_data_source, // @[ListBuffer.scala:39:14] output [10:0] io_data_tag, // @[ListBuffer.scala:39:14] output [5:0] io_data_offset, // @[ListBuffer.scala:39:14] output [5:0] io_data_put // @[ListBuffer.scala:39:14] ); wire [42:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18] wire [4:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18] wire [4:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18] wire [4:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18] wire [4:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18] reg [35:0] valid; // @[ListBuffer.scala:47:22] reg [27:0] used; // @[ListBuffer.scala:50:22] wire [27:0] _freeOH_T_19 = ~used; // @[ListBuffer.scala:50:22, :54:25] wire [26:0] _freeOH_T_3 = _freeOH_T_19[26:0] | {_freeOH_T_19[25:0], 1'h0}; // @[package.scala:253:{43,53}] wire [26:0] _freeOH_T_6 = _freeOH_T_3 | {_freeOH_T_3[24:0], 2'h0}; // @[package.scala:253:{43,53}] wire [26:0] _freeOH_T_9 = _freeOH_T_6 | {_freeOH_T_6[22:0], 4'h0}; // @[package.scala:253:{43,53}] wire [26:0] _freeOH_T_12 = _freeOH_T_9 | {_freeOH_T_9[18:0], 8'h0}; // @[package.scala:253:{43,53}] wire [27:0] _GEN = {~(_freeOH_T_12 | {_freeOH_T_12[10:0], 16'h0}), 1'h1} & _freeOH_T_19; // @[package.scala:253:{43,53}] wire [14:0] _freeIdx_T_1 = {4'h0, _GEN[27:17]} | _GEN[15:1]; // @[OneHot.scala:31:18, :32:28] wire [6:0] _freeIdx_T_3 = _freeIdx_T_1[14:8] | _freeIdx_T_1[6:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] _freeIdx_T_5 = _freeIdx_T_3[6:4] | _freeIdx_T_3[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [4:0] freeIdx = {|(_GEN[27:16]), |(_freeIdx_T_1[14:7]), |(_freeIdx_T_3[6:3]), |(_freeIdx_T_5[2:1]), _freeIdx_T_5[2] | _freeIdx_T_5[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire [35:0] _push_valid_T = valid >> io_push_bits_index; // @[ListBuffer.scala:47:22, :63:25] wire io_push_ready_0 = used != 28'hFFFFFFF; // @[ListBuffer.scala:50:22, :65:26] wire data_MPORT_en = io_push_ready_0 & io_push_valid; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module MulRawFN_35 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} inst mulFullRaw of MulFullRawFN_35 connect mulFullRaw.io.a.sig, io.a.sig connect mulFullRaw.io.a.sExp, io.a.sExp connect mulFullRaw.io.a.sign, io.a.sign connect mulFullRaw.io.a.isZero, io.a.isZero connect mulFullRaw.io.a.isInf, io.a.isInf connect mulFullRaw.io.a.isNaN, io.a.isNaN connect mulFullRaw.io.b.sig, io.b.sig connect mulFullRaw.io.b.sExp, io.b.sExp connect mulFullRaw.io.b.sign, io.b.sign connect mulFullRaw.io.b.isZero, io.b.isZero connect mulFullRaw.io.b.isInf, io.b.isInf connect mulFullRaw.io.b.isNaN, io.b.isNaN connect io.invalidExc, mulFullRaw.io.invalidExc connect io.rawOut, mulFullRaw.io.rawOut node _io_rawOut_sig_T = shr(mulFullRaw.io.rawOut.sig, 22) node _io_rawOut_sig_T_1 = bits(mulFullRaw.io.rawOut.sig, 21, 0) node _io_rawOut_sig_T_2 = orr(_io_rawOut_sig_T_1) node _io_rawOut_sig_T_3 = cat(_io_rawOut_sig_T, _io_rawOut_sig_T_2) connect io.rawOut.sig, _io_rawOut_sig_T_3
module MulRawFN_35( // @[MulRecFN.scala:75:7] input io_a_isNaN, // @[MulRecFN.scala:77:16] input io_a_isInf, // @[MulRecFN.scala:77:16] input io_a_isZero, // @[MulRecFN.scala:77:16] input io_a_sign, // @[MulRecFN.scala:77:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_a_sig, // @[MulRecFN.scala:77:16] input io_b_isNaN, // @[MulRecFN.scala:77:16] input io_b_isInf, // @[MulRecFN.scala:77:16] input io_b_isZero, // @[MulRecFN.scala:77:16] input io_b_sign, // @[MulRecFN.scala:77:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_b_sig, // @[MulRecFN.scala:77:16] output io_invalidExc, // @[MulRecFN.scala:77:16] output io_rawOut_isNaN, // @[MulRecFN.scala:77:16] output io_rawOut_isInf, // @[MulRecFN.scala:77:16] output io_rawOut_isZero, // @[MulRecFN.scala:77:16] output io_rawOut_sign, // @[MulRecFN.scala:77:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16] output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16] ); wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28] wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7] wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7] wire io_invalidExc_0; // @[MulRecFN.scala:75:7] wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15] wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37] wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}] assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10] MulFullRawFN_35 mulFullRaw ( // @[MulRecFN.scala:84:28] .io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7] .io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7] .io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7] .io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7] .io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7] .io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7] .io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7] .io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7] .io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7] .io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7] .io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7] .io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7] .io_invalidExc (io_invalidExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (_mulFullRaw_io_rawOut_sig) ); // @[MulRecFN.scala:84:28] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_61 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[12] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 node _source_ok_T_32 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[2]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[3]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[4]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[5]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[6]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[7]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[8]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[9]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[10]) node source_ok = or(_source_ok_T_41, _source_ok_WIRE[11]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = and(_T_11, _T_24) node _T_121 = and(_T_120, _T_37) node _T_122 = and(_T_121, _T_50) node _T_123 = and(_T_122, _T_63) node _T_124 = and(_T_123, _T_71) node _T_125 = and(_T_124, _T_79) node _T_126 = and(_T_125, _T_87) node _T_127 = and(_T_126, _T_95) node _T_128 = and(_T_127, _T_103) node _T_129 = and(_T_128, _T_111) node _T_130 = and(_T_129, _T_119) node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(_T_130, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_130, UInt<1>(0h1), "") : assert_1 node _T_134 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_134 : node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_136 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_139 = shr(io.in.a.bits.source, 2) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = leq(UInt<1>(0h0), uncommonBits_4) node _T_142 = and(_T_140, _T_141) node _T_143 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_144 = and(_T_142, _T_143) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_145 = shr(io.in.a.bits.source, 2) node _T_146 = eq(_T_145, UInt<1>(0h1)) node _T_147 = leq(UInt<1>(0h0), uncommonBits_5) node _T_148 = and(_T_146, _T_147) node _T_149 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_150 = and(_T_148, _T_149) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_151 = shr(io.in.a.bits.source, 2) node _T_152 = eq(_T_151, UInt<2>(0h2)) node _T_153 = leq(UInt<1>(0h0), uncommonBits_6) node _T_154 = and(_T_152, _T_153) node _T_155 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_156 = and(_T_154, _T_155) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_157 = shr(io.in.a.bits.source, 2) node _T_158 = eq(_T_157, UInt<2>(0h3)) node _T_159 = leq(UInt<1>(0h0), uncommonBits_7) node _T_160 = and(_T_158, _T_159) node _T_161 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_166 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_167 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_169 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_170 = or(_T_138, _T_144) node _T_171 = or(_T_170, _T_150) node _T_172 = or(_T_171, _T_156) node _T_173 = or(_T_172, _T_162) node _T_174 = or(_T_173, _T_163) node _T_175 = or(_T_174, _T_164) node _T_176 = or(_T_175, _T_165) node _T_177 = or(_T_176, _T_166) node _T_178 = or(_T_177, _T_167) node _T_179 = or(_T_178, _T_168) node _T_180 = or(_T_179, _T_169) node _T_181 = and(_T_137, _T_180) node _T_182 = or(UInt<1>(0h0), _T_181) node _T_183 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_184 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<13>(0h1000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = and(_T_183, _T_188) node _T_190 = or(UInt<1>(0h0), _T_189) node _T_191 = and(_T_182, _T_190) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_191, UInt<1>(0h1), "") : assert_2 node _T_195 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_196 = shr(io.in.a.bits.source, 2) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = leq(UInt<1>(0h0), uncommonBits_8) node _T_199 = and(_T_197, _T_198) node _T_200 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_201 = and(_T_199, _T_200) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_202 = shr(io.in.a.bits.source, 2) node _T_203 = eq(_T_202, UInt<1>(0h1)) node _T_204 = leq(UInt<1>(0h0), uncommonBits_9) node _T_205 = and(_T_203, _T_204) node _T_206 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_207 = and(_T_205, _T_206) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_208 = shr(io.in.a.bits.source, 2) node _T_209 = eq(_T_208, UInt<2>(0h2)) node _T_210 = leq(UInt<1>(0h0), uncommonBits_10) node _T_211 = and(_T_209, _T_210) node _T_212 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_213 = and(_T_211, _T_212) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_214 = shr(io.in.a.bits.source, 2) node _T_215 = eq(_T_214, UInt<2>(0h3)) node _T_216 = leq(UInt<1>(0h0), uncommonBits_11) node _T_217 = and(_T_215, _T_216) node _T_218 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_219 = and(_T_217, _T_218) node _T_220 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_221 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_222 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_223 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_225 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_226 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[12] connect _WIRE[0], _T_195 connect _WIRE[1], _T_201 connect _WIRE[2], _T_207 connect _WIRE[3], _T_213 connect _WIRE[4], _T_219 connect _WIRE[5], _T_220 connect _WIRE[6], _T_221 connect _WIRE[7], _T_222 connect _WIRE[8], _T_223 connect _WIRE[9], _T_224 connect _WIRE[10], _T_225 connect _WIRE[11], _T_226 node _T_227 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_228 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_229 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_230 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_231 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_232 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_233 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_234 = mux(_WIRE[5], _T_227, UInt<1>(0h0)) node _T_235 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_236 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_237 = mux(_WIRE[8], _T_228, UInt<1>(0h0)) node _T_238 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_239 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_240 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_241 = or(_T_229, _T_230) node _T_242 = or(_T_241, _T_231) node _T_243 = or(_T_242, _T_232) node _T_244 = or(_T_243, _T_233) node _T_245 = or(_T_244, _T_234) node _T_246 = or(_T_245, _T_235) node _T_247 = or(_T_246, _T_236) node _T_248 = or(_T_247, _T_237) node _T_249 = or(_T_248, _T_238) node _T_250 = or(_T_249, _T_239) node _T_251 = or(_T_250, _T_240) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_251 node _T_252 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_253 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_254 = and(_T_252, _T_253) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<13>(0h1000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = and(_T_255, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = and(_WIRE_1, _T_262) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_263, UInt<1>(0h1), "") : assert_3 node _T_267 = asUInt(reset) node _T_268 = eq(_T_267, UInt<1>(0h0)) when _T_268 : node _T_269 = eq(source_ok, UInt<1>(0h0)) when _T_269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_270 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_270, UInt<1>(0h1), "") : assert_5 node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(is_aligned, UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_277 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_278 = asUInt(reset) node _T_279 = eq(_T_278, UInt<1>(0h0)) when _T_279 : node _T_280 = eq(_T_277, UInt<1>(0h0)) when _T_280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_277, UInt<1>(0h1), "") : assert_7 node _T_281 = not(io.in.a.bits.mask) node _T_282 = eq(_T_281, UInt<1>(0h0)) node _T_283 = asUInt(reset) node _T_284 = eq(_T_283, UInt<1>(0h0)) when _T_284 : node _T_285 = eq(_T_282, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_282, UInt<1>(0h1), "") : assert_8 node _T_286 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_287 = asUInt(reset) node _T_288 = eq(_T_287, UInt<1>(0h0)) when _T_288 : node _T_289 = eq(_T_286, UInt<1>(0h0)) when _T_289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_286, UInt<1>(0h1), "") : assert_9 node _T_290 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_290 : node _T_291 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_292 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_295 = shr(io.in.a.bits.source, 2) node _T_296 = eq(_T_295, UInt<1>(0h0)) node _T_297 = leq(UInt<1>(0h0), uncommonBits_12) node _T_298 = and(_T_296, _T_297) node _T_299 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_300 = and(_T_298, _T_299) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<1>(0h1)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_13) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<2>(0h2)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_14) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_313 = shr(io.in.a.bits.source, 2) node _T_314 = eq(_T_313, UInt<2>(0h3)) node _T_315 = leq(UInt<1>(0h0), uncommonBits_15) node _T_316 = and(_T_314, _T_315) node _T_317 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_318 = and(_T_316, _T_317) node _T_319 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_321 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_322 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_323 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_324 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_325 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_326 = or(_T_294, _T_300) node _T_327 = or(_T_326, _T_306) node _T_328 = or(_T_327, _T_312) node _T_329 = or(_T_328, _T_318) node _T_330 = or(_T_329, _T_319) node _T_331 = or(_T_330, _T_320) node _T_332 = or(_T_331, _T_321) node _T_333 = or(_T_332, _T_322) node _T_334 = or(_T_333, _T_323) node _T_335 = or(_T_334, _T_324) node _T_336 = or(_T_335, _T_325) node _T_337 = and(_T_293, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<13>(0h1000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = and(_T_339, _T_344) node _T_346 = or(UInt<1>(0h0), _T_345) node _T_347 = and(_T_338, _T_346) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_347, UInt<1>(0h1), "") : assert_10 node _T_351 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_352 = shr(io.in.a.bits.source, 2) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = leq(UInt<1>(0h0), uncommonBits_16) node _T_355 = and(_T_353, _T_354) node _T_356 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_357 = and(_T_355, _T_356) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_358 = shr(io.in.a.bits.source, 2) node _T_359 = eq(_T_358, UInt<1>(0h1)) node _T_360 = leq(UInt<1>(0h0), uncommonBits_17) node _T_361 = and(_T_359, _T_360) node _T_362 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_363 = and(_T_361, _T_362) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_364 = shr(io.in.a.bits.source, 2) node _T_365 = eq(_T_364, UInt<2>(0h2)) node _T_366 = leq(UInt<1>(0h0), uncommonBits_18) node _T_367 = and(_T_365, _T_366) node _T_368 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_369 = and(_T_367, _T_368) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_370 = shr(io.in.a.bits.source, 2) node _T_371 = eq(_T_370, UInt<2>(0h3)) node _T_372 = leq(UInt<1>(0h0), uncommonBits_19) node _T_373 = and(_T_371, _T_372) node _T_374 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_375 = and(_T_373, _T_374) node _T_376 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_377 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_378 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_379 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_380 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_381 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_382 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[12] connect _WIRE_2[0], _T_351 connect _WIRE_2[1], _T_357 connect _WIRE_2[2], _T_363 connect _WIRE_2[3], _T_369 connect _WIRE_2[4], _T_375 connect _WIRE_2[5], _T_376 connect _WIRE_2[6], _T_377 connect _WIRE_2[7], _T_378 connect _WIRE_2[8], _T_379 connect _WIRE_2[9], _T_380 connect _WIRE_2[10], _T_381 connect _WIRE_2[11], _T_382 node _T_383 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_384 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_385 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_386 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_387 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_388 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_389 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_390 = mux(_WIRE_2[5], _T_383, UInt<1>(0h0)) node _T_391 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_392 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_393 = mux(_WIRE_2[8], _T_384, UInt<1>(0h0)) node _T_394 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_395 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_396 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_397 = or(_T_385, _T_386) node _T_398 = or(_T_397, _T_387) node _T_399 = or(_T_398, _T_388) node _T_400 = or(_T_399, _T_389) node _T_401 = or(_T_400, _T_390) node _T_402 = or(_T_401, _T_391) node _T_403 = or(_T_402, _T_392) node _T_404 = or(_T_403, _T_393) node _T_405 = or(_T_404, _T_394) node _T_406 = or(_T_405, _T_395) node _T_407 = or(_T_406, _T_396) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_407 node _T_408 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_409 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_410 = and(_T_408, _T_409) node _T_411 = or(UInt<1>(0h0), _T_410) node _T_412 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_413 = cvt(_T_412) node _T_414 = and(_T_413, asSInt(UInt<13>(0h1000))) node _T_415 = asSInt(_T_414) node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0))) node _T_417 = and(_T_411, _T_416) node _T_418 = or(UInt<1>(0h0), _T_417) node _T_419 = and(_WIRE_3, _T_418) node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(_T_419, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_419, UInt<1>(0h1), "") : assert_11 node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(source_ok, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_426 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_426, UInt<1>(0h1), "") : assert_13 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(is_aligned, UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_433 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_433, UInt<1>(0h1), "") : assert_15 node _T_437 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_T_437, UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_437, UInt<1>(0h1), "") : assert_16 node _T_441 = not(io.in.a.bits.mask) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_442, UInt<1>(0h1), "") : assert_17 node _T_446 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_446, UInt<1>(0h1), "") : assert_18 node _T_450 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_450 : node _T_451 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_452 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_453 = and(_T_451, _T_452) node _T_454 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_455 = shr(io.in.a.bits.source, 2) node _T_456 = eq(_T_455, UInt<1>(0h0)) node _T_457 = leq(UInt<1>(0h0), uncommonBits_20) node _T_458 = and(_T_456, _T_457) node _T_459 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_460 = and(_T_458, _T_459) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_461 = shr(io.in.a.bits.source, 2) node _T_462 = eq(_T_461, UInt<1>(0h1)) node _T_463 = leq(UInt<1>(0h0), uncommonBits_21) node _T_464 = and(_T_462, _T_463) node _T_465 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_466 = and(_T_464, _T_465) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_467 = shr(io.in.a.bits.source, 2) node _T_468 = eq(_T_467, UInt<2>(0h2)) node _T_469 = leq(UInt<1>(0h0), uncommonBits_22) node _T_470 = and(_T_468, _T_469) node _T_471 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_472 = and(_T_470, _T_471) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_473 = shr(io.in.a.bits.source, 2) node _T_474 = eq(_T_473, UInt<2>(0h3)) node _T_475 = leq(UInt<1>(0h0), uncommonBits_23) node _T_476 = and(_T_474, _T_475) node _T_477 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_478 = and(_T_476, _T_477) node _T_479 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_480 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_482 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_483 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_484 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_485 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_486 = or(_T_454, _T_460) node _T_487 = or(_T_486, _T_466) node _T_488 = or(_T_487, _T_472) node _T_489 = or(_T_488, _T_478) node _T_490 = or(_T_489, _T_479) node _T_491 = or(_T_490, _T_480) node _T_492 = or(_T_491, _T_481) node _T_493 = or(_T_492, _T_482) node _T_494 = or(_T_493, _T_483) node _T_495 = or(_T_494, _T_484) node _T_496 = or(_T_495, _T_485) node _T_497 = and(_T_453, _T_496) node _T_498 = or(UInt<1>(0h0), _T_497) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_498, UInt<1>(0h1), "") : assert_19 node _T_502 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_503 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_504 = and(_T_502, _T_503) node _T_505 = or(UInt<1>(0h0), _T_504) node _T_506 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<13>(0h1000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = and(_T_505, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_512, UInt<1>(0h1), "") : assert_20 node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(source_ok, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(is_aligned, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_522, UInt<1>(0h1), "") : assert_23 node _T_526 = eq(io.in.a.bits.mask, mask) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_526, UInt<1>(0h1), "") : assert_24 node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_530, UInt<1>(0h1), "") : assert_25 node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_534 : node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_537 = and(_T_535, _T_536) node _T_538 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_539 = shr(io.in.a.bits.source, 2) node _T_540 = eq(_T_539, UInt<1>(0h0)) node _T_541 = leq(UInt<1>(0h0), uncommonBits_24) node _T_542 = and(_T_540, _T_541) node _T_543 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_544 = and(_T_542, _T_543) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_545 = shr(io.in.a.bits.source, 2) node _T_546 = eq(_T_545, UInt<1>(0h1)) node _T_547 = leq(UInt<1>(0h0), uncommonBits_25) node _T_548 = and(_T_546, _T_547) node _T_549 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_550 = and(_T_548, _T_549) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_551 = shr(io.in.a.bits.source, 2) node _T_552 = eq(_T_551, UInt<2>(0h2)) node _T_553 = leq(UInt<1>(0h0), uncommonBits_26) node _T_554 = and(_T_552, _T_553) node _T_555 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_556 = and(_T_554, _T_555) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_557 = shr(io.in.a.bits.source, 2) node _T_558 = eq(_T_557, UInt<2>(0h3)) node _T_559 = leq(UInt<1>(0h0), uncommonBits_27) node _T_560 = and(_T_558, _T_559) node _T_561 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_562 = and(_T_560, _T_561) node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_566 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_567 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_569 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_570 = or(_T_538, _T_544) node _T_571 = or(_T_570, _T_550) node _T_572 = or(_T_571, _T_556) node _T_573 = or(_T_572, _T_562) node _T_574 = or(_T_573, _T_563) node _T_575 = or(_T_574, _T_564) node _T_576 = or(_T_575, _T_565) node _T_577 = or(_T_576, _T_566) node _T_578 = or(_T_577, _T_567) node _T_579 = or(_T_578, _T_568) node _T_580 = or(_T_579, _T_569) node _T_581 = and(_T_537, _T_580) node _T_582 = or(UInt<1>(0h0), _T_581) node _T_583 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_584 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_585 = and(_T_583, _T_584) node _T_586 = or(UInt<1>(0h0), _T_585) node _T_587 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_588 = cvt(_T_587) node _T_589 = and(_T_588, asSInt(UInt<13>(0h1000))) node _T_590 = asSInt(_T_589) node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0))) node _T_592 = and(_T_586, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = and(_T_582, _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_594, UInt<1>(0h1), "") : assert_26 node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(source_ok, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_601 = asUInt(reset) node _T_602 = eq(_T_601, UInt<1>(0h0)) when _T_602 : node _T_603 = eq(is_aligned, UInt<1>(0h0)) when _T_603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_604 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(_T_604, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_604, UInt<1>(0h1), "") : assert_29 node _T_608 = eq(io.in.a.bits.mask, mask) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_608, UInt<1>(0h1), "") : assert_30 node _T_612 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_612 : node _T_613 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_614 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_615 = and(_T_613, _T_614) node _T_616 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_617 = shr(io.in.a.bits.source, 2) node _T_618 = eq(_T_617, UInt<1>(0h0)) node _T_619 = leq(UInt<1>(0h0), uncommonBits_28) node _T_620 = and(_T_618, _T_619) node _T_621 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_622 = and(_T_620, _T_621) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_623 = shr(io.in.a.bits.source, 2) node _T_624 = eq(_T_623, UInt<1>(0h1)) node _T_625 = leq(UInt<1>(0h0), uncommonBits_29) node _T_626 = and(_T_624, _T_625) node _T_627 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_628 = and(_T_626, _T_627) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_629 = shr(io.in.a.bits.source, 2) node _T_630 = eq(_T_629, UInt<2>(0h2)) node _T_631 = leq(UInt<1>(0h0), uncommonBits_30) node _T_632 = and(_T_630, _T_631) node _T_633 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_634 = and(_T_632, _T_633) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_635 = shr(io.in.a.bits.source, 2) node _T_636 = eq(_T_635, UInt<2>(0h3)) node _T_637 = leq(UInt<1>(0h0), uncommonBits_31) node _T_638 = and(_T_636, _T_637) node _T_639 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_640 = and(_T_638, _T_639) node _T_641 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_642 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_643 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_616, _T_622) node _T_649 = or(_T_648, _T_628) node _T_650 = or(_T_649, _T_634) node _T_651 = or(_T_650, _T_640) node _T_652 = or(_T_651, _T_641) node _T_653 = or(_T_652, _T_642) node _T_654 = or(_T_653, _T_643) node _T_655 = or(_T_654, _T_644) node _T_656 = or(_T_655, _T_645) node _T_657 = or(_T_656, _T_646) node _T_658 = or(_T_657, _T_647) node _T_659 = and(_T_615, _T_658) node _T_660 = or(UInt<1>(0h0), _T_659) node _T_661 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_662 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_663 = and(_T_661, _T_662) node _T_664 = or(UInt<1>(0h0), _T_663) node _T_665 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<13>(0h1000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = and(_T_664, _T_669) node _T_671 = or(UInt<1>(0h0), _T_670) node _T_672 = and(_T_660, _T_671) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_672, UInt<1>(0h1), "") : assert_31 node _T_676 = asUInt(reset) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(source_ok, UInt<1>(0h0)) when _T_678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(is_aligned, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_682 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_T_682, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_682, UInt<1>(0h1), "") : assert_34 node _T_686 = not(mask) node _T_687 = and(io.in.a.bits.mask, _T_686) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_688, UInt<1>(0h1), "") : assert_35 node _T_692 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_692 : node _T_693 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_694 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_695 = and(_T_693, _T_694) node _T_696 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_697 = shr(io.in.a.bits.source, 2) node _T_698 = eq(_T_697, UInt<1>(0h0)) node _T_699 = leq(UInt<1>(0h0), uncommonBits_32) node _T_700 = and(_T_698, _T_699) node _T_701 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_702 = and(_T_700, _T_701) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_703 = shr(io.in.a.bits.source, 2) node _T_704 = eq(_T_703, UInt<1>(0h1)) node _T_705 = leq(UInt<1>(0h0), uncommonBits_33) node _T_706 = and(_T_704, _T_705) node _T_707 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_708 = and(_T_706, _T_707) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_709 = shr(io.in.a.bits.source, 2) node _T_710 = eq(_T_709, UInt<2>(0h2)) node _T_711 = leq(UInt<1>(0h0), uncommonBits_34) node _T_712 = and(_T_710, _T_711) node _T_713 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_714 = and(_T_712, _T_713) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_715 = shr(io.in.a.bits.source, 2) node _T_716 = eq(_T_715, UInt<2>(0h3)) node _T_717 = leq(UInt<1>(0h0), uncommonBits_35) node _T_718 = and(_T_716, _T_717) node _T_719 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_720 = and(_T_718, _T_719) node _T_721 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_722 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_723 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_724 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_725 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_726 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_727 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_728 = or(_T_696, _T_702) node _T_729 = or(_T_728, _T_708) node _T_730 = or(_T_729, _T_714) node _T_731 = or(_T_730, _T_720) node _T_732 = or(_T_731, _T_721) node _T_733 = or(_T_732, _T_722) node _T_734 = or(_T_733, _T_723) node _T_735 = or(_T_734, _T_724) node _T_736 = or(_T_735, _T_725) node _T_737 = or(_T_736, _T_726) node _T_738 = or(_T_737, _T_727) node _T_739 = and(_T_695, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_742 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_743 = cvt(_T_742) node _T_744 = and(_T_743, asSInt(UInt<13>(0h1000))) node _T_745 = asSInt(_T_744) node _T_746 = eq(_T_745, asSInt(UInt<1>(0h0))) node _T_747 = and(_T_741, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = and(_T_740, _T_748) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_749, UInt<1>(0h1), "") : assert_36 node _T_753 = asUInt(reset) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : node _T_755 = eq(source_ok, UInt<1>(0h0)) when _T_755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(is_aligned, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_759 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_759, UInt<1>(0h1), "") : assert_39 node _T_763 = eq(io.in.a.bits.mask, mask) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_763, UInt<1>(0h1), "") : assert_40 node _T_767 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_767 : node _T_768 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_769 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_770 = and(_T_768, _T_769) node _T_771 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<1>(0h0)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_36) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_778 = shr(io.in.a.bits.source, 2) node _T_779 = eq(_T_778, UInt<1>(0h1)) node _T_780 = leq(UInt<1>(0h0), uncommonBits_37) node _T_781 = and(_T_779, _T_780) node _T_782 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_783 = and(_T_781, _T_782) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_784 = shr(io.in.a.bits.source, 2) node _T_785 = eq(_T_784, UInt<2>(0h2)) node _T_786 = leq(UInt<1>(0h0), uncommonBits_38) node _T_787 = and(_T_785, _T_786) node _T_788 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_789 = and(_T_787, _T_788) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_790 = shr(io.in.a.bits.source, 2) node _T_791 = eq(_T_790, UInt<2>(0h3)) node _T_792 = leq(UInt<1>(0h0), uncommonBits_39) node _T_793 = and(_T_791, _T_792) node _T_794 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_795 = and(_T_793, _T_794) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_802 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_803 = or(_T_771, _T_777) node _T_804 = or(_T_803, _T_783) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_795) node _T_807 = or(_T_806, _T_796) node _T_808 = or(_T_807, _T_797) node _T_809 = or(_T_808, _T_798) node _T_810 = or(_T_809, _T_799) node _T_811 = or(_T_810, _T_800) node _T_812 = or(_T_811, _T_801) node _T_813 = or(_T_812, _T_802) node _T_814 = and(_T_770, _T_813) node _T_815 = or(UInt<1>(0h0), _T_814) node _T_816 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_817 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_818 = cvt(_T_817) node _T_819 = and(_T_818, asSInt(UInt<13>(0h1000))) node _T_820 = asSInt(_T_819) node _T_821 = eq(_T_820, asSInt(UInt<1>(0h0))) node _T_822 = and(_T_816, _T_821) node _T_823 = or(UInt<1>(0h0), _T_822) node _T_824 = and(_T_815, _T_823) node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(_T_824, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_824, UInt<1>(0h1), "") : assert_41 node _T_828 = asUInt(reset) node _T_829 = eq(_T_828, UInt<1>(0h0)) when _T_829 : node _T_830 = eq(source_ok, UInt<1>(0h0)) when _T_830 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(is_aligned, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_834 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_834, UInt<1>(0h1), "") : assert_44 node _T_838 = eq(io.in.a.bits.mask, mask) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_838, UInt<1>(0h1), "") : assert_45 node _T_842 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_842 : node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_847 = shr(io.in.a.bits.source, 2) node _T_848 = eq(_T_847, UInt<1>(0h0)) node _T_849 = leq(UInt<1>(0h0), uncommonBits_40) node _T_850 = and(_T_848, _T_849) node _T_851 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_852 = and(_T_850, _T_851) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<1>(0h1)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_41) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_859 = shr(io.in.a.bits.source, 2) node _T_860 = eq(_T_859, UInt<2>(0h2)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_42) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_865 = shr(io.in.a.bits.source, 2) node _T_866 = eq(_T_865, UInt<2>(0h3)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_43) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_870 = and(_T_868, _T_869) node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_872 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_873 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_874 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_875 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_876 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_877 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_878 = or(_T_846, _T_852) node _T_879 = or(_T_878, _T_858) node _T_880 = or(_T_879, _T_864) node _T_881 = or(_T_880, _T_870) node _T_882 = or(_T_881, _T_871) node _T_883 = or(_T_882, _T_872) node _T_884 = or(_T_883, _T_873) node _T_885 = or(_T_884, _T_874) node _T_886 = or(_T_885, _T_875) node _T_887 = or(_T_886, _T_876) node _T_888 = or(_T_887, _T_877) node _T_889 = and(_T_845, _T_888) node _T_890 = or(UInt<1>(0h0), _T_889) node _T_891 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_892 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), _T_897) node _T_899 = and(_T_890, _T_898) node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(_T_899, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_899, UInt<1>(0h1), "") : assert_46 node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(source_ok, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(is_aligned, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_909 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(_T_909, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_909, UInt<1>(0h1), "") : assert_49 node _T_913 = eq(io.in.a.bits.mask, mask) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_913, UInt<1>(0h1), "") : assert_50 node _T_917 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_917, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_921 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_921, UInt<1>(0h1), "") : assert_52 node _source_ok_T_42 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h0)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<1>(0h1)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h2)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_61 = shr(io.in.d.bits.source, 2) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<2>(0h3)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_68 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_69 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[12] connect _source_ok_WIRE_1[0], _source_ok_T_42 connect _source_ok_WIRE_1[1], _source_ok_T_48 connect _source_ok_WIRE_1[2], _source_ok_T_54 connect _source_ok_WIRE_1[3], _source_ok_T_60 connect _source_ok_WIRE_1[4], _source_ok_T_66 connect _source_ok_WIRE_1[5], _source_ok_T_67 connect _source_ok_WIRE_1[6], _source_ok_T_68 connect _source_ok_WIRE_1[7], _source_ok_T_69 connect _source_ok_WIRE_1[8], _source_ok_T_70 connect _source_ok_WIRE_1[9], _source_ok_T_71 connect _source_ok_WIRE_1[10], _source_ok_T_72 connect _source_ok_WIRE_1[11], _source_ok_T_73 node _source_ok_T_74 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[2]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[3]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[4]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[5]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[6]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[7]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[8]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[9]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[10]) node source_ok_1 = or(_source_ok_T_83, _source_ok_WIRE_1[11]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_925 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_925 : node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(source_ok_1, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_929 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_929, UInt<1>(0h1), "") : assert_54 node _T_933 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_933, UInt<1>(0h1), "") : assert_55 node _T_937 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_937, UInt<1>(0h1), "") : assert_56 node _T_941 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_941, UInt<1>(0h1), "") : assert_57 node _T_945 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_945 : node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok_1, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(sink_ok, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_952 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_952, UInt<1>(0h1), "") : assert_60 node _T_956 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_956, UInt<1>(0h1), "") : assert_61 node _T_960 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_960, UInt<1>(0h1), "") : assert_62 node _T_964 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_964, UInt<1>(0h1), "") : assert_63 node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_969, UInt<1>(0h1), "") : assert_64 node _T_973 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_973 : node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok_1, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(sink_ok, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_980 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_980, UInt<1>(0h1), "") : assert_67 node _T_984 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_984, UInt<1>(0h1), "") : assert_68 node _T_988 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_988, UInt<1>(0h1), "") : assert_69 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(_T_992, io.in.d.bits.corrupt) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_993, UInt<1>(0h1), "") : assert_70 node _T_997 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_998 = or(UInt<1>(0h0), _T_997) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_998, UInt<1>(0h1), "") : assert_71 node _T_1002 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1002 : node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(source_ok_1, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1006 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_73 node _T_1010 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_74 node _T_1014 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1015 = or(UInt<1>(0h0), _T_1014) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_75 node _T_1019 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1019 : node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(source_ok_1, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1023 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_77 node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1028 = or(_T_1027, io.in.d.bits.corrupt) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_78 node _T_1032 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1033 = or(UInt<1>(0h0), _T_1032) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_79 node _T_1037 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1037 : node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(source_ok_1, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_81 node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_82 node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1050 = or(UInt<1>(0h0), _T_1049) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1054 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1058 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1062 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1066 = eq(a_first, UInt<1>(0h0)) node _T_1067 = and(io.in.a.valid, _T_1066) when _T_1067 : node _T_1068 = eq(io.in.a.bits.opcode, opcode) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_87 node _T_1072 = eq(io.in.a.bits.param, param) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_88 node _T_1076 = eq(io.in.a.bits.size, size) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_89 node _T_1080 = eq(io.in.a.bits.source, source) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_90 node _T_1084 = eq(io.in.a.bits.address, address) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_91 node _T_1088 = and(io.in.a.ready, io.in.a.valid) node _T_1089 = and(_T_1088, a_first) when _T_1089 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1090 = eq(d_first, UInt<1>(0h0)) node _T_1091 = and(io.in.d.valid, _T_1090) when _T_1091 : node _T_1092 = eq(io.in.d.bits.opcode, opcode_1) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_92 node _T_1096 = eq(io.in.d.bits.param, param_1) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_93 node _T_1100 = eq(io.in.d.bits.size, size_1) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_94 node _T_1104 = eq(io.in.d.bits.source, source_1) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_95 node _T_1108 = eq(io.in.d.bits.sink, sink) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_96 node _T_1112 = eq(io.in.d.bits.denied, denied) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_97 node _T_1116 = and(io.in.d.ready, io.in.d.valid) node _T_1117 = and(_T_1116, d_first) when _T_1117 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1118 = and(io.in.a.valid, a_first_1) node _T_1119 = and(_T_1118, UInt<1>(0h1)) when _T_1119 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1120 = and(io.in.a.ready, io.in.a.valid) node _T_1121 = and(_T_1120, a_first_1) node _T_1122 = and(_T_1121, UInt<1>(0h1)) when _T_1122 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1123 = dshr(inflight, io.in.a.bits.source) node _T_1124 = bits(_T_1123, 0, 0) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1129 = and(io.in.d.valid, d_first_1) node _T_1130 = and(_T_1129, UInt<1>(0h1)) node _T_1131 = eq(d_release_ack, UInt<1>(0h0)) node _T_1132 = and(_T_1130, _T_1131) when _T_1132 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1133 = and(io.in.d.ready, io.in.d.valid) node _T_1134 = and(_T_1133, d_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) node _T_1136 = eq(d_release_ack, UInt<1>(0h0)) node _T_1137 = and(_T_1135, _T_1136) when _T_1137 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1138 = and(io.in.d.valid, d_first_1) node _T_1139 = and(_T_1138, UInt<1>(0h1)) node _T_1140 = eq(d_release_ack, UInt<1>(0h0)) node _T_1141 = and(_T_1139, _T_1140) when _T_1141 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1142 = dshr(inflight, io.in.d.bits.source) node _T_1143 = bits(_T_1142, 0, 0) node _T_1144 = or(_T_1143, same_cycle_resp) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1148 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1149 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1150 = or(_T_1148, _T_1149) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_100 node _T_1154 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_101 else : node _T_1158 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1159 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1160 = or(_T_1158, _T_1159) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_102 node _T_1164 = eq(io.in.d.bits.size, a_size_lookup) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_103 node _T_1168 = and(io.in.d.valid, d_first_1) node _T_1169 = and(_T_1168, a_first_1) node _T_1170 = and(_T_1169, io.in.a.valid) node _T_1171 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1172 = and(_T_1170, _T_1171) node _T_1173 = eq(d_release_ack, UInt<1>(0h0)) node _T_1174 = and(_T_1172, _T_1173) when _T_1174 : node _T_1175 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1176 = or(_T_1175, io.in.a.ready) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_126 node _T_1180 = orr(inflight) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) node _T_1182 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1183 = or(_T_1181, _T_1182) node _T_1184 = lt(watchdog, plusarg_reader.out) node _T_1185 = or(_T_1183, _T_1184) node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(_T_1185, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1185, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1189 = and(io.in.a.ready, io.in.a.valid) node _T_1190 = and(io.in.d.ready, io.in.d.valid) node _T_1191 = or(_T_1189, _T_1190) when _T_1191 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1192 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1193 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1194 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1195 = and(_T_1193, _T_1194) node _T_1196 = and(_T_1192, _T_1195) when _T_1196 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1197 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1198 = and(_T_1197, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1199 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1200 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = and(_T_1198, _T_1201) when _T_1202 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1203 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1209 = and(io.in.d.valid, d_first_2) node _T_1210 = and(_T_1209, UInt<1>(0h1)) node _T_1211 = and(_T_1210, d_release_ack_1) when _T_1211 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1212 = and(io.in.d.ready, io.in.d.valid) node _T_1213 = and(_T_1212, d_first_2) node _T_1214 = and(_T_1213, UInt<1>(0h1)) node _T_1215 = and(_T_1214, d_release_ack_1) when _T_1215 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1216 = and(io.in.d.valid, d_first_2) node _T_1217 = and(_T_1216, UInt<1>(0h1)) node _T_1218 = and(_T_1217, d_release_ack_1) when _T_1218 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1219 = dshr(inflight_1, io.in.d.bits.source) node _T_1220 = bits(_T_1219, 0, 0) node _T_1221 = or(_T_1220, same_cycle_resp_1) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1225 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_108 else : node _T_1229 = eq(io.in.d.bits.size, c_size_lookup) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_109 node _T_1233 = and(io.in.d.valid, d_first_2) node _T_1234 = and(_T_1233, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1235 = and(_T_1234, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1236 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1237 = and(_T_1235, _T_1236) node _T_1238 = and(_T_1237, d_release_ack_1) node _T_1239 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1240 = and(_T_1238, _T_1239) when _T_1240 : node _T_1241 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1242 = or(_T_1241, _WIRE_27.ready) node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(_T_1242, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1242, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_127 node _T_1246 = orr(inflight_1) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) node _T_1248 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1249 = or(_T_1247, _T_1248) node _T_1250 = lt(watchdog_1, plusarg_reader_1.out) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1255 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1256 = and(io.in.d.ready, io.in.d.valid) node _T_1257 = or(_T_1255, _T_1256) when _T_1257 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_61( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_41 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_61 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_44 = _source_ok_T_43 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_62 = _source_ok_T_61 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire _source_ok_T_67 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire _source_ok_T_68 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire _source_ok_T_69 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_82 = _source_ok_T_81 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_83 = _source_ok_T_82 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_83 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _T_1189 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1189; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1189; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1257 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1257; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1122 = _T_1189 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1122 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1122 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1122 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1122 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1122 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1168 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1168 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1137 = _T_1257 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1137 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1137 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1137 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1233 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1233 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1215 = _T_1257 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1215 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1215 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1215 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_17 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<8>(0h90)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<6>(0h20)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<6>(0h21)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<6>(0h22)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<6>(0h23)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 5, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 6) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<1>(0h1)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<6>(0h3f)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 5, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 6) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h0)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<6>(0h3f)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<8>(0ha2)) wire _source_ok_WIRE : UInt<1>[10] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_37 connect _source_ok_WIRE[8], _source_ok_T_38 connect _source_ok_WIRE[9], _source_ok_T_39 node _source_ok_T_40 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[2]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[3]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[4]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[5]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[6]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[7]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[8]) node source_ok = or(_source_ok_T_47, _source_ok_WIRE[9]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<6>(0h20)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<6>(0h21)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<6>(0h22)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<6>(0h23)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 5, 0) node _T_64 = shr(io.in.a.bits.source, 6) node _T_65 = eq(_T_64, UInt<1>(0h1)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<6>(0h3f)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 5, 0) node _T_77 = shr(io.in.a.bits.source, 6) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<6>(0h3f)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _T_90 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_91 = eq(_T_90, UInt<1>(0h0)) node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_93 = cvt(_T_92) node _T_94 = and(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = asSInt(_T_94) node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0))) node _T_97 = or(_T_91, _T_96) node _T_98 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_99 = eq(_T_98, UInt<1>(0h0)) node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _T_114 = and(_T_11, _T_24) node _T_115 = and(_T_114, _T_37) node _T_116 = and(_T_115, _T_50) node _T_117 = and(_T_116, _T_63) node _T_118 = and(_T_117, _T_76) node _T_119 = and(_T_118, _T_89) node _T_120 = and(_T_119, _T_97) node _T_121 = and(_T_120, _T_105) node _T_122 = and(_T_121, _T_113) node _T_123 = asUInt(reset) node _T_124 = eq(_T_123, UInt<1>(0h0)) when _T_124 : node _T_125 = eq(_T_122, UInt<1>(0h0)) when _T_125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_122, UInt<1>(0h1), "") : assert_1 node _T_126 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_126 : node _T_127 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_128 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_131 = shr(io.in.a.bits.source, 2) node _T_132 = eq(_T_131, UInt<6>(0h20)) node _T_133 = leq(UInt<1>(0h0), uncommonBits_6) node _T_134 = and(_T_132, _T_133) node _T_135 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_136 = and(_T_134, _T_135) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_137 = shr(io.in.a.bits.source, 2) node _T_138 = eq(_T_137, UInt<6>(0h21)) node _T_139 = leq(UInt<1>(0h0), uncommonBits_7) node _T_140 = and(_T_138, _T_139) node _T_141 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_142 = and(_T_140, _T_141) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_143 = shr(io.in.a.bits.source, 2) node _T_144 = eq(_T_143, UInt<6>(0h22)) node _T_145 = leq(UInt<1>(0h0), uncommonBits_8) node _T_146 = and(_T_144, _T_145) node _T_147 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_148 = and(_T_146, _T_147) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_149 = shr(io.in.a.bits.source, 2) node _T_150 = eq(_T_149, UInt<6>(0h23)) node _T_151 = leq(UInt<1>(0h0), uncommonBits_9) node _T_152 = and(_T_150, _T_151) node _T_153 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_154 = and(_T_152, _T_153) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 5, 0) node _T_155 = shr(io.in.a.bits.source, 6) node _T_156 = eq(_T_155, UInt<1>(0h1)) node _T_157 = leq(UInt<1>(0h0), uncommonBits_10) node _T_158 = and(_T_156, _T_157) node _T_159 = leq(uncommonBits_10, UInt<6>(0h3f)) node _T_160 = and(_T_158, _T_159) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 5, 0) node _T_161 = shr(io.in.a.bits.source, 6) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = leq(UInt<1>(0h0), uncommonBits_11) node _T_164 = and(_T_162, _T_163) node _T_165 = leq(uncommonBits_11, UInt<6>(0h3f)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_168 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_169 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_170 = or(_T_130, _T_136) node _T_171 = or(_T_170, _T_142) node _T_172 = or(_T_171, _T_148) node _T_173 = or(_T_172, _T_154) node _T_174 = or(_T_173, _T_160) node _T_175 = or(_T_174, _T_166) node _T_176 = or(_T_175, _T_167) node _T_177 = or(_T_176, _T_168) node _T_178 = or(_T_177, _T_169) node _T_179 = and(_T_129, _T_178) node _T_180 = or(UInt<1>(0h0), _T_179) node _T_181 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<14>(0h2000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_188 = cvt(_T_187) node _T_189 = and(_T_188, asSInt(UInt<13>(0h1000))) node _T_190 = asSInt(_T_189) node _T_191 = eq(_T_190, asSInt(UInt<1>(0h0))) node _T_192 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_193 = cvt(_T_192) node _T_194 = and(_T_193, asSInt(UInt<17>(0h10000))) node _T_195 = asSInt(_T_194) node _T_196 = eq(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<18>(0h2f000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<17>(0h10000))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_208 = cvt(_T_207) node _T_209 = and(_T_208, asSInt(UInt<13>(0h1000))) node _T_210 = asSInt(_T_209) node _T_211 = eq(_T_210, asSInt(UInt<1>(0h0))) node _T_212 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_213 = cvt(_T_212) node _T_214 = and(_T_213, asSInt(UInt<27>(0h4000000))) node _T_215 = asSInt(_T_214) node _T_216 = eq(_T_215, asSInt(UInt<1>(0h0))) node _T_217 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_218 = cvt(_T_217) node _T_219 = and(_T_218, asSInt(UInt<13>(0h1000))) node _T_220 = asSInt(_T_219) node _T_221 = eq(_T_220, asSInt(UInt<1>(0h0))) node _T_222 = or(_T_186, _T_191) node _T_223 = or(_T_222, _T_196) node _T_224 = or(_T_223, _T_201) node _T_225 = or(_T_224, _T_206) node _T_226 = or(_T_225, _T_211) node _T_227 = or(_T_226, _T_216) node _T_228 = or(_T_227, _T_221) node _T_229 = and(_T_181, _T_228) node _T_230 = or(UInt<1>(0h0), _T_229) node _T_231 = and(_T_180, _T_230) node _T_232 = asUInt(reset) node _T_233 = eq(_T_232, UInt<1>(0h0)) when _T_233 : node _T_234 = eq(_T_231, UInt<1>(0h0)) when _T_234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_231, UInt<1>(0h1), "") : assert_2 node _T_235 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_236 = shr(io.in.a.bits.source, 2) node _T_237 = eq(_T_236, UInt<6>(0h20)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_12) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_242 = shr(io.in.a.bits.source, 2) node _T_243 = eq(_T_242, UInt<6>(0h21)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_13) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_247 = and(_T_245, _T_246) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_248 = shr(io.in.a.bits.source, 2) node _T_249 = eq(_T_248, UInt<6>(0h22)) node _T_250 = leq(UInt<1>(0h0), uncommonBits_14) node _T_251 = and(_T_249, _T_250) node _T_252 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_253 = and(_T_251, _T_252) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_254 = shr(io.in.a.bits.source, 2) node _T_255 = eq(_T_254, UInt<6>(0h23)) node _T_256 = leq(UInt<1>(0h0), uncommonBits_15) node _T_257 = and(_T_255, _T_256) node _T_258 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_259 = and(_T_257, _T_258) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 5, 0) node _T_260 = shr(io.in.a.bits.source, 6) node _T_261 = eq(_T_260, UInt<1>(0h1)) node _T_262 = leq(UInt<1>(0h0), uncommonBits_16) node _T_263 = and(_T_261, _T_262) node _T_264 = leq(uncommonBits_16, UInt<6>(0h3f)) node _T_265 = and(_T_263, _T_264) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 5, 0) node _T_266 = shr(io.in.a.bits.source, 6) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_17) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_17, UInt<6>(0h3f)) node _T_271 = and(_T_269, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_273 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_274 = eq(io.in.a.bits.source, UInt<8>(0ha2)) wire _WIRE : UInt<1>[10] connect _WIRE[0], _T_235 connect _WIRE[1], _T_241 connect _WIRE[2], _T_247 connect _WIRE[3], _T_253 connect _WIRE[4], _T_259 connect _WIRE[5], _T_265 connect _WIRE[6], _T_271 connect _WIRE[7], _T_272 connect _WIRE[8], _T_273 connect _WIRE[9], _T_274 node _T_275 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_276 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_277 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_278 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_279 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_280 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_281 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_282 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = mux(_WIRE[7], _T_275, UInt<1>(0h0)) node _T_284 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_285 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_286 = or(_T_276, _T_277) node _T_287 = or(_T_286, _T_278) node _T_288 = or(_T_287, _T_279) node _T_289 = or(_T_288, _T_280) node _T_290 = or(_T_289, _T_281) node _T_291 = or(_T_290, _T_282) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_284) node _T_294 = or(_T_293, _T_285) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_294 node _T_295 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_296 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_297 = and(_T_295, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_300 = cvt(_T_299) node _T_301 = and(_T_300, asSInt(UInt<14>(0h2000))) node _T_302 = asSInt(_T_301) node _T_303 = eq(_T_302, asSInt(UInt<1>(0h0))) node _T_304 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_305 = cvt(_T_304) node _T_306 = and(_T_305, asSInt(UInt<13>(0h1000))) node _T_307 = asSInt(_T_306) node _T_308 = eq(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_310 = cvt(_T_309) node _T_311 = and(_T_310, asSInt(UInt<17>(0h10000))) node _T_312 = asSInt(_T_311) node _T_313 = eq(_T_312, asSInt(UInt<1>(0h0))) node _T_314 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<18>(0h2f000))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<17>(0h10000))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<13>(0h1000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_330 = cvt(_T_329) node _T_331 = and(_T_330, asSInt(UInt<27>(0h4000000))) node _T_332 = asSInt(_T_331) node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0))) node _T_334 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<13>(0h1000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = or(_T_303, _T_308) node _T_340 = or(_T_339, _T_313) node _T_341 = or(_T_340, _T_318) node _T_342 = or(_T_341, _T_323) node _T_343 = or(_T_342, _T_328) node _T_344 = or(_T_343, _T_333) node _T_345 = or(_T_344, _T_338) node _T_346 = and(_T_298, _T_345) node _T_347 = or(UInt<1>(0h0), _T_346) node _T_348 = and(_WIRE_1, _T_347) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_348, UInt<1>(0h1), "") : assert_3 node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(source_ok, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_355 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_355, UInt<1>(0h1), "") : assert_5 node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(is_aligned, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_362 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_362, UInt<1>(0h1), "") : assert_7 node _T_366 = not(io.in.a.bits.mask) node _T_367 = eq(_T_366, UInt<1>(0h0)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_367, UInt<1>(0h1), "") : assert_8 node _T_371 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_T_371, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_371, UInt<1>(0h1), "") : assert_9 node _T_375 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_375 : node _T_376 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_377 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_378 = and(_T_376, _T_377) node _T_379 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_380 = shr(io.in.a.bits.source, 2) node _T_381 = eq(_T_380, UInt<6>(0h20)) node _T_382 = leq(UInt<1>(0h0), uncommonBits_18) node _T_383 = and(_T_381, _T_382) node _T_384 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_385 = and(_T_383, _T_384) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_386 = shr(io.in.a.bits.source, 2) node _T_387 = eq(_T_386, UInt<6>(0h21)) node _T_388 = leq(UInt<1>(0h0), uncommonBits_19) node _T_389 = and(_T_387, _T_388) node _T_390 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_391 = and(_T_389, _T_390) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_392 = shr(io.in.a.bits.source, 2) node _T_393 = eq(_T_392, UInt<6>(0h22)) node _T_394 = leq(UInt<1>(0h0), uncommonBits_20) node _T_395 = and(_T_393, _T_394) node _T_396 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_397 = and(_T_395, _T_396) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_398 = shr(io.in.a.bits.source, 2) node _T_399 = eq(_T_398, UInt<6>(0h23)) node _T_400 = leq(UInt<1>(0h0), uncommonBits_21) node _T_401 = and(_T_399, _T_400) node _T_402 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_403 = and(_T_401, _T_402) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 5, 0) node _T_404 = shr(io.in.a.bits.source, 6) node _T_405 = eq(_T_404, UInt<1>(0h1)) node _T_406 = leq(UInt<1>(0h0), uncommonBits_22) node _T_407 = and(_T_405, _T_406) node _T_408 = leq(uncommonBits_22, UInt<6>(0h3f)) node _T_409 = and(_T_407, _T_408) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 5, 0) node _T_410 = shr(io.in.a.bits.source, 6) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = leq(UInt<1>(0h0), uncommonBits_23) node _T_413 = and(_T_411, _T_412) node _T_414 = leq(uncommonBits_23, UInt<6>(0h3f)) node _T_415 = and(_T_413, _T_414) node _T_416 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_417 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_418 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_419 = or(_T_379, _T_385) node _T_420 = or(_T_419, _T_391) node _T_421 = or(_T_420, _T_397) node _T_422 = or(_T_421, _T_403) node _T_423 = or(_T_422, _T_409) node _T_424 = or(_T_423, _T_415) node _T_425 = or(_T_424, _T_416) node _T_426 = or(_T_425, _T_417) node _T_427 = or(_T_426, _T_418) node _T_428 = and(_T_378, _T_427) node _T_429 = or(UInt<1>(0h0), _T_428) node _T_430 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_431 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_432 = cvt(_T_431) node _T_433 = and(_T_432, asSInt(UInt<14>(0h2000))) node _T_434 = asSInt(_T_433) node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0))) node _T_436 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<13>(0h1000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<17>(0h10000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_447 = cvt(_T_446) node _T_448 = and(_T_447, asSInt(UInt<18>(0h2f000))) node _T_449 = asSInt(_T_448) node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0))) node _T_451 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<17>(0h10000))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<13>(0h1000))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<27>(0h4000000))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<13>(0h1000))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = or(_T_435, _T_440) node _T_472 = or(_T_471, _T_445) node _T_473 = or(_T_472, _T_450) node _T_474 = or(_T_473, _T_455) node _T_475 = or(_T_474, _T_460) node _T_476 = or(_T_475, _T_465) node _T_477 = or(_T_476, _T_470) node _T_478 = and(_T_430, _T_477) node _T_479 = or(UInt<1>(0h0), _T_478) node _T_480 = and(_T_429, _T_479) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_480, UInt<1>(0h1), "") : assert_10 node _T_484 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_485 = shr(io.in.a.bits.source, 2) node _T_486 = eq(_T_485, UInt<6>(0h20)) node _T_487 = leq(UInt<1>(0h0), uncommonBits_24) node _T_488 = and(_T_486, _T_487) node _T_489 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_490 = and(_T_488, _T_489) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_491 = shr(io.in.a.bits.source, 2) node _T_492 = eq(_T_491, UInt<6>(0h21)) node _T_493 = leq(UInt<1>(0h0), uncommonBits_25) node _T_494 = and(_T_492, _T_493) node _T_495 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_496 = and(_T_494, _T_495) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_497 = shr(io.in.a.bits.source, 2) node _T_498 = eq(_T_497, UInt<6>(0h22)) node _T_499 = leq(UInt<1>(0h0), uncommonBits_26) node _T_500 = and(_T_498, _T_499) node _T_501 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_502 = and(_T_500, _T_501) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_503 = shr(io.in.a.bits.source, 2) node _T_504 = eq(_T_503, UInt<6>(0h23)) node _T_505 = leq(UInt<1>(0h0), uncommonBits_27) node _T_506 = and(_T_504, _T_505) node _T_507 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_508 = and(_T_506, _T_507) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 5, 0) node _T_509 = shr(io.in.a.bits.source, 6) node _T_510 = eq(_T_509, UInt<1>(0h1)) node _T_511 = leq(UInt<1>(0h0), uncommonBits_28) node _T_512 = and(_T_510, _T_511) node _T_513 = leq(uncommonBits_28, UInt<6>(0h3f)) node _T_514 = and(_T_512, _T_513) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 5, 0) node _T_515 = shr(io.in.a.bits.source, 6) node _T_516 = eq(_T_515, UInt<1>(0h0)) node _T_517 = leq(UInt<1>(0h0), uncommonBits_29) node _T_518 = and(_T_516, _T_517) node _T_519 = leq(uncommonBits_29, UInt<6>(0h3f)) node _T_520 = and(_T_518, _T_519) node _T_521 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_522 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_523 = eq(io.in.a.bits.source, UInt<8>(0ha2)) wire _WIRE_2 : UInt<1>[10] connect _WIRE_2[0], _T_484 connect _WIRE_2[1], _T_490 connect _WIRE_2[2], _T_496 connect _WIRE_2[3], _T_502 connect _WIRE_2[4], _T_508 connect _WIRE_2[5], _T_514 connect _WIRE_2[6], _T_520 connect _WIRE_2[7], _T_521 connect _WIRE_2[8], _T_522 connect _WIRE_2[9], _T_523 node _T_524 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_525 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_527 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_528 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_529 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_530 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_531 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_532 = mux(_WIRE_2[7], _T_524, UInt<1>(0h0)) node _T_533 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_534 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_535 = or(_T_525, _T_526) node _T_536 = or(_T_535, _T_527) node _T_537 = or(_T_536, _T_528) node _T_538 = or(_T_537, _T_529) node _T_539 = or(_T_538, _T_530) node _T_540 = or(_T_539, _T_531) node _T_541 = or(_T_540, _T_532) node _T_542 = or(_T_541, _T_533) node _T_543 = or(_T_542, _T_534) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_543 node _T_544 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_545 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_546 = and(_T_544, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_549 = cvt(_T_548) node _T_550 = and(_T_549, asSInt(UInt<14>(0h2000))) node _T_551 = asSInt(_T_550) node _T_552 = eq(_T_551, asSInt(UInt<1>(0h0))) node _T_553 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_554 = cvt(_T_553) node _T_555 = and(_T_554, asSInt(UInt<13>(0h1000))) node _T_556 = asSInt(_T_555) node _T_557 = eq(_T_556, asSInt(UInt<1>(0h0))) node _T_558 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_559 = cvt(_T_558) node _T_560 = and(_T_559, asSInt(UInt<17>(0h10000))) node _T_561 = asSInt(_T_560) node _T_562 = eq(_T_561, asSInt(UInt<1>(0h0))) node _T_563 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_564 = cvt(_T_563) node _T_565 = and(_T_564, asSInt(UInt<18>(0h2f000))) node _T_566 = asSInt(_T_565) node _T_567 = eq(_T_566, asSInt(UInt<1>(0h0))) node _T_568 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_569 = cvt(_T_568) node _T_570 = and(_T_569, asSInt(UInt<17>(0h10000))) node _T_571 = asSInt(_T_570) node _T_572 = eq(_T_571, asSInt(UInt<1>(0h0))) node _T_573 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_574 = cvt(_T_573) node _T_575 = and(_T_574, asSInt(UInt<13>(0h1000))) node _T_576 = asSInt(_T_575) node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0))) node _T_578 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<27>(0h4000000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_584 = cvt(_T_583) node _T_585 = and(_T_584, asSInt(UInt<13>(0h1000))) node _T_586 = asSInt(_T_585) node _T_587 = eq(_T_586, asSInt(UInt<1>(0h0))) node _T_588 = or(_T_552, _T_557) node _T_589 = or(_T_588, _T_562) node _T_590 = or(_T_589, _T_567) node _T_591 = or(_T_590, _T_572) node _T_592 = or(_T_591, _T_577) node _T_593 = or(_T_592, _T_582) node _T_594 = or(_T_593, _T_587) node _T_595 = and(_T_547, _T_594) node _T_596 = or(UInt<1>(0h0), _T_595) node _T_597 = and(_WIRE_3, _T_596) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_597, UInt<1>(0h1), "") : assert_11 node _T_601 = asUInt(reset) node _T_602 = eq(_T_601, UInt<1>(0h0)) when _T_602 : node _T_603 = eq(source_ok, UInt<1>(0h0)) when _T_603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_604 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(_T_604, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_604, UInt<1>(0h1), "") : assert_13 node _T_608 = asUInt(reset) node _T_609 = eq(_T_608, UInt<1>(0h0)) when _T_609 : node _T_610 = eq(is_aligned, UInt<1>(0h0)) when _T_610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_611 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_611, UInt<1>(0h1), "") : assert_15 node _T_615 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_616 = asUInt(reset) node _T_617 = eq(_T_616, UInt<1>(0h0)) when _T_617 : node _T_618 = eq(_T_615, UInt<1>(0h0)) when _T_618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_615, UInt<1>(0h1), "") : assert_16 node _T_619 = not(io.in.a.bits.mask) node _T_620 = eq(_T_619, UInt<1>(0h0)) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_620, UInt<1>(0h1), "") : assert_17 node _T_624 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_624, UInt<1>(0h1), "") : assert_18 node _T_628 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_628 : node _T_629 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_630 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_631 = and(_T_629, _T_630) node _T_632 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_633 = shr(io.in.a.bits.source, 2) node _T_634 = eq(_T_633, UInt<6>(0h20)) node _T_635 = leq(UInt<1>(0h0), uncommonBits_30) node _T_636 = and(_T_634, _T_635) node _T_637 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_638 = and(_T_636, _T_637) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_639 = shr(io.in.a.bits.source, 2) node _T_640 = eq(_T_639, UInt<6>(0h21)) node _T_641 = leq(UInt<1>(0h0), uncommonBits_31) node _T_642 = and(_T_640, _T_641) node _T_643 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_644 = and(_T_642, _T_643) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_645 = shr(io.in.a.bits.source, 2) node _T_646 = eq(_T_645, UInt<6>(0h22)) node _T_647 = leq(UInt<1>(0h0), uncommonBits_32) node _T_648 = and(_T_646, _T_647) node _T_649 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_650 = and(_T_648, _T_649) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_651 = shr(io.in.a.bits.source, 2) node _T_652 = eq(_T_651, UInt<6>(0h23)) node _T_653 = leq(UInt<1>(0h0), uncommonBits_33) node _T_654 = and(_T_652, _T_653) node _T_655 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_656 = and(_T_654, _T_655) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 5, 0) node _T_657 = shr(io.in.a.bits.source, 6) node _T_658 = eq(_T_657, UInt<1>(0h1)) node _T_659 = leq(UInt<1>(0h0), uncommonBits_34) node _T_660 = and(_T_658, _T_659) node _T_661 = leq(uncommonBits_34, UInt<6>(0h3f)) node _T_662 = and(_T_660, _T_661) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 5, 0) node _T_663 = shr(io.in.a.bits.source, 6) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = leq(UInt<1>(0h0), uncommonBits_35) node _T_666 = and(_T_664, _T_665) node _T_667 = leq(uncommonBits_35, UInt<6>(0h3f)) node _T_668 = and(_T_666, _T_667) node _T_669 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_670 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_671 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_672 = or(_T_632, _T_638) node _T_673 = or(_T_672, _T_644) node _T_674 = or(_T_673, _T_650) node _T_675 = or(_T_674, _T_656) node _T_676 = or(_T_675, _T_662) node _T_677 = or(_T_676, _T_668) node _T_678 = or(_T_677, _T_669) node _T_679 = or(_T_678, _T_670) node _T_680 = or(_T_679, _T_671) node _T_681 = and(_T_631, _T_680) node _T_682 = or(UInt<1>(0h0), _T_681) node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_T_682, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_682, UInt<1>(0h1), "") : assert_19 node _T_686 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_687 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_688 = and(_T_686, _T_687) node _T_689 = or(UInt<1>(0h0), _T_688) node _T_690 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_691 = cvt(_T_690) node _T_692 = and(_T_691, asSInt(UInt<13>(0h1000))) node _T_693 = asSInt(_T_692) node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) node _T_695 = and(_T_689, _T_694) node _T_696 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_697 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_698 = and(_T_696, _T_697) node _T_699 = or(UInt<1>(0h0), _T_698) node _T_700 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_701 = cvt(_T_700) node _T_702 = and(_T_701, asSInt(UInt<14>(0h2000))) node _T_703 = asSInt(_T_702) node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) node _T_705 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<17>(0h10000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<18>(0h2f000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<17>(0h10000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_721 = cvt(_T_720) node _T_722 = and(_T_721, asSInt(UInt<13>(0h1000))) node _T_723 = asSInt(_T_722) node _T_724 = eq(_T_723, asSInt(UInt<1>(0h0))) node _T_725 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_726 = cvt(_T_725) node _T_727 = and(_T_726, asSInt(UInt<27>(0h4000000))) node _T_728 = asSInt(_T_727) node _T_729 = eq(_T_728, asSInt(UInt<1>(0h0))) node _T_730 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_731 = cvt(_T_730) node _T_732 = and(_T_731, asSInt(UInt<13>(0h1000))) node _T_733 = asSInt(_T_732) node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0))) node _T_735 = or(_T_704, _T_709) node _T_736 = or(_T_735, _T_714) node _T_737 = or(_T_736, _T_719) node _T_738 = or(_T_737, _T_724) node _T_739 = or(_T_738, _T_729) node _T_740 = or(_T_739, _T_734) node _T_741 = and(_T_699, _T_740) node _T_742 = or(UInt<1>(0h0), _T_695) node _T_743 = or(_T_742, _T_741) node _T_744 = asUInt(reset) node _T_745 = eq(_T_744, UInt<1>(0h0)) when _T_745 : node _T_746 = eq(_T_743, UInt<1>(0h0)) when _T_746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_743, UInt<1>(0h1), "") : assert_20 node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(source_ok, UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(is_aligned, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_753 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_754 = asUInt(reset) node _T_755 = eq(_T_754, UInt<1>(0h0)) when _T_755 : node _T_756 = eq(_T_753, UInt<1>(0h0)) when _T_756 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_753, UInt<1>(0h1), "") : assert_23 node _T_757 = eq(io.in.a.bits.mask, mask) node _T_758 = asUInt(reset) node _T_759 = eq(_T_758, UInt<1>(0h0)) when _T_759 : node _T_760 = eq(_T_757, UInt<1>(0h0)) when _T_760 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_757, UInt<1>(0h1), "") : assert_24 node _T_761 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_761, UInt<1>(0h1), "") : assert_25 node _T_765 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_765 : node _T_766 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_767 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_768 = and(_T_766, _T_767) node _T_769 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<6>(0h20)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_36) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<6>(0h21)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_37) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_782 = shr(io.in.a.bits.source, 2) node _T_783 = eq(_T_782, UInt<6>(0h22)) node _T_784 = leq(UInt<1>(0h0), uncommonBits_38) node _T_785 = and(_T_783, _T_784) node _T_786 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_787 = and(_T_785, _T_786) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_788 = shr(io.in.a.bits.source, 2) node _T_789 = eq(_T_788, UInt<6>(0h23)) node _T_790 = leq(UInt<1>(0h0), uncommonBits_39) node _T_791 = and(_T_789, _T_790) node _T_792 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 5, 0) node _T_794 = shr(io.in.a.bits.source, 6) node _T_795 = eq(_T_794, UInt<1>(0h1)) node _T_796 = leq(UInt<1>(0h0), uncommonBits_40) node _T_797 = and(_T_795, _T_796) node _T_798 = leq(uncommonBits_40, UInt<6>(0h3f)) node _T_799 = and(_T_797, _T_798) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 5, 0) node _T_800 = shr(io.in.a.bits.source, 6) node _T_801 = eq(_T_800, UInt<1>(0h0)) node _T_802 = leq(UInt<1>(0h0), uncommonBits_41) node _T_803 = and(_T_801, _T_802) node _T_804 = leq(uncommonBits_41, UInt<6>(0h3f)) node _T_805 = and(_T_803, _T_804) node _T_806 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_807 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_808 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_809 = or(_T_769, _T_775) node _T_810 = or(_T_809, _T_781) node _T_811 = or(_T_810, _T_787) node _T_812 = or(_T_811, _T_793) node _T_813 = or(_T_812, _T_799) node _T_814 = or(_T_813, _T_805) node _T_815 = or(_T_814, _T_806) node _T_816 = or(_T_815, _T_807) node _T_817 = or(_T_816, _T_808) node _T_818 = and(_T_768, _T_817) node _T_819 = or(UInt<1>(0h0), _T_818) node _T_820 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_821 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_822 = and(_T_820, _T_821) node _T_823 = or(UInt<1>(0h0), _T_822) node _T_824 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<13>(0h1000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = and(_T_823, _T_828) node _T_830 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_831 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_832 = and(_T_830, _T_831) node _T_833 = or(UInt<1>(0h0), _T_832) node _T_834 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<14>(0h2000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<18>(0h2f000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<13>(0h1000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<27>(0h4000000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<13>(0h1000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = or(_T_838, _T_843) node _T_865 = or(_T_864, _T_848) node _T_866 = or(_T_865, _T_853) node _T_867 = or(_T_866, _T_858) node _T_868 = or(_T_867, _T_863) node _T_869 = and(_T_833, _T_868) node _T_870 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_871 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_872 = cvt(_T_871) node _T_873 = and(_T_872, asSInt(UInt<17>(0h10000))) node _T_874 = asSInt(_T_873) node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0))) node _T_876 = and(_T_870, _T_875) node _T_877 = or(UInt<1>(0h0), _T_829) node _T_878 = or(_T_877, _T_869) node _T_879 = or(_T_878, _T_876) node _T_880 = and(_T_819, _T_879) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_880, UInt<1>(0h1), "") : assert_26 node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(source_ok, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(is_aligned, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_890 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_890, UInt<1>(0h1), "") : assert_29 node _T_894 = eq(io.in.a.bits.mask, mask) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_894, UInt<1>(0h1), "") : assert_30 node _T_898 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_898 : node _T_899 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_900 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_901 = and(_T_899, _T_900) node _T_902 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_903 = shr(io.in.a.bits.source, 2) node _T_904 = eq(_T_903, UInt<6>(0h20)) node _T_905 = leq(UInt<1>(0h0), uncommonBits_42) node _T_906 = and(_T_904, _T_905) node _T_907 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_908 = and(_T_906, _T_907) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_909 = shr(io.in.a.bits.source, 2) node _T_910 = eq(_T_909, UInt<6>(0h21)) node _T_911 = leq(UInt<1>(0h0), uncommonBits_43) node _T_912 = and(_T_910, _T_911) node _T_913 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_914 = and(_T_912, _T_913) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_915 = shr(io.in.a.bits.source, 2) node _T_916 = eq(_T_915, UInt<6>(0h22)) node _T_917 = leq(UInt<1>(0h0), uncommonBits_44) node _T_918 = and(_T_916, _T_917) node _T_919 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_920 = and(_T_918, _T_919) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_921 = shr(io.in.a.bits.source, 2) node _T_922 = eq(_T_921, UInt<6>(0h23)) node _T_923 = leq(UInt<1>(0h0), uncommonBits_45) node _T_924 = and(_T_922, _T_923) node _T_925 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_926 = and(_T_924, _T_925) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 5, 0) node _T_927 = shr(io.in.a.bits.source, 6) node _T_928 = eq(_T_927, UInt<1>(0h1)) node _T_929 = leq(UInt<1>(0h0), uncommonBits_46) node _T_930 = and(_T_928, _T_929) node _T_931 = leq(uncommonBits_46, UInt<6>(0h3f)) node _T_932 = and(_T_930, _T_931) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 5, 0) node _T_933 = shr(io.in.a.bits.source, 6) node _T_934 = eq(_T_933, UInt<1>(0h0)) node _T_935 = leq(UInt<1>(0h0), uncommonBits_47) node _T_936 = and(_T_934, _T_935) node _T_937 = leq(uncommonBits_47, UInt<6>(0h3f)) node _T_938 = and(_T_936, _T_937) node _T_939 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_940 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_941 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_942 = or(_T_902, _T_908) node _T_943 = or(_T_942, _T_914) node _T_944 = or(_T_943, _T_920) node _T_945 = or(_T_944, _T_926) node _T_946 = or(_T_945, _T_932) node _T_947 = or(_T_946, _T_938) node _T_948 = or(_T_947, _T_939) node _T_949 = or(_T_948, _T_940) node _T_950 = or(_T_949, _T_941) node _T_951 = and(_T_901, _T_950) node _T_952 = or(UInt<1>(0h0), _T_951) node _T_953 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_954 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_955 = and(_T_953, _T_954) node _T_956 = or(UInt<1>(0h0), _T_955) node _T_957 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_958 = cvt(_T_957) node _T_959 = and(_T_958, asSInt(UInt<13>(0h1000))) node _T_960 = asSInt(_T_959) node _T_961 = eq(_T_960, asSInt(UInt<1>(0h0))) node _T_962 = and(_T_956, _T_961) node _T_963 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_964 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_965 = and(_T_963, _T_964) node _T_966 = or(UInt<1>(0h0), _T_965) node _T_967 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_968 = cvt(_T_967) node _T_969 = and(_T_968, asSInt(UInt<14>(0h2000))) node _T_970 = asSInt(_T_969) node _T_971 = eq(_T_970, asSInt(UInt<1>(0h0))) node _T_972 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_973 = cvt(_T_972) node _T_974 = and(_T_973, asSInt(UInt<18>(0h2f000))) node _T_975 = asSInt(_T_974) node _T_976 = eq(_T_975, asSInt(UInt<1>(0h0))) node _T_977 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_978 = cvt(_T_977) node _T_979 = and(_T_978, asSInt(UInt<17>(0h10000))) node _T_980 = asSInt(_T_979) node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0))) node _T_982 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_983 = cvt(_T_982) node _T_984 = and(_T_983, asSInt(UInt<13>(0h1000))) node _T_985 = asSInt(_T_984) node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0))) node _T_987 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<27>(0h4000000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<13>(0h1000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = or(_T_971, _T_976) node _T_998 = or(_T_997, _T_981) node _T_999 = or(_T_998, _T_986) node _T_1000 = or(_T_999, _T_991) node _T_1001 = or(_T_1000, _T_996) node _T_1002 = and(_T_966, _T_1001) node _T_1003 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1004 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1005 = cvt(_T_1004) node _T_1006 = and(_T_1005, asSInt(UInt<17>(0h10000))) node _T_1007 = asSInt(_T_1006) node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0))) node _T_1009 = and(_T_1003, _T_1008) node _T_1010 = or(UInt<1>(0h0), _T_962) node _T_1011 = or(_T_1010, _T_1002) node _T_1012 = or(_T_1011, _T_1009) node _T_1013 = and(_T_952, _T_1012) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_31 node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(source_ok, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(is_aligned, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1023 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_34 node _T_1027 = not(mask) node _T_1028 = and(io.in.a.bits.mask, _T_1027) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_35 node _T_1033 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1033 : node _T_1034 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1035 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1036 = and(_T_1034, _T_1035) node _T_1037 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1038 = shr(io.in.a.bits.source, 2) node _T_1039 = eq(_T_1038, UInt<6>(0h20)) node _T_1040 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1041 = and(_T_1039, _T_1040) node _T_1042 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1043 = and(_T_1041, _T_1042) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1044 = shr(io.in.a.bits.source, 2) node _T_1045 = eq(_T_1044, UInt<6>(0h21)) node _T_1046 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1047 = and(_T_1045, _T_1046) node _T_1048 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1049 = and(_T_1047, _T_1048) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1050 = shr(io.in.a.bits.source, 2) node _T_1051 = eq(_T_1050, UInt<6>(0h22)) node _T_1052 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1053 = and(_T_1051, _T_1052) node _T_1054 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1055 = and(_T_1053, _T_1054) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1056 = shr(io.in.a.bits.source, 2) node _T_1057 = eq(_T_1056, UInt<6>(0h23)) node _T_1058 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1059 = and(_T_1057, _T_1058) node _T_1060 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1061 = and(_T_1059, _T_1060) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 5, 0) node _T_1062 = shr(io.in.a.bits.source, 6) node _T_1063 = eq(_T_1062, UInt<1>(0h1)) node _T_1064 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1065 = and(_T_1063, _T_1064) node _T_1066 = leq(uncommonBits_52, UInt<6>(0h3f)) node _T_1067 = and(_T_1065, _T_1066) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 5, 0) node _T_1068 = shr(io.in.a.bits.source, 6) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) node _T_1070 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = leq(uncommonBits_53, UInt<6>(0h3f)) node _T_1073 = and(_T_1071, _T_1072) node _T_1074 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_1075 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_1076 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_1077 = or(_T_1037, _T_1043) node _T_1078 = or(_T_1077, _T_1049) node _T_1079 = or(_T_1078, _T_1055) node _T_1080 = or(_T_1079, _T_1061) node _T_1081 = or(_T_1080, _T_1067) node _T_1082 = or(_T_1081, _T_1073) node _T_1083 = or(_T_1082, _T_1074) node _T_1084 = or(_T_1083, _T_1075) node _T_1085 = or(_T_1084, _T_1076) node _T_1086 = and(_T_1036, _T_1085) node _T_1087 = or(UInt<1>(0h0), _T_1086) node _T_1088 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1089 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1090 = and(_T_1088, _T_1089) node _T_1091 = or(UInt<1>(0h0), _T_1090) node _T_1092 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1093 = cvt(_T_1092) node _T_1094 = and(_T_1093, asSInt(UInt<14>(0h2000))) node _T_1095 = asSInt(_T_1094) node _T_1096 = eq(_T_1095, asSInt(UInt<1>(0h0))) node _T_1097 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1098 = cvt(_T_1097) node _T_1099 = and(_T_1098, asSInt(UInt<13>(0h1000))) node _T_1100 = asSInt(_T_1099) node _T_1101 = eq(_T_1100, asSInt(UInt<1>(0h0))) node _T_1102 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1103 = cvt(_T_1102) node _T_1104 = and(_T_1103, asSInt(UInt<18>(0h2f000))) node _T_1105 = asSInt(_T_1104) node _T_1106 = eq(_T_1105, asSInt(UInt<1>(0h0))) node _T_1107 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1108 = cvt(_T_1107) node _T_1109 = and(_T_1108, asSInt(UInt<17>(0h10000))) node _T_1110 = asSInt(_T_1109) node _T_1111 = eq(_T_1110, asSInt(UInt<1>(0h0))) node _T_1112 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1113 = cvt(_T_1112) node _T_1114 = and(_T_1113, asSInt(UInt<13>(0h1000))) node _T_1115 = asSInt(_T_1114) node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0))) node _T_1117 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1118 = cvt(_T_1117) node _T_1119 = and(_T_1118, asSInt(UInt<27>(0h4000000))) node _T_1120 = asSInt(_T_1119) node _T_1121 = eq(_T_1120, asSInt(UInt<1>(0h0))) node _T_1122 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1123 = cvt(_T_1122) node _T_1124 = and(_T_1123, asSInt(UInt<13>(0h1000))) node _T_1125 = asSInt(_T_1124) node _T_1126 = eq(_T_1125, asSInt(UInt<1>(0h0))) node _T_1127 = or(_T_1096, _T_1101) node _T_1128 = or(_T_1127, _T_1106) node _T_1129 = or(_T_1128, _T_1111) node _T_1130 = or(_T_1129, _T_1116) node _T_1131 = or(_T_1130, _T_1121) node _T_1132 = or(_T_1131, _T_1126) node _T_1133 = and(_T_1091, _T_1132) node _T_1134 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1135 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1136 = cvt(_T_1135) node _T_1137 = and(_T_1136, asSInt(UInt<17>(0h10000))) node _T_1138 = asSInt(_T_1137) node _T_1139 = eq(_T_1138, asSInt(UInt<1>(0h0))) node _T_1140 = and(_T_1134, _T_1139) node _T_1141 = or(UInt<1>(0h0), _T_1133) node _T_1142 = or(_T_1141, _T_1140) node _T_1143 = and(_T_1087, _T_1142) node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(_T_1143, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1143, UInt<1>(0h1), "") : assert_36 node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(source_ok, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(is_aligned, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1153 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_39 node _T_1157 = eq(io.in.a.bits.mask, mask) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_40 node _T_1161 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1161 : node _T_1162 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1163 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1164 = and(_T_1162, _T_1163) node _T_1165 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_1166 = shr(io.in.a.bits.source, 2) node _T_1167 = eq(_T_1166, UInt<6>(0h20)) node _T_1168 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1169 = and(_T_1167, _T_1168) node _T_1170 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_1171 = and(_T_1169, _T_1170) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1172 = shr(io.in.a.bits.source, 2) node _T_1173 = eq(_T_1172, UInt<6>(0h21)) node _T_1174 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1175 = and(_T_1173, _T_1174) node _T_1176 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1177 = and(_T_1175, _T_1176) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1178 = shr(io.in.a.bits.source, 2) node _T_1179 = eq(_T_1178, UInt<6>(0h22)) node _T_1180 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1181 = and(_T_1179, _T_1180) node _T_1182 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1183 = and(_T_1181, _T_1182) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1184 = shr(io.in.a.bits.source, 2) node _T_1185 = eq(_T_1184, UInt<6>(0h23)) node _T_1186 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1189 = and(_T_1187, _T_1188) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 5, 0) node _T_1190 = shr(io.in.a.bits.source, 6) node _T_1191 = eq(_T_1190, UInt<1>(0h1)) node _T_1192 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1193 = and(_T_1191, _T_1192) node _T_1194 = leq(uncommonBits_58, UInt<6>(0h3f)) node _T_1195 = and(_T_1193, _T_1194) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 5, 0) node _T_1196 = shr(io.in.a.bits.source, 6) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) node _T_1198 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1199 = and(_T_1197, _T_1198) node _T_1200 = leq(uncommonBits_59, UInt<6>(0h3f)) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_1203 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_1204 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_1205 = or(_T_1165, _T_1171) node _T_1206 = or(_T_1205, _T_1177) node _T_1207 = or(_T_1206, _T_1183) node _T_1208 = or(_T_1207, _T_1189) node _T_1209 = or(_T_1208, _T_1195) node _T_1210 = or(_T_1209, _T_1201) node _T_1211 = or(_T_1210, _T_1202) node _T_1212 = or(_T_1211, _T_1203) node _T_1213 = or(_T_1212, _T_1204) node _T_1214 = and(_T_1164, _T_1213) node _T_1215 = or(UInt<1>(0h0), _T_1214) node _T_1216 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1217 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = or(UInt<1>(0h0), _T_1218) node _T_1220 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<14>(0h2000))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1226 = cvt(_T_1225) node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000))) node _T_1228 = asSInt(_T_1227) node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0))) node _T_1230 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<18>(0h2f000))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1236 = cvt(_T_1235) node _T_1237 = and(_T_1236, asSInt(UInt<17>(0h10000))) node _T_1238 = asSInt(_T_1237) node _T_1239 = eq(_T_1238, asSInt(UInt<1>(0h0))) node _T_1240 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1241 = cvt(_T_1240) node _T_1242 = and(_T_1241, asSInt(UInt<13>(0h1000))) node _T_1243 = asSInt(_T_1242) node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0))) node _T_1245 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1246 = cvt(_T_1245) node _T_1247 = and(_T_1246, asSInt(UInt<27>(0h4000000))) node _T_1248 = asSInt(_T_1247) node _T_1249 = eq(_T_1248, asSInt(UInt<1>(0h0))) node _T_1250 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1251 = cvt(_T_1250) node _T_1252 = and(_T_1251, asSInt(UInt<13>(0h1000))) node _T_1253 = asSInt(_T_1252) node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0))) node _T_1255 = or(_T_1224, _T_1229) node _T_1256 = or(_T_1255, _T_1234) node _T_1257 = or(_T_1256, _T_1239) node _T_1258 = or(_T_1257, _T_1244) node _T_1259 = or(_T_1258, _T_1249) node _T_1260 = or(_T_1259, _T_1254) node _T_1261 = and(_T_1219, _T_1260) node _T_1262 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1263 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1264 = cvt(_T_1263) node _T_1265 = and(_T_1264, asSInt(UInt<17>(0h10000))) node _T_1266 = asSInt(_T_1265) node _T_1267 = eq(_T_1266, asSInt(UInt<1>(0h0))) node _T_1268 = and(_T_1262, _T_1267) node _T_1269 = or(UInt<1>(0h0), _T_1261) node _T_1270 = or(_T_1269, _T_1268) node _T_1271 = and(_T_1215, _T_1270) node _T_1272 = asUInt(reset) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) when _T_1273 : node _T_1274 = eq(_T_1271, UInt<1>(0h0)) when _T_1274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1271, UInt<1>(0h1), "") : assert_41 node _T_1275 = asUInt(reset) node _T_1276 = eq(_T_1275, UInt<1>(0h0)) when _T_1276 : node _T_1277 = eq(source_ok, UInt<1>(0h0)) when _T_1277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(is_aligned, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1281 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_44 node _T_1285 = eq(io.in.a.bits.mask, mask) node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(_T_1285, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1285, UInt<1>(0h1), "") : assert_45 node _T_1289 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1289 : node _T_1290 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1291 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1292 = and(_T_1290, _T_1291) node _T_1293 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1294 = shr(io.in.a.bits.source, 2) node _T_1295 = eq(_T_1294, UInt<6>(0h20)) node _T_1296 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1297 = and(_T_1295, _T_1296) node _T_1298 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1299 = and(_T_1297, _T_1298) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1300 = shr(io.in.a.bits.source, 2) node _T_1301 = eq(_T_1300, UInt<6>(0h21)) node _T_1302 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1303 = and(_T_1301, _T_1302) node _T_1304 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1305 = and(_T_1303, _T_1304) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1306 = shr(io.in.a.bits.source, 2) node _T_1307 = eq(_T_1306, UInt<6>(0h22)) node _T_1308 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1309 = and(_T_1307, _T_1308) node _T_1310 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1311 = and(_T_1309, _T_1310) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1312 = shr(io.in.a.bits.source, 2) node _T_1313 = eq(_T_1312, UInt<6>(0h23)) node _T_1314 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1315 = and(_T_1313, _T_1314) node _T_1316 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1317 = and(_T_1315, _T_1316) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 5, 0) node _T_1318 = shr(io.in.a.bits.source, 6) node _T_1319 = eq(_T_1318, UInt<1>(0h1)) node _T_1320 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1321 = and(_T_1319, _T_1320) node _T_1322 = leq(uncommonBits_64, UInt<6>(0h3f)) node _T_1323 = and(_T_1321, _T_1322) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 5, 0) node _T_1324 = shr(io.in.a.bits.source, 6) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) node _T_1326 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1327 = and(_T_1325, _T_1326) node _T_1328 = leq(uncommonBits_65, UInt<6>(0h3f)) node _T_1329 = and(_T_1327, _T_1328) node _T_1330 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_1331 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_1332 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_1333 = or(_T_1293, _T_1299) node _T_1334 = or(_T_1333, _T_1305) node _T_1335 = or(_T_1334, _T_1311) node _T_1336 = or(_T_1335, _T_1317) node _T_1337 = or(_T_1336, _T_1323) node _T_1338 = or(_T_1337, _T_1329) node _T_1339 = or(_T_1338, _T_1330) node _T_1340 = or(_T_1339, _T_1331) node _T_1341 = or(_T_1340, _T_1332) node _T_1342 = and(_T_1292, _T_1341) node _T_1343 = or(UInt<1>(0h0), _T_1342) node _T_1344 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1345 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1346 = and(_T_1344, _T_1345) node _T_1347 = or(UInt<1>(0h0), _T_1346) node _T_1348 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1349 = cvt(_T_1348) node _T_1350 = and(_T_1349, asSInt(UInt<13>(0h1000))) node _T_1351 = asSInt(_T_1350) node _T_1352 = eq(_T_1351, asSInt(UInt<1>(0h0))) node _T_1353 = and(_T_1347, _T_1352) node _T_1354 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1355 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1356 = cvt(_T_1355) node _T_1357 = and(_T_1356, asSInt(UInt<14>(0h2000))) node _T_1358 = asSInt(_T_1357) node _T_1359 = eq(_T_1358, asSInt(UInt<1>(0h0))) node _T_1360 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1361 = cvt(_T_1360) node _T_1362 = and(_T_1361, asSInt(UInt<17>(0h10000))) node _T_1363 = asSInt(_T_1362) node _T_1364 = eq(_T_1363, asSInt(UInt<1>(0h0))) node _T_1365 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1366 = cvt(_T_1365) node _T_1367 = and(_T_1366, asSInt(UInt<18>(0h2f000))) node _T_1368 = asSInt(_T_1367) node _T_1369 = eq(_T_1368, asSInt(UInt<1>(0h0))) node _T_1370 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1371 = cvt(_T_1370) node _T_1372 = and(_T_1371, asSInt(UInt<17>(0h10000))) node _T_1373 = asSInt(_T_1372) node _T_1374 = eq(_T_1373, asSInt(UInt<1>(0h0))) node _T_1375 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1376 = cvt(_T_1375) node _T_1377 = and(_T_1376, asSInt(UInt<13>(0h1000))) node _T_1378 = asSInt(_T_1377) node _T_1379 = eq(_T_1378, asSInt(UInt<1>(0h0))) node _T_1380 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1381 = cvt(_T_1380) node _T_1382 = and(_T_1381, asSInt(UInt<27>(0h4000000))) node _T_1383 = asSInt(_T_1382) node _T_1384 = eq(_T_1383, asSInt(UInt<1>(0h0))) node _T_1385 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1386 = cvt(_T_1385) node _T_1387 = and(_T_1386, asSInt(UInt<13>(0h1000))) node _T_1388 = asSInt(_T_1387) node _T_1389 = eq(_T_1388, asSInt(UInt<1>(0h0))) node _T_1390 = or(_T_1359, _T_1364) node _T_1391 = or(_T_1390, _T_1369) node _T_1392 = or(_T_1391, _T_1374) node _T_1393 = or(_T_1392, _T_1379) node _T_1394 = or(_T_1393, _T_1384) node _T_1395 = or(_T_1394, _T_1389) node _T_1396 = and(_T_1354, _T_1395) node _T_1397 = or(UInt<1>(0h0), _T_1353) node _T_1398 = or(_T_1397, _T_1396) node _T_1399 = and(_T_1343, _T_1398) node _T_1400 = asUInt(reset) node _T_1401 = eq(_T_1400, UInt<1>(0h0)) when _T_1401 : node _T_1402 = eq(_T_1399, UInt<1>(0h0)) when _T_1402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1399, UInt<1>(0h1), "") : assert_46 node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(source_ok, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1406 = asUInt(reset) node _T_1407 = eq(_T_1406, UInt<1>(0h0)) when _T_1407 : node _T_1408 = eq(is_aligned, UInt<1>(0h0)) when _T_1408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1409 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1410 = asUInt(reset) node _T_1411 = eq(_T_1410, UInt<1>(0h0)) when _T_1411 : node _T_1412 = eq(_T_1409, UInt<1>(0h0)) when _T_1412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1409, UInt<1>(0h1), "") : assert_49 node _T_1413 = eq(io.in.a.bits.mask, mask) node _T_1414 = asUInt(reset) node _T_1415 = eq(_T_1414, UInt<1>(0h0)) when _T_1415 : node _T_1416 = eq(_T_1413, UInt<1>(0h0)) when _T_1416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1413, UInt<1>(0h1), "") : assert_50 node _T_1417 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1418 = asUInt(reset) node _T_1419 = eq(_T_1418, UInt<1>(0h0)) when _T_1419 : node _T_1420 = eq(_T_1417, UInt<1>(0h0)) when _T_1420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1417, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1421 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1422 = asUInt(reset) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) when _T_1423 : node _T_1424 = eq(_T_1421, UInt<1>(0h0)) when _T_1424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1421, UInt<1>(0h1), "") : assert_52 node _source_ok_T_48 = eq(io.in.d.bits.source, UInt<8>(0h90)) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<6>(0h20)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<6>(0h21)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_61 = shr(io.in.d.bits.source, 2) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<6>(0h22)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_67 = shr(io.in.d.bits.source, 2) node _source_ok_T_68 = eq(_source_ok_T_67, UInt<6>(0h23)) node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_T_71 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<6>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 5, 0) node _source_ok_T_73 = shr(io.in.d.bits.source, 6) node _source_ok_T_74 = eq(_source_ok_T_73, UInt<1>(0h1)) node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_T_77 = leq(source_ok_uncommonBits_10, UInt<6>(0h3f)) node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<6>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 5, 0) node _source_ok_T_79 = shr(io.in.d.bits.source, 6) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_11, UInt<6>(0h3f)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<8>(0ha0)) node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<8>(0ha1)) node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<8>(0ha2)) wire _source_ok_WIRE_1 : UInt<1>[10] connect _source_ok_WIRE_1[0], _source_ok_T_48 connect _source_ok_WIRE_1[1], _source_ok_T_54 connect _source_ok_WIRE_1[2], _source_ok_T_60 connect _source_ok_WIRE_1[3], _source_ok_T_66 connect _source_ok_WIRE_1[4], _source_ok_T_72 connect _source_ok_WIRE_1[5], _source_ok_T_78 connect _source_ok_WIRE_1[6], _source_ok_T_84 connect _source_ok_WIRE_1[7], _source_ok_T_85 connect _source_ok_WIRE_1[8], _source_ok_T_86 connect _source_ok_WIRE_1[9], _source_ok_T_87 node _source_ok_T_88 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE_1[2]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE_1[3]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE_1[4]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[5]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[6]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[7]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[8]) node source_ok_1 = or(_source_ok_T_95, _source_ok_WIRE_1[9]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1425 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1425 : node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(source_ok_1, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1429 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_54 node _T_1433 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1434 = asUInt(reset) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) when _T_1435 : node _T_1436 = eq(_T_1433, UInt<1>(0h0)) when _T_1436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1433, UInt<1>(0h1), "") : assert_55 node _T_1437 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1438 = asUInt(reset) node _T_1439 = eq(_T_1438, UInt<1>(0h0)) when _T_1439 : node _T_1440 = eq(_T_1437, UInt<1>(0h0)) when _T_1440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1437, UInt<1>(0h1), "") : assert_56 node _T_1441 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_57 node _T_1445 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1445 : node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(source_ok_1, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1449 = asUInt(reset) node _T_1450 = eq(_T_1449, UInt<1>(0h0)) when _T_1450 : node _T_1451 = eq(sink_ok, UInt<1>(0h0)) when _T_1451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1452 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_60 node _T_1456 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(_T_1456, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1456, UInt<1>(0h1), "") : assert_61 node _T_1460 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1461 = asUInt(reset) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) when _T_1462 : node _T_1463 = eq(_T_1460, UInt<1>(0h0)) when _T_1463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1460, UInt<1>(0h1), "") : assert_62 node _T_1464 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1465 = asUInt(reset) node _T_1466 = eq(_T_1465, UInt<1>(0h0)) when _T_1466 : node _T_1467 = eq(_T_1464, UInt<1>(0h0)) when _T_1467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1464, UInt<1>(0h1), "") : assert_63 node _T_1468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1469 = or(UInt<1>(0h1), _T_1468) node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(_T_1469, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1469, UInt<1>(0h1), "") : assert_64 node _T_1473 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1473 : node _T_1474 = asUInt(reset) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) when _T_1475 : node _T_1476 = eq(source_ok_1, UInt<1>(0h0)) when _T_1476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1477 = asUInt(reset) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) when _T_1478 : node _T_1479 = eq(sink_ok, UInt<1>(0h0)) when _T_1479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1480 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1481 = asUInt(reset) node _T_1482 = eq(_T_1481, UInt<1>(0h0)) when _T_1482 : node _T_1483 = eq(_T_1480, UInt<1>(0h0)) when _T_1483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1480, UInt<1>(0h1), "") : assert_67 node _T_1484 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(_T_1484, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1484, UInt<1>(0h1), "") : assert_68 node _T_1488 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1489 = asUInt(reset) node _T_1490 = eq(_T_1489, UInt<1>(0h0)) when _T_1490 : node _T_1491 = eq(_T_1488, UInt<1>(0h0)) when _T_1491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1488, UInt<1>(0h1), "") : assert_69 node _T_1492 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1493 = or(_T_1492, io.in.d.bits.corrupt) node _T_1494 = asUInt(reset) node _T_1495 = eq(_T_1494, UInt<1>(0h0)) when _T_1495 : node _T_1496 = eq(_T_1493, UInt<1>(0h0)) when _T_1496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1493, UInt<1>(0h1), "") : assert_70 node _T_1497 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1498 = or(UInt<1>(0h1), _T_1497) node _T_1499 = asUInt(reset) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) when _T_1500 : node _T_1501 = eq(_T_1498, UInt<1>(0h0)) when _T_1501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1498, UInt<1>(0h1), "") : assert_71 node _T_1502 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1502 : node _T_1503 = asUInt(reset) node _T_1504 = eq(_T_1503, UInt<1>(0h0)) when _T_1504 : node _T_1505 = eq(source_ok_1, UInt<1>(0h0)) when _T_1505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1506 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1507 = asUInt(reset) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) when _T_1508 : node _T_1509 = eq(_T_1506, UInt<1>(0h0)) when _T_1509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1506, UInt<1>(0h1), "") : assert_73 node _T_1510 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1511 = asUInt(reset) node _T_1512 = eq(_T_1511, UInt<1>(0h0)) when _T_1512 : node _T_1513 = eq(_T_1510, UInt<1>(0h0)) when _T_1513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1510, UInt<1>(0h1), "") : assert_74 node _T_1514 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1515 = or(UInt<1>(0h1), _T_1514) node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(_T_1515, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1515, UInt<1>(0h1), "") : assert_75 node _T_1519 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1519 : node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(source_ok_1, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1523 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1524 = asUInt(reset) node _T_1525 = eq(_T_1524, UInt<1>(0h0)) when _T_1525 : node _T_1526 = eq(_T_1523, UInt<1>(0h0)) when _T_1526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1523, UInt<1>(0h1), "") : assert_77 node _T_1527 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1528 = or(_T_1527, io.in.d.bits.corrupt) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_78 node _T_1532 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1533 = or(UInt<1>(0h1), _T_1532) node _T_1534 = asUInt(reset) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) when _T_1535 : node _T_1536 = eq(_T_1533, UInt<1>(0h0)) when _T_1536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1533, UInt<1>(0h1), "") : assert_79 node _T_1537 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1537 : node _T_1538 = asUInt(reset) node _T_1539 = eq(_T_1538, UInt<1>(0h0)) when _T_1539 : node _T_1540 = eq(source_ok_1, UInt<1>(0h0)) when _T_1540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1541 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1542 = asUInt(reset) node _T_1543 = eq(_T_1542, UInt<1>(0h0)) when _T_1543 : node _T_1544 = eq(_T_1541, UInt<1>(0h0)) when _T_1544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1541, UInt<1>(0h1), "") : assert_81 node _T_1545 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1546 = asUInt(reset) node _T_1547 = eq(_T_1546, UInt<1>(0h0)) when _T_1547 : node _T_1548 = eq(_T_1545, UInt<1>(0h0)) when _T_1548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1545, UInt<1>(0h1), "") : assert_82 node _T_1549 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1550 = or(UInt<1>(0h1), _T_1549) node _T_1551 = asUInt(reset) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : node _T_1553 = eq(_T_1550, UInt<1>(0h0)) when _T_1553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1550, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1554 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1555 = asUInt(reset) node _T_1556 = eq(_T_1555, UInt<1>(0h0)) when _T_1556 : node _T_1557 = eq(_T_1554, UInt<1>(0h0)) when _T_1557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1554, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1558 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1559 = asUInt(reset) node _T_1560 = eq(_T_1559, UInt<1>(0h0)) when _T_1560 : node _T_1561 = eq(_T_1558, UInt<1>(0h0)) when _T_1561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1558, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1562 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(_T_1562, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1562, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1566 = eq(a_first, UInt<1>(0h0)) node _T_1567 = and(io.in.a.valid, _T_1566) when _T_1567 : node _T_1568 = eq(io.in.a.bits.opcode, opcode) node _T_1569 = asUInt(reset) node _T_1570 = eq(_T_1569, UInt<1>(0h0)) when _T_1570 : node _T_1571 = eq(_T_1568, UInt<1>(0h0)) when _T_1571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1568, UInt<1>(0h1), "") : assert_87 node _T_1572 = eq(io.in.a.bits.param, param) node _T_1573 = asUInt(reset) node _T_1574 = eq(_T_1573, UInt<1>(0h0)) when _T_1574 : node _T_1575 = eq(_T_1572, UInt<1>(0h0)) when _T_1575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1572, UInt<1>(0h1), "") : assert_88 node _T_1576 = eq(io.in.a.bits.size, size) node _T_1577 = asUInt(reset) node _T_1578 = eq(_T_1577, UInt<1>(0h0)) when _T_1578 : node _T_1579 = eq(_T_1576, UInt<1>(0h0)) when _T_1579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1576, UInt<1>(0h1), "") : assert_89 node _T_1580 = eq(io.in.a.bits.source, source) node _T_1581 = asUInt(reset) node _T_1582 = eq(_T_1581, UInt<1>(0h0)) when _T_1582 : node _T_1583 = eq(_T_1580, UInt<1>(0h0)) when _T_1583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1580, UInt<1>(0h1), "") : assert_90 node _T_1584 = eq(io.in.a.bits.address, address) node _T_1585 = asUInt(reset) node _T_1586 = eq(_T_1585, UInt<1>(0h0)) when _T_1586 : node _T_1587 = eq(_T_1584, UInt<1>(0h0)) when _T_1587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1584, UInt<1>(0h1), "") : assert_91 node _T_1588 = and(io.in.a.ready, io.in.a.valid) node _T_1589 = and(_T_1588, a_first) when _T_1589 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1590 = eq(d_first, UInt<1>(0h0)) node _T_1591 = and(io.in.d.valid, _T_1590) when _T_1591 : node _T_1592 = eq(io.in.d.bits.opcode, opcode_1) node _T_1593 = asUInt(reset) node _T_1594 = eq(_T_1593, UInt<1>(0h0)) when _T_1594 : node _T_1595 = eq(_T_1592, UInt<1>(0h0)) when _T_1595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1592, UInt<1>(0h1), "") : assert_92 node _T_1596 = eq(io.in.d.bits.param, param_1) node _T_1597 = asUInt(reset) node _T_1598 = eq(_T_1597, UInt<1>(0h0)) when _T_1598 : node _T_1599 = eq(_T_1596, UInt<1>(0h0)) when _T_1599 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1596, UInt<1>(0h1), "") : assert_93 node _T_1600 = eq(io.in.d.bits.size, size_1) node _T_1601 = asUInt(reset) node _T_1602 = eq(_T_1601, UInt<1>(0h0)) when _T_1602 : node _T_1603 = eq(_T_1600, UInt<1>(0h0)) when _T_1603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1600, UInt<1>(0h1), "") : assert_94 node _T_1604 = eq(io.in.d.bits.source, source_1) node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(_T_1604, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1604, UInt<1>(0h1), "") : assert_95 node _T_1608 = eq(io.in.d.bits.sink, sink) node _T_1609 = asUInt(reset) node _T_1610 = eq(_T_1609, UInt<1>(0h0)) when _T_1610 : node _T_1611 = eq(_T_1608, UInt<1>(0h0)) when _T_1611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1608, UInt<1>(0h1), "") : assert_96 node _T_1612 = eq(io.in.d.bits.denied, denied) node _T_1613 = asUInt(reset) node _T_1614 = eq(_T_1613, UInt<1>(0h0)) when _T_1614 : node _T_1615 = eq(_T_1612, UInt<1>(0h0)) when _T_1615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1612, UInt<1>(0h1), "") : assert_97 node _T_1616 = and(io.in.d.ready, io.in.d.valid) node _T_1617 = and(_T_1616, d_first) when _T_1617 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<163>, clock, reset, UInt<163>(0h0) regreset inflight_opcodes : UInt<652>, clock, reset, UInt<652>(0h0) regreset inflight_sizes : UInt<1304>, clock, reset, UInt<1304>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<163> connect a_set, UInt<163>(0h0) wire a_set_wo_ready : UInt<163> connect a_set_wo_ready, UInt<163>(0h0) wire a_opcodes_set : UInt<652> connect a_opcodes_set, UInt<652>(0h0) wire a_sizes_set : UInt<1304> connect a_sizes_set, UInt<1304>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1618 = and(io.in.a.valid, a_first_1) node _T_1619 = and(_T_1618, UInt<1>(0h1)) when _T_1619 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1620 = and(io.in.a.ready, io.in.a.valid) node _T_1621 = and(_T_1620, a_first_1) node _T_1622 = and(_T_1621, UInt<1>(0h1)) when _T_1622 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1623 = dshr(inflight, io.in.a.bits.source) node _T_1624 = bits(_T_1623, 0, 0) node _T_1625 = eq(_T_1624, UInt<1>(0h0)) node _T_1626 = asUInt(reset) node _T_1627 = eq(_T_1626, UInt<1>(0h0)) when _T_1627 : node _T_1628 = eq(_T_1625, UInt<1>(0h0)) when _T_1628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1625, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<163> connect d_clr, UInt<163>(0h0) wire d_clr_wo_ready : UInt<163> connect d_clr_wo_ready, UInt<163>(0h0) wire d_opcodes_clr : UInt<652> connect d_opcodes_clr, UInt<652>(0h0) wire d_sizes_clr : UInt<1304> connect d_sizes_clr, UInt<1304>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1629 = and(io.in.d.valid, d_first_1) node _T_1630 = and(_T_1629, UInt<1>(0h1)) node _T_1631 = eq(d_release_ack, UInt<1>(0h0)) node _T_1632 = and(_T_1630, _T_1631) when _T_1632 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1633 = and(io.in.d.ready, io.in.d.valid) node _T_1634 = and(_T_1633, d_first_1) node _T_1635 = and(_T_1634, UInt<1>(0h1)) node _T_1636 = eq(d_release_ack, UInt<1>(0h0)) node _T_1637 = and(_T_1635, _T_1636) when _T_1637 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1638 = and(io.in.d.valid, d_first_1) node _T_1639 = and(_T_1638, UInt<1>(0h1)) node _T_1640 = eq(d_release_ack, UInt<1>(0h0)) node _T_1641 = and(_T_1639, _T_1640) when _T_1641 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1642 = dshr(inflight, io.in.d.bits.source) node _T_1643 = bits(_T_1642, 0, 0) node _T_1644 = or(_T_1643, same_cycle_resp) node _T_1645 = asUInt(reset) node _T_1646 = eq(_T_1645, UInt<1>(0h0)) when _T_1646 : node _T_1647 = eq(_T_1644, UInt<1>(0h0)) when _T_1647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1644, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1648 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1649 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1650 = or(_T_1648, _T_1649) node _T_1651 = asUInt(reset) node _T_1652 = eq(_T_1651, UInt<1>(0h0)) when _T_1652 : node _T_1653 = eq(_T_1650, UInt<1>(0h0)) when _T_1653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1650, UInt<1>(0h1), "") : assert_100 node _T_1654 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1655 = asUInt(reset) node _T_1656 = eq(_T_1655, UInt<1>(0h0)) when _T_1656 : node _T_1657 = eq(_T_1654, UInt<1>(0h0)) when _T_1657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1654, UInt<1>(0h1), "") : assert_101 else : node _T_1658 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1659 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1660 = or(_T_1658, _T_1659) node _T_1661 = asUInt(reset) node _T_1662 = eq(_T_1661, UInt<1>(0h0)) when _T_1662 : node _T_1663 = eq(_T_1660, UInt<1>(0h0)) when _T_1663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1660, UInt<1>(0h1), "") : assert_102 node _T_1664 = eq(io.in.d.bits.size, a_size_lookup) node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(_T_1664, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1664, UInt<1>(0h1), "") : assert_103 node _T_1668 = and(io.in.d.valid, d_first_1) node _T_1669 = and(_T_1668, a_first_1) node _T_1670 = and(_T_1669, io.in.a.valid) node _T_1671 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1672 = and(_T_1670, _T_1671) node _T_1673 = eq(d_release_ack, UInt<1>(0h0)) node _T_1674 = and(_T_1672, _T_1673) when _T_1674 : node _T_1675 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1676 = or(_T_1675, io.in.a.ready) node _T_1677 = asUInt(reset) node _T_1678 = eq(_T_1677, UInt<1>(0h0)) when _T_1678 : node _T_1679 = eq(_T_1676, UInt<1>(0h0)) when _T_1679 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1676, UInt<1>(0h1), "") : assert_104 node _T_1680 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1681 = orr(a_set_wo_ready) node _T_1682 = eq(_T_1681, UInt<1>(0h0)) node _T_1683 = or(_T_1680, _T_1682) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_34 node _T_1687 = orr(inflight) node _T_1688 = eq(_T_1687, UInt<1>(0h0)) node _T_1689 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1690 = or(_T_1688, _T_1689) node _T_1691 = lt(watchdog, plusarg_reader.out) node _T_1692 = or(_T_1690, _T_1691) node _T_1693 = asUInt(reset) node _T_1694 = eq(_T_1693, UInt<1>(0h0)) when _T_1694 : node _T_1695 = eq(_T_1692, UInt<1>(0h0)) when _T_1695 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1692, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1696 = and(io.in.a.ready, io.in.a.valid) node _T_1697 = and(io.in.d.ready, io.in.d.valid) node _T_1698 = or(_T_1696, _T_1697) when _T_1698 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<163>, clock, reset, UInt<163>(0h0) regreset inflight_opcodes_1 : UInt<652>, clock, reset, UInt<652>(0h0) regreset inflight_sizes_1 : UInt<1304>, clock, reset, UInt<1304>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<163> connect c_set, UInt<163>(0h0) wire c_set_wo_ready : UInt<163> connect c_set_wo_ready, UInt<163>(0h0) wire c_opcodes_set : UInt<652> connect c_opcodes_set, UInt<652>(0h0) wire c_sizes_set : UInt<1304> connect c_sizes_set, UInt<1304>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1699 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1700 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1701 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1702 = and(_T_1700, _T_1701) node _T_1703 = and(_T_1699, _T_1702) when _T_1703 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1704 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1705 = and(_T_1704, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1706 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1707 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1708 = and(_T_1706, _T_1707) node _T_1709 = and(_T_1705, _T_1708) when _T_1709 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1710 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1711 = bits(_T_1710, 0, 0) node _T_1712 = eq(_T_1711, UInt<1>(0h0)) node _T_1713 = asUInt(reset) node _T_1714 = eq(_T_1713, UInt<1>(0h0)) when _T_1714 : node _T_1715 = eq(_T_1712, UInt<1>(0h0)) when _T_1715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1712, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<163> connect d_clr_1, UInt<163>(0h0) wire d_clr_wo_ready_1 : UInt<163> connect d_clr_wo_ready_1, UInt<163>(0h0) wire d_opcodes_clr_1 : UInt<652> connect d_opcodes_clr_1, UInt<652>(0h0) wire d_sizes_clr_1 : UInt<1304> connect d_sizes_clr_1, UInt<1304>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1716 = and(io.in.d.valid, d_first_2) node _T_1717 = and(_T_1716, UInt<1>(0h1)) node _T_1718 = and(_T_1717, d_release_ack_1) when _T_1718 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1719 = and(io.in.d.ready, io.in.d.valid) node _T_1720 = and(_T_1719, d_first_2) node _T_1721 = and(_T_1720, UInt<1>(0h1)) node _T_1722 = and(_T_1721, d_release_ack_1) when _T_1722 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1723 = and(io.in.d.valid, d_first_2) node _T_1724 = and(_T_1723, UInt<1>(0h1)) node _T_1725 = and(_T_1724, d_release_ack_1) when _T_1725 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1726 = dshr(inflight_1, io.in.d.bits.source) node _T_1727 = bits(_T_1726, 0, 0) node _T_1728 = or(_T_1727, same_cycle_resp_1) node _T_1729 = asUInt(reset) node _T_1730 = eq(_T_1729, UInt<1>(0h0)) when _T_1730 : node _T_1731 = eq(_T_1728, UInt<1>(0h0)) when _T_1731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1728, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1732 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1733 = asUInt(reset) node _T_1734 = eq(_T_1733, UInt<1>(0h0)) when _T_1734 : node _T_1735 = eq(_T_1732, UInt<1>(0h0)) when _T_1735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1732, UInt<1>(0h1), "") : assert_109 else : node _T_1736 = eq(io.in.d.bits.size, c_size_lookup) node _T_1737 = asUInt(reset) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) when _T_1738 : node _T_1739 = eq(_T_1736, UInt<1>(0h0)) when _T_1739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1736, UInt<1>(0h1), "") : assert_110 node _T_1740 = and(io.in.d.valid, d_first_2) node _T_1741 = and(_T_1740, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1742 = and(_T_1741, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1743 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1744 = and(_T_1742, _T_1743) node _T_1745 = and(_T_1744, d_release_ack_1) node _T_1746 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1747 = and(_T_1745, _T_1746) when _T_1747 : node _T_1748 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1749 = or(_T_1748, _WIRE_27.ready) node _T_1750 = asUInt(reset) node _T_1751 = eq(_T_1750, UInt<1>(0h0)) when _T_1751 : node _T_1752 = eq(_T_1749, UInt<1>(0h0)) when _T_1752 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1749, UInt<1>(0h1), "") : assert_111 node _T_1753 = orr(c_set_wo_ready) when _T_1753 : node _T_1754 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1755 = asUInt(reset) node _T_1756 = eq(_T_1755, UInt<1>(0h0)) when _T_1756 : node _T_1757 = eq(_T_1754, UInt<1>(0h0)) when _T_1757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1754, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_35 node _T_1758 = orr(inflight_1) node _T_1759 = eq(_T_1758, UInt<1>(0h0)) node _T_1760 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1761 = or(_T_1759, _T_1760) node _T_1762 = lt(watchdog_1, plusarg_reader_1.out) node _T_1763 = or(_T_1761, _T_1762) node _T_1764 = asUInt(reset) node _T_1765 = eq(_T_1764, UInt<1>(0h0)) when _T_1765 : node _T_1766 = eq(_T_1763, UInt<1>(0h0)) when _T_1766 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1763, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1767 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1768 = and(io.in.d.ready, io.in.d.valid) node _T_1769 = or(_T_1767, _T_1768) when _T_1769 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_36 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_37 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor_17( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [1303:0] c_sizes_set = 1304'h0; // @[Monitor.scala:741:34] wire [651:0] c_opcodes_set = 652'h0; // @[Monitor.scala:740:34] wire [162:0] c_set = 163'h0; // @[Monitor.scala:738:34] wire [162:0] c_set_wo_ready = 163'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_25 = io_in_a_bits_source_0[7:6]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_31 = io_in_a_bits_source_0[7:6]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'hA0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'hA1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'hA2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_47 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_22 = _uncommonBits_T_22[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_23 = _uncommonBits_T_23[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_28 = _uncommonBits_T_28[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_35 = _uncommonBits_T_35[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_40 = _uncommonBits_T_40[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_41 = _uncommonBits_T_41[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_46 = _uncommonBits_T_46[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_47 = _uncommonBits_T_47[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_52 = _uncommonBits_T_52[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_53 = _uncommonBits_T_53[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_58 = _uncommonBits_T_58[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_59 = _uncommonBits_T_59[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_64 = _uncommonBits_T_64[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_65 = _uncommonBits_T_65[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = io_in_d_bits_source_0 == 8'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_49 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_55 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_61 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_67 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_50 = _source_ok_T_49 == 6'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 6'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_62 = _source_ok_T_61 == 6'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_68 = _source_ok_T_67 == 6'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_73 = io_in_d_bits_source_0[7:6]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_79 = io_in_d_bits_source_0[7:6]; // @[Monitor.scala:36:7] wire _source_ok_T_74 = _source_ok_T_73 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_80 = _source_ok_T_79 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire _source_ok_T_85 = io_in_d_bits_source_0 == 8'hA0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire _source_ok_T_86 = io_in_d_bits_source_0 == 8'hA1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_86; // @[Parameters.scala:1138:31] wire _source_ok_T_87 = io_in_d_bits_source_0 == 8'hA2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_87; // @[Parameters.scala:1138:31] wire _source_ok_T_88 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_89 = _source_ok_T_88 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_90 = _source_ok_T_89 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_91 = _source_ok_T_90 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_95 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _T_1696 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1696; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1696; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1769 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1769; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1769; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1769; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [162:0] inflight; // @[Monitor.scala:614:27] reg [651:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1303:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [162:0] a_set; // @[Monitor.scala:626:34] wire [162:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [651:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1303:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [651:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [651:0] _a_opcode_lookup_T_6 = {648'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [651:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[651:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [1303:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1303:0] _a_size_lookup_T_6 = {1296'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [1303:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1303:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[162:0] : 163'h0; // @[OneHot.scala:58:35] wire _T_1622 = _T_1696 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1622 ? _a_set_T[162:0] : 163'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1622 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1622 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1622 ? _a_opcodes_set_T_1[651:0] : 652'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1622 ? _a_sizes_set_T_1[1303:0] : 1304'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [162:0] d_clr; // @[Monitor.scala:664:34] wire [162:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [651:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1303:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1668 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1668 & ~d_release_ack ? _d_clr_wo_ready_T[162:0] : 163'h0; // @[OneHot.scala:58:35] wire _T_1637 = _T_1769 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1637 ? _d_clr_T[162:0] : 163'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1637 ? _d_opcodes_clr_T_5[651:0] : 652'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1637 ? _d_sizes_clr_T_5[1303:0] : 1304'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [162:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [162:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [162:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [651:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [651:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [651:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1303:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1303:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1303:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [162:0] inflight_1; // @[Monitor.scala:726:35] wire [162:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [651:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [651:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1303:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1303:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [651:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [651:0] _c_opcode_lookup_T_6 = {648'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [651:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[651:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1303:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1303:0] _c_size_lookup_T_6 = {1296'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [1303:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1303:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [162:0] d_clr_1; // @[Monitor.scala:774:34] wire [162:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [651:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1303:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1740 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1740 & d_release_ack_1 ? _d_clr_wo_ready_T_1[162:0] : 163'h0; // @[OneHot.scala:58:35] wire _T_1722 = _T_1769 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1722 ? _d_clr_T_1[162:0] : 163'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1722 ? _d_opcodes_clr_T_11[651:0] : 652'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1722 ? _d_sizes_clr_T_11[1303:0] : 1304'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [162:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [162:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [651:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [651:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1303:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1303:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_347 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_347( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLCacheCork : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_15 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in wire a_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} wire a_d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} node _isPut_T = eq(nodeIn.a.bits.opcode, UInt<1>(0h0)) node _isPut_T_1 = eq(nodeIn.a.bits.opcode, UInt<1>(0h1)) node isPut = or(_isPut_T, _isPut_T_1) node _toD_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h6)) node _toD_T_1 = eq(nodeIn.a.bits.param, UInt<2>(0h2)) node _toD_T_2 = and(_toD_T, _toD_T_1) node _toD_T_3 = eq(nodeIn.a.bits.opcode, UInt<3>(0h7)) node toD = or(_toD_T_2, _toD_T_3) node _nodeIn_a_ready_T = mux(toD, a_d.ready, a_a.ready) connect nodeIn.a.ready, _nodeIn_a_ready_T node _a_a_valid_T = eq(toD, UInt<1>(0h0)) node _a_a_valid_T_1 = and(nodeIn.a.valid, _a_a_valid_T) connect a_a.valid, _a_a_valid_T_1 connect a_a.bits, nodeIn.a.bits node _a_a_bits_source_T = shl(nodeIn.a.bits.source, 1) node _a_a_bits_source_T_1 = mux(isPut, UInt<1>(0h1), UInt<1>(0h0)) node _a_a_bits_source_T_2 = or(_a_a_bits_source_T, _a_a_bits_source_T_1) connect a_a.bits.source, _a_a_bits_source_T_2 node _T = eq(nodeIn.a.bits.opcode, UInt<3>(0h6)) node _T_1 = eq(nodeIn.a.bits.opcode, UInt<3>(0h7)) node _T_2 = or(_T, _T_1) when _T_2 : connect a_a.bits.opcode, UInt<3>(0h4) connect a_a.bits.param, UInt<1>(0h0) node _a_a_bits_source_T_3 = shl(nodeIn.a.bits.source, 1) node _a_a_bits_source_T_4 = or(_a_a_bits_source_T_3, UInt<1>(0h1)) connect a_a.bits.source, _a_a_bits_source_T_4 node _a_d_valid_T = and(nodeIn.a.valid, toD) connect a_d.valid, _a_d_valid_T wire a_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect a_d_bits_d.opcode, UInt<3>(0h4) connect a_d_bits_d.param, UInt<2>(0h0) connect a_d_bits_d.size, nodeIn.a.bits.size connect a_d_bits_d.source, nodeIn.a.bits.source connect a_d_bits_d.sink, UInt<1>(0h0) connect a_d_bits_d.denied, UInt<1>(0h0) invalidate a_d_bits_d.data connect a_d_bits_d.corrupt, UInt<1>(0h0) connect a_d.bits.corrupt, a_d_bits_d.corrupt connect a_d.bits.data, a_d_bits_d.data connect a_d.bits.denied, a_d_bits_d.denied connect a_d.bits.sink, a_d_bits_d.sink connect a_d.bits.source, a_d_bits_d.source connect a_d.bits.size, a_d_bits_d.size connect a_d.bits.param, a_d_bits_d.param connect a_d.bits.opcode, a_d_bits_d.opcode wire c_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} node _c_a_valid_T = eq(nodeIn.c.bits.opcode, UInt<3>(0h7)) node _c_a_valid_T_1 = and(nodeIn.c.valid, _c_a_valid_T) connect c_a.valid, _c_a_valid_T_1 node _c_a_bits_T = shl(nodeIn.c.bits.source, 1) node _c_a_bits_legal_T = leq(UInt<1>(0h0), nodeIn.c.bits.size) node _c_a_bits_legal_T_1 = leq(nodeIn.c.bits.size, UInt<3>(0h6)) node _c_a_bits_legal_T_2 = and(_c_a_bits_legal_T, _c_a_bits_legal_T_1) node _c_a_bits_legal_T_3 = or(UInt<1>(0h0), _c_a_bits_legal_T_2) node _c_a_bits_legal_T_4 = xor(nodeIn.c.bits.address, UInt<1>(0h0)) node _c_a_bits_legal_T_5 = cvt(_c_a_bits_legal_T_4) node _c_a_bits_legal_T_6 = and(_c_a_bits_legal_T_5, asSInt(UInt<1>(0h0))) node _c_a_bits_legal_T_7 = asSInt(_c_a_bits_legal_T_6) node _c_a_bits_legal_T_8 = eq(_c_a_bits_legal_T_7, asSInt(UInt<1>(0h0))) node _c_a_bits_legal_T_9 = and(_c_a_bits_legal_T_3, _c_a_bits_legal_T_8) node c_a_bits_legal = or(UInt<1>(0h0), _c_a_bits_legal_T_9) wire c_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect c_a_bits_a.opcode, UInt<1>(0h0) connect c_a_bits_a.param, UInt<1>(0h0) connect c_a_bits_a.size, nodeIn.c.bits.size connect c_a_bits_a.source, _c_a_bits_T connect c_a_bits_a.address, nodeIn.c.bits.address node _c_a_bits_a_mask_sizeOH_T = or(nodeIn.c.bits.size, UInt<3>(0h0)) node c_a_bits_a_mask_sizeOH_shiftAmount = bits(_c_a_bits_a_mask_sizeOH_T, 1, 0) node _c_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), c_a_bits_a_mask_sizeOH_shiftAmount) node _c_a_bits_a_mask_sizeOH_T_2 = bits(_c_a_bits_a_mask_sizeOH_T_1, 2, 0) node c_a_bits_a_mask_sizeOH = or(_c_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node c_a_bits_a_mask_sub_sub_sub_0_1 = geq(nodeIn.c.bits.size, UInt<2>(0h3)) node c_a_bits_a_mask_sub_sub_size = bits(c_a_bits_a_mask_sizeOH, 2, 2) node c_a_bits_a_mask_sub_sub_bit = bits(nodeIn.c.bits.address, 2, 2) node c_a_bits_a_mask_sub_sub_nbit = eq(c_a_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node c_a_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_nbit) node _c_a_bits_a_mask_sub_sub_acc_T = and(c_a_bits_a_mask_sub_sub_size, c_a_bits_a_mask_sub_sub_0_2) node c_a_bits_a_mask_sub_sub_0_1 = or(c_a_bits_a_mask_sub_sub_sub_0_1, _c_a_bits_a_mask_sub_sub_acc_T) node c_a_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_bit) node _c_a_bits_a_mask_sub_sub_acc_T_1 = and(c_a_bits_a_mask_sub_sub_size, c_a_bits_a_mask_sub_sub_1_2) node c_a_bits_a_mask_sub_sub_1_1 = or(c_a_bits_a_mask_sub_sub_sub_0_1, _c_a_bits_a_mask_sub_sub_acc_T_1) node c_a_bits_a_mask_sub_size = bits(c_a_bits_a_mask_sizeOH, 1, 1) node c_a_bits_a_mask_sub_bit = bits(nodeIn.c.bits.address, 1, 1) node c_a_bits_a_mask_sub_nbit = eq(c_a_bits_a_mask_sub_bit, UInt<1>(0h0)) node c_a_bits_a_mask_sub_0_2 = and(c_a_bits_a_mask_sub_sub_0_2, c_a_bits_a_mask_sub_nbit) node _c_a_bits_a_mask_sub_acc_T = and(c_a_bits_a_mask_sub_size, c_a_bits_a_mask_sub_0_2) node c_a_bits_a_mask_sub_0_1 = or(c_a_bits_a_mask_sub_sub_0_1, _c_a_bits_a_mask_sub_acc_T) node c_a_bits_a_mask_sub_1_2 = and(c_a_bits_a_mask_sub_sub_0_2, c_a_bits_a_mask_sub_bit) node _c_a_bits_a_mask_sub_acc_T_1 = and(c_a_bits_a_mask_sub_size, c_a_bits_a_mask_sub_1_2) node c_a_bits_a_mask_sub_1_1 = or(c_a_bits_a_mask_sub_sub_0_1, _c_a_bits_a_mask_sub_acc_T_1) node c_a_bits_a_mask_sub_2_2 = and(c_a_bits_a_mask_sub_sub_1_2, c_a_bits_a_mask_sub_nbit) node _c_a_bits_a_mask_sub_acc_T_2 = and(c_a_bits_a_mask_sub_size, c_a_bits_a_mask_sub_2_2) node c_a_bits_a_mask_sub_2_1 = or(c_a_bits_a_mask_sub_sub_1_1, _c_a_bits_a_mask_sub_acc_T_2) node c_a_bits_a_mask_sub_3_2 = and(c_a_bits_a_mask_sub_sub_1_2, c_a_bits_a_mask_sub_bit) node _c_a_bits_a_mask_sub_acc_T_3 = and(c_a_bits_a_mask_sub_size, c_a_bits_a_mask_sub_3_2) node c_a_bits_a_mask_sub_3_1 = or(c_a_bits_a_mask_sub_sub_1_1, _c_a_bits_a_mask_sub_acc_T_3) node c_a_bits_a_mask_size = bits(c_a_bits_a_mask_sizeOH, 0, 0) node c_a_bits_a_mask_bit = bits(nodeIn.c.bits.address, 0, 0) node c_a_bits_a_mask_nbit = eq(c_a_bits_a_mask_bit, UInt<1>(0h0)) node c_a_bits_a_mask_eq = and(c_a_bits_a_mask_sub_0_2, c_a_bits_a_mask_nbit) node _c_a_bits_a_mask_acc_T = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq) node c_a_bits_a_mask_acc = or(c_a_bits_a_mask_sub_0_1, _c_a_bits_a_mask_acc_T) node c_a_bits_a_mask_eq_1 = and(c_a_bits_a_mask_sub_0_2, c_a_bits_a_mask_bit) node _c_a_bits_a_mask_acc_T_1 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_1) node c_a_bits_a_mask_acc_1 = or(c_a_bits_a_mask_sub_0_1, _c_a_bits_a_mask_acc_T_1) node c_a_bits_a_mask_eq_2 = and(c_a_bits_a_mask_sub_1_2, c_a_bits_a_mask_nbit) node _c_a_bits_a_mask_acc_T_2 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_2) node c_a_bits_a_mask_acc_2 = or(c_a_bits_a_mask_sub_1_1, _c_a_bits_a_mask_acc_T_2) node c_a_bits_a_mask_eq_3 = and(c_a_bits_a_mask_sub_1_2, c_a_bits_a_mask_bit) node _c_a_bits_a_mask_acc_T_3 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_3) node c_a_bits_a_mask_acc_3 = or(c_a_bits_a_mask_sub_1_1, _c_a_bits_a_mask_acc_T_3) node c_a_bits_a_mask_eq_4 = and(c_a_bits_a_mask_sub_2_2, c_a_bits_a_mask_nbit) node _c_a_bits_a_mask_acc_T_4 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_4) node c_a_bits_a_mask_acc_4 = or(c_a_bits_a_mask_sub_2_1, _c_a_bits_a_mask_acc_T_4) node c_a_bits_a_mask_eq_5 = and(c_a_bits_a_mask_sub_2_2, c_a_bits_a_mask_bit) node _c_a_bits_a_mask_acc_T_5 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_5) node c_a_bits_a_mask_acc_5 = or(c_a_bits_a_mask_sub_2_1, _c_a_bits_a_mask_acc_T_5) node c_a_bits_a_mask_eq_6 = and(c_a_bits_a_mask_sub_3_2, c_a_bits_a_mask_nbit) node _c_a_bits_a_mask_acc_T_6 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_6) node c_a_bits_a_mask_acc_6 = or(c_a_bits_a_mask_sub_3_1, _c_a_bits_a_mask_acc_T_6) node c_a_bits_a_mask_eq_7 = and(c_a_bits_a_mask_sub_3_2, c_a_bits_a_mask_bit) node _c_a_bits_a_mask_acc_T_7 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_7) node c_a_bits_a_mask_acc_7 = or(c_a_bits_a_mask_sub_3_1, _c_a_bits_a_mask_acc_T_7) node c_a_bits_a_mask_lo_lo = cat(c_a_bits_a_mask_acc_1, c_a_bits_a_mask_acc) node c_a_bits_a_mask_lo_hi = cat(c_a_bits_a_mask_acc_3, c_a_bits_a_mask_acc_2) node c_a_bits_a_mask_lo = cat(c_a_bits_a_mask_lo_hi, c_a_bits_a_mask_lo_lo) node c_a_bits_a_mask_hi_lo = cat(c_a_bits_a_mask_acc_5, c_a_bits_a_mask_acc_4) node c_a_bits_a_mask_hi_hi = cat(c_a_bits_a_mask_acc_7, c_a_bits_a_mask_acc_6) node c_a_bits_a_mask_hi = cat(c_a_bits_a_mask_hi_hi, c_a_bits_a_mask_hi_lo) node _c_a_bits_a_mask_T = cat(c_a_bits_a_mask_hi, c_a_bits_a_mask_lo) connect c_a_bits_a.mask, _c_a_bits_a_mask_T connect c_a_bits_a.data, nodeIn.c.bits.data connect c_a_bits_a.corrupt, nodeIn.c.bits.corrupt connect c_a.bits, c_a_bits_a wire c_d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} node _c_d_valid_T = eq(nodeIn.c.bits.opcode, UInt<3>(0h6)) node _c_d_valid_T_1 = and(nodeIn.c.valid, _c_d_valid_T) connect c_d.valid, _c_d_valid_T_1 wire c_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect c_d_bits_d.opcode, UInt<3>(0h6) connect c_d_bits_d.param, UInt<1>(0h0) connect c_d_bits_d.size, nodeIn.c.bits.size connect c_d_bits_d.source, nodeIn.c.bits.source connect c_d_bits_d.sink, UInt<1>(0h0) connect c_d_bits_d.denied, UInt<1>(0h0) invalidate c_d_bits_d.data connect c_d_bits_d.corrupt, UInt<1>(0h0) connect c_d.bits.corrupt, c_d_bits_d.corrupt connect c_d.bits.data, c_d_bits_d.data connect c_d.bits.denied, c_d_bits_d.denied connect c_d.bits.sink, c_d_bits_d.sink connect c_d.bits.source, c_d_bits_d.source connect c_d.bits.size, c_d_bits_d.size connect c_d.bits.param, c_d_bits_d.param connect c_d.bits.opcode, c_d_bits_d.opcode node _T_3 = eq(nodeIn.c.valid, UInt<1>(0h0)) node _T_4 = eq(nodeIn.c.bits.opcode, UInt<3>(0h6)) node _T_5 = or(_T_3, _T_4) node _T_6 = eq(nodeIn.c.bits.opcode, UInt<3>(0h7)) node _T_7 = or(_T_5, _T_6) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:116 assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert node _nodeIn_c_ready_T = eq(nodeIn.c.bits.opcode, UInt<3>(0h6)) node _nodeIn_c_ready_T_1 = mux(_nodeIn_c_ready_T, c_d.ready, c_a.ready) connect nodeIn.c.ready, _nodeIn_c_ready_T_1 connect nodeIn.e.ready, UInt<1>(0h1) wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.ready, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_11 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:124 assert (!out.b.valid)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 inst pool of IDPool connect pool.clock, clock connect pool.reset, reset node _pool_io_free_valid_T = and(nodeIn.e.ready, nodeIn.e.valid) connect pool.io.free.valid, _pool_io_free_valid_T connect pool.io.free.bits, nodeIn.e.bits.sink wire in_d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} node _d_first_T = and(in_d.ready, in_d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), in_d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(in_d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T node _d_grant_T = eq(in_d.bits.opcode, UInt<3>(0h5)) node _d_grant_T_1 = eq(in_d.bits.opcode, UInt<3>(0h4)) node d_grant = or(_d_grant_T, _d_grant_T_1) node _pool_io_alloc_ready_T = and(nodeIn.d.ready, nodeIn.d.valid) node _pool_io_alloc_ready_T_1 = and(_pool_io_alloc_ready_T, d_first) node _pool_io_alloc_ready_T_2 = and(_pool_io_alloc_ready_T_1, d_grant) connect pool.io.alloc.ready, _pool_io_alloc_ready_T_2 node _nodeIn_d_valid_T = eq(d_first, UInt<1>(0h0)) node _nodeIn_d_valid_T_1 = or(pool.io.alloc.valid, _nodeIn_d_valid_T) node _nodeIn_d_valid_T_2 = eq(d_grant, UInt<1>(0h0)) node _nodeIn_d_valid_T_3 = or(_nodeIn_d_valid_T_1, _nodeIn_d_valid_T_2) node _nodeIn_d_valid_T_4 = and(in_d.valid, _nodeIn_d_valid_T_3) connect nodeIn.d.valid, _nodeIn_d_valid_T_4 node _in_d_ready_T = eq(d_first, UInt<1>(0h0)) node _in_d_ready_T_1 = or(pool.io.alloc.valid, _in_d_ready_T) node _in_d_ready_T_2 = eq(d_grant, UInt<1>(0h0)) node _in_d_ready_T_3 = or(_in_d_ready_T_1, _in_d_ready_T_2) node _in_d_ready_T_4 = and(nodeIn.d.ready, _in_d_ready_T_3) connect in_d.ready, _in_d_ready_T_4 connect nodeIn.d.bits.corrupt, in_d.bits.corrupt connect nodeIn.d.bits.data, in_d.bits.data connect nodeIn.d.bits.denied, in_d.bits.denied connect nodeIn.d.bits.sink, in_d.bits.sink connect nodeIn.d.bits.source, in_d.bits.source connect nodeIn.d.bits.size, in_d.bits.size connect nodeIn.d.bits.param, in_d.bits.param connect nodeIn.d.bits.opcode, in_d.bits.opcode reg nodeIn_d_bits_sink_r : UInt<3>, clock when d_first : connect nodeIn_d_bits_sink_r, pool.io.alloc.bits node _nodeIn_d_bits_sink_T = mux(d_first, pool.io.alloc.bits, nodeIn_d_bits_sink_r) connect nodeIn.d.bits.sink, _nodeIn_d_bits_sink_T wire d_d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect d_d, nodeOut.d node _d_d_bits_source_T = shr(nodeOut.d.bits.source, 1) connect d_d.bits.source, _d_d_bits_source_T reg wSourceVec : UInt<1>[5], clock node _aWOk_T = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _aWOk_T_1 = cvt(_aWOk_T) node _aWOk_T_2 = and(_aWOk_T_1, asSInt(UInt<1>(0h0))) node _aWOk_T_3 = asSInt(_aWOk_T_2) node _aWOk_T_4 = eq(_aWOk_T_3, asSInt(UInt<1>(0h0))) node _bypass_T = and(UInt<1>(0h0), nodeIn.a.valid) node _bypass_T_1 = eq(nodeIn.a.bits.source, d_d.bits.source) node bypass = and(_bypass_T, _bypass_T_1) node _dWHeld_T = mux(bypass, UInt<1>(0h1), wSourceVec[d_d.bits.source]) reg dWHeld_r : UInt<1>, clock when d_first : connect dWHeld_r, _dWHeld_T node dWHeld = mux(d_first, _dWHeld_T, dWHeld_r) node _T_15 = and(nodeIn.a.ready, nodeIn.a.valid) when _T_15 : connect wSourceVec[nodeIn.a.bits.source], UInt<1>(0h1) node _T_16 = eq(nodeOut.d.bits.opcode, UInt<1>(0h1)) node _T_17 = bits(nodeOut.d.bits.source, 0, 0) node _T_18 = and(_T_16, _T_17) when _T_18 : connect d_d.bits.opcode, UInt<3>(0h5) node _d_d_bits_param_T = mux(dWHeld, UInt<2>(0h0), UInt<2>(0h1)) connect d_d.bits.param, _d_d_bits_param_T node _T_19 = eq(nodeOut.d.bits.opcode, UInt<1>(0h0)) node _T_20 = bits(nodeOut.d.bits.source, 0, 0) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = and(_T_19, _T_21) when _T_22 : connect d_d.bits.opcode, UInt<3>(0h6) node _decode_T = dshl(UInt<6>(0h3f), c_a.bits.size) node _decode_T_1 = bits(_decode_T, 5, 0) node _decode_T_2 = not(_decode_T_1) node decode = shr(_decode_T_2, 3) node _opdata_T = bits(c_a.bits.opcode, 2, 2) node opdata = eq(_opdata_T, UInt<1>(0h0)) node _T_23 = mux(opdata, decode, UInt<1>(0h0)) node _decode_T_3 = dshl(UInt<6>(0h3f), a_a.bits.size) node _decode_T_4 = bits(_decode_T_3, 5, 0) node _decode_T_5 = not(_decode_T_4) node decode_1 = shr(_decode_T_5, 3) node _opdata_T_1 = bits(a_a.bits.opcode, 2, 2) node opdata_1 = eq(_opdata_T_1, UInt<1>(0h0)) node _T_24 = mux(opdata_1, decode_1, UInt<1>(0h0)) regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, nodeOut.a.ready) node _readys_T = cat(a_a.valid, c_a.valid) node _readys_T_1 = shl(_readys_T, 1) node _readys_T_2 = bits(_readys_T_1, 1, 0) node _readys_T_3 = or(_readys_T, _readys_T_2) node _readys_T_4 = bits(_readys_T_3, 1, 0) node _readys_T_5 = shl(_readys_T_4, 1) node _readys_T_6 = bits(_readys_T_5, 1, 0) node _readys_T_7 = not(_readys_T_6) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], c_a.valid) node _winner_T_1 = and(readys[1], a_a.valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T_25 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_26 = eq(winner[0], UInt<1>(0h0)) node _T_27 = or(_T_25, _T_26) node _T_28 = eq(prefixOR_1, UInt<1>(0h0)) node _T_29 = eq(winner[1], UInt<1>(0h0)) node _T_30 = or(_T_28, _T_29) node _T_31 = and(_T_27, _T_30) node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : node _T_34 = eq(_T_31, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_2 assert(clock, _T_31, UInt<1>(0h1), "") : assert_2 node _T_35 = or(c_a.valid, a_a.valid) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = or(winner[0], winner[1]) node _T_38 = or(_T_36, _T_37) node _T_39 = asUInt(reset) node _T_40 = eq(_T_39, UInt<1>(0h0)) when _T_40 : node _T_41 = eq(_T_38, UInt<1>(0h0)) when _T_41 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_3 assert(clock, _T_38, UInt<1>(0h1), "") : assert_3 node maskedBeats_0 = mux(winner[0], _T_23, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], _T_24, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _c_a_ready_T = and(nodeOut.a.ready, allowed[0]) connect c_a.ready, _c_a_ready_T node _a_a_ready_T = and(nodeOut.a.ready, allowed[1]) connect a_a.ready, _a_a_ready_T node _nodeOut_a_valid_T = or(c_a.valid, a_a.valid) node _nodeOut_a_valid_T_1 = mux(state[0], c_a.valid, UInt<1>(0h0)) node _nodeOut_a_valid_T_2 = mux(state[1], a_a.valid, UInt<1>(0h0)) node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2) wire _nodeOut_a_valid_WIRE : UInt<1> connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3 node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE) connect nodeOut.a.valid, _nodeOut_a_valid_T_4 wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _nodeOut_a_bits_T = mux(muxState[0], c_a.bits.corrupt, UInt<1>(0h0)) node _nodeOut_a_bits_T_1 = mux(muxState[1], a_a.bits.corrupt, UInt<1>(0h0)) node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1) wire _nodeOut_a_bits_WIRE_1 : UInt<1> connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2 connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1 node _nodeOut_a_bits_T_3 = mux(muxState[0], c_a.bits.data, UInt<1>(0h0)) node _nodeOut_a_bits_T_4 = mux(muxState[1], a_a.bits.data, UInt<1>(0h0)) node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4) wire _nodeOut_a_bits_WIRE_2 : UInt<64> connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5 connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2 node _nodeOut_a_bits_T_6 = mux(muxState[0], c_a.bits.mask, UInt<1>(0h0)) node _nodeOut_a_bits_T_7 = mux(muxState[1], a_a.bits.mask, UInt<1>(0h0)) node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7) wire _nodeOut_a_bits_WIRE_3 : UInt<8> connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8 connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3 wire _nodeOut_a_bits_WIRE_4 : { } connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4 wire _nodeOut_a_bits_WIRE_5 : { } connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5 node _nodeOut_a_bits_T_9 = mux(muxState[0], c_a.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_T_10 = mux(muxState[1], a_a.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10) wire _nodeOut_a_bits_WIRE_6 : UInt<32> connect _nodeOut_a_bits_WIRE_6, _nodeOut_a_bits_T_11 connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_6 node _nodeOut_a_bits_T_12 = mux(muxState[0], c_a.bits.source, UInt<1>(0h0)) node _nodeOut_a_bits_T_13 = mux(muxState[1], a_a.bits.source, UInt<1>(0h0)) node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13) wire _nodeOut_a_bits_WIRE_7 : UInt<4> connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_14 connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_7 node _nodeOut_a_bits_T_15 = mux(muxState[0], c_a.bits.size, UInt<1>(0h0)) node _nodeOut_a_bits_T_16 = mux(muxState[1], a_a.bits.size, UInt<1>(0h0)) node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16) wire _nodeOut_a_bits_WIRE_8 : UInt<3> connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_17 connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_8 node _nodeOut_a_bits_T_18 = mux(muxState[0], c_a.bits.param, UInt<1>(0h0)) node _nodeOut_a_bits_T_19 = mux(muxState[1], a_a.bits.param, UInt<1>(0h0)) node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19) wire _nodeOut_a_bits_WIRE_9 : UInt<3> connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_20 connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_9 node _nodeOut_a_bits_T_21 = mux(muxState[0], c_a.bits.opcode, UInt<1>(0h0)) node _nodeOut_a_bits_T_22 = mux(muxState[1], a_a.bits.opcode, UInt<1>(0h0)) node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22) wire _nodeOut_a_bits_WIRE_10 : UInt<3> connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_23 connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_10 connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode node _decode_T_6 = dshl(UInt<6>(0h3f), d_d.bits.size) node _decode_T_7 = bits(_decode_T_6, 5, 0) node _decode_T_8 = not(_decode_T_7) node decode_2 = shr(_decode_T_8, 3) node opdata_2 = bits(d_d.bits.opcode, 0, 0) node _T_42 = mux(opdata_2, decode_2, UInt<1>(0h0)) inst q of Queue2_TLBundleD_a32d64s3k3z3c_1 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, c_d.valid connect q.io.enq.bits.corrupt, c_d.bits.corrupt connect q.io.enq.bits.data, c_d.bits.data connect q.io.enq.bits.denied, c_d.bits.denied connect q.io.enq.bits.sink, c_d.bits.sink connect q.io.enq.bits.source, c_d.bits.source connect q.io.enq.bits.size, c_d.bits.size connect q.io.enq.bits.param, c_d.bits.param connect q.io.enq.bits.opcode, c_d.bits.opcode connect c_d.ready, q.io.enq.ready inst q_1 of Queue2_TLBundleD_a32d64s3k3z3c_2 connect q_1.clock, clock connect q_1.reset, reset connect q_1.io.enq.valid, a_d.valid connect q_1.io.enq.bits.corrupt, a_d.bits.corrupt connect q_1.io.enq.bits.data, a_d.bits.data connect q_1.io.enq.bits.denied, a_d.bits.denied connect q_1.io.enq.bits.sink, a_d.bits.sink connect q_1.io.enq.bits.source, a_d.bits.source connect q_1.io.enq.bits.size, a_d.bits.size connect q_1.io.enq.bits.param, a_d.bits.param connect q_1.io.enq.bits.opcode, a_d.bits.opcode connect a_d.ready, q_1.io.enq.ready regreset beatsLeft_1 : UInt, clock, reset, UInt<1>(0h0) node idle_1 = eq(beatsLeft_1, UInt<1>(0h0)) node latch_1 = and(idle_1, in_d.ready) node readys_hi = cat(q_1.io.deq.valid, q.io.deq.valid) node _readys_T_10 = cat(readys_hi, d_d.valid) node _readys_T_11 = shl(_readys_T_10, 1) node _readys_T_12 = bits(_readys_T_11, 2, 0) node _readys_T_13 = or(_readys_T_10, _readys_T_12) node _readys_T_14 = shl(_readys_T_13, 2) node _readys_T_15 = bits(_readys_T_14, 2, 0) node _readys_T_16 = or(_readys_T_13, _readys_T_15) node _readys_T_17 = bits(_readys_T_16, 2, 0) node _readys_T_18 = shl(_readys_T_17, 1) node _readys_T_19 = bits(_readys_T_18, 2, 0) node _readys_T_20 = not(_readys_T_19) node _readys_T_21 = bits(_readys_T_20, 0, 0) node _readys_T_22 = bits(_readys_T_20, 1, 1) node _readys_T_23 = bits(_readys_T_20, 2, 2) wire readys_1 : UInt<1>[3] connect readys_1[0], _readys_T_21 connect readys_1[1], _readys_T_22 connect readys_1[2], _readys_T_23 node _winner_T_2 = and(readys_1[0], d_d.valid) node _winner_T_3 = and(readys_1[1], q.io.deq.valid) node _winner_T_4 = and(readys_1[2], q_1.io.deq.valid) wire winner_1 : UInt<1>[3] connect winner_1[0], _winner_T_2 connect winner_1[1], _winner_T_3 connect winner_1[2], _winner_T_4 node prefixOR_1_1 = or(UInt<1>(0h0), winner_1[0]) node prefixOR_2 = or(prefixOR_1_1, winner_1[1]) node _prefixOR_T_1 = or(prefixOR_2, winner_1[2]) node _T_43 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_44 = eq(winner_1[0], UInt<1>(0h0)) node _T_45 = or(_T_43, _T_44) node _T_46 = eq(prefixOR_1_1, UInt<1>(0h0)) node _T_47 = eq(winner_1[1], UInt<1>(0h0)) node _T_48 = or(_T_46, _T_47) node _T_49 = eq(prefixOR_2, UInt<1>(0h0)) node _T_50 = eq(winner_1[2], UInt<1>(0h0)) node _T_51 = or(_T_49, _T_50) node _T_52 = and(_T_45, _T_48) node _T_53 = and(_T_52, _T_51) node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : node _T_56 = eq(_T_53, UInt<1>(0h0)) when _T_56 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_4 assert(clock, _T_53, UInt<1>(0h1), "") : assert_4 node _T_57 = or(d_d.valid, q.io.deq.valid) node _T_58 = or(_T_57, q_1.io.deq.valid) node _T_59 = eq(_T_58, UInt<1>(0h0)) node _T_60 = or(winner_1[0], winner_1[1]) node _T_61 = or(_T_60, winner_1[2]) node _T_62 = or(_T_59, _T_61) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node maskedBeats_0_1 = mux(winner_1[0], _T_42, UInt<1>(0h0)) node maskedBeats_1_1 = mux(winner_1[1], UInt<1>(0h0), UInt<1>(0h0)) node maskedBeats_2 = mux(winner_1[2], UInt<1>(0h0), UInt<1>(0h0)) node _initBeats_T = or(maskedBeats_0_1, maskedBeats_1_1) node initBeats_1 = or(_initBeats_T, maskedBeats_2) node _beatsLeft_T_4 = and(in_d.ready, in_d.valid) node _beatsLeft_T_5 = sub(beatsLeft_1, _beatsLeft_T_4) node _beatsLeft_T_6 = tail(_beatsLeft_T_5, 1) node _beatsLeft_T_7 = mux(latch_1, initBeats_1, _beatsLeft_T_6) connect beatsLeft_1, _beatsLeft_T_7 wire _state_WIRE_1 : UInt<1>[3] connect _state_WIRE_1[0], UInt<1>(0h0) connect _state_WIRE_1[1], UInt<1>(0h0) connect _state_WIRE_1[2], UInt<1>(0h0) regreset state_1 : UInt<1>[3], clock, reset, _state_WIRE_1 node muxState_1 = mux(idle_1, winner_1, state_1) connect state_1, muxState_1 node allowed_1 = mux(idle_1, readys_1, state_1) node _d_d_ready_T = and(in_d.ready, allowed_1[0]) connect d_d.ready, _d_d_ready_T node _q_io_deq_ready_T = and(in_d.ready, allowed_1[1]) connect q.io.deq.ready, _q_io_deq_ready_T node _q_io_deq_ready_T_1 = and(in_d.ready, allowed_1[2]) connect q_1.io.deq.ready, _q_io_deq_ready_T_1 node _in_d_valid_T = or(d_d.valid, q.io.deq.valid) node _in_d_valid_T_1 = or(_in_d_valid_T, q_1.io.deq.valid) node _in_d_valid_T_2 = mux(state_1[0], d_d.valid, UInt<1>(0h0)) node _in_d_valid_T_3 = mux(state_1[1], q.io.deq.valid, UInt<1>(0h0)) node _in_d_valid_T_4 = mux(state_1[2], q_1.io.deq.valid, UInt<1>(0h0)) node _in_d_valid_T_5 = or(_in_d_valid_T_2, _in_d_valid_T_3) node _in_d_valid_T_6 = or(_in_d_valid_T_5, _in_d_valid_T_4) wire _in_d_valid_WIRE : UInt<1> connect _in_d_valid_WIRE, _in_d_valid_T_6 node _in_d_valid_T_7 = mux(idle_1, _in_d_valid_T_1, _in_d_valid_WIRE) connect in_d.valid, _in_d_valid_T_7 wire _in_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} node _in_d_bits_T = mux(muxState_1[0], d_d.bits.corrupt, UInt<1>(0h0)) node _in_d_bits_T_1 = mux(muxState_1[1], q.io.deq.bits.corrupt, UInt<1>(0h0)) node _in_d_bits_T_2 = mux(muxState_1[2], q_1.io.deq.bits.corrupt, UInt<1>(0h0)) node _in_d_bits_T_3 = or(_in_d_bits_T, _in_d_bits_T_1) node _in_d_bits_T_4 = or(_in_d_bits_T_3, _in_d_bits_T_2) wire _in_d_bits_WIRE_1 : UInt<1> connect _in_d_bits_WIRE_1, _in_d_bits_T_4 connect _in_d_bits_WIRE.corrupt, _in_d_bits_WIRE_1 node _in_d_bits_T_5 = mux(muxState_1[0], d_d.bits.data, UInt<1>(0h0)) node _in_d_bits_T_6 = mux(muxState_1[1], q.io.deq.bits.data, UInt<1>(0h0)) node _in_d_bits_T_7 = mux(muxState_1[2], q_1.io.deq.bits.data, UInt<1>(0h0)) node _in_d_bits_T_8 = or(_in_d_bits_T_5, _in_d_bits_T_6) node _in_d_bits_T_9 = or(_in_d_bits_T_8, _in_d_bits_T_7) wire _in_d_bits_WIRE_2 : UInt<64> connect _in_d_bits_WIRE_2, _in_d_bits_T_9 connect _in_d_bits_WIRE.data, _in_d_bits_WIRE_2 wire _in_d_bits_WIRE_3 : { } connect _in_d_bits_WIRE.echo, _in_d_bits_WIRE_3 wire _in_d_bits_WIRE_4 : { } connect _in_d_bits_WIRE.user, _in_d_bits_WIRE_4 node _in_d_bits_T_10 = mux(muxState_1[0], d_d.bits.denied, UInt<1>(0h0)) node _in_d_bits_T_11 = mux(muxState_1[1], q.io.deq.bits.denied, UInt<1>(0h0)) node _in_d_bits_T_12 = mux(muxState_1[2], q_1.io.deq.bits.denied, UInt<1>(0h0)) node _in_d_bits_T_13 = or(_in_d_bits_T_10, _in_d_bits_T_11) node _in_d_bits_T_14 = or(_in_d_bits_T_13, _in_d_bits_T_12) wire _in_d_bits_WIRE_5 : UInt<1> connect _in_d_bits_WIRE_5, _in_d_bits_T_14 connect _in_d_bits_WIRE.denied, _in_d_bits_WIRE_5 node _in_d_bits_T_15 = mux(muxState_1[0], d_d.bits.sink, UInt<1>(0h0)) node _in_d_bits_T_16 = mux(muxState_1[1], q.io.deq.bits.sink, UInt<1>(0h0)) node _in_d_bits_T_17 = mux(muxState_1[2], q_1.io.deq.bits.sink, UInt<1>(0h0)) node _in_d_bits_T_18 = or(_in_d_bits_T_15, _in_d_bits_T_16) node _in_d_bits_T_19 = or(_in_d_bits_T_18, _in_d_bits_T_17) wire _in_d_bits_WIRE_6 : UInt<3> connect _in_d_bits_WIRE_6, _in_d_bits_T_19 connect _in_d_bits_WIRE.sink, _in_d_bits_WIRE_6 node _in_d_bits_T_20 = mux(muxState_1[0], d_d.bits.source, UInt<1>(0h0)) node _in_d_bits_T_21 = mux(muxState_1[1], q.io.deq.bits.source, UInt<1>(0h0)) node _in_d_bits_T_22 = mux(muxState_1[2], q_1.io.deq.bits.source, UInt<1>(0h0)) node _in_d_bits_T_23 = or(_in_d_bits_T_20, _in_d_bits_T_21) node _in_d_bits_T_24 = or(_in_d_bits_T_23, _in_d_bits_T_22) wire _in_d_bits_WIRE_7 : UInt<3> connect _in_d_bits_WIRE_7, _in_d_bits_T_24 connect _in_d_bits_WIRE.source, _in_d_bits_WIRE_7 node _in_d_bits_T_25 = mux(muxState_1[0], d_d.bits.size, UInt<1>(0h0)) node _in_d_bits_T_26 = mux(muxState_1[1], q.io.deq.bits.size, UInt<1>(0h0)) node _in_d_bits_T_27 = mux(muxState_1[2], q_1.io.deq.bits.size, UInt<1>(0h0)) node _in_d_bits_T_28 = or(_in_d_bits_T_25, _in_d_bits_T_26) node _in_d_bits_T_29 = or(_in_d_bits_T_28, _in_d_bits_T_27) wire _in_d_bits_WIRE_8 : UInt<3> connect _in_d_bits_WIRE_8, _in_d_bits_T_29 connect _in_d_bits_WIRE.size, _in_d_bits_WIRE_8 node _in_d_bits_T_30 = mux(muxState_1[0], d_d.bits.param, UInt<1>(0h0)) node _in_d_bits_T_31 = mux(muxState_1[1], q.io.deq.bits.param, UInt<1>(0h0)) node _in_d_bits_T_32 = mux(muxState_1[2], q_1.io.deq.bits.param, UInt<1>(0h0)) node _in_d_bits_T_33 = or(_in_d_bits_T_30, _in_d_bits_T_31) node _in_d_bits_T_34 = or(_in_d_bits_T_33, _in_d_bits_T_32) wire _in_d_bits_WIRE_9 : UInt<2> connect _in_d_bits_WIRE_9, _in_d_bits_T_34 connect _in_d_bits_WIRE.param, _in_d_bits_WIRE_9 node _in_d_bits_T_35 = mux(muxState_1[0], d_d.bits.opcode, UInt<1>(0h0)) node _in_d_bits_T_36 = mux(muxState_1[1], q.io.deq.bits.opcode, UInt<1>(0h0)) node _in_d_bits_T_37 = mux(muxState_1[2], q_1.io.deq.bits.opcode, UInt<1>(0h0)) node _in_d_bits_T_38 = or(_in_d_bits_T_35, _in_d_bits_T_36) node _in_d_bits_T_39 = or(_in_d_bits_T_38, _in_d_bits_T_37) wire _in_d_bits_WIRE_10 : UInt<3> connect _in_d_bits_WIRE_10, _in_d_bits_T_39 connect _in_d_bits_WIRE.opcode, _in_d_bits_WIRE_10 connect in_d.bits.corrupt, _in_d_bits_WIRE.corrupt connect in_d.bits.data, _in_d_bits_WIRE.data connect in_d.bits.denied, _in_d_bits_WIRE.denied connect in_d.bits.sink, _in_d_bits_WIRE.sink connect in_d.bits.source, _in_d_bits_WIRE.source connect in_d.bits.size, _in_d_bits_WIRE.size connect in_d.bits.param, _in_d_bits_WIRE.param connect in_d.bits.opcode, _in_d_bits_WIRE.opcode connect nodeIn.b.valid, UInt<1>(0h0) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<4>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<3>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.valid, UInt<1>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_6.bits.sink, UInt<1>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0)
module TLCacheCork( // @[CacheCork.scala:42:9] input clock, // @[CacheCork.scala:42:9] input reset, // @[CacheCork.scala:42:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _q_1_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _q_1_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _q_1_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _q_1_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [2:0] _q_1_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [2:0] _q_1_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _q_1_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire [63:0] _q_1_io_deq_bits_data; // @[Decoupled.scala:362:21] wire _q_1_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [2:0] _q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [2:0] _q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire [63:0] _q_io_deq_bits_data; // @[Decoupled.scala:362:21] wire _q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _pool_io_alloc_valid; // @[CacheCork.scala:127:26] wire [2:0] _pool_io_alloc_bits; // @[CacheCork.scala:127:26] wire auto_in_a_valid_0 = auto_in_a_valid; // @[CacheCork.scala:42:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[CacheCork.scala:42:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[CacheCork.scala:42:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[CacheCork.scala:42:9] wire [2:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[CacheCork.scala:42:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[CacheCork.scala:42:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[CacheCork.scala:42:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[CacheCork.scala:42:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[CacheCork.scala:42:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[CacheCork.scala:42:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[CacheCork.scala:42:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[CacheCork.scala:42:9] wire [2:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[CacheCork.scala:42:9] wire [2:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[CacheCork.scala:42:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[CacheCork.scala:42:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[CacheCork.scala:42:9] wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[CacheCork.scala:42:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[CacheCork.scala:42:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[CacheCork.scala:42:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[CacheCork.scala:42:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[CacheCork.scala:42:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[CacheCork.scala:42:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[CacheCork.scala:42:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[CacheCork.scala:42:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[CacheCork.scala:42:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[CacheCork.scala:42:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[CacheCork.scala:42:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[CacheCork.scala:42:9] wire auto_in_b_ready = 1'h1; // @[CacheCork.scala:42:9] wire auto_in_e_ready = 1'h1; // @[CacheCork.scala:42:9] wire nodeIn_b_ready = 1'h1; // @[MixedNode.scala:551:17] wire nodeIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire _c_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _c_a_bits_legal_T_8 = 1'h1; // @[Parameters.scala:137:59] wire _aWOk_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _dWHeld_T = 1'h1; // @[CacheCork.scala:151:25] wire opdata = 1'h1; // @[Edges.scala:92:28] wire auto_in_b_valid = 1'h0; // @[CacheCork.scala:42:9] wire auto_in_b_bits_corrupt = 1'h0; // @[CacheCork.scala:42:9] wire auto_out_d_bits_sink = 1'h0; // @[CacheCork.scala:42:9] wire nodeIn_b_valid = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire a_d_bits_denied = 1'h0; // @[CacheCork.scala:75:23] wire a_d_bits_corrupt = 1'h0; // @[CacheCork.scala:75:23] wire a_d_bits_d_denied = 1'h0; // @[Edges.scala:645:17] wire a_d_bits_d_corrupt = 1'h0; // @[Edges.scala:645:17] wire c_d_bits_denied = 1'h0; // @[CacheCork.scala:112:23] wire c_d_bits_corrupt = 1'h0; // @[CacheCork.scala:112:23] wire c_d_bits_d_denied = 1'h0; // @[Edges.scala:677:17] wire c_d_bits_d_corrupt = 1'h0; // @[Edges.scala:677:17] wire _bypass_T = 1'h0; // @[CacheCork.scala:150:57] wire bypass = 1'h0; // @[CacheCork.scala:150:71] wire _opdata_T = 1'h0; // @[Edges.scala:92:37] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire maskedBeats_1_1 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_2 = 1'h0; // @[Arbiter.scala:82:69] wire _state_WIRE_1_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_2 = 1'h0; // @[Arbiter.scala:88:34] wire [2:0] auto_in_b_bits_opcode = 3'h0; // @[CacheCork.scala:42:9] wire [2:0] auto_in_b_bits_size = 3'h0; // @[CacheCork.scala:42:9] wire [2:0] auto_in_b_bits_source = 3'h0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_size = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_source = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] a_d_bits_sink = 3'h0; // @[CacheCork.scala:75:23] wire [2:0] a_d_bits_d_sink = 3'h0; // @[Edges.scala:645:17] wire [2:0] c_a_bits_opcode = 3'h0; // @[CacheCork.scala:101:23] wire [2:0] c_a_bits_param = 3'h0; // @[CacheCork.scala:101:23] wire [2:0] c_a_bits_a_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] c_a_bits_a_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] c_d_bits_sink = 3'h0; // @[CacheCork.scala:112:23] wire [2:0] c_d_bits_d_sink = 3'h0; // @[Edges.scala:677:17] wire [2:0] d_d_bits_sink = 3'h0; // @[CacheCork.scala:141:23] wire [2:0] _nodeOut_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_21 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_d_bits_T_15 = 3'h0; // @[Mux.scala:30:73] wire [1:0] auto_in_b_bits_param = 2'h0; // @[CacheCork.scala:42:9] wire [1:0] auto_out_d_bits_param = 2'h0; // @[CacheCork.scala:42:9] wire [1:0] nodeIn_b_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] a_d_bits_param = 2'h0; // @[CacheCork.scala:75:23] wire [1:0] a_d_bits_d_param = 2'h0; // @[Edges.scala:645:17] wire [1:0] c_d_bits_param = 2'h0; // @[CacheCork.scala:112:23] wire [1:0] c_d_bits_d_param = 2'h0; // @[Edges.scala:677:17] wire [31:0] auto_in_b_bits_address = 32'h0; // @[CacheCork.scala:42:9] wire [31:0] nodeIn_b_bits_address = 32'h0; // @[MixedNode.scala:551:17] wire [7:0] auto_in_b_bits_mask = 8'h0; // @[CacheCork.scala:42:9] wire [7:0] nodeIn_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17] wire [63:0] auto_in_b_bits_data = 64'h0; // @[CacheCork.scala:42:9] wire [63:0] nodeIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] a_d_bits_data = 64'h0; // @[CacheCork.scala:75:23] wire [63:0] a_d_bits_d_data = 64'h0; // @[Edges.scala:645:17] wire [63:0] c_d_bits_data = 64'h0; // @[CacheCork.scala:112:23] wire [63:0] c_d_bits_d_data = 64'h0; // @[Edges.scala:677:17] wire [2:0] a_d_bits_opcode = 3'h4; // @[CacheCork.scala:75:23] wire [2:0] a_d_bits_d_opcode = 3'h4; // @[Edges.scala:645:17] wire [2:0] c_d_bits_opcode = 3'h6; // @[CacheCork.scala:112:23] wire [2:0] c_d_bits_d_opcode = 3'h6; // @[Edges.scala:677:17] wire [32:0] _c_a_bits_legal_T_6 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _c_a_bits_legal_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _aWOk_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _aWOk_T_3 = 33'h0; // @[Parameters.scala:137:46] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[CacheCork.scala:42:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[CacheCork.scala:42:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[CacheCork.scala:42:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[CacheCork.scala:42:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[CacheCork.scala:42:9] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[CacheCork.scala:42:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[CacheCork.scala:42:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[CacheCork.scala:42:9] wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[CacheCork.scala:42:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[CacheCork.scala:42:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[CacheCork.scala:42:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[CacheCork.scala:42:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[CacheCork.scala:42:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[CacheCork.scala:42:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[CacheCork.scala:42:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[CacheCork.scala:42:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[CacheCork.scala:42:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[CacheCork.scala:42:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[CacheCork.scala:42:9] wire auto_in_a_ready_0; // @[CacheCork.scala:42:9] wire auto_in_c_ready_0; // @[CacheCork.scala:42:9] wire [2:0] auto_in_d_bits_opcode_0; // @[CacheCork.scala:42:9] wire [1:0] auto_in_d_bits_param_0; // @[CacheCork.scala:42:9] wire [2:0] auto_in_d_bits_size_0; // @[CacheCork.scala:42:9] wire [2:0] auto_in_d_bits_source_0; // @[CacheCork.scala:42:9] wire [2:0] auto_in_d_bits_sink_0; // @[CacheCork.scala:42:9] wire auto_in_d_bits_denied_0; // @[CacheCork.scala:42:9] wire [63:0] auto_in_d_bits_data_0; // @[CacheCork.scala:42:9] wire auto_in_d_bits_corrupt_0; // @[CacheCork.scala:42:9] wire auto_in_d_valid_0; // @[CacheCork.scala:42:9] wire [2:0] auto_out_a_bits_opcode_0; // @[CacheCork.scala:42:9] wire [2:0] auto_out_a_bits_param_0; // @[CacheCork.scala:42:9] wire [2:0] auto_out_a_bits_size_0; // @[CacheCork.scala:42:9] wire [3:0] auto_out_a_bits_source_0; // @[CacheCork.scala:42:9] wire [31:0] auto_out_a_bits_address_0; // @[CacheCork.scala:42:9] wire [7:0] auto_out_a_bits_mask_0; // @[CacheCork.scala:42:9] wire [63:0] auto_out_a_bits_data_0; // @[CacheCork.scala:42:9] wire auto_out_a_bits_corrupt_0; // @[CacheCork.scala:42:9] wire auto_out_a_valid_0; // @[CacheCork.scala:42:9] wire auto_out_d_ready_0; // @[CacheCork.scala:42:9] wire _nodeIn_a_ready_T; // @[CacheCork.scala:79:26] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[CacheCork.scala:42:9] wire [2:0] a_a_bits_size = nodeIn_a_bits_size; // @[CacheCork.scala:74:23] wire [2:0] a_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:645:17] wire [2:0] a_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:645:17] wire [31:0] a_a_bits_address = nodeIn_a_bits_address; // @[CacheCork.scala:74:23] wire [31:0] _aWOk_T = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [7:0] a_a_bits_mask = nodeIn_a_bits_mask; // @[CacheCork.scala:74:23] wire [63:0] a_a_bits_data = nodeIn_a_bits_data; // @[CacheCork.scala:74:23] wire a_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[CacheCork.scala:74:23] wire _nodeIn_c_ready_T_1; // @[CacheCork.scala:117:26] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[CacheCork.scala:42:9] wire [2:0] c_a_bits_a_size = nodeIn_c_bits_size; // @[Edges.scala:480:17] wire [2:0] _c_a_bits_a_mask_sizeOH_T = nodeIn_c_bits_size; // @[Misc.scala:202:34] wire [2:0] c_d_bits_d_size = nodeIn_c_bits_size; // @[Edges.scala:677:17] wire [2:0] c_d_bits_d_source = nodeIn_c_bits_source; // @[Edges.scala:677:17] wire [31:0] _c_a_bits_legal_T_4 = nodeIn_c_bits_address; // @[Parameters.scala:137:31] wire [31:0] c_a_bits_a_address = nodeIn_c_bits_address; // @[Edges.scala:480:17] wire [63:0] c_a_bits_a_data = nodeIn_c_bits_data; // @[Edges.scala:480:17] wire c_a_bits_a_corrupt = nodeIn_c_bits_corrupt; // @[Edges.scala:480:17] wire _nodeIn_d_valid_T_4; // @[CacheCork.scala:135:34] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[CacheCork.scala:42:9] wire [2:0] in_d_bits_opcode; // @[CacheCork.scala:131:24] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CacheCork.scala:42:9] wire [1:0] in_d_bits_param; // @[CacheCork.scala:131:24] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[CacheCork.scala:42:9] wire [2:0] in_d_bits_size; // @[CacheCork.scala:131:24] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[CacheCork.scala:42:9] wire [2:0] in_d_bits_source; // @[CacheCork.scala:131:24] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[CacheCork.scala:42:9] wire [2:0] _nodeIn_d_bits_sink_T; // @[package.scala:88:42] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[CacheCork.scala:42:9] wire in_d_bits_denied; // @[CacheCork.scala:131:24] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[CacheCork.scala:42:9] wire [63:0] in_d_bits_data; // @[CacheCork.scala:131:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[CacheCork.scala:42:9] wire in_d_bits_corrupt; // @[CacheCork.scala:131:24] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[CacheCork.scala:42:9] wire _pool_io_free_valid_T = nodeIn_e_valid; // @[Decoupled.scala:51:35] wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[CacheCork.scala:42:9] wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[CacheCork.scala:42:9] wire [2:0] _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[CacheCork.scala:42:9] wire [2:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[CacheCork.scala:42:9] wire [3:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[CacheCork.scala:42:9] wire [31:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[CacheCork.scala:42:9] wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[CacheCork.scala:42:9] wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[CacheCork.scala:42:9] wire _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[CacheCork.scala:42:9] wire d_d_ready; // @[CacheCork.scala:141:23] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[CacheCork.scala:42:9] wire d_d_valid = nodeOut_d_valid; // @[CacheCork.scala:141:23] wire [2:0] d_d_bits_size = nodeOut_d_bits_size; // @[CacheCork.scala:141:23] wire d_d_bits_denied = nodeOut_d_bits_denied; // @[CacheCork.scala:141:23] wire [63:0] d_d_bits_data = nodeOut_d_bits_data; // @[CacheCork.scala:141:23] wire d_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[CacheCork.scala:141:23] wire _a_a_ready_T; // @[Arbiter.scala:94:31] wire _a_a_valid_T_1; // @[CacheCork.scala:81:33] wire [2:0] a_a_bits_opcode; // @[CacheCork.scala:74:23] wire [2:0] a_a_bits_param; // @[CacheCork.scala:74:23] wire [3:0] a_a_bits_source; // @[CacheCork.scala:74:23] wire a_a_ready; // @[CacheCork.scala:74:23] wire a_a_valid; // @[CacheCork.scala:74:23] wire _a_d_valid_T; // @[CacheCork.scala:93:33] wire [2:0] a_d_bits_size; // @[CacheCork.scala:75:23] wire [2:0] a_d_bits_source; // @[CacheCork.scala:75:23] wire a_d_ready; // @[CacheCork.scala:75:23] wire a_d_valid; // @[CacheCork.scala:75:23] wire _isPut_T = nodeIn_a_bits_opcode == 3'h0; // @[CacheCork.scala:76:38] wire _isPut_T_1 = nodeIn_a_bits_opcode == 3'h1; // @[CacheCork.scala:76:74] wire isPut = _isPut_T | _isPut_T_1; // @[CacheCork.scala:76:{38,54,74}] wire _a_a_bits_source_T_1 = isPut; // @[CacheCork.scala:76:54, :83:55] wire _toD_T = nodeIn_a_bits_opcode == 3'h6; // @[CacheCork.scala:77:37] wire _toD_T_1 = nodeIn_a_bits_param == 3'h2; // @[CacheCork.scala:77:73] wire _toD_T_2 = _toD_T & _toD_T_1; // @[CacheCork.scala:77:{37,54,73}] wire _toD_T_3 = &nodeIn_a_bits_opcode; // @[CacheCork.scala:78:37] wire toD = _toD_T_2 | _toD_T_3; // @[CacheCork.scala:77:{54,97}, :78:37] assign _nodeIn_a_ready_T = toD ? a_d_ready : a_a_ready; // @[CacheCork.scala:74:23, :75:23, :77:97, :79:26] assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[CacheCork.scala:79:26] wire _a_a_valid_T = ~toD; // @[CacheCork.scala:77:97, :81:36] assign _a_a_valid_T_1 = nodeIn_a_valid & _a_a_valid_T; // @[CacheCork.scala:81:{33,36}] assign a_a_valid = _a_a_valid_T_1; // @[CacheCork.scala:74:23, :81:33] wire [3:0] _GEN = {nodeIn_a_bits_source, 1'h0}; // @[CacheCork.scala:83:45] wire [3:0] _a_a_bits_source_T; // @[CacheCork.scala:83:45] assign _a_a_bits_source_T = _GEN; // @[CacheCork.scala:83:45] wire [3:0] _a_a_bits_source_T_3; // @[CacheCork.scala:89:47] assign _a_a_bits_source_T_3 = _GEN; // @[CacheCork.scala:83:45, :89:47] wire [3:0] _a_a_bits_source_T_2 = {_a_a_bits_source_T[3:1], _a_a_bits_source_T[0] | _a_a_bits_source_T_1}; // @[CacheCork.scala:83:{45,50,55}] wire _T_2 = _toD_T | (&nodeIn_a_bits_opcode); // @[CacheCork.scala:77:37, :78:37, :86:49] assign a_a_bits_opcode = _T_2 ? 3'h4 : nodeIn_a_bits_opcode; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :87:27] assign a_a_bits_param = _T_2 ? 3'h0 : nodeIn_a_bits_param; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :88:27] wire [3:0] _a_a_bits_source_T_4 = {_a_a_bits_source_T_3[3:1], 1'h1}; // @[CacheCork.scala:89:{47,52}] assign a_a_bits_source = _T_2 ? _a_a_bits_source_T_4 : _a_a_bits_source_T_2; // @[CacheCork.scala:74:23, :83:{25,50}, :86:{49,86}, :89:{27,52}] assign _a_d_valid_T = nodeIn_a_valid & toD; // @[CacheCork.scala:77:97, :93:33] assign a_d_valid = _a_d_valid_T; // @[CacheCork.scala:75:23, :93:33] assign a_d_bits_size = a_d_bits_d_size; // @[Edges.scala:645:17] assign a_d_bits_source = a_d_bits_d_source; // @[Edges.scala:645:17] wire _c_a_ready_T; // @[Arbiter.scala:94:31] wire _c_a_valid_T_1; // @[CacheCork.scala:102:33] wire [3:0] c_a_bits_a_source; // @[Edges.scala:480:17] wire [7:0] c_a_bits_a_mask; // @[Edges.scala:480:17] wire [2:0] c_a_bits_size; // @[CacheCork.scala:101:23] wire [3:0] c_a_bits_source; // @[CacheCork.scala:101:23] wire [31:0] c_a_bits_address; // @[CacheCork.scala:101:23] wire [7:0] c_a_bits_mask; // @[CacheCork.scala:101:23] wire [63:0] c_a_bits_data; // @[CacheCork.scala:101:23] wire c_a_bits_corrupt; // @[CacheCork.scala:101:23] wire c_a_ready; // @[CacheCork.scala:101:23] wire c_a_valid; // @[CacheCork.scala:101:23] wire _c_a_valid_T = &nodeIn_c_bits_opcode; // @[CacheCork.scala:102:53] assign _c_a_valid_T_1 = nodeIn_c_valid & _c_a_valid_T; // @[CacheCork.scala:102:{33,53}] assign c_a_valid = _c_a_valid_T_1; // @[CacheCork.scala:101:23, :102:33] wire [3:0] _c_a_bits_T = {nodeIn_c_bits_source, 1'h0}; // @[CacheCork.scala:104:41] assign c_a_bits_a_source = _c_a_bits_T; // @[Edges.scala:480:17] wire _c_a_bits_legal_T_1 = nodeIn_c_bits_size != 3'h7; // @[Parameters.scala:92:38] wire _c_a_bits_legal_T_2 = _c_a_bits_legal_T_1; // @[Parameters.scala:92:{33,38}] wire _c_a_bits_legal_T_3 = _c_a_bits_legal_T_2; // @[Parameters.scala:684:29] wire _c_a_bits_legal_T_9 = _c_a_bits_legal_T_3; // @[Parameters.scala:684:{29,54}] wire [32:0] _c_a_bits_legal_T_5 = {1'h0, _c_a_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire c_a_bits_legal = _c_a_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26] assign c_a_bits_size = c_a_bits_a_size; // @[Edges.scala:480:17] assign c_a_bits_source = c_a_bits_a_source; // @[Edges.scala:480:17] assign c_a_bits_address = c_a_bits_a_address; // @[Edges.scala:480:17] wire [7:0] _c_a_bits_a_mask_T; // @[Misc.scala:222:10] assign c_a_bits_mask = c_a_bits_a_mask; // @[Edges.scala:480:17] assign c_a_bits_data = c_a_bits_a_data; // @[Edges.scala:480:17] assign c_a_bits_corrupt = c_a_bits_a_corrupt; // @[Edges.scala:480:17] wire [1:0] c_a_bits_a_mask_sizeOH_shiftAmount = _c_a_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _c_a_bits_a_mask_sizeOH_T_1 = 4'h1 << c_a_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _c_a_bits_a_mask_sizeOH_T_2 = _c_a_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] c_a_bits_a_mask_sizeOH = {_c_a_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire c_a_bits_a_mask_sub_sub_sub_0_1 = nodeIn_c_bits_size > 3'h2; // @[Misc.scala:206:21] wire c_a_bits_a_mask_sub_sub_size = c_a_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire c_a_bits_a_mask_sub_sub_bit = nodeIn_c_bits_address[2]; // @[Misc.scala:210:26] wire c_a_bits_a_mask_sub_sub_1_2 = c_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire c_a_bits_a_mask_sub_sub_nbit = ~c_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire c_a_bits_a_mask_sub_sub_0_2 = c_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_sub_sub_acc_T = c_a_bits_a_mask_sub_sub_size & c_a_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_sub_0_1 = c_a_bits_a_mask_sub_sub_sub_0_1 | _c_a_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _c_a_bits_a_mask_sub_sub_acc_T_1 = c_a_bits_a_mask_sub_sub_size & c_a_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_sub_1_1 = c_a_bits_a_mask_sub_sub_sub_0_1 | _c_a_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire c_a_bits_a_mask_sub_size = c_a_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire c_a_bits_a_mask_sub_bit = nodeIn_c_bits_address[1]; // @[Misc.scala:210:26] wire c_a_bits_a_mask_sub_nbit = ~c_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire c_a_bits_a_mask_sub_0_2 = c_a_bits_a_mask_sub_sub_0_2 & c_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_sub_acc_T = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_0_1 = c_a_bits_a_mask_sub_sub_0_1 | _c_a_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_sub_1_2 = c_a_bits_a_mask_sub_sub_0_2 & c_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_sub_acc_T_1 = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_1_1 = c_a_bits_a_mask_sub_sub_0_1 | _c_a_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_sub_2_2 = c_a_bits_a_mask_sub_sub_1_2 & c_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_sub_acc_T_2 = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_2_1 = c_a_bits_a_mask_sub_sub_1_1 | _c_a_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_sub_3_2 = c_a_bits_a_mask_sub_sub_1_2 & c_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_sub_acc_T_3 = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_3_1 = c_a_bits_a_mask_sub_sub_1_1 | _c_a_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_size = c_a_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire c_a_bits_a_mask_bit = nodeIn_c_bits_address[0]; // @[Misc.scala:210:26] wire c_a_bits_a_mask_nbit = ~c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire c_a_bits_a_mask_eq = c_a_bits_a_mask_sub_0_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_acc_T = c_a_bits_a_mask_size & c_a_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc = c_a_bits_a_mask_sub_0_1 | _c_a_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_1 = c_a_bits_a_mask_sub_0_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_acc_T_1 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_1 = c_a_bits_a_mask_sub_0_1 | _c_a_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_2 = c_a_bits_a_mask_sub_1_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_acc_T_2 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_2 = c_a_bits_a_mask_sub_1_1 | _c_a_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_3 = c_a_bits_a_mask_sub_1_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_acc_T_3 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_3 = c_a_bits_a_mask_sub_1_1 | _c_a_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_4 = c_a_bits_a_mask_sub_2_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_acc_T_4 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_4 = c_a_bits_a_mask_sub_2_1 | _c_a_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_5 = c_a_bits_a_mask_sub_2_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_acc_T_5 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_5 = c_a_bits_a_mask_sub_2_1 | _c_a_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_6 = c_a_bits_a_mask_sub_3_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_acc_T_6 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_6 = c_a_bits_a_mask_sub_3_1 | _c_a_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_7 = c_a_bits_a_mask_sub_3_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_acc_T_7 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_7 = c_a_bits_a_mask_sub_3_1 | _c_a_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] c_a_bits_a_mask_lo_lo = {c_a_bits_a_mask_acc_1, c_a_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] c_a_bits_a_mask_lo_hi = {c_a_bits_a_mask_acc_3, c_a_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] c_a_bits_a_mask_lo = {c_a_bits_a_mask_lo_hi, c_a_bits_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] c_a_bits_a_mask_hi_lo = {c_a_bits_a_mask_acc_5, c_a_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] c_a_bits_a_mask_hi_hi = {c_a_bits_a_mask_acc_7, c_a_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] c_a_bits_a_mask_hi = {c_a_bits_a_mask_hi_hi, c_a_bits_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _c_a_bits_a_mask_T = {c_a_bits_a_mask_hi, c_a_bits_a_mask_lo}; // @[Misc.scala:222:10] assign c_a_bits_a_mask = _c_a_bits_a_mask_T; // @[Misc.scala:222:10] wire _c_d_valid_T_1; // @[CacheCork.scala:113:33] wire [2:0] c_d_bits_size; // @[CacheCork.scala:112:23] wire [2:0] c_d_bits_source; // @[CacheCork.scala:112:23] wire c_d_ready; // @[CacheCork.scala:112:23] wire c_d_valid; // @[CacheCork.scala:112:23] wire _T_4 = nodeIn_c_bits_opcode == 3'h6; // @[CacheCork.scala:113:53] wire _c_d_valid_T; // @[CacheCork.scala:113:53] assign _c_d_valid_T = _T_4; // @[CacheCork.scala:113:53] wire _nodeIn_c_ready_T; // @[CacheCork.scala:117:44] assign _nodeIn_c_ready_T = _T_4; // @[CacheCork.scala:113:53, :117:44] assign _c_d_valid_T_1 = nodeIn_c_valid & _c_d_valid_T; // @[CacheCork.scala:113:{33,53}] assign c_d_valid = _c_d_valid_T_1; // @[CacheCork.scala:112:23, :113:33] assign c_d_bits_size = c_d_bits_d_size; // @[Edges.scala:677:17] assign c_d_bits_source = c_d_bits_d_source; // @[Edges.scala:677:17] assign _nodeIn_c_ready_T_1 = _nodeIn_c_ready_T ? c_d_ready : c_a_ready; // @[CacheCork.scala:101:23, :112:23, :117:{26,44}] assign nodeIn_c_ready = _nodeIn_c_ready_T_1; // @[CacheCork.scala:117:26] wire _in_d_ready_T_4; // @[CacheCork.scala:136:34] wire _in_d_valid_T_7; // @[Arbiter.scala:96:24] wire [2:0] _in_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign nodeIn_d_bits_opcode = in_d_bits_opcode; // @[CacheCork.scala:131:24] wire [1:0] _in_d_bits_WIRE_param; // @[Mux.scala:30:73] assign nodeIn_d_bits_param = in_d_bits_param; // @[CacheCork.scala:131:24] wire [2:0] _in_d_bits_WIRE_size; // @[Mux.scala:30:73] assign nodeIn_d_bits_size = in_d_bits_size; // @[CacheCork.scala:131:24] wire [2:0] _in_d_bits_WIRE_source; // @[Mux.scala:30:73] assign nodeIn_d_bits_source = in_d_bits_source; // @[CacheCork.scala:131:24] wire [2:0] _in_d_bits_WIRE_sink; // @[Mux.scala:30:73] wire _in_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign nodeIn_d_bits_denied = in_d_bits_denied; // @[CacheCork.scala:131:24] wire [63:0] _in_d_bits_WIRE_data; // @[Mux.scala:30:73] assign nodeIn_d_bits_data = in_d_bits_data; // @[CacheCork.scala:131:24] wire _in_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign nodeIn_d_bits_corrupt = in_d_bits_corrupt; // @[CacheCork.scala:131:24] wire [2:0] in_d_bits_sink; // @[CacheCork.scala:131:24] wire in_d_ready; // @[CacheCork.scala:131:24] wire in_d_valid; // @[CacheCork.scala:131:24] wire _GEN_0 = in_d_ready & in_d_valid; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _GEN_0; // @[Decoupled.scala:51:35] wire _beatsLeft_T_4; // @[Decoupled.scala:51:35] assign _beatsLeft_T_4 = _GEN_0; // @[Decoupled.scala:51:35] wire [12:0] _d_first_beats1_decode_T = 13'h3F << in_d_bits_size; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = in_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _d_grant_T = in_d_bits_opcode == 3'h5; // @[CacheCork.scala:131:24, :133:40] wire _d_grant_T_1 = in_d_bits_opcode == 3'h4; // @[CacheCork.scala:131:24, :133:74] wire d_grant = _d_grant_T | _d_grant_T_1; // @[CacheCork.scala:133:{40,54,74}] wire _pool_io_alloc_ready_T = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire _pool_io_alloc_ready_T_1 = _pool_io_alloc_ready_T & d_first; // @[Decoupled.scala:51:35] wire _pool_io_alloc_ready_T_2 = _pool_io_alloc_ready_T_1 & d_grant; // @[CacheCork.scala:133:54, :134:{42,53}] wire _nodeIn_d_valid_T = ~d_first; // @[Edges.scala:231:25] wire _nodeIn_d_valid_T_1 = _pool_io_alloc_valid | _nodeIn_d_valid_T; // @[CacheCork.scala:127:26, :135:{58,61}] wire _nodeIn_d_valid_T_2 = ~d_grant; // @[CacheCork.scala:133:54, :135:73] wire _nodeIn_d_valid_T_3 = _nodeIn_d_valid_T_1 | _nodeIn_d_valid_T_2; // @[CacheCork.scala:135:{58,70,73}] assign _nodeIn_d_valid_T_4 = in_d_valid & _nodeIn_d_valid_T_3; // @[CacheCork.scala:131:24, :135:{34,70}] assign nodeIn_d_valid = _nodeIn_d_valid_T_4; // @[CacheCork.scala:135:34] wire _in_d_ready_T = ~d_first; // @[Edges.scala:231:25] wire _in_d_ready_T_1 = _pool_io_alloc_valid | _in_d_ready_T; // @[CacheCork.scala:127:26, :136:{58,61}] wire _in_d_ready_T_2 = ~d_grant; // @[CacheCork.scala:133:54, :135:73, :136:73] wire _in_d_ready_T_3 = _in_d_ready_T_1 | _in_d_ready_T_2; // @[CacheCork.scala:136:{58,70,73}] assign _in_d_ready_T_4 = nodeIn_d_ready & _in_d_ready_T_3; // @[CacheCork.scala:136:{34,70}] assign in_d_ready = _in_d_ready_T_4; // @[CacheCork.scala:131:24, :136:34] reg [2:0] nodeIn_d_bits_sink_r; // @[package.scala:88:63] assign _nodeIn_d_bits_sink_T = d_first ? _pool_io_alloc_bits : nodeIn_d_bits_sink_r; // @[package.scala:88:{42,63}] assign nodeIn_d_bits_sink = _nodeIn_d_bits_sink_T; // @[package.scala:88:42] wire _d_d_ready_T; // @[Arbiter.scala:94:31] assign nodeOut_d_ready = d_d_ready; // @[CacheCork.scala:141:23] wire [2:0] _d_d_bits_source_T; // @[CacheCork.scala:143:46] wire [2:0] d_d_bits_opcode; // @[CacheCork.scala:141:23] wire [1:0] d_d_bits_param; // @[CacheCork.scala:141:23] wire [2:0] d_d_bits_source; // @[CacheCork.scala:141:23] assign _d_d_bits_source_T = nodeOut_d_bits_source[3:1]; // @[CacheCork.scala:143:46] assign d_d_bits_source = _d_d_bits_source_T; // @[CacheCork.scala:141:23, :143:46] wire [32:0] _aWOk_T_1 = {1'h0, _aWOk_T}; // @[Parameters.scala:137:{31,41}] wire _bypass_T_1 = nodeIn_a_bits_source == d_d_bits_source; // @[CacheCork.scala:141:23, :150:91] reg dWHeld_r; // @[package.scala:88:63] wire dWHeld = d_first ? _dWHeld_T : dWHeld_r; // @[package.scala:88:{42,63}] wire _T_18 = nodeOut_d_bits_opcode == 3'h1 & nodeOut_d_bits_source[0]; // @[CacheCork.scala:162:{33,51,71}] wire [1:0] _d_d_bits_param_T = {1'h0, ~dWHeld}; // @[package.scala:88:42] assign d_d_bits_param = _T_18 ? _d_d_bits_param_T : 2'h0; // @[CacheCork.scala:141:23, :142:13, :162:{51,76}, :164:{26,32}] assign d_d_bits_opcode = nodeOut_d_bits_opcode == 3'h0 & ~(nodeOut_d_bits_source[0]) ? 3'h6 : _T_18 ? 3'h5 : nodeOut_d_bits_opcode; // @[CacheCork.scala:141:23, :142:13, :162:{51,71,76}, :163:27, :166:{33,47,50,73}, :167:27] wire [12:0] _decode_T = 13'h3F << c_a_bits_size; // @[package.scala:243:71] wire [5:0] _decode_T_1 = _decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _decode_T_2 = ~_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] decode = _decode_T_2[5:3]; // @[package.scala:243:46] wire [12:0] _decode_T_3 = 13'h3F << a_a_bits_size; // @[package.scala:243:71] wire [5:0] _decode_T_4 = _decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _decode_T_5 = ~_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] decode_1 = _decode_T_5[5:3]; // @[package.scala:243:46] wire _opdata_T_1 = a_a_bits_opcode[2]; // @[Edges.scala:92:37] wire opdata_1 = ~_opdata_T_1; // @[Edges.scala:92:{28,37}] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24] wire [1:0] _readys_T = {a_a_valid, c_a_valid}; // @[CacheCork.scala:74:23, :101:23] wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17] wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17] wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}] wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & c_a_valid; // @[CacheCork.scala:101:23] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & a_a_valid; // @[CacheCork.scala:74:23] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _nodeOut_a_valid_T = c_a_valid | a_a_valid; // @[CacheCork.scala:74:23, :101:23] wire [2:0] maskedBeats_0 = winner_0 ? decode : 3'h0; // @[Edges.scala:220:59, :221:14] wire [2:0] maskedBeats_1 = winner_1 & opdata_1 ? decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [2:0] initBeats = maskedBeats_0 | maskedBeats_1; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T = nodeOut_a_ready & nodeOut_a_valid; // @[Decoupled.scala:51:35] wire [3:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {3'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35] wire [2:0] _beatsLeft_T_2 = _beatsLeft_T_1[2:0]; // @[Arbiter.scala:85:52] wire [2:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_0; // @[Arbiter.scala:88:26] reg state_1; // @[Arbiter.scala:88:26] wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _c_a_ready_T = nodeOut_a_ready & allowed_0; // @[Arbiter.scala:92:24, :94:31] assign c_a_ready = _c_a_ready_T; // @[CacheCork.scala:101:23] assign _a_a_ready_T = nodeOut_a_ready & allowed_1; // @[Arbiter.scala:92:24, :94:31] assign a_a_ready = _a_a_ready_T; // @[CacheCork.scala:74:23] wire _nodeOut_a_valid_T_1 = state_0 & c_a_valid; // @[Mux.scala:30:73] wire _nodeOut_a_valid_T_2 = state_1 & a_a_valid; // @[Mux.scala:30:73] wire _nodeOut_a_valid_T_3 = _nodeOut_a_valid_T_1 | _nodeOut_a_valid_T_2; // @[Mux.scala:30:73] wire _nodeOut_a_valid_WIRE = _nodeOut_a_valid_T_3; // @[Mux.scala:30:73] assign _nodeOut_a_valid_T_4 = idle ? _nodeOut_a_valid_T : _nodeOut_a_valid_WIRE; // @[Mux.scala:30:73] assign nodeOut_a_valid = _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24] wire [2:0] _nodeOut_a_bits_WIRE_10; // @[Mux.scala:30:73] assign nodeOut_a_bits_opcode = _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_WIRE_9; // @[Mux.scala:30:73] assign nodeOut_a_bits_param = _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_WIRE_8; // @[Mux.scala:30:73] assign nodeOut_a_bits_size = _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [3:0] _nodeOut_a_bits_WIRE_7; // @[Mux.scala:30:73] assign nodeOut_a_bits_source = _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _nodeOut_a_bits_WIRE_6; // @[Mux.scala:30:73] assign nodeOut_a_bits_address = _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [7:0] _nodeOut_a_bits_WIRE_3; // @[Mux.scala:30:73] assign nodeOut_a_bits_mask = _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73] wire [63:0] _nodeOut_a_bits_WIRE_2; // @[Mux.scala:30:73] assign nodeOut_a_bits_data = _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73] wire _nodeOut_a_bits_WIRE_1; // @[Mux.scala:30:73] assign nodeOut_a_bits_corrupt = _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _nodeOut_a_bits_T = muxState_0 & c_a_bits_corrupt; // @[Mux.scala:30:73] wire _nodeOut_a_bits_T_1 = muxState_1 & a_a_bits_corrupt; // @[Mux.scala:30:73] wire _nodeOut_a_bits_T_2 = _nodeOut_a_bits_T | _nodeOut_a_bits_T_1; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_1 = _nodeOut_a_bits_T_2; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_corrupt = _nodeOut_a_bits_WIRE_1; // @[Mux.scala:30:73] wire [63:0] _nodeOut_a_bits_T_3 = muxState_0 ? c_a_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _nodeOut_a_bits_T_4 = muxState_1 ? a_a_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _nodeOut_a_bits_T_5 = _nodeOut_a_bits_T_3 | _nodeOut_a_bits_T_4; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_2 = _nodeOut_a_bits_T_5; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_data = _nodeOut_a_bits_WIRE_2; // @[Mux.scala:30:73] wire [7:0] _nodeOut_a_bits_T_6 = muxState_0 ? c_a_bits_mask : 8'h0; // @[Mux.scala:30:73] wire [7:0] _nodeOut_a_bits_T_7 = muxState_1 ? a_a_bits_mask : 8'h0; // @[Mux.scala:30:73] wire [7:0] _nodeOut_a_bits_T_8 = _nodeOut_a_bits_T_6 | _nodeOut_a_bits_T_7; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_3 = _nodeOut_a_bits_T_8; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_mask = _nodeOut_a_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _nodeOut_a_bits_T_9 = muxState_0 ? c_a_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _nodeOut_a_bits_T_10 = muxState_1 ? a_a_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _nodeOut_a_bits_T_11 = _nodeOut_a_bits_T_9 | _nodeOut_a_bits_T_10; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_6 = _nodeOut_a_bits_T_11; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_address = _nodeOut_a_bits_WIRE_6; // @[Mux.scala:30:73] wire [3:0] _nodeOut_a_bits_T_12 = muxState_0 ? c_a_bits_source : 4'h0; // @[Mux.scala:30:73] wire [3:0] _nodeOut_a_bits_T_13 = muxState_1 ? a_a_bits_source : 4'h0; // @[Mux.scala:30:73] wire [3:0] _nodeOut_a_bits_T_14 = _nodeOut_a_bits_T_12 | _nodeOut_a_bits_T_13; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_7 = _nodeOut_a_bits_T_14; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_source = _nodeOut_a_bits_WIRE_7; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_15 = muxState_0 ? c_a_bits_size : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_16 = muxState_1 ? a_a_bits_size : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_17 = _nodeOut_a_bits_T_15 | _nodeOut_a_bits_T_16; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_8 = _nodeOut_a_bits_T_17; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_size = _nodeOut_a_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_19 = muxState_1 ? a_a_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_20 = _nodeOut_a_bits_T_19; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_9 = _nodeOut_a_bits_T_20; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_param = _nodeOut_a_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_22 = muxState_1 ? a_a_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_23 = _nodeOut_a_bits_T_22; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_10 = _nodeOut_a_bits_T_23; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_opcode = _nodeOut_a_bits_WIRE_10; // @[Mux.scala:30:73] wire [12:0] _decode_T_6 = 13'h3F << d_d_bits_size; // @[package.scala:243:71] wire [5:0] _decode_T_7 = _decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _decode_T_8 = ~_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] decode_2 = _decode_T_8[5:3]; // @[package.scala:243:46] wire opdata_2 = d_d_bits_opcode[0]; // @[Edges.scala:106:36] reg [2:0] beatsLeft_1; // @[Arbiter.scala:60:30] wire idle_1 = beatsLeft_1 == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_1 = idle_1 & in_d_ready; // @[CacheCork.scala:131:24] wire [1:0] readys_hi = {_q_1_io_deq_valid, _q_io_deq_valid}; // @[Decoupled.scala:362:21] wire [2:0] _readys_T_10 = {readys_hi, d_d_valid}; // @[CacheCork.scala:141:23] wire [3:0] _readys_T_11 = {_readys_T_10, 1'h0}; // @[package.scala:253:48] wire [2:0] _readys_T_12 = _readys_T_11[2:0]; // @[package.scala:253:{48,53}] wire [2:0] _readys_T_13 = _readys_T_10 | _readys_T_12; // @[package.scala:253:{43,53}] wire [4:0] _readys_T_14 = {_readys_T_13, 2'h0}; // @[package.scala:253:{43,48}] wire [2:0] _readys_T_15 = _readys_T_14[2:0]; // @[package.scala:253:{48,53}] wire [2:0] _readys_T_16 = _readys_T_13 | _readys_T_15; // @[package.scala:253:{43,53}] wire [2:0] _readys_T_17 = _readys_T_16; // @[package.scala:253:43, :254:17] wire [3:0] _readys_T_18 = {_readys_T_17, 1'h0}; // @[package.scala:254:17] wire [2:0] _readys_T_19 = _readys_T_18[2:0]; // @[Arbiter.scala:16:{78,83}] wire [2:0] _readys_T_20 = ~_readys_T_19; // @[Arbiter.scala:16:{61,83}] wire _readys_T_21 = _readys_T_20[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_0 = _readys_T_21; // @[Arbiter.scala:68:{27,76}] wire _readys_T_22 = _readys_T_20[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_1 = _readys_T_22; // @[Arbiter.scala:68:{27,76}] wire _readys_T_23 = _readys_T_20[2]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_2 = _readys_T_23; // @[Arbiter.scala:68:{27,76}] wire _winner_T_2 = readys_1_0 & d_d_valid; // @[CacheCork.scala:141:23] wire winner_1_0 = _winner_T_2; // @[Arbiter.scala:71:{27,69}] wire _winner_T_3 = readys_1_1 & _q_io_deq_valid; // @[Decoupled.scala:362:21] wire winner_1_1 = _winner_T_3; // @[Arbiter.scala:71:{27,69}] wire _winner_T_4 = readys_1_2 & _q_1_io_deq_valid; // @[Decoupled.scala:362:21] wire winner_1_2 = _winner_T_4; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_1 = winner_1_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2 = prefixOR_1_1 | winner_1_1; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_1 = prefixOR_2 | winner_1_2; // @[Arbiter.scala:71:27, :76:48] wire _in_d_valid_T = d_d_valid | _q_io_deq_valid; // @[Decoupled.scala:362:21]
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_3 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}} inst input_buffer of InputBuffer_3 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) inst route_arbiter of Arbiter6_RouteComputerReq_3 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<6>}[6], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_10 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_10 : connect states[0].g, UInt<3>(0h2) node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_11 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_11 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_12 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_12 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_13 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_13 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_14 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_14 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_15 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_15 : connect states[5].g, UInt<3>(0h2) node _T_16 = and(io.router_req.ready, io.router_req.valid) when _T_16 : node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_21 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_22 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_23 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_24 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_25 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_26 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` regreset mask : UInt<6>, clock, reset, UInt<6>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}[6] wire vcalloc_vals : UInt<1>[6] node vcalloc_filter_lo_hi = cat(vcalloc_vals[2], vcalloc_vals[1]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_vals[0]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_vals[3]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_vals[0]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_vals[3]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_16, UInt<12>(0h800), UInt<12>(0h0)) node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_15, UInt<12>(0h400), _vcalloc_filter_T_17) node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_14, UInt<12>(0h200), _vcalloc_filter_T_18) node _vcalloc_filter_T_20 = mux(_vcalloc_filter_T_13, UInt<12>(0h100), _vcalloc_filter_T_19) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_12, UInt<12>(0h80), _vcalloc_filter_T_20) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_11, UInt<12>(0h40), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_10, UInt<12>(0h20), _vcalloc_filter_T_22) node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_9, UInt<12>(0h10), _vcalloc_filter_T_23) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_8, UInt<12>(0h8), _vcalloc_filter_T_24) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_7, UInt<12>(0h4), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_6, UInt<12>(0h2), _vcalloc_filter_T_26) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<12>(0h1), _vcalloc_filter_T_27) node _vcalloc_sel_T = bits(vcalloc_filter, 5, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 6) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_27 = and(io.router_req.ready, io.router_req.valid) when _T_27 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_28 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_29 = or(_T_28, vcalloc_vals[2]) node _T_30 = or(_T_29, vcalloc_vals[3]) node _T_31 = or(_T_30, vcalloc_vals[4]) node _T_32 = or(_T_31, vcalloc_vals[5]) when _T_32 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = bits(vcalloc_sel, 0, 0) node _mask_T_10 = bits(vcalloc_sel, 1, 1) node _mask_T_11 = bits(vcalloc_sel, 2, 2) node _mask_T_12 = bits(vcalloc_sel, 3, 3) node _mask_T_13 = bits(vcalloc_sel, 4, 4) node _mask_T_14 = bits(vcalloc_sel, 5, 5) node _mask_T_15 = mux(_mask_T_9, _mask_T_3, UInt<1>(0h0)) node _mask_T_16 = mux(_mask_T_10, _mask_T_4, UInt<1>(0h0)) node _mask_T_17 = mux(_mask_T_11, _mask_T_5, UInt<1>(0h0)) node _mask_T_18 = mux(_mask_T_12, _mask_T_6, UInt<1>(0h0)) node _mask_T_19 = mux(_mask_T_13, _mask_T_7, UInt<1>(0h0)) node _mask_T_20 = mux(_mask_T_14, _mask_T_8, UInt<1>(0h0)) node _mask_T_21 = or(_mask_T_15, _mask_T_16) node _mask_T_22 = or(_mask_T_21, _mask_T_17) node _mask_T_23 = or(_mask_T_22, _mask_T_18) node _mask_T_24 = or(_mask_T_23, _mask_T_19) node _mask_T_25 = or(_mask_T_24, _mask_T_20) wire _mask_WIRE : UInt<6> connect _mask_WIRE, _mask_T_25 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_4 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}} wire _io_vcalloc_req_bits_WIRE_1 : { `1` : UInt<1>[1], `0` : UInt<1>[6]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[6] node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_7) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_12, _io_vcalloc_req_bits_T_8) node _io_vcalloc_req_bits_T_14 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_15 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_10) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_15, _io_vcalloc_req_bits_T_11) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_16 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_22 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18) node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_19) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_20) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_21) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_22) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_27 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_30) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_31) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_32) node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_33) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_38 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_40) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_41) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_44) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_49 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_55) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_60 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_66 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_62) node _io_vcalloc_req_bits_T_68 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_63) node _io_vcalloc_req_bits_T_69 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_64) node _io_vcalloc_req_bits_T_70 = or(_io_vcalloc_req_bits_T_69, _io_vcalloc_req_bits_T_65) node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_70, _io_vcalloc_req_bits_T_66) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_71 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>[1] node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_72, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_75) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_76) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_77) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_9[0], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_9 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_90 = or(_io_vcalloc_req_bits_T_89, _io_vcalloc_req_bits_T_85) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_90, _io_vcalloc_req_bits_T_86) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_88) wire _io_vcalloc_req_bits_WIRE_11 : UInt<3> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_93 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_11 wire _io_vcalloc_req_bits_WIRE_12 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_97 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_95) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_96) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_97) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_98) node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_99) wire _io_vcalloc_req_bits_WIRE_13 : UInt<2> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_104 connect _io_vcalloc_req_bits_WIRE_12.egress_node_id, _io_vcalloc_req_bits_WIRE_13 node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_113 = or(_io_vcalloc_req_bits_T_112, _io_vcalloc_req_bits_T_108) node _io_vcalloc_req_bits_T_114 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_109) node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_114, _io_vcalloc_req_bits_T_110) wire _io_vcalloc_req_bits_WIRE_14 : UInt<4> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_115 connect _io_vcalloc_req_bits_WIRE_12.egress_node, _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_121 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_117) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_118) node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_119) node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_120) node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_121) wire _io_vcalloc_req_bits_WIRE_15 : UInt<2> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_126 connect _io_vcalloc_req_bits_WIRE_12.ingress_node_id, _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = or(_io_vcalloc_req_bits_T_127, _io_vcalloc_req_bits_T_128) node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_133, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_132) wire _io_vcalloc_req_bits_WIRE_16 : UInt<4> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_137 connect _io_vcalloc_req_bits_WIRE_12.ingress_node, _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_138 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_139 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_140 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_141 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_142 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_139) node _io_vcalloc_req_bits_T_145 = or(_io_vcalloc_req_bits_T_144, _io_vcalloc_req_bits_T_140) node _io_vcalloc_req_bits_T_146 = or(_io_vcalloc_req_bits_T_145, _io_vcalloc_req_bits_T_141) node _io_vcalloc_req_bits_T_147 = or(_io_vcalloc_req_bits_T_146, _io_vcalloc_req_bits_T_142) node _io_vcalloc_req_bits_T_148 = or(_io_vcalloc_req_bits_T_147, _io_vcalloc_req_bits_T_143) wire _io_vcalloc_req_bits_WIRE_17 : UInt<2> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_148 connect _io_vcalloc_req_bits_WIRE_12.vnet_id, _io_vcalloc_req_bits_WIRE_17 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_12 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].flow, states[0].flow node _T_33 = bits(vcalloc_sel, 0, 0) node _T_34 = and(vcalloc_vals[0], _T_33) node _T_35 = and(_T_34, io.vcalloc_req.ready) when _T_35 : connect states[0].g, UInt<3>(0h3) node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].flow, states[1].flow node _T_36 = bits(vcalloc_sel, 1, 1) node _T_37 = and(vcalloc_vals[1], _T_36) node _T_38 = and(_T_37, io.vcalloc_req.ready) when _T_38 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].flow, states[2].flow node _T_39 = bits(vcalloc_sel, 2, 2) node _T_40 = and(vcalloc_vals[2], _T_39) node _T_41 = and(_T_40, io.vcalloc_req.ready) when _T_41 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].flow, states[3].flow node _T_42 = bits(vcalloc_sel, 3, 3) node _T_43 = and(vcalloc_vals[3], _T_42) node _T_44 = and(_T_43, io.vcalloc_req.ready) when _T_44 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].flow, states[4].flow node _T_45 = bits(vcalloc_sel, 4, 4) node _T_46 = and(vcalloc_vals[4], _T_45) node _T_47 = and(_T_46, io.vcalloc_req.ready) when _T_47 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].flow, states[5].flow node _T_48 = bits(vcalloc_sel, 5, 5) node _T_49 = and(vcalloc_vals[5], _T_48) node _T_50 = and(_T_49, io.vcalloc_req.ready) when _T_50 : connect states[5].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[4], vcalloc_vals[5]) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(vcalloc_vals[3], _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) node _io_debug_va_stall_T_8 = add(_io_debug_va_stall_T_3, _io_debug_va_stall_T_7) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 2, 0) node _io_debug_va_stall_T_10 = sub(_io_debug_va_stall_T_9, io.vcalloc_req.ready) node _io_debug_va_stall_T_11 = tail(_io_debug_va_stall_T_10, 1) connect io.debug.va_stall, _io_debug_va_stall_T_11 node _T_51 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_51 : node _T_52 = bits(vcalloc_sel, 0, 0) when _T_52 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].g, UInt<3>(0h3) node _T_53 = eq(states[0].g, UInt<3>(0h2)) node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : node _T_56 = eq(_T_53, UInt<1>(0h0)) when _T_56 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_53, UInt<1>(0h1), "") : assert_3 node _T_57 = bits(vcalloc_sel, 1, 1) when _T_57 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].g, UInt<3>(0h3) node _T_58 = eq(states[1].g, UInt<3>(0h2)) node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_T_58, UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_58, UInt<1>(0h1), "") : assert_4 node _T_62 = bits(vcalloc_sel, 2, 2) when _T_62 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].g, UInt<3>(0h3) node _T_63 = eq(states[2].g, UInt<3>(0h2)) node _T_64 = asUInt(reset) node _T_65 = eq(_T_64, UInt<1>(0h0)) when _T_65 : node _T_66 = eq(_T_63, UInt<1>(0h0)) when _T_66 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_63, UInt<1>(0h1), "") : assert_5 node _T_67 = bits(vcalloc_sel, 3, 3) when _T_67 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].g, UInt<3>(0h3) node _T_68 = eq(states[3].g, UInt<3>(0h2)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_68, UInt<1>(0h1), "") : assert_6 node _T_72 = bits(vcalloc_sel, 4, 4) when _T_72 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].g, UInt<3>(0h3) node _T_73 = eq(states[4].g, UInt<3>(0h2)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_73, UInt<1>(0h1), "") : assert_7 node _T_77 = bits(vcalloc_sel, 5, 5) when _T_77 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].g, UInt<3>(0h3) node _T_78 = eq(states[5].g, UInt<3>(0h2)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_78, UInt<1>(0h1), "") : assert_8 inst salloc_arb of SwitchArbiter_9 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_lo_hi = cat(states[0].vc_sel.`0`[2], states[0].vc_sel.`0`[1]) node credit_available_lo = cat(credit_available_lo_hi, states[0].vc_sel.`0`[0]) node credit_available_hi_hi = cat(states[0].vc_sel.`0`[5], states[0].vc_sel.`0`[4]) node credit_available_hi = cat(credit_available_hi_hi, states[0].vc_sel.`0`[3]) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node _credit_available_T_1 = cat(states[0].vc_sel.`1`[0], _credit_available_T) node credit_available_lo_hi_1 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, io.out_credit_available.`0`[0]) node credit_available_hi_hi_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, io.out_credit_available.`0`[3]) node _credit_available_T_2 = cat(credit_available_hi_1, credit_available_lo_1) node _credit_available_T_3 = cat(io.out_credit_available.`1`[0], _credit_available_T_2) node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3) node credit_available = neq(_credit_available_T_4, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3] connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4] connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_82 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_83 = and(_T_82, input_buffer.io.deq[0].bits.tail) when _T_83 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready node credit_available_lo_hi_2 = cat(states[1].vc_sel.`0`[2], states[1].vc_sel.`0`[1]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, states[1].vc_sel.`0`[0]) node credit_available_hi_hi_2 = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, states[1].vc_sel.`0`[3]) node _credit_available_T_5 = cat(credit_available_hi_2, credit_available_lo_2) node _credit_available_T_6 = cat(states[1].vc_sel.`1`[0], _credit_available_T_5) node credit_available_lo_hi_3 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, io.out_credit_available.`0`[0]) node credit_available_hi_hi_3 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, io.out_credit_available.`0`[3]) node _credit_available_T_7 = cat(credit_available_hi_3, credit_available_lo_3) node _credit_available_T_8 = cat(io.out_credit_available.`1`[0], _credit_available_T_7) node _credit_available_T_9 = and(_credit_available_T_6, _credit_available_T_8) node credit_available_1 = neq(_credit_available_T_9, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_84 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_85 = and(_T_84, input_buffer.io.deq[1].bits.tail) when _T_85 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_hi_4 = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, states[2].vc_sel.`0`[0]) node credit_available_hi_hi_4 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) node credit_available_hi_4 = cat(credit_available_hi_hi_4, states[2].vc_sel.`0`[3]) node _credit_available_T_10 = cat(credit_available_hi_4, credit_available_lo_4) node _credit_available_T_11 = cat(states[2].vc_sel.`1`[0], _credit_available_T_10) node credit_available_lo_hi_5 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_5 = cat(credit_available_lo_hi_5, io.out_credit_available.`0`[0]) node credit_available_hi_hi_5 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_5 = cat(credit_available_hi_hi_5, io.out_credit_available.`0`[3]) node _credit_available_T_12 = cat(credit_available_hi_5, credit_available_lo_5) node _credit_available_T_13 = cat(io.out_credit_available.`1`[0], _credit_available_T_12) node _credit_available_T_14 = and(_credit_available_T_11, _credit_available_T_13) node credit_available_2 = neq(_credit_available_T_14, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_86 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_87 = and(_T_86, input_buffer.io.deq[2].bits.tail) when _T_87 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_hi_6 = cat(states[3].vc_sel.`0`[2], states[3].vc_sel.`0`[1]) node credit_available_lo_6 = cat(credit_available_lo_hi_6, states[3].vc_sel.`0`[0]) node credit_available_hi_hi_6 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) node credit_available_hi_6 = cat(credit_available_hi_hi_6, states[3].vc_sel.`0`[3]) node _credit_available_T_15 = cat(credit_available_hi_6, credit_available_lo_6) node _credit_available_T_16 = cat(states[3].vc_sel.`1`[0], _credit_available_T_15) node credit_available_lo_hi_7 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_7 = cat(credit_available_lo_hi_7, io.out_credit_available.`0`[0]) node credit_available_hi_hi_7 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_7 = cat(credit_available_hi_hi_7, io.out_credit_available.`0`[3]) node _credit_available_T_17 = cat(credit_available_hi_7, credit_available_lo_7) node _credit_available_T_18 = cat(io.out_credit_available.`1`[0], _credit_available_T_17) node _credit_available_T_19 = and(_credit_available_T_16, _credit_available_T_18) node credit_available_3 = neq(_credit_available_T_19, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_88 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_89 = and(_T_88, input_buffer.io.deq[3].bits.tail) when _T_89 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_hi_8 = cat(states[4].vc_sel.`0`[2], states[4].vc_sel.`0`[1]) node credit_available_lo_8 = cat(credit_available_lo_hi_8, states[4].vc_sel.`0`[0]) node credit_available_hi_hi_8 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) node credit_available_hi_8 = cat(credit_available_hi_hi_8, states[4].vc_sel.`0`[3]) node _credit_available_T_20 = cat(credit_available_hi_8, credit_available_lo_8) node _credit_available_T_21 = cat(states[4].vc_sel.`1`[0], _credit_available_T_20) node credit_available_lo_hi_9 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_9 = cat(credit_available_lo_hi_9, io.out_credit_available.`0`[0]) node credit_available_hi_hi_9 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_9 = cat(credit_available_hi_hi_9, io.out_credit_available.`0`[3]) node _credit_available_T_22 = cat(credit_available_hi_9, credit_available_lo_9) node _credit_available_T_23 = cat(io.out_credit_available.`1`[0], _credit_available_T_22) node _credit_available_T_24 = and(_credit_available_T_21, _credit_available_T_23) node credit_available_4 = neq(_credit_available_T_24, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_90 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_91 = and(_T_90, input_buffer.io.deq[4].bits.tail) when _T_91 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_hi_10 = cat(states[5].vc_sel.`0`[2], states[5].vc_sel.`0`[1]) node credit_available_lo_10 = cat(credit_available_lo_hi_10, states[5].vc_sel.`0`[0]) node credit_available_hi_hi_10 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) node credit_available_hi_10 = cat(credit_available_hi_hi_10, states[5].vc_sel.`0`[3]) node _credit_available_T_25 = cat(credit_available_hi_10, credit_available_lo_10) node _credit_available_T_26 = cat(states[5].vc_sel.`1`[0], _credit_available_T_25) node credit_available_lo_hi_11 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_11 = cat(credit_available_lo_hi_11, io.out_credit_available.`0`[0]) node credit_available_hi_hi_11 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_11 = cat(credit_available_hi_hi_11, io.out_credit_available.`0`[3]) node _credit_available_T_27 = cat(credit_available_hi_11, credit_available_lo_11) node _credit_available_T_28 = cat(io.out_credit_available.`1`[0], _credit_available_T_27) node _credit_available_T_29 = and(_credit_available_T_26, _credit_available_T_28) node credit_available_5 = neq(_credit_available_T_29, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_92 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_93 = and(_T_92, input_buffer.io.deq[5].bits.tail) when _T_93 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5) node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 1, 0) node _io_debug_sa_stall_T_14 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_15 = bits(_io_debug_sa_stall_T_14, 1, 0) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_17) node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_21 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_8) node _io_in_vc_free_T_14 = or(_io_in_vc_free_T_13, _io_in_vc_free_T_9) node _io_in_vc_free_T_15 = or(_io_in_vc_free_T_14, _io_in_vc_free_T_10) node _io_in_vc_free_T_16 = or(_io_in_vc_free_T_15, _io_in_vc_free_T_11) node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_16, _io_in_vc_free_T_12) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_17 node _io_in_vc_free_T_18 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_18, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_19 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 5, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) wire vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]} wire _vc_sel_WIRE : UInt<1>[6] node _vc_sel_T_6 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_7 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_8 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = or(_vc_sel_T_6, _vc_sel_T_7) node _vc_sel_T_13 = or(_vc_sel_T_12, _vc_sel_T_8) node _vc_sel_T_14 = or(_vc_sel_T_13, _vc_sel_T_9) node _vc_sel_T_15 = or(_vc_sel_T_14, _vc_sel_T_10) node _vc_sel_T_16 = or(_vc_sel_T_15, _vc_sel_T_11) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_16 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_17 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_20 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_21 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_22 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_23 = or(_vc_sel_T_17, _vc_sel_T_18) node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_19) node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_20) node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_21) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_22) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_27 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_31 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_32 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_34 = or(_vc_sel_T_28, _vc_sel_T_29) node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_30) node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_31) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_32) node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_33) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_38 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_39 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_41 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_45 = or(_vc_sel_T_39, _vc_sel_T_40) node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_41) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_42) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_43) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_44) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_49 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_50 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_56 = or(_vc_sel_T_50, _vc_sel_T_51) node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_52) node _vc_sel_T_58 = or(_vc_sel_T_57, _vc_sel_T_53) node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_54) node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_55) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_60 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_61 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_62 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_63 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_64 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_65 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_66 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_67 = or(_vc_sel_T_61, _vc_sel_T_62) node _vc_sel_T_68 = or(_vc_sel_T_67, _vc_sel_T_63) node _vc_sel_T_69 = or(_vc_sel_T_68, _vc_sel_T_64) node _vc_sel_T_70 = or(_vc_sel_T_69, _vc_sel_T_65) node _vc_sel_T_71 = or(_vc_sel_T_70, _vc_sel_T_66) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_71 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_7 : UInt<1>[1] node _vc_sel_T_72 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_76 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_77 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_78 = or(_vc_sel_T_72, _vc_sel_T_73) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_74) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_75) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_76) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_77) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_82 connect _vc_sel_WIRE_7[0], _vc_sel_WIRE_8 connect vc_sel.`1`, _vc_sel_WIRE_7 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node channel_oh_0 = or(_channel_oh_T_3, vc_sel.`0`[5]) node virt_channel_lo_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1]) node virt_channel_lo = cat(virt_channel_lo_hi, vc_sel.`0`[0]) node virt_channel_hi_hi = cat(vc_sel.`0`[5], vc_sel.`0`[4]) node virt_channel_hi = cat(virt_channel_hi_hi, vc_sel.`0`[3]) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 5, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node _virt_channel_T_8 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_9 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_10 = or(_virt_channel_T_8, _virt_channel_T_9) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_10 node _T_94 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_94 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_7) node _salloc_outs_0_flit_payload_T_13 = or(_salloc_outs_0_flit_payload_T_12, _salloc_outs_0_flit_payload_T_8) node _salloc_outs_0_flit_payload_T_14 = or(_salloc_outs_0_flit_payload_T_13, _salloc_outs_0_flit_payload_T_9) node _salloc_outs_0_flit_payload_T_15 = or(_salloc_outs_0_flit_payload_T_14, _salloc_outs_0_flit_payload_T_10) node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_15, _salloc_outs_0_flit_payload_T_11) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_16 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_7) node _salloc_outs_0_flit_head_T_13 = or(_salloc_outs_0_flit_head_T_12, _salloc_outs_0_flit_head_T_8) node _salloc_outs_0_flit_head_T_14 = or(_salloc_outs_0_flit_head_T_13, _salloc_outs_0_flit_head_T_9) node _salloc_outs_0_flit_head_T_15 = or(_salloc_outs_0_flit_head_T_14, _salloc_outs_0_flit_head_T_10) node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_15, _salloc_outs_0_flit_head_T_11) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_16 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_7) node _salloc_outs_0_flit_tail_T_13 = or(_salloc_outs_0_flit_tail_T_12, _salloc_outs_0_flit_tail_T_8) node _salloc_outs_0_flit_tail_T_14 = or(_salloc_outs_0_flit_tail_T_13, _salloc_outs_0_flit_tail_T_9) node _salloc_outs_0_flit_tail_T_15 = or(_salloc_outs_0_flit_tail_T_14, _salloc_outs_0_flit_tail_T_10) node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_15, _salloc_outs_0_flit_tail_T_11) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_16 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_7) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_12, _salloc_outs_0_flit_flow_T_8) node _salloc_outs_0_flit_flow_T_14 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_15 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_10) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_15, _salloc_outs_0_flit_flow_T_11) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_16 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_21 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_22 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_18) node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_19) node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_20) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_21) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_22) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_27 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_28, _salloc_outs_0_flit_flow_T_29) node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_30) node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_31) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_32) node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_33) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_38 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_40) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_41) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_44) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_49 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_51) node _salloc_outs_0_flit_flow_T_57 = or(_salloc_outs_0_flit_flow_T_56, _salloc_outs_0_flit_flow_T_52) node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_57, _salloc_outs_0_flit_flow_T_53) node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_55) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_60 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`0`[1], UInt<1>(0h0) connect states[0].vc_sel.`0`[2], UInt<1>(0h0) connect states[0].vc_sel.`0`[3], UInt<1>(0h0) connect states[0].vc_sel.`0`[4], UInt<1>(0h0) connect states[0].vc_sel.`0`[5], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`0`[3], UInt<1>(0h0) connect states[1].vc_sel.`0`[4], UInt<1>(0h0) connect states[1].vc_sel.`0`[5], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`0`[1], UInt<1>(0h0) connect states[2].vc_sel.`0`[3], UInt<1>(0h0) connect states[2].vc_sel.`0`[4], UInt<1>(0h0) connect states[2].vc_sel.`0`[5], UInt<1>(0h0) connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`0`[1], UInt<1>(0h0) connect states[3].vc_sel.`0`[4], UInt<1>(0h0) connect states[3].vc_sel.`0`[5], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`0`[1], UInt<1>(0h0) connect states[4].vc_sel.`0`[2], UInt<1>(0h0) connect states[4].vc_sel.`0`[3], UInt<1>(0h0) connect states[4].vc_sel.`0`[5], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`0`[1], UInt<1>(0h0) connect states[5].vc_sel.`0`[2], UInt<1>(0h0) connect states[5].vc_sel.`0`[3], UInt<1>(0h0) node _T_95 = asUInt(reset) when _T_95 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0)
module InputUnit_3( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [5:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [5:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire vcalloc_vals_0; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [5:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [5:0] mask; // @[InputUnit.scala:250:21] wire [5:0] _vcalloc_filter_T_3 = {vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [11:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 12'h1 : _vcalloc_filter_T_3[1] ? 12'h2 : _vcalloc_filter_T_3[2] ? 12'h4 : _vcalloc_filter_T_3[3] ? 12'h8 : _vcalloc_filter_T_3[4] ? 12'h10 : _vcalloc_filter_T_3[5] ? 12'h20 : vcalloc_vals_0 ? 12'h40 : vcalloc_vals_1 ? 12'h80 : vcalloc_vals_2 ? 12'h100 : vcalloc_vals_3 ? 12'h200 : vcalloc_vals_4 ? 12'h400 : {vcalloc_vals_5, 11'h0}; // @[OneHot.scala:85:71] wire [5:0] vcalloc_sel = vcalloc_filter[5:0] | vcalloc_filter[11:6]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5; // @[package.scala:81:59] assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_3 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) wire _source_ok_WIRE : UInt<1>[5] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 node _source_ok_T_25 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_26 = or(_source_ok_T_25, _source_ok_WIRE[2]) node _source_ok_T_27 = or(_source_ok_T_26, _source_ok_WIRE[3]) node source_ok = or(_source_ok_T_27, _source_ok_WIRE[4]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = and(_T_11, _T_24) node _T_65 = and(_T_64, _T_37) node _T_66 = and(_T_65, _T_50) node _T_67 = and(_T_66, _T_63) node _T_68 = asUInt(reset) node _T_69 = eq(_T_68, UInt<1>(0h0)) when _T_69 : node _T_70 = eq(_T_67, UInt<1>(0h0)) when _T_70 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_67, UInt<1>(0h1), "") : assert_1 node _T_71 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_71 : node _T_72 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_73 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_76 = shr(io.in.a.bits.source, 2) node _T_77 = eq(_T_76, UInt<1>(0h0)) node _T_78 = leq(UInt<1>(0h0), uncommonBits_4) node _T_79 = and(_T_77, _T_78) node _T_80 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_81 = and(_T_79, _T_80) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_82 = shr(io.in.a.bits.source, 2) node _T_83 = eq(_T_82, UInt<1>(0h1)) node _T_84 = leq(UInt<1>(0h0), uncommonBits_5) node _T_85 = and(_T_83, _T_84) node _T_86 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_87 = and(_T_85, _T_86) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_88 = shr(io.in.a.bits.source, 2) node _T_89 = eq(_T_88, UInt<2>(0h2)) node _T_90 = leq(UInt<1>(0h0), uncommonBits_6) node _T_91 = and(_T_89, _T_90) node _T_92 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_93 = and(_T_91, _T_92) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_94 = shr(io.in.a.bits.source, 2) node _T_95 = eq(_T_94, UInt<2>(0h3)) node _T_96 = leq(UInt<1>(0h0), uncommonBits_7) node _T_97 = and(_T_95, _T_96) node _T_98 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_99 = and(_T_97, _T_98) node _T_100 = or(_T_75, _T_81) node _T_101 = or(_T_100, _T_87) node _T_102 = or(_T_101, _T_93) node _T_103 = or(_T_102, _T_99) node _T_104 = and(_T_74, _T_103) node _T_105 = or(UInt<1>(0h0), _T_104) node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_107 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<14>(0h2000))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<13>(0h1000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_118 = cvt(_T_117) node _T_119 = and(_T_118, asSInt(UInt<17>(0h10000))) node _T_120 = asSInt(_T_119) node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<18>(0h2f000))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<17>(0h10000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<27>(0h4000000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<13>(0h1000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<19>(0h40000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = or(_T_111, _T_116) node _T_148 = or(_T_147, _T_121) node _T_149 = or(_T_148, _T_126) node _T_150 = or(_T_149, _T_131) node _T_151 = or(_T_150, _T_136) node _T_152 = or(_T_151, _T_141) node _T_153 = or(_T_152, _T_146) node _T_154 = and(_T_106, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(_T_105, _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_156, UInt<1>(0h1), "") : assert_2 node _T_160 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_161 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_162 = and(_T_160, _T_161) node _T_163 = or(UInt<1>(0h0), _T_162) node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<14>(0h2000))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_170 = cvt(_T_169) node _T_171 = and(_T_170, asSInt(UInt<13>(0h1000))) node _T_172 = asSInt(_T_171) node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0))) node _T_174 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_175 = cvt(_T_174) node _T_176 = and(_T_175, asSInt(UInt<17>(0h10000))) node _T_177 = asSInt(_T_176) node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0))) node _T_179 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<18>(0h2f000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<17>(0h10000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<27>(0h4000000))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<13>(0h1000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<19>(0h40000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = or(_T_168, _T_173) node _T_205 = or(_T_204, _T_178) node _T_206 = or(_T_205, _T_183) node _T_207 = or(_T_206, _T_188) node _T_208 = or(_T_207, _T_193) node _T_209 = or(_T_208, _T_198) node _T_210 = or(_T_209, _T_203) node _T_211 = and(_T_163, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = and(UInt<1>(0h0), _T_212) node _T_214 = asUInt(reset) node _T_215 = eq(_T_214, UInt<1>(0h0)) when _T_215 : node _T_216 = eq(_T_213, UInt<1>(0h0)) when _T_216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_213, UInt<1>(0h1), "") : assert_3 node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(source_ok, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_220 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_220, UInt<1>(0h1), "") : assert_5 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(is_aligned, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_227 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_227, UInt<1>(0h1), "") : assert_7 node _T_231 = not(io.in.a.bits.mask) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_232, UInt<1>(0h1), "") : assert_8 node _T_236 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_237 = asUInt(reset) node _T_238 = eq(_T_237, UInt<1>(0h0)) when _T_238 : node _T_239 = eq(_T_236, UInt<1>(0h0)) when _T_239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_236, UInt<1>(0h1), "") : assert_9 node _T_240 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_240 : node _T_241 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_242 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_243 = and(_T_241, _T_242) node _T_244 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_245 = shr(io.in.a.bits.source, 2) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = leq(UInt<1>(0h0), uncommonBits_8) node _T_248 = and(_T_246, _T_247) node _T_249 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_251 = shr(io.in.a.bits.source, 2) node _T_252 = eq(_T_251, UInt<1>(0h1)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_9) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_256 = and(_T_254, _T_255) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_257 = shr(io.in.a.bits.source, 2) node _T_258 = eq(_T_257, UInt<2>(0h2)) node _T_259 = leq(UInt<1>(0h0), uncommonBits_10) node _T_260 = and(_T_258, _T_259) node _T_261 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_262 = and(_T_260, _T_261) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_263 = shr(io.in.a.bits.source, 2) node _T_264 = eq(_T_263, UInt<2>(0h3)) node _T_265 = leq(UInt<1>(0h0), uncommonBits_11) node _T_266 = and(_T_264, _T_265) node _T_267 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_268 = and(_T_266, _T_267) node _T_269 = or(_T_244, _T_250) node _T_270 = or(_T_269, _T_256) node _T_271 = or(_T_270, _T_262) node _T_272 = or(_T_271, _T_268) node _T_273 = and(_T_243, _T_272) node _T_274 = or(UInt<1>(0h0), _T_273) node _T_275 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_276 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<14>(0h2000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<17>(0h10000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<18>(0h2f000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<27>(0h4000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<13>(0h1000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<19>(0h40000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = or(_T_280, _T_285) node _T_317 = or(_T_316, _T_290) node _T_318 = or(_T_317, _T_295) node _T_319 = or(_T_318, _T_300) node _T_320 = or(_T_319, _T_305) node _T_321 = or(_T_320, _T_310) node _T_322 = or(_T_321, _T_315) node _T_323 = and(_T_275, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = and(_T_274, _T_324) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_325, UInt<1>(0h1), "") : assert_10 node _T_329 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_330 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_331 = and(_T_329, _T_330) node _T_332 = or(UInt<1>(0h0), _T_331) node _T_333 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<14>(0h2000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_344 = cvt(_T_343) node _T_345 = and(_T_344, asSInt(UInt<17>(0h10000))) node _T_346 = asSInt(_T_345) node _T_347 = eq(_T_346, asSInt(UInt<1>(0h0))) node _T_348 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_349 = cvt(_T_348) node _T_350 = and(_T_349, asSInt(UInt<18>(0h2f000))) node _T_351 = asSInt(_T_350) node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0))) node _T_353 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<17>(0h10000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_359 = cvt(_T_358) node _T_360 = and(_T_359, asSInt(UInt<27>(0h4000000))) node _T_361 = asSInt(_T_360) node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0))) node _T_363 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_364 = cvt(_T_363) node _T_365 = and(_T_364, asSInt(UInt<13>(0h1000))) node _T_366 = asSInt(_T_365) node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0))) node _T_368 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<19>(0h40000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = or(_T_337, _T_342) node _T_374 = or(_T_373, _T_347) node _T_375 = or(_T_374, _T_352) node _T_376 = or(_T_375, _T_357) node _T_377 = or(_T_376, _T_362) node _T_378 = or(_T_377, _T_367) node _T_379 = or(_T_378, _T_372) node _T_380 = and(_T_332, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = and(UInt<1>(0h0), _T_381) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_382, UInt<1>(0h1), "") : assert_11 node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(source_ok, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_389 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_389, UInt<1>(0h1), "") : assert_13 node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(is_aligned, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_396 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_397 = asUInt(reset) node _T_398 = eq(_T_397, UInt<1>(0h0)) when _T_398 : node _T_399 = eq(_T_396, UInt<1>(0h0)) when _T_399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_396, UInt<1>(0h1), "") : assert_15 node _T_400 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_400, UInt<1>(0h1), "") : assert_16 node _T_404 = not(io.in.a.bits.mask) node _T_405 = eq(_T_404, UInt<1>(0h0)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_405, UInt<1>(0h1), "") : assert_17 node _T_409 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_409, UInt<1>(0h1), "") : assert_18 node _T_413 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_413 : node _T_414 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_415 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_416 = and(_T_414, _T_415) node _T_417 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_418 = shr(io.in.a.bits.source, 2) node _T_419 = eq(_T_418, UInt<1>(0h0)) node _T_420 = leq(UInt<1>(0h0), uncommonBits_12) node _T_421 = and(_T_419, _T_420) node _T_422 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_423 = and(_T_421, _T_422) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_424 = shr(io.in.a.bits.source, 2) node _T_425 = eq(_T_424, UInt<1>(0h1)) node _T_426 = leq(UInt<1>(0h0), uncommonBits_13) node _T_427 = and(_T_425, _T_426) node _T_428 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_429 = and(_T_427, _T_428) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_430 = shr(io.in.a.bits.source, 2) node _T_431 = eq(_T_430, UInt<2>(0h2)) node _T_432 = leq(UInt<1>(0h0), uncommonBits_14) node _T_433 = and(_T_431, _T_432) node _T_434 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_435 = and(_T_433, _T_434) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_436 = shr(io.in.a.bits.source, 2) node _T_437 = eq(_T_436, UInt<2>(0h3)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_15) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_441 = and(_T_439, _T_440) node _T_442 = or(_T_417, _T_423) node _T_443 = or(_T_442, _T_429) node _T_444 = or(_T_443, _T_435) node _T_445 = or(_T_444, _T_441) node _T_446 = and(_T_416, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_447, UInt<1>(0h1), "") : assert_19 node _T_451 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_452 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_453 = and(_T_451, _T_452) node _T_454 = or(UInt<1>(0h0), _T_453) node _T_455 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_456 = cvt(_T_455) node _T_457 = and(_T_456, asSInt(UInt<13>(0h1000))) node _T_458 = asSInt(_T_457) node _T_459 = eq(_T_458, asSInt(UInt<1>(0h0))) node _T_460 = and(_T_454, _T_459) node _T_461 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_462 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_463 = and(_T_461, _T_462) node _T_464 = or(UInt<1>(0h0), _T_463) node _T_465 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_466 = cvt(_T_465) node _T_467 = and(_T_466, asSInt(UInt<14>(0h2000))) node _T_468 = asSInt(_T_467) node _T_469 = eq(_T_468, asSInt(UInt<1>(0h0))) node _T_470 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_471 = cvt(_T_470) node _T_472 = and(_T_471, asSInt(UInt<17>(0h10000))) node _T_473 = asSInt(_T_472) node _T_474 = eq(_T_473, asSInt(UInt<1>(0h0))) node _T_475 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_476 = cvt(_T_475) node _T_477 = and(_T_476, asSInt(UInt<18>(0h2f000))) node _T_478 = asSInt(_T_477) node _T_479 = eq(_T_478, asSInt(UInt<1>(0h0))) node _T_480 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_481 = cvt(_T_480) node _T_482 = and(_T_481, asSInt(UInt<17>(0h10000))) node _T_483 = asSInt(_T_482) node _T_484 = eq(_T_483, asSInt(UInt<1>(0h0))) node _T_485 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_486 = cvt(_T_485) node _T_487 = and(_T_486, asSInt(UInt<27>(0h4000000))) node _T_488 = asSInt(_T_487) node _T_489 = eq(_T_488, asSInt(UInt<1>(0h0))) node _T_490 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_491 = cvt(_T_490) node _T_492 = and(_T_491, asSInt(UInt<13>(0h1000))) node _T_493 = asSInt(_T_492) node _T_494 = eq(_T_493, asSInt(UInt<1>(0h0))) node _T_495 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_496 = cvt(_T_495) node _T_497 = and(_T_496, asSInt(UInt<19>(0h40000))) node _T_498 = asSInt(_T_497) node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0))) node _T_500 = or(_T_469, _T_474) node _T_501 = or(_T_500, _T_479) node _T_502 = or(_T_501, _T_484) node _T_503 = or(_T_502, _T_489) node _T_504 = or(_T_503, _T_494) node _T_505 = or(_T_504, _T_499) node _T_506 = and(_T_464, _T_505) node _T_507 = or(UInt<1>(0h0), _T_460) node _T_508 = or(_T_507, _T_506) node _T_509 = asUInt(reset) node _T_510 = eq(_T_509, UInt<1>(0h0)) when _T_510 : node _T_511 = eq(_T_508, UInt<1>(0h0)) when _T_511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_508, UInt<1>(0h1), "") : assert_20 node _T_512 = asUInt(reset) node _T_513 = eq(_T_512, UInt<1>(0h0)) when _T_513 : node _T_514 = eq(source_ok, UInt<1>(0h0)) when _T_514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(is_aligned, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_518 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(_T_518, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_518, UInt<1>(0h1), "") : assert_23 node _T_522 = eq(io.in.a.bits.mask, mask) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_522, UInt<1>(0h1), "") : assert_24 node _T_526 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_526, UInt<1>(0h1), "") : assert_25 node _T_530 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_530 : node _T_531 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_532 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_533 = and(_T_531, _T_532) node _T_534 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_535 = shr(io.in.a.bits.source, 2) node _T_536 = eq(_T_535, UInt<1>(0h0)) node _T_537 = leq(UInt<1>(0h0), uncommonBits_16) node _T_538 = and(_T_536, _T_537) node _T_539 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_540 = and(_T_538, _T_539) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_541 = shr(io.in.a.bits.source, 2) node _T_542 = eq(_T_541, UInt<1>(0h1)) node _T_543 = leq(UInt<1>(0h0), uncommonBits_17) node _T_544 = and(_T_542, _T_543) node _T_545 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_546 = and(_T_544, _T_545) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_547 = shr(io.in.a.bits.source, 2) node _T_548 = eq(_T_547, UInt<2>(0h2)) node _T_549 = leq(UInt<1>(0h0), uncommonBits_18) node _T_550 = and(_T_548, _T_549) node _T_551 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_552 = and(_T_550, _T_551) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_553 = shr(io.in.a.bits.source, 2) node _T_554 = eq(_T_553, UInt<2>(0h3)) node _T_555 = leq(UInt<1>(0h0), uncommonBits_19) node _T_556 = and(_T_554, _T_555) node _T_557 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(_T_534, _T_540) node _T_560 = or(_T_559, _T_546) node _T_561 = or(_T_560, _T_552) node _T_562 = or(_T_561, _T_558) node _T_563 = and(_T_533, _T_562) node _T_564 = or(UInt<1>(0h0), _T_563) node _T_565 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_566 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_567 = and(_T_565, _T_566) node _T_568 = or(UInt<1>(0h0), _T_567) node _T_569 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_570 = cvt(_T_569) node _T_571 = and(_T_570, asSInt(UInt<13>(0h1000))) node _T_572 = asSInt(_T_571) node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0))) node _T_574 = and(_T_568, _T_573) node _T_575 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_576 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_577 = and(_T_575, _T_576) node _T_578 = or(UInt<1>(0h0), _T_577) node _T_579 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<14>(0h2000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<18>(0h2f000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<17>(0h10000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<27>(0h4000000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<13>(0h1000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<19>(0h40000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = or(_T_583, _T_588) node _T_610 = or(_T_609, _T_593) node _T_611 = or(_T_610, _T_598) node _T_612 = or(_T_611, _T_603) node _T_613 = or(_T_612, _T_608) node _T_614 = and(_T_578, _T_613) node _T_615 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_617 = cvt(_T_616) node _T_618 = and(_T_617, asSInt(UInt<17>(0h10000))) node _T_619 = asSInt(_T_618) node _T_620 = eq(_T_619, asSInt(UInt<1>(0h0))) node _T_621 = and(_T_615, _T_620) node _T_622 = or(UInt<1>(0h0), _T_574) node _T_623 = or(_T_622, _T_614) node _T_624 = or(_T_623, _T_621) node _T_625 = and(_T_564, _T_624) node _T_626 = asUInt(reset) node _T_627 = eq(_T_626, UInt<1>(0h0)) when _T_627 : node _T_628 = eq(_T_625, UInt<1>(0h0)) when _T_628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_625, UInt<1>(0h1), "") : assert_26 node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(source_ok, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_632 = asUInt(reset) node _T_633 = eq(_T_632, UInt<1>(0h0)) when _T_633 : node _T_634 = eq(is_aligned, UInt<1>(0h0)) when _T_634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_635 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_T_635, UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_635, UInt<1>(0h1), "") : assert_29 node _T_639 = eq(io.in.a.bits.mask, mask) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_639, UInt<1>(0h1), "") : assert_30 node _T_643 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_643 : node _T_644 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_645 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_646 = and(_T_644, _T_645) node _T_647 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_648 = shr(io.in.a.bits.source, 2) node _T_649 = eq(_T_648, UInt<1>(0h0)) node _T_650 = leq(UInt<1>(0h0), uncommonBits_20) node _T_651 = and(_T_649, _T_650) node _T_652 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_653 = and(_T_651, _T_652) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_654 = shr(io.in.a.bits.source, 2) node _T_655 = eq(_T_654, UInt<1>(0h1)) node _T_656 = leq(UInt<1>(0h0), uncommonBits_21) node _T_657 = and(_T_655, _T_656) node _T_658 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_659 = and(_T_657, _T_658) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_660 = shr(io.in.a.bits.source, 2) node _T_661 = eq(_T_660, UInt<2>(0h2)) node _T_662 = leq(UInt<1>(0h0), uncommonBits_22) node _T_663 = and(_T_661, _T_662) node _T_664 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_665 = and(_T_663, _T_664) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_666 = shr(io.in.a.bits.source, 2) node _T_667 = eq(_T_666, UInt<2>(0h3)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_23) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_671 = and(_T_669, _T_670) node _T_672 = or(_T_647, _T_653) node _T_673 = or(_T_672, _T_659) node _T_674 = or(_T_673, _T_665) node _T_675 = or(_T_674, _T_671) node _T_676 = and(_T_646, _T_675) node _T_677 = or(UInt<1>(0h0), _T_676) node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_679 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_680 = and(_T_678, _T_679) node _T_681 = or(UInt<1>(0h0), _T_680) node _T_682 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_683 = cvt(_T_682) node _T_684 = and(_T_683, asSInt(UInt<13>(0h1000))) node _T_685 = asSInt(_T_684) node _T_686 = eq(_T_685, asSInt(UInt<1>(0h0))) node _T_687 = and(_T_681, _T_686) node _T_688 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_689 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_690 = and(_T_688, _T_689) node _T_691 = or(UInt<1>(0h0), _T_690) node _T_692 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_693 = cvt(_T_692) node _T_694 = and(_T_693, asSInt(UInt<14>(0h2000))) node _T_695 = asSInt(_T_694) node _T_696 = eq(_T_695, asSInt(UInt<1>(0h0))) node _T_697 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_698 = cvt(_T_697) node _T_699 = and(_T_698, asSInt(UInt<18>(0h2f000))) node _T_700 = asSInt(_T_699) node _T_701 = eq(_T_700, asSInt(UInt<1>(0h0))) node _T_702 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_703 = cvt(_T_702) node _T_704 = and(_T_703, asSInt(UInt<17>(0h10000))) node _T_705 = asSInt(_T_704) node _T_706 = eq(_T_705, asSInt(UInt<1>(0h0))) node _T_707 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_708 = cvt(_T_707) node _T_709 = and(_T_708, asSInt(UInt<27>(0h4000000))) node _T_710 = asSInt(_T_709) node _T_711 = eq(_T_710, asSInt(UInt<1>(0h0))) node _T_712 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_713 = cvt(_T_712) node _T_714 = and(_T_713, asSInt(UInt<13>(0h1000))) node _T_715 = asSInt(_T_714) node _T_716 = eq(_T_715, asSInt(UInt<1>(0h0))) node _T_717 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_718 = cvt(_T_717) node _T_719 = and(_T_718, asSInt(UInt<19>(0h40000))) node _T_720 = asSInt(_T_719) node _T_721 = eq(_T_720, asSInt(UInt<1>(0h0))) node _T_722 = or(_T_696, _T_701) node _T_723 = or(_T_722, _T_706) node _T_724 = or(_T_723, _T_711) node _T_725 = or(_T_724, _T_716) node _T_726 = or(_T_725, _T_721) node _T_727 = and(_T_691, _T_726) node _T_728 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_729 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_730 = cvt(_T_729) node _T_731 = and(_T_730, asSInt(UInt<17>(0h10000))) node _T_732 = asSInt(_T_731) node _T_733 = eq(_T_732, asSInt(UInt<1>(0h0))) node _T_734 = and(_T_728, _T_733) node _T_735 = or(UInt<1>(0h0), _T_687) node _T_736 = or(_T_735, _T_727) node _T_737 = or(_T_736, _T_734) node _T_738 = and(_T_677, _T_737) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_738, UInt<1>(0h1), "") : assert_31 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(source_ok, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(is_aligned, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_748 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(_T_748, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_748, UInt<1>(0h1), "") : assert_34 node _T_752 = not(mask) node _T_753 = and(io.in.a.bits.mask, _T_752) node _T_754 = eq(_T_753, UInt<1>(0h0)) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_754, UInt<1>(0h1), "") : assert_35 node _T_758 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_758 : node _T_759 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_760 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_761 = and(_T_759, _T_760) node _T_762 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_763 = shr(io.in.a.bits.source, 2) node _T_764 = eq(_T_763, UInt<1>(0h0)) node _T_765 = leq(UInt<1>(0h0), uncommonBits_24) node _T_766 = and(_T_764, _T_765) node _T_767 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_768 = and(_T_766, _T_767) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_769 = shr(io.in.a.bits.source, 2) node _T_770 = eq(_T_769, UInt<1>(0h1)) node _T_771 = leq(UInt<1>(0h0), uncommonBits_25) node _T_772 = and(_T_770, _T_771) node _T_773 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_774 = and(_T_772, _T_773) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_775 = shr(io.in.a.bits.source, 2) node _T_776 = eq(_T_775, UInt<2>(0h2)) node _T_777 = leq(UInt<1>(0h0), uncommonBits_26) node _T_778 = and(_T_776, _T_777) node _T_779 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_780 = and(_T_778, _T_779) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_781 = shr(io.in.a.bits.source, 2) node _T_782 = eq(_T_781, UInt<2>(0h3)) node _T_783 = leq(UInt<1>(0h0), uncommonBits_27) node _T_784 = and(_T_782, _T_783) node _T_785 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_786 = and(_T_784, _T_785) node _T_787 = or(_T_762, _T_768) node _T_788 = or(_T_787, _T_774) node _T_789 = or(_T_788, _T_780) node _T_790 = or(_T_789, _T_786) node _T_791 = and(_T_761, _T_790) node _T_792 = or(UInt<1>(0h0), _T_791) node _T_793 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_794 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_795 = and(_T_793, _T_794) node _T_796 = or(UInt<1>(0h0), _T_795) node _T_797 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<14>(0h2000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_803 = cvt(_T_802) node _T_804 = and(_T_803, asSInt(UInt<13>(0h1000))) node _T_805 = asSInt(_T_804) node _T_806 = eq(_T_805, asSInt(UInt<1>(0h0))) node _T_807 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_808 = cvt(_T_807) node _T_809 = and(_T_808, asSInt(UInt<18>(0h2f000))) node _T_810 = asSInt(_T_809) node _T_811 = eq(_T_810, asSInt(UInt<1>(0h0))) node _T_812 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_813 = cvt(_T_812) node _T_814 = and(_T_813, asSInt(UInt<17>(0h10000))) node _T_815 = asSInt(_T_814) node _T_816 = eq(_T_815, asSInt(UInt<1>(0h0))) node _T_817 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_818 = cvt(_T_817) node _T_819 = and(_T_818, asSInt(UInt<27>(0h4000000))) node _T_820 = asSInt(_T_819) node _T_821 = eq(_T_820, asSInt(UInt<1>(0h0))) node _T_822 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_823 = cvt(_T_822) node _T_824 = and(_T_823, asSInt(UInt<13>(0h1000))) node _T_825 = asSInt(_T_824) node _T_826 = eq(_T_825, asSInt(UInt<1>(0h0))) node _T_827 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_828 = cvt(_T_827) node _T_829 = and(_T_828, asSInt(UInt<19>(0h40000))) node _T_830 = asSInt(_T_829) node _T_831 = eq(_T_830, asSInt(UInt<1>(0h0))) node _T_832 = or(_T_801, _T_806) node _T_833 = or(_T_832, _T_811) node _T_834 = or(_T_833, _T_816) node _T_835 = or(_T_834, _T_821) node _T_836 = or(_T_835, _T_826) node _T_837 = or(_T_836, _T_831) node _T_838 = and(_T_796, _T_837) node _T_839 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_840 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_841 = cvt(_T_840) node _T_842 = and(_T_841, asSInt(UInt<17>(0h10000))) node _T_843 = asSInt(_T_842) node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0))) node _T_845 = and(_T_839, _T_844) node _T_846 = or(UInt<1>(0h0), _T_838) node _T_847 = or(_T_846, _T_845) node _T_848 = and(_T_792, _T_847) node _T_849 = asUInt(reset) node _T_850 = eq(_T_849, UInt<1>(0h0)) when _T_850 : node _T_851 = eq(_T_848, UInt<1>(0h0)) when _T_851 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_848, UInt<1>(0h1), "") : assert_36 node _T_852 = asUInt(reset) node _T_853 = eq(_T_852, UInt<1>(0h0)) when _T_853 : node _T_854 = eq(source_ok, UInt<1>(0h0)) when _T_854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(is_aligned, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_858 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_858, UInt<1>(0h1), "") : assert_39 node _T_862 = eq(io.in.a.bits.mask, mask) node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(_T_862, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_862, UInt<1>(0h1), "") : assert_40 node _T_866 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_866 : node _T_867 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_868 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_869 = and(_T_867, _T_868) node _T_870 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_871 = shr(io.in.a.bits.source, 2) node _T_872 = eq(_T_871, UInt<1>(0h0)) node _T_873 = leq(UInt<1>(0h0), uncommonBits_28) node _T_874 = and(_T_872, _T_873) node _T_875 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_876 = and(_T_874, _T_875) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_877 = shr(io.in.a.bits.source, 2) node _T_878 = eq(_T_877, UInt<1>(0h1)) node _T_879 = leq(UInt<1>(0h0), uncommonBits_29) node _T_880 = and(_T_878, _T_879) node _T_881 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_882 = and(_T_880, _T_881) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_883 = shr(io.in.a.bits.source, 2) node _T_884 = eq(_T_883, UInt<2>(0h2)) node _T_885 = leq(UInt<1>(0h0), uncommonBits_30) node _T_886 = and(_T_884, _T_885) node _T_887 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_888 = and(_T_886, _T_887) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_889 = shr(io.in.a.bits.source, 2) node _T_890 = eq(_T_889, UInt<2>(0h3)) node _T_891 = leq(UInt<1>(0h0), uncommonBits_31) node _T_892 = and(_T_890, _T_891) node _T_893 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_894 = and(_T_892, _T_893) node _T_895 = or(_T_870, _T_876) node _T_896 = or(_T_895, _T_882) node _T_897 = or(_T_896, _T_888) node _T_898 = or(_T_897, _T_894) node _T_899 = and(_T_869, _T_898) node _T_900 = or(UInt<1>(0h0), _T_899) node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_903 = and(_T_901, _T_902) node _T_904 = or(UInt<1>(0h0), _T_903) node _T_905 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<14>(0h2000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<13>(0h1000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<18>(0h2f000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_921 = cvt(_T_920) node _T_922 = and(_T_921, asSInt(UInt<17>(0h10000))) node _T_923 = asSInt(_T_922) node _T_924 = eq(_T_923, asSInt(UInt<1>(0h0))) node _T_925 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_926 = cvt(_T_925) node _T_927 = and(_T_926, asSInt(UInt<27>(0h4000000))) node _T_928 = asSInt(_T_927) node _T_929 = eq(_T_928, asSInt(UInt<1>(0h0))) node _T_930 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_931 = cvt(_T_930) node _T_932 = and(_T_931, asSInt(UInt<13>(0h1000))) node _T_933 = asSInt(_T_932) node _T_934 = eq(_T_933, asSInt(UInt<1>(0h0))) node _T_935 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_936 = cvt(_T_935) node _T_937 = and(_T_936, asSInt(UInt<19>(0h40000))) node _T_938 = asSInt(_T_937) node _T_939 = eq(_T_938, asSInt(UInt<1>(0h0))) node _T_940 = or(_T_909, _T_914) node _T_941 = or(_T_940, _T_919) node _T_942 = or(_T_941, _T_924) node _T_943 = or(_T_942, _T_929) node _T_944 = or(_T_943, _T_934) node _T_945 = or(_T_944, _T_939) node _T_946 = and(_T_904, _T_945) node _T_947 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_948 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_949 = cvt(_T_948) node _T_950 = and(_T_949, asSInt(UInt<17>(0h10000))) node _T_951 = asSInt(_T_950) node _T_952 = eq(_T_951, asSInt(UInt<1>(0h0))) node _T_953 = and(_T_947, _T_952) node _T_954 = or(UInt<1>(0h0), _T_946) node _T_955 = or(_T_954, _T_953) node _T_956 = and(_T_900, _T_955) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_956, UInt<1>(0h1), "") : assert_41 node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(source_ok, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(is_aligned, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_966 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(_T_966, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_966, UInt<1>(0h1), "") : assert_44 node _T_970 = eq(io.in.a.bits.mask, mask) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_970, UInt<1>(0h1), "") : assert_45 node _T_974 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_974 : node _T_975 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_976 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_977 = and(_T_975, _T_976) node _T_978 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_979 = shr(io.in.a.bits.source, 2) node _T_980 = eq(_T_979, UInt<1>(0h0)) node _T_981 = leq(UInt<1>(0h0), uncommonBits_32) node _T_982 = and(_T_980, _T_981) node _T_983 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_984 = and(_T_982, _T_983) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_985 = shr(io.in.a.bits.source, 2) node _T_986 = eq(_T_985, UInt<1>(0h1)) node _T_987 = leq(UInt<1>(0h0), uncommonBits_33) node _T_988 = and(_T_986, _T_987) node _T_989 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_990 = and(_T_988, _T_989) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_991 = shr(io.in.a.bits.source, 2) node _T_992 = eq(_T_991, UInt<2>(0h2)) node _T_993 = leq(UInt<1>(0h0), uncommonBits_34) node _T_994 = and(_T_992, _T_993) node _T_995 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_996 = and(_T_994, _T_995) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_997 = shr(io.in.a.bits.source, 2) node _T_998 = eq(_T_997, UInt<2>(0h3)) node _T_999 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1000 = and(_T_998, _T_999) node _T_1001 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1002 = and(_T_1000, _T_1001) node _T_1003 = or(_T_978, _T_984) node _T_1004 = or(_T_1003, _T_990) node _T_1005 = or(_T_1004, _T_996) node _T_1006 = or(_T_1005, _T_1002) node _T_1007 = and(_T_977, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1010 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1011 = and(_T_1009, _T_1010) node _T_1012 = or(UInt<1>(0h0), _T_1011) node _T_1013 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1014 = cvt(_T_1013) node _T_1015 = and(_T_1014, asSInt(UInt<13>(0h1000))) node _T_1016 = asSInt(_T_1015) node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0))) node _T_1018 = and(_T_1012, _T_1017) node _T_1019 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1020 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1021 = cvt(_T_1020) node _T_1022 = and(_T_1021, asSInt(UInt<14>(0h2000))) node _T_1023 = asSInt(_T_1022) node _T_1024 = eq(_T_1023, asSInt(UInt<1>(0h0))) node _T_1025 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1026 = cvt(_T_1025) node _T_1027 = and(_T_1026, asSInt(UInt<17>(0h10000))) node _T_1028 = asSInt(_T_1027) node _T_1029 = eq(_T_1028, asSInt(UInt<1>(0h0))) node _T_1030 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1031 = cvt(_T_1030) node _T_1032 = and(_T_1031, asSInt(UInt<18>(0h2f000))) node _T_1033 = asSInt(_T_1032) node _T_1034 = eq(_T_1033, asSInt(UInt<1>(0h0))) node _T_1035 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1036 = cvt(_T_1035) node _T_1037 = and(_T_1036, asSInt(UInt<17>(0h10000))) node _T_1038 = asSInt(_T_1037) node _T_1039 = eq(_T_1038, asSInt(UInt<1>(0h0))) node _T_1040 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1041 = cvt(_T_1040) node _T_1042 = and(_T_1041, asSInt(UInt<27>(0h4000000))) node _T_1043 = asSInt(_T_1042) node _T_1044 = eq(_T_1043, asSInt(UInt<1>(0h0))) node _T_1045 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1046 = cvt(_T_1045) node _T_1047 = and(_T_1046, asSInt(UInt<13>(0h1000))) node _T_1048 = asSInt(_T_1047) node _T_1049 = eq(_T_1048, asSInt(UInt<1>(0h0))) node _T_1050 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1051 = cvt(_T_1050) node _T_1052 = and(_T_1051, asSInt(UInt<19>(0h40000))) node _T_1053 = asSInt(_T_1052) node _T_1054 = eq(_T_1053, asSInt(UInt<1>(0h0))) node _T_1055 = or(_T_1024, _T_1029) node _T_1056 = or(_T_1055, _T_1034) node _T_1057 = or(_T_1056, _T_1039) node _T_1058 = or(_T_1057, _T_1044) node _T_1059 = or(_T_1058, _T_1049) node _T_1060 = or(_T_1059, _T_1054) node _T_1061 = and(_T_1019, _T_1060) node _T_1062 = or(UInt<1>(0h0), _T_1018) node _T_1063 = or(_T_1062, _T_1061) node _T_1064 = and(_T_1008, _T_1063) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_46 node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(source_ok, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(is_aligned, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1074 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_49 node _T_1078 = eq(io.in.a.bits.mask, mask) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_50 node _T_1082 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1086 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_52 node _source_ok_T_28 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_29 = shr(io.in.d.bits.source, 2) node _source_ok_T_30 = eq(_source_ok_T_29, UInt<1>(0h0)) node _source_ok_T_31 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31) node _source_ok_T_33 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h1)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<2>(0h2)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h3)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) wire _source_ok_WIRE_1 : UInt<1>[5] connect _source_ok_WIRE_1[0], _source_ok_T_28 connect _source_ok_WIRE_1[1], _source_ok_T_34 connect _source_ok_WIRE_1[2], _source_ok_T_40 connect _source_ok_WIRE_1[3], _source_ok_T_46 connect _source_ok_WIRE_1[4], _source_ok_T_52 node _source_ok_T_53 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE_1[2]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE_1[3]) node source_ok_1 = or(_source_ok_T_55, _source_ok_WIRE_1[4]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1090 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1090 : node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(source_ok_1, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1094 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_54 node _T_1098 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_55 node _T_1102 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_56 node _T_1106 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_57 node _T_1110 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1110 : node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(source_ok_1, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(sink_ok, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1117 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_60 node _T_1121 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_61 node _T_1125 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_62 node _T_1129 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_63 node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1134 = or(UInt<1>(0h1), _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_64 node _T_1138 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1138 : node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(source_ok_1, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(sink_ok, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1145 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_67 node _T_1149 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_68 node _T_1153 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_69 node _T_1157 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1158 = or(_T_1157, io.in.d.bits.corrupt) node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(_T_1158, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1158, UInt<1>(0h1), "") : assert_70 node _T_1162 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1163 = or(UInt<1>(0h1), _T_1162) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_71 node _T_1167 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1167 : node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(source_ok_1, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1171 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_73 node _T_1175 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_74 node _T_1179 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1180 = or(UInt<1>(0h1), _T_1179) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_75 node _T_1184 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1184 : node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(source_ok_1, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1188 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1189 = asUInt(reset) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) when _T_1190 : node _T_1191 = eq(_T_1188, UInt<1>(0h0)) when _T_1191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1188, UInt<1>(0h1), "") : assert_77 node _T_1192 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1193 = or(_T_1192, io.in.d.bits.corrupt) node _T_1194 = asUInt(reset) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) when _T_1195 : node _T_1196 = eq(_T_1193, UInt<1>(0h0)) when _T_1196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1193, UInt<1>(0h1), "") : assert_78 node _T_1197 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1198 = or(UInt<1>(0h1), _T_1197) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_79 node _T_1202 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1202 : node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(source_ok_1, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1206 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1207 = asUInt(reset) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) when _T_1208 : node _T_1209 = eq(_T_1206, UInt<1>(0h0)) when _T_1209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1206, UInt<1>(0h1), "") : assert_81 node _T_1210 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1211 = asUInt(reset) node _T_1212 = eq(_T_1211, UInt<1>(0h0)) when _T_1212 : node _T_1213 = eq(_T_1210, UInt<1>(0h0)) when _T_1213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1210, UInt<1>(0h1), "") : assert_82 node _T_1214 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1215 = or(UInt<1>(0h1), _T_1214) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1219 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1223 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1227 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1231 = eq(a_first, UInt<1>(0h0)) node _T_1232 = and(io.in.a.valid, _T_1231) when _T_1232 : node _T_1233 = eq(io.in.a.bits.opcode, opcode) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_87 node _T_1237 = eq(io.in.a.bits.param, param) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_88 node _T_1241 = eq(io.in.a.bits.size, size) node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(_T_1241, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1241, UInt<1>(0h1), "") : assert_89 node _T_1245 = eq(io.in.a.bits.source, source) node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(_T_1245, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1245, UInt<1>(0h1), "") : assert_90 node _T_1249 = eq(io.in.a.bits.address, address) node _T_1250 = asUInt(reset) node _T_1251 = eq(_T_1250, UInt<1>(0h0)) when _T_1251 : node _T_1252 = eq(_T_1249, UInt<1>(0h0)) when _T_1252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1249, UInt<1>(0h1), "") : assert_91 node _T_1253 = and(io.in.a.ready, io.in.a.valid) node _T_1254 = and(_T_1253, a_first) when _T_1254 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1255 = eq(d_first, UInt<1>(0h0)) node _T_1256 = and(io.in.d.valid, _T_1255) when _T_1256 : node _T_1257 = eq(io.in.d.bits.opcode, opcode_1) node _T_1258 = asUInt(reset) node _T_1259 = eq(_T_1258, UInt<1>(0h0)) when _T_1259 : node _T_1260 = eq(_T_1257, UInt<1>(0h0)) when _T_1260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1257, UInt<1>(0h1), "") : assert_92 node _T_1261 = eq(io.in.d.bits.param, param_1) node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(_T_1261, UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1261, UInt<1>(0h1), "") : assert_93 node _T_1265 = eq(io.in.d.bits.size, size_1) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_94 node _T_1269 = eq(io.in.d.bits.source, source_1) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_95 node _T_1273 = eq(io.in.d.bits.sink, sink) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_96 node _T_1277 = eq(io.in.d.bits.denied, denied) node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(_T_1277, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1277, UInt<1>(0h1), "") : assert_97 node _T_1281 = and(io.in.d.ready, io.in.d.valid) node _T_1282 = and(_T_1281, d_first) when _T_1282 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<17>, clock, reset, UInt<17>(0h0) regreset inflight_opcodes : UInt<68>, clock, reset, UInt<68>(0h0) regreset inflight_sizes : UInt<136>, clock, reset, UInt<136>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<17> connect a_set, UInt<17>(0h0) wire a_set_wo_ready : UInt<17> connect a_set_wo_ready, UInt<17>(0h0) wire a_opcodes_set : UInt<68> connect a_opcodes_set, UInt<68>(0h0) wire a_sizes_set : UInt<136> connect a_sizes_set, UInt<136>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1283 = and(io.in.a.valid, a_first_1) node _T_1284 = and(_T_1283, UInt<1>(0h1)) when _T_1284 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1285 = and(io.in.a.ready, io.in.a.valid) node _T_1286 = and(_T_1285, a_first_1) node _T_1287 = and(_T_1286, UInt<1>(0h1)) when _T_1287 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1288 = dshr(inflight, io.in.a.bits.source) node _T_1289 = bits(_T_1288, 0, 0) node _T_1290 = eq(_T_1289, UInt<1>(0h0)) node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(_T_1290, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1290, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<17> connect d_clr, UInt<17>(0h0) wire d_clr_wo_ready : UInt<17> connect d_clr_wo_ready, UInt<17>(0h0) wire d_opcodes_clr : UInt<68> connect d_opcodes_clr, UInt<68>(0h0) wire d_sizes_clr : UInt<136> connect d_sizes_clr, UInt<136>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1294 = and(io.in.d.valid, d_first_1) node _T_1295 = and(_T_1294, UInt<1>(0h1)) node _T_1296 = eq(d_release_ack, UInt<1>(0h0)) node _T_1297 = and(_T_1295, _T_1296) when _T_1297 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1298 = and(io.in.d.ready, io.in.d.valid) node _T_1299 = and(_T_1298, d_first_1) node _T_1300 = and(_T_1299, UInt<1>(0h1)) node _T_1301 = eq(d_release_ack, UInt<1>(0h0)) node _T_1302 = and(_T_1300, _T_1301) when _T_1302 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1303 = and(io.in.d.valid, d_first_1) node _T_1304 = and(_T_1303, UInt<1>(0h1)) node _T_1305 = eq(d_release_ack, UInt<1>(0h0)) node _T_1306 = and(_T_1304, _T_1305) when _T_1306 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1307 = dshr(inflight, io.in.d.bits.source) node _T_1308 = bits(_T_1307, 0, 0) node _T_1309 = or(_T_1308, same_cycle_resp) node _T_1310 = asUInt(reset) node _T_1311 = eq(_T_1310, UInt<1>(0h0)) when _T_1311 : node _T_1312 = eq(_T_1309, UInt<1>(0h0)) when _T_1312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1309, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1313 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1314 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1315 = or(_T_1313, _T_1314) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_100 node _T_1319 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(_T_1319, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1319, UInt<1>(0h1), "") : assert_101 else : node _T_1323 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1324 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1325 = or(_T_1323, _T_1324) node _T_1326 = asUInt(reset) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) when _T_1327 : node _T_1328 = eq(_T_1325, UInt<1>(0h0)) when _T_1328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1325, UInt<1>(0h1), "") : assert_102 node _T_1329 = eq(io.in.d.bits.size, a_size_lookup) node _T_1330 = asUInt(reset) node _T_1331 = eq(_T_1330, UInt<1>(0h0)) when _T_1331 : node _T_1332 = eq(_T_1329, UInt<1>(0h0)) when _T_1332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1329, UInt<1>(0h1), "") : assert_103 node _T_1333 = and(io.in.d.valid, d_first_1) node _T_1334 = and(_T_1333, a_first_1) node _T_1335 = and(_T_1334, io.in.a.valid) node _T_1336 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1337 = and(_T_1335, _T_1336) node _T_1338 = eq(d_release_ack, UInt<1>(0h0)) node _T_1339 = and(_T_1337, _T_1338) when _T_1339 : node _T_1340 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1341 = or(_T_1340, io.in.a.ready) node _T_1342 = asUInt(reset) node _T_1343 = eq(_T_1342, UInt<1>(0h0)) when _T_1343 : node _T_1344 = eq(_T_1341, UInt<1>(0h0)) when _T_1344 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1341, UInt<1>(0h1), "") : assert_104 node _T_1345 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1346 = orr(a_set_wo_ready) node _T_1347 = eq(_T_1346, UInt<1>(0h0)) node _T_1348 = or(_T_1345, _T_1347) node _T_1349 = asUInt(reset) node _T_1350 = eq(_T_1349, UInt<1>(0h0)) when _T_1350 : node _T_1351 = eq(_T_1348, UInt<1>(0h0)) when _T_1351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1348, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_6 node _T_1352 = orr(inflight) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) node _T_1354 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1355 = or(_T_1353, _T_1354) node _T_1356 = lt(watchdog, plusarg_reader.out) node _T_1357 = or(_T_1355, _T_1356) node _T_1358 = asUInt(reset) node _T_1359 = eq(_T_1358, UInt<1>(0h0)) when _T_1359 : node _T_1360 = eq(_T_1357, UInt<1>(0h0)) when _T_1360 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1357, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1361 = and(io.in.a.ready, io.in.a.valid) node _T_1362 = and(io.in.d.ready, io.in.d.valid) node _T_1363 = or(_T_1361, _T_1362) when _T_1363 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<17>, clock, reset, UInt<17>(0h0) regreset inflight_opcodes_1 : UInt<68>, clock, reset, UInt<68>(0h0) regreset inflight_sizes_1 : UInt<136>, clock, reset, UInt<136>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<17> connect c_set, UInt<17>(0h0) wire c_set_wo_ready : UInt<17> connect c_set_wo_ready, UInt<17>(0h0) wire c_opcodes_set : UInt<68> connect c_opcodes_set, UInt<68>(0h0) wire c_sizes_set : UInt<136> connect c_sizes_set, UInt<136>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1364 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1365 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1366 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1367 = and(_T_1365, _T_1366) node _T_1368 = and(_T_1364, _T_1367) when _T_1368 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1369 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1370 = and(_T_1369, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1371 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1372 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1373 = and(_T_1371, _T_1372) node _T_1374 = and(_T_1370, _T_1373) when _T_1374 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1375 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1376 = bits(_T_1375, 0, 0) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) node _T_1378 = asUInt(reset) node _T_1379 = eq(_T_1378, UInt<1>(0h0)) when _T_1379 : node _T_1380 = eq(_T_1377, UInt<1>(0h0)) when _T_1380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1377, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<17> connect d_clr_1, UInt<17>(0h0) wire d_clr_wo_ready_1 : UInt<17> connect d_clr_wo_ready_1, UInt<17>(0h0) wire d_opcodes_clr_1 : UInt<68> connect d_opcodes_clr_1, UInt<68>(0h0) wire d_sizes_clr_1 : UInt<136> connect d_sizes_clr_1, UInt<136>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1381 = and(io.in.d.valid, d_first_2) node _T_1382 = and(_T_1381, UInt<1>(0h1)) node _T_1383 = and(_T_1382, d_release_ack_1) when _T_1383 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1384 = and(io.in.d.ready, io.in.d.valid) node _T_1385 = and(_T_1384, d_first_2) node _T_1386 = and(_T_1385, UInt<1>(0h1)) node _T_1387 = and(_T_1386, d_release_ack_1) when _T_1387 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1388 = and(io.in.d.valid, d_first_2) node _T_1389 = and(_T_1388, UInt<1>(0h1)) node _T_1390 = and(_T_1389, d_release_ack_1) when _T_1390 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1391 = dshr(inflight_1, io.in.d.bits.source) node _T_1392 = bits(_T_1391, 0, 0) node _T_1393 = or(_T_1392, same_cycle_resp_1) node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(_T_1393, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1393, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1397 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1398 = asUInt(reset) node _T_1399 = eq(_T_1398, UInt<1>(0h0)) when _T_1399 : node _T_1400 = eq(_T_1397, UInt<1>(0h0)) when _T_1400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1397, UInt<1>(0h1), "") : assert_109 else : node _T_1401 = eq(io.in.d.bits.size, c_size_lookup) node _T_1402 = asUInt(reset) node _T_1403 = eq(_T_1402, UInt<1>(0h0)) when _T_1403 : node _T_1404 = eq(_T_1401, UInt<1>(0h0)) when _T_1404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1401, UInt<1>(0h1), "") : assert_110 node _T_1405 = and(io.in.d.valid, d_first_2) node _T_1406 = and(_T_1405, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1407 = and(_T_1406, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1408 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1409 = and(_T_1407, _T_1408) node _T_1410 = and(_T_1409, d_release_ack_1) node _T_1411 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1412 = and(_T_1410, _T_1411) when _T_1412 : node _T_1413 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1414 = or(_T_1413, _WIRE_23.ready) node _T_1415 = asUInt(reset) node _T_1416 = eq(_T_1415, UInt<1>(0h0)) when _T_1416 : node _T_1417 = eq(_T_1414, UInt<1>(0h0)) when _T_1417 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1414, UInt<1>(0h1), "") : assert_111 node _T_1418 = orr(c_set_wo_ready) when _T_1418 : node _T_1419 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1420 = asUInt(reset) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) when _T_1421 : node _T_1422 = eq(_T_1419, UInt<1>(0h0)) when _T_1422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1419, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_7 node _T_1423 = orr(inflight_1) node _T_1424 = eq(_T_1423, UInt<1>(0h0)) node _T_1425 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1426 = or(_T_1424, _T_1425) node _T_1427 = lt(watchdog_1, plusarg_reader_1.out) node _T_1428 = or(_T_1426, _T_1427) node _T_1429 = asUInt(reset) node _T_1430 = eq(_T_1429, UInt<1>(0h0)) when _T_1430 : node _T_1431 = eq(_T_1428, UInt<1>(0h0)) when _T_1431 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:206:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1428, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1432 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1433 = and(io.in.d.ready, io.in.d.valid) node _T_1434 = or(_T_1432, _T_1433) when _T_1434 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_3( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1361 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1361; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1361; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1434 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1434; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1434; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1434; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1287 = _T_1361 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1287 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1287 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1287 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1287 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1287 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1333 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1333 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1302 = _T_1434 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1302 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1302 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1302 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1405 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1405 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1387 = _T_1434 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1387 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1387 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1387 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module FMADecoder_5 : input clock : Clock input reset : Reset output io : { flip uopc : UInt<7>, cmd : UInt<2>} wire decoder_decoded_plaInput : UInt<7> node decoder_decoded_invInputs = not(decoder_decoded_plaInput) wire decoder_decoded : UInt<2> node decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoder_decoded_invInputs, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoder_decoded_invInputs, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5) node decoder_decoded_andMatrixOutputs_lo = cat(decoder_decoded_andMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_6) node decoder_decoded_andMatrixOutputs_hi_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2, decoder_decoded_andMatrixOutputs_andMatrixInput_3) node decoder_decoded_andMatrixOutputs_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0, decoder_decoded_andMatrixOutputs_andMatrixInput_1) node decoder_decoded_andMatrixOutputs_hi = cat(decoder_decoded_andMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_hi_lo) node _decoder_decoded_andMatrixOutputs_T = cat(decoder_decoded_andMatrixOutputs_hi, decoder_decoded_andMatrixOutputs_lo) node decoder_decoded_andMatrixOutputs_6_2 = andr(_decoder_decoded_andMatrixOutputs_T) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_1, decoder_decoded_andMatrixOutputs_andMatrixInput_4_1) node decoder_decoded_andMatrixOutputs_lo_1 = cat(decoder_decoded_andMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_1) node decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, decoder_decoded_andMatrixOutputs_andMatrixInput_1_1) node decoder_decoded_andMatrixOutputs_hi_1 = cat(decoder_decoded_andMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_1) node _decoder_decoded_andMatrixOutputs_T_1 = cat(decoder_decoded_andMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_lo_1) node decoder_decoded_andMatrixOutputs_0_2 = andr(_decoder_decoded_andMatrixOutputs_T_1) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_2, decoder_decoded_andMatrixOutputs_andMatrixInput_4_2) node decoder_decoded_andMatrixOutputs_lo_2 = cat(decoder_decoded_andMatrixOutputs_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_2) node decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, decoder_decoded_andMatrixOutputs_andMatrixInput_1_2) node decoder_decoded_andMatrixOutputs_hi_2 = cat(decoder_decoded_andMatrixOutputs_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_2) node _decoder_decoded_andMatrixOutputs_T_2 = cat(decoder_decoded_andMatrixOutputs_hi_2, decoder_decoded_andMatrixOutputs_lo_2) node decoder_decoded_andMatrixOutputs_1_2 = andr(_decoder_decoded_andMatrixOutputs_T_2) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_3) node decoder_decoded_andMatrixOutputs_lo_3 = cat(decoder_decoded_andMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_6_1) node decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, decoder_decoded_andMatrixOutputs_andMatrixInput_3_3) node decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, decoder_decoded_andMatrixOutputs_andMatrixInput_1_3) node decoder_decoded_andMatrixOutputs_hi_3 = cat(decoder_decoded_andMatrixOutputs_hi_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_1) node _decoder_decoded_andMatrixOutputs_T_3 = cat(decoder_decoded_andMatrixOutputs_hi_3, decoder_decoded_andMatrixOutputs_lo_3) node decoder_decoded_andMatrixOutputs_2_2 = andr(_decoder_decoded_andMatrixOutputs_T_3) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoder_decoded_invInputs, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoder_decoded_invInputs, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, decoder_decoded_andMatrixOutputs_andMatrixInput_4_4) node decoder_decoded_andMatrixOutputs_lo_4 = cat(decoder_decoded_andMatrixOutputs_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_4) node decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, decoder_decoded_andMatrixOutputs_andMatrixInput_1_4) node decoder_decoded_andMatrixOutputs_hi_4 = cat(decoder_decoded_andMatrixOutputs_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_4) node _decoder_decoded_andMatrixOutputs_T_4 = cat(decoder_decoded_andMatrixOutputs_hi_4, decoder_decoded_andMatrixOutputs_lo_4) node decoder_decoded_andMatrixOutputs_4_2 = andr(_decoder_decoded_andMatrixOutputs_T_4) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, decoder_decoded_andMatrixOutputs_andMatrixInput_4_5) node decoder_decoded_andMatrixOutputs_lo_5 = cat(decoder_decoded_andMatrixOutputs_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_5_5) node decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, decoder_decoded_andMatrixOutputs_andMatrixInput_1_5) node decoder_decoded_andMatrixOutputs_hi_5 = cat(decoder_decoded_andMatrixOutputs_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_5) node _decoder_decoded_andMatrixOutputs_T_5 = cat(decoder_decoded_andMatrixOutputs_hi_5, decoder_decoded_andMatrixOutputs_lo_5) node decoder_decoded_andMatrixOutputs_3_2 = andr(_decoder_decoded_andMatrixOutputs_T_5) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_6) node decoder_decoded_andMatrixOutputs_lo_6 = cat(decoder_decoded_andMatrixOutputs_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_6_2) node decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, decoder_decoded_andMatrixOutputs_andMatrixInput_3_6) node decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, decoder_decoded_andMatrixOutputs_andMatrixInput_1_6) node decoder_decoded_andMatrixOutputs_hi_6 = cat(decoder_decoded_andMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_lo_2) node _decoder_decoded_andMatrixOutputs_T_6 = cat(decoder_decoded_andMatrixOutputs_hi_6, decoder_decoded_andMatrixOutputs_lo_6) node decoder_decoded_andMatrixOutputs_5_2 = andr(_decoder_decoded_andMatrixOutputs_T_6) node decoder_decoded_orMatrixOutputs_lo = cat(decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_3_2) node decoder_decoded_orMatrixOutputs_hi = cat(decoder_decoded_andMatrixOutputs_6_2, decoder_decoded_andMatrixOutputs_0_2) node _decoder_decoded_orMatrixOutputs_T = cat(decoder_decoded_orMatrixOutputs_hi, decoder_decoded_orMatrixOutputs_lo) node _decoder_decoded_orMatrixOutputs_T_1 = orr(_decoder_decoded_orMatrixOutputs_T) node decoder_decoded_orMatrixOutputs_hi_1 = cat(decoder_decoded_andMatrixOutputs_2_2, decoder_decoded_andMatrixOutputs_4_2) node _decoder_decoded_orMatrixOutputs_T_2 = cat(decoder_decoded_orMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_5_2) node _decoder_decoded_orMatrixOutputs_T_3 = orr(_decoder_decoded_orMatrixOutputs_T_2) node decoder_decoded_orMatrixOutputs = cat(_decoder_decoded_orMatrixOutputs_T_3, _decoder_decoded_orMatrixOutputs_T_1) node _decoder_decoded_invMatrixOutputs_T = bits(decoder_decoded_orMatrixOutputs, 0, 0) node _decoder_decoded_invMatrixOutputs_T_1 = bits(decoder_decoded_orMatrixOutputs, 1, 1) node decoder_decoded_invMatrixOutputs = cat(_decoder_decoded_invMatrixOutputs_T_1, _decoder_decoded_invMatrixOutputs_T) connect decoder_decoded, decoder_decoded_invMatrixOutputs connect decoder_decoded_plaInput, io.uopc node decoder_0 = bits(decoder_decoded, 1, 0) connect io.cmd, decoder_0
module FMADecoder_5( // @[fpu.scala:123:7] input clock, // @[fpu.scala:123:7] input reset, // @[fpu.scala:123:7] input [6:0] io_uopc, // @[fpu.scala:125:14] output [1:0] io_cmd // @[fpu.scala:125:14] ); wire [6:0] io_uopc_0 = io_uopc; // @[fpu.scala:123:7] wire [6:0] decoder_decoded_plaInput = io_uopc_0; // @[pla.scala:77:22] wire [1:0] decoder_0; // @[Decode.scala:50:77] wire [1:0] io_cmd_0; // @[fpu.scala:123:7] wire [6:0] decoder_decoded_invInputs = ~decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [1:0] decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [1:0] decoder_decoded; // @[pla.scala:81:23] assign decoder_0 = decoder_decoded; // @[pla.scala:81:23] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0 = decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo = {decoder_decoded_andMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_2, decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0, decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi = {decoder_decoded_andMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T = {decoder_decoded_andMatrixOutputs_hi, decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_6_2 = &_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_1, decoder_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_1 = {decoder_decoded_andMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_1 = {decoder_decoded_andMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_1 = {decoder_decoded_andMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_0_2 = &_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_2, decoder_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_2 = {decoder_decoded_andMatrixOutputs_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_2 = {decoder_decoded_andMatrixOutputs_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_2 = {decoder_decoded_andMatrixOutputs_hi_2, decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_1_2 = &_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_3 = {decoder_decoded_andMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_3 = {decoder_decoded_andMatrixOutputs_hi_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_3 = {decoder_decoded_andMatrixOutputs_hi_3, decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_2_2 = &_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_4 = {decoder_decoded_andMatrixOutputs_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_4 = {decoder_decoded_andMatrixOutputs_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_4 = {decoder_decoded_andMatrixOutputs_hi_4, decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_4_2 = &_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_5 = {decoder_decoded_andMatrixOutputs_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_5 = {decoder_decoded_andMatrixOutputs_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_5 = {decoder_decoded_andMatrixOutputs_hi_5, decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_3_2 = &_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_6 = {decoder_decoded_andMatrixOutputs_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, decoder_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_6 = {decoder_decoded_andMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_6 = {decoder_decoded_andMatrixOutputs_hi_6, decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_5_2 = &_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_orMatrixOutputs_lo = {decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi = {decoder_decoded_andMatrixOutputs_6_2, decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _decoder_decoded_orMatrixOutputs_T = {decoder_decoded_orMatrixOutputs_hi, decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_1 = |_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_hi_1 = {decoder_decoded_andMatrixOutputs_2_2, decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _decoder_decoded_orMatrixOutputs_T_2 = {decoder_decoded_orMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_3 = |_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs = {_decoder_decoded_orMatrixOutputs_T_3, _decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire _decoder_decoded_invMatrixOutputs_T = decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_1 = decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] assign decoder_decoded_invMatrixOutputs = {_decoder_decoded_invMatrixOutputs_T_1, _decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] assign decoder_decoded = decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign io_cmd_0 = decoder_0; // @[Decode.scala:50:77] assign io_cmd = io_cmd_0; // @[fpu.scala:123:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_121 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_377 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_121( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_377 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_10 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<8>, sig : UInt<33>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hc0))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node _adjustedSig_T = bits(io.in.sig, 32, 7) node _adjustedSig_T_1 = bits(io.in.sig, 6, 0) node _adjustedSig_T_2 = orr(_adjustedSig_T_1) node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = cat(UInt<24>(0h0), UInt<1>(0h0)) node roundMask = cat(_roundMask_T, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) connect common_underflow, UInt<1>(0h0) node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_10( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [7:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [32:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [7:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [32:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [24:0] _roundMask_T = 25'h0; // @[RoundAnyRawFNToRecFN.scala:153:36] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] roundMask = 27'h3; // @[RoundAnyRawFNToRecFN.scala:153:55] wire [27:0] _shiftedRoundMask_T = 28'h3; // @[RoundAnyRawFNToRecFN.scala:162:41] wire [26:0] shiftedRoundMask = 27'h1; // @[RoundAnyRawFNToRecFN.scala:162:53] wire [26:0] _roundPosMask_T = 27'h7FFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28] wire [26:0] roundPosMask = 27'h2; // @[RoundAnyRawFNToRecFN.scala:163:46] wire [26:0] _roundedSig_T_10 = 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32] wire [25:0] _roundedSig_T_6 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [25:0] _roundedSig_T_14 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:265:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:277:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:278:16] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32] wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22] wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire [9:0] _sAdjustedExp_T = {{2{io_in_sExp_0[7]}}, io_in_sExp_0} + 10'hC0; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25] wire [8:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[8:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14] wire [9:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}] wire [25:0] _adjustedSig_T = io_in_sig_0[32:7]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23] wire [6:0] _adjustedSig_T_1 = io_in_sig_0[6:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26] wire _adjustedSig_T_2 = |_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}] wire [26:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [26:0] _roundPosBit_T = adjustedSig & 27'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & 27'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | 27'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_7 = {25'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_11 = adjustedSig & 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {sAdjustedExp[9], sAdjustedExp} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15] wire [8:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73] wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? 23'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_200 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_217 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_200( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_217 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_106 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = or(_T_667, _T_672) node _T_699 = or(_T_698, _T_677) node _T_700 = or(_T_699, _T_682) node _T_701 = or(_T_700, _T_687) node _T_702 = or(_T_701, _T_692) node _T_703 = or(_T_702, _T_697) node _T_704 = and(_T_662, _T_703) node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = and(_T_705, _T_710) node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_714 = and(_T_712, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = or(_T_720, _T_725) node _T_727 = and(_T_715, _T_726) node _T_728 = or(UInt<1>(0h0), _T_704) node _T_729 = or(_T_728, _T_711) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_731, UInt<1>(0h1), "") : assert_36 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_741, UInt<1>(0h1), "") : assert_39 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_745, UInt<1>(0h1), "") : assert_40 node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = or(_T_764, _T_769) node _T_796 = or(_T_795, _T_774) node _T_797 = or(_T_796, _T_779) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_789) node _T_800 = or(_T_799, _T_794) node _T_801 = and(_T_759, _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = or(_T_817, _T_822) node _T_824 = and(_T_812, _T_823) node _T_825 = or(UInt<1>(0h0), _T_801) node _T_826 = or(_T_825, _T_808) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_828, UInt<1>(0h1), "") : assert_41 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_838, UInt<1>(0h1), "") : assert_44 node _T_842 = eq(io.in.a.bits.mask, mask) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_842, UInt<1>(0h1), "") : assert_45 node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_846 : node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_849 = and(_T_847, _T_848) node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = or(_T_868, _T_873) node _T_900 = or(_T_899, _T_878) node _T_901 = or(_T_900, _T_883) node _T_902 = or(_T_901, _T_888) node _T_903 = or(_T_902, _T_893) node _T_904 = or(_T_903, _T_898) node _T_905 = and(_T_863, _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_862) node _T_923 = or(_T_922, _T_905) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_852, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_925, UInt<1>(0h1), "") : assert_46 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_935, UInt<1>(0h1), "") : assert_49 node _T_939 = eq(io.in.a.bits.mask, mask) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_939, UInt<1>(0h1), "") : assert_50 node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_943, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_947, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<8>(0h80)) node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_955 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_955, UInt<1>(0h1), "") : assert_54 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_959, UInt<1>(0h1), "") : assert_55 node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_963, UInt<1>(0h1), "") : assert_56 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_967, UInt<1>(0h1), "") : assert_57 node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(sink_ok, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_978 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_978, UInt<1>(0h1), "") : assert_60 node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_982, UInt<1>(0h1), "") : assert_61 node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_986, UInt<1>(0h1), "") : assert_62 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_990, UInt<1>(0h1), "") : assert_63 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_995, UInt<1>(0h1), "") : assert_64 node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(sink_ok, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67 node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68 node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h1), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71 node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h1), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75 node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1045 : node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79 node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}} connect _WIRE_4.bits.sink, UInt<7>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1092 = eq(a_first, UInt<1>(0h0)) node _T_1093 = and(io.in.a.valid, _T_1092) when _T_1093 : node _T_1094 = eq(io.in.a.bits.opcode, opcode) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87 node _T_1098 = eq(io.in.a.bits.param, param) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88 node _T_1102 = eq(io.in.a.bits.size, size) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89 node _T_1106 = eq(io.in.a.bits.source, source) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90 node _T_1110 = eq(io.in.a.bits.address, address) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91 node _T_1114 = and(io.in.a.ready, io.in.a.valid) node _T_1115 = and(_T_1114, a_first) when _T_1115 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1116 = eq(d_first, UInt<1>(0h0)) node _T_1117 = and(io.in.d.valid, _T_1116) when _T_1117 : node _T_1118 = eq(io.in.d.bits.opcode, opcode_1) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92 node _T_1122 = eq(io.in.d.bits.param, param_1) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93 node _T_1126 = eq(io.in.d.bits.size, size_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94 node _T_1130 = eq(io.in.d.bits.source, source_1) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95 node _T_1134 = eq(io.in.d.bits.sink, sink) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96 node _T_1138 = eq(io.in.d.bits.denied, denied) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97 node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = and(_T_1142, d_first) when _T_1143 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1144 = and(io.in.a.valid, a_first_1) node _T_1145 = and(_T_1144, UInt<1>(0h1)) when _T_1145 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1146 = and(io.in.a.ready, io.in.a.valid) node _T_1147 = and(_T_1146, a_first_1) node _T_1148 = and(_T_1147, UInt<1>(0h1)) when _T_1148 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1149 = dshr(inflight, io.in.a.bits.source) node _T_1150 = bits(_T_1149, 0, 0) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1155 = and(io.in.d.valid, d_first_1) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = eq(d_release_ack, UInt<1>(0h0)) node _T_1158 = and(_T_1156, _T_1157) when _T_1158 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1159 = and(io.in.d.ready, io.in.d.valid) node _T_1160 = and(_T_1159, d_first_1) node _T_1161 = and(_T_1160, UInt<1>(0h1)) node _T_1162 = eq(d_release_ack, UInt<1>(0h0)) node _T_1163 = and(_T_1161, _T_1162) when _T_1163 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1164 = and(io.in.d.valid, d_first_1) node _T_1165 = and(_T_1164, UInt<1>(0h1)) node _T_1166 = eq(d_release_ack, UInt<1>(0h0)) node _T_1167 = and(_T_1165, _T_1166) when _T_1167 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1168 = dshr(inflight, io.in.d.bits.source) node _T_1169 = bits(_T_1168, 0, 0) node _T_1170 = or(_T_1169, same_cycle_resp) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100 node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101 else : node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1186 = or(_T_1184, _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102 node _T_1190 = eq(io.in.d.bits.size, a_size_lookup) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103 node _T_1194 = and(io.in.d.valid, d_first_1) node _T_1195 = and(_T_1194, a_first_1) node _T_1196 = and(_T_1195, io.in.a.valid) node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = eq(d_release_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.a.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104 node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1207 = orr(a_set_wo_ready) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = or(_T_1206, _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_219 node _T_1213 = orr(inflight) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog, plusarg_reader.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1222 = and(io.in.a.ready, io.in.a.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1225 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1231 = and(_T_1230, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = and(_T_1231, _T_1234) when _T_1235 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1237 = bits(_T_1236, 0, 0) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1242 = and(io.in.d.valid, d_first_2) node _T_1243 = and(_T_1242, UInt<1>(0h1)) node _T_1244 = and(_T_1243, d_release_ack_1) when _T_1244 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1245 = and(io.in.d.ready, io.in.d.valid) node _T_1246 = and(_T_1245, d_first_2) node _T_1247 = and(_T_1246, UInt<1>(0h1)) node _T_1248 = and(_T_1247, d_release_ack_1) when _T_1248 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1249 = and(io.in.d.valid, d_first_2) node _T_1250 = and(_T_1249, UInt<1>(0h1)) node _T_1251 = and(_T_1250, d_release_ack_1) when _T_1251 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1252 = dshr(inflight_1, io.in.d.bits.source) node _T_1253 = bits(_T_1252, 0, 0) node _T_1254 = or(_T_1253, same_cycle_resp_1) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109 else : node _T_1262 = eq(io.in.d.bits.size, c_size_lookup) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _T_1266 = and(io.in.d.valid, d_first_2) node _T_1267 = and(_T_1266, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1268 = and(_T_1267, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = and(_T_1270, d_release_ack_1) node _T_1272 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1275 = or(_T_1274, _WIRE_23.ready) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111 node _T_1279 = orr(c_set_wo_ready) when _T_1279 : node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_220 node _T_1284 = orr(inflight_1) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1287 = or(_T_1285, _T_1286) node _T_1288 = lt(watchdog_1, plusarg_reader_1.out) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1294 = and(io.in.d.ready, io.in.d.valid) node _T_1295 = or(_T_1293, _T_1294) when _T_1295 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_106( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [6:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_5 = 2'h1 << _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1194 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1163 = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1163 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1163 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1163 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1248 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1248 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1248 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1248 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_6 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_12 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_6 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<4>(0hb), io.in.bits.egress_id) node _T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _T_2 = eq(UInt<4>(0h9), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _T_4 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _T_5 = or(_T, _T_1) node _T_6 = or(_T_5, _T_2) node _T_7 = or(_T_6, _T_3) node _T_8 = or(_T_7, _T_4) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = and(io.in.valid, _T_9) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_11, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<2>(0h3) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<2>(0h2) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0hb), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<4>(0h9), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0hb), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0h8), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0hc), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_5, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_T_10, _route_buffer_io_enq_bits_flow_egress_node_T_7) node _route_buffer_io_enq_bits_flow_egress_node_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_T_11, _route_buffer_io_enq_bits_flow_egress_node_T_8) node _route_buffer_io_enq_bits_flow_egress_node_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_T_12, _route_buffer_io_enq_bits_flow_egress_node_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_13 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0hb), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<4>(0h9), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_10, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_11, _route_buffer_io_enq_bits_flow_egress_node_id_T_8) node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_12, _route_buffer_io_enq_bits_flow_egress_node_id_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_13 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<2>(0h3)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] node _T_15 = and(io.in.ready, io.in.valid) node _T_16 = and(_T_15, io.in.bits.head) node _T_17 = and(_T_16, at_dest) when _T_17 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) node _T_18 = eq(UInt<3>(0h4), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_19 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_20 = and(route_q.io.enq.valid, _T_19) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_13 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_6 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] node _T_25 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_26 = and(vcalloc_q.io.enq.valid, _T_25) node _T_27 = eq(_T_26, UInt<1>(0h0)) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_27, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node c_lo = cat(c_lo_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node c_hi = cat(c_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _c_T = cat(c_hi, c_lo) node _c_T_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_lo_hi_1 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node c_lo_1 = cat(c_lo_hi_1, io.out_credit_available.`0`[0]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node c_hi_1 = cat(c_hi_hi_1, io.out_credit_available.`0`[3]) node _c_T_2 = cat(c_hi_1, c_lo_1) node _c_T_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_channel_oh_0 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 5, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_10 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1
module IngressUnit_6( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'hB; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = io_in_bits_egress_id == 5'h9; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hD; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_13 = (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'hB : 4'h0) | {_route_buffer_io_enq_bits_flow_egress_node_id_T_13, 3'h0} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'hC : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 4'hA : 4'h0); // @[Mux.scala:30:73] wire [1:0] route_buffer_io_enq_bits_flow_egress_node_id = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_13}; // @[IngressUnit.scala:30:72, :45:50] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 == 4'h3; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 != 4'h3; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_172 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_172( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_421 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_165 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_421( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_165 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_31 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_50 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_51 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_52 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_53 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_54 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_55 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_56 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_57 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_58 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_59 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_61 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[42] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 connect _source_ok_WIRE[30], _source_ok_T_50 connect _source_ok_WIRE[31], _source_ok_T_51 connect _source_ok_WIRE[32], _source_ok_T_52 connect _source_ok_WIRE[33], _source_ok_T_53 connect _source_ok_WIRE[34], _source_ok_T_54 connect _source_ok_WIRE[35], _source_ok_T_55 connect _source_ok_WIRE[36], _source_ok_T_56 connect _source_ok_WIRE[37], _source_ok_T_57 connect _source_ok_WIRE[38], _source_ok_T_58 connect _source_ok_WIRE[39], _source_ok_T_59 connect _source_ok_WIRE[40], _source_ok_T_60 connect _source_ok_WIRE[41], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[6]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[7]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[8]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[9]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[10]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[11]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[12]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[13]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[14]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[15]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[16]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[17]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[18]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[19]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[20]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[21]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[22]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[23]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[24]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[25]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[26]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[27]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[28]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[29]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[30]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE[31]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE[32]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE[33]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE[34]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE[35]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE[36]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE[37]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE[38]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE[39]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE[40]) node source_ok = or(_source_ok_T_101, _source_ok_WIRE[41]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = or(_T_273, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_281 = eq(_T_280, UInt<1>(0h0)) node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_289, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_297, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_305 = eq(_T_304, UInt<1>(0h0)) node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = or(_T_305, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_321 = eq(_T_320, UInt<1>(0h0)) node _T_322 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = or(_T_321, _T_326) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_329 = eq(_T_328, UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = or(_T_329, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_337, _T_342) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = or(_T_345, _T_350) node _T_352 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = or(_T_353, _T_358) node _T_360 = and(_T_11, _T_24) node _T_361 = and(_T_360, _T_37) node _T_362 = and(_T_361, _T_50) node _T_363 = and(_T_362, _T_63) node _T_364 = and(_T_363, _T_71) node _T_365 = and(_T_364, _T_79) node _T_366 = and(_T_365, _T_87) node _T_367 = and(_T_366, _T_95) node _T_368 = and(_T_367, _T_103) node _T_369 = and(_T_368, _T_111) node _T_370 = and(_T_369, _T_119) node _T_371 = and(_T_370, _T_127) node _T_372 = and(_T_371, _T_135) node _T_373 = and(_T_372, _T_143) node _T_374 = and(_T_373, _T_151) node _T_375 = and(_T_374, _T_159) node _T_376 = and(_T_375, _T_167) node _T_377 = and(_T_376, _T_175) node _T_378 = and(_T_377, _T_183) node _T_379 = and(_T_378, _T_191) node _T_380 = and(_T_379, _T_199) node _T_381 = and(_T_380, _T_207) node _T_382 = and(_T_381, _T_215) node _T_383 = and(_T_382, _T_223) node _T_384 = and(_T_383, _T_231) node _T_385 = and(_T_384, _T_239) node _T_386 = and(_T_385, _T_247) node _T_387 = and(_T_386, _T_255) node _T_388 = and(_T_387, _T_263) node _T_389 = and(_T_388, _T_271) node _T_390 = and(_T_389, _T_279) node _T_391 = and(_T_390, _T_287) node _T_392 = and(_T_391, _T_295) node _T_393 = and(_T_392, _T_303) node _T_394 = and(_T_393, _T_311) node _T_395 = and(_T_394, _T_319) node _T_396 = and(_T_395, _T_327) node _T_397 = and(_T_396, _T_335) node _T_398 = and(_T_397, _T_343) node _T_399 = and(_T_398, _T_351) node _T_400 = and(_T_399, _T_359) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_400, UInt<1>(0h1), "") : assert_1 node _T_404 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_404 : node _T_405 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_406 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_4) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_414 = and(_T_412, _T_413) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_415 = shr(io.in.a.bits.source, 2) node _T_416 = eq(_T_415, UInt<1>(0h1)) node _T_417 = leq(UInt<1>(0h0), uncommonBits_5) node _T_418 = and(_T_416, _T_417) node _T_419 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<2>(0h2)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_6) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<2>(0h3)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_7) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_434 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_441 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_444 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_469 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_470 = or(_T_408, _T_414) node _T_471 = or(_T_470, _T_420) node _T_472 = or(_T_471, _T_426) node _T_473 = or(_T_472, _T_432) node _T_474 = or(_T_473, _T_433) node _T_475 = or(_T_474, _T_434) node _T_476 = or(_T_475, _T_435) node _T_477 = or(_T_476, _T_436) node _T_478 = or(_T_477, _T_437) node _T_479 = or(_T_478, _T_438) node _T_480 = or(_T_479, _T_439) node _T_481 = or(_T_480, _T_440) node _T_482 = or(_T_481, _T_441) node _T_483 = or(_T_482, _T_442) node _T_484 = or(_T_483, _T_443) node _T_485 = or(_T_484, _T_444) node _T_486 = or(_T_485, _T_445) node _T_487 = or(_T_486, _T_446) node _T_488 = or(_T_487, _T_447) node _T_489 = or(_T_488, _T_448) node _T_490 = or(_T_489, _T_449) node _T_491 = or(_T_490, _T_450) node _T_492 = or(_T_491, _T_451) node _T_493 = or(_T_492, _T_452) node _T_494 = or(_T_493, _T_453) node _T_495 = or(_T_494, _T_454) node _T_496 = or(_T_495, _T_455) node _T_497 = or(_T_496, _T_456) node _T_498 = or(_T_497, _T_457) node _T_499 = or(_T_498, _T_458) node _T_500 = or(_T_499, _T_459) node _T_501 = or(_T_500, _T_460) node _T_502 = or(_T_501, _T_461) node _T_503 = or(_T_502, _T_462) node _T_504 = or(_T_503, _T_463) node _T_505 = or(_T_504, _T_464) node _T_506 = or(_T_505, _T_465) node _T_507 = or(_T_506, _T_466) node _T_508 = or(_T_507, _T_467) node _T_509 = or(_T_508, _T_468) node _T_510 = or(_T_509, _T_469) node _T_511 = and(_T_407, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<14>(0h2000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_525 = cvt(_T_524) node _T_526 = and(_T_525, asSInt(UInt<17>(0h10000))) node _T_527 = asSInt(_T_526) node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0))) node _T_529 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<18>(0h2f000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<17>(0h10000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<27>(0h4000000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<13>(0h1000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = or(_T_518, _T_523) node _T_555 = or(_T_554, _T_528) node _T_556 = or(_T_555, _T_533) node _T_557 = or(_T_556, _T_538) node _T_558 = or(_T_557, _T_543) node _T_559 = or(_T_558, _T_548) node _T_560 = or(_T_559, _T_553) node _T_561 = and(_T_513, _T_560) node _T_562 = or(UInt<1>(0h0), _T_561) node _T_563 = and(_T_512, _T_562) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_563, UInt<1>(0h1), "") : assert_2 node _T_567 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_568 = shr(io.in.a.bits.source, 2) node _T_569 = eq(_T_568, UInt<1>(0h0)) node _T_570 = leq(UInt<1>(0h0), uncommonBits_8) node _T_571 = and(_T_569, _T_570) node _T_572 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_573 = and(_T_571, _T_572) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_574 = shr(io.in.a.bits.source, 2) node _T_575 = eq(_T_574, UInt<1>(0h1)) node _T_576 = leq(UInt<1>(0h0), uncommonBits_9) node _T_577 = and(_T_575, _T_576) node _T_578 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_579 = and(_T_577, _T_578) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_580 = shr(io.in.a.bits.source, 2) node _T_581 = eq(_T_580, UInt<2>(0h2)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_10) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<2>(0h3)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_11) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _T_592 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_593 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_594 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_595 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_596 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_597 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_598 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_599 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_600 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_601 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_602 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_603 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_604 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_606 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_607 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_608 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_609 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_610 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_613 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_614 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_615 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_616 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_617 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_618 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_619 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_620 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_621 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_622 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_623 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_624 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_625 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_628 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[42] connect _WIRE[0], _T_567 connect _WIRE[1], _T_573 connect _WIRE[2], _T_579 connect _WIRE[3], _T_585 connect _WIRE[4], _T_591 connect _WIRE[5], _T_592 connect _WIRE[6], _T_593 connect _WIRE[7], _T_594 connect _WIRE[8], _T_595 connect _WIRE[9], _T_596 connect _WIRE[10], _T_597 connect _WIRE[11], _T_598 connect _WIRE[12], _T_599 connect _WIRE[13], _T_600 connect _WIRE[14], _T_601 connect _WIRE[15], _T_602 connect _WIRE[16], _T_603 connect _WIRE[17], _T_604 connect _WIRE[18], _T_605 connect _WIRE[19], _T_606 connect _WIRE[20], _T_607 connect _WIRE[21], _T_608 connect _WIRE[22], _T_609 connect _WIRE[23], _T_610 connect _WIRE[24], _T_611 connect _WIRE[25], _T_612 connect _WIRE[26], _T_613 connect _WIRE[27], _T_614 connect _WIRE[28], _T_615 connect _WIRE[29], _T_616 connect _WIRE[30], _T_617 connect _WIRE[31], _T_618 connect _WIRE[32], _T_619 connect _WIRE[33], _T_620 connect _WIRE[34], _T_621 connect _WIRE[35], _T_622 connect _WIRE[36], _T_623 connect _WIRE[37], _T_624 connect _WIRE[38], _T_625 connect _WIRE[39], _T_626 connect _WIRE[40], _T_627 connect _WIRE[41], _T_628 node _T_629 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_630 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_631 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_632 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_633 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_634 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_635 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_636 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_637 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_638 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_639 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_640 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_641 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_642 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_643 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_644 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_645 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_646 = mux(_WIRE[5], _T_629, UInt<1>(0h0)) node _T_647 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_648 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_649 = mux(_WIRE[8], _T_630, UInt<1>(0h0)) node _T_650 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_651 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_652 = mux(_WIRE[11], _T_631, UInt<1>(0h0)) node _T_653 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_654 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_655 = mux(_WIRE[14], _T_632, UInt<1>(0h0)) node _T_656 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_657 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_658 = mux(_WIRE[17], _T_633, UInt<1>(0h0)) node _T_659 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_660 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_661 = mux(_WIRE[20], _T_634, UInt<1>(0h0)) node _T_662 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_663 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_664 = mux(_WIRE[23], _T_635, UInt<1>(0h0)) node _T_665 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_666 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_667 = mux(_WIRE[26], _T_636, UInt<1>(0h0)) node _T_668 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_669 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_670 = mux(_WIRE[29], _T_637, UInt<1>(0h0)) node _T_671 = mux(_WIRE[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_672 = mux(_WIRE[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_673 = mux(_WIRE[32], _T_638, UInt<1>(0h0)) node _T_674 = mux(_WIRE[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_675 = mux(_WIRE[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_676 = mux(_WIRE[35], _T_639, UInt<1>(0h0)) node _T_677 = mux(_WIRE[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_678 = mux(_WIRE[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_679 = mux(_WIRE[38], _T_640, UInt<1>(0h0)) node _T_680 = mux(_WIRE[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_681 = mux(_WIRE[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_682 = mux(_WIRE[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_683 = or(_T_641, _T_642) node _T_684 = or(_T_683, _T_643) node _T_685 = or(_T_684, _T_644) node _T_686 = or(_T_685, _T_645) node _T_687 = or(_T_686, _T_646) node _T_688 = or(_T_687, _T_647) node _T_689 = or(_T_688, _T_648) node _T_690 = or(_T_689, _T_649) node _T_691 = or(_T_690, _T_650) node _T_692 = or(_T_691, _T_651) node _T_693 = or(_T_692, _T_652) node _T_694 = or(_T_693, _T_653) node _T_695 = or(_T_694, _T_654) node _T_696 = or(_T_695, _T_655) node _T_697 = or(_T_696, _T_656) node _T_698 = or(_T_697, _T_657) node _T_699 = or(_T_698, _T_658) node _T_700 = or(_T_699, _T_659) node _T_701 = or(_T_700, _T_660) node _T_702 = or(_T_701, _T_661) node _T_703 = or(_T_702, _T_662) node _T_704 = or(_T_703, _T_663) node _T_705 = or(_T_704, _T_664) node _T_706 = or(_T_705, _T_665) node _T_707 = or(_T_706, _T_666) node _T_708 = or(_T_707, _T_667) node _T_709 = or(_T_708, _T_668) node _T_710 = or(_T_709, _T_669) node _T_711 = or(_T_710, _T_670) node _T_712 = or(_T_711, _T_671) node _T_713 = or(_T_712, _T_672) node _T_714 = or(_T_713, _T_673) node _T_715 = or(_T_714, _T_674) node _T_716 = or(_T_715, _T_675) node _T_717 = or(_T_716, _T_676) node _T_718 = or(_T_717, _T_677) node _T_719 = or(_T_718, _T_678) node _T_720 = or(_T_719, _T_679) node _T_721 = or(_T_720, _T_680) node _T_722 = or(_T_721, _T_681) node _T_723 = or(_T_722, _T_682) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_723 node _T_724 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_725 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_726 = and(_T_724, _T_725) node _T_727 = or(UInt<1>(0h0), _T_726) node _T_728 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<14>(0h2000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<18>(0h2f000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_749 = cvt(_T_748) node _T_750 = and(_T_749, asSInt(UInt<17>(0h10000))) node _T_751 = asSInt(_T_750) node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0))) node _T_753 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<13>(0h1000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_759 = cvt(_T_758) node _T_760 = and(_T_759, asSInt(UInt<27>(0h4000000))) node _T_761 = asSInt(_T_760) node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0))) node _T_763 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_764 = cvt(_T_763) node _T_765 = and(_T_764, asSInt(UInt<13>(0h1000))) node _T_766 = asSInt(_T_765) node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0))) node _T_768 = or(_T_732, _T_737) node _T_769 = or(_T_768, _T_742) node _T_770 = or(_T_769, _T_747) node _T_771 = or(_T_770, _T_752) node _T_772 = or(_T_771, _T_757) node _T_773 = or(_T_772, _T_762) node _T_774 = or(_T_773, _T_767) node _T_775 = and(_T_727, _T_774) node _T_776 = or(UInt<1>(0h0), _T_775) node _T_777 = and(_WIRE_1, _T_776) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_777, UInt<1>(0h1), "") : assert_3 node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(source_ok, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_784 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(_T_784, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_784, UInt<1>(0h1), "") : assert_5 node _T_788 = asUInt(reset) node _T_789 = eq(_T_788, UInt<1>(0h0)) when _T_789 : node _T_790 = eq(is_aligned, UInt<1>(0h0)) when _T_790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_791 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(_T_791, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_791, UInt<1>(0h1), "") : assert_7 node _T_795 = not(io.in.a.bits.mask) node _T_796 = eq(_T_795, UInt<1>(0h0)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_796, UInt<1>(0h1), "") : assert_8 node _T_800 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_800, UInt<1>(0h1), "") : assert_9 node _T_804 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_809 = shr(io.in.a.bits.source, 2) node _T_810 = eq(_T_809, UInt<1>(0h0)) node _T_811 = leq(UInt<1>(0h0), uncommonBits_12) node _T_812 = and(_T_810, _T_811) node _T_813 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_814 = and(_T_812, _T_813) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_815 = shr(io.in.a.bits.source, 2) node _T_816 = eq(_T_815, UInt<1>(0h1)) node _T_817 = leq(UInt<1>(0h0), uncommonBits_13) node _T_818 = and(_T_816, _T_817) node _T_819 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_820 = and(_T_818, _T_819) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_821 = shr(io.in.a.bits.source, 2) node _T_822 = eq(_T_821, UInt<2>(0h2)) node _T_823 = leq(UInt<1>(0h0), uncommonBits_14) node _T_824 = and(_T_822, _T_823) node _T_825 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_826 = and(_T_824, _T_825) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_827 = shr(io.in.a.bits.source, 2) node _T_828 = eq(_T_827, UInt<2>(0h3)) node _T_829 = leq(UInt<1>(0h0), uncommonBits_15) node _T_830 = and(_T_828, _T_829) node _T_831 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_832 = and(_T_830, _T_831) node _T_833 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_834 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_835 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_836 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_837 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_838 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_839 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_840 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_841 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_842 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_843 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_844 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_847 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_848 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_849 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_850 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_851 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_853 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_854 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_855 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_856 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_857 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_858 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_859 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_860 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_861 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_862 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_863 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_864 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_865 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_866 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_867 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_868 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_869 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_870 = or(_T_808, _T_814) node _T_871 = or(_T_870, _T_820) node _T_872 = or(_T_871, _T_826) node _T_873 = or(_T_872, _T_832) node _T_874 = or(_T_873, _T_833) node _T_875 = or(_T_874, _T_834) node _T_876 = or(_T_875, _T_835) node _T_877 = or(_T_876, _T_836) node _T_878 = or(_T_877, _T_837) node _T_879 = or(_T_878, _T_838) node _T_880 = or(_T_879, _T_839) node _T_881 = or(_T_880, _T_840) node _T_882 = or(_T_881, _T_841) node _T_883 = or(_T_882, _T_842) node _T_884 = or(_T_883, _T_843) node _T_885 = or(_T_884, _T_844) node _T_886 = or(_T_885, _T_845) node _T_887 = or(_T_886, _T_846) node _T_888 = or(_T_887, _T_847) node _T_889 = or(_T_888, _T_848) node _T_890 = or(_T_889, _T_849) node _T_891 = or(_T_890, _T_850) node _T_892 = or(_T_891, _T_851) node _T_893 = or(_T_892, _T_852) node _T_894 = or(_T_893, _T_853) node _T_895 = or(_T_894, _T_854) node _T_896 = or(_T_895, _T_855) node _T_897 = or(_T_896, _T_856) node _T_898 = or(_T_897, _T_857) node _T_899 = or(_T_898, _T_858) node _T_900 = or(_T_899, _T_859) node _T_901 = or(_T_900, _T_860) node _T_902 = or(_T_901, _T_861) node _T_903 = or(_T_902, _T_862) node _T_904 = or(_T_903, _T_863) node _T_905 = or(_T_904, _T_864) node _T_906 = or(_T_905, _T_865) node _T_907 = or(_T_906, _T_866) node _T_908 = or(_T_907, _T_867) node _T_909 = or(_T_908, _T_868) node _T_910 = or(_T_909, _T_869) node _T_911 = and(_T_807, _T_910) node _T_912 = or(UInt<1>(0h0), _T_911) node _T_913 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_914 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<14>(0h2000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<17>(0h10000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<18>(0h2f000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_935 = cvt(_T_934) node _T_936 = and(_T_935, asSInt(UInt<17>(0h10000))) node _T_937 = asSInt(_T_936) node _T_938 = eq(_T_937, asSInt(UInt<1>(0h0))) node _T_939 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_940 = cvt(_T_939) node _T_941 = and(_T_940, asSInt(UInt<13>(0h1000))) node _T_942 = asSInt(_T_941) node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0))) node _T_944 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_945 = cvt(_T_944) node _T_946 = and(_T_945, asSInt(UInt<27>(0h4000000))) node _T_947 = asSInt(_T_946) node _T_948 = eq(_T_947, asSInt(UInt<1>(0h0))) node _T_949 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_950 = cvt(_T_949) node _T_951 = and(_T_950, asSInt(UInt<13>(0h1000))) node _T_952 = asSInt(_T_951) node _T_953 = eq(_T_952, asSInt(UInt<1>(0h0))) node _T_954 = or(_T_918, _T_923) node _T_955 = or(_T_954, _T_928) node _T_956 = or(_T_955, _T_933) node _T_957 = or(_T_956, _T_938) node _T_958 = or(_T_957, _T_943) node _T_959 = or(_T_958, _T_948) node _T_960 = or(_T_959, _T_953) node _T_961 = and(_T_913, _T_960) node _T_962 = or(UInt<1>(0h0), _T_961) node _T_963 = and(_T_912, _T_962) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_963, UInt<1>(0h1), "") : assert_10 node _T_967 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_968 = shr(io.in.a.bits.source, 2) node _T_969 = eq(_T_968, UInt<1>(0h0)) node _T_970 = leq(UInt<1>(0h0), uncommonBits_16) node _T_971 = and(_T_969, _T_970) node _T_972 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_973 = and(_T_971, _T_972) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_974 = shr(io.in.a.bits.source, 2) node _T_975 = eq(_T_974, UInt<1>(0h1)) node _T_976 = leq(UInt<1>(0h0), uncommonBits_17) node _T_977 = and(_T_975, _T_976) node _T_978 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_979 = and(_T_977, _T_978) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_980 = shr(io.in.a.bits.source, 2) node _T_981 = eq(_T_980, UInt<2>(0h2)) node _T_982 = leq(UInt<1>(0h0), uncommonBits_18) node _T_983 = and(_T_981, _T_982) node _T_984 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_985 = and(_T_983, _T_984) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_986 = shr(io.in.a.bits.source, 2) node _T_987 = eq(_T_986, UInt<2>(0h3)) node _T_988 = leq(UInt<1>(0h0), uncommonBits_19) node _T_989 = and(_T_987, _T_988) node _T_990 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_991 = and(_T_989, _T_990) node _T_992 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_993 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_994 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_995 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_996 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_997 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_998 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_999 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1000 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1001 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1002 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1003 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1004 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1005 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1006 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1007 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1008 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1009 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1010 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1011 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1012 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1013 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1014 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1015 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1016 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1017 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1018 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1019 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1020 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1021 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1022 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1023 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1024 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1025 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1026 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1027 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1028 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[42] connect _WIRE_2[0], _T_967 connect _WIRE_2[1], _T_973 connect _WIRE_2[2], _T_979 connect _WIRE_2[3], _T_985 connect _WIRE_2[4], _T_991 connect _WIRE_2[5], _T_992 connect _WIRE_2[6], _T_993 connect _WIRE_2[7], _T_994 connect _WIRE_2[8], _T_995 connect _WIRE_2[9], _T_996 connect _WIRE_2[10], _T_997 connect _WIRE_2[11], _T_998 connect _WIRE_2[12], _T_999 connect _WIRE_2[13], _T_1000 connect _WIRE_2[14], _T_1001 connect _WIRE_2[15], _T_1002 connect _WIRE_2[16], _T_1003 connect _WIRE_2[17], _T_1004 connect _WIRE_2[18], _T_1005 connect _WIRE_2[19], _T_1006 connect _WIRE_2[20], _T_1007 connect _WIRE_2[21], _T_1008 connect _WIRE_2[22], _T_1009 connect _WIRE_2[23], _T_1010 connect _WIRE_2[24], _T_1011 connect _WIRE_2[25], _T_1012 connect _WIRE_2[26], _T_1013 connect _WIRE_2[27], _T_1014 connect _WIRE_2[28], _T_1015 connect _WIRE_2[29], _T_1016 connect _WIRE_2[30], _T_1017 connect _WIRE_2[31], _T_1018 connect _WIRE_2[32], _T_1019 connect _WIRE_2[33], _T_1020 connect _WIRE_2[34], _T_1021 connect _WIRE_2[35], _T_1022 connect _WIRE_2[36], _T_1023 connect _WIRE_2[37], _T_1024 connect _WIRE_2[38], _T_1025 connect _WIRE_2[39], _T_1026 connect _WIRE_2[40], _T_1027 connect _WIRE_2[41], _T_1028 node _T_1029 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1030 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1031 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1032 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1033 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1034 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1035 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1036 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1037 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1038 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1039 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1040 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1041 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1042 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1043 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1044 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1045 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1046 = mux(_WIRE_2[5], _T_1029, UInt<1>(0h0)) node _T_1047 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1048 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1049 = mux(_WIRE_2[8], _T_1030, UInt<1>(0h0)) node _T_1050 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_1051 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1052 = mux(_WIRE_2[11], _T_1031, UInt<1>(0h0)) node _T_1053 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1054 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_1055 = mux(_WIRE_2[14], _T_1032, UInt<1>(0h0)) node _T_1056 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_1057 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_1058 = mux(_WIRE_2[17], _T_1033, UInt<1>(0h0)) node _T_1059 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_1060 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_1061 = mux(_WIRE_2[20], _T_1034, UInt<1>(0h0)) node _T_1062 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_1063 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_1064 = mux(_WIRE_2[23], _T_1035, UInt<1>(0h0)) node _T_1065 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_1066 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_1067 = mux(_WIRE_2[26], _T_1036, UInt<1>(0h0)) node _T_1068 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_1069 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_1070 = mux(_WIRE_2[29], _T_1037, UInt<1>(0h0)) node _T_1071 = mux(_WIRE_2[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_1072 = mux(_WIRE_2[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_1073 = mux(_WIRE_2[32], _T_1038, UInt<1>(0h0)) node _T_1074 = mux(_WIRE_2[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_1075 = mux(_WIRE_2[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_1076 = mux(_WIRE_2[35], _T_1039, UInt<1>(0h0)) node _T_1077 = mux(_WIRE_2[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_1078 = mux(_WIRE_2[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_1079 = mux(_WIRE_2[38], _T_1040, UInt<1>(0h0)) node _T_1080 = mux(_WIRE_2[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_1081 = mux(_WIRE_2[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_1082 = mux(_WIRE_2[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_1083 = or(_T_1041, _T_1042) node _T_1084 = or(_T_1083, _T_1043) node _T_1085 = or(_T_1084, _T_1044) node _T_1086 = or(_T_1085, _T_1045) node _T_1087 = or(_T_1086, _T_1046) node _T_1088 = or(_T_1087, _T_1047) node _T_1089 = or(_T_1088, _T_1048) node _T_1090 = or(_T_1089, _T_1049) node _T_1091 = or(_T_1090, _T_1050) node _T_1092 = or(_T_1091, _T_1051) node _T_1093 = or(_T_1092, _T_1052) node _T_1094 = or(_T_1093, _T_1053) node _T_1095 = or(_T_1094, _T_1054) node _T_1096 = or(_T_1095, _T_1055) node _T_1097 = or(_T_1096, _T_1056) node _T_1098 = or(_T_1097, _T_1057) node _T_1099 = or(_T_1098, _T_1058) node _T_1100 = or(_T_1099, _T_1059) node _T_1101 = or(_T_1100, _T_1060) node _T_1102 = or(_T_1101, _T_1061) node _T_1103 = or(_T_1102, _T_1062) node _T_1104 = or(_T_1103, _T_1063) node _T_1105 = or(_T_1104, _T_1064) node _T_1106 = or(_T_1105, _T_1065) node _T_1107 = or(_T_1106, _T_1066) node _T_1108 = or(_T_1107, _T_1067) node _T_1109 = or(_T_1108, _T_1068) node _T_1110 = or(_T_1109, _T_1069) node _T_1111 = or(_T_1110, _T_1070) node _T_1112 = or(_T_1111, _T_1071) node _T_1113 = or(_T_1112, _T_1072) node _T_1114 = or(_T_1113, _T_1073) node _T_1115 = or(_T_1114, _T_1074) node _T_1116 = or(_T_1115, _T_1075) node _T_1117 = or(_T_1116, _T_1076) node _T_1118 = or(_T_1117, _T_1077) node _T_1119 = or(_T_1118, _T_1078) node _T_1120 = or(_T_1119, _T_1079) node _T_1121 = or(_T_1120, _T_1080) node _T_1122 = or(_T_1121, _T_1081) node _T_1123 = or(_T_1122, _T_1082) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_1123 node _T_1124 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1125 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1126 = and(_T_1124, _T_1125) node _T_1127 = or(UInt<1>(0h0), _T_1126) node _T_1128 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1129 = cvt(_T_1128) node _T_1130 = and(_T_1129, asSInt(UInt<14>(0h2000))) node _T_1131 = asSInt(_T_1130) node _T_1132 = eq(_T_1131, asSInt(UInt<1>(0h0))) node _T_1133 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1134 = cvt(_T_1133) node _T_1135 = and(_T_1134, asSInt(UInt<13>(0h1000))) node _T_1136 = asSInt(_T_1135) node _T_1137 = eq(_T_1136, asSInt(UInt<1>(0h0))) node _T_1138 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1139 = cvt(_T_1138) node _T_1140 = and(_T_1139, asSInt(UInt<17>(0h10000))) node _T_1141 = asSInt(_T_1140) node _T_1142 = eq(_T_1141, asSInt(UInt<1>(0h0))) node _T_1143 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1144 = cvt(_T_1143) node _T_1145 = and(_T_1144, asSInt(UInt<18>(0h2f000))) node _T_1146 = asSInt(_T_1145) node _T_1147 = eq(_T_1146, asSInt(UInt<1>(0h0))) node _T_1148 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1149 = cvt(_T_1148) node _T_1150 = and(_T_1149, asSInt(UInt<17>(0h10000))) node _T_1151 = asSInt(_T_1150) node _T_1152 = eq(_T_1151, asSInt(UInt<1>(0h0))) node _T_1153 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1154 = cvt(_T_1153) node _T_1155 = and(_T_1154, asSInt(UInt<13>(0h1000))) node _T_1156 = asSInt(_T_1155) node _T_1157 = eq(_T_1156, asSInt(UInt<1>(0h0))) node _T_1158 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1159 = cvt(_T_1158) node _T_1160 = and(_T_1159, asSInt(UInt<27>(0h4000000))) node _T_1161 = asSInt(_T_1160) node _T_1162 = eq(_T_1161, asSInt(UInt<1>(0h0))) node _T_1163 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1164 = cvt(_T_1163) node _T_1165 = and(_T_1164, asSInt(UInt<13>(0h1000))) node _T_1166 = asSInt(_T_1165) node _T_1167 = eq(_T_1166, asSInt(UInt<1>(0h0))) node _T_1168 = or(_T_1132, _T_1137) node _T_1169 = or(_T_1168, _T_1142) node _T_1170 = or(_T_1169, _T_1147) node _T_1171 = or(_T_1170, _T_1152) node _T_1172 = or(_T_1171, _T_1157) node _T_1173 = or(_T_1172, _T_1162) node _T_1174 = or(_T_1173, _T_1167) node _T_1175 = and(_T_1127, _T_1174) node _T_1176 = or(UInt<1>(0h0), _T_1175) node _T_1177 = and(_WIRE_3, _T_1176) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_11 node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(source_ok, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1184 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_13 node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(is_aligned, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1191 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(_T_1191, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1191, UInt<1>(0h1), "") : assert_15 node _T_1195 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(_T_1195, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1195, UInt<1>(0h1), "") : assert_16 node _T_1199 = not(io.in.a.bits.mask) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) node _T_1201 = asUInt(reset) node _T_1202 = eq(_T_1201, UInt<1>(0h0)) when _T_1202 : node _T_1203 = eq(_T_1200, UInt<1>(0h0)) when _T_1203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1200, UInt<1>(0h1), "") : assert_17 node _T_1204 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(_T_1204, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1204, UInt<1>(0h1), "") : assert_18 node _T_1208 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1208 : node _T_1209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1211 = and(_T_1209, _T_1210) node _T_1212 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_1213 = shr(io.in.a.bits.source, 2) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = leq(UInt<1>(0h0), uncommonBits_20) node _T_1216 = and(_T_1214, _T_1215) node _T_1217 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_1218 = and(_T_1216, _T_1217) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_1219 = shr(io.in.a.bits.source, 2) node _T_1220 = eq(_T_1219, UInt<1>(0h1)) node _T_1221 = leq(UInt<1>(0h0), uncommonBits_21) node _T_1222 = and(_T_1220, _T_1221) node _T_1223 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_1224 = and(_T_1222, _T_1223) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_1225 = shr(io.in.a.bits.source, 2) node _T_1226 = eq(_T_1225, UInt<2>(0h2)) node _T_1227 = leq(UInt<1>(0h0), uncommonBits_22) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_1230 = and(_T_1228, _T_1229) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_1231 = shr(io.in.a.bits.source, 2) node _T_1232 = eq(_T_1231, UInt<2>(0h3)) node _T_1233 = leq(UInt<1>(0h0), uncommonBits_23) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1236 = and(_T_1234, _T_1235) node _T_1237 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1238 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1239 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1240 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1241 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1242 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1243 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1244 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1245 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1246 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1247 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1248 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1249 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1250 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1251 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1252 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1253 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1254 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1255 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1256 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1257 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1258 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1259 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1260 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1261 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1262 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1263 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1264 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1265 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1266 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1267 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1268 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1269 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1270 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1271 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1272 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1273 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1274 = or(_T_1212, _T_1218) node _T_1275 = or(_T_1274, _T_1224) node _T_1276 = or(_T_1275, _T_1230) node _T_1277 = or(_T_1276, _T_1236) node _T_1278 = or(_T_1277, _T_1237) node _T_1279 = or(_T_1278, _T_1238) node _T_1280 = or(_T_1279, _T_1239) node _T_1281 = or(_T_1280, _T_1240) node _T_1282 = or(_T_1281, _T_1241) node _T_1283 = or(_T_1282, _T_1242) node _T_1284 = or(_T_1283, _T_1243) node _T_1285 = or(_T_1284, _T_1244) node _T_1286 = or(_T_1285, _T_1245) node _T_1287 = or(_T_1286, _T_1246) node _T_1288 = or(_T_1287, _T_1247) node _T_1289 = or(_T_1288, _T_1248) node _T_1290 = or(_T_1289, _T_1249) node _T_1291 = or(_T_1290, _T_1250) node _T_1292 = or(_T_1291, _T_1251) node _T_1293 = or(_T_1292, _T_1252) node _T_1294 = or(_T_1293, _T_1253) node _T_1295 = or(_T_1294, _T_1254) node _T_1296 = or(_T_1295, _T_1255) node _T_1297 = or(_T_1296, _T_1256) node _T_1298 = or(_T_1297, _T_1257) node _T_1299 = or(_T_1298, _T_1258) node _T_1300 = or(_T_1299, _T_1259) node _T_1301 = or(_T_1300, _T_1260) node _T_1302 = or(_T_1301, _T_1261) node _T_1303 = or(_T_1302, _T_1262) node _T_1304 = or(_T_1303, _T_1263) node _T_1305 = or(_T_1304, _T_1264) node _T_1306 = or(_T_1305, _T_1265) node _T_1307 = or(_T_1306, _T_1266) node _T_1308 = or(_T_1307, _T_1267) node _T_1309 = or(_T_1308, _T_1268) node _T_1310 = or(_T_1309, _T_1269) node _T_1311 = or(_T_1310, _T_1270) node _T_1312 = or(_T_1311, _T_1271) node _T_1313 = or(_T_1312, _T_1272) node _T_1314 = or(_T_1313, _T_1273) node _T_1315 = and(_T_1211, _T_1314) node _T_1316 = or(UInt<1>(0h0), _T_1315) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_19 node _T_1320 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1321 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1322 = and(_T_1320, _T_1321) node _T_1323 = or(UInt<1>(0h0), _T_1322) node _T_1324 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1325 = cvt(_T_1324) node _T_1326 = and(_T_1325, asSInt(UInt<13>(0h1000))) node _T_1327 = asSInt(_T_1326) node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0))) node _T_1329 = and(_T_1323, _T_1328) node _T_1330 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1331 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1332 = and(_T_1330, _T_1331) node _T_1333 = or(UInt<1>(0h0), _T_1332) node _T_1334 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1335 = cvt(_T_1334) node _T_1336 = and(_T_1335, asSInt(UInt<14>(0h2000))) node _T_1337 = asSInt(_T_1336) node _T_1338 = eq(_T_1337, asSInt(UInt<1>(0h0))) node _T_1339 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1340 = cvt(_T_1339) node _T_1341 = and(_T_1340, asSInt(UInt<17>(0h10000))) node _T_1342 = asSInt(_T_1341) node _T_1343 = eq(_T_1342, asSInt(UInt<1>(0h0))) node _T_1344 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1345 = cvt(_T_1344) node _T_1346 = and(_T_1345, asSInt(UInt<18>(0h2f000))) node _T_1347 = asSInt(_T_1346) node _T_1348 = eq(_T_1347, asSInt(UInt<1>(0h0))) node _T_1349 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1350 = cvt(_T_1349) node _T_1351 = and(_T_1350, asSInt(UInt<17>(0h10000))) node _T_1352 = asSInt(_T_1351) node _T_1353 = eq(_T_1352, asSInt(UInt<1>(0h0))) node _T_1354 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1355 = cvt(_T_1354) node _T_1356 = and(_T_1355, asSInt(UInt<13>(0h1000))) node _T_1357 = asSInt(_T_1356) node _T_1358 = eq(_T_1357, asSInt(UInt<1>(0h0))) node _T_1359 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1360 = cvt(_T_1359) node _T_1361 = and(_T_1360, asSInt(UInt<27>(0h4000000))) node _T_1362 = asSInt(_T_1361) node _T_1363 = eq(_T_1362, asSInt(UInt<1>(0h0))) node _T_1364 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1365 = cvt(_T_1364) node _T_1366 = and(_T_1365, asSInt(UInt<13>(0h1000))) node _T_1367 = asSInt(_T_1366) node _T_1368 = eq(_T_1367, asSInt(UInt<1>(0h0))) node _T_1369 = or(_T_1338, _T_1343) node _T_1370 = or(_T_1369, _T_1348) node _T_1371 = or(_T_1370, _T_1353) node _T_1372 = or(_T_1371, _T_1358) node _T_1373 = or(_T_1372, _T_1363) node _T_1374 = or(_T_1373, _T_1368) node _T_1375 = and(_T_1333, _T_1374) node _T_1376 = or(UInt<1>(0h0), _T_1329) node _T_1377 = or(_T_1376, _T_1375) node _T_1378 = asUInt(reset) node _T_1379 = eq(_T_1378, UInt<1>(0h0)) when _T_1379 : node _T_1380 = eq(_T_1377, UInt<1>(0h0)) when _T_1380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1377, UInt<1>(0h1), "") : assert_20 node _T_1381 = asUInt(reset) node _T_1382 = eq(_T_1381, UInt<1>(0h0)) when _T_1382 : node _T_1383 = eq(source_ok, UInt<1>(0h0)) when _T_1383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(is_aligned, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1387 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1388 = asUInt(reset) node _T_1389 = eq(_T_1388, UInt<1>(0h0)) when _T_1389 : node _T_1390 = eq(_T_1387, UInt<1>(0h0)) when _T_1390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1387, UInt<1>(0h1), "") : assert_23 node _T_1391 = eq(io.in.a.bits.mask, mask) node _T_1392 = asUInt(reset) node _T_1393 = eq(_T_1392, UInt<1>(0h0)) when _T_1393 : node _T_1394 = eq(_T_1391, UInt<1>(0h0)) when _T_1394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1391, UInt<1>(0h1), "") : assert_24 node _T_1395 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1396 = asUInt(reset) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(_T_1395, UInt<1>(0h0)) when _T_1398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1395, UInt<1>(0h1), "") : assert_25 node _T_1399 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1399 : node _T_1400 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1401 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1402 = and(_T_1400, _T_1401) node _T_1403 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1404 = shr(io.in.a.bits.source, 2) node _T_1405 = eq(_T_1404, UInt<1>(0h0)) node _T_1406 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1407 = and(_T_1405, _T_1406) node _T_1408 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1409 = and(_T_1407, _T_1408) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1410 = shr(io.in.a.bits.source, 2) node _T_1411 = eq(_T_1410, UInt<1>(0h1)) node _T_1412 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1413 = and(_T_1411, _T_1412) node _T_1414 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1415 = and(_T_1413, _T_1414) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1416 = shr(io.in.a.bits.source, 2) node _T_1417 = eq(_T_1416, UInt<2>(0h2)) node _T_1418 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1419 = and(_T_1417, _T_1418) node _T_1420 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1421 = and(_T_1419, _T_1420) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1422 = shr(io.in.a.bits.source, 2) node _T_1423 = eq(_T_1422, UInt<2>(0h3)) node _T_1424 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1425 = and(_T_1423, _T_1424) node _T_1426 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1427 = and(_T_1425, _T_1426) node _T_1428 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1429 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1430 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1431 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1432 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1433 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1434 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1435 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1436 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1437 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1438 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1439 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1440 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1441 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1442 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1443 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1444 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1445 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1446 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1447 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1448 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1449 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1450 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1451 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1452 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1453 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1454 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1455 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1456 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1457 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1458 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1459 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1460 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1461 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1462 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1463 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1464 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1465 = or(_T_1403, _T_1409) node _T_1466 = or(_T_1465, _T_1415) node _T_1467 = or(_T_1466, _T_1421) node _T_1468 = or(_T_1467, _T_1427) node _T_1469 = or(_T_1468, _T_1428) node _T_1470 = or(_T_1469, _T_1429) node _T_1471 = or(_T_1470, _T_1430) node _T_1472 = or(_T_1471, _T_1431) node _T_1473 = or(_T_1472, _T_1432) node _T_1474 = or(_T_1473, _T_1433) node _T_1475 = or(_T_1474, _T_1434) node _T_1476 = or(_T_1475, _T_1435) node _T_1477 = or(_T_1476, _T_1436) node _T_1478 = or(_T_1477, _T_1437) node _T_1479 = or(_T_1478, _T_1438) node _T_1480 = or(_T_1479, _T_1439) node _T_1481 = or(_T_1480, _T_1440) node _T_1482 = or(_T_1481, _T_1441) node _T_1483 = or(_T_1482, _T_1442) node _T_1484 = or(_T_1483, _T_1443) node _T_1485 = or(_T_1484, _T_1444) node _T_1486 = or(_T_1485, _T_1445) node _T_1487 = or(_T_1486, _T_1446) node _T_1488 = or(_T_1487, _T_1447) node _T_1489 = or(_T_1488, _T_1448) node _T_1490 = or(_T_1489, _T_1449) node _T_1491 = or(_T_1490, _T_1450) node _T_1492 = or(_T_1491, _T_1451) node _T_1493 = or(_T_1492, _T_1452) node _T_1494 = or(_T_1493, _T_1453) node _T_1495 = or(_T_1494, _T_1454) node _T_1496 = or(_T_1495, _T_1455) node _T_1497 = or(_T_1496, _T_1456) node _T_1498 = or(_T_1497, _T_1457) node _T_1499 = or(_T_1498, _T_1458) node _T_1500 = or(_T_1499, _T_1459) node _T_1501 = or(_T_1500, _T_1460) node _T_1502 = or(_T_1501, _T_1461) node _T_1503 = or(_T_1502, _T_1462) node _T_1504 = or(_T_1503, _T_1463) node _T_1505 = or(_T_1504, _T_1464) node _T_1506 = and(_T_1402, _T_1505) node _T_1507 = or(UInt<1>(0h0), _T_1506) node _T_1508 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1509 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1510 = and(_T_1508, _T_1509) node _T_1511 = or(UInt<1>(0h0), _T_1510) node _T_1512 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1513 = cvt(_T_1512) node _T_1514 = and(_T_1513, asSInt(UInt<13>(0h1000))) node _T_1515 = asSInt(_T_1514) node _T_1516 = eq(_T_1515, asSInt(UInt<1>(0h0))) node _T_1517 = and(_T_1511, _T_1516) node _T_1518 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1519 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1520 = and(_T_1518, _T_1519) node _T_1521 = or(UInt<1>(0h0), _T_1520) node _T_1522 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1523 = cvt(_T_1522) node _T_1524 = and(_T_1523, asSInt(UInt<14>(0h2000))) node _T_1525 = asSInt(_T_1524) node _T_1526 = eq(_T_1525, asSInt(UInt<1>(0h0))) node _T_1527 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1528 = cvt(_T_1527) node _T_1529 = and(_T_1528, asSInt(UInt<18>(0h2f000))) node _T_1530 = asSInt(_T_1529) node _T_1531 = eq(_T_1530, asSInt(UInt<1>(0h0))) node _T_1532 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1533 = cvt(_T_1532) node _T_1534 = and(_T_1533, asSInt(UInt<17>(0h10000))) node _T_1535 = asSInt(_T_1534) node _T_1536 = eq(_T_1535, asSInt(UInt<1>(0h0))) node _T_1537 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1538 = cvt(_T_1537) node _T_1539 = and(_T_1538, asSInt(UInt<13>(0h1000))) node _T_1540 = asSInt(_T_1539) node _T_1541 = eq(_T_1540, asSInt(UInt<1>(0h0))) node _T_1542 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1543 = cvt(_T_1542) node _T_1544 = and(_T_1543, asSInt(UInt<27>(0h4000000))) node _T_1545 = asSInt(_T_1544) node _T_1546 = eq(_T_1545, asSInt(UInt<1>(0h0))) node _T_1547 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1548 = cvt(_T_1547) node _T_1549 = and(_T_1548, asSInt(UInt<13>(0h1000))) node _T_1550 = asSInt(_T_1549) node _T_1551 = eq(_T_1550, asSInt(UInt<1>(0h0))) node _T_1552 = or(_T_1526, _T_1531) node _T_1553 = or(_T_1552, _T_1536) node _T_1554 = or(_T_1553, _T_1541) node _T_1555 = or(_T_1554, _T_1546) node _T_1556 = or(_T_1555, _T_1551) node _T_1557 = and(_T_1521, _T_1556) node _T_1558 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1559 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1560 = cvt(_T_1559) node _T_1561 = and(_T_1560, asSInt(UInt<17>(0h10000))) node _T_1562 = asSInt(_T_1561) node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0))) node _T_1564 = and(_T_1558, _T_1563) node _T_1565 = or(UInt<1>(0h0), _T_1517) node _T_1566 = or(_T_1565, _T_1557) node _T_1567 = or(_T_1566, _T_1564) node _T_1568 = and(_T_1507, _T_1567) node _T_1569 = asUInt(reset) node _T_1570 = eq(_T_1569, UInt<1>(0h0)) when _T_1570 : node _T_1571 = eq(_T_1568, UInt<1>(0h0)) when _T_1571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1568, UInt<1>(0h1), "") : assert_26 node _T_1572 = asUInt(reset) node _T_1573 = eq(_T_1572, UInt<1>(0h0)) when _T_1573 : node _T_1574 = eq(source_ok, UInt<1>(0h0)) when _T_1574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1575 = asUInt(reset) node _T_1576 = eq(_T_1575, UInt<1>(0h0)) when _T_1576 : node _T_1577 = eq(is_aligned, UInt<1>(0h0)) when _T_1577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1578 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1579 = asUInt(reset) node _T_1580 = eq(_T_1579, UInt<1>(0h0)) when _T_1580 : node _T_1581 = eq(_T_1578, UInt<1>(0h0)) when _T_1581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1578, UInt<1>(0h1), "") : assert_29 node _T_1582 = eq(io.in.a.bits.mask, mask) node _T_1583 = asUInt(reset) node _T_1584 = eq(_T_1583, UInt<1>(0h0)) when _T_1584 : node _T_1585 = eq(_T_1582, UInt<1>(0h0)) when _T_1585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1582, UInt<1>(0h1), "") : assert_30 node _T_1586 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1586 : node _T_1587 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1588 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1589 = and(_T_1587, _T_1588) node _T_1590 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1591 = shr(io.in.a.bits.source, 2) node _T_1592 = eq(_T_1591, UInt<1>(0h0)) node _T_1593 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1594 = and(_T_1592, _T_1593) node _T_1595 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1596 = and(_T_1594, _T_1595) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1597 = shr(io.in.a.bits.source, 2) node _T_1598 = eq(_T_1597, UInt<1>(0h1)) node _T_1599 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1600 = and(_T_1598, _T_1599) node _T_1601 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1602 = and(_T_1600, _T_1601) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1603 = shr(io.in.a.bits.source, 2) node _T_1604 = eq(_T_1603, UInt<2>(0h2)) node _T_1605 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1606 = and(_T_1604, _T_1605) node _T_1607 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1608 = and(_T_1606, _T_1607) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1609 = shr(io.in.a.bits.source, 2) node _T_1610 = eq(_T_1609, UInt<2>(0h3)) node _T_1611 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1612 = and(_T_1610, _T_1611) node _T_1613 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1614 = and(_T_1612, _T_1613) node _T_1615 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1616 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1617 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1618 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1619 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1620 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1621 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1622 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1623 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1624 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1625 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1626 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1627 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1628 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1629 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1630 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1631 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1632 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1633 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1634 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1635 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1636 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1637 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1638 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1639 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1640 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1641 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1642 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1643 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1644 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1645 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1646 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1647 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1648 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1649 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1650 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1651 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1652 = or(_T_1590, _T_1596) node _T_1653 = or(_T_1652, _T_1602) node _T_1654 = or(_T_1653, _T_1608) node _T_1655 = or(_T_1654, _T_1614) node _T_1656 = or(_T_1655, _T_1615) node _T_1657 = or(_T_1656, _T_1616) node _T_1658 = or(_T_1657, _T_1617) node _T_1659 = or(_T_1658, _T_1618) node _T_1660 = or(_T_1659, _T_1619) node _T_1661 = or(_T_1660, _T_1620) node _T_1662 = or(_T_1661, _T_1621) node _T_1663 = or(_T_1662, _T_1622) node _T_1664 = or(_T_1663, _T_1623) node _T_1665 = or(_T_1664, _T_1624) node _T_1666 = or(_T_1665, _T_1625) node _T_1667 = or(_T_1666, _T_1626) node _T_1668 = or(_T_1667, _T_1627) node _T_1669 = or(_T_1668, _T_1628) node _T_1670 = or(_T_1669, _T_1629) node _T_1671 = or(_T_1670, _T_1630) node _T_1672 = or(_T_1671, _T_1631) node _T_1673 = or(_T_1672, _T_1632) node _T_1674 = or(_T_1673, _T_1633) node _T_1675 = or(_T_1674, _T_1634) node _T_1676 = or(_T_1675, _T_1635) node _T_1677 = or(_T_1676, _T_1636) node _T_1678 = or(_T_1677, _T_1637) node _T_1679 = or(_T_1678, _T_1638) node _T_1680 = or(_T_1679, _T_1639) node _T_1681 = or(_T_1680, _T_1640) node _T_1682 = or(_T_1681, _T_1641) node _T_1683 = or(_T_1682, _T_1642) node _T_1684 = or(_T_1683, _T_1643) node _T_1685 = or(_T_1684, _T_1644) node _T_1686 = or(_T_1685, _T_1645) node _T_1687 = or(_T_1686, _T_1646) node _T_1688 = or(_T_1687, _T_1647) node _T_1689 = or(_T_1688, _T_1648) node _T_1690 = or(_T_1689, _T_1649) node _T_1691 = or(_T_1690, _T_1650) node _T_1692 = or(_T_1691, _T_1651) node _T_1693 = and(_T_1589, _T_1692) node _T_1694 = or(UInt<1>(0h0), _T_1693) node _T_1695 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1696 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1697 = and(_T_1695, _T_1696) node _T_1698 = or(UInt<1>(0h0), _T_1697) node _T_1699 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1700 = cvt(_T_1699) node _T_1701 = and(_T_1700, asSInt(UInt<13>(0h1000))) node _T_1702 = asSInt(_T_1701) node _T_1703 = eq(_T_1702, asSInt(UInt<1>(0h0))) node _T_1704 = and(_T_1698, _T_1703) node _T_1705 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1706 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1707 = and(_T_1705, _T_1706) node _T_1708 = or(UInt<1>(0h0), _T_1707) node _T_1709 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1710 = cvt(_T_1709) node _T_1711 = and(_T_1710, asSInt(UInt<14>(0h2000))) node _T_1712 = asSInt(_T_1711) node _T_1713 = eq(_T_1712, asSInt(UInt<1>(0h0))) node _T_1714 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1715 = cvt(_T_1714) node _T_1716 = and(_T_1715, asSInt(UInt<18>(0h2f000))) node _T_1717 = asSInt(_T_1716) node _T_1718 = eq(_T_1717, asSInt(UInt<1>(0h0))) node _T_1719 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1720 = cvt(_T_1719) node _T_1721 = and(_T_1720, asSInt(UInt<17>(0h10000))) node _T_1722 = asSInt(_T_1721) node _T_1723 = eq(_T_1722, asSInt(UInt<1>(0h0))) node _T_1724 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1725 = cvt(_T_1724) node _T_1726 = and(_T_1725, asSInt(UInt<13>(0h1000))) node _T_1727 = asSInt(_T_1726) node _T_1728 = eq(_T_1727, asSInt(UInt<1>(0h0))) node _T_1729 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1730 = cvt(_T_1729) node _T_1731 = and(_T_1730, asSInt(UInt<27>(0h4000000))) node _T_1732 = asSInt(_T_1731) node _T_1733 = eq(_T_1732, asSInt(UInt<1>(0h0))) node _T_1734 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1735 = cvt(_T_1734) node _T_1736 = and(_T_1735, asSInt(UInt<13>(0h1000))) node _T_1737 = asSInt(_T_1736) node _T_1738 = eq(_T_1737, asSInt(UInt<1>(0h0))) node _T_1739 = or(_T_1713, _T_1718) node _T_1740 = or(_T_1739, _T_1723) node _T_1741 = or(_T_1740, _T_1728) node _T_1742 = or(_T_1741, _T_1733) node _T_1743 = or(_T_1742, _T_1738) node _T_1744 = and(_T_1708, _T_1743) node _T_1745 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1746 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1747 = cvt(_T_1746) node _T_1748 = and(_T_1747, asSInt(UInt<17>(0h10000))) node _T_1749 = asSInt(_T_1748) node _T_1750 = eq(_T_1749, asSInt(UInt<1>(0h0))) node _T_1751 = and(_T_1745, _T_1750) node _T_1752 = or(UInt<1>(0h0), _T_1704) node _T_1753 = or(_T_1752, _T_1744) node _T_1754 = or(_T_1753, _T_1751) node _T_1755 = and(_T_1694, _T_1754) node _T_1756 = asUInt(reset) node _T_1757 = eq(_T_1756, UInt<1>(0h0)) when _T_1757 : node _T_1758 = eq(_T_1755, UInt<1>(0h0)) when _T_1758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1755, UInt<1>(0h1), "") : assert_31 node _T_1759 = asUInt(reset) node _T_1760 = eq(_T_1759, UInt<1>(0h0)) when _T_1760 : node _T_1761 = eq(source_ok, UInt<1>(0h0)) when _T_1761 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1762 = asUInt(reset) node _T_1763 = eq(_T_1762, UInt<1>(0h0)) when _T_1763 : node _T_1764 = eq(is_aligned, UInt<1>(0h0)) when _T_1764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1765 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(_T_1765, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1765, UInt<1>(0h1), "") : assert_34 node _T_1769 = not(mask) node _T_1770 = and(io.in.a.bits.mask, _T_1769) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(_T_1771, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1771, UInt<1>(0h1), "") : assert_35 node _T_1775 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1775 : node _T_1776 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1777 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1778 = and(_T_1776, _T_1777) node _T_1779 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1780 = shr(io.in.a.bits.source, 2) node _T_1781 = eq(_T_1780, UInt<1>(0h0)) node _T_1782 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1783 = and(_T_1781, _T_1782) node _T_1784 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1785 = and(_T_1783, _T_1784) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1786 = shr(io.in.a.bits.source, 2) node _T_1787 = eq(_T_1786, UInt<1>(0h1)) node _T_1788 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1789 = and(_T_1787, _T_1788) node _T_1790 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1791 = and(_T_1789, _T_1790) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1792 = shr(io.in.a.bits.source, 2) node _T_1793 = eq(_T_1792, UInt<2>(0h2)) node _T_1794 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1795 = and(_T_1793, _T_1794) node _T_1796 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1797 = and(_T_1795, _T_1796) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1798 = shr(io.in.a.bits.source, 2) node _T_1799 = eq(_T_1798, UInt<2>(0h3)) node _T_1800 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1801 = and(_T_1799, _T_1800) node _T_1802 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1803 = and(_T_1801, _T_1802) node _T_1804 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1805 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1806 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1807 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1808 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1809 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1810 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1811 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1812 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1813 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1814 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1815 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1816 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1817 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1818 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1819 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1820 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1821 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1822 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1823 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1824 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1825 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1826 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1827 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1828 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1829 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1830 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1831 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1832 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1833 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1834 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1835 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1836 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1837 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1838 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1839 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1840 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1841 = or(_T_1779, _T_1785) node _T_1842 = or(_T_1841, _T_1791) node _T_1843 = or(_T_1842, _T_1797) node _T_1844 = or(_T_1843, _T_1803) node _T_1845 = or(_T_1844, _T_1804) node _T_1846 = or(_T_1845, _T_1805) node _T_1847 = or(_T_1846, _T_1806) node _T_1848 = or(_T_1847, _T_1807) node _T_1849 = or(_T_1848, _T_1808) node _T_1850 = or(_T_1849, _T_1809) node _T_1851 = or(_T_1850, _T_1810) node _T_1852 = or(_T_1851, _T_1811) node _T_1853 = or(_T_1852, _T_1812) node _T_1854 = or(_T_1853, _T_1813) node _T_1855 = or(_T_1854, _T_1814) node _T_1856 = or(_T_1855, _T_1815) node _T_1857 = or(_T_1856, _T_1816) node _T_1858 = or(_T_1857, _T_1817) node _T_1859 = or(_T_1858, _T_1818) node _T_1860 = or(_T_1859, _T_1819) node _T_1861 = or(_T_1860, _T_1820) node _T_1862 = or(_T_1861, _T_1821) node _T_1863 = or(_T_1862, _T_1822) node _T_1864 = or(_T_1863, _T_1823) node _T_1865 = or(_T_1864, _T_1824) node _T_1866 = or(_T_1865, _T_1825) node _T_1867 = or(_T_1866, _T_1826) node _T_1868 = or(_T_1867, _T_1827) node _T_1869 = or(_T_1868, _T_1828) node _T_1870 = or(_T_1869, _T_1829) node _T_1871 = or(_T_1870, _T_1830) node _T_1872 = or(_T_1871, _T_1831) node _T_1873 = or(_T_1872, _T_1832) node _T_1874 = or(_T_1873, _T_1833) node _T_1875 = or(_T_1874, _T_1834) node _T_1876 = or(_T_1875, _T_1835) node _T_1877 = or(_T_1876, _T_1836) node _T_1878 = or(_T_1877, _T_1837) node _T_1879 = or(_T_1878, _T_1838) node _T_1880 = or(_T_1879, _T_1839) node _T_1881 = or(_T_1880, _T_1840) node _T_1882 = and(_T_1778, _T_1881) node _T_1883 = or(UInt<1>(0h0), _T_1882) node _T_1884 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1885 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1886 = and(_T_1884, _T_1885) node _T_1887 = or(UInt<1>(0h0), _T_1886) node _T_1888 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1889 = cvt(_T_1888) node _T_1890 = and(_T_1889, asSInt(UInt<14>(0h2000))) node _T_1891 = asSInt(_T_1890) node _T_1892 = eq(_T_1891, asSInt(UInt<1>(0h0))) node _T_1893 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1894 = cvt(_T_1893) node _T_1895 = and(_T_1894, asSInt(UInt<13>(0h1000))) node _T_1896 = asSInt(_T_1895) node _T_1897 = eq(_T_1896, asSInt(UInt<1>(0h0))) node _T_1898 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1899 = cvt(_T_1898) node _T_1900 = and(_T_1899, asSInt(UInt<18>(0h2f000))) node _T_1901 = asSInt(_T_1900) node _T_1902 = eq(_T_1901, asSInt(UInt<1>(0h0))) node _T_1903 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1904 = cvt(_T_1903) node _T_1905 = and(_T_1904, asSInt(UInt<17>(0h10000))) node _T_1906 = asSInt(_T_1905) node _T_1907 = eq(_T_1906, asSInt(UInt<1>(0h0))) node _T_1908 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1909 = cvt(_T_1908) node _T_1910 = and(_T_1909, asSInt(UInt<13>(0h1000))) node _T_1911 = asSInt(_T_1910) node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0))) node _T_1913 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1914 = cvt(_T_1913) node _T_1915 = and(_T_1914, asSInt(UInt<27>(0h4000000))) node _T_1916 = asSInt(_T_1915) node _T_1917 = eq(_T_1916, asSInt(UInt<1>(0h0))) node _T_1918 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1919 = cvt(_T_1918) node _T_1920 = and(_T_1919, asSInt(UInt<13>(0h1000))) node _T_1921 = asSInt(_T_1920) node _T_1922 = eq(_T_1921, asSInt(UInt<1>(0h0))) node _T_1923 = or(_T_1892, _T_1897) node _T_1924 = or(_T_1923, _T_1902) node _T_1925 = or(_T_1924, _T_1907) node _T_1926 = or(_T_1925, _T_1912) node _T_1927 = or(_T_1926, _T_1917) node _T_1928 = or(_T_1927, _T_1922) node _T_1929 = and(_T_1887, _T_1928) node _T_1930 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1931 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1932 = cvt(_T_1931) node _T_1933 = and(_T_1932, asSInt(UInt<17>(0h10000))) node _T_1934 = asSInt(_T_1933) node _T_1935 = eq(_T_1934, asSInt(UInt<1>(0h0))) node _T_1936 = and(_T_1930, _T_1935) node _T_1937 = or(UInt<1>(0h0), _T_1929) node _T_1938 = or(_T_1937, _T_1936) node _T_1939 = and(_T_1883, _T_1938) node _T_1940 = asUInt(reset) node _T_1941 = eq(_T_1940, UInt<1>(0h0)) when _T_1941 : node _T_1942 = eq(_T_1939, UInt<1>(0h0)) when _T_1942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1939, UInt<1>(0h1), "") : assert_36 node _T_1943 = asUInt(reset) node _T_1944 = eq(_T_1943, UInt<1>(0h0)) when _T_1944 : node _T_1945 = eq(source_ok, UInt<1>(0h0)) when _T_1945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1946 = asUInt(reset) node _T_1947 = eq(_T_1946, UInt<1>(0h0)) when _T_1947 : node _T_1948 = eq(is_aligned, UInt<1>(0h0)) when _T_1948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1949 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1950 = asUInt(reset) node _T_1951 = eq(_T_1950, UInt<1>(0h0)) when _T_1951 : node _T_1952 = eq(_T_1949, UInt<1>(0h0)) when _T_1952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1949, UInt<1>(0h1), "") : assert_39 node _T_1953 = eq(io.in.a.bits.mask, mask) node _T_1954 = asUInt(reset) node _T_1955 = eq(_T_1954, UInt<1>(0h0)) when _T_1955 : node _T_1956 = eq(_T_1953, UInt<1>(0h0)) when _T_1956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1953, UInt<1>(0h1), "") : assert_40 node _T_1957 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1957 : node _T_1958 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1959 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1960 = and(_T_1958, _T_1959) node _T_1961 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1962 = shr(io.in.a.bits.source, 2) node _T_1963 = eq(_T_1962, UInt<1>(0h0)) node _T_1964 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1965 = and(_T_1963, _T_1964) node _T_1966 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1967 = and(_T_1965, _T_1966) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1968 = shr(io.in.a.bits.source, 2) node _T_1969 = eq(_T_1968, UInt<1>(0h1)) node _T_1970 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1971 = and(_T_1969, _T_1970) node _T_1972 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1973 = and(_T_1971, _T_1972) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1974 = shr(io.in.a.bits.source, 2) node _T_1975 = eq(_T_1974, UInt<2>(0h2)) node _T_1976 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1977 = and(_T_1975, _T_1976) node _T_1978 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1979 = and(_T_1977, _T_1978) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1980 = shr(io.in.a.bits.source, 2) node _T_1981 = eq(_T_1980, UInt<2>(0h3)) node _T_1982 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1983 = and(_T_1981, _T_1982) node _T_1984 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1985 = and(_T_1983, _T_1984) node _T_1986 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1987 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1988 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1989 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1990 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1991 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1992 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1993 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1994 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1995 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1996 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1997 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1998 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1999 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_2000 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_2001 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_2002 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_2003 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_2004 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_2005 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_2006 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_2007 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_2008 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_2009 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_2010 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_2011 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_2012 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_2013 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_2014 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_2015 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_2016 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_2017 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_2018 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_2019 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_2020 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_2021 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_2022 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_2023 = or(_T_1961, _T_1967) node _T_2024 = or(_T_2023, _T_1973) node _T_2025 = or(_T_2024, _T_1979) node _T_2026 = or(_T_2025, _T_1985) node _T_2027 = or(_T_2026, _T_1986) node _T_2028 = or(_T_2027, _T_1987) node _T_2029 = or(_T_2028, _T_1988) node _T_2030 = or(_T_2029, _T_1989) node _T_2031 = or(_T_2030, _T_1990) node _T_2032 = or(_T_2031, _T_1991) node _T_2033 = or(_T_2032, _T_1992) node _T_2034 = or(_T_2033, _T_1993) node _T_2035 = or(_T_2034, _T_1994) node _T_2036 = or(_T_2035, _T_1995) node _T_2037 = or(_T_2036, _T_1996) node _T_2038 = or(_T_2037, _T_1997) node _T_2039 = or(_T_2038, _T_1998) node _T_2040 = or(_T_2039, _T_1999) node _T_2041 = or(_T_2040, _T_2000) node _T_2042 = or(_T_2041, _T_2001) node _T_2043 = or(_T_2042, _T_2002) node _T_2044 = or(_T_2043, _T_2003) node _T_2045 = or(_T_2044, _T_2004) node _T_2046 = or(_T_2045, _T_2005) node _T_2047 = or(_T_2046, _T_2006) node _T_2048 = or(_T_2047, _T_2007) node _T_2049 = or(_T_2048, _T_2008) node _T_2050 = or(_T_2049, _T_2009) node _T_2051 = or(_T_2050, _T_2010) node _T_2052 = or(_T_2051, _T_2011) node _T_2053 = or(_T_2052, _T_2012) node _T_2054 = or(_T_2053, _T_2013) node _T_2055 = or(_T_2054, _T_2014) node _T_2056 = or(_T_2055, _T_2015) node _T_2057 = or(_T_2056, _T_2016) node _T_2058 = or(_T_2057, _T_2017) node _T_2059 = or(_T_2058, _T_2018) node _T_2060 = or(_T_2059, _T_2019) node _T_2061 = or(_T_2060, _T_2020) node _T_2062 = or(_T_2061, _T_2021) node _T_2063 = or(_T_2062, _T_2022) node _T_2064 = and(_T_1960, _T_2063) node _T_2065 = or(UInt<1>(0h0), _T_2064) node _T_2066 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2067 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_2068 = and(_T_2066, _T_2067) node _T_2069 = or(UInt<1>(0h0), _T_2068) node _T_2070 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<14>(0h2000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<13>(0h1000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<18>(0h2f000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<17>(0h10000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<13>(0h1000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_2096 = cvt(_T_2095) node _T_2097 = and(_T_2096, asSInt(UInt<27>(0h4000000))) node _T_2098 = asSInt(_T_2097) node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0))) node _T_2100 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_2101 = cvt(_T_2100) node _T_2102 = and(_T_2101, asSInt(UInt<13>(0h1000))) node _T_2103 = asSInt(_T_2102) node _T_2104 = eq(_T_2103, asSInt(UInt<1>(0h0))) node _T_2105 = or(_T_2074, _T_2079) node _T_2106 = or(_T_2105, _T_2084) node _T_2107 = or(_T_2106, _T_2089) node _T_2108 = or(_T_2107, _T_2094) node _T_2109 = or(_T_2108, _T_2099) node _T_2110 = or(_T_2109, _T_2104) node _T_2111 = and(_T_2069, _T_2110) node _T_2112 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2113 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_2114 = cvt(_T_2113) node _T_2115 = and(_T_2114, asSInt(UInt<17>(0h10000))) node _T_2116 = asSInt(_T_2115) node _T_2117 = eq(_T_2116, asSInt(UInt<1>(0h0))) node _T_2118 = and(_T_2112, _T_2117) node _T_2119 = or(UInt<1>(0h0), _T_2111) node _T_2120 = or(_T_2119, _T_2118) node _T_2121 = and(_T_2065, _T_2120) node _T_2122 = asUInt(reset) node _T_2123 = eq(_T_2122, UInt<1>(0h0)) when _T_2123 : node _T_2124 = eq(_T_2121, UInt<1>(0h0)) when _T_2124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_2121, UInt<1>(0h1), "") : assert_41 node _T_2125 = asUInt(reset) node _T_2126 = eq(_T_2125, UInt<1>(0h0)) when _T_2126 : node _T_2127 = eq(source_ok, UInt<1>(0h0)) when _T_2127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_2128 = asUInt(reset) node _T_2129 = eq(_T_2128, UInt<1>(0h0)) when _T_2129 : node _T_2130 = eq(is_aligned, UInt<1>(0h0)) when _T_2130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_2131 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_2132 = asUInt(reset) node _T_2133 = eq(_T_2132, UInt<1>(0h0)) when _T_2133 : node _T_2134 = eq(_T_2131, UInt<1>(0h0)) when _T_2134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_2131, UInt<1>(0h1), "") : assert_44 node _T_2135 = eq(io.in.a.bits.mask, mask) node _T_2136 = asUInt(reset) node _T_2137 = eq(_T_2136, UInt<1>(0h0)) when _T_2137 : node _T_2138 = eq(_T_2135, UInt<1>(0h0)) when _T_2138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_2135, UInt<1>(0h1), "") : assert_45 node _T_2139 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_2139 : node _T_2140 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2141 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_2142 = and(_T_2140, _T_2141) node _T_2143 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_2144 = shr(io.in.a.bits.source, 2) node _T_2145 = eq(_T_2144, UInt<1>(0h0)) node _T_2146 = leq(UInt<1>(0h0), uncommonBits_40) node _T_2147 = and(_T_2145, _T_2146) node _T_2148 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_2149 = and(_T_2147, _T_2148) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_2150 = shr(io.in.a.bits.source, 2) node _T_2151 = eq(_T_2150, UInt<1>(0h1)) node _T_2152 = leq(UInt<1>(0h0), uncommonBits_41) node _T_2153 = and(_T_2151, _T_2152) node _T_2154 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_2155 = and(_T_2153, _T_2154) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_2156 = shr(io.in.a.bits.source, 2) node _T_2157 = eq(_T_2156, UInt<2>(0h2)) node _T_2158 = leq(UInt<1>(0h0), uncommonBits_42) node _T_2159 = and(_T_2157, _T_2158) node _T_2160 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_2161 = and(_T_2159, _T_2160) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_2162 = shr(io.in.a.bits.source, 2) node _T_2163 = eq(_T_2162, UInt<2>(0h3)) node _T_2164 = leq(UInt<1>(0h0), uncommonBits_43) node _T_2165 = and(_T_2163, _T_2164) node _T_2166 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_2167 = and(_T_2165, _T_2166) node _T_2168 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_2169 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_2170 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_2171 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_2172 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_2173 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_2174 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_2175 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_2176 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_2177 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_2178 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_2179 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_2180 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_2181 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_2182 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_2183 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_2184 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_2185 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_2186 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_2187 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_2188 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_2189 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_2190 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_2191 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_2192 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_2193 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_2194 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_2195 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_2196 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_2197 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_2198 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_2199 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_2200 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_2201 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_2202 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_2203 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_2204 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_2205 = or(_T_2143, _T_2149) node _T_2206 = or(_T_2205, _T_2155) node _T_2207 = or(_T_2206, _T_2161) node _T_2208 = or(_T_2207, _T_2167) node _T_2209 = or(_T_2208, _T_2168) node _T_2210 = or(_T_2209, _T_2169) node _T_2211 = or(_T_2210, _T_2170) node _T_2212 = or(_T_2211, _T_2171) node _T_2213 = or(_T_2212, _T_2172) node _T_2214 = or(_T_2213, _T_2173) node _T_2215 = or(_T_2214, _T_2174) node _T_2216 = or(_T_2215, _T_2175) node _T_2217 = or(_T_2216, _T_2176) node _T_2218 = or(_T_2217, _T_2177) node _T_2219 = or(_T_2218, _T_2178) node _T_2220 = or(_T_2219, _T_2179) node _T_2221 = or(_T_2220, _T_2180) node _T_2222 = or(_T_2221, _T_2181) node _T_2223 = or(_T_2222, _T_2182) node _T_2224 = or(_T_2223, _T_2183) node _T_2225 = or(_T_2224, _T_2184) node _T_2226 = or(_T_2225, _T_2185) node _T_2227 = or(_T_2226, _T_2186) node _T_2228 = or(_T_2227, _T_2187) node _T_2229 = or(_T_2228, _T_2188) node _T_2230 = or(_T_2229, _T_2189) node _T_2231 = or(_T_2230, _T_2190) node _T_2232 = or(_T_2231, _T_2191) node _T_2233 = or(_T_2232, _T_2192) node _T_2234 = or(_T_2233, _T_2193) node _T_2235 = or(_T_2234, _T_2194) node _T_2236 = or(_T_2235, _T_2195) node _T_2237 = or(_T_2236, _T_2196) node _T_2238 = or(_T_2237, _T_2197) node _T_2239 = or(_T_2238, _T_2198) node _T_2240 = or(_T_2239, _T_2199) node _T_2241 = or(_T_2240, _T_2200) node _T_2242 = or(_T_2241, _T_2201) node _T_2243 = or(_T_2242, _T_2202) node _T_2244 = or(_T_2243, _T_2203) node _T_2245 = or(_T_2244, _T_2204) node _T_2246 = and(_T_2142, _T_2245) node _T_2247 = or(UInt<1>(0h0), _T_2246) node _T_2248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_2250 = and(_T_2248, _T_2249) node _T_2251 = or(UInt<1>(0h0), _T_2250) node _T_2252 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_2253 = cvt(_T_2252) node _T_2254 = and(_T_2253, asSInt(UInt<13>(0h1000))) node _T_2255 = asSInt(_T_2254) node _T_2256 = eq(_T_2255, asSInt(UInt<1>(0h0))) node _T_2257 = and(_T_2251, _T_2256) node _T_2258 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2259 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_2260 = cvt(_T_2259) node _T_2261 = and(_T_2260, asSInt(UInt<14>(0h2000))) node _T_2262 = asSInt(_T_2261) node _T_2263 = eq(_T_2262, asSInt(UInt<1>(0h0))) node _T_2264 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_2265 = cvt(_T_2264) node _T_2266 = and(_T_2265, asSInt(UInt<17>(0h10000))) node _T_2267 = asSInt(_T_2266) node _T_2268 = eq(_T_2267, asSInt(UInt<1>(0h0))) node _T_2269 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_2270 = cvt(_T_2269) node _T_2271 = and(_T_2270, asSInt(UInt<18>(0h2f000))) node _T_2272 = asSInt(_T_2271) node _T_2273 = eq(_T_2272, asSInt(UInt<1>(0h0))) node _T_2274 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_2275 = cvt(_T_2274) node _T_2276 = and(_T_2275, asSInt(UInt<17>(0h10000))) node _T_2277 = asSInt(_T_2276) node _T_2278 = eq(_T_2277, asSInt(UInt<1>(0h0))) node _T_2279 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_2280 = cvt(_T_2279) node _T_2281 = and(_T_2280, asSInt(UInt<13>(0h1000))) node _T_2282 = asSInt(_T_2281) node _T_2283 = eq(_T_2282, asSInt(UInt<1>(0h0))) node _T_2284 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_2285 = cvt(_T_2284) node _T_2286 = and(_T_2285, asSInt(UInt<27>(0h4000000))) node _T_2287 = asSInt(_T_2286) node _T_2288 = eq(_T_2287, asSInt(UInt<1>(0h0))) node _T_2289 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_2290 = cvt(_T_2289) node _T_2291 = and(_T_2290, asSInt(UInt<13>(0h1000))) node _T_2292 = asSInt(_T_2291) node _T_2293 = eq(_T_2292, asSInt(UInt<1>(0h0))) node _T_2294 = or(_T_2263, _T_2268) node _T_2295 = or(_T_2294, _T_2273) node _T_2296 = or(_T_2295, _T_2278) node _T_2297 = or(_T_2296, _T_2283) node _T_2298 = or(_T_2297, _T_2288) node _T_2299 = or(_T_2298, _T_2293) node _T_2300 = and(_T_2258, _T_2299) node _T_2301 = or(UInt<1>(0h0), _T_2257) node _T_2302 = or(_T_2301, _T_2300) node _T_2303 = and(_T_2247, _T_2302) node _T_2304 = asUInt(reset) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) when _T_2305 : node _T_2306 = eq(_T_2303, UInt<1>(0h0)) when _T_2306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_2303, UInt<1>(0h1), "") : assert_46 node _T_2307 = asUInt(reset) node _T_2308 = eq(_T_2307, UInt<1>(0h0)) when _T_2308 : node _T_2309 = eq(source_ok, UInt<1>(0h0)) when _T_2309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_2310 = asUInt(reset) node _T_2311 = eq(_T_2310, UInt<1>(0h0)) when _T_2311 : node _T_2312 = eq(is_aligned, UInt<1>(0h0)) when _T_2312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_2313 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_2314 = asUInt(reset) node _T_2315 = eq(_T_2314, UInt<1>(0h0)) when _T_2315 : node _T_2316 = eq(_T_2313, UInt<1>(0h0)) when _T_2316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_2313, UInt<1>(0h1), "") : assert_49 node _T_2317 = eq(io.in.a.bits.mask, mask) node _T_2318 = asUInt(reset) node _T_2319 = eq(_T_2318, UInt<1>(0h0)) when _T_2319 : node _T_2320 = eq(_T_2317, UInt<1>(0h0)) when _T_2320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_2317, UInt<1>(0h1), "") : assert_50 node _T_2321 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_2322 = asUInt(reset) node _T_2323 = eq(_T_2322, UInt<1>(0h0)) when _T_2323 : node _T_2324 = eq(_T_2321, UInt<1>(0h0)) when _T_2324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_2321, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_2325 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2326 = asUInt(reset) node _T_2327 = eq(_T_2326, UInt<1>(0h0)) when _T_2327 : node _T_2328 = eq(_T_2325, UInt<1>(0h0)) when _T_2328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_2325, UInt<1>(0h1), "") : assert_52 node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_103 = shr(io.in.d.bits.source, 2) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<1>(0h0)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_109 = shr(io.in.d.bits.source, 2) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<1>(0h1)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_115 = shr(io.in.d.bits.source, 2) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_121 = shr(io.in.d.bits.source, 2) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<2>(0h3)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h4c)) node _source_ok_T_128 = eq(io.in.d.bits.source, UInt<7>(0h4d)) node _source_ok_T_129 = eq(io.in.d.bits.source, UInt<7>(0h4e)) node _source_ok_T_130 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_131 = eq(io.in.d.bits.source, UInt<7>(0h49)) node _source_ok_T_132 = eq(io.in.d.bits.source, UInt<7>(0h4a)) node _source_ok_T_133 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_134 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_135 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_136 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_137 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_138 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_T_139 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_140 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_141 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_142 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_143 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_144 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_145 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_146 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_147 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_148 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_149 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_150 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_151 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_152 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_153 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_154 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_155 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_156 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_157 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_159 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_160 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_161 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_163 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[42] connect _source_ok_WIRE_1[0], _source_ok_T_102 connect _source_ok_WIRE_1[1], _source_ok_T_108 connect _source_ok_WIRE_1[2], _source_ok_T_114 connect _source_ok_WIRE_1[3], _source_ok_T_120 connect _source_ok_WIRE_1[4], _source_ok_T_126 connect _source_ok_WIRE_1[5], _source_ok_T_127 connect _source_ok_WIRE_1[6], _source_ok_T_128 connect _source_ok_WIRE_1[7], _source_ok_T_129 connect _source_ok_WIRE_1[8], _source_ok_T_130 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_132 connect _source_ok_WIRE_1[11], _source_ok_T_133 connect _source_ok_WIRE_1[12], _source_ok_T_134 connect _source_ok_WIRE_1[13], _source_ok_T_135 connect _source_ok_WIRE_1[14], _source_ok_T_136 connect _source_ok_WIRE_1[15], _source_ok_T_137 connect _source_ok_WIRE_1[16], _source_ok_T_138 connect _source_ok_WIRE_1[17], _source_ok_T_139 connect _source_ok_WIRE_1[18], _source_ok_T_140 connect _source_ok_WIRE_1[19], _source_ok_T_141 connect _source_ok_WIRE_1[20], _source_ok_T_142 connect _source_ok_WIRE_1[21], _source_ok_T_143 connect _source_ok_WIRE_1[22], _source_ok_T_144 connect _source_ok_WIRE_1[23], _source_ok_T_145 connect _source_ok_WIRE_1[24], _source_ok_T_146 connect _source_ok_WIRE_1[25], _source_ok_T_147 connect _source_ok_WIRE_1[26], _source_ok_T_148 connect _source_ok_WIRE_1[27], _source_ok_T_149 connect _source_ok_WIRE_1[28], _source_ok_T_150 connect _source_ok_WIRE_1[29], _source_ok_T_151 connect _source_ok_WIRE_1[30], _source_ok_T_152 connect _source_ok_WIRE_1[31], _source_ok_T_153 connect _source_ok_WIRE_1[32], _source_ok_T_154 connect _source_ok_WIRE_1[33], _source_ok_T_155 connect _source_ok_WIRE_1[34], _source_ok_T_156 connect _source_ok_WIRE_1[35], _source_ok_T_157 connect _source_ok_WIRE_1[36], _source_ok_T_158 connect _source_ok_WIRE_1[37], _source_ok_T_159 connect _source_ok_WIRE_1[38], _source_ok_T_160 connect _source_ok_WIRE_1[39], _source_ok_T_161 connect _source_ok_WIRE_1[40], _source_ok_T_162 connect _source_ok_WIRE_1[41], _source_ok_T_163 node _source_ok_T_164 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_1[2]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_1[3]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_1[4]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_1[5]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_1[6]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[7]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[8]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[9]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[10]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[11]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[12]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[13]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[14]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[15]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[16]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[17]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[18]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[19]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[20]) node _source_ok_T_184 = or(_source_ok_T_183, _source_ok_WIRE_1[21]) node _source_ok_T_185 = or(_source_ok_T_184, _source_ok_WIRE_1[22]) node _source_ok_T_186 = or(_source_ok_T_185, _source_ok_WIRE_1[23]) node _source_ok_T_187 = or(_source_ok_T_186, _source_ok_WIRE_1[24]) node _source_ok_T_188 = or(_source_ok_T_187, _source_ok_WIRE_1[25]) node _source_ok_T_189 = or(_source_ok_T_188, _source_ok_WIRE_1[26]) node _source_ok_T_190 = or(_source_ok_T_189, _source_ok_WIRE_1[27]) node _source_ok_T_191 = or(_source_ok_T_190, _source_ok_WIRE_1[28]) node _source_ok_T_192 = or(_source_ok_T_191, _source_ok_WIRE_1[29]) node _source_ok_T_193 = or(_source_ok_T_192, _source_ok_WIRE_1[30]) node _source_ok_T_194 = or(_source_ok_T_193, _source_ok_WIRE_1[31]) node _source_ok_T_195 = or(_source_ok_T_194, _source_ok_WIRE_1[32]) node _source_ok_T_196 = or(_source_ok_T_195, _source_ok_WIRE_1[33]) node _source_ok_T_197 = or(_source_ok_T_196, _source_ok_WIRE_1[34]) node _source_ok_T_198 = or(_source_ok_T_197, _source_ok_WIRE_1[35]) node _source_ok_T_199 = or(_source_ok_T_198, _source_ok_WIRE_1[36]) node _source_ok_T_200 = or(_source_ok_T_199, _source_ok_WIRE_1[37]) node _source_ok_T_201 = or(_source_ok_T_200, _source_ok_WIRE_1[38]) node _source_ok_T_202 = or(_source_ok_T_201, _source_ok_WIRE_1[39]) node _source_ok_T_203 = or(_source_ok_T_202, _source_ok_WIRE_1[40]) node source_ok_1 = or(_source_ok_T_203, _source_ok_WIRE_1[41]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_2329 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_2329 : node _T_2330 = asUInt(reset) node _T_2331 = eq(_T_2330, UInt<1>(0h0)) when _T_2331 : node _T_2332 = eq(source_ok_1, UInt<1>(0h0)) when _T_2332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_2333 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2334 = asUInt(reset) node _T_2335 = eq(_T_2334, UInt<1>(0h0)) when _T_2335 : node _T_2336 = eq(_T_2333, UInt<1>(0h0)) when _T_2336 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_2333, UInt<1>(0h1), "") : assert_54 node _T_2337 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2338 = asUInt(reset) node _T_2339 = eq(_T_2338, UInt<1>(0h0)) when _T_2339 : node _T_2340 = eq(_T_2337, UInt<1>(0h0)) when _T_2340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_2337, UInt<1>(0h1), "") : assert_55 node _T_2341 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2342 = asUInt(reset) node _T_2343 = eq(_T_2342, UInt<1>(0h0)) when _T_2343 : node _T_2344 = eq(_T_2341, UInt<1>(0h0)) when _T_2344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_2341, UInt<1>(0h1), "") : assert_56 node _T_2345 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2346 = asUInt(reset) node _T_2347 = eq(_T_2346, UInt<1>(0h0)) when _T_2347 : node _T_2348 = eq(_T_2345, UInt<1>(0h0)) when _T_2348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_2345, UInt<1>(0h1), "") : assert_57 node _T_2349 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_2349 : node _T_2350 = asUInt(reset) node _T_2351 = eq(_T_2350, UInt<1>(0h0)) when _T_2351 : node _T_2352 = eq(source_ok_1, UInt<1>(0h0)) when _T_2352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_2353 = asUInt(reset) node _T_2354 = eq(_T_2353, UInt<1>(0h0)) when _T_2354 : node _T_2355 = eq(sink_ok, UInt<1>(0h0)) when _T_2355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_2356 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2357 = asUInt(reset) node _T_2358 = eq(_T_2357, UInt<1>(0h0)) when _T_2358 : node _T_2359 = eq(_T_2356, UInt<1>(0h0)) when _T_2359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_2356, UInt<1>(0h1), "") : assert_60 node _T_2360 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2361 = asUInt(reset) node _T_2362 = eq(_T_2361, UInt<1>(0h0)) when _T_2362 : node _T_2363 = eq(_T_2360, UInt<1>(0h0)) when _T_2363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_2360, UInt<1>(0h1), "") : assert_61 node _T_2364 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2365 = asUInt(reset) node _T_2366 = eq(_T_2365, UInt<1>(0h0)) when _T_2366 : node _T_2367 = eq(_T_2364, UInt<1>(0h0)) when _T_2367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_2364, UInt<1>(0h1), "") : assert_62 node _T_2368 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2369 = asUInt(reset) node _T_2370 = eq(_T_2369, UInt<1>(0h0)) when _T_2370 : node _T_2371 = eq(_T_2368, UInt<1>(0h0)) when _T_2371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_2368, UInt<1>(0h1), "") : assert_63 node _T_2372 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2373 = or(UInt<1>(0h1), _T_2372) node _T_2374 = asUInt(reset) node _T_2375 = eq(_T_2374, UInt<1>(0h0)) when _T_2375 : node _T_2376 = eq(_T_2373, UInt<1>(0h0)) when _T_2376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_2373, UInt<1>(0h1), "") : assert_64 node _T_2377 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_2377 : node _T_2378 = asUInt(reset) node _T_2379 = eq(_T_2378, UInt<1>(0h0)) when _T_2379 : node _T_2380 = eq(source_ok_1, UInt<1>(0h0)) when _T_2380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_2381 = asUInt(reset) node _T_2382 = eq(_T_2381, UInt<1>(0h0)) when _T_2382 : node _T_2383 = eq(sink_ok, UInt<1>(0h0)) when _T_2383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_2384 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2385 = asUInt(reset) node _T_2386 = eq(_T_2385, UInt<1>(0h0)) when _T_2386 : node _T_2387 = eq(_T_2384, UInt<1>(0h0)) when _T_2387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_2384, UInt<1>(0h1), "") : assert_67 node _T_2388 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2389 = asUInt(reset) node _T_2390 = eq(_T_2389, UInt<1>(0h0)) when _T_2390 : node _T_2391 = eq(_T_2388, UInt<1>(0h0)) when _T_2391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_2388, UInt<1>(0h1), "") : assert_68 node _T_2392 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2393 = asUInt(reset) node _T_2394 = eq(_T_2393, UInt<1>(0h0)) when _T_2394 : node _T_2395 = eq(_T_2392, UInt<1>(0h0)) when _T_2395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_2392, UInt<1>(0h1), "") : assert_69 node _T_2396 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2397 = or(_T_2396, io.in.d.bits.corrupt) node _T_2398 = asUInt(reset) node _T_2399 = eq(_T_2398, UInt<1>(0h0)) when _T_2399 : node _T_2400 = eq(_T_2397, UInt<1>(0h0)) when _T_2400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_2397, UInt<1>(0h1), "") : assert_70 node _T_2401 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2402 = or(UInt<1>(0h1), _T_2401) node _T_2403 = asUInt(reset) node _T_2404 = eq(_T_2403, UInt<1>(0h0)) when _T_2404 : node _T_2405 = eq(_T_2402, UInt<1>(0h0)) when _T_2405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_2402, UInt<1>(0h1), "") : assert_71 node _T_2406 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_2406 : node _T_2407 = asUInt(reset) node _T_2408 = eq(_T_2407, UInt<1>(0h0)) when _T_2408 : node _T_2409 = eq(source_ok_1, UInt<1>(0h0)) when _T_2409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_2410 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2411 = asUInt(reset) node _T_2412 = eq(_T_2411, UInt<1>(0h0)) when _T_2412 : node _T_2413 = eq(_T_2410, UInt<1>(0h0)) when _T_2413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_2410, UInt<1>(0h1), "") : assert_73 node _T_2414 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2415 = asUInt(reset) node _T_2416 = eq(_T_2415, UInt<1>(0h0)) when _T_2416 : node _T_2417 = eq(_T_2414, UInt<1>(0h0)) when _T_2417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_2414, UInt<1>(0h1), "") : assert_74 node _T_2418 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2419 = or(UInt<1>(0h1), _T_2418) node _T_2420 = asUInt(reset) node _T_2421 = eq(_T_2420, UInt<1>(0h0)) when _T_2421 : node _T_2422 = eq(_T_2419, UInt<1>(0h0)) when _T_2422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_2419, UInt<1>(0h1), "") : assert_75 node _T_2423 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_2423 : node _T_2424 = asUInt(reset) node _T_2425 = eq(_T_2424, UInt<1>(0h0)) when _T_2425 : node _T_2426 = eq(source_ok_1, UInt<1>(0h0)) when _T_2426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_2427 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2428 = asUInt(reset) node _T_2429 = eq(_T_2428, UInt<1>(0h0)) when _T_2429 : node _T_2430 = eq(_T_2427, UInt<1>(0h0)) when _T_2430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_2427, UInt<1>(0h1), "") : assert_77 node _T_2431 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2432 = or(_T_2431, io.in.d.bits.corrupt) node _T_2433 = asUInt(reset) node _T_2434 = eq(_T_2433, UInt<1>(0h0)) when _T_2434 : node _T_2435 = eq(_T_2432, UInt<1>(0h0)) when _T_2435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_2432, UInt<1>(0h1), "") : assert_78 node _T_2436 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2437 = or(UInt<1>(0h1), _T_2436) node _T_2438 = asUInt(reset) node _T_2439 = eq(_T_2438, UInt<1>(0h0)) when _T_2439 : node _T_2440 = eq(_T_2437, UInt<1>(0h0)) when _T_2440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_2437, UInt<1>(0h1), "") : assert_79 node _T_2441 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_2441 : node _T_2442 = asUInt(reset) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) when _T_2443 : node _T_2444 = eq(source_ok_1, UInt<1>(0h0)) when _T_2444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2445 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2446 = asUInt(reset) node _T_2447 = eq(_T_2446, UInt<1>(0h0)) when _T_2447 : node _T_2448 = eq(_T_2445, UInt<1>(0h0)) when _T_2448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2445, UInt<1>(0h1), "") : assert_81 node _T_2449 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2450 = asUInt(reset) node _T_2451 = eq(_T_2450, UInt<1>(0h0)) when _T_2451 : node _T_2452 = eq(_T_2449, UInt<1>(0h0)) when _T_2452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2449, UInt<1>(0h1), "") : assert_82 node _T_2453 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2454 = or(UInt<1>(0h1), _T_2453) node _T_2455 = asUInt(reset) node _T_2456 = eq(_T_2455, UInt<1>(0h0)) when _T_2456 : node _T_2457 = eq(_T_2454, UInt<1>(0h0)) when _T_2457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2454, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2458 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2459 = asUInt(reset) node _T_2460 = eq(_T_2459, UInt<1>(0h0)) when _T_2460 : node _T_2461 = eq(_T_2458, UInt<1>(0h0)) when _T_2461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2458, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2462 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2463 = asUInt(reset) node _T_2464 = eq(_T_2463, UInt<1>(0h0)) when _T_2464 : node _T_2465 = eq(_T_2462, UInt<1>(0h0)) when _T_2465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2462, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2466 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2467 = asUInt(reset) node _T_2468 = eq(_T_2467, UInt<1>(0h0)) when _T_2468 : node _T_2469 = eq(_T_2466, UInt<1>(0h0)) when _T_2469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2466, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2470 = eq(a_first, UInt<1>(0h0)) node _T_2471 = and(io.in.a.valid, _T_2470) when _T_2471 : node _T_2472 = eq(io.in.a.bits.opcode, opcode) node _T_2473 = asUInt(reset) node _T_2474 = eq(_T_2473, UInt<1>(0h0)) when _T_2474 : node _T_2475 = eq(_T_2472, UInt<1>(0h0)) when _T_2475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2472, UInt<1>(0h1), "") : assert_87 node _T_2476 = eq(io.in.a.bits.param, param) node _T_2477 = asUInt(reset) node _T_2478 = eq(_T_2477, UInt<1>(0h0)) when _T_2478 : node _T_2479 = eq(_T_2476, UInt<1>(0h0)) when _T_2479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2476, UInt<1>(0h1), "") : assert_88 node _T_2480 = eq(io.in.a.bits.size, size) node _T_2481 = asUInt(reset) node _T_2482 = eq(_T_2481, UInt<1>(0h0)) when _T_2482 : node _T_2483 = eq(_T_2480, UInt<1>(0h0)) when _T_2483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2480, UInt<1>(0h1), "") : assert_89 node _T_2484 = eq(io.in.a.bits.source, source) node _T_2485 = asUInt(reset) node _T_2486 = eq(_T_2485, UInt<1>(0h0)) when _T_2486 : node _T_2487 = eq(_T_2484, UInt<1>(0h0)) when _T_2487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2484, UInt<1>(0h1), "") : assert_90 node _T_2488 = eq(io.in.a.bits.address, address) node _T_2489 = asUInt(reset) node _T_2490 = eq(_T_2489, UInt<1>(0h0)) when _T_2490 : node _T_2491 = eq(_T_2488, UInt<1>(0h0)) when _T_2491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2488, UInt<1>(0h1), "") : assert_91 node _T_2492 = and(io.in.a.ready, io.in.a.valid) node _T_2493 = and(_T_2492, a_first) when _T_2493 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2494 = eq(d_first, UInt<1>(0h0)) node _T_2495 = and(io.in.d.valid, _T_2494) when _T_2495 : node _T_2496 = eq(io.in.d.bits.opcode, opcode_1) node _T_2497 = asUInt(reset) node _T_2498 = eq(_T_2497, UInt<1>(0h0)) when _T_2498 : node _T_2499 = eq(_T_2496, UInt<1>(0h0)) when _T_2499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2496, UInt<1>(0h1), "") : assert_92 node _T_2500 = eq(io.in.d.bits.param, param_1) node _T_2501 = asUInt(reset) node _T_2502 = eq(_T_2501, UInt<1>(0h0)) when _T_2502 : node _T_2503 = eq(_T_2500, UInt<1>(0h0)) when _T_2503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2500, UInt<1>(0h1), "") : assert_93 node _T_2504 = eq(io.in.d.bits.size, size_1) node _T_2505 = asUInt(reset) node _T_2506 = eq(_T_2505, UInt<1>(0h0)) when _T_2506 : node _T_2507 = eq(_T_2504, UInt<1>(0h0)) when _T_2507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2504, UInt<1>(0h1), "") : assert_94 node _T_2508 = eq(io.in.d.bits.source, source_1) node _T_2509 = asUInt(reset) node _T_2510 = eq(_T_2509, UInt<1>(0h0)) when _T_2510 : node _T_2511 = eq(_T_2508, UInt<1>(0h0)) when _T_2511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2508, UInt<1>(0h1), "") : assert_95 node _T_2512 = eq(io.in.d.bits.sink, sink) node _T_2513 = asUInt(reset) node _T_2514 = eq(_T_2513, UInt<1>(0h0)) when _T_2514 : node _T_2515 = eq(_T_2512, UInt<1>(0h0)) when _T_2515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2512, UInt<1>(0h1), "") : assert_96 node _T_2516 = eq(io.in.d.bits.denied, denied) node _T_2517 = asUInt(reset) node _T_2518 = eq(_T_2517, UInt<1>(0h0)) when _T_2518 : node _T_2519 = eq(_T_2516, UInt<1>(0h0)) when _T_2519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2516, UInt<1>(0h1), "") : assert_97 node _T_2520 = and(io.in.d.ready, io.in.d.valid) node _T_2521 = and(_T_2520, d_first) when _T_2521 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<1032>, clock, reset, UInt<1032>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<1032> connect a_sizes_set, UInt<1032>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2522 = and(io.in.a.valid, a_first_1) node _T_2523 = and(_T_2522, UInt<1>(0h1)) when _T_2523 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2524 = and(io.in.a.ready, io.in.a.valid) node _T_2525 = and(_T_2524, a_first_1) node _T_2526 = and(_T_2525, UInt<1>(0h1)) when _T_2526 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2527 = dshr(inflight, io.in.a.bits.source) node _T_2528 = bits(_T_2527, 0, 0) node _T_2529 = eq(_T_2528, UInt<1>(0h0)) node _T_2530 = asUInt(reset) node _T_2531 = eq(_T_2530, UInt<1>(0h0)) when _T_2531 : node _T_2532 = eq(_T_2529, UInt<1>(0h0)) when _T_2532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2529, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<1032> connect d_sizes_clr, UInt<1032>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2533 = and(io.in.d.valid, d_first_1) node _T_2534 = and(_T_2533, UInt<1>(0h1)) node _T_2535 = eq(d_release_ack, UInt<1>(0h0)) node _T_2536 = and(_T_2534, _T_2535) when _T_2536 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2537 = and(io.in.d.ready, io.in.d.valid) node _T_2538 = and(_T_2537, d_first_1) node _T_2539 = and(_T_2538, UInt<1>(0h1)) node _T_2540 = eq(d_release_ack, UInt<1>(0h0)) node _T_2541 = and(_T_2539, _T_2540) when _T_2541 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2542 = and(io.in.d.valid, d_first_1) node _T_2543 = and(_T_2542, UInt<1>(0h1)) node _T_2544 = eq(d_release_ack, UInt<1>(0h0)) node _T_2545 = and(_T_2543, _T_2544) when _T_2545 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2546 = dshr(inflight, io.in.d.bits.source) node _T_2547 = bits(_T_2546, 0, 0) node _T_2548 = or(_T_2547, same_cycle_resp) node _T_2549 = asUInt(reset) node _T_2550 = eq(_T_2549, UInt<1>(0h0)) when _T_2550 : node _T_2551 = eq(_T_2548, UInt<1>(0h0)) when _T_2551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2548, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2552 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2553 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2554 = or(_T_2552, _T_2553) node _T_2555 = asUInt(reset) node _T_2556 = eq(_T_2555, UInt<1>(0h0)) when _T_2556 : node _T_2557 = eq(_T_2554, UInt<1>(0h0)) when _T_2557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2554, UInt<1>(0h1), "") : assert_100 node _T_2558 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2559 = asUInt(reset) node _T_2560 = eq(_T_2559, UInt<1>(0h0)) when _T_2560 : node _T_2561 = eq(_T_2558, UInt<1>(0h0)) when _T_2561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2558, UInt<1>(0h1), "") : assert_101 else : node _T_2562 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2563 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2564 = or(_T_2562, _T_2563) node _T_2565 = asUInt(reset) node _T_2566 = eq(_T_2565, UInt<1>(0h0)) when _T_2566 : node _T_2567 = eq(_T_2564, UInt<1>(0h0)) when _T_2567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2564, UInt<1>(0h1), "") : assert_102 node _T_2568 = eq(io.in.d.bits.size, a_size_lookup) node _T_2569 = asUInt(reset) node _T_2570 = eq(_T_2569, UInt<1>(0h0)) when _T_2570 : node _T_2571 = eq(_T_2568, UInt<1>(0h0)) when _T_2571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2568, UInt<1>(0h1), "") : assert_103 node _T_2572 = and(io.in.d.valid, d_first_1) node _T_2573 = and(_T_2572, a_first_1) node _T_2574 = and(_T_2573, io.in.a.valid) node _T_2575 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2576 = and(_T_2574, _T_2575) node _T_2577 = eq(d_release_ack, UInt<1>(0h0)) node _T_2578 = and(_T_2576, _T_2577) when _T_2578 : node _T_2579 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2580 = or(_T_2579, io.in.a.ready) node _T_2581 = asUInt(reset) node _T_2582 = eq(_T_2581, UInt<1>(0h0)) when _T_2582 : node _T_2583 = eq(_T_2580, UInt<1>(0h0)) when _T_2583 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2580, UInt<1>(0h1), "") : assert_104 node _T_2584 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2585 = orr(a_set_wo_ready) node _T_2586 = eq(_T_2585, UInt<1>(0h0)) node _T_2587 = or(_T_2584, _T_2586) node _T_2588 = asUInt(reset) node _T_2589 = eq(_T_2588, UInt<1>(0h0)) when _T_2589 : node _T_2590 = eq(_T_2587, UInt<1>(0h0)) when _T_2590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_2587, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_94 node _T_2591 = orr(inflight) node _T_2592 = eq(_T_2591, UInt<1>(0h0)) node _T_2593 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2594 = or(_T_2592, _T_2593) node _T_2595 = lt(watchdog, plusarg_reader.out) node _T_2596 = or(_T_2594, _T_2595) node _T_2597 = asUInt(reset) node _T_2598 = eq(_T_2597, UInt<1>(0h0)) when _T_2598 : node _T_2599 = eq(_T_2596, UInt<1>(0h0)) when _T_2599 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2596, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2600 = and(io.in.a.ready, io.in.a.valid) node _T_2601 = and(io.in.d.ready, io.in.d.valid) node _T_2602 = or(_T_2600, _T_2601) when _T_2602 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<1032>, clock, reset, UInt<1032>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<1032> connect c_sizes_set, UInt<1032>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2603 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2604 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2605 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2606 = and(_T_2604, _T_2605) node _T_2607 = and(_T_2603, _T_2606) when _T_2607 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2608 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2609 = and(_T_2608, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2610 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2611 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2612 = and(_T_2610, _T_2611) node _T_2613 = and(_T_2609, _T_2612) when _T_2613 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2614 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2615 = bits(_T_2614, 0, 0) node _T_2616 = eq(_T_2615, UInt<1>(0h0)) node _T_2617 = asUInt(reset) node _T_2618 = eq(_T_2617, UInt<1>(0h0)) when _T_2618 : node _T_2619 = eq(_T_2616, UInt<1>(0h0)) when _T_2619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_2616, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<1032> connect d_sizes_clr_1, UInt<1032>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2620 = and(io.in.d.valid, d_first_2) node _T_2621 = and(_T_2620, UInt<1>(0h1)) node _T_2622 = and(_T_2621, d_release_ack_1) when _T_2622 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2623 = and(io.in.d.ready, io.in.d.valid) node _T_2624 = and(_T_2623, d_first_2) node _T_2625 = and(_T_2624, UInt<1>(0h1)) node _T_2626 = and(_T_2625, d_release_ack_1) when _T_2626 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2627 = and(io.in.d.valid, d_first_2) node _T_2628 = and(_T_2627, UInt<1>(0h1)) node _T_2629 = and(_T_2628, d_release_ack_1) when _T_2629 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2630 = dshr(inflight_1, io.in.d.bits.source) node _T_2631 = bits(_T_2630, 0, 0) node _T_2632 = or(_T_2631, same_cycle_resp_1) node _T_2633 = asUInt(reset) node _T_2634 = eq(_T_2633, UInt<1>(0h0)) when _T_2634 : node _T_2635 = eq(_T_2632, UInt<1>(0h0)) when _T_2635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2632, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2636 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2637 = asUInt(reset) node _T_2638 = eq(_T_2637, UInt<1>(0h0)) when _T_2638 : node _T_2639 = eq(_T_2636, UInt<1>(0h0)) when _T_2639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2636, UInt<1>(0h1), "") : assert_109 else : node _T_2640 = eq(io.in.d.bits.size, c_size_lookup) node _T_2641 = asUInt(reset) node _T_2642 = eq(_T_2641, UInt<1>(0h0)) when _T_2642 : node _T_2643 = eq(_T_2640, UInt<1>(0h0)) when _T_2643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2640, UInt<1>(0h1), "") : assert_110 node _T_2644 = and(io.in.d.valid, d_first_2) node _T_2645 = and(_T_2644, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2646 = and(_T_2645, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2647 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2648 = and(_T_2646, _T_2647) node _T_2649 = and(_T_2648, d_release_ack_1) node _T_2650 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2651 = and(_T_2649, _T_2650) when _T_2651 : node _T_2652 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2653 = or(_T_2652, _WIRE_27.ready) node _T_2654 = asUInt(reset) node _T_2655 = eq(_T_2654, UInt<1>(0h0)) when _T_2655 : node _T_2656 = eq(_T_2653, UInt<1>(0h0)) when _T_2656 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_2653, UInt<1>(0h1), "") : assert_111 node _T_2657 = orr(c_set_wo_ready) when _T_2657 : node _T_2658 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2659 = asUInt(reset) node _T_2660 = eq(_T_2659, UInt<1>(0h0)) when _T_2660 : node _T_2661 = eq(_T_2658, UInt<1>(0h0)) when _T_2661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_2658, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_95 node _T_2662 = orr(inflight_1) node _T_2663 = eq(_T_2662, UInt<1>(0h0)) node _T_2664 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2665 = or(_T_2663, _T_2664) node _T_2666 = lt(watchdog_1, plusarg_reader_1.out) node _T_2667 = or(_T_2665, _T_2666) node _T_2668 = asUInt(reset) node _T_2669 = eq(_T_2668, UInt<1>(0h0)) when _T_2669 : node _T_2670 = eq(_T_2667, UInt<1>(0h0)) when _T_2670 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_2667, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2671 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2672 = and(io.in.d.ready, io.in.d.valid) node _T_2673 = or(_T_2671, _T_2672) when _T_2673 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_31( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [255:0] _GEN_0 = {248'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [255:0] _GEN_3 = {248'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_17 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = or(UInt<1>(0h0), _T_70) node _T_72 = and(_T_21, _T_71) node _T_73 = asUInt(reset) node _T_74 = eq(_T_73, UInt<1>(0h0)) when _T_74 : node _T_75 = eq(_T_72, UInt<1>(0h0)) when _T_75 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_72, UInt<1>(0h1), "") : assert_2 node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_77 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_78 = and(_T_76, _T_77) node _T_79 = or(UInt<1>(0h0), _T_78) node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<14>(0h2000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<13>(0h1000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<17>(0h10000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<18>(0h2f000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<17>(0h10000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<13>(0h1000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<27>(0h4000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<13>(0h1000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = or(_T_84, _T_89) node _T_121 = or(_T_120, _T_94) node _T_122 = or(_T_121, _T_99) node _T_123 = or(_T_122, _T_104) node _T_124 = or(_T_123, _T_109) node _T_125 = or(_T_124, _T_114) node _T_126 = or(_T_125, _T_119) node _T_127 = and(_T_79, _T_126) node _T_128 = or(UInt<1>(0h0), _T_127) node _T_129 = and(UInt<1>(0h0), _T_128) node _T_130 = asUInt(reset) node _T_131 = eq(_T_130, UInt<1>(0h0)) when _T_131 : node _T_132 = eq(_T_129, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_129, UInt<1>(0h1), "") : assert_3 node _T_133 = asUInt(reset) node _T_134 = eq(_T_133, UInt<1>(0h0)) when _T_134 : node _T_135 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_136 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_136, UInt<1>(0h1), "") : assert_5 node _T_140 = asUInt(reset) node _T_141 = eq(_T_140, UInt<1>(0h0)) when _T_141 : node _T_142 = eq(is_aligned, UInt<1>(0h0)) when _T_142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_143 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : node _T_146 = eq(_T_143, UInt<1>(0h0)) when _T_146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_143, UInt<1>(0h1), "") : assert_7 node _T_147 = not(io.in.a.bits.mask) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_148, UInt<1>(0h1), "") : assert_8 node _T_152 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_T_152, UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_152, UInt<1>(0h1), "") : assert_9 node _T_156 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_156 : node _T_157 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_158 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(UInt<1>(0h0), _T_161) node _T_163 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<14>(0h2000))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_170 = cvt(_T_169) node _T_171 = and(_T_170, asSInt(UInt<13>(0h1000))) node _T_172 = asSInt(_T_171) node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0))) node _T_174 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_175 = cvt(_T_174) node _T_176 = and(_T_175, asSInt(UInt<17>(0h10000))) node _T_177 = asSInt(_T_176) node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0))) node _T_179 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<18>(0h2f000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<17>(0h10000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<13>(0h1000))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<27>(0h4000000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<13>(0h1000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = or(_T_168, _T_173) node _T_205 = or(_T_204, _T_178) node _T_206 = or(_T_205, _T_183) node _T_207 = or(_T_206, _T_188) node _T_208 = or(_T_207, _T_193) node _T_209 = or(_T_208, _T_198) node _T_210 = or(_T_209, _T_203) node _T_211 = and(_T_163, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = and(_T_162, _T_212) node _T_214 = asUInt(reset) node _T_215 = eq(_T_214, UInt<1>(0h0)) when _T_215 : node _T_216 = eq(_T_213, UInt<1>(0h0)) when _T_216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_213, UInt<1>(0h1), "") : assert_10 node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_219 = and(_T_217, _T_218) node _T_220 = or(UInt<1>(0h0), _T_219) node _T_221 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<14>(0h2000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<17>(0h10000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<18>(0h2f000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<13>(0h1000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<27>(0h4000000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<13>(0h1000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = or(_T_225, _T_230) node _T_262 = or(_T_261, _T_235) node _T_263 = or(_T_262, _T_240) node _T_264 = or(_T_263, _T_245) node _T_265 = or(_T_264, _T_250) node _T_266 = or(_T_265, _T_255) node _T_267 = or(_T_266, _T_260) node _T_268 = and(_T_220, _T_267) node _T_269 = or(UInt<1>(0h0), _T_268) node _T_270 = and(UInt<1>(0h0), _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_270, UInt<1>(0h1), "") : assert_11 node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_277 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_278 = asUInt(reset) node _T_279 = eq(_T_278, UInt<1>(0h0)) when _T_279 : node _T_280 = eq(_T_277, UInt<1>(0h0)) when _T_280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_277, UInt<1>(0h1), "") : assert_13 node _T_281 = asUInt(reset) node _T_282 = eq(_T_281, UInt<1>(0h0)) when _T_282 : node _T_283 = eq(is_aligned, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_284 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_284, UInt<1>(0h1), "") : assert_15 node _T_288 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_288, UInt<1>(0h1), "") : assert_16 node _T_292 = not(io.in.a.bits.mask) node _T_293 = eq(_T_292, UInt<1>(0h0)) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_293, UInt<1>(0h1), "") : assert_17 node _T_297 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(_T_297, UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_297, UInt<1>(0h1), "") : assert_18 node _T_301 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_301 : node _T_302 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_303 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_304 = and(_T_302, _T_303) node _T_305 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_306 = and(_T_304, _T_305) node _T_307 = or(UInt<1>(0h0), _T_306) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_307, UInt<1>(0h1), "") : assert_19 node _T_311 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_312 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_313 = and(_T_311, _T_312) node _T_314 = or(UInt<1>(0h0), _T_313) node _T_315 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<13>(0h1000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = and(_T_314, _T_319) node _T_321 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_322 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_323 = and(_T_321, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<14>(0h2000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_336 = cvt(_T_335) node _T_337 = and(_T_336, asSInt(UInt<18>(0h2f000))) node _T_338 = asSInt(_T_337) node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0))) node _T_340 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<13>(0h1000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<27>(0h4000000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<13>(0h1000))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = or(_T_329, _T_334) node _T_361 = or(_T_360, _T_339) node _T_362 = or(_T_361, _T_344) node _T_363 = or(_T_362, _T_349) node _T_364 = or(_T_363, _T_354) node _T_365 = or(_T_364, _T_359) node _T_366 = and(_T_324, _T_365) node _T_367 = or(UInt<1>(0h0), _T_320) node _T_368 = or(_T_367, _T_366) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_368, UInt<1>(0h1), "") : assert_20 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_378 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_378, UInt<1>(0h1), "") : assert_23 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_382, UInt<1>(0h1), "") : assert_24 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_386, UInt<1>(0h1), "") : assert_25 node _T_390 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_390 : node _T_391 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_392 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_395 = and(_T_393, _T_394) node _T_396 = or(UInt<1>(0h0), _T_395) node _T_397 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_398 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_399 = and(_T_397, _T_398) node _T_400 = or(UInt<1>(0h0), _T_399) node _T_401 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_402 = cvt(_T_401) node _T_403 = and(_T_402, asSInt(UInt<13>(0h1000))) node _T_404 = asSInt(_T_403) node _T_405 = eq(_T_404, asSInt(UInt<1>(0h0))) node _T_406 = and(_T_400, _T_405) node _T_407 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_408 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_409 = and(_T_407, _T_408) node _T_410 = or(UInt<1>(0h0), _T_409) node _T_411 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_412 = cvt(_T_411) node _T_413 = and(_T_412, asSInt(UInt<14>(0h2000))) node _T_414 = asSInt(_T_413) node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0))) node _T_416 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_417 = cvt(_T_416) node _T_418 = and(_T_417, asSInt(UInt<18>(0h2f000))) node _T_419 = asSInt(_T_418) node _T_420 = eq(_T_419, asSInt(UInt<1>(0h0))) node _T_421 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_422 = cvt(_T_421) node _T_423 = and(_T_422, asSInt(UInt<17>(0h10000))) node _T_424 = asSInt(_T_423) node _T_425 = eq(_T_424, asSInt(UInt<1>(0h0))) node _T_426 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_427 = cvt(_T_426) node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000))) node _T_429 = asSInt(_T_428) node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0))) node _T_431 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_432 = cvt(_T_431) node _T_433 = and(_T_432, asSInt(UInt<27>(0h4000000))) node _T_434 = asSInt(_T_433) node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0))) node _T_436 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<13>(0h1000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = or(_T_415, _T_420) node _T_442 = or(_T_441, _T_425) node _T_443 = or(_T_442, _T_430) node _T_444 = or(_T_443, _T_435) node _T_445 = or(_T_444, _T_440) node _T_446 = and(_T_410, _T_445) node _T_447 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_448 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_449 = cvt(_T_448) node _T_450 = and(_T_449, asSInt(UInt<17>(0h10000))) node _T_451 = asSInt(_T_450) node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0))) node _T_453 = and(_T_447, _T_452) node _T_454 = or(UInt<1>(0h0), _T_406) node _T_455 = or(_T_454, _T_446) node _T_456 = or(_T_455, _T_453) node _T_457 = and(_T_396, _T_456) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_457, UInt<1>(0h1), "") : assert_26 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(is_aligned, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_467 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_467, UInt<1>(0h1), "") : assert_29 node _T_471 = eq(io.in.a.bits.mask, mask) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_471, UInt<1>(0h1), "") : assert_30 node _T_475 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_475 : node _T_476 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_477 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_478 = and(_T_476, _T_477) node _T_479 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_480 = and(_T_478, _T_479) node _T_481 = or(UInt<1>(0h0), _T_480) node _T_482 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_483 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_484 = and(_T_482, _T_483) node _T_485 = or(UInt<1>(0h0), _T_484) node _T_486 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_487 = cvt(_T_486) node _T_488 = and(_T_487, asSInt(UInt<13>(0h1000))) node _T_489 = asSInt(_T_488) node _T_490 = eq(_T_489, asSInt(UInt<1>(0h0))) node _T_491 = and(_T_485, _T_490) node _T_492 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_493 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_494 = and(_T_492, _T_493) node _T_495 = or(UInt<1>(0h0), _T_494) node _T_496 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_497 = cvt(_T_496) node _T_498 = and(_T_497, asSInt(UInt<14>(0h2000))) node _T_499 = asSInt(_T_498) node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0))) node _T_501 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_502 = cvt(_T_501) node _T_503 = and(_T_502, asSInt(UInt<18>(0h2f000))) node _T_504 = asSInt(_T_503) node _T_505 = eq(_T_504, asSInt(UInt<1>(0h0))) node _T_506 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<17>(0h10000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<13>(0h1000))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<27>(0h4000000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<13>(0h1000))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = or(_T_500, _T_505) node _T_527 = or(_T_526, _T_510) node _T_528 = or(_T_527, _T_515) node _T_529 = or(_T_528, _T_520) node _T_530 = or(_T_529, _T_525) node _T_531 = and(_T_495, _T_530) node _T_532 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_533 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_534 = cvt(_T_533) node _T_535 = and(_T_534, asSInt(UInt<17>(0h10000))) node _T_536 = asSInt(_T_535) node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0))) node _T_538 = and(_T_532, _T_537) node _T_539 = or(UInt<1>(0h0), _T_491) node _T_540 = or(_T_539, _T_531) node _T_541 = or(_T_540, _T_538) node _T_542 = and(_T_481, _T_541) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_542, UInt<1>(0h1), "") : assert_31 node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(is_aligned, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_552 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_552, UInt<1>(0h1), "") : assert_34 node _T_556 = not(mask) node _T_557 = and(io.in.a.bits.mask, _T_556) node _T_558 = eq(_T_557, UInt<1>(0h0)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_558, UInt<1>(0h1), "") : assert_35 node _T_562 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_562 : node _T_563 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_564 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_565 = and(_T_563, _T_564) node _T_566 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_567 = and(_T_565, _T_566) node _T_568 = or(UInt<1>(0h0), _T_567) node _T_569 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_570 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_571 = and(_T_569, _T_570) node _T_572 = or(UInt<1>(0h0), _T_571) node _T_573 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_574 = cvt(_T_573) node _T_575 = and(_T_574, asSInt(UInt<14>(0h2000))) node _T_576 = asSInt(_T_575) node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0))) node _T_578 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<13>(0h1000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_584 = cvt(_T_583) node _T_585 = and(_T_584, asSInt(UInt<18>(0h2f000))) node _T_586 = asSInt(_T_585) node _T_587 = eq(_T_586, asSInt(UInt<1>(0h0))) node _T_588 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<17>(0h10000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_594 = cvt(_T_593) node _T_595 = and(_T_594, asSInt(UInt<13>(0h1000))) node _T_596 = asSInt(_T_595) node _T_597 = eq(_T_596, asSInt(UInt<1>(0h0))) node _T_598 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_599 = cvt(_T_598) node _T_600 = and(_T_599, asSInt(UInt<27>(0h4000000))) node _T_601 = asSInt(_T_600) node _T_602 = eq(_T_601, asSInt(UInt<1>(0h0))) node _T_603 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_604 = cvt(_T_603) node _T_605 = and(_T_604, asSInt(UInt<13>(0h1000))) node _T_606 = asSInt(_T_605) node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0))) node _T_608 = or(_T_577, _T_582) node _T_609 = or(_T_608, _T_587) node _T_610 = or(_T_609, _T_592) node _T_611 = or(_T_610, _T_597) node _T_612 = or(_T_611, _T_602) node _T_613 = or(_T_612, _T_607) node _T_614 = and(_T_572, _T_613) node _T_615 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_617 = cvt(_T_616) node _T_618 = and(_T_617, asSInt(UInt<17>(0h10000))) node _T_619 = asSInt(_T_618) node _T_620 = eq(_T_619, asSInt(UInt<1>(0h0))) node _T_621 = and(_T_615, _T_620) node _T_622 = or(UInt<1>(0h0), _T_614) node _T_623 = or(_T_622, _T_621) node _T_624 = and(_T_568, _T_623) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_624, UInt<1>(0h1), "") : assert_36 node _T_628 = asUInt(reset) node _T_629 = eq(_T_628, UInt<1>(0h0)) when _T_629 : node _T_630 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(is_aligned, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_634 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_634, UInt<1>(0h1), "") : assert_39 node _T_638 = eq(io.in.a.bits.mask, mask) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_638, UInt<1>(0h1), "") : assert_40 node _T_642 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_642 : node _T_643 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_644 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_645 = and(_T_643, _T_644) node _T_646 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_647 = and(_T_645, _T_646) node _T_648 = or(UInt<1>(0h0), _T_647) node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_650 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_651 = and(_T_649, _T_650) node _T_652 = or(UInt<1>(0h0), _T_651) node _T_653 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<14>(0h2000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<18>(0h2f000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<17>(0h10000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<13>(0h1000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<27>(0h4000000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = or(_T_657, _T_662) node _T_689 = or(_T_688, _T_667) node _T_690 = or(_T_689, _T_672) node _T_691 = or(_T_690, _T_677) node _T_692 = or(_T_691, _T_682) node _T_693 = or(_T_692, _T_687) node _T_694 = and(_T_652, _T_693) node _T_695 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_696 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_697 = cvt(_T_696) node _T_698 = and(_T_697, asSInt(UInt<17>(0h10000))) node _T_699 = asSInt(_T_698) node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0))) node _T_701 = and(_T_695, _T_700) node _T_702 = or(UInt<1>(0h0), _T_694) node _T_703 = or(_T_702, _T_701) node _T_704 = and(_T_648, _T_703) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_704, UInt<1>(0h1), "") : assert_41 node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_711 = asUInt(reset) node _T_712 = eq(_T_711, UInt<1>(0h0)) when _T_712 : node _T_713 = eq(is_aligned, UInt<1>(0h0)) when _T_713 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_714 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(_T_714, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_714, UInt<1>(0h1), "") : assert_44 node _T_718 = eq(io.in.a.bits.mask, mask) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_718, UInt<1>(0h1), "") : assert_45 node _T_722 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_722 : node _T_723 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_724 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_725 = and(_T_723, _T_724) node _T_726 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_727 = and(_T_725, _T_726) node _T_728 = or(UInt<1>(0h0), _T_727) node _T_729 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_730 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_731 = and(_T_729, _T_730) node _T_732 = or(UInt<1>(0h0), _T_731) node _T_733 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = and(_T_732, _T_737) node _T_739 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_740 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_741 = cvt(_T_740) node _T_742 = and(_T_741, asSInt(UInt<14>(0h2000))) node _T_743 = asSInt(_T_742) node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0))) node _T_745 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_746 = cvt(_T_745) node _T_747 = and(_T_746, asSInt(UInt<17>(0h10000))) node _T_748 = asSInt(_T_747) node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0))) node _T_750 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_751 = cvt(_T_750) node _T_752 = and(_T_751, asSInt(UInt<18>(0h2f000))) node _T_753 = asSInt(_T_752) node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0))) node _T_755 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<17>(0h10000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<27>(0h4000000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<13>(0h1000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = or(_T_744, _T_749) node _T_776 = or(_T_775, _T_754) node _T_777 = or(_T_776, _T_759) node _T_778 = or(_T_777, _T_764) node _T_779 = or(_T_778, _T_769) node _T_780 = or(_T_779, _T_774) node _T_781 = and(_T_739, _T_780) node _T_782 = or(UInt<1>(0h0), _T_738) node _T_783 = or(_T_782, _T_781) node _T_784 = and(_T_728, _T_783) node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(_T_784, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_784, UInt<1>(0h1), "") : assert_46 node _T_788 = asUInt(reset) node _T_789 = eq(_T_788, UInt<1>(0h0)) when _T_789 : node _T_790 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(is_aligned, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_794 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(_T_794, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_794, UInt<1>(0h1), "") : assert_49 node _T_798 = eq(io.in.a.bits.mask, mask) node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(_T_798, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_798, UInt<1>(0h1), "") : assert_50 node _T_802 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_803 = asUInt(reset) node _T_804 = eq(_T_803, UInt<1>(0h0)) when _T_804 : node _T_805 = eq(_T_802, UInt<1>(0h0)) when _T_805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_802, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_806 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(_T_806, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_806, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_810 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_810 : node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_814 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_814, UInt<1>(0h1), "") : assert_54 node _T_818 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_818, UInt<1>(0h1), "") : assert_55 node _T_822 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_822, UInt<1>(0h1), "") : assert_56 node _T_826 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_826, UInt<1>(0h1), "") : assert_57 node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_834 = asUInt(reset) node _T_835 = eq(_T_834, UInt<1>(0h0)) when _T_835 : node _T_836 = eq(sink_ok, UInt<1>(0h0)) when _T_836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_837 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_837, UInt<1>(0h1), "") : assert_60 node _T_841 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_842 = asUInt(reset) node _T_843 = eq(_T_842, UInt<1>(0h0)) when _T_843 : node _T_844 = eq(_T_841, UInt<1>(0h0)) when _T_844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_841, UInt<1>(0h1), "") : assert_61 node _T_845 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(_T_845, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_845, UInt<1>(0h1), "") : assert_62 node _T_849 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_850 = asUInt(reset) node _T_851 = eq(_T_850, UInt<1>(0h0)) when _T_851 : node _T_852 = eq(_T_849, UInt<1>(0h0)) when _T_852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_849, UInt<1>(0h1), "") : assert_63 node _T_853 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_854 = or(UInt<1>(0h1), _T_853) node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(_T_854, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_854, UInt<1>(0h1), "") : assert_64 node _T_858 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_858 : node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(sink_ok, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_865 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_865, UInt<1>(0h1), "") : assert_67 node _T_869 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_869, UInt<1>(0h1), "") : assert_68 node _T_873 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_873, UInt<1>(0h1), "") : assert_69 node _T_877 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_878 = or(_T_877, io.in.d.bits.corrupt) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_878, UInt<1>(0h1), "") : assert_70 node _T_882 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_883 = or(UInt<1>(0h1), _T_882) node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(_T_883, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_883, UInt<1>(0h1), "") : assert_71 node _T_887 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_887 : node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_891 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_892 = asUInt(reset) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(_T_891, UInt<1>(0h0)) when _T_894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_891, UInt<1>(0h1), "") : assert_73 node _T_895 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(_T_895, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_895, UInt<1>(0h1), "") : assert_74 node _T_899 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_900 = or(UInt<1>(0h1), _T_899) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_900, UInt<1>(0h1), "") : assert_75 node _T_904 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_904 : node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_908 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(_T_908, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_908, UInt<1>(0h1), "") : assert_77 node _T_912 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_913 = or(_T_912, io.in.d.bits.corrupt) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_913, UInt<1>(0h1), "") : assert_78 node _T_917 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_918 = or(UInt<1>(0h1), _T_917) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_918, UInt<1>(0h1), "") : assert_79 node _T_922 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_922 : node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_926 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(_T_926, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_926, UInt<1>(0h1), "") : assert_81 node _T_930 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_930, UInt<1>(0h1), "") : assert_82 node _T_934 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_935 = or(UInt<1>(0h1), _T_934) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_935, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_939 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_939, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_943 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_943, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_947 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_947, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_951 = eq(a_first, UInt<1>(0h0)) node _T_952 = and(io.in.a.valid, _T_951) when _T_952 : node _T_953 = eq(io.in.a.bits.opcode, opcode) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_953, UInt<1>(0h1), "") : assert_87 node _T_957 = eq(io.in.a.bits.param, param) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_957, UInt<1>(0h1), "") : assert_88 node _T_961 = eq(io.in.a.bits.size, size) node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_T_961, UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_961, UInt<1>(0h1), "") : assert_89 node _T_965 = eq(io.in.a.bits.source, source) node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(_T_965, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_965, UInt<1>(0h1), "") : assert_90 node _T_969 = eq(io.in.a.bits.address, address) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_969, UInt<1>(0h1), "") : assert_91 node _T_973 = and(io.in.a.ready, io.in.a.valid) node _T_974 = and(_T_973, a_first) when _T_974 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_975 = eq(d_first, UInt<1>(0h0)) node _T_976 = and(io.in.d.valid, _T_975) when _T_976 : node _T_977 = eq(io.in.d.bits.opcode, opcode_1) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_977, UInt<1>(0h1), "") : assert_92 node _T_981 = eq(io.in.d.bits.param, param_1) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_981, UInt<1>(0h1), "") : assert_93 node _T_985 = eq(io.in.d.bits.size, size_1) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_985, UInt<1>(0h1), "") : assert_94 node _T_989 = eq(io.in.d.bits.source, source_1) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_989, UInt<1>(0h1), "") : assert_95 node _T_993 = eq(io.in.d.bits.sink, sink) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_993, UInt<1>(0h1), "") : assert_96 node _T_997 = eq(io.in.d.bits.denied, denied) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_997, UInt<1>(0h1), "") : assert_97 node _T_1001 = and(io.in.d.ready, io.in.d.valid) node _T_1002 = and(_T_1001, d_first) when _T_1002 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1003 = and(io.in.a.valid, a_first_1) node _T_1004 = and(_T_1003, UInt<1>(0h1)) when _T_1004 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1005 = and(io.in.a.ready, io.in.a.valid) node _T_1006 = and(_T_1005, a_first_1) node _T_1007 = and(_T_1006, UInt<1>(0h1)) when _T_1007 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1008 = dshr(inflight, io.in.a.bits.source) node _T_1009 = bits(_T_1008, 0, 0) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1014 = and(io.in.d.valid, d_first_1) node _T_1015 = and(_T_1014, UInt<1>(0h1)) node _T_1016 = eq(d_release_ack, UInt<1>(0h0)) node _T_1017 = and(_T_1015, _T_1016) when _T_1017 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1018 = and(io.in.d.ready, io.in.d.valid) node _T_1019 = and(_T_1018, d_first_1) node _T_1020 = and(_T_1019, UInt<1>(0h1)) node _T_1021 = eq(d_release_ack, UInt<1>(0h0)) node _T_1022 = and(_T_1020, _T_1021) when _T_1022 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1023 = and(io.in.d.valid, d_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) node _T_1025 = eq(d_release_ack, UInt<1>(0h0)) node _T_1026 = and(_T_1024, _T_1025) when _T_1026 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1027 = dshr(inflight, io.in.d.bits.source) node _T_1028 = bits(_T_1027, 0, 0) node _T_1029 = or(_T_1028, same_cycle_resp) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1033 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1034 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1035 = or(_T_1033, _T_1034) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_100 node _T_1039 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_101 else : node _T_1043 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1044 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1045 = or(_T_1043, _T_1044) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_102 node _T_1049 = eq(io.in.d.bits.size, a_size_lookup) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_103 node _T_1053 = and(io.in.d.valid, d_first_1) node _T_1054 = and(_T_1053, a_first_1) node _T_1055 = and(_T_1054, io.in.a.valid) node _T_1056 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1057 = and(_T_1055, _T_1056) node _T_1058 = eq(d_release_ack, UInt<1>(0h0)) node _T_1059 = and(_T_1057, _T_1058) when _T_1059 : node _T_1060 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1061 = or(_T_1060, io.in.a.ready) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_104 node _T_1065 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1066 = orr(a_set_wo_ready) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) node _T_1068 = or(_T_1065, _T_1067) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_34 node _T_1072 = orr(inflight) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) node _T_1074 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1075 = or(_T_1073, _T_1074) node _T_1076 = lt(watchdog, plusarg_reader.out) node _T_1077 = or(_T_1075, _T_1076) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1081 = and(io.in.a.ready, io.in.a.valid) node _T_1082 = and(io.in.d.ready, io.in.d.valid) node _T_1083 = or(_T_1081, _T_1082) when _T_1083 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1084 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1085 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1086 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1087 = and(_T_1085, _T_1086) node _T_1088 = and(_T_1084, _T_1087) when _T_1088 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1089 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1090 = and(_T_1089, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1091 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1092 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1093 = and(_T_1091, _T_1092) node _T_1094 = and(_T_1090, _T_1093) when _T_1094 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1095 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1096 = bits(_T_1095, 0, 0) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1101 = and(io.in.d.valid, d_first_2) node _T_1102 = and(_T_1101, UInt<1>(0h1)) node _T_1103 = and(_T_1102, d_release_ack_1) when _T_1103 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1104 = and(io.in.d.ready, io.in.d.valid) node _T_1105 = and(_T_1104, d_first_2) node _T_1106 = and(_T_1105, UInt<1>(0h1)) node _T_1107 = and(_T_1106, d_release_ack_1) when _T_1107 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1108 = and(io.in.d.valid, d_first_2) node _T_1109 = and(_T_1108, UInt<1>(0h1)) node _T_1110 = and(_T_1109, d_release_ack_1) when _T_1110 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1111 = dshr(inflight_1, io.in.d.bits.source) node _T_1112 = bits(_T_1111, 0, 0) node _T_1113 = or(_T_1112, same_cycle_resp_1) node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_T_1113, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1113, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1117 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_109 else : node _T_1121 = eq(io.in.d.bits.size, c_size_lookup) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_110 node _T_1125 = and(io.in.d.valid, d_first_2) node _T_1126 = and(_T_1125, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1127 = and(_T_1126, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1128 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1129 = and(_T_1127, _T_1128) node _T_1130 = and(_T_1129, d_release_ack_1) node _T_1131 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1132 = and(_T_1130, _T_1131) when _T_1132 : node _T_1133 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1134 = or(_T_1133, _WIRE_23.ready) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_111 node _T_1138 = orr(c_set_wo_ready) when _T_1138 : node _T_1139 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_35 node _T_1143 = orr(inflight_1) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) node _T_1145 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1146 = or(_T_1144, _T_1145) node _T_1147 = lt(watchdog_1, plusarg_reader_1.out) node _T_1148 = or(_T_1146, _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1152 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1153 = and(io.in.d.ready, io.in.d.valid) node _T_1154 = or(_T_1152, _T_1153) when _T_1154 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_17( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h0; // @[Edges.scala:92:37] wire _a_first_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:92:37] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire a_first_beats1_opdata = 1'h1; // @[Edges.scala:92:28] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire a_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:92:28] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] a_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] a_first_beats1_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h2; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_opcode = 3'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [7:0] io_in_a_bits_mask = 8'hF; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:657:53] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:657:61] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [4:0] _a_sizes_set_interm_T_1 = 5'h5; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'h4; // @[Monitor.scala:658:51] wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [11:0] is_aligned_mask = 12'h3; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFFC; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFFC; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFFC; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC; // @[package.scala:243:71] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [28:0] _is_aligned_T = {27'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_0_1 = _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_0_1 = mask_sub_sub_0_1; // @[Misc.scala:215:29] wire mask_sub_1_1 = mask_sub_sub_0_1; // @[Misc.scala:215:29] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_1 = _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_1 = mask_sub_sub_1_1; // @[Misc.scala:215:29] wire mask_sub_3_1 = mask_sub_sub_1_1; // @[Misc.scala:215:29] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1081 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1081; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1081; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [28:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1004 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1004; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1004; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1081 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = {3'h0, a_set}; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'h5 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1053 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1053 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1125 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1125 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_16 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, clock inst q of Queue3_EgressFlit_16 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h9), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_16 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h3), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_17 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h0), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_18 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0hc), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_19 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h6), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_20 = or(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_21 = or(_q_io_enq_bits_ingress_id_T_20, _q_io_enq_bits_ingress_id_T_17) node _q_io_enq_bits_ingress_id_T_22 = or(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_18) node _q_io_enq_bits_ingress_id_T_23 = or(_q_io_enq_bits_ingress_id_T_22, _q_io_enq_bits_ingress_id_T_19) wire _q_io_enq_bits_ingress_id_WIRE : UInt<5> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_23 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow
module EgressUnit_16( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 3'h0; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_53 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_107 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_108 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_53( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_14 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) wire _source_ok_WIRE : UInt<1>[7] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 node _source_ok_T_27 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_28 = or(_source_ok_T_27, _source_ok_WIRE[2]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[3]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[4]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[5]) node source_ok = or(_source_ok_T_31, _source_ok_WIRE[6]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = and(_T_11, _T_24) node _T_81 = and(_T_80, _T_37) node _T_82 = and(_T_81, _T_50) node _T_83 = and(_T_82, _T_63) node _T_84 = and(_T_83, _T_71) node _T_85 = and(_T_84, _T_79) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_85, UInt<1>(0h1), "") : assert_1 node _T_89 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_89 : node _T_90 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_91 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_92 = and(_T_90, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_94 = shr(io.in.a.bits.source, 2) node _T_95 = eq(_T_94, UInt<1>(0h0)) node _T_96 = leq(UInt<1>(0h0), uncommonBits_4) node _T_97 = and(_T_95, _T_96) node _T_98 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_99 = and(_T_97, _T_98) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_100 = shr(io.in.a.bits.source, 2) node _T_101 = eq(_T_100, UInt<1>(0h1)) node _T_102 = leq(UInt<1>(0h0), uncommonBits_5) node _T_103 = and(_T_101, _T_102) node _T_104 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_105 = and(_T_103, _T_104) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_106 = shr(io.in.a.bits.source, 2) node _T_107 = eq(_T_106, UInt<2>(0h2)) node _T_108 = leq(UInt<1>(0h0), uncommonBits_6) node _T_109 = and(_T_107, _T_108) node _T_110 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_111 = and(_T_109, _T_110) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<2>(0h3)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_7) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_119 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_120 = or(_T_93, _T_99) node _T_121 = or(_T_120, _T_105) node _T_122 = or(_T_121, _T_111) node _T_123 = or(_T_122, _T_117) node _T_124 = or(_T_123, _T_118) node _T_125 = or(_T_124, _T_119) node _T_126 = and(_T_92, _T_125) node _T_127 = or(UInt<1>(0h0), _T_126) node _T_128 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_129 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_130 = cvt(_T_129) node _T_131 = and(_T_130, asSInt(UInt<14>(0h2000))) node _T_132 = asSInt(_T_131) node _T_133 = eq(_T_132, asSInt(UInt<1>(0h0))) node _T_134 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<13>(0h1000))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<17>(0h10000))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<18>(0h2f000))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<12>(0h800))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<16>(0h8000))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<17>(0h10000))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<13>(0h1000))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_170 = cvt(_T_169) node _T_171 = and(_T_170, asSInt(UInt<27>(0h4000000))) node _T_172 = asSInt(_T_171) node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0))) node _T_174 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_175 = cvt(_T_174) node _T_176 = and(_T_175, asSInt(UInt<13>(0h1000))) node _T_177 = asSInt(_T_176) node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0))) node _T_179 = or(_T_133, _T_138) node _T_180 = or(_T_179, _T_143) node _T_181 = or(_T_180, _T_148) node _T_182 = or(_T_181, _T_153) node _T_183 = or(_T_182, _T_158) node _T_184 = or(_T_183, _T_163) node _T_185 = or(_T_184, _T_168) node _T_186 = or(_T_185, _T_173) node _T_187 = or(_T_186, _T_178) node _T_188 = and(_T_128, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = and(_T_127, _T_189) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_190, UInt<1>(0h1), "") : assert_2 node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _T_197 = or(UInt<1>(0h0), _T_196) node _T_198 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_199 = cvt(_T_198) node _T_200 = and(_T_199, asSInt(UInt<14>(0h2000))) node _T_201 = asSInt(_T_200) node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0))) node _T_203 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<13>(0h1000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<17>(0h10000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<18>(0h2f000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<12>(0h800))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_224 = cvt(_T_223) node _T_225 = and(_T_224, asSInt(UInt<16>(0h8000))) node _T_226 = asSInt(_T_225) node _T_227 = eq(_T_226, asSInt(UInt<1>(0h0))) node _T_228 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<17>(0h10000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_234 = cvt(_T_233) node _T_235 = and(_T_234, asSInt(UInt<13>(0h1000))) node _T_236 = asSInt(_T_235) node _T_237 = eq(_T_236, asSInt(UInt<1>(0h0))) node _T_238 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_239 = cvt(_T_238) node _T_240 = and(_T_239, asSInt(UInt<27>(0h4000000))) node _T_241 = asSInt(_T_240) node _T_242 = eq(_T_241, asSInt(UInt<1>(0h0))) node _T_243 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_244 = cvt(_T_243) node _T_245 = and(_T_244, asSInt(UInt<13>(0h1000))) node _T_246 = asSInt(_T_245) node _T_247 = eq(_T_246, asSInt(UInt<1>(0h0))) node _T_248 = or(_T_202, _T_207) node _T_249 = or(_T_248, _T_212) node _T_250 = or(_T_249, _T_217) node _T_251 = or(_T_250, _T_222) node _T_252 = or(_T_251, _T_227) node _T_253 = or(_T_252, _T_232) node _T_254 = or(_T_253, _T_237) node _T_255 = or(_T_254, _T_242) node _T_256 = or(_T_255, _T_247) node _T_257 = and(_T_197, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(UInt<1>(0h0), _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_259, UInt<1>(0h1), "") : assert_3 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(source_ok, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_266 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_267 = asUInt(reset) node _T_268 = eq(_T_267, UInt<1>(0h0)) when _T_268 : node _T_269 = eq(_T_266, UInt<1>(0h0)) when _T_269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_266, UInt<1>(0h1), "") : assert_5 node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(is_aligned, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_273 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(_T_273, UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_273, UInt<1>(0h1), "") : assert_7 node _T_277 = not(io.in.a.bits.mask) node _T_278 = eq(_T_277, UInt<1>(0h0)) node _T_279 = asUInt(reset) node _T_280 = eq(_T_279, UInt<1>(0h0)) when _T_280 : node _T_281 = eq(_T_278, UInt<1>(0h0)) when _T_281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_278, UInt<1>(0h1), "") : assert_8 node _T_282 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_283 = asUInt(reset) node _T_284 = eq(_T_283, UInt<1>(0h0)) when _T_284 : node _T_285 = eq(_T_282, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_282, UInt<1>(0h1), "") : assert_9 node _T_286 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_286 : node _T_287 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_288 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_289 = and(_T_287, _T_288) node _T_290 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_291 = shr(io.in.a.bits.source, 2) node _T_292 = eq(_T_291, UInt<1>(0h0)) node _T_293 = leq(UInt<1>(0h0), uncommonBits_8) node _T_294 = and(_T_292, _T_293) node _T_295 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_296 = and(_T_294, _T_295) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_297 = shr(io.in.a.bits.source, 2) node _T_298 = eq(_T_297, UInt<1>(0h1)) node _T_299 = leq(UInt<1>(0h0), uncommonBits_9) node _T_300 = and(_T_298, _T_299) node _T_301 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_302 = and(_T_300, _T_301) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<2>(0h2)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_10) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<2>(0h3)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_11) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_316 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_317 = or(_T_290, _T_296) node _T_318 = or(_T_317, _T_302) node _T_319 = or(_T_318, _T_308) node _T_320 = or(_T_319, _T_314) node _T_321 = or(_T_320, _T_315) node _T_322 = or(_T_321, _T_316) node _T_323 = and(_T_289, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<14>(0h2000))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<13>(0h1000))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<17>(0h10000))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<18>(0h2f000))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<12>(0h800))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<16>(0h8000))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_357 = cvt(_T_356) node _T_358 = and(_T_357, asSInt(UInt<17>(0h10000))) node _T_359 = asSInt(_T_358) node _T_360 = eq(_T_359, asSInt(UInt<1>(0h0))) node _T_361 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_362 = cvt(_T_361) node _T_363 = and(_T_362, asSInt(UInt<13>(0h1000))) node _T_364 = asSInt(_T_363) node _T_365 = eq(_T_364, asSInt(UInt<1>(0h0))) node _T_366 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_367 = cvt(_T_366) node _T_368 = and(_T_367, asSInt(UInt<27>(0h4000000))) node _T_369 = asSInt(_T_368) node _T_370 = eq(_T_369, asSInt(UInt<1>(0h0))) node _T_371 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_372 = cvt(_T_371) node _T_373 = and(_T_372, asSInt(UInt<13>(0h1000))) node _T_374 = asSInt(_T_373) node _T_375 = eq(_T_374, asSInt(UInt<1>(0h0))) node _T_376 = or(_T_330, _T_335) node _T_377 = or(_T_376, _T_340) node _T_378 = or(_T_377, _T_345) node _T_379 = or(_T_378, _T_350) node _T_380 = or(_T_379, _T_355) node _T_381 = or(_T_380, _T_360) node _T_382 = or(_T_381, _T_365) node _T_383 = or(_T_382, _T_370) node _T_384 = or(_T_383, _T_375) node _T_385 = and(_T_325, _T_384) node _T_386 = or(UInt<1>(0h0), _T_385) node _T_387 = and(_T_324, _T_386) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_387, UInt<1>(0h1), "") : assert_10 node _T_391 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_392 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_393 = and(_T_391, _T_392) node _T_394 = or(UInt<1>(0h0), _T_393) node _T_395 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_396 = cvt(_T_395) node _T_397 = and(_T_396, asSInt(UInt<14>(0h2000))) node _T_398 = asSInt(_T_397) node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0))) node _T_400 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_401 = cvt(_T_400) node _T_402 = and(_T_401, asSInt(UInt<13>(0h1000))) node _T_403 = asSInt(_T_402) node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0))) node _T_405 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_406 = cvt(_T_405) node _T_407 = and(_T_406, asSInt(UInt<17>(0h10000))) node _T_408 = asSInt(_T_407) node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0))) node _T_410 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_411 = cvt(_T_410) node _T_412 = and(_T_411, asSInt(UInt<18>(0h2f000))) node _T_413 = asSInt(_T_412) node _T_414 = eq(_T_413, asSInt(UInt<1>(0h0))) node _T_415 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_416 = cvt(_T_415) node _T_417 = and(_T_416, asSInt(UInt<12>(0h800))) node _T_418 = asSInt(_T_417) node _T_419 = eq(_T_418, asSInt(UInt<1>(0h0))) node _T_420 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_421 = cvt(_T_420) node _T_422 = and(_T_421, asSInt(UInt<16>(0h8000))) node _T_423 = asSInt(_T_422) node _T_424 = eq(_T_423, asSInt(UInt<1>(0h0))) node _T_425 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_426 = cvt(_T_425) node _T_427 = and(_T_426, asSInt(UInt<17>(0h10000))) node _T_428 = asSInt(_T_427) node _T_429 = eq(_T_428, asSInt(UInt<1>(0h0))) node _T_430 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_431 = cvt(_T_430) node _T_432 = and(_T_431, asSInt(UInt<13>(0h1000))) node _T_433 = asSInt(_T_432) node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0))) node _T_435 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_436 = cvt(_T_435) node _T_437 = and(_T_436, asSInt(UInt<27>(0h4000000))) node _T_438 = asSInt(_T_437) node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0))) node _T_440 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_441 = cvt(_T_440) node _T_442 = and(_T_441, asSInt(UInt<13>(0h1000))) node _T_443 = asSInt(_T_442) node _T_444 = eq(_T_443, asSInt(UInt<1>(0h0))) node _T_445 = or(_T_399, _T_404) node _T_446 = or(_T_445, _T_409) node _T_447 = or(_T_446, _T_414) node _T_448 = or(_T_447, _T_419) node _T_449 = or(_T_448, _T_424) node _T_450 = or(_T_449, _T_429) node _T_451 = or(_T_450, _T_434) node _T_452 = or(_T_451, _T_439) node _T_453 = or(_T_452, _T_444) node _T_454 = and(_T_394, _T_453) node _T_455 = or(UInt<1>(0h0), _T_454) node _T_456 = and(UInt<1>(0h0), _T_455) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_456, UInt<1>(0h1), "") : assert_11 node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(source_ok, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_463 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_463, UInt<1>(0h1), "") : assert_13 node _T_467 = asUInt(reset) node _T_468 = eq(_T_467, UInt<1>(0h0)) when _T_468 : node _T_469 = eq(is_aligned, UInt<1>(0h0)) when _T_469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_470 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_471 = asUInt(reset) node _T_472 = eq(_T_471, UInt<1>(0h0)) when _T_472 : node _T_473 = eq(_T_470, UInt<1>(0h0)) when _T_473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_470, UInt<1>(0h1), "") : assert_15 node _T_474 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_474, UInt<1>(0h1), "") : assert_16 node _T_478 = not(io.in.a.bits.mask) node _T_479 = eq(_T_478, UInt<1>(0h0)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_479, UInt<1>(0h1), "") : assert_17 node _T_483 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(_T_483, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_483, UInt<1>(0h1), "") : assert_18 node _T_487 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_487 : node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<1>(0h0)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_12) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_498 = shr(io.in.a.bits.source, 2) node _T_499 = eq(_T_498, UInt<1>(0h1)) node _T_500 = leq(UInt<1>(0h0), uncommonBits_13) node _T_501 = and(_T_499, _T_500) node _T_502 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_503 = and(_T_501, _T_502) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_504 = shr(io.in.a.bits.source, 2) node _T_505 = eq(_T_504, UInt<2>(0h2)) node _T_506 = leq(UInt<1>(0h0), uncommonBits_14) node _T_507 = and(_T_505, _T_506) node _T_508 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_509 = and(_T_507, _T_508) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_510 = shr(io.in.a.bits.source, 2) node _T_511 = eq(_T_510, UInt<2>(0h3)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_15) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_517 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_518 = or(_T_491, _T_497) node _T_519 = or(_T_518, _T_503) node _T_520 = or(_T_519, _T_509) node _T_521 = or(_T_520, _T_515) node _T_522 = or(_T_521, _T_516) node _T_523 = or(_T_522, _T_517) node _T_524 = and(_T_490, _T_523) node _T_525 = or(UInt<1>(0h0), _T_524) node _T_526 = asUInt(reset) node _T_527 = eq(_T_526, UInt<1>(0h0)) when _T_527 : node _T_528 = eq(_T_525, UInt<1>(0h0)) when _T_528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_525, UInt<1>(0h1), "") : assert_19 node _T_529 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_530 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_531 = and(_T_529, _T_530) node _T_532 = or(UInt<1>(0h0), _T_531) node _T_533 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_534 = cvt(_T_533) node _T_535 = and(_T_534, asSInt(UInt<13>(0h1000))) node _T_536 = asSInt(_T_535) node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0))) node _T_538 = and(_T_532, _T_537) node _T_539 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_540 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_541 = and(_T_539, _T_540) node _T_542 = or(UInt<1>(0h0), _T_541) node _T_543 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_544 = cvt(_T_543) node _T_545 = and(_T_544, asSInt(UInt<14>(0h2000))) node _T_546 = asSInt(_T_545) node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0))) node _T_548 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_549 = cvt(_T_548) node _T_550 = and(_T_549, asSInt(UInt<17>(0h10000))) node _T_551 = asSInt(_T_550) node _T_552 = eq(_T_551, asSInt(UInt<1>(0h0))) node _T_553 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_554 = cvt(_T_553) node _T_555 = and(_T_554, asSInt(UInt<18>(0h2f000))) node _T_556 = asSInt(_T_555) node _T_557 = eq(_T_556, asSInt(UInt<1>(0h0))) node _T_558 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_559 = cvt(_T_558) node _T_560 = and(_T_559, asSInt(UInt<12>(0h800))) node _T_561 = asSInt(_T_560) node _T_562 = eq(_T_561, asSInt(UInt<1>(0h0))) node _T_563 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_564 = cvt(_T_563) node _T_565 = and(_T_564, asSInt(UInt<16>(0h8000))) node _T_566 = asSInt(_T_565) node _T_567 = eq(_T_566, asSInt(UInt<1>(0h0))) node _T_568 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_569 = cvt(_T_568) node _T_570 = and(_T_569, asSInt(UInt<17>(0h10000))) node _T_571 = asSInt(_T_570) node _T_572 = eq(_T_571, asSInt(UInt<1>(0h0))) node _T_573 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_574 = cvt(_T_573) node _T_575 = and(_T_574, asSInt(UInt<13>(0h1000))) node _T_576 = asSInt(_T_575) node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0))) node _T_578 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<27>(0h4000000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_584 = cvt(_T_583) node _T_585 = and(_T_584, asSInt(UInt<13>(0h1000))) node _T_586 = asSInt(_T_585) node _T_587 = eq(_T_586, asSInt(UInt<1>(0h0))) node _T_588 = or(_T_547, _T_552) node _T_589 = or(_T_588, _T_557) node _T_590 = or(_T_589, _T_562) node _T_591 = or(_T_590, _T_567) node _T_592 = or(_T_591, _T_572) node _T_593 = or(_T_592, _T_577) node _T_594 = or(_T_593, _T_582) node _T_595 = or(_T_594, _T_587) node _T_596 = and(_T_542, _T_595) node _T_597 = or(UInt<1>(0h0), _T_538) node _T_598 = or(_T_597, _T_596) node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(_T_598, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_598, UInt<1>(0h1), "") : assert_20 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(source_ok, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(is_aligned, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_608 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_608, UInt<1>(0h1), "") : assert_23 node _T_612 = eq(io.in.a.bits.mask, mask) node _T_613 = asUInt(reset) node _T_614 = eq(_T_613, UInt<1>(0h0)) when _T_614 : node _T_615 = eq(_T_612, UInt<1>(0h0)) when _T_615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_612, UInt<1>(0h1), "") : assert_24 node _T_616 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_617 = asUInt(reset) node _T_618 = eq(_T_617, UInt<1>(0h0)) when _T_618 : node _T_619 = eq(_T_616, UInt<1>(0h0)) when _T_619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_616, UInt<1>(0h1), "") : assert_25 node _T_620 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_620 : node _T_621 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_622 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_623 = and(_T_621, _T_622) node _T_624 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_625 = shr(io.in.a.bits.source, 2) node _T_626 = eq(_T_625, UInt<1>(0h0)) node _T_627 = leq(UInt<1>(0h0), uncommonBits_16) node _T_628 = and(_T_626, _T_627) node _T_629 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_630 = and(_T_628, _T_629) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_631 = shr(io.in.a.bits.source, 2) node _T_632 = eq(_T_631, UInt<1>(0h1)) node _T_633 = leq(UInt<1>(0h0), uncommonBits_17) node _T_634 = and(_T_632, _T_633) node _T_635 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_636 = and(_T_634, _T_635) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_637 = shr(io.in.a.bits.source, 2) node _T_638 = eq(_T_637, UInt<2>(0h2)) node _T_639 = leq(UInt<1>(0h0), uncommonBits_18) node _T_640 = and(_T_638, _T_639) node _T_641 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_642 = and(_T_640, _T_641) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_643 = shr(io.in.a.bits.source, 2) node _T_644 = eq(_T_643, UInt<2>(0h3)) node _T_645 = leq(UInt<1>(0h0), uncommonBits_19) node _T_646 = and(_T_644, _T_645) node _T_647 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_650 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_651 = or(_T_624, _T_630) node _T_652 = or(_T_651, _T_636) node _T_653 = or(_T_652, _T_642) node _T_654 = or(_T_653, _T_648) node _T_655 = or(_T_654, _T_649) node _T_656 = or(_T_655, _T_650) node _T_657 = and(_T_623, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<13>(0h1000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = and(_T_662, _T_667) node _T_669 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_670 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_671 = and(_T_669, _T_670) node _T_672 = or(UInt<1>(0h0), _T_671) node _T_673 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<14>(0h2000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<18>(0h2f000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<12>(0h800))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<16>(0h8000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<17>(0h10000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<27>(0h4000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<13>(0h1000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = or(_T_677, _T_682) node _T_714 = or(_T_713, _T_687) node _T_715 = or(_T_714, _T_692) node _T_716 = or(_T_715, _T_697) node _T_717 = or(_T_716, _T_702) node _T_718 = or(_T_717, _T_707) node _T_719 = or(_T_718, _T_712) node _T_720 = and(_T_672, _T_719) node _T_721 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_722 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_723 = cvt(_T_722) node _T_724 = and(_T_723, asSInt(UInt<17>(0h10000))) node _T_725 = asSInt(_T_724) node _T_726 = eq(_T_725, asSInt(UInt<1>(0h0))) node _T_727 = and(_T_721, _T_726) node _T_728 = or(UInt<1>(0h0), _T_668) node _T_729 = or(_T_728, _T_720) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_731, UInt<1>(0h1), "") : assert_26 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(source_ok, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_741 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_741, UInt<1>(0h1), "") : assert_29 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_745, UInt<1>(0h1), "") : assert_30 node _T_749 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_754 = shr(io.in.a.bits.source, 2) node _T_755 = eq(_T_754, UInt<1>(0h0)) node _T_756 = leq(UInt<1>(0h0), uncommonBits_20) node _T_757 = and(_T_755, _T_756) node _T_758 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_759 = and(_T_757, _T_758) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_760 = shr(io.in.a.bits.source, 2) node _T_761 = eq(_T_760, UInt<1>(0h1)) node _T_762 = leq(UInt<1>(0h0), uncommonBits_21) node _T_763 = and(_T_761, _T_762) node _T_764 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_765 = and(_T_763, _T_764) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_766 = shr(io.in.a.bits.source, 2) node _T_767 = eq(_T_766, UInt<2>(0h2)) node _T_768 = leq(UInt<1>(0h0), uncommonBits_22) node _T_769 = and(_T_767, _T_768) node _T_770 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_771 = and(_T_769, _T_770) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<2>(0h3)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_23) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_779 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_780 = or(_T_753, _T_759) node _T_781 = or(_T_780, _T_765) node _T_782 = or(_T_781, _T_771) node _T_783 = or(_T_782, _T_777) node _T_784 = or(_T_783, _T_778) node _T_785 = or(_T_784, _T_779) node _T_786 = and(_T_752, _T_785) node _T_787 = or(UInt<1>(0h0), _T_786) node _T_788 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_789 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_790 = and(_T_788, _T_789) node _T_791 = or(UInt<1>(0h0), _T_790) node _T_792 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_793 = cvt(_T_792) node _T_794 = and(_T_793, asSInt(UInt<13>(0h1000))) node _T_795 = asSInt(_T_794) node _T_796 = eq(_T_795, asSInt(UInt<1>(0h0))) node _T_797 = and(_T_791, _T_796) node _T_798 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_799 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_800 = and(_T_798, _T_799) node _T_801 = or(UInt<1>(0h0), _T_800) node _T_802 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_803 = cvt(_T_802) node _T_804 = and(_T_803, asSInt(UInt<14>(0h2000))) node _T_805 = asSInt(_T_804) node _T_806 = eq(_T_805, asSInt(UInt<1>(0h0))) node _T_807 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_808 = cvt(_T_807) node _T_809 = and(_T_808, asSInt(UInt<18>(0h2f000))) node _T_810 = asSInt(_T_809) node _T_811 = eq(_T_810, asSInt(UInt<1>(0h0))) node _T_812 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_813 = cvt(_T_812) node _T_814 = and(_T_813, asSInt(UInt<12>(0h800))) node _T_815 = asSInt(_T_814) node _T_816 = eq(_T_815, asSInt(UInt<1>(0h0))) node _T_817 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_818 = cvt(_T_817) node _T_819 = and(_T_818, asSInt(UInt<16>(0h8000))) node _T_820 = asSInt(_T_819) node _T_821 = eq(_T_820, asSInt(UInt<1>(0h0))) node _T_822 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_823 = cvt(_T_822) node _T_824 = and(_T_823, asSInt(UInt<17>(0h10000))) node _T_825 = asSInt(_T_824) node _T_826 = eq(_T_825, asSInt(UInt<1>(0h0))) node _T_827 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_828 = cvt(_T_827) node _T_829 = and(_T_828, asSInt(UInt<13>(0h1000))) node _T_830 = asSInt(_T_829) node _T_831 = eq(_T_830, asSInt(UInt<1>(0h0))) node _T_832 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_833 = cvt(_T_832) node _T_834 = and(_T_833, asSInt(UInt<27>(0h4000000))) node _T_835 = asSInt(_T_834) node _T_836 = eq(_T_835, asSInt(UInt<1>(0h0))) node _T_837 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_838 = cvt(_T_837) node _T_839 = and(_T_838, asSInt(UInt<13>(0h1000))) node _T_840 = asSInt(_T_839) node _T_841 = eq(_T_840, asSInt(UInt<1>(0h0))) node _T_842 = or(_T_806, _T_811) node _T_843 = or(_T_842, _T_816) node _T_844 = or(_T_843, _T_821) node _T_845 = or(_T_844, _T_826) node _T_846 = or(_T_845, _T_831) node _T_847 = or(_T_846, _T_836) node _T_848 = or(_T_847, _T_841) node _T_849 = and(_T_801, _T_848) node _T_850 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_851 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_852 = cvt(_T_851) node _T_853 = and(_T_852, asSInt(UInt<17>(0h10000))) node _T_854 = asSInt(_T_853) node _T_855 = eq(_T_854, asSInt(UInt<1>(0h0))) node _T_856 = and(_T_850, _T_855) node _T_857 = or(UInt<1>(0h0), _T_797) node _T_858 = or(_T_857, _T_849) node _T_859 = or(_T_858, _T_856) node _T_860 = and(_T_787, _T_859) node _T_861 = asUInt(reset) node _T_862 = eq(_T_861, UInt<1>(0h0)) when _T_862 : node _T_863 = eq(_T_860, UInt<1>(0h0)) when _T_863 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_860, UInt<1>(0h1), "") : assert_31 node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(source_ok, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_867 = asUInt(reset) node _T_868 = eq(_T_867, UInt<1>(0h0)) when _T_868 : node _T_869 = eq(is_aligned, UInt<1>(0h0)) when _T_869 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_870 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_871 = asUInt(reset) node _T_872 = eq(_T_871, UInt<1>(0h0)) when _T_872 : node _T_873 = eq(_T_870, UInt<1>(0h0)) when _T_873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_870, UInt<1>(0h1), "") : assert_34 node _T_874 = not(mask) node _T_875 = and(io.in.a.bits.mask, _T_874) node _T_876 = eq(_T_875, UInt<1>(0h0)) node _T_877 = asUInt(reset) node _T_878 = eq(_T_877, UInt<1>(0h0)) when _T_878 : node _T_879 = eq(_T_876, UInt<1>(0h0)) when _T_879 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_876, UInt<1>(0h1), "") : assert_35 node _T_880 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_880 : node _T_881 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_882 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_883 = and(_T_881, _T_882) node _T_884 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_885 = shr(io.in.a.bits.source, 2) node _T_886 = eq(_T_885, UInt<1>(0h0)) node _T_887 = leq(UInt<1>(0h0), uncommonBits_24) node _T_888 = and(_T_886, _T_887) node _T_889 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_890 = and(_T_888, _T_889) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_891 = shr(io.in.a.bits.source, 2) node _T_892 = eq(_T_891, UInt<1>(0h1)) node _T_893 = leq(UInt<1>(0h0), uncommonBits_25) node _T_894 = and(_T_892, _T_893) node _T_895 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_896 = and(_T_894, _T_895) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_897 = shr(io.in.a.bits.source, 2) node _T_898 = eq(_T_897, UInt<2>(0h2)) node _T_899 = leq(UInt<1>(0h0), uncommonBits_26) node _T_900 = and(_T_898, _T_899) node _T_901 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_902 = and(_T_900, _T_901) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_903 = shr(io.in.a.bits.source, 2) node _T_904 = eq(_T_903, UInt<2>(0h3)) node _T_905 = leq(UInt<1>(0h0), uncommonBits_27) node _T_906 = and(_T_904, _T_905) node _T_907 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_908 = and(_T_906, _T_907) node _T_909 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_910 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_911 = or(_T_884, _T_890) node _T_912 = or(_T_911, _T_896) node _T_913 = or(_T_912, _T_902) node _T_914 = or(_T_913, _T_908) node _T_915 = or(_T_914, _T_909) node _T_916 = or(_T_915, _T_910) node _T_917 = and(_T_883, _T_916) node _T_918 = or(UInt<1>(0h0), _T_917) node _T_919 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_920 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_921 = and(_T_919, _T_920) node _T_922 = or(UInt<1>(0h0), _T_921) node _T_923 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_924 = cvt(_T_923) node _T_925 = and(_T_924, asSInt(UInt<14>(0h2000))) node _T_926 = asSInt(_T_925) node _T_927 = eq(_T_926, asSInt(UInt<1>(0h0))) node _T_928 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_929 = cvt(_T_928) node _T_930 = and(_T_929, asSInt(UInt<13>(0h1000))) node _T_931 = asSInt(_T_930) node _T_932 = eq(_T_931, asSInt(UInt<1>(0h0))) node _T_933 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_934 = cvt(_T_933) node _T_935 = and(_T_934, asSInt(UInt<18>(0h2f000))) node _T_936 = asSInt(_T_935) node _T_937 = eq(_T_936, asSInt(UInt<1>(0h0))) node _T_938 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_939 = cvt(_T_938) node _T_940 = and(_T_939, asSInt(UInt<12>(0h800))) node _T_941 = asSInt(_T_940) node _T_942 = eq(_T_941, asSInt(UInt<1>(0h0))) node _T_943 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_944 = cvt(_T_943) node _T_945 = and(_T_944, asSInt(UInt<16>(0h8000))) node _T_946 = asSInt(_T_945) node _T_947 = eq(_T_946, asSInt(UInt<1>(0h0))) node _T_948 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_949 = cvt(_T_948) node _T_950 = and(_T_949, asSInt(UInt<17>(0h10000))) node _T_951 = asSInt(_T_950) node _T_952 = eq(_T_951, asSInt(UInt<1>(0h0))) node _T_953 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_954 = cvt(_T_953) node _T_955 = and(_T_954, asSInt(UInt<13>(0h1000))) node _T_956 = asSInt(_T_955) node _T_957 = eq(_T_956, asSInt(UInt<1>(0h0))) node _T_958 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_959 = cvt(_T_958) node _T_960 = and(_T_959, asSInt(UInt<27>(0h4000000))) node _T_961 = asSInt(_T_960) node _T_962 = eq(_T_961, asSInt(UInt<1>(0h0))) node _T_963 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_964 = cvt(_T_963) node _T_965 = and(_T_964, asSInt(UInt<13>(0h1000))) node _T_966 = asSInt(_T_965) node _T_967 = eq(_T_966, asSInt(UInt<1>(0h0))) node _T_968 = or(_T_927, _T_932) node _T_969 = or(_T_968, _T_937) node _T_970 = or(_T_969, _T_942) node _T_971 = or(_T_970, _T_947) node _T_972 = or(_T_971, _T_952) node _T_973 = or(_T_972, _T_957) node _T_974 = or(_T_973, _T_962) node _T_975 = or(_T_974, _T_967) node _T_976 = and(_T_922, _T_975) node _T_977 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_978 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_979 = cvt(_T_978) node _T_980 = and(_T_979, asSInt(UInt<17>(0h10000))) node _T_981 = asSInt(_T_980) node _T_982 = eq(_T_981, asSInt(UInt<1>(0h0))) node _T_983 = and(_T_977, _T_982) node _T_984 = or(UInt<1>(0h0), _T_976) node _T_985 = or(_T_984, _T_983) node _T_986 = and(_T_918, _T_985) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_986, UInt<1>(0h1), "") : assert_36 node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(source_ok, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(is_aligned, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_996 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_996, UInt<1>(0h1), "") : assert_39 node _T_1000 = eq(io.in.a.bits.mask, mask) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_40 node _T_1004 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1004 : node _T_1005 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1006 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1007 = and(_T_1005, _T_1006) node _T_1008 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1009 = shr(io.in.a.bits.source, 2) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) node _T_1011 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1012 = and(_T_1010, _T_1011) node _T_1013 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1014 = and(_T_1012, _T_1013) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1015 = shr(io.in.a.bits.source, 2) node _T_1016 = eq(_T_1015, UInt<1>(0h1)) node _T_1017 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1018 = and(_T_1016, _T_1017) node _T_1019 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1020 = and(_T_1018, _T_1019) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1021 = shr(io.in.a.bits.source, 2) node _T_1022 = eq(_T_1021, UInt<2>(0h2)) node _T_1023 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1024 = and(_T_1022, _T_1023) node _T_1025 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1026 = and(_T_1024, _T_1025) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1027 = shr(io.in.a.bits.source, 2) node _T_1028 = eq(_T_1027, UInt<2>(0h3)) node _T_1029 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1030 = and(_T_1028, _T_1029) node _T_1031 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1032 = and(_T_1030, _T_1031) node _T_1033 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1034 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1035 = or(_T_1008, _T_1014) node _T_1036 = or(_T_1035, _T_1020) node _T_1037 = or(_T_1036, _T_1026) node _T_1038 = or(_T_1037, _T_1032) node _T_1039 = or(_T_1038, _T_1033) node _T_1040 = or(_T_1039, _T_1034) node _T_1041 = and(_T_1007, _T_1040) node _T_1042 = or(UInt<1>(0h0), _T_1041) node _T_1043 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1044 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1045 = and(_T_1043, _T_1044) node _T_1046 = or(UInt<1>(0h0), _T_1045) node _T_1047 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1048 = cvt(_T_1047) node _T_1049 = and(_T_1048, asSInt(UInt<14>(0h2000))) node _T_1050 = asSInt(_T_1049) node _T_1051 = eq(_T_1050, asSInt(UInt<1>(0h0))) node _T_1052 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1053 = cvt(_T_1052) node _T_1054 = and(_T_1053, asSInt(UInt<13>(0h1000))) node _T_1055 = asSInt(_T_1054) node _T_1056 = eq(_T_1055, asSInt(UInt<1>(0h0))) node _T_1057 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1058 = cvt(_T_1057) node _T_1059 = and(_T_1058, asSInt(UInt<18>(0h2f000))) node _T_1060 = asSInt(_T_1059) node _T_1061 = eq(_T_1060, asSInt(UInt<1>(0h0))) node _T_1062 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_1063 = cvt(_T_1062) node _T_1064 = and(_T_1063, asSInt(UInt<12>(0h800))) node _T_1065 = asSInt(_T_1064) node _T_1066 = eq(_T_1065, asSInt(UInt<1>(0h0))) node _T_1067 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_1068 = cvt(_T_1067) node _T_1069 = and(_T_1068, asSInt(UInt<16>(0h8000))) node _T_1070 = asSInt(_T_1069) node _T_1071 = eq(_T_1070, asSInt(UInt<1>(0h0))) node _T_1072 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1073 = cvt(_T_1072) node _T_1074 = and(_T_1073, asSInt(UInt<17>(0h10000))) node _T_1075 = asSInt(_T_1074) node _T_1076 = eq(_T_1075, asSInt(UInt<1>(0h0))) node _T_1077 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1078 = cvt(_T_1077) node _T_1079 = and(_T_1078, asSInt(UInt<13>(0h1000))) node _T_1080 = asSInt(_T_1079) node _T_1081 = eq(_T_1080, asSInt(UInt<1>(0h0))) node _T_1082 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1083 = cvt(_T_1082) node _T_1084 = and(_T_1083, asSInt(UInt<27>(0h4000000))) node _T_1085 = asSInt(_T_1084) node _T_1086 = eq(_T_1085, asSInt(UInt<1>(0h0))) node _T_1087 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1088 = cvt(_T_1087) node _T_1089 = and(_T_1088, asSInt(UInt<13>(0h1000))) node _T_1090 = asSInt(_T_1089) node _T_1091 = eq(_T_1090, asSInt(UInt<1>(0h0))) node _T_1092 = or(_T_1051, _T_1056) node _T_1093 = or(_T_1092, _T_1061) node _T_1094 = or(_T_1093, _T_1066) node _T_1095 = or(_T_1094, _T_1071) node _T_1096 = or(_T_1095, _T_1076) node _T_1097 = or(_T_1096, _T_1081) node _T_1098 = or(_T_1097, _T_1086) node _T_1099 = or(_T_1098, _T_1091) node _T_1100 = and(_T_1046, _T_1099) node _T_1101 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1102 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1103 = cvt(_T_1102) node _T_1104 = and(_T_1103, asSInt(UInt<17>(0h10000))) node _T_1105 = asSInt(_T_1104) node _T_1106 = eq(_T_1105, asSInt(UInt<1>(0h0))) node _T_1107 = and(_T_1101, _T_1106) node _T_1108 = or(UInt<1>(0h0), _T_1100) node _T_1109 = or(_T_1108, _T_1107) node _T_1110 = and(_T_1042, _T_1109) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_41 node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(source_ok, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(is_aligned, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1120 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_44 node _T_1124 = eq(io.in.a.bits.mask, mask) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_45 node _T_1128 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1128 : node _T_1129 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1130 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1131 = and(_T_1129, _T_1130) node _T_1132 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1133 = shr(io.in.a.bits.source, 2) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) node _T_1135 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1136 = and(_T_1134, _T_1135) node _T_1137 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1138 = and(_T_1136, _T_1137) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1139 = shr(io.in.a.bits.source, 2) node _T_1140 = eq(_T_1139, UInt<1>(0h1)) node _T_1141 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1144 = and(_T_1142, _T_1143) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1145 = shr(io.in.a.bits.source, 2) node _T_1146 = eq(_T_1145, UInt<2>(0h2)) node _T_1147 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1148 = and(_T_1146, _T_1147) node _T_1149 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1150 = and(_T_1148, _T_1149) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1151 = shr(io.in.a.bits.source, 2) node _T_1152 = eq(_T_1151, UInt<2>(0h3)) node _T_1153 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1154 = and(_T_1152, _T_1153) node _T_1155 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1156 = and(_T_1154, _T_1155) node _T_1157 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1158 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1159 = or(_T_1132, _T_1138) node _T_1160 = or(_T_1159, _T_1144) node _T_1161 = or(_T_1160, _T_1150) node _T_1162 = or(_T_1161, _T_1156) node _T_1163 = or(_T_1162, _T_1157) node _T_1164 = or(_T_1163, _T_1158) node _T_1165 = and(_T_1131, _T_1164) node _T_1166 = or(UInt<1>(0h0), _T_1165) node _T_1167 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1168 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1169 = and(_T_1167, _T_1168) node _T_1170 = or(UInt<1>(0h0), _T_1169) node _T_1171 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1172 = cvt(_T_1171) node _T_1173 = and(_T_1172, asSInt(UInt<13>(0h1000))) node _T_1174 = asSInt(_T_1173) node _T_1175 = eq(_T_1174, asSInt(UInt<1>(0h0))) node _T_1176 = and(_T_1170, _T_1175) node _T_1177 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1179 = cvt(_T_1178) node _T_1180 = and(_T_1179, asSInt(UInt<14>(0h2000))) node _T_1181 = asSInt(_T_1180) node _T_1182 = eq(_T_1181, asSInt(UInt<1>(0h0))) node _T_1183 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1184 = cvt(_T_1183) node _T_1185 = and(_T_1184, asSInt(UInt<17>(0h10000))) node _T_1186 = asSInt(_T_1185) node _T_1187 = eq(_T_1186, asSInt(UInt<1>(0h0))) node _T_1188 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1189 = cvt(_T_1188) node _T_1190 = and(_T_1189, asSInt(UInt<18>(0h2f000))) node _T_1191 = asSInt(_T_1190) node _T_1192 = eq(_T_1191, asSInt(UInt<1>(0h0))) node _T_1193 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_1194 = cvt(_T_1193) node _T_1195 = and(_T_1194, asSInt(UInt<12>(0h800))) node _T_1196 = asSInt(_T_1195) node _T_1197 = eq(_T_1196, asSInt(UInt<1>(0h0))) node _T_1198 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_1199 = cvt(_T_1198) node _T_1200 = and(_T_1199, asSInt(UInt<16>(0h8000))) node _T_1201 = asSInt(_T_1200) node _T_1202 = eq(_T_1201, asSInt(UInt<1>(0h0))) node _T_1203 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1204 = cvt(_T_1203) node _T_1205 = and(_T_1204, asSInt(UInt<17>(0h10000))) node _T_1206 = asSInt(_T_1205) node _T_1207 = eq(_T_1206, asSInt(UInt<1>(0h0))) node _T_1208 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1209 = cvt(_T_1208) node _T_1210 = and(_T_1209, asSInt(UInt<13>(0h1000))) node _T_1211 = asSInt(_T_1210) node _T_1212 = eq(_T_1211, asSInt(UInt<1>(0h0))) node _T_1213 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1214 = cvt(_T_1213) node _T_1215 = and(_T_1214, asSInt(UInt<27>(0h4000000))) node _T_1216 = asSInt(_T_1215) node _T_1217 = eq(_T_1216, asSInt(UInt<1>(0h0))) node _T_1218 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1219 = cvt(_T_1218) node _T_1220 = and(_T_1219, asSInt(UInt<13>(0h1000))) node _T_1221 = asSInt(_T_1220) node _T_1222 = eq(_T_1221, asSInt(UInt<1>(0h0))) node _T_1223 = or(_T_1182, _T_1187) node _T_1224 = or(_T_1223, _T_1192) node _T_1225 = or(_T_1224, _T_1197) node _T_1226 = or(_T_1225, _T_1202) node _T_1227 = or(_T_1226, _T_1207) node _T_1228 = or(_T_1227, _T_1212) node _T_1229 = or(_T_1228, _T_1217) node _T_1230 = or(_T_1229, _T_1222) node _T_1231 = and(_T_1177, _T_1230) node _T_1232 = or(UInt<1>(0h0), _T_1176) node _T_1233 = or(_T_1232, _T_1231) node _T_1234 = and(_T_1166, _T_1233) node _T_1235 = asUInt(reset) node _T_1236 = eq(_T_1235, UInt<1>(0h0)) when _T_1236 : node _T_1237 = eq(_T_1234, UInt<1>(0h0)) when _T_1237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1234, UInt<1>(0h1), "") : assert_46 node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(source_ok, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(is_aligned, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1244 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_49 node _T_1248 = eq(io.in.a.bits.mask, mask) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_50 node _T_1252 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1256 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(_T_1256, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1256, UInt<1>(0h1), "") : assert_52 node _source_ok_T_32 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_33 = shr(io.in.d.bits.source, 2) node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0)) node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_39 = shr(io.in.d.bits.source, 2) node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h1)) node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_45 = shr(io.in.d.bits.source, 2) node _source_ok_T_46 = eq(_source_ok_T_45, UInt<2>(0h2)) node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_T_49 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h3)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_58 = eq(io.in.d.bits.source, UInt<6>(0h20)) wire _source_ok_WIRE_1 : UInt<1>[7] connect _source_ok_WIRE_1[0], _source_ok_T_32 connect _source_ok_WIRE_1[1], _source_ok_T_38 connect _source_ok_WIRE_1[2], _source_ok_T_44 connect _source_ok_WIRE_1[3], _source_ok_T_50 connect _source_ok_WIRE_1[4], _source_ok_T_56 connect _source_ok_WIRE_1[5], _source_ok_T_57 connect _source_ok_WIRE_1[6], _source_ok_T_58 node _source_ok_T_59 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE_1[2]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE_1[3]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE_1[4]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[5]) node source_ok_1 = or(_source_ok_T_63, _source_ok_WIRE_1[6]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1260 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1260 : node _T_1261 = asUInt(reset) node _T_1262 = eq(_T_1261, UInt<1>(0h0)) when _T_1262 : node _T_1263 = eq(source_ok_1, UInt<1>(0h0)) when _T_1263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1264 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_54 node _T_1268 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_55 node _T_1272 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1273 = asUInt(reset) node _T_1274 = eq(_T_1273, UInt<1>(0h0)) when _T_1274 : node _T_1275 = eq(_T_1272, UInt<1>(0h0)) when _T_1275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1272, UInt<1>(0h1), "") : assert_56 node _T_1276 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1277 = asUInt(reset) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(_T_1276, UInt<1>(0h0)) when _T_1279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1276, UInt<1>(0h1), "") : assert_57 node _T_1280 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1280 : node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(source_ok_1, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(sink_ok, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1287 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(_T_1287, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1287, UInt<1>(0h1), "") : assert_60 node _T_1291 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_61 node _T_1295 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1296 = asUInt(reset) node _T_1297 = eq(_T_1296, UInt<1>(0h0)) when _T_1297 : node _T_1298 = eq(_T_1295, UInt<1>(0h0)) when _T_1298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1295, UInt<1>(0h1), "") : assert_62 node _T_1299 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_63 node _T_1303 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1304 = or(UInt<1>(0h1), _T_1303) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_64 node _T_1308 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1308 : node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(source_ok_1, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1312 = asUInt(reset) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(sink_ok, UInt<1>(0h0)) when _T_1314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1315 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_67 node _T_1319 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(_T_1319, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1319, UInt<1>(0h1), "") : assert_68 node _T_1323 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1324 = asUInt(reset) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(_T_1323, UInt<1>(0h0)) when _T_1326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1323, UInt<1>(0h1), "") : assert_69 node _T_1327 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1328 = or(_T_1327, io.in.d.bits.corrupt) node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(_T_1328, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1328, UInt<1>(0h1), "") : assert_70 node _T_1332 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1333 = or(UInt<1>(0h1), _T_1332) node _T_1334 = asUInt(reset) node _T_1335 = eq(_T_1334, UInt<1>(0h0)) when _T_1335 : node _T_1336 = eq(_T_1333, UInt<1>(0h0)) when _T_1336 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1333, UInt<1>(0h1), "") : assert_71 node _T_1337 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1337 : node _T_1338 = asUInt(reset) node _T_1339 = eq(_T_1338, UInt<1>(0h0)) when _T_1339 : node _T_1340 = eq(source_ok_1, UInt<1>(0h0)) when _T_1340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1341 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1342 = asUInt(reset) node _T_1343 = eq(_T_1342, UInt<1>(0h0)) when _T_1343 : node _T_1344 = eq(_T_1341, UInt<1>(0h0)) when _T_1344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1341, UInt<1>(0h1), "") : assert_73 node _T_1345 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1346 = asUInt(reset) node _T_1347 = eq(_T_1346, UInt<1>(0h0)) when _T_1347 : node _T_1348 = eq(_T_1345, UInt<1>(0h0)) when _T_1348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1345, UInt<1>(0h1), "") : assert_74 node _T_1349 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1350 = or(UInt<1>(0h1), _T_1349) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_75 node _T_1354 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1354 : node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(source_ok_1, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1358 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_77 node _T_1362 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1363 = or(_T_1362, io.in.d.bits.corrupt) node _T_1364 = asUInt(reset) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) when _T_1365 : node _T_1366 = eq(_T_1363, UInt<1>(0h0)) when _T_1366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1363, UInt<1>(0h1), "") : assert_78 node _T_1367 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1368 = or(UInt<1>(0h1), _T_1367) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_79 node _T_1372 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1372 : node _T_1373 = asUInt(reset) node _T_1374 = eq(_T_1373, UInt<1>(0h0)) when _T_1374 : node _T_1375 = eq(source_ok_1, UInt<1>(0h0)) when _T_1375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1376 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1377 = asUInt(reset) node _T_1378 = eq(_T_1377, UInt<1>(0h0)) when _T_1378 : node _T_1379 = eq(_T_1376, UInt<1>(0h0)) when _T_1379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1376, UInt<1>(0h1), "") : assert_81 node _T_1380 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1381 = asUInt(reset) node _T_1382 = eq(_T_1381, UInt<1>(0h0)) when _T_1382 : node _T_1383 = eq(_T_1380, UInt<1>(0h0)) when _T_1383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1380, UInt<1>(0h1), "") : assert_82 node _T_1384 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1385 = or(UInt<1>(0h1), _T_1384) node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(_T_1385, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1385, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1389 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1390 = asUInt(reset) node _T_1391 = eq(_T_1390, UInt<1>(0h0)) when _T_1391 : node _T_1392 = eq(_T_1389, UInt<1>(0h0)) when _T_1392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1389, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<6>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1393 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(_T_1393, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1393, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1397 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1398 = asUInt(reset) node _T_1399 = eq(_T_1398, UInt<1>(0h0)) when _T_1399 : node _T_1400 = eq(_T_1397, UInt<1>(0h0)) when _T_1400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1397, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1401 = eq(a_first, UInt<1>(0h0)) node _T_1402 = and(io.in.a.valid, _T_1401) when _T_1402 : node _T_1403 = eq(io.in.a.bits.opcode, opcode) node _T_1404 = asUInt(reset) node _T_1405 = eq(_T_1404, UInt<1>(0h0)) when _T_1405 : node _T_1406 = eq(_T_1403, UInt<1>(0h0)) when _T_1406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1403, UInt<1>(0h1), "") : assert_87 node _T_1407 = eq(io.in.a.bits.param, param) node _T_1408 = asUInt(reset) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(_T_1407, UInt<1>(0h0)) when _T_1410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1407, UInt<1>(0h1), "") : assert_88 node _T_1411 = eq(io.in.a.bits.size, size) node _T_1412 = asUInt(reset) node _T_1413 = eq(_T_1412, UInt<1>(0h0)) when _T_1413 : node _T_1414 = eq(_T_1411, UInt<1>(0h0)) when _T_1414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1411, UInt<1>(0h1), "") : assert_89 node _T_1415 = eq(io.in.a.bits.source, source) node _T_1416 = asUInt(reset) node _T_1417 = eq(_T_1416, UInt<1>(0h0)) when _T_1417 : node _T_1418 = eq(_T_1415, UInt<1>(0h0)) when _T_1418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1415, UInt<1>(0h1), "") : assert_90 node _T_1419 = eq(io.in.a.bits.address, address) node _T_1420 = asUInt(reset) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) when _T_1421 : node _T_1422 = eq(_T_1419, UInt<1>(0h0)) when _T_1422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1419, UInt<1>(0h1), "") : assert_91 node _T_1423 = and(io.in.a.ready, io.in.a.valid) node _T_1424 = and(_T_1423, a_first) when _T_1424 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1425 = eq(d_first, UInt<1>(0h0)) node _T_1426 = and(io.in.d.valid, _T_1425) when _T_1426 : node _T_1427 = eq(io.in.d.bits.opcode, opcode_1) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_92 node _T_1431 = eq(io.in.d.bits.param, param_1) node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(_T_1431, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1431, UInt<1>(0h1), "") : assert_93 node _T_1435 = eq(io.in.d.bits.size, size_1) node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(_T_1435, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1435, UInt<1>(0h1), "") : assert_94 node _T_1439 = eq(io.in.d.bits.source, source_1) node _T_1440 = asUInt(reset) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : node _T_1442 = eq(_T_1439, UInt<1>(0h0)) when _T_1442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1439, UInt<1>(0h1), "") : assert_95 node _T_1443 = eq(io.in.d.bits.sink, sink) node _T_1444 = asUInt(reset) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) when _T_1445 : node _T_1446 = eq(_T_1443, UInt<1>(0h0)) when _T_1446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1443, UInt<1>(0h1), "") : assert_96 node _T_1447 = eq(io.in.d.bits.denied, denied) node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(_T_1447, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1447, UInt<1>(0h1), "") : assert_97 node _T_1451 = and(io.in.d.ready, io.in.d.valid) node _T_1452 = and(_T_1451, d_first) when _T_1452 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<34>, clock, reset, UInt<34>(0h0) regreset inflight_opcodes : UInt<136>, clock, reset, UInt<136>(0h0) regreset inflight_sizes : UInt<272>, clock, reset, UInt<272>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<34> connect a_set, UInt<34>(0h0) wire a_set_wo_ready : UInt<34> connect a_set_wo_ready, UInt<34>(0h0) wire a_opcodes_set : UInt<136> connect a_opcodes_set, UInt<136>(0h0) wire a_sizes_set : UInt<272> connect a_sizes_set, UInt<272>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1453 = and(io.in.a.valid, a_first_1) node _T_1454 = and(_T_1453, UInt<1>(0h1)) when _T_1454 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1455 = and(io.in.a.ready, io.in.a.valid) node _T_1456 = and(_T_1455, a_first_1) node _T_1457 = and(_T_1456, UInt<1>(0h1)) when _T_1457 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1458 = dshr(inflight, io.in.a.bits.source) node _T_1459 = bits(_T_1458, 0, 0) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) node _T_1461 = asUInt(reset) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) when _T_1462 : node _T_1463 = eq(_T_1460, UInt<1>(0h0)) when _T_1463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1460, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<34> connect d_clr, UInt<34>(0h0) wire d_clr_wo_ready : UInt<34> connect d_clr_wo_ready, UInt<34>(0h0) wire d_opcodes_clr : UInt<136> connect d_opcodes_clr, UInt<136>(0h0) wire d_sizes_clr : UInt<272> connect d_sizes_clr, UInt<272>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1464 = and(io.in.d.valid, d_first_1) node _T_1465 = and(_T_1464, UInt<1>(0h1)) node _T_1466 = eq(d_release_ack, UInt<1>(0h0)) node _T_1467 = and(_T_1465, _T_1466) when _T_1467 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1468 = and(io.in.d.ready, io.in.d.valid) node _T_1469 = and(_T_1468, d_first_1) node _T_1470 = and(_T_1469, UInt<1>(0h1)) node _T_1471 = eq(d_release_ack, UInt<1>(0h0)) node _T_1472 = and(_T_1470, _T_1471) when _T_1472 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1473 = and(io.in.d.valid, d_first_1) node _T_1474 = and(_T_1473, UInt<1>(0h1)) node _T_1475 = eq(d_release_ack, UInt<1>(0h0)) node _T_1476 = and(_T_1474, _T_1475) when _T_1476 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1477 = dshr(inflight, io.in.d.bits.source) node _T_1478 = bits(_T_1477, 0, 0) node _T_1479 = or(_T_1478, same_cycle_resp) node _T_1480 = asUInt(reset) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) when _T_1481 : node _T_1482 = eq(_T_1479, UInt<1>(0h0)) when _T_1482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1479, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1483 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1484 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1485 = or(_T_1483, _T_1484) node _T_1486 = asUInt(reset) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) when _T_1487 : node _T_1488 = eq(_T_1485, UInt<1>(0h0)) when _T_1488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1485, UInt<1>(0h1), "") : assert_100 node _T_1489 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1490 = asUInt(reset) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) when _T_1491 : node _T_1492 = eq(_T_1489, UInt<1>(0h0)) when _T_1492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1489, UInt<1>(0h1), "") : assert_101 else : node _T_1493 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1494 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1495 = or(_T_1493, _T_1494) node _T_1496 = asUInt(reset) node _T_1497 = eq(_T_1496, UInt<1>(0h0)) when _T_1497 : node _T_1498 = eq(_T_1495, UInt<1>(0h0)) when _T_1498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1495, UInt<1>(0h1), "") : assert_102 node _T_1499 = eq(io.in.d.bits.size, a_size_lookup) node _T_1500 = asUInt(reset) node _T_1501 = eq(_T_1500, UInt<1>(0h0)) when _T_1501 : node _T_1502 = eq(_T_1499, UInt<1>(0h0)) when _T_1502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1499, UInt<1>(0h1), "") : assert_103 node _T_1503 = and(io.in.d.valid, d_first_1) node _T_1504 = and(_T_1503, a_first_1) node _T_1505 = and(_T_1504, io.in.a.valid) node _T_1506 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1507 = and(_T_1505, _T_1506) node _T_1508 = eq(d_release_ack, UInt<1>(0h0)) node _T_1509 = and(_T_1507, _T_1508) when _T_1509 : node _T_1510 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1511 = or(_T_1510, io.in.a.ready) node _T_1512 = asUInt(reset) node _T_1513 = eq(_T_1512, UInt<1>(0h0)) when _T_1513 : node _T_1514 = eq(_T_1511, UInt<1>(0h0)) when _T_1514 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1511, UInt<1>(0h1), "") : assert_104 node _T_1515 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1516 = orr(a_set_wo_ready) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) node _T_1518 = or(_T_1515, _T_1517) node _T_1519 = asUInt(reset) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) when _T_1520 : node _T_1521 = eq(_T_1518, UInt<1>(0h0)) when _T_1521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1518, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_28 node _T_1522 = orr(inflight) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) node _T_1524 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1525 = or(_T_1523, _T_1524) node _T_1526 = lt(watchdog, plusarg_reader.out) node _T_1527 = or(_T_1525, _T_1526) node _T_1528 = asUInt(reset) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(_T_1527, UInt<1>(0h0)) when _T_1530 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1527, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1531 = and(io.in.a.ready, io.in.a.valid) node _T_1532 = and(io.in.d.ready, io.in.d.valid) node _T_1533 = or(_T_1531, _T_1532) when _T_1533 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<34>, clock, reset, UInt<34>(0h0) regreset inflight_opcodes_1 : UInt<136>, clock, reset, UInt<136>(0h0) regreset inflight_sizes_1 : UInt<272>, clock, reset, UInt<272>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<6>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<6>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<34> connect c_set, UInt<34>(0h0) wire c_set_wo_ready : UInt<34> connect c_set_wo_ready, UInt<34>(0h0) wire c_opcodes_set : UInt<136> connect c_opcodes_set, UInt<136>(0h0) wire c_sizes_set : UInt<272> connect c_sizes_set, UInt<272>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1534 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1535 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1536 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1537 = and(_T_1535, _T_1536) node _T_1538 = and(_T_1534, _T_1537) when _T_1538 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<6>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1539 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1540 = and(_T_1539, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<6>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1541 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1542 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1543 = and(_T_1541, _T_1542) node _T_1544 = and(_T_1540, _T_1543) when _T_1544 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<6>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<6>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1545 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1546 = bits(_T_1545, 0, 0) node _T_1547 = eq(_T_1546, UInt<1>(0h0)) node _T_1548 = asUInt(reset) node _T_1549 = eq(_T_1548, UInt<1>(0h0)) when _T_1549 : node _T_1550 = eq(_T_1547, UInt<1>(0h0)) when _T_1550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1547, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<34> connect d_clr_1, UInt<34>(0h0) wire d_clr_wo_ready_1 : UInt<34> connect d_clr_wo_ready_1, UInt<34>(0h0) wire d_opcodes_clr_1 : UInt<136> connect d_opcodes_clr_1, UInt<136>(0h0) wire d_sizes_clr_1 : UInt<272> connect d_sizes_clr_1, UInt<272>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1551 = and(io.in.d.valid, d_first_2) node _T_1552 = and(_T_1551, UInt<1>(0h1)) node _T_1553 = and(_T_1552, d_release_ack_1) when _T_1553 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1554 = and(io.in.d.ready, io.in.d.valid) node _T_1555 = and(_T_1554, d_first_2) node _T_1556 = and(_T_1555, UInt<1>(0h1)) node _T_1557 = and(_T_1556, d_release_ack_1) when _T_1557 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1558 = and(io.in.d.valid, d_first_2) node _T_1559 = and(_T_1558, UInt<1>(0h1)) node _T_1560 = and(_T_1559, d_release_ack_1) when _T_1560 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1561 = dshr(inflight_1, io.in.d.bits.source) node _T_1562 = bits(_T_1561, 0, 0) node _T_1563 = or(_T_1562, same_cycle_resp_1) node _T_1564 = asUInt(reset) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(_T_1563, UInt<1>(0h0)) when _T_1566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1563, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<6>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1567 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(_T_1567, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1567, UInt<1>(0h1), "") : assert_109 else : node _T_1571 = eq(io.in.d.bits.size, c_size_lookup) node _T_1572 = asUInt(reset) node _T_1573 = eq(_T_1572, UInt<1>(0h0)) when _T_1573 : node _T_1574 = eq(_T_1571, UInt<1>(0h0)) when _T_1574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1571, UInt<1>(0h1), "") : assert_110 node _T_1575 = and(io.in.d.valid, d_first_2) node _T_1576 = and(_T_1575, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<6>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1577 = and(_T_1576, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<6>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1578 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1579 = and(_T_1577, _T_1578) node _T_1580 = and(_T_1579, d_release_ack_1) node _T_1581 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1582 = and(_T_1580, _T_1581) when _T_1582 : node _T_1583 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<6>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1584 = or(_T_1583, _WIRE_23.ready) node _T_1585 = asUInt(reset) node _T_1586 = eq(_T_1585, UInt<1>(0h0)) when _T_1586 : node _T_1587 = eq(_T_1584, UInt<1>(0h0)) when _T_1587 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1584, UInt<1>(0h1), "") : assert_111 node _T_1588 = orr(c_set_wo_ready) when _T_1588 : node _T_1589 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(_T_1589, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1589, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_29 node _T_1593 = orr(inflight_1) node _T_1594 = eq(_T_1593, UInt<1>(0h0)) node _T_1595 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1596 = or(_T_1594, _T_1595) node _T_1597 = lt(watchdog_1, plusarg_reader_1.out) node _T_1598 = or(_T_1596, _T_1597) node _T_1599 = asUInt(reset) node _T_1600 = eq(_T_1599, UInt<1>(0h0)) when _T_1600 : node _T_1601 = eq(_T_1598, UInt<1>(0h0)) when _T_1601 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1598, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<6>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1602 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1603 = and(io.in.d.ready, io.in.d.valid) node _T_1604 = or(_T_1602, _T_1603) when _T_1604 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_30 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_31 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor_14( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [271:0] c_sizes_set = 272'h0; // @[Monitor.scala:741:34] wire [135:0] c_opcodes_set = 136'h0; // @[Monitor.scala:740:34] wire [33:0] c_set = 34'h0; // @[Monitor.scala:738:34] wire [33:0] c_set_wo_ready = 34'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 6'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_28 = _source_ok_T_27 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_31 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_33 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_39 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_45 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_51 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_40 = _source_ok_T_39 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_46 = _source_ok_T_45 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_52 = _source_ok_T_51 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire _source_ok_T_57 = io_in_d_bits_source_0 == 6'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire _source_ok_T_58 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_63 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _T_1531 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1531; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1531; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1604 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1604; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1604; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1604; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [33:0] inflight; // @[Monitor.scala:614:27] reg [135:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [271:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [33:0] a_set; // @[Monitor.scala:626:34] wire [33:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [135:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [271:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [135:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [135:0] _a_opcode_lookup_T_6 = {132'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [135:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[135:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [271:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [271:0] _a_size_lookup_T_6 = {264'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [271:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[271:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire _T_1457 = _T_1531 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1457 ? _a_set_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1457 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1457 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1457 ? _a_opcodes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1457 ? _a_sizes_set_T_1[271:0] : 272'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [33:0] d_clr; // @[Monitor.scala:664:34] wire [33:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [135:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [271:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1503 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1503 & ~d_release_ack ? _d_clr_wo_ready_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire _T_1472 = _T_1604 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1472 ? _d_clr_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1472 ? _d_opcodes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1472 ? _d_sizes_clr_T_5[271:0] : 272'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [33:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [33:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [33:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [135:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [135:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [135:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [271:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [271:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [271:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [33:0] inflight_1; // @[Monitor.scala:726:35] wire [33:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [135:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [135:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [271:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [271:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [135:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [135:0] _c_opcode_lookup_T_6 = {132'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [135:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[135:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [271:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [271:0] _c_size_lookup_T_6 = {264'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [271:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[271:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [33:0] d_clr_1; // @[Monitor.scala:774:34] wire [33:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [135:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [271:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1575 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1575 & d_release_ack_1 ? _d_clr_wo_ready_T_1[33:0] : 34'h0; // @[OneHot.scala:58:35] wire _T_1557 = _T_1604 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1557 ? _d_clr_T_1[33:0] : 34'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1557 ? _d_opcodes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1557 ? _d_sizes_clr_T_11[271:0] : 272'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [33:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [33:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [135:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [135:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [271:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [271:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_264 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_264( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module ListBuffer_QueuedRequest_q36_e28_5 : input clock : Clock input reset : Reset output io : { flip push : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}}}, valid : UInt<36>, flip pop : { valid : UInt<1>, bits : UInt<6>}, data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}} regreset valid : UInt<36>, clock, reset, UInt<36>(0h0) cmem head : UInt<5> [36] cmem tail : UInt<5> [36] regreset used : UInt<28>, clock, reset, UInt<28>(0h0) cmem next : UInt<5> [28] cmem data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} [28] node _freeOH_T = not(used) node _freeOH_T_1 = shl(_freeOH_T, 1) node _freeOH_T_2 = bits(_freeOH_T_1, 27, 0) node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2) node _freeOH_T_4 = shl(_freeOH_T_3, 2) node _freeOH_T_5 = bits(_freeOH_T_4, 27, 0) node _freeOH_T_6 = or(_freeOH_T_3, _freeOH_T_5) node _freeOH_T_7 = shl(_freeOH_T_6, 4) node _freeOH_T_8 = bits(_freeOH_T_7, 27, 0) node _freeOH_T_9 = or(_freeOH_T_6, _freeOH_T_8) node _freeOH_T_10 = shl(_freeOH_T_9, 8) node _freeOH_T_11 = bits(_freeOH_T_10, 27, 0) node _freeOH_T_12 = or(_freeOH_T_9, _freeOH_T_11) node _freeOH_T_13 = shl(_freeOH_T_12, 16) node _freeOH_T_14 = bits(_freeOH_T_13, 27, 0) node _freeOH_T_15 = or(_freeOH_T_12, _freeOH_T_14) node _freeOH_T_16 = bits(_freeOH_T_15, 27, 0) node _freeOH_T_17 = shl(_freeOH_T_16, 1) node _freeOH_T_18 = not(_freeOH_T_17) node _freeOH_T_19 = not(used) node freeOH = and(_freeOH_T_18, _freeOH_T_19) node freeIdx_hi = bits(freeOH, 28, 16) node freeIdx_lo = bits(freeOH, 15, 0) node _freeIdx_T = orr(freeIdx_hi) node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo) node freeIdx_hi_1 = bits(_freeIdx_T_1, 15, 8) node freeIdx_lo_1 = bits(_freeIdx_T_1, 7, 0) node _freeIdx_T_2 = orr(freeIdx_hi_1) node _freeIdx_T_3 = or(freeIdx_hi_1, freeIdx_lo_1) node freeIdx_hi_2 = bits(_freeIdx_T_3, 7, 4) node freeIdx_lo_2 = bits(_freeIdx_T_3, 3, 0) node _freeIdx_T_4 = orr(freeIdx_hi_2) node _freeIdx_T_5 = or(freeIdx_hi_2, freeIdx_lo_2) node freeIdx_hi_3 = bits(_freeIdx_T_5, 3, 2) node freeIdx_lo_3 = bits(_freeIdx_T_5, 1, 0) node _freeIdx_T_6 = orr(freeIdx_hi_3) node _freeIdx_T_7 = or(freeIdx_hi_3, freeIdx_lo_3) node _freeIdx_T_8 = bits(_freeIdx_T_7, 1, 1) node _freeIdx_T_9 = cat(_freeIdx_T_6, _freeIdx_T_8) node _freeIdx_T_10 = cat(_freeIdx_T_4, _freeIdx_T_9) node _freeIdx_T_11 = cat(_freeIdx_T_2, _freeIdx_T_10) node freeIdx = cat(_freeIdx_T, _freeIdx_T_11) wire valid_set : UInt<36> connect valid_set, UInt<36>(0h0) wire valid_clr : UInt<36> connect valid_clr, UInt<36>(0h0) wire used_set : UInt<28> connect used_set, UInt<28>(0h0) wire used_clr : UInt<28> connect used_clr, UInt<28>(0h0) read mport push_tail = tail[io.push.bits.index], clock node _push_valid_T = dshr(valid, io.push.bits.index) node push_valid = bits(_push_valid_T, 0, 0) node _io_push_ready_T = andr(used) node _io_push_ready_T_1 = eq(_io_push_ready_T, UInt<1>(0h0)) connect io.push.ready, _io_push_ready_T_1 node _T = and(io.push.ready, io.push.valid) when _T : node valid_set_shiftAmount = bits(io.push.bits.index, 5, 0) node _valid_set_T = dshl(UInt<1>(0h1), valid_set_shiftAmount) node _valid_set_T_1 = bits(_valid_set_T, 35, 0) connect valid_set, _valid_set_T_1 connect used_set, freeOH write mport MPORT = data[freeIdx], clock connect MPORT, io.push.bits.data when push_valid : write mport MPORT_1 = next[push_tail], clock connect MPORT_1, freeIdx else : write mport MPORT_2 = head[io.push.bits.index], clock connect MPORT_2, freeIdx write mport MPORT_3 = tail[io.push.bits.index], clock connect MPORT_3, freeIdx read mport pop_head = head[io.pop.bits], clock node _pop_valid_T = dshr(valid, io.pop.bits) node pop_valid = bits(_pop_valid_T, 0, 0) read mport io_data_MPORT = data[pop_head], clock connect io.data, io_data_MPORT connect io.valid, valid node _T_1 = eq(io.pop.valid, UInt<1>(0h0)) node _T_2 = dshr(io.valid, io.pop.bits) node _T_3 = bits(_T_2, 0, 0) node _T_4 = or(_T_1, _T_3) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ListBuffer.scala:86 assert (!io.pop.fire || (io.valid)(io.pop.bits))\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert when io.pop.valid : node used_clr_shiftAmount = bits(pop_head, 4, 0) node _used_clr_T = dshl(UInt<1>(0h1), used_clr_shiftAmount) node _used_clr_T_1 = bits(_used_clr_T, 27, 0) connect used_clr, _used_clr_T_1 read mport MPORT_4 = tail[io.pop.bits], clock node _T_8 = eq(pop_head, MPORT_4) when _T_8 : node valid_clr_shiftAmount = bits(io.pop.bits, 5, 0) node _valid_clr_T = dshl(UInt<1>(0h1), valid_clr_shiftAmount) node _valid_clr_T_1 = bits(_valid_clr_T, 35, 0) connect valid_clr, _valid_clr_T_1 node _T_9 = and(io.push.ready, io.push.valid) node _T_10 = and(_T_9, push_valid) node _T_11 = eq(push_tail, pop_head) node _T_12 = and(_T_10, _T_11) read mport MPORT_5 = next[pop_head], clock node _T_13 = mux(_T_12, freeIdx, MPORT_5) write mport MPORT_6 = head[io.pop.bits], clock connect MPORT_6, _T_13 node _T_14 = eq(io.pop.valid, UInt<1>(0h0)) node _T_15 = or(UInt<1>(0h1), _T_14) node _T_16 = or(_T_15, pop_valid) when _T_16 : node _used_T = not(used_clr) node _used_T_1 = and(used, _used_T) node _used_T_2 = or(_used_T_1, used_set) connect used, _used_T_2 node _valid_T = not(valid_clr) node _valid_T_1 = and(valid, _valid_T) node _valid_T_2 = or(_valid_T_1, valid_set) connect valid, _valid_T_2
module ListBuffer_QueuedRequest_q36_e28_5( // @[ListBuffer.scala:36:7] input clock, // @[ListBuffer.scala:36:7] input reset, // @[ListBuffer.scala:36:7] output io_push_ready, // @[ListBuffer.scala:39:14] input io_push_valid, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_index, // @[ListBuffer.scala:39:14] input io_push_bits_data_prio_0, // @[ListBuffer.scala:39:14] input io_push_bits_data_prio_2, // @[ListBuffer.scala:39:14] input io_push_bits_data_control, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_opcode, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_param, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_size, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_data_source, // @[ListBuffer.scala:39:14] input [8:0] io_push_bits_data_tag, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_data_offset, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_data_put, // @[ListBuffer.scala:39:14] output [35:0] io_valid, // @[ListBuffer.scala:39:14] input io_pop_valid, // @[ListBuffer.scala:39:14] input [5:0] io_pop_bits, // @[ListBuffer.scala:39:14] output io_data_prio_0, // @[ListBuffer.scala:39:14] output io_data_prio_1, // @[ListBuffer.scala:39:14] output io_data_prio_2, // @[ListBuffer.scala:39:14] output io_data_control, // @[ListBuffer.scala:39:14] output [2:0] io_data_opcode, // @[ListBuffer.scala:39:14] output [2:0] io_data_param, // @[ListBuffer.scala:39:14] output [2:0] io_data_size, // @[ListBuffer.scala:39:14] output [5:0] io_data_source, // @[ListBuffer.scala:39:14] output [8:0] io_data_tag, // @[ListBuffer.scala:39:14] output [5:0] io_data_offset, // @[ListBuffer.scala:39:14] output [5:0] io_data_put // @[ListBuffer.scala:39:14] ); wire [39:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18] wire [4:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18] wire [4:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18] wire [4:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18] wire [4:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18] wire io_push_valid_0 = io_push_valid; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_index_0 = io_push_bits_index; // @[ListBuffer.scala:36:7] wire io_push_bits_data_prio_0_0 = io_push_bits_data_prio_0; // @[ListBuffer.scala:36:7] wire io_push_bits_data_prio_2_0 = io_push_bits_data_prio_2; // @[ListBuffer.scala:36:7] wire io_push_bits_data_control_0 = io_push_bits_data_control; // @[ListBuffer.scala:36:7] wire [2:0] io_push_bits_data_opcode_0 = io_push_bits_data_opcode; // @[ListBuffer.scala:36:7] wire [2:0] io_push_bits_data_param_0 = io_push_bits_data_param; // @[ListBuffer.scala:36:7] wire [2:0] io_push_bits_data_size_0 = io_push_bits_data_size; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_data_source_0 = io_push_bits_data_source; // @[ListBuffer.scala:36:7] wire [8:0] io_push_bits_data_tag_0 = io_push_bits_data_tag; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_data_offset_0 = io_push_bits_data_offset; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_data_put_0 = io_push_bits_data_put; // @[ListBuffer.scala:36:7] wire io_pop_valid_0 = io_pop_valid; // @[ListBuffer.scala:36:7] wire [5:0] io_pop_bits_0 = io_pop_bits; // @[ListBuffer.scala:36:7] wire io_push_bits_data_prio_1 = 1'h0; // @[ListBuffer.scala:36:7] wire _io_push_ready_T_1; // @[ListBuffer.scala:65:20] wire [5:0] valid_set_shiftAmount = io_push_bits_index_0; // @[OneHot.scala:64:49] wire [5:0] valid_clr_shiftAmount = io_pop_bits_0; // @[OneHot.scala:64:49] wire io_push_ready_0; // @[ListBuffer.scala:36:7] wire io_data_prio_0_0; // @[ListBuffer.scala:36:7] wire io_data_prio_1_0; // @[ListBuffer.scala:36:7] wire io_data_prio_2_0; // @[ListBuffer.scala:36:7] wire io_data_control_0; // @[ListBuffer.scala:36:7] wire [2:0] io_data_opcode_0; // @[ListBuffer.scala:36:7] wire [2:0] io_data_param_0; // @[ListBuffer.scala:36:7] wire [2:0] io_data_size_0; // @[ListBuffer.scala:36:7] wire [5:0] io_data_source_0; // @[ListBuffer.scala:36:7] wire [8:0] io_data_tag_0; // @[ListBuffer.scala:36:7] wire [5:0] io_data_offset_0; // @[ListBuffer.scala:36:7] wire [5:0] io_data_put_0; // @[ListBuffer.scala:36:7] wire [35:0] io_valid_0; // @[ListBuffer.scala:36:7] reg [35:0] valid; // @[ListBuffer.scala:47:22] assign io_valid_0 = valid; // @[ListBuffer.scala:36:7, :47:22] reg [27:0] used; // @[ListBuffer.scala:50:22] assign io_data_prio_0_0 = _data_ext_R0_data[0]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_prio_1_0 = _data_ext_R0_data[1]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_prio_2_0 = _data_ext_R0_data[2]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_control_0 = _data_ext_R0_data[3]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_opcode_0 = _data_ext_R0_data[6:4]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_param_0 = _data_ext_R0_data[9:7]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_size_0 = _data_ext_R0_data[12:10]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_source_0 = _data_ext_R0_data[18:13]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_tag_0 = _data_ext_R0_data[27:19]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_offset_0 = _data_ext_R0_data[33:28]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_put_0 = _data_ext_R0_data[39:34]; // @[ListBuffer.scala:36:7, :52:18] wire [27:0] _freeOH_T = ~used; // @[ListBuffer.scala:50:22, :54:25] wire [28:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48] wire [27:0] _freeOH_T_2 = _freeOH_T_1[27:0]; // @[package.scala:253:{48,53}] wire [27:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}] wire [29:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [27:0] _freeOH_T_5 = _freeOH_T_4[27:0]; // @[package.scala:253:{48,53}] wire [27:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}] wire [31:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [27:0] _freeOH_T_8 = _freeOH_T_7[27:0]; // @[package.scala:253:{48,53}] wire [27:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}] wire [35:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}] wire [27:0] _freeOH_T_11 = _freeOH_T_10[27:0]; // @[package.scala:253:{48,53}] wire [27:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11; // @[package.scala:253:{43,53}] wire [43:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}] wire [27:0] _freeOH_T_14 = _freeOH_T_13[27:0]; // @[package.scala:253:{48,53}] wire [27:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14; // @[package.scala:253:{43,53}] wire [27:0] _freeOH_T_16 = _freeOH_T_15; // @[package.scala:253:43, :254:17] wire [28:0] _freeOH_T_17 = {_freeOH_T_16, 1'h0}; // @[package.scala:254:17] wire [28:0] _freeOH_T_18 = ~_freeOH_T_17; // @[ListBuffer.scala:54:{16,32}] wire [27:0] _freeOH_T_19 = ~used; // @[ListBuffer.scala:50:22, :54:{25,40}] wire [28:0] freeOH = {1'h0, _freeOH_T_18[27:0] & _freeOH_T_19}; // @[ListBuffer.scala:54:{16,38,40}] wire [12:0] freeIdx_hi = freeOH[28:16]; // @[OneHot.scala:30:18] wire [15:0] freeIdx_lo = freeOH[15:0]; // @[OneHot.scala:31:18] wire _freeIdx_T = |freeIdx_hi; // @[OneHot.scala:30:18, :32:14] wire [15:0] _freeIdx_T_1 = {3'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] freeIdx_hi_1 = _freeIdx_T_1[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] freeIdx_lo_1 = _freeIdx_T_1[7:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14] wire [7:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] freeIdx_hi_2 = _freeIdx_T_3[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] freeIdx_lo_2 = _freeIdx_T_3[3:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14] wire [3:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] freeIdx_hi_3 = _freeIdx_T_5[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] freeIdx_lo_3 = _freeIdx_T_5[1:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14] wire [1:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire _freeIdx_T_8 = _freeIdx_T_7[1]; // @[OneHot.scala:32:28] wire [1:0] _freeIdx_T_9 = {_freeIdx_T_6, _freeIdx_T_8}; // @[OneHot.scala:32:{10,14}] wire [2:0] _freeIdx_T_10 = {_freeIdx_T_4, _freeIdx_T_9}; // @[OneHot.scala:32:{10,14}] wire [3:0] _freeIdx_T_11 = {_freeIdx_T_2, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}] wire [4:0] freeIdx = {_freeIdx_T, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}] wire [35:0] valid_set; // @[ListBuffer.scala:57:30] wire [35:0] valid_clr; // @[ListBuffer.scala:58:30] wire [27:0] used_set; // @[ListBuffer.scala:59:30] wire [27:0] used_clr; // @[ListBuffer.scala:60:30] wire [35:0] _push_valid_T = valid >> io_push_bits_index_0; // @[ListBuffer.scala:36:7, :47:22, :63:25] wire push_valid = _push_valid_T[0]; // @[ListBuffer.scala:63:25] wire _io_push_ready_T = &used; // @[ListBuffer.scala:50:22, :65:26] assign _io_push_ready_T_1 = ~_io_push_ready_T; // @[ListBuffer.scala:65:{20,26}] assign io_push_ready_0 = _io_push_ready_T_1; // @[ListBuffer.scala:36:7, :65:20] wire data_MPORT_en = io_push_ready_0 & io_push_valid_0; // @[Decoupled.scala:51:35] wire [63:0] _valid_set_T = 64'h1 << valid_set_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [35:0] _valid_set_T_1 = _valid_set_T[35:0]; // @[OneHot.scala:65:{12,27}] assign valid_set = data_MPORT_en ? _valid_set_T_1 : 36'h0; // @[OneHot.scala:65:27] assign used_set = data_MPORT_en ? freeOH[27:0] : 28'h0; // @[Decoupled.scala:51:35] wire [35:0] _GEN = {30'h0, io_pop_bits_0}; // @[ListBuffer.scala:36:7, :79:24] wire [35:0] _pop_valid_T = valid >> _GEN; // @[ListBuffer.scala:47:22, :79:24] wire pop_valid = _pop_valid_T[0]; // @[ListBuffer.scala:79:24]
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u_3 : input clock : Clock input reset : Reset output auto : { } wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}[0] wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}[0]
module TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u_3( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset // @[Xbar.scala:74:9] ); endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_6 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_uncommonBits_T = or(request.source, UInt<2>(0h0)) node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 1, 0) node _req_clientBit_T = shr(request.source, 2) node _req_clientBit_T_1 = eq(_req_clientBit_T, UInt<4>(0h8)) node _req_clientBit_T_2 = leq(UInt<1>(0h0), req_clientBit_uncommonBits) node _req_clientBit_T_3 = and(_req_clientBit_T_1, _req_clientBit_T_2) node _req_clientBit_T_4 = leq(req_clientBit_uncommonBits, UInt<2>(0h2)) node req_clientBit = and(_req_clientBit_T_3, _req_clientBit_T_4) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<2>(0h0)) node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 1, 0) node _probe_bit_T = shr(io.sinkc.bits.source, 2) node _probe_bit_T_1 = eq(_probe_bit_T, UInt<4>(0h8)) node _probe_bit_T_2 = leq(UInt<1>(0h0), probe_bit_uncommonBits) node _probe_bit_T_3 = and(_probe_bit_T_1, _probe_bit_T_2) node _probe_bit_T_4 = leq(probe_bit_uncommonBits, UInt<2>(0h2)) node probe_bit = and(_probe_bit_T_3, _probe_bit_T_4) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<2>(0h0)) node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 1, 0) node _new_clientBit_T = shr(new_request.source, 2) node _new_clientBit_T_1 = eq(_new_clientBit_T, UInt<4>(0h8)) node _new_clientBit_T_2 = leq(UInt<1>(0h0), new_clientBit_uncommonBits) node _new_clientBit_T_3 = and(_new_clientBit_T_1, _new_clientBit_T_2) node _new_clientBit_T_4 = leq(new_clientBit_uncommonBits, UInt<2>(0h2)) node new_clientBit = and(_new_clientBit_T_3, _new_clientBit_T_4) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)
module MSHR_6( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire excluded_client = 1'h0; // @[MSHR.scala:279:28] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire allocate_as_full_prio_1 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire new_request_prio_1 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _io_schedule_bits_b_bits_clients_T = 1'h1; // @[MSHR.scala:289:53] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _last_probe_T_1 = 1'h1; // @[MSHR.scala:459:66] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [5:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [5:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [1:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _req_clientBit_T = request_source[5:2]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T == 4'h8; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_4 = req_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire req_clientBit = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:56:48] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:56:48] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:56:48] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [1:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _probe_bit_T = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T == 4'h8; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_4 = probe_bit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire probe_bit = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:56:48] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:56:48] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [1:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _new_clientBit_T = new_request_source[5:2]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T == 4'h8; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_4 = new_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire new_clientBit = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:56:48] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module Tile_59 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_315 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_59( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_315 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_15 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) when _T_6 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_2 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_2 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_7 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_8 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_9 = neq(_T_8, UInt<1>(0h0)) node _T_10 = or(_T_7, _T_9) node _T_11 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_12 = and(_T_10, _T_11) when _T_12 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_13 = or(prs2_wakeups_0, prs2_wakeups_1) when _T_13 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_2 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_2 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_14 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_15 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_16 = neq(_T_15, UInt<1>(0h0)) node _T_17 = or(_T_14, _T_16) node _T_18 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_19 = and(_T_17, _T_18) when _T_19 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_20 = or(prs3_wakeups_0, prs3_wakeups_1) when _T_20 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_2 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_21 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_22 = and(io.pred_wakeup_port.valid, _T_21) when _T_22 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h1)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_23 = eq(io.squash_grant, UInt<1>(0h0)) node _T_24 = and(io.grant, _T_23) when _T_24 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_25 = and(slot_valid, slot_uop.iw_issued) when _T_25 : connect next_valid, rebusied
module IssueSlot_15( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire rebusied_prs1 = 1'h0; // @[issue-slot.scala:92:31] wire rebusied_prs2 = 1'h0; // @[issue-slot.scala:93:31] wire rebusied = 1'h0; // @[issue-slot.scala:94:32] wire prs1_rebusys_0 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_0 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] next_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] _next_uop_iw_p1_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] wire _iss_ready_T_6 = slot_uop_prs3_busy; // @[issue-slot.scala:56:21, :136:131] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_2 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} cmem ram : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>} [15] wire _valids_WIRE : UInt<1>[15] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) connect _valids_WIRE[8], UInt<1>(0h0) connect _valids_WIRE[9], UInt<1>(0h0) connect _valids_WIRE[10], UInt<1>(0h0) connect _valids_WIRE[11], UInt<1>(0h0) connect _valids_WIRE[12], UInt<1>(0h0) connect _valids_WIRE[13], UInt<1>(0h0) connect _valids_WIRE[14], UInt<1>(0h0) regreset valids : UInt<1>[15], clock, reset, _valids_WIRE reg uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[15], clock regreset enq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset deq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _io_empty_T = eq(maybe_full, UInt<1>(0h0)) node _io_empty_T_1 = and(ptr_match, _io_empty_T) connect io.empty, _io_empty_T_1 node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) node _do_enq_T_1 = and(io.brupdate.b1.mispredict_mask, io.enq.bits.uop.br_mask) node _do_enq_T_2 = neq(_do_enq_T_1, UInt<1>(0h0)) node _do_enq_T_3 = or(_do_enq_T_2, UInt<1>(0h0)) node _do_enq_T_4 = eq(_do_enq_T_3, UInt<1>(0h0)) node _do_enq_T_5 = and(_do_enq_T, _do_enq_T_4) node _do_enq_T_6 = and(io.flush, io.enq.bits.uop.uses_ldq) node _do_enq_T_7 = eq(_do_enq_T_6, UInt<1>(0h0)) node _do_enq_T_8 = and(_do_enq_T_5, _do_enq_T_7) wire do_enq : UInt<1> connect do_enq, _do_enq_T_8 node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0)) node _do_deq_T_1 = or(io.deq.ready, _do_deq_T) node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0)) node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2) wire do_deq : UInt<1> connect do_deq, _do_deq_T_3 node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask) node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0)) node _valids_0_T_2 = or(_valids_0_T_1, UInt<1>(0h0)) node _valids_0_T_3 = eq(_valids_0_T_2, UInt<1>(0h0)) node _valids_0_T_4 = and(valids[0], _valids_0_T_3) node _valids_0_T_5 = and(io.flush, uops[0].uses_ldq) node _valids_0_T_6 = eq(_valids_0_T_5, UInt<1>(0h0)) node _valids_0_T_7 = and(_valids_0_T_4, _valids_0_T_6) connect valids[0], _valids_0_T_7 when valids[0] : node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T) connect uops[0].br_mask, _uops_0_br_mask_T_1 node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask) node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0)) node _valids_1_T_2 = or(_valids_1_T_1, UInt<1>(0h0)) node _valids_1_T_3 = eq(_valids_1_T_2, UInt<1>(0h0)) node _valids_1_T_4 = and(valids[1], _valids_1_T_3) node _valids_1_T_5 = and(io.flush, uops[1].uses_ldq) node _valids_1_T_6 = eq(_valids_1_T_5, UInt<1>(0h0)) node _valids_1_T_7 = and(_valids_1_T_4, _valids_1_T_6) connect valids[1], _valids_1_T_7 when valids[1] : node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T) connect uops[1].br_mask, _uops_1_br_mask_T_1 node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask) node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0)) node _valids_2_T_2 = or(_valids_2_T_1, UInt<1>(0h0)) node _valids_2_T_3 = eq(_valids_2_T_2, UInt<1>(0h0)) node _valids_2_T_4 = and(valids[2], _valids_2_T_3) node _valids_2_T_5 = and(io.flush, uops[2].uses_ldq) node _valids_2_T_6 = eq(_valids_2_T_5, UInt<1>(0h0)) node _valids_2_T_7 = and(_valids_2_T_4, _valids_2_T_6) connect valids[2], _valids_2_T_7 when valids[2] : node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T) connect uops[2].br_mask, _uops_2_br_mask_T_1 node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask) node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0)) node _valids_3_T_2 = or(_valids_3_T_1, UInt<1>(0h0)) node _valids_3_T_3 = eq(_valids_3_T_2, UInt<1>(0h0)) node _valids_3_T_4 = and(valids[3], _valids_3_T_3) node _valids_3_T_5 = and(io.flush, uops[3].uses_ldq) node _valids_3_T_6 = eq(_valids_3_T_5, UInt<1>(0h0)) node _valids_3_T_7 = and(_valids_3_T_4, _valids_3_T_6) connect valids[3], _valids_3_T_7 when valids[3] : node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T) connect uops[3].br_mask, _uops_3_br_mask_T_1 node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask) node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0)) node _valids_4_T_2 = or(_valids_4_T_1, UInt<1>(0h0)) node _valids_4_T_3 = eq(_valids_4_T_2, UInt<1>(0h0)) node _valids_4_T_4 = and(valids[4], _valids_4_T_3) node _valids_4_T_5 = and(io.flush, uops[4].uses_ldq) node _valids_4_T_6 = eq(_valids_4_T_5, UInt<1>(0h0)) node _valids_4_T_7 = and(_valids_4_T_4, _valids_4_T_6) connect valids[4], _valids_4_T_7 when valids[4] : node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T) connect uops[4].br_mask, _uops_4_br_mask_T_1 node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask) node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0)) node _valids_5_T_2 = or(_valids_5_T_1, UInt<1>(0h0)) node _valids_5_T_3 = eq(_valids_5_T_2, UInt<1>(0h0)) node _valids_5_T_4 = and(valids[5], _valids_5_T_3) node _valids_5_T_5 = and(io.flush, uops[5].uses_ldq) node _valids_5_T_6 = eq(_valids_5_T_5, UInt<1>(0h0)) node _valids_5_T_7 = and(_valids_5_T_4, _valids_5_T_6) connect valids[5], _valids_5_T_7 when valids[5] : node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T) connect uops[5].br_mask, _uops_5_br_mask_T_1 node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask) node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0)) node _valids_6_T_2 = or(_valids_6_T_1, UInt<1>(0h0)) node _valids_6_T_3 = eq(_valids_6_T_2, UInt<1>(0h0)) node _valids_6_T_4 = and(valids[6], _valids_6_T_3) node _valids_6_T_5 = and(io.flush, uops[6].uses_ldq) node _valids_6_T_6 = eq(_valids_6_T_5, UInt<1>(0h0)) node _valids_6_T_7 = and(_valids_6_T_4, _valids_6_T_6) connect valids[6], _valids_6_T_7 when valids[6] : node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T) connect uops[6].br_mask, _uops_6_br_mask_T_1 node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask) node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0)) node _valids_7_T_2 = or(_valids_7_T_1, UInt<1>(0h0)) node _valids_7_T_3 = eq(_valids_7_T_2, UInt<1>(0h0)) node _valids_7_T_4 = and(valids[7], _valids_7_T_3) node _valids_7_T_5 = and(io.flush, uops[7].uses_ldq) node _valids_7_T_6 = eq(_valids_7_T_5, UInt<1>(0h0)) node _valids_7_T_7 = and(_valids_7_T_4, _valids_7_T_6) connect valids[7], _valids_7_T_7 when valids[7] : node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T) connect uops[7].br_mask, _uops_7_br_mask_T_1 node _valids_8_T = and(io.brupdate.b1.mispredict_mask, uops[8].br_mask) node _valids_8_T_1 = neq(_valids_8_T, UInt<1>(0h0)) node _valids_8_T_2 = or(_valids_8_T_1, UInt<1>(0h0)) node _valids_8_T_3 = eq(_valids_8_T_2, UInt<1>(0h0)) node _valids_8_T_4 = and(valids[8], _valids_8_T_3) node _valids_8_T_5 = and(io.flush, uops[8].uses_ldq) node _valids_8_T_6 = eq(_valids_8_T_5, UInt<1>(0h0)) node _valids_8_T_7 = and(_valids_8_T_4, _valids_8_T_6) connect valids[8], _valids_8_T_7 when valids[8] : node _uops_8_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_8_br_mask_T_1 = and(uops[8].br_mask, _uops_8_br_mask_T) connect uops[8].br_mask, _uops_8_br_mask_T_1 node _valids_9_T = and(io.brupdate.b1.mispredict_mask, uops[9].br_mask) node _valids_9_T_1 = neq(_valids_9_T, UInt<1>(0h0)) node _valids_9_T_2 = or(_valids_9_T_1, UInt<1>(0h0)) node _valids_9_T_3 = eq(_valids_9_T_2, UInt<1>(0h0)) node _valids_9_T_4 = and(valids[9], _valids_9_T_3) node _valids_9_T_5 = and(io.flush, uops[9].uses_ldq) node _valids_9_T_6 = eq(_valids_9_T_5, UInt<1>(0h0)) node _valids_9_T_7 = and(_valids_9_T_4, _valids_9_T_6) connect valids[9], _valids_9_T_7 when valids[9] : node _uops_9_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_9_br_mask_T_1 = and(uops[9].br_mask, _uops_9_br_mask_T) connect uops[9].br_mask, _uops_9_br_mask_T_1 node _valids_10_T = and(io.brupdate.b1.mispredict_mask, uops[10].br_mask) node _valids_10_T_1 = neq(_valids_10_T, UInt<1>(0h0)) node _valids_10_T_2 = or(_valids_10_T_1, UInt<1>(0h0)) node _valids_10_T_3 = eq(_valids_10_T_2, UInt<1>(0h0)) node _valids_10_T_4 = and(valids[10], _valids_10_T_3) node _valids_10_T_5 = and(io.flush, uops[10].uses_ldq) node _valids_10_T_6 = eq(_valids_10_T_5, UInt<1>(0h0)) node _valids_10_T_7 = and(_valids_10_T_4, _valids_10_T_6) connect valids[10], _valids_10_T_7 when valids[10] : node _uops_10_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_10_br_mask_T_1 = and(uops[10].br_mask, _uops_10_br_mask_T) connect uops[10].br_mask, _uops_10_br_mask_T_1 node _valids_11_T = and(io.brupdate.b1.mispredict_mask, uops[11].br_mask) node _valids_11_T_1 = neq(_valids_11_T, UInt<1>(0h0)) node _valids_11_T_2 = or(_valids_11_T_1, UInt<1>(0h0)) node _valids_11_T_3 = eq(_valids_11_T_2, UInt<1>(0h0)) node _valids_11_T_4 = and(valids[11], _valids_11_T_3) node _valids_11_T_5 = and(io.flush, uops[11].uses_ldq) node _valids_11_T_6 = eq(_valids_11_T_5, UInt<1>(0h0)) node _valids_11_T_7 = and(_valids_11_T_4, _valids_11_T_6) connect valids[11], _valids_11_T_7 when valids[11] : node _uops_11_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_11_br_mask_T_1 = and(uops[11].br_mask, _uops_11_br_mask_T) connect uops[11].br_mask, _uops_11_br_mask_T_1 node _valids_12_T = and(io.brupdate.b1.mispredict_mask, uops[12].br_mask) node _valids_12_T_1 = neq(_valids_12_T, UInt<1>(0h0)) node _valids_12_T_2 = or(_valids_12_T_1, UInt<1>(0h0)) node _valids_12_T_3 = eq(_valids_12_T_2, UInt<1>(0h0)) node _valids_12_T_4 = and(valids[12], _valids_12_T_3) node _valids_12_T_5 = and(io.flush, uops[12].uses_ldq) node _valids_12_T_6 = eq(_valids_12_T_5, UInt<1>(0h0)) node _valids_12_T_7 = and(_valids_12_T_4, _valids_12_T_6) connect valids[12], _valids_12_T_7 when valids[12] : node _uops_12_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_12_br_mask_T_1 = and(uops[12].br_mask, _uops_12_br_mask_T) connect uops[12].br_mask, _uops_12_br_mask_T_1 node _valids_13_T = and(io.brupdate.b1.mispredict_mask, uops[13].br_mask) node _valids_13_T_1 = neq(_valids_13_T, UInt<1>(0h0)) node _valids_13_T_2 = or(_valids_13_T_1, UInt<1>(0h0)) node _valids_13_T_3 = eq(_valids_13_T_2, UInt<1>(0h0)) node _valids_13_T_4 = and(valids[13], _valids_13_T_3) node _valids_13_T_5 = and(io.flush, uops[13].uses_ldq) node _valids_13_T_6 = eq(_valids_13_T_5, UInt<1>(0h0)) node _valids_13_T_7 = and(_valids_13_T_4, _valids_13_T_6) connect valids[13], _valids_13_T_7 when valids[13] : node _uops_13_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_13_br_mask_T_1 = and(uops[13].br_mask, _uops_13_br_mask_T) connect uops[13].br_mask, _uops_13_br_mask_T_1 node _valids_14_T = and(io.brupdate.b1.mispredict_mask, uops[14].br_mask) node _valids_14_T_1 = neq(_valids_14_T, UInt<1>(0h0)) node _valids_14_T_2 = or(_valids_14_T_1, UInt<1>(0h0)) node _valids_14_T_3 = eq(_valids_14_T_2, UInt<1>(0h0)) node _valids_14_T_4 = and(valids[14], _valids_14_T_3) node _valids_14_T_5 = and(io.flush, uops[14].uses_ldq) node _valids_14_T_6 = eq(_valids_14_T_5, UInt<1>(0h0)) node _valids_14_T_7 = and(_valids_14_T_4, _valids_14_T_6) connect valids[14], _valids_14_T_7 when valids[14] : node _uops_14_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_14_br_mask_T_1 = and(uops[14].br_mask, _uops_14_br_mask_T) connect uops[14].br_mask, _uops_14_br_mask_T_1 when do_enq : infer mport MPORT = ram[enq_ptr_value], clock connect MPORT, io.enq.bits connect valids[enq_ptr_value], UInt<1>(0h1) connect uops[enq_ptr_value], io.enq.bits.uop node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T) connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1 node wrap = eq(enq_ptr_value, UInt<4>(0he)) node _value_T = add(enq_ptr_value, UInt<1>(0h1)) node _value_T_1 = tail(_value_T, 1) connect enq_ptr_value, _value_T_1 when wrap : connect enq_ptr_value, UInt<1>(0h0) when do_deq : connect valids[deq_ptr_value], UInt<1>(0h0) node wrap_1 = eq(deq_ptr_value, UInt<4>(0he)) node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) node _value_T_3 = tail(_value_T_2, 1) connect deq_ptr_value, _value_T_3 when wrap_1 : connect deq_ptr_value, UInt<1>(0h0) node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>} infer mport out_MPORT = ram[deq_ptr_value], clock connect out, out_MPORT connect out.uop, uops[deq_ptr_value] node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0)) node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value]) connect io.deq.valid, _io_deq_valid_T_1 connect io.deq.bits, out node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = mux(maybe_full, UInt<4>(0hf), UInt<1>(0h0)) node _io_count_T_1 = gt(deq_ptr_value, enq_ptr_value) node _io_count_T_2 = add(UInt<4>(0hf), ptr_diff) node _io_count_T_3 = tail(_io_count_T_2, 1) node _io_count_T_4 = mux(_io_count_T_1, _io_count_T_3, ptr_diff) node _io_count_T_5 = mux(ptr_match, _io_count_T, _io_count_T_4) connect io.count, _io_count_T_5
module BranchKillableQueue_2( // @[util.scala:458:7] input clock, // @[util.scala:458:7] input reset, // @[util.scala:458:7] output io_enq_ready, // @[util.scala:463:14] input io_enq_valid, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14] input io_enq_bits_uop_is_rvc, // @[util.scala:463:14] input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14] input [11:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14] input io_enq_bits_uop_is_sfb, // @[util.scala:463:14] input io_enq_bits_uop_is_fence, // @[util.scala:463:14] input io_enq_bits_uop_is_fencei, // @[util.scala:463:14] input io_enq_bits_uop_is_sfence, // @[util.scala:463:14] input io_enq_bits_uop_is_amo, // @[util.scala:463:14] input io_enq_bits_uop_is_eret, // @[util.scala:463:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_enq_bits_uop_is_rocc, // @[util.scala:463:14] input io_enq_bits_uop_is_mov, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14] input io_enq_bits_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14] input io_enq_bits_uop_taken, // @[util.scala:463:14] input io_enq_bits_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_pdst, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_prs1, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_prs2, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_prs3, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_ppred, // @[util.scala:463:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14] input io_enq_bits_uop_exception, // @[util.scala:463:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14] input io_enq_bits_uop_mem_signed, // @[util.scala:463:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14] input io_enq_bits_uop_uses_stq, // @[util.scala:463:14] input io_enq_bits_uop_is_unique, // @[util.scala:463:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14] input io_enq_bits_uop_frs3_en, // @[util.scala:463:14] input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14] input io_enq_bits_uop_fp_val, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14] input [39:0] io_enq_bits_addr, // @[util.scala:463:14] input [63:0] io_enq_bits_data, // @[util.scala:463:14] input io_enq_bits_is_hella, // @[util.scala:463:14] input io_enq_bits_tag_match, // @[util.scala:463:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14] input [19:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_way_en, // @[util.scala:463:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14] input io_deq_ready, // @[util.scala:463:14] output io_deq_valid, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14] output io_deq_bits_uop_is_rvc, // @[util.scala:463:14] output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14] output [11:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14] output io_deq_bits_uop_is_sfb, // @[util.scala:463:14] output io_deq_bits_uop_is_fence, // @[util.scala:463:14] output io_deq_bits_uop_is_fencei, // @[util.scala:463:14] output io_deq_bits_uop_is_sfence, // @[util.scala:463:14] output io_deq_bits_uop_is_amo, // @[util.scala:463:14] output io_deq_bits_uop_is_eret, // @[util.scala:463:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] output io_deq_bits_uop_is_rocc, // @[util.scala:463:14] output io_deq_bits_uop_is_mov, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14] output io_deq_bits_uop_edge_inst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14] output io_deq_bits_uop_taken, // @[util.scala:463:14] output io_deq_bits_uop_imm_rename, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_pdst, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_prs1, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_prs2, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_prs3, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_ppred, // @[util.scala:463:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14] output io_deq_bits_uop_exception, // @[util.scala:463:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14] output io_deq_bits_uop_mem_signed, // @[util.scala:463:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14] output io_deq_bits_uop_uses_stq, // @[util.scala:463:14] output io_deq_bits_uop_is_unique, // @[util.scala:463:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14] output io_deq_bits_uop_frs3_en, // @[util.scala:463:14] output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14] output io_deq_bits_uop_fp_val, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14] output [39:0] io_deq_bits_addr, // @[util.scala:463:14] output [63:0] io_deq_bits_data, // @[util.scala:463:14] output io_deq_bits_is_hella, // @[util.scala:463:14] output io_deq_bits_tag_match, // @[util.scala:463:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14] output [19:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_way_en, // @[util.scala:463:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14] input [11:0] io_brupdate_b1_resolve_mask, // @[util.scala:463:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[util.scala:463:14] input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:463:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:463:14] input io_brupdate_b2_uop_is_rvc, // @[util.scala:463:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:463:14] input io_brupdate_b2_uop_iq_type_0, // @[util.scala:463:14] input io_brupdate_b2_uop_iq_type_1, // @[util.scala:463:14] input io_brupdate_b2_uop_iq_type_2, // @[util.scala:463:14] input io_brupdate_b2_uop_iq_type_3, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_0, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_1, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_2, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_3, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_4, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_5, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_6, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_7, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_8, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_9, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_issued, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[util.scala:463:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[util.scala:463:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:463:14] input [3:0] io_brupdate_b2_uop_br_type, // @[util.scala:463:14] input io_brupdate_b2_uop_is_sfb, // @[util.scala:463:14] input io_brupdate_b2_uop_is_fence, // @[util.scala:463:14] input io_brupdate_b2_uop_is_fencei, // @[util.scala:463:14] input io_brupdate_b2_uop_is_sfence, // @[util.scala:463:14] input io_brupdate_b2_uop_is_amo, // @[util.scala:463:14] input io_brupdate_b2_uop_is_eret, // @[util.scala:463:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_brupdate_b2_uop_is_rocc, // @[util.scala:463:14] input io_brupdate_b2_uop_is_mov, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:463:14] input io_brupdate_b2_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:463:14] input io_brupdate_b2_uop_taken, // @[util.scala:463:14] input io_brupdate_b2_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_pimm, // @[util.scala:463:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:463:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:463:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:463:14] input io_brupdate_b2_uop_prs1_busy, // @[util.scala:463:14] input io_brupdate_b2_uop_prs2_busy, // @[util.scala:463:14] input io_brupdate_b2_uop_prs3_busy, // @[util.scala:463:14] input io_brupdate_b2_uop_ppred_busy, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:463:14] input io_brupdate_b2_uop_exception, // @[util.scala:463:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:463:14] input io_brupdate_b2_uop_mem_signed, // @[util.scala:463:14] input io_brupdate_b2_uop_uses_ldq, // @[util.scala:463:14] input io_brupdate_b2_uop_uses_stq, // @[util.scala:463:14] input io_brupdate_b2_uop_is_unique, // @[util.scala:463:14] input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[util.scala:463:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:463:14] input io_brupdate_b2_uop_frs3_en, // @[util.scala:463:14] input io_brupdate_b2_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_val, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[util.scala:463:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:463:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:463:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:463:14] input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:463:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:463:14] input io_brupdate_b2_mispredict, // @[util.scala:463:14] input io_brupdate_b2_taken, // @[util.scala:463:14] input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:463:14] input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:463:14] input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:463:14] input [20:0] io_brupdate_b2_target_offset, // @[util.scala:463:14] input io_flush, // @[util.scala:463:14] output io_empty, // @[util.scala:463:14] output [3:0] io_count // @[util.scala:463:14] ); wire [136:0] _ram_ext_R0_data; // @[util.scala:503:22] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7] wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7] wire [11:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7] wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7] wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7] wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7] wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7] wire [39:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7] wire [19:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:458:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:458:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:458:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:458:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[util.scala:458:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:458:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:458:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:458:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[util.scala:458:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:458:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:458:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:458:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:458:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:458:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[util.scala:458:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:458:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:458:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:458:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:458:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:458:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:458:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:458:7] wire io_flush_0 = io_flush; // @[util.scala:458:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_1 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_2 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_3 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_4 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_5 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_6 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_7 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_8 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_9 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_10 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_11 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_12 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_13 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_14 = 1'h0; // @[util.scala:504:34] wire _io_enq_ready_T; // @[util.scala:543:21] wire _io_deq_valid_T_1; // @[util.scala:548:42] wire [31:0] out_uop_inst; // @[util.scala:545:19] wire [31:0] out_uop_debug_inst; // @[util.scala:545:19] wire out_uop_is_rvc; // @[util.scala:545:19] wire [39:0] out_uop_debug_pc; // @[util.scala:545:19] wire out_uop_iq_type_0; // @[util.scala:545:19] wire out_uop_iq_type_1; // @[util.scala:545:19] wire out_uop_iq_type_2; // @[util.scala:545:19] wire out_uop_iq_type_3; // @[util.scala:545:19] wire out_uop_fu_code_0; // @[util.scala:545:19] wire out_uop_fu_code_1; // @[util.scala:545:19] wire out_uop_fu_code_2; // @[util.scala:545:19] wire out_uop_fu_code_3; // @[util.scala:545:19] wire out_uop_fu_code_4; // @[util.scala:545:19] wire out_uop_fu_code_5; // @[util.scala:545:19] wire out_uop_fu_code_6; // @[util.scala:545:19] wire out_uop_fu_code_7; // @[util.scala:545:19] wire out_uop_fu_code_8; // @[util.scala:545:19] wire out_uop_fu_code_9; // @[util.scala:545:19] wire out_uop_iw_issued; // @[util.scala:545:19] wire out_uop_iw_issued_partial_agen; // @[util.scala:545:19] wire out_uop_iw_issued_partial_dgen; // @[util.scala:545:19] wire [1:0] out_uop_iw_p1_speculative_child; // @[util.scala:545:19] wire [1:0] out_uop_iw_p2_speculative_child; // @[util.scala:545:19] wire out_uop_iw_p1_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p2_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p3_bypass_hint; // @[util.scala:545:19] wire [1:0] out_uop_dis_col_sel; // @[util.scala:545:19] wire [11:0] out_uop_br_mask; // @[util.scala:545:19] wire [3:0] out_uop_br_tag; // @[util.scala:545:19] wire [3:0] out_uop_br_type; // @[util.scala:545:19] wire out_uop_is_sfb; // @[util.scala:545:19] wire out_uop_is_fence; // @[util.scala:545:19] wire out_uop_is_fencei; // @[util.scala:545:19] wire out_uop_is_sfence; // @[util.scala:545:19] wire out_uop_is_amo; // @[util.scala:545:19] wire out_uop_is_eret; // @[util.scala:545:19] wire out_uop_is_sys_pc2epc; // @[util.scala:545:19] wire out_uop_is_rocc; // @[util.scala:545:19] wire out_uop_is_mov; // @[util.scala:545:19] wire [4:0] out_uop_ftq_idx; // @[util.scala:545:19] wire out_uop_edge_inst; // @[util.scala:545:19] wire [5:0] out_uop_pc_lob; // @[util.scala:545:19] wire out_uop_taken; // @[util.scala:545:19] wire out_uop_imm_rename; // @[util.scala:545:19] wire [2:0] out_uop_imm_sel; // @[util.scala:545:19] wire [4:0] out_uop_pimm; // @[util.scala:545:19] wire [19:0] out_uop_imm_packed; // @[util.scala:545:19] wire [1:0] out_uop_op1_sel; // @[util.scala:545:19] wire [2:0] out_uop_op2_sel; // @[util.scala:545:19] wire out_uop_fp_ctrl_ldst; // @[util.scala:545:19] wire out_uop_fp_ctrl_wen; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren1; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren2; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren3; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap12; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap23; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:545:19] wire out_uop_fp_ctrl_fromint; // @[util.scala:545:19] wire out_uop_fp_ctrl_toint; // @[util.scala:545:19] wire out_uop_fp_ctrl_fastpipe; // @[util.scala:545:19] wire out_uop_fp_ctrl_fma; // @[util.scala:545:19] wire out_uop_fp_ctrl_div; // @[util.scala:545:19] wire out_uop_fp_ctrl_sqrt; // @[util.scala:545:19] wire out_uop_fp_ctrl_wflags; // @[util.scala:545:19] wire out_uop_fp_ctrl_vec; // @[util.scala:545:19] wire [5:0] out_uop_rob_idx; // @[util.scala:545:19] wire [3:0] out_uop_ldq_idx; // @[util.scala:545:19] wire [3:0] out_uop_stq_idx; // @[util.scala:545:19] wire [1:0] out_uop_rxq_idx; // @[util.scala:545:19] wire [6:0] out_uop_pdst; // @[util.scala:545:19] wire [6:0] out_uop_prs1; // @[util.scala:545:19] wire [6:0] out_uop_prs2; // @[util.scala:545:19] wire [6:0] out_uop_prs3; // @[util.scala:545:19] wire [4:0] out_uop_ppred; // @[util.scala:545:19] wire out_uop_prs1_busy; // @[util.scala:545:19] wire out_uop_prs2_busy; // @[util.scala:545:19] wire out_uop_prs3_busy; // @[util.scala:545:19] wire out_uop_ppred_busy; // @[util.scala:545:19] wire [6:0] out_uop_stale_pdst; // @[util.scala:545:19] wire out_uop_exception; // @[util.scala:545:19] wire [63:0] out_uop_exc_cause; // @[util.scala:545:19] wire [4:0] out_uop_mem_cmd; // @[util.scala:545:19] wire [1:0] out_uop_mem_size; // @[util.scala:545:19] wire out_uop_mem_signed; // @[util.scala:545:19] wire out_uop_uses_ldq; // @[util.scala:545:19] wire out_uop_uses_stq; // @[util.scala:545:19] wire out_uop_is_unique; // @[util.scala:545:19] wire out_uop_flush_on_commit; // @[util.scala:545:19] wire [2:0] out_uop_csr_cmd; // @[util.scala:545:19] wire out_uop_ldst_is_rs1; // @[util.scala:545:19] wire [5:0] out_uop_ldst; // @[util.scala:545:19] wire [5:0] out_uop_lrs1; // @[util.scala:545:19] wire [5:0] out_uop_lrs2; // @[util.scala:545:19] wire [5:0] out_uop_lrs3; // @[util.scala:545:19] wire [1:0] out_uop_dst_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:545:19] wire out_uop_frs3_en; // @[util.scala:545:19] wire out_uop_fcn_dw; // @[util.scala:545:19] wire [4:0] out_uop_fcn_op; // @[util.scala:545:19] wire out_uop_fp_val; // @[util.scala:545:19] wire [2:0] out_uop_fp_rm; // @[util.scala:545:19] wire [1:0] out_uop_fp_typ; // @[util.scala:545:19] wire out_uop_xcpt_pf_if; // @[util.scala:545:19] wire out_uop_xcpt_ae_if; // @[util.scala:545:19] wire out_uop_xcpt_ma_if; // @[util.scala:545:19] wire out_uop_bp_debug_if; // @[util.scala:545:19] wire out_uop_bp_xcpt_if; // @[util.scala:545:19] wire [2:0] out_uop_debug_fsrc; // @[util.scala:545:19] wire [2:0] out_uop_debug_tsrc; // @[util.scala:545:19] wire [39:0] out_addr; // @[util.scala:545:19] wire [63:0] out_data; // @[util.scala:545:19] wire out_is_hella; // @[util.scala:545:19] wire out_tag_match; // @[util.scala:545:19] wire [1:0] out_old_meta_coh_state; // @[util.scala:545:19] wire [19:0] out_old_meta_tag; // @[util.scala:545:19] wire [3:0] out_way_en; // @[util.scala:545:19] wire [4:0] out_sdq_id; // @[util.scala:545:19] wire _io_empty_T_1; // @[util.scala:512:27] wire [3:0] _io_count_T_5; // @[util.scala:556:22] wire io_enq_ready_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] wire [11:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] wire io_deq_bits_uop_taken_0; // @[util.scala:458:7] wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] wire io_deq_bits_uop_exception_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] wire [39:0] io_deq_bits_addr_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7] wire io_deq_bits_is_hella_0; // @[util.scala:458:7] wire io_deq_bits_tag_match_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_way_en_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7] wire io_deq_valid_0; // @[util.scala:458:7] wire io_empty_0; // @[util.scala:458:7] wire [3:0] io_count_0; // @[util.scala:458:7] assign out_addr = _ram_ext_R0_data[39:0]; // @[util.scala:503:22, :545:19] assign out_data = _ram_ext_R0_data[103:40]; // @[util.scala:503:22, :545:19] assign out_is_hella = _ram_ext_R0_data[104]; // @[util.scala:503:22, :545:19] assign out_tag_match = _ram_ext_R0_data[105]; // @[util.scala:503:22, :545:19] assign out_old_meta_coh_state = _ram_ext_R0_data[107:106]; // @[util.scala:503:22, :545:19] assign out_old_meta_tag = _ram_ext_R0_data[127:108]; // @[util.scala:503:22, :545:19] assign out_way_en = _ram_ext_R0_data[131:128]; // @[util.scala:503:22, :545:19] assign out_sdq_id = _ram_ext_R0_data[136:132]; // @[util.scala:503:22, :545:19] reg valids_0; // @[util.scala:504:26] reg valids_1; // @[util.scala:504:26] reg valids_2; // @[util.scala:504:26] reg valids_3; // @[util.scala:504:26] reg valids_4; // @[util.scala:504:26] reg valids_5; // @[util.scala:504:26] reg valids_6; // @[util.scala:504:26] reg valids_7; // @[util.scala:504:26] reg valids_8; // @[util.scala:504:26] reg valids_9; // @[util.scala:504:26] reg valids_10; // @[util.scala:504:26] reg valids_11; // @[util.scala:504:26] reg valids_12; // @[util.scala:504:26] reg valids_13; // @[util.scala:504:26] reg valids_14; // @[util.scala:504:26] reg [31:0] uops_0_inst; // @[util.scala:505:22] reg [31:0] uops_0_debug_inst; // @[util.scala:505:22] reg uops_0_is_rvc; // @[util.scala:505:22] reg [39:0] uops_0_debug_pc; // @[util.scala:505:22] reg uops_0_iq_type_0; // @[util.scala:505:22] reg uops_0_iq_type_1; // @[util.scala:505:22] reg uops_0_iq_type_2; // @[util.scala:505:22] reg uops_0_iq_type_3; // @[util.scala:505:22] reg uops_0_fu_code_0; // @[util.scala:505:22] reg uops_0_fu_code_1; // @[util.scala:505:22] reg uops_0_fu_code_2; // @[util.scala:505:22] reg uops_0_fu_code_3; // @[util.scala:505:22] reg uops_0_fu_code_4; // @[util.scala:505:22] reg uops_0_fu_code_5; // @[util.scala:505:22] reg uops_0_fu_code_6; // @[util.scala:505:22] reg uops_0_fu_code_7; // @[util.scala:505:22] reg uops_0_fu_code_8; // @[util.scala:505:22] reg uops_0_fu_code_9; // @[util.scala:505:22] reg uops_0_iw_issued; // @[util.scala:505:22] reg uops_0_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_0_iw_issued_partial_dgen; // @[util.scala:505:22] reg [1:0] uops_0_iw_p1_speculative_child; // @[util.scala:505:22] reg [1:0] uops_0_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_0_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p3_bypass_hint; // @[util.scala:505:22] reg [1:0] uops_0_dis_col_sel; // @[util.scala:505:22] reg [11:0] uops_0_br_mask; // @[util.scala:505:22] reg [3:0] uops_0_br_tag; // @[util.scala:505:22] reg [3:0] uops_0_br_type; // @[util.scala:505:22] reg uops_0_is_sfb; // @[util.scala:505:22] reg uops_0_is_fence; // @[util.scala:505:22] reg uops_0_is_fencei; // @[util.scala:505:22] reg uops_0_is_sfence; // @[util.scala:505:22] reg uops_0_is_amo; // @[util.scala:505:22] reg uops_0_is_eret; // @[util.scala:505:22] reg uops_0_is_sys_pc2epc; // @[util.scala:505:22] reg uops_0_is_rocc; // @[util.scala:505:22] reg uops_0_is_mov; // @[util.scala:505:22] reg [4:0] uops_0_ftq_idx; // @[util.scala:505:22] reg uops_0_edge_inst; // @[util.scala:505:22] reg [5:0] uops_0_pc_lob; // @[util.scala:505:22] reg uops_0_taken; // @[util.scala:505:22] reg uops_0_imm_rename; // @[util.scala:505:22] reg [2:0] uops_0_imm_sel; // @[util.scala:505:22] reg [4:0] uops_0_pimm; // @[util.scala:505:22] reg [19:0] uops_0_imm_packed; // @[util.scala:505:22] reg [1:0] uops_0_op1_sel; // @[util.scala:505:22] reg [2:0] uops_0_op2_sel; // @[util.scala:505:22] reg uops_0_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_0_fp_ctrl_wen; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_0_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_0_fp_ctrl_toint; // @[util.scala:505:22] reg uops_0_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_0_fp_ctrl_fma; // @[util.scala:505:22] reg uops_0_fp_ctrl_div; // @[util.scala:505:22] reg uops_0_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_0_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_0_fp_ctrl_vec; // @[util.scala:505:22] reg [5:0] uops_0_rob_idx; // @[util.scala:505:22] reg [3:0] uops_0_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_0_stq_idx; // @[util.scala:505:22] reg [1:0] uops_0_rxq_idx; // @[util.scala:505:22] reg [6:0] uops_0_pdst; // @[util.scala:505:22] reg [6:0] uops_0_prs1; // @[util.scala:505:22] reg [6:0] uops_0_prs2; // @[util.scala:505:22] reg [6:0] uops_0_prs3; // @[util.scala:505:22] reg [4:0] uops_0_ppred; // @[util.scala:505:22] reg uops_0_prs1_busy; // @[util.scala:505:22] reg uops_0_prs2_busy; // @[util.scala:505:22] reg uops_0_prs3_busy; // @[util.scala:505:22] reg uops_0_ppred_busy; // @[util.scala:505:22] reg [6:0] uops_0_stale_pdst; // @[util.scala:505:22] reg uops_0_exception; // @[util.scala:505:22] reg [63:0] uops_0_exc_cause; // @[util.scala:505:22] reg [4:0] uops_0_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_0_mem_size; // @[util.scala:505:22] reg uops_0_mem_signed; // @[util.scala:505:22] reg uops_0_uses_ldq; // @[util.scala:505:22] reg uops_0_uses_stq; // @[util.scala:505:22] reg uops_0_is_unique; // @[util.scala:505:22] reg uops_0_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_0_csr_cmd; // @[util.scala:505:22] reg uops_0_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_0_ldst; // @[util.scala:505:22] reg [5:0] uops_0_lrs1; // @[util.scala:505:22] reg [5:0] uops_0_lrs2; // @[util.scala:505:22] reg [5:0] uops_0_lrs3; // @[util.scala:505:22] reg [1:0] uops_0_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:505:22] reg uops_0_frs3_en; // @[util.scala:505:22] reg uops_0_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_0_fcn_op; // @[util.scala:505:22] reg uops_0_fp_val; // @[util.scala:505:22] reg [2:0] uops_0_fp_rm; // @[util.scala:505:22] reg [1:0] uops_0_fp_typ; // @[util.scala:505:22] reg uops_0_xcpt_pf_if; // @[util.scala:505:22] reg uops_0_xcpt_ae_if; // @[util.scala:505:22] reg uops_0_xcpt_ma_if; // @[util.scala:505:22] reg uops_0_bp_debug_if; // @[util.scala:505:22] reg uops_0_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_0_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_0_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_1_inst; // @[util.scala:505:22] reg [31:0] uops_1_debug_inst; // @[util.scala:505:22] reg uops_1_is_rvc; // @[util.scala:505:22] reg [39:0] uops_1_debug_pc; // @[util.scala:505:22] reg uops_1_iq_type_0; // @[util.scala:505:22] reg uops_1_iq_type_1; // @[util.scala:505:22] reg uops_1_iq_type_2; // @[util.scala:505:22] reg uops_1_iq_type_3; // @[util.scala:505:22] reg uops_1_fu_code_0; // @[util.scala:505:22] reg uops_1_fu_code_1; // @[util.scala:505:22] reg uops_1_fu_code_2; // @[util.scala:505:22] reg uops_1_fu_code_3; // @[util.scala:505:22] reg uops_1_fu_code_4; // @[util.scala:505:22] reg uops_1_fu_code_5; // @[util.scala:505:22] reg uops_1_fu_code_6; // @[util.scala:505:22] reg uops_1_fu_code_7; // @[util.scala:505:22] reg uops_1_fu_code_8; // @[util.scala:505:22] reg uops_1_fu_code_9; // @[util.scala:505:22] reg uops_1_iw_issued; // @[util.scala:505:22] reg uops_1_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_1_iw_issued_partial_dgen; // @[util.scala:505:22] reg [1:0] uops_1_iw_p1_speculative_child; // @[util.scala:505:22] reg [1:0] uops_1_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_1_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p3_bypass_hint; // @[util.scala:505:22] reg [1:0] uops_1_dis_col_sel; // @[util.scala:505:22] reg [11:0] uops_1_br_mask; // @[util.scala:505:22] reg [3:0] uops_1_br_tag; // @[util.scala:505:22] reg [3:0] uops_1_br_type; // @[util.scala:505:22] reg uops_1_is_sfb; // @[util.scala:505:22] reg uops_1_is_fence; // @[util.scala:505:22] reg uops_1_is_fencei; // @[util.scala:505:22] reg uops_1_is_sfence; // @[util.scala:505:22] reg uops_1_is_amo; // @[util.scala:505:22] reg uops_1_is_eret; // @[util.scala:505:22] reg uops_1_is_sys_pc2epc; // @[util.scala:505:22] reg uops_1_is_rocc; // @[util.scala:505:22] reg uops_1_is_mov; // @[util.scala:505:22] reg [4:0] uops_1_ftq_idx; // @[util.scala:505:22] reg uops_1_edge_inst; // @[util.scala:505:22] reg [5:0] uops_1_pc_lob; // @[util.scala:505:22] reg uops_1_taken; // @[util.scala:505:22] reg uops_1_imm_rename; // @[util.scala:505:22] reg [2:0] uops_1_imm_sel; // @[util.scala:505:22] reg [4:0] uops_1_pimm; // @[util.scala:505:22] reg [19:0] uops_1_imm_packed; // @[util.scala:505:22] reg [1:0] uops_1_op1_sel; // @[util.scala:505:22] reg [2:0] uops_1_op2_sel; // @[util.scala:505:22] reg uops_1_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_1_fp_ctrl_wen; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_1_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_1_fp_ctrl_toint; // @[util.scala:505:22] reg uops_1_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_1_fp_ctrl_fma; // @[util.scala:505:22] reg uops_1_fp_ctrl_div; // @[util.scala:505:22] reg uops_1_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_1_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_1_fp_ctrl_vec; // @[util.scala:505:22] reg [5:0] uops_1_rob_idx; // @[util.scala:505:22] reg [3:0] uops_1_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_1_stq_idx; // @[util.scala:505:22] reg [1:0] uops_1_rxq_idx; // @[util.scala:505:22] reg [6:0] uops_1_pdst; // @[util.scala:505:22] reg [6:0] uops_1_prs1; // @[util.scala:505:22] reg [6:0] uops_1_prs2; // @[util.scala:505:22] reg [6:0] uops_1_prs3; // @[util.scala:505:22] reg [4:0] uops_1_ppred; // @[util.scala:505:22] reg uops_1_prs1_busy; // @[util.scala:505:22] reg uops_1_prs2_busy; // @[util.scala:505:22] reg uops_1_prs3_busy; // @[util.scala:505:22] reg uops_1_ppred_busy; // @[util.scala:505:22] reg [6:0] uops_1_stale_pdst; // @[util.scala:505:22] reg uops_1_exception; // @[util.scala:505:22] reg [63:0] uops_1_exc_cause; // @[util.scala:505:22] reg [4:0] uops_1_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_1_mem_size; // @[util.scala:505:22] reg uops_1_mem_signed; // @[util.scala:505:22] reg uops_1_uses_ldq; // @[util.scala:505:22] reg uops_1_uses_stq; // @[util.scala:505:22] reg uops_1_is_unique; // @[util.scala:505:22] reg uops_1_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_1_csr_cmd; // @[util.scala:505:22] reg uops_1_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_1_ldst; // @[util.scala:505:22] reg [5:0] uops_1_lrs1; // @[util.scala:505:22] reg [5:0] uops_1_lrs2; // @[util.scala:505:22] reg [5:0] uops_1_lrs3; // @[util.scala:505:22] reg [1:0] uops_1_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:505:22] reg uops_1_frs3_en; // @[util.scala:505:22] reg uops_1_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_1_fcn_op; // @[util.scala:505:22] reg uops_1_fp_val; // @[util.scala:505:22] reg [2:0] uops_1_fp_rm; // @[util.scala:505:22] reg [1:0] uops_1_fp_typ; // @[util.scala:505:22] reg uops_1_xcpt_pf_if; // @[util.scala:505:22] reg uops_1_xcpt_ae_if; // @[util.scala:505:22] reg uops_1_xcpt_ma_if; // @[util.scala:505:22] reg uops_1_bp_debug_if; // @[util.scala:505:22] reg uops_1_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_1_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_1_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_2_inst; // @[util.scala:505:22] reg [31:0] uops_2_debug_inst; // @[util.scala:505:22] reg uops_2_is_rvc; // @[util.scala:505:22] reg [39:0] uops_2_debug_pc; // @[util.scala:505:22] reg uops_2_iq_type_0; // @[util.scala:505:22] reg uops_2_iq_type_1; // @[util.scala:505:22] reg uops_2_iq_type_2; // @[util.scala:505:22] reg uops_2_iq_type_3; // @[util.scala:505:22] reg uops_2_fu_code_0; // @[util.scala:505:22] reg uops_2_fu_code_1; // @[util.scala:505:22] reg uops_2_fu_code_2; // @[util.scala:505:22] reg uops_2_fu_code_3; // @[util.scala:505:22] reg uops_2_fu_code_4; // @[util.scala:505:22] reg uops_2_fu_code_5; // @[util.scala:505:22] reg uops_2_fu_code_6; // @[util.scala:505:22] reg uops_2_fu_code_7; // @[util.scala:505:22] reg uops_2_fu_code_8; // @[util.scala:505:22] reg uops_2_fu_code_9; // @[util.scala:505:22] reg uops_2_iw_issued; // @[util.scala:505:22] reg uops_2_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_2_iw_issued_partial_dgen; // @[util.scala:505:22] reg [1:0] uops_2_iw_p1_speculative_child; // @[util.scala:505:22] reg [1:0] uops_2_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_2_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p3_bypass_hint; // @[util.scala:505:22] reg [1:0] uops_2_dis_col_sel; // @[util.scala:505:22] reg [11:0] uops_2_br_mask; // @[util.scala:505:22] reg [3:0] uops_2_br_tag; // @[util.scala:505:22] reg [3:0] uops_2_br_type; // @[util.scala:505:22] reg uops_2_is_sfb; // @[util.scala:505:22] reg uops_2_is_fence; // @[util.scala:505:22] reg uops_2_is_fencei; // @[util.scala:505:22] reg uops_2_is_sfence; // @[util.scala:505:22] reg uops_2_is_amo; // @[util.scala:505:22] reg uops_2_is_eret; // @[util.scala:505:22] reg uops_2_is_sys_pc2epc; // @[util.scala:505:22] reg uops_2_is_rocc; // @[util.scala:505:22] reg uops_2_is_mov; // @[util.scala:505:22] reg [4:0] uops_2_ftq_idx; // @[util.scala:505:22] reg uops_2_edge_inst; // @[util.scala:505:22] reg [5:0] uops_2_pc_lob; // @[util.scala:505:22] reg uops_2_taken; // @[util.scala:505:22] reg uops_2_imm_rename; // @[util.scala:505:22] reg [2:0] uops_2_imm_sel; // @[util.scala:505:22] reg [4:0] uops_2_pimm; // @[util.scala:505:22] reg [19:0] uops_2_imm_packed; // @[util.scala:505:22] reg [1:0] uops_2_op1_sel; // @[util.scala:505:22] reg [2:0] uops_2_op2_sel; // @[util.scala:505:22] reg uops_2_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_2_fp_ctrl_wen; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_2_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_2_fp_ctrl_toint; // @[util.scala:505:22] reg uops_2_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_2_fp_ctrl_fma; // @[util.scala:505:22] reg uops_2_fp_ctrl_div; // @[util.scala:505:22] reg uops_2_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_2_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_2_fp_ctrl_vec; // @[util.scala:505:22] reg [5:0] uops_2_rob_idx; // @[util.scala:505:22] reg [3:0] uops_2_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_2_stq_idx; // @[util.scala:505:22] reg [1:0] uops_2_rxq_idx; // @[util.scala:505:22] reg [6:0] uops_2_pdst; // @[util.scala:505:22] reg [6:0] uops_2_prs1; // @[util.scala:505:22] reg [6:0] uops_2_prs2; // @[util.scala:505:22] reg [6:0] uops_2_prs3; // @[util.scala:505:22] reg [4:0] uops_2_ppred; // @[util.scala:505:22] reg uops_2_prs1_busy; // @[util.scala:505:22] reg uops_2_prs2_busy; // @[util.scala:505:22] reg uops_2_prs3_busy; // @[util.scala:505:22] reg uops_2_ppred_busy; // @[util.scala:505:22] reg [6:0] uops_2_stale_pdst; // @[util.scala:505:22] reg uops_2_exception; // @[util.scala:505:22] reg [63:0] uops_2_exc_cause; // @[util.scala:505:22] reg [4:0] uops_2_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_2_mem_size; // @[util.scala:505:22] reg uops_2_mem_signed; // @[util.scala:505:22] reg uops_2_uses_ldq; // @[util.scala:505:22] reg uops_2_uses_stq; // @[util.scala:505:22] reg uops_2_is_unique; // @[util.scala:505:22] reg uops_2_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_2_csr_cmd; // @[util.scala:505:22] reg uops_2_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_2_ldst; // @[util.scala:505:22] reg [5:0] uops_2_lrs1; // @[util.scala:505:22] reg [5:0] uops_2_lrs2; // @[util.scala:505:22] reg [5:0] uops_2_lrs3; // @[util.scala:505:22] reg [1:0] uops_2_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:505:22] reg uops_2_frs3_en; // @[util.scala:505:22] reg uops_2_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_2_fcn_op; // @[util.scala:505:22] reg uops_2_fp_val; // @[util.scala:505:22] reg [2:0] uops_2_fp_rm; // @[util.scala:505:22] reg [1:0] uops_2_fp_typ; // @[util.scala:505:22] reg uops_2_xcpt_pf_if; // @[util.scala:505:22] reg uops_2_xcpt_ae_if; // @[util.scala:505:22] reg uops_2_xcpt_ma_if; // @[util.scala:505:22] reg uops_2_bp_debug_if; // @[util.scala:505:22] reg uops_2_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_2_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_2_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_3_inst; // @[util.scala:505:22] reg [31:0] uops_3_debug_inst; // @[util.scala:505:22] reg uops_3_is_rvc; // @[util.scala:505:22] reg [39:0] uops_3_debug_pc; // @[util.scala:505:22] reg uops_3_iq_type_0; // @[util.scala:505:22] reg uops_3_iq_type_1; // @[util.scala:505:22] reg uops_3_iq_type_2; // @[util.scala:505:22] reg uops_3_iq_type_3; // @[util.scala:505:22] reg uops_3_fu_code_0; // @[util.scala:505:22] reg uops_3_fu_code_1; // @[util.scala:505:22] reg uops_3_fu_code_2; // @[util.scala:505:22] reg uops_3_fu_code_3; // @[util.scala:505:22] reg uops_3_fu_code_4; // @[util.scala:505:22] reg uops_3_fu_code_5; // @[util.scala:505:22] reg uops_3_fu_code_6; // @[util.scala:505:22] reg uops_3_fu_code_7; // @[util.scala:505:22] reg uops_3_fu_code_8; // @[util.scala:505:22] reg uops_3_fu_code_9; // @[util.scala:505:22] reg uops_3_iw_issued; // @[util.scala:505:22] reg uops_3_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_3_iw_issued_partial_dgen; // @[util.scala:505:22] reg [1:0] uops_3_iw_p1_speculative_child; // @[util.scala:505:22] reg [1:0] uops_3_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_3_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p3_bypass_hint; // @[util.scala:505:22] reg [1:0] uops_3_dis_col_sel; // @[util.scala:505:22] reg [11:0] uops_3_br_mask; // @[util.scala:505:22] reg [3:0] uops_3_br_tag; // @[util.scala:505:22] reg [3:0] uops_3_br_type; // @[util.scala:505:22] reg uops_3_is_sfb; // @[util.scala:505:22] reg uops_3_is_fence; // @[util.scala:505:22] reg uops_3_is_fencei; // @[util.scala:505:22] reg uops_3_is_sfence; // @[util.scala:505:22] reg uops_3_is_amo; // @[util.scala:505:22] reg uops_3_is_eret; // @[util.scala:505:22] reg uops_3_is_sys_pc2epc; // @[util.scala:505:22] reg uops_3_is_rocc; // @[util.scala:505:22] reg uops_3_is_mov; // @[util.scala:505:22] reg [4:0] uops_3_ftq_idx; // @[util.scala:505:22] reg uops_3_edge_inst; // @[util.scala:505:22] reg [5:0] uops_3_pc_lob; // @[util.scala:505:22] reg uops_3_taken; // @[util.scala:505:22] reg uops_3_imm_rename; // @[util.scala:505:22] reg [2:0] uops_3_imm_sel; // @[util.scala:505:22] reg [4:0] uops_3_pimm; // @[util.scala:505:22] reg [19:0] uops_3_imm_packed; // @[util.scala:505:22] reg [1:0] uops_3_op1_sel; // @[util.scala:505:22] reg [2:0] uops_3_op2_sel; // @[util.scala:505:22] reg uops_3_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_3_fp_ctrl_wen; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_3_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_3_fp_ctrl_toint; // @[util.scala:505:22] reg uops_3_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_3_fp_ctrl_fma; // @[util.scala:505:22] reg uops_3_fp_ctrl_div; // @[util.scala:505:22] reg uops_3_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_3_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_3_fp_ctrl_vec; // @[util.scala:505:22] reg [5:0] uops_3_rob_idx; // @[util.scala:505:22] reg [3:0] uops_3_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_3_stq_idx; // @[util.scala:505:22] reg [1:0] uops_3_rxq_idx; // @[util.scala:505:22] reg [6:0] uops_3_pdst; // @[util.scala:505:22] reg [6:0] uops_3_prs1; // @[util.scala:505:22] reg [6:0] uops_3_prs2; // @[util.scala:505:22] reg [6:0] uops_3_prs3; // @[util.scala:505:22] reg [4:0] uops_3_ppred; // @[util.scala:505:22] reg uops_3_prs1_busy; // @[util.scala:505:22] reg uops_3_prs2_busy; // @[util.scala:505:22] reg uops_3_prs3_busy; // @[util.scala:505:22] reg uops_3_ppred_busy; // @[util.scala:505:22] reg [6:0] uops_3_stale_pdst; // @[util.scala:505:22] reg uops_3_exception; // @[util.scala:505:22] reg [63:0] uops_3_exc_cause; // @[util.scala:505:22] reg [4:0] uops_3_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_3_mem_size; // @[util.scala:505:22] reg uops_3_mem_signed; // @[util.scala:505:22] reg uops_3_uses_ldq; // @[util.scala:505:22] reg uops_3_uses_stq; // @[util.scala:505:22] reg uops_3_is_unique; // @[util.scala:505:22] reg uops_3_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_3_csr_cmd; // @[util.scala:505:22] reg uops_3_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_3_ldst; // @[util.scala:505:22] reg [5:0] uops_3_lrs1; // @[util.scala:505:22] reg [5:0] uops_3_lrs2; // @[util.scala:505:22] reg [5:0] uops_3_lrs3; // @[util.scala:505:22] reg [1:0] uops_3_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:505:22] reg uops_3_frs3_en; // @[util.scala:505:22] reg uops_3_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_3_fcn_op; // @[util.scala:505:22] reg uops_3_fp_val; // @[util.scala:505:22] reg [2:0] uops_3_fp_rm; // @[util.scala:505:22] reg [1:0] uops_3_fp_typ; // @[util.scala:505:22] reg uops_3_xcpt_pf_if; // @[util.scala:505:22] reg uops_3_xcpt_ae_if; // @[util.scala:505:22] reg uops_3_xcpt_ma_if; // @[util.scala:505:22] reg uops_3_bp_debug_if; // @[util.scala:505:22] reg uops_3_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_3_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_3_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_4_inst; // @[util.scala:505:22] reg [31:0] uops_4_debug_inst; // @[util.scala:505:22] reg uops_4_is_rvc; // @[util.scala:505:22] reg [39:0] uops_4_debug_pc; // @[util.scala:505:22] reg uops_4_iq_type_0; // @[util.scala:505:22] reg uops_4_iq_type_1; // @[util.scala:505:22] reg uops_4_iq_type_2; // @[util.scala:505:22] reg uops_4_iq_type_3; // @[util.scala:505:22] reg uops_4_fu_code_0; // @[util.scala:505:22] reg uops_4_fu_code_1; // @[util.scala:505:22] reg uops_4_fu_code_2; // @[util.scala:505:22] reg uops_4_fu_code_3; // @[util.scala:505:22] reg uops_4_fu_code_4; // @[util.scala:505:22] reg uops_4_fu_code_5; // @[util.scala:505:22] reg uops_4_fu_code_6; // @[util.scala:505:22] reg uops_4_fu_code_7; // @[util.scala:505:22] reg uops_4_fu_code_8; // @[util.scala:505:22] reg uops_4_fu_code_9; // @[util.scala:505:22] reg uops_4_iw_issued; // @[util.scala:505:22] reg uops_4_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_4_iw_issued_partial_dgen; // @[util.scala:505:22] reg [1:0] uops_4_iw_p1_speculative_child; // @[util.scala:505:22] reg [1:0] uops_4_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_4_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p3_bypass_hint; // @[util.scala:505:22] reg [1:0] uops_4_dis_col_sel; // @[util.scala:505:22] reg [11:0] uops_4_br_mask; // @[util.scala:505:22] reg [3:0] uops_4_br_tag; // @[util.scala:505:22] reg [3:0] uops_4_br_type; // @[util.scala:505:22] reg uops_4_is_sfb; // @[util.scala:505:22] reg uops_4_is_fence; // @[util.scala:505:22] reg uops_4_is_fencei; // @[util.scala:505:22] reg uops_4_is_sfence; // @[util.scala:505:22] reg uops_4_is_amo; // @[util.scala:505:22] reg uops_4_is_eret; // @[util.scala:505:22] reg uops_4_is_sys_pc2epc; // @[util.scala:505:22] reg uops_4_is_rocc; // @[util.scala:505:22] reg uops_4_is_mov; // @[util.scala:505:22] reg [4:0] uops_4_ftq_idx; // @[util.scala:505:22] reg uops_4_edge_inst; // @[util.scala:505:22] reg [5:0] uops_4_pc_lob; // @[util.scala:505:22] reg uops_4_taken; // @[util.scala:505:22] reg uops_4_imm_rename; // @[util.scala:505:22] reg [2:0] uops_4_imm_sel; // @[util.scala:505:22] reg [4:0] uops_4_pimm; // @[util.scala:505:22] reg [19:0] uops_4_imm_packed; // @[util.scala:505:22] reg [1:0] uops_4_op1_sel; // @[util.scala:505:22] reg [2:0] uops_4_op2_sel; // @[util.scala:505:22] reg uops_4_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_4_fp_ctrl_wen; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_4_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_4_fp_ctrl_toint; // @[util.scala:505:22] reg uops_4_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_4_fp_ctrl_fma; // @[util.scala:505:22] reg uops_4_fp_ctrl_div; // @[util.scala:505:22] reg uops_4_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_4_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_4_fp_ctrl_vec; // @[util.scala:505:22] reg [5:0] uops_4_rob_idx; // @[util.scala:505:22] reg [3:0] uops_4_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_4_stq_idx; // @[util.scala:505:22] reg [1:0] uops_4_rxq_idx; // @[util.scala:505:22] reg [6:0] uops_4_pdst; // @[util.scala:505:22] reg [6:0] uops_4_prs1; // @[util.scala:505:22] reg [6:0] uops_4_prs2; // @[util.scala:505:22] reg [6:0] uops_4_prs3; // @[util.scala:505:22] reg [4:0] uops_4_ppred; // @[util.scala:505:22] reg uops_4_prs1_busy; // @[util.scala:505:22] reg uops_4_prs2_busy; // @[util.scala:505:22] reg uops_4_prs3_busy; // @[util.scala:505:22] reg uops_4_ppred_busy; // @[util.scala:505:22] reg [6:0] uops_4_stale_pdst; // @[util.scala:505:22] reg uops_4_exception; // @[util.scala:505:22] reg [63:0] uops_4_exc_cause; // @[util.scala:505:22] reg [4:0] uops_4_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_4_mem_size; // @[util.scala:505:22] reg uops_4_mem_signed; // @[util.scala:505:22] reg uops_4_uses_ldq; // @[util.scala:505:22] reg uops_4_uses_stq; // @[util.scala:505:22] reg uops_4_is_unique; // @[util.scala:505:22] reg uops_4_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_4_csr_cmd; // @[util.scala:505:22] reg uops_4_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_4_ldst; // @[util.scala:505:22] reg [5:0] uops_4_lrs1; // @[util.scala:505:22] reg [5:0] uops_4_lrs2; // @[util.scala:505:22] reg [5:0] uops_4_lrs3; // @[util.scala:505:22] reg [1:0] uops_4_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:505:22] reg uops_4_frs3_en; // @[util.scala:505:22] reg uops_4_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_4_fcn_op; // @[util.scala:505:22] reg uops_4_fp_val; // @[util.scala:505:22] reg [2:0] uops_4_fp_rm; // @[util.scala:505:22] reg [1:0] uops_4_fp_typ; // @[util.scala:505:22] reg uops_4_xcpt_pf_if; // @[util.scala:505:22] reg uops_4_xcpt_ae_if; // @[util.scala:505:22] reg uops_4_xcpt_ma_if; // @[util.scala:505:22] reg uops_4_bp_debug_if; // @[util.scala:505:22] reg uops_4_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_4_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_4_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_5_inst; // @[util.scala:505:22] reg [31:0] uops_5_debug_inst; // @[util.scala:505:22] reg uops_5_is_rvc; // @[util.scala:505:22] reg [39:0] uops_5_debug_pc; // @[util.scala:505:22] reg uops_5_iq_type_0; // @[util.scala:505:22] reg uops_5_iq_type_1; // @[util.scala:505:22] reg uops_5_iq_type_2; // @[util.scala:505:22] reg uops_5_iq_type_3; // @[util.scala:505:22] reg uops_5_fu_code_0; // @[util.scala:505:22] reg uops_5_fu_code_1; // @[util.scala:505:22] reg uops_5_fu_code_2; // @[util.scala:505:22] reg uops_5_fu_code_3; // @[util.scala:505:22] reg uops_5_fu_code_4; // @[util.scala:505:22] reg uops_5_fu_code_5; // @[util.scala:505:22] reg uops_5_fu_code_6; // @[util.scala:505:22] reg uops_5_fu_code_7; // @[util.scala:505:22] reg uops_5_fu_code_8; // @[util.scala:505:22] reg uops_5_fu_code_9; // @[util.scala:505:22] reg uops_5_iw_issued; // @[util.scala:505:22] reg uops_5_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_5_iw_issued_partial_dgen; // @[util.scala:505:22] reg [1:0] uops_5_iw_p1_speculative_child; // @[util.scala:505:22] reg [1:0] uops_5_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_5_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p3_bypass_hint; // @[util.scala:505:22] reg [1:0] uops_5_dis_col_sel; // @[util.scala:505:22] reg [11:0] uops_5_br_mask; // @[util.scala:505:22] reg [3:0] uops_5_br_tag; // @[util.scala:505:22] reg [3:0] uops_5_br_type; // @[util.scala:505:22] reg uops_5_is_sfb; // @[util.scala:505:22] reg uops_5_is_fence; // @[util.scala:505:22] reg uops_5_is_fencei; // @[util.scala:505:22] reg uops_5_is_sfence; // @[util.scala:505:22] reg uops_5_is_amo; // @[util.scala:505:22] reg uops_5_is_eret; // @[util.scala:505:22] reg uops_5_is_sys_pc2epc; // @[util.scala:505:22] reg uops_5_is_rocc; // @[util.scala:505:22] reg uops_5_is_mov; // @[util.scala:505:22] reg [4:0] uops_5_ftq_idx; // @[util.scala:505:22] reg uops_5_edge_inst; // @[util.scala:505:22] reg [5:0] uops_5_pc_lob; // @[util.scala:505:22] reg uops_5_taken; // @[util.scala:505:22] reg uops_5_imm_rename; // @[util.scala:505:22] reg [2:0] uops_5_imm_sel; // @[util.scala:505:22] reg [4:0] uops_5_pimm; // @[util.scala:505:22] reg [19:0] uops_5_imm_packed; // @[util.scala:505:22] reg [1:0] uops_5_op1_sel; // @[util.scala:505:22] reg [2:0] uops_5_op2_sel; // @[util.scala:505:22] reg uops_5_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_5_fp_ctrl_wen; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_5_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_5_fp_ctrl_toint; // @[util.scala:505:22] reg uops_5_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_5_fp_ctrl_fma; // @[util.scala:505:22] reg uops_5_fp_ctrl_div; // @[util.scala:505:22] reg uops_5_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_5_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_5_fp_ctrl_vec; // @[util.scala:505:22] reg [5:0] uops_5_rob_idx; // @[util.scala:505:22] reg [3:0] uops_5_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_5_stq_idx; // @[util.scala:505:22] reg [1:0] uops_5_rxq_idx; // @[util.scala:505:22] reg [6:0] uops_5_pdst; // @[util.scala:505:22] reg [6:0] uops_5_prs1; // @[util.scala:505:22] reg [6:0] uops_5_prs2; // @[util.scala:505:22] reg [6:0] uops_5_prs3; // @[util.scala:505:22] reg [4:0] uops_5_ppred; // @[util.scala:505:22] reg uops_5_prs1_busy; // @[util.scala:505:22] reg uops_5_prs2_busy; // @[util.scala:505:22] reg uops_5_prs3_busy; // @[util.scala:505:22] reg uops_5_ppred_busy; // @[util.scala:505:22] reg [6:0] uops_5_stale_pdst; // @[util.scala:505:22] reg uops_5_exception; // @[util.scala:505:22] reg [63:0] uops_5_exc_cause; // @[util.scala:505:22] reg [4:0] uops_5_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_5_mem_size; // @[util.scala:505:22] reg uops_5_mem_signed; // @[util.scala:505:22] reg uops_5_uses_ldq; // @[util.scala:505:22] reg uops_5_uses_stq; // @[util.scala:505:22] reg uops_5_is_unique; // @[util.scala:505:22] reg uops_5_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_5_csr_cmd; // @[util.scala:505:22] reg uops_5_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_5_ldst; // @[util.scala:505:22] reg [5:0] uops_5_lrs1; // @[util.scala:505:22] reg [5:0] uops_5_lrs2; // @[util.scala:505:22] reg [5:0] uops_5_lrs3; // @[util.scala:505:22] reg [1:0] uops_5_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:505:22] reg uops_5_frs3_en; // @[util.scala:505:22] reg uops_5_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_5_fcn_op; // @[util.scala:505:22] reg uops_5_fp_val; // @[util.scala:505:22] reg [2:0] uops_5_fp_rm; // @[util.scala:505:22] reg [1:0] uops_5_fp_typ; // @[util.scala:505:22] reg uops_5_xcpt_pf_if; // @[util.scala:505:22] reg uops_5_xcpt_ae_if; // @[util.scala:505:22] reg uops_5_xcpt_ma_if; // @[util.scala:505:22] reg uops_5_bp_debug_if; // @[util.scala:505:22] reg uops_5_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_5_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_5_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_6_inst; // @[util.scala:505:22] reg [31:0] uops_6_debug_inst; // @[util.scala:505:22] reg uops_6_is_rvc; // @[util.scala:505:22] reg [39:0] uops_6_debug_pc; // @[util.scala:505:22] reg uops_6_iq_type_0; // @[util.scala:505:22] reg uops_6_iq_type_1; // @[util.scala:505:22] reg uops_6_iq_type_2; // @[util.scala:505:22] reg uops_6_iq_type_3; // @[util.scala:505:22] reg uops_6_fu_code_0; // @[util.scala:505:22] reg uops_6_fu_code_1; // @[util.scala:505:22] reg uops_6_fu_code_2; // @[util.scala:505:22] reg uops_6_fu_code_3; // @[util.scala:505:22] reg uops_6_fu_code_4; // @[util.scala:505:22] reg uops_6_fu_code_5; // @[util.scala:505:22] reg uops_6_fu_code_6; // @[util.scala:505:22] reg uops_6_fu_code_7; // @[util.scala:505:22] reg uops_6_fu_code_8; // @[util.scala:505:22] reg uops_6_fu_code_9; // @[util.scala:505:22] reg uops_6_iw_issued; // @[util.scala:505:22] reg uops_6_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_6_iw_issued_partial_dgen; // @[util.scala:505:22] reg [1:0] uops_6_iw_p1_speculative_child; // @[util.scala:505:22] reg [1:0] uops_6_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_6_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p3_bypass_hint; // @[util.scala:505:22] reg [1:0] uops_6_dis_col_sel; // @[util.scala:505:22] reg [11:0] uops_6_br_mask; // @[util.scala:505:22] reg [3:0] uops_6_br_tag; // @[util.scala:505:22] reg [3:0] uops_6_br_type; // @[util.scala:505:22] reg uops_6_is_sfb; // @[util.scala:505:22] reg uops_6_is_fence; // @[util.scala:505:22] reg uops_6_is_fencei; // @[util.scala:505:22] reg uops_6_is_sfence; // @[util.scala:505:22] reg uops_6_is_amo; // @[util.scala:505:22] reg uops_6_is_eret; // @[util.scala:505:22] reg uops_6_is_sys_pc2epc; // @[util.scala:505:22] reg uops_6_is_rocc; // @[util.scala:505:22] reg uops_6_is_mov; // @[util.scala:505:22] reg [4:0] uops_6_ftq_idx; // @[util.scala:505:22] reg uops_6_edge_inst; // @[util.scala:505:22] reg [5:0] uops_6_pc_lob; // @[util.scala:505:22] reg uops_6_taken; // @[util.scala:505:22] reg uops_6_imm_rename; // @[util.scala:505:22] reg [2:0] uops_6_imm_sel; // @[util.scala:505:22] reg [4:0] uops_6_pimm; // @[util.scala:505:22] reg [19:0] uops_6_imm_packed; // @[util.scala:505:22] reg [1:0] uops_6_op1_sel; // @[util.scala:505:22] reg [2:0] uops_6_op2_sel; // @[util.scala:505:22] reg uops_6_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_6_fp_ctrl_wen; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_6_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_6_fp_ctrl_toint; // @[util.scala:505:22] reg uops_6_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_6_fp_ctrl_fma; // @[util.scala:505:22] reg uops_6_fp_ctrl_div; // @[util.scala:505:22] reg uops_6_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_6_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_6_fp_ctrl_vec; // @[util.scala:505:22] reg [5:0] uops_6_rob_idx; // @[util.scala:505:22] reg [3:0] uops_6_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_6_stq_idx; // @[util.scala:505:22] reg [1:0] uops_6_rxq_idx; // @[util.scala:505:22] reg [6:0] uops_6_pdst; // @[util.scala:505:22] reg [6:0] uops_6_prs1; // @[util.scala:505:22] reg [6:0] uops_6_prs2; // @[util.scala:505:22] reg [6:0] uops_6_prs3; // @[util.scala:505:22] reg [4:0] uops_6_ppred; // @[util.scala:505:22] reg uops_6_prs1_busy; // @[util.scala:505:22] reg uops_6_prs2_busy; // @[util.scala:505:22] reg uops_6_prs3_busy; // @[util.scala:505:22] reg uops_6_ppred_busy; // @[util.scala:505:22] reg [6:0] uops_6_stale_pdst; // @[util.scala:505:22] reg uops_6_exception; // @[util.scala:505:22] reg [63:0] uops_6_exc_cause; // @[util.scala:505:22] reg [4:0] uops_6_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_6_mem_size; // @[util.scala:505:22] reg uops_6_mem_signed; // @[util.scala:505:22] reg uops_6_uses_ldq; // @[util.scala:505:22] reg uops_6_uses_stq; // @[util.scala:505:22] reg uops_6_is_unique; // @[util.scala:505:22] reg uops_6_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_6_csr_cmd; // @[util.scala:505:22] reg uops_6_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_6_ldst; // @[util.scala:505:22] reg [5:0] uops_6_lrs1; // @[util.scala:505:22] reg [5:0] uops_6_lrs2; // @[util.scala:505:22] reg [5:0] uops_6_lrs3; // @[util.scala:505:22] reg [1:0] uops_6_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:505:22] reg uops_6_frs3_en; // @[util.scala:505:22] reg uops_6_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_6_fcn_op; // @[util.scala:505:22] reg uops_6_fp_val; // @[util.scala:505:22] reg [2:0] uops_6_fp_rm; // @[util.scala:505:22] reg [1:0] uops_6_fp_typ; // @[util.scala:505:22] reg uops_6_xcpt_pf_if; // @[util.scala:505:22] reg uops_6_xcpt_ae_if; // @[util.scala:505:22] reg uops_6_xcpt_ma_if; // @[util.scala:505:22] reg uops_6_bp_debug_if; // @[util.scala:505:22] reg uops_6_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_6_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_6_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_7_inst; // @[util.scala:505:22] reg [31:0] uops_7_debug_inst; // @[util.scala:505:22] reg uops_7_is_rvc; // @[util.scala:505:22] reg [39:0] uops_7_debug_pc; // @[util.scala:505:22] reg uops_7_iq_type_0; // @[util.scala:505:22] reg uops_7_iq_type_1; // @[util.scala:505:22] reg uops_7_iq_type_2; // @[util.scala:505:22] reg uops_7_iq_type_3; // @[util.scala:505:22] reg uops_7_fu_code_0; // @[util.scala:505:22] reg uops_7_fu_code_1; // @[util.scala:505:22] reg uops_7_fu_code_2; // @[util.scala:505:22] reg uops_7_fu_code_3; // @[util.scala:505:22] reg uops_7_fu_code_4; // @[util.scala:505:22] reg uops_7_fu_code_5; // @[util.scala:505:22] reg uops_7_fu_code_6; // @[util.scala:505:22] reg uops_7_fu_code_7; // @[util.scala:505:22] reg uops_7_fu_code_8; // @[util.scala:505:22] reg uops_7_fu_code_9; // @[util.scala:505:22] reg uops_7_iw_issued; // @[util.scala:505:22] reg uops_7_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_7_iw_issued_partial_dgen; // @[util.scala:505:22] reg [1:0] uops_7_iw_p1_speculative_child; // @[util.scala:505:22] reg [1:0] uops_7_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_7_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p3_bypass_hint; // @[util.scala:505:22] reg [1:0] uops_7_dis_col_sel; // @[util.scala:505:22] reg [11:0] uops_7_br_mask; // @[util.scala:505:22] reg [3:0] uops_7_br_tag; // @[util.scala:505:22] reg [3:0] uops_7_br_type; // @[util.scala:505:22] reg uops_7_is_sfb; // @[util.scala:505:22] reg uops_7_is_fence; // @[util.scala:505:22] reg uops_7_is_fencei; // @[util.scala:505:22] reg uops_7_is_sfence; // @[util.scala:505:22] reg uops_7_is_amo; // @[util.scala:505:22] reg uops_7_is_eret; // @[util.scala:505:22] reg uops_7_is_sys_pc2epc; // @[util.scala:505:22] reg uops_7_is_rocc; // @[util.scala:505:22] reg uops_7_is_mov; // @[util.scala:505:22] reg [4:0] uops_7_ftq_idx; // @[util.scala:505:22] reg uops_7_edge_inst; // @[util.scala:505:22] reg [5:0] uops_7_pc_lob; // @[util.scala:505:22] reg uops_7_taken; // @[util.scala:505:22] reg uops_7_imm_rename; // @[util.scala:505:22] reg [2:0] uops_7_imm_sel; // @[util.scala:505:22] reg [4:0] uops_7_pimm; // @[util.scala:505:22] reg [19:0] uops_7_imm_packed; // @[util.scala:505:22] reg [1:0] uops_7_op1_sel; // @[util.scala:505:22] reg [2:0] uops_7_op2_sel; // @[util.scala:505:22] reg uops_7_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_7_fp_ctrl_wen; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_7_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_7_fp_ctrl_toint; // @[util.scala:505:22] reg uops_7_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_7_fp_ctrl_fma; // @[util.scala:505:22] reg uops_7_fp_ctrl_div; // @[util.scala:505:22] reg uops_7_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_7_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_7_fp_ctrl_vec; // @[util.scala:505:22] reg [5:0] uops_7_rob_idx; // @[util.scala:505:22] reg [3:0] uops_7_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_7_stq_idx; // @[util.scala:505:22] reg [1:0] uops_7_rxq_idx; // @[util.scala:505:22] reg [6:0] uops_7_pdst; // @[util.scala:505:22] reg [6:0] uops_7_prs1; // @[util.scala:505:22] reg [6:0] uops_7_prs2; // @[util.scala:505:22] reg [6:0] uops_7_prs3; // @[util.scala:505:22] reg [4:0] uops_7_ppred; // @[util.scala:505:22] reg uops_7_prs1_busy; // @[util.scala:505:22] reg uops_7_prs2_busy; // @[util.scala:505:22] reg uops_7_prs3_busy; // @[util.scala:505:22] reg uops_7_ppred_busy; // @[util.scala:505:22] reg [6:0] uops_7_stale_pdst; // @[util.scala:505:22] reg uops_7_exception; // @[util.scala:505:22] reg [63:0] uops_7_exc_cause; // @[util.scala:505:22] reg [4:0] uops_7_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_7_mem_size; // @[util.scala:505:22] reg uops_7_mem_signed; // @[util.scala:505:22] reg uops_7_uses_ldq; // @[util.scala:505:22] reg uops_7_uses_stq; // @[util.scala:505:22] reg uops_7_is_unique; // @[util.scala:505:22] reg uops_7_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_7_csr_cmd; // @[util.scala:505:22] reg uops_7_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_7_ldst; // @[util.scala:505:22] reg [5:0] uops_7_lrs1; // @[util.scala:505:22] reg [5:0] uops_7_lrs2; // @[util.scala:505:22] reg [5:0] uops_7_lrs3; // @[util.scala:505:22] reg [1:0] uops_7_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:505:22] reg uops_7_frs3_en; // @[util.scala:505:22] reg uops_7_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_7_fcn_op; // @[util.scala:505:22] reg uops_7_fp_val; // @[util.scala:505:22] reg [2:0] uops_7_fp_rm; // @[util.scala:505:22] reg [1:0] uops_7_fp_typ; // @[util.scala:505:22] reg uops_7_xcpt_pf_if; // @[util.scala:505:22] reg uops_7_xcpt_ae_if; // @[util.scala:505:22] reg uops_7_xcpt_ma_if; // @[util.scala:505:22] reg uops_7_bp_debug_if; // @[util.scala:505:22] reg uops_7_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_7_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_7_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_8_inst; // @[util.scala:505:22] reg [31:0] uops_8_debug_inst; // @[util.scala:505:22] reg uops_8_is_rvc; // @[util.scala:505:22] reg [39:0] uops_8_debug_pc; // @[util.scala:505:22] reg uops_8_iq_type_0; // @[util.scala:505:22] reg uops_8_iq_type_1; // @[util.scala:505:22] reg uops_8_iq_type_2; // @[util.scala:505:22] reg uops_8_iq_type_3; // @[util.scala:505:22] reg uops_8_fu_code_0; // @[util.scala:505:22] reg uops_8_fu_code_1; // @[util.scala:505:22] reg uops_8_fu_code_2; // @[util.scala:505:22] reg uops_8_fu_code_3; // @[util.scala:505:22] reg uops_8_fu_code_4; // @[util.scala:505:22] reg uops_8_fu_code_5; // @[util.scala:505:22] reg uops_8_fu_code_6; // @[util.scala:505:22] reg uops_8_fu_code_7; // @[util.scala:505:22] reg uops_8_fu_code_8; // @[util.scala:505:22] reg uops_8_fu_code_9; // @[util.scala:505:22] reg uops_8_iw_issued; // @[util.scala:505:22] reg uops_8_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_8_iw_issued_partial_dgen; // @[util.scala:505:22] reg [1:0] uops_8_iw_p1_speculative_child; // @[util.scala:505:22] reg [1:0] uops_8_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_8_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p3_bypass_hint; // @[util.scala:505:22] reg [1:0] uops_8_dis_col_sel; // @[util.scala:505:22] reg [11:0] uops_8_br_mask; // @[util.scala:505:22] reg [3:0] uops_8_br_tag; // @[util.scala:505:22] reg [3:0] uops_8_br_type; // @[util.scala:505:22] reg uops_8_is_sfb; // @[util.scala:505:22] reg uops_8_is_fence; // @[util.scala:505:22] reg uops_8_is_fencei; // @[util.scala:505:22] reg uops_8_is_sfence; // @[util.scala:505:22] reg uops_8_is_amo; // @[util.scala:505:22] reg uops_8_is_eret; // @[util.scala:505:22] reg uops_8_is_sys_pc2epc; // @[util.scala:505:22] reg uops_8_is_rocc; // @[util.scala:505:22] reg uops_8_is_mov; // @[util.scala:505:22] reg [4:0] uops_8_ftq_idx; // @[util.scala:505:22] reg uops_8_edge_inst; // @[util.scala:505:22] reg [5:0] uops_8_pc_lob; // @[util.scala:505:22] reg uops_8_taken; // @[util.scala:505:22] reg uops_8_imm_rename; // @[util.scala:505:22] reg [2:0] uops_8_imm_sel; // @[util.scala:505:22] reg [4:0] uops_8_pimm; // @[util.scala:505:22] reg [19:0] uops_8_imm_packed; // @[util.scala:505:22] reg [1:0] uops_8_op1_sel; // @[util.scala:505:22] reg [2:0] uops_8_op2_sel; // @[util.scala:505:22] reg uops_8_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_8_fp_ctrl_wen; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_8_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_8_fp_ctrl_toint; // @[util.scala:505:22] reg uops_8_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_8_fp_ctrl_fma; // @[util.scala:505:22] reg uops_8_fp_ctrl_div; // @[util.scala:505:22] reg uops_8_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_8_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_8_fp_ctrl_vec; // @[util.scala:505:22] reg [5:0] uops_8_rob_idx; // @[util.scala:505:22] reg [3:0] uops_8_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_8_stq_idx; // @[util.scala:505:22] reg [1:0] uops_8_rxq_idx; // @[util.scala:505:22] reg [6:0] uops_8_pdst; // @[util.scala:505:22] reg [6:0] uops_8_prs1; // @[util.scala:505:22] reg [6:0] uops_8_prs2; // @[util.scala:505:22] reg [6:0] uops_8_prs3; // @[util.scala:505:22] reg [4:0] uops_8_ppred; // @[util.scala:505:22] reg uops_8_prs1_busy; // @[util.scala:505:22] reg uops_8_prs2_busy; // @[util.scala:505:22] reg uops_8_prs3_busy; // @[util.scala:505:22] reg uops_8_ppred_busy; // @[util.scala:505:22] reg [6:0] uops_8_stale_pdst; // @[util.scala:505:22] reg uops_8_exception; // @[util.scala:505:22] reg [63:0] uops_8_exc_cause; // @[util.scala:505:22] reg [4:0] uops_8_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_8_mem_size; // @[util.scala:505:22] reg uops_8_mem_signed; // @[util.scala:505:22] reg uops_8_uses_ldq; // @[util.scala:505:22] reg uops_8_uses_stq; // @[util.scala:505:22] reg uops_8_is_unique; // @[util.scala:505:22] reg uops_8_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_8_csr_cmd; // @[util.scala:505:22] reg uops_8_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_8_ldst; // @[util.scala:505:22] reg [5:0] uops_8_lrs1; // @[util.scala:505:22] reg [5:0] uops_8_lrs2; // @[util.scala:505:22] reg [5:0] uops_8_lrs3; // @[util.scala:505:22] reg [1:0] uops_8_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:505:22] reg uops_8_frs3_en; // @[util.scala:505:22] reg uops_8_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_8_fcn_op; // @[util.scala:505:22] reg uops_8_fp_val; // @[util.scala:505:22] reg [2:0] uops_8_fp_rm; // @[util.scala:505:22] reg [1:0] uops_8_fp_typ; // @[util.scala:505:22] reg uops_8_xcpt_pf_if; // @[util.scala:505:22] reg uops_8_xcpt_ae_if; // @[util.scala:505:22] reg uops_8_xcpt_ma_if; // @[util.scala:505:22] reg uops_8_bp_debug_if; // @[util.scala:505:22] reg uops_8_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_8_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_8_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_9_inst; // @[util.scala:505:22] reg [31:0] uops_9_debug_inst; // @[util.scala:505:22] reg uops_9_is_rvc; // @[util.scala:505:22] reg [39:0] uops_9_debug_pc; // @[util.scala:505:22] reg uops_9_iq_type_0; // @[util.scala:505:22] reg uops_9_iq_type_1; // @[util.scala:505:22] reg uops_9_iq_type_2; // @[util.scala:505:22] reg uops_9_iq_type_3; // @[util.scala:505:22] reg uops_9_fu_code_0; // @[util.scala:505:22] reg uops_9_fu_code_1; // @[util.scala:505:22] reg uops_9_fu_code_2; // @[util.scala:505:22] reg uops_9_fu_code_3; // @[util.scala:505:22] reg uops_9_fu_code_4; // @[util.scala:505:22] reg uops_9_fu_code_5; // @[util.scala:505:22] reg uops_9_fu_code_6; // @[util.scala:505:22] reg uops_9_fu_code_7; // @[util.scala:505:22] reg uops_9_fu_code_8; // @[util.scala:505:22] reg uops_9_fu_code_9; // @[util.scala:505:22] reg uops_9_iw_issued; // @[util.scala:505:22] reg uops_9_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_9_iw_issued_partial_dgen; // @[util.scala:505:22] reg [1:0] uops_9_iw_p1_speculative_child; // @[util.scala:505:22] reg [1:0] uops_9_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_9_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p3_bypass_hint; // @[util.scala:505:22] reg [1:0] uops_9_dis_col_sel; // @[util.scala:505:22] reg [11:0] uops_9_br_mask; // @[util.scala:505:22] reg [3:0] uops_9_br_tag; // @[util.scala:505:22] reg [3:0] uops_9_br_type; // @[util.scala:505:22] reg uops_9_is_sfb; // @[util.scala:505:22] reg uops_9_is_fence; // @[util.scala:505:22] reg uops_9_is_fencei; // @[util.scala:505:22] reg uops_9_is_sfence; // @[util.scala:505:22] reg uops_9_is_amo; // @[util.scala:505:22] reg uops_9_is_eret; // @[util.scala:505:22] reg uops_9_is_sys_pc2epc; // @[util.scala:505:22] reg uops_9_is_rocc; // @[util.scala:505:22] reg uops_9_is_mov; // @[util.scala:505:22] reg [4:0] uops_9_ftq_idx; // @[util.scala:505:22] reg uops_9_edge_inst; // @[util.scala:505:22] reg [5:0] uops_9_pc_lob; // @[util.scala:505:22] reg uops_9_taken; // @[util.scala:505:22] reg uops_9_imm_rename; // @[util.scala:505:22] reg [2:0] uops_9_imm_sel; // @[util.scala:505:22] reg [4:0] uops_9_pimm; // @[util.scala:505:22] reg [19:0] uops_9_imm_packed; // @[util.scala:505:22] reg [1:0] uops_9_op1_sel; // @[util.scala:505:22] reg [2:0] uops_9_op2_sel; // @[util.scala:505:22] reg uops_9_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_9_fp_ctrl_wen; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_9_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_9_fp_ctrl_toint; // @[util.scala:505:22] reg uops_9_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_9_fp_ctrl_fma; // @[util.scala:505:22] reg uops_9_fp_ctrl_div; // @[util.scala:505:22] reg uops_9_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_9_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_9_fp_ctrl_vec; // @[util.scala:505:22] reg [5:0] uops_9_rob_idx; // @[util.scala:505:22] reg [3:0] uops_9_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_9_stq_idx; // @[util.scala:505:22] reg [1:0] uops_9_rxq_idx; // @[util.scala:505:22] reg [6:0] uops_9_pdst; // @[util.scala:505:22] reg [6:0] uops_9_prs1; // @[util.scala:505:22] reg [6:0] uops_9_prs2; // @[util.scala:505:22] reg [6:0] uops_9_prs3; // @[util.scala:505:22] reg [4:0] uops_9_ppred; // @[util.scala:505:22] reg uops_9_prs1_busy; // @[util.scala:505:22] reg uops_9_prs2_busy; // @[util.scala:505:22] reg uops_9_prs3_busy; // @[util.scala:505:22] reg uops_9_ppred_busy; // @[util.scala:505:22] reg [6:0] uops_9_stale_pdst; // @[util.scala:505:22] reg uops_9_exception; // @[util.scala:505:22] reg [63:0] uops_9_exc_cause; // @[util.scala:505:22] reg [4:0] uops_9_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_9_mem_size; // @[util.scala:505:22] reg uops_9_mem_signed; // @[util.scala:505:22] reg uops_9_uses_ldq; // @[util.scala:505:22] reg uops_9_uses_stq; // @[util.scala:505:22] reg uops_9_is_unique; // @[util.scala:505:22] reg uops_9_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_9_csr_cmd; // @[util.scala:505:22] reg uops_9_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_9_ldst; // @[util.scala:505:22] reg [5:0] uops_9_lrs1; // @[util.scala:505:22] reg [5:0] uops_9_lrs2; // @[util.scala:505:22] reg [5:0] uops_9_lrs3; // @[util.scala:505:22] reg [1:0] uops_9_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:505:22] reg uops_9_frs3_en; // @[util.scala:505:22] reg uops_9_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_9_fcn_op; // @[util.scala:505:22] reg uops_9_fp_val; // @[util.scala:505:22] reg [2:0] uops_9_fp_rm; // @[util.scala:505:22] reg [1:0] uops_9_fp_typ; // @[util.scala:505:22] reg uops_9_xcpt_pf_if; // @[util.scala:505:22] reg uops_9_xcpt_ae_if; // @[util.scala:505:22] reg uops_9_xcpt_ma_if; // @[util.scala:505:22] reg uops_9_bp_debug_if; // @[util.scala:505:22] reg uops_9_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_9_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_9_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_10_inst; // @[util.scala:505:22] reg [31:0] uops_10_debug_inst; // @[util.scala:505:22] reg uops_10_is_rvc; // @[util.scala:505:22] reg [39:0] uops_10_debug_pc; // @[util.scala:505:22] reg uops_10_iq_type_0; // @[util.scala:505:22] reg uops_10_iq_type_1; // @[util.scala:505:22] reg uops_10_iq_type_2; // @[util.scala:505:22] reg uops_10_iq_type_3; // @[util.scala:505:22] reg uops_10_fu_code_0; // @[util.scala:505:22] reg uops_10_fu_code_1; // @[util.scala:505:22] reg uops_10_fu_code_2; // @[util.scala:505:22] reg uops_10_fu_code_3; // @[util.scala:505:22] reg uops_10_fu_code_4; // @[util.scala:505:22] reg uops_10_fu_code_5; // @[util.scala:505:22] reg uops_10_fu_code_6; // @[util.scala:505:22] reg uops_10_fu_code_7; // @[util.scala:505:22] reg uops_10_fu_code_8; // @[util.scala:505:22] reg uops_10_fu_code_9; // @[util.scala:505:22] reg uops_10_iw_issued; // @[util.scala:505:22] reg uops_10_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_10_iw_issued_partial_dgen; // @[util.scala:505:22] reg [1:0] uops_10_iw_p1_speculative_child; // @[util.scala:505:22] reg [1:0] uops_10_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_10_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p3_bypass_hint; // @[util.scala:505:22] reg [1:0] uops_10_dis_col_sel; // @[util.scala:505:22] reg [11:0] uops_10_br_mask; // @[util.scala:505:22] reg [3:0] uops_10_br_tag; // @[util.scala:505:22] reg [3:0] uops_10_br_type; // @[util.scala:505:22] reg uops_10_is_sfb; // @[util.scala:505:22] reg uops_10_is_fence; // @[util.scala:505:22] reg uops_10_is_fencei; // @[util.scala:505:22] reg uops_10_is_sfence; // @[util.scala:505:22] reg uops_10_is_amo; // @[util.scala:505:22] reg uops_10_is_eret; // @[util.scala:505:22] reg uops_10_is_sys_pc2epc; // @[util.scala:505:22] reg uops_10_is_rocc; // @[util.scala:505:22] reg uops_10_is_mov; // @[util.scala:505:22] reg [4:0] uops_10_ftq_idx; // @[util.scala:505:22] reg uops_10_edge_inst; // @[util.scala:505:22] reg [5:0] uops_10_pc_lob; // @[util.scala:505:22] reg uops_10_taken; // @[util.scala:505:22] reg uops_10_imm_rename; // @[util.scala:505:22] reg [2:0] uops_10_imm_sel; // @[util.scala:505:22] reg [4:0] uops_10_pimm; // @[util.scala:505:22] reg [19:0] uops_10_imm_packed; // @[util.scala:505:22] reg [1:0] uops_10_op1_sel; // @[util.scala:505:22] reg [2:0] uops_10_op2_sel; // @[util.scala:505:22] reg uops_10_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_10_fp_ctrl_wen; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_10_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_10_fp_ctrl_toint; // @[util.scala:505:22] reg uops_10_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_10_fp_ctrl_fma; // @[util.scala:505:22] reg uops_10_fp_ctrl_div; // @[util.scala:505:22] reg uops_10_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_10_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_10_fp_ctrl_vec; // @[util.scala:505:22] reg [5:0] uops_10_rob_idx; // @[util.scala:505:22] reg [3:0] uops_10_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_10_stq_idx; // @[util.scala:505:22] reg [1:0] uops_10_rxq_idx; // @[util.scala:505:22] reg [6:0] uops_10_pdst; // @[util.scala:505:22] reg [6:0] uops_10_prs1; // @[util.scala:505:22] reg [6:0] uops_10_prs2; // @[util.scala:505:22] reg [6:0] uops_10_prs3; // @[util.scala:505:22] reg [4:0] uops_10_ppred; // @[util.scala:505:22] reg uops_10_prs1_busy; // @[util.scala:505:22] reg uops_10_prs2_busy; // @[util.scala:505:22] reg uops_10_prs3_busy; // @[util.scala:505:22] reg uops_10_ppred_busy; // @[util.scala:505:22] reg [6:0] uops_10_stale_pdst; // @[util.scala:505:22] reg uops_10_exception; // @[util.scala:505:22] reg [63:0] uops_10_exc_cause; // @[util.scala:505:22] reg [4:0] uops_10_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_10_mem_size; // @[util.scala:505:22] reg uops_10_mem_signed; // @[util.scala:505:22] reg uops_10_uses_ldq; // @[util.scala:505:22] reg uops_10_uses_stq; // @[util.scala:505:22] reg uops_10_is_unique; // @[util.scala:505:22] reg uops_10_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_10_csr_cmd; // @[util.scala:505:22] reg uops_10_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_10_ldst; // @[util.scala:505:22] reg [5:0] uops_10_lrs1; // @[util.scala:505:22] reg [5:0] uops_10_lrs2; // @[util.scala:505:22] reg [5:0] uops_10_lrs3; // @[util.scala:505:22] reg [1:0] uops_10_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:505:22] reg uops_10_frs3_en; // @[util.scala:505:22] reg uops_10_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_10_fcn_op; // @[util.scala:505:22] reg uops_10_fp_val; // @[util.scala:505:22] reg [2:0] uops_10_fp_rm; // @[util.scala:505:22] reg [1:0] uops_10_fp_typ; // @[util.scala:505:22] reg uops_10_xcpt_pf_if; // @[util.scala:505:22] reg uops_10_xcpt_ae_if; // @[util.scala:505:22] reg uops_10_xcpt_ma_if; // @[util.scala:505:22] reg uops_10_bp_debug_if; // @[util.scala:505:22] reg uops_10_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_10_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_10_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_11_inst; // @[util.scala:505:22] reg [31:0] uops_11_debug_inst; // @[util.scala:505:22] reg uops_11_is_rvc; // @[util.scala:505:22] reg [39:0] uops_11_debug_pc; // @[util.scala:505:22] reg uops_11_iq_type_0; // @[util.scala:505:22] reg uops_11_iq_type_1; // @[util.scala:505:22] reg uops_11_iq_type_2; // @[util.scala:505:22] reg uops_11_iq_type_3; // @[util.scala:505:22] reg uops_11_fu_code_0; // @[util.scala:505:22] reg uops_11_fu_code_1; // @[util.scala:505:22] reg uops_11_fu_code_2; // @[util.scala:505:22] reg uops_11_fu_code_3; // @[util.scala:505:22] reg uops_11_fu_code_4; // @[util.scala:505:22] reg uops_11_fu_code_5; // @[util.scala:505:22] reg uops_11_fu_code_6; // @[util.scala:505:22] reg uops_11_fu_code_7; // @[util.scala:505:22] reg uops_11_fu_code_8; // @[util.scala:505:22] reg uops_11_fu_code_9; // @[util.scala:505:22] reg uops_11_iw_issued; // @[util.scala:505:22] reg uops_11_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_11_iw_issued_partial_dgen; // @[util.scala:505:22] reg [1:0] uops_11_iw_p1_speculative_child; // @[util.scala:505:22] reg [1:0] uops_11_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_11_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p3_bypass_hint; // @[util.scala:505:22] reg [1:0] uops_11_dis_col_sel; // @[util.scala:505:22] reg [11:0] uops_11_br_mask; // @[util.scala:505:22] reg [3:0] uops_11_br_tag; // @[util.scala:505:22] reg [3:0] uops_11_br_type; // @[util.scala:505:22] reg uops_11_is_sfb; // @[util.scala:505:22] reg uops_11_is_fence; // @[util.scala:505:22] reg uops_11_is_fencei; // @[util.scala:505:22] reg uops_11_is_sfence; // @[util.scala:505:22] reg uops_11_is_amo; // @[util.scala:505:22] reg uops_11_is_eret; // @[util.scala:505:22] reg uops_11_is_sys_pc2epc; // @[util.scala:505:22] reg uops_11_is_rocc; // @[util.scala:505:22] reg uops_11_is_mov; // @[util.scala:505:22] reg [4:0] uops_11_ftq_idx; // @[util.scala:505:22] reg uops_11_edge_inst; // @[util.scala:505:22] reg [5:0] uops_11_pc_lob; // @[util.scala:505:22] reg uops_11_taken; // @[util.scala:505:22] reg uops_11_imm_rename; // @[util.scala:505:22] reg [2:0] uops_11_imm_sel; // @[util.scala:505:22] reg [4:0] uops_11_pimm; // @[util.scala:505:22] reg [19:0] uops_11_imm_packed; // @[util.scala:505:22] reg [1:0] uops_11_op1_sel; // @[util.scala:505:22] reg [2:0] uops_11_op2_sel; // @[util.scala:505:22] reg uops_11_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_11_fp_ctrl_wen; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_11_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_11_fp_ctrl_toint; // @[util.scala:505:22] reg uops_11_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_11_fp_ctrl_fma; // @[util.scala:505:22] reg uops_11_fp_ctrl_div; // @[util.scala:505:22] reg uops_11_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_11_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_11_fp_ctrl_vec; // @[util.scala:505:22] reg [5:0] uops_11_rob_idx; // @[util.scala:505:22] reg [3:0] uops_11_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_11_stq_idx; // @[util.scala:505:22] reg [1:0] uops_11_rxq_idx; // @[util.scala:505:22] reg [6:0] uops_11_pdst; // @[util.scala:505:22] reg [6:0] uops_11_prs1; // @[util.scala:505:22] reg [6:0] uops_11_prs2; // @[util.scala:505:22] reg [6:0] uops_11_prs3; // @[util.scala:505:22] reg [4:0] uops_11_ppred; // @[util.scala:505:22] reg uops_11_prs1_busy; // @[util.scala:505:22] reg uops_11_prs2_busy; // @[util.scala:505:22] reg uops_11_prs3_busy; // @[util.scala:505:22] reg uops_11_ppred_busy; // @[util.scala:505:22] reg [6:0] uops_11_stale_pdst; // @[util.scala:505:22] reg uops_11_exception; // @[util.scala:505:22] reg [63:0] uops_11_exc_cause; // @[util.scala:505:22] reg [4:0] uops_11_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_11_mem_size; // @[util.scala:505:22] reg uops_11_mem_signed; // @[util.scala:505:22] reg uops_11_uses_ldq; // @[util.scala:505:22] reg uops_11_uses_stq; // @[util.scala:505:22] reg uops_11_is_unique; // @[util.scala:505:22] reg uops_11_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_11_csr_cmd; // @[util.scala:505:22] reg uops_11_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_11_ldst; // @[util.scala:505:22] reg [5:0] uops_11_lrs1; // @[util.scala:505:22] reg [5:0] uops_11_lrs2; // @[util.scala:505:22] reg [5:0] uops_11_lrs3; // @[util.scala:505:22] reg [1:0] uops_11_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:505:22] reg uops_11_frs3_en; // @[util.scala:505:22] reg uops_11_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_11_fcn_op; // @[util.scala:505:22] reg uops_11_fp_val; // @[util.scala:505:22] reg [2:0] uops_11_fp_rm; // @[util.scala:505:22] reg [1:0] uops_11_fp_typ; // @[util.scala:505:22] reg uops_11_xcpt_pf_if; // @[util.scala:505:22] reg uops_11_xcpt_ae_if; // @[util.scala:505:22] reg uops_11_xcpt_ma_if; // @[util.scala:505:22] reg uops_11_bp_debug_if; // @[util.scala:505:22] reg uops_11_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_11_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_11_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_12_inst; // @[util.scala:505:22] reg [31:0] uops_12_debug_inst; // @[util.scala:505:22] reg uops_12_is_rvc; // @[util.scala:505:22] reg [39:0] uops_12_debug_pc; // @[util.scala:505:22] reg uops_12_iq_type_0; // @[util.scala:505:22] reg uops_12_iq_type_1; // @[util.scala:505:22] reg uops_12_iq_type_2; // @[util.scala:505:22] reg uops_12_iq_type_3; // @[util.scala:505:22] reg uops_12_fu_code_0; // @[util.scala:505:22] reg uops_12_fu_code_1; // @[util.scala:505:22] reg uops_12_fu_code_2; // @[util.scala:505:22] reg uops_12_fu_code_3; // @[util.scala:505:22] reg uops_12_fu_code_4; // @[util.scala:505:22] reg uops_12_fu_code_5; // @[util.scala:505:22] reg uops_12_fu_code_6; // @[util.scala:505:22] reg uops_12_fu_code_7; // @[util.scala:505:22] reg uops_12_fu_code_8; // @[util.scala:505:22] reg uops_12_fu_code_9; // @[util.scala:505:22] reg uops_12_iw_issued; // @[util.scala:505:22] reg uops_12_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_12_iw_issued_partial_dgen; // @[util.scala:505:22] reg [1:0] uops_12_iw_p1_speculative_child; // @[util.scala:505:22] reg [1:0] uops_12_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_12_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p3_bypass_hint; // @[util.scala:505:22] reg [1:0] uops_12_dis_col_sel; // @[util.scala:505:22] reg [11:0] uops_12_br_mask; // @[util.scala:505:22] reg [3:0] uops_12_br_tag; // @[util.scala:505:22] reg [3:0] uops_12_br_type; // @[util.scala:505:22] reg uops_12_is_sfb; // @[util.scala:505:22] reg uops_12_is_fence; // @[util.scala:505:22] reg uops_12_is_fencei; // @[util.scala:505:22] reg uops_12_is_sfence; // @[util.scala:505:22] reg uops_12_is_amo; // @[util.scala:505:22] reg uops_12_is_eret; // @[util.scala:505:22] reg uops_12_is_sys_pc2epc; // @[util.scala:505:22] reg uops_12_is_rocc; // @[util.scala:505:22] reg uops_12_is_mov; // @[util.scala:505:22] reg [4:0] uops_12_ftq_idx; // @[util.scala:505:22] reg uops_12_edge_inst; // @[util.scala:505:22] reg [5:0] uops_12_pc_lob; // @[util.scala:505:22] reg uops_12_taken; // @[util.scala:505:22] reg uops_12_imm_rename; // @[util.scala:505:22] reg [2:0] uops_12_imm_sel; // @[util.scala:505:22] reg [4:0] uops_12_pimm; // @[util.scala:505:22] reg [19:0] uops_12_imm_packed; // @[util.scala:505:22] reg [1:0] uops_12_op1_sel; // @[util.scala:505:22] reg [2:0] uops_12_op2_sel; // @[util.scala:505:22] reg uops_12_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_12_fp_ctrl_wen; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_12_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_12_fp_ctrl_toint; // @[util.scala:505:22] reg uops_12_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_12_fp_ctrl_fma; // @[util.scala:505:22] reg uops_12_fp_ctrl_div; // @[util.scala:505:22] reg uops_12_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_12_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_12_fp_ctrl_vec; // @[util.scala:505:22] reg [5:0] uops_12_rob_idx; // @[util.scala:505:22] reg [3:0] uops_12_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_12_stq_idx; // @[util.scala:505:22] reg [1:0] uops_12_rxq_idx; // @[util.scala:505:22] reg [6:0] uops_12_pdst; // @[util.scala:505:22] reg [6:0] uops_12_prs1; // @[util.scala:505:22] reg [6:0] uops_12_prs2; // @[util.scala:505:22] reg [6:0] uops_12_prs3; // @[util.scala:505:22] reg [4:0] uops_12_ppred; // @[util.scala:505:22] reg uops_12_prs1_busy; // @[util.scala:505:22] reg uops_12_prs2_busy; // @[util.scala:505:22] reg uops_12_prs3_busy; // @[util.scala:505:22] reg uops_12_ppred_busy; // @[util.scala:505:22] reg [6:0] uops_12_stale_pdst; // @[util.scala:505:22] reg uops_12_exception; // @[util.scala:505:22] reg [63:0] uops_12_exc_cause; // @[util.scala:505:22] reg [4:0] uops_12_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_12_mem_size; // @[util.scala:505:22] reg uops_12_mem_signed; // @[util.scala:505:22] reg uops_12_uses_ldq; // @[util.scala:505:22] reg uops_12_uses_stq; // @[util.scala:505:22] reg uops_12_is_unique; // @[util.scala:505:22] reg uops_12_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_12_csr_cmd; // @[util.scala:505:22] reg uops_12_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_12_ldst; // @[util.scala:505:22] reg [5:0] uops_12_lrs1; // @[util.scala:505:22] reg [5:0] uops_12_lrs2; // @[util.scala:505:22] reg [5:0] uops_12_lrs3; // @[util.scala:505:22] reg [1:0] uops_12_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:505:22] reg uops_12_frs3_en; // @[util.scala:505:22] reg uops_12_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_12_fcn_op; // @[util.scala:505:22] reg uops_12_fp_val; // @[util.scala:505:22] reg [2:0] uops_12_fp_rm; // @[util.scala:505:22] reg [1:0] uops_12_fp_typ; // @[util.scala:505:22] reg uops_12_xcpt_pf_if; // @[util.scala:505:22] reg uops_12_xcpt_ae_if; // @[util.scala:505:22] reg uops_12_xcpt_ma_if; // @[util.scala:505:22] reg uops_12_bp_debug_if; // @[util.scala:505:22] reg uops_12_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_12_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_12_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_13_inst; // @[util.scala:505:22] reg [31:0] uops_13_debug_inst; // @[util.scala:505:22] reg uops_13_is_rvc; // @[util.scala:505:22] reg [39:0] uops_13_debug_pc; // @[util.scala:505:22] reg uops_13_iq_type_0; // @[util.scala:505:22] reg uops_13_iq_type_1; // @[util.scala:505:22] reg uops_13_iq_type_2; // @[util.scala:505:22] reg uops_13_iq_type_3; // @[util.scala:505:22] reg uops_13_fu_code_0; // @[util.scala:505:22] reg uops_13_fu_code_1; // @[util.scala:505:22] reg uops_13_fu_code_2; // @[util.scala:505:22] reg uops_13_fu_code_3; // @[util.scala:505:22] reg uops_13_fu_code_4; // @[util.scala:505:22] reg uops_13_fu_code_5; // @[util.scala:505:22] reg uops_13_fu_code_6; // @[util.scala:505:22] reg uops_13_fu_code_7; // @[util.scala:505:22] reg uops_13_fu_code_8; // @[util.scala:505:22] reg uops_13_fu_code_9; // @[util.scala:505:22] reg uops_13_iw_issued; // @[util.scala:505:22] reg uops_13_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_13_iw_issued_partial_dgen; // @[util.scala:505:22] reg [1:0] uops_13_iw_p1_speculative_child; // @[util.scala:505:22] reg [1:0] uops_13_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_13_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p3_bypass_hint; // @[util.scala:505:22] reg [1:0] uops_13_dis_col_sel; // @[util.scala:505:22] reg [11:0] uops_13_br_mask; // @[util.scala:505:22] reg [3:0] uops_13_br_tag; // @[util.scala:505:22] reg [3:0] uops_13_br_type; // @[util.scala:505:22] reg uops_13_is_sfb; // @[util.scala:505:22] reg uops_13_is_fence; // @[util.scala:505:22] reg uops_13_is_fencei; // @[util.scala:505:22] reg uops_13_is_sfence; // @[util.scala:505:22] reg uops_13_is_amo; // @[util.scala:505:22] reg uops_13_is_eret; // @[util.scala:505:22] reg uops_13_is_sys_pc2epc; // @[util.scala:505:22] reg uops_13_is_rocc; // @[util.scala:505:22] reg uops_13_is_mov; // @[util.scala:505:22] reg [4:0] uops_13_ftq_idx; // @[util.scala:505:22] reg uops_13_edge_inst; // @[util.scala:505:22] reg [5:0] uops_13_pc_lob; // @[util.scala:505:22] reg uops_13_taken; // @[util.scala:505:22] reg uops_13_imm_rename; // @[util.scala:505:22] reg [2:0] uops_13_imm_sel; // @[util.scala:505:22] reg [4:0] uops_13_pimm; // @[util.scala:505:22] reg [19:0] uops_13_imm_packed; // @[util.scala:505:22] reg [1:0] uops_13_op1_sel; // @[util.scala:505:22] reg [2:0] uops_13_op2_sel; // @[util.scala:505:22] reg uops_13_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_13_fp_ctrl_wen; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_13_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_13_fp_ctrl_toint; // @[util.scala:505:22] reg uops_13_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_13_fp_ctrl_fma; // @[util.scala:505:22] reg uops_13_fp_ctrl_div; // @[util.scala:505:22] reg uops_13_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_13_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_13_fp_ctrl_vec; // @[util.scala:505:22] reg [5:0] uops_13_rob_idx; // @[util.scala:505:22] reg [3:0] uops_13_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_13_stq_idx; // @[util.scala:505:22] reg [1:0] uops_13_rxq_idx; // @[util.scala:505:22] reg [6:0] uops_13_pdst; // @[util.scala:505:22] reg [6:0] uops_13_prs1; // @[util.scala:505:22] reg [6:0] uops_13_prs2; // @[util.scala:505:22] reg [6:0] uops_13_prs3; // @[util.scala:505:22] reg [4:0] uops_13_ppred; // @[util.scala:505:22] reg uops_13_prs1_busy; // @[util.scala:505:22] reg uops_13_prs2_busy; // @[util.scala:505:22] reg uops_13_prs3_busy; // @[util.scala:505:22] reg uops_13_ppred_busy; // @[util.scala:505:22] reg [6:0] uops_13_stale_pdst; // @[util.scala:505:22] reg uops_13_exception; // @[util.scala:505:22] reg [63:0] uops_13_exc_cause; // @[util.scala:505:22] reg [4:0] uops_13_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_13_mem_size; // @[util.scala:505:22] reg uops_13_mem_signed; // @[util.scala:505:22] reg uops_13_uses_ldq; // @[util.scala:505:22] reg uops_13_uses_stq; // @[util.scala:505:22] reg uops_13_is_unique; // @[util.scala:505:22] reg uops_13_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_13_csr_cmd; // @[util.scala:505:22] reg uops_13_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_13_ldst; // @[util.scala:505:22] reg [5:0] uops_13_lrs1; // @[util.scala:505:22] reg [5:0] uops_13_lrs2; // @[util.scala:505:22] reg [5:0] uops_13_lrs3; // @[util.scala:505:22] reg [1:0] uops_13_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:505:22] reg uops_13_frs3_en; // @[util.scala:505:22] reg uops_13_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_13_fcn_op; // @[util.scala:505:22] reg uops_13_fp_val; // @[util.scala:505:22] reg [2:0] uops_13_fp_rm; // @[util.scala:505:22] reg [1:0] uops_13_fp_typ; // @[util.scala:505:22] reg uops_13_xcpt_pf_if; // @[util.scala:505:22] reg uops_13_xcpt_ae_if; // @[util.scala:505:22] reg uops_13_xcpt_ma_if; // @[util.scala:505:22] reg uops_13_bp_debug_if; // @[util.scala:505:22] reg uops_13_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_13_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_13_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_14_inst; // @[util.scala:505:22] reg [31:0] uops_14_debug_inst; // @[util.scala:505:22] reg uops_14_is_rvc; // @[util.scala:505:22] reg [39:0] uops_14_debug_pc; // @[util.scala:505:22] reg uops_14_iq_type_0; // @[util.scala:505:22] reg uops_14_iq_type_1; // @[util.scala:505:22] reg uops_14_iq_type_2; // @[util.scala:505:22] reg uops_14_iq_type_3; // @[util.scala:505:22] reg uops_14_fu_code_0; // @[util.scala:505:22] reg uops_14_fu_code_1; // @[util.scala:505:22] reg uops_14_fu_code_2; // @[util.scala:505:22] reg uops_14_fu_code_3; // @[util.scala:505:22] reg uops_14_fu_code_4; // @[util.scala:505:22] reg uops_14_fu_code_5; // @[util.scala:505:22] reg uops_14_fu_code_6; // @[util.scala:505:22] reg uops_14_fu_code_7; // @[util.scala:505:22] reg uops_14_fu_code_8; // @[util.scala:505:22] reg uops_14_fu_code_9; // @[util.scala:505:22] reg uops_14_iw_issued; // @[util.scala:505:22] reg uops_14_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_14_iw_issued_partial_dgen; // @[util.scala:505:22] reg [1:0] uops_14_iw_p1_speculative_child; // @[util.scala:505:22] reg [1:0] uops_14_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_14_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p3_bypass_hint; // @[util.scala:505:22] reg [1:0] uops_14_dis_col_sel; // @[util.scala:505:22] reg [11:0] uops_14_br_mask; // @[util.scala:505:22] reg [3:0] uops_14_br_tag; // @[util.scala:505:22] reg [3:0] uops_14_br_type; // @[util.scala:505:22] reg uops_14_is_sfb; // @[util.scala:505:22] reg uops_14_is_fence; // @[util.scala:505:22] reg uops_14_is_fencei; // @[util.scala:505:22] reg uops_14_is_sfence; // @[util.scala:505:22] reg uops_14_is_amo; // @[util.scala:505:22] reg uops_14_is_eret; // @[util.scala:505:22] reg uops_14_is_sys_pc2epc; // @[util.scala:505:22] reg uops_14_is_rocc; // @[util.scala:505:22] reg uops_14_is_mov; // @[util.scala:505:22] reg [4:0] uops_14_ftq_idx; // @[util.scala:505:22] reg uops_14_edge_inst; // @[util.scala:505:22] reg [5:0] uops_14_pc_lob; // @[util.scala:505:22] reg uops_14_taken; // @[util.scala:505:22] reg uops_14_imm_rename; // @[util.scala:505:22] reg [2:0] uops_14_imm_sel; // @[util.scala:505:22] reg [4:0] uops_14_pimm; // @[util.scala:505:22] reg [19:0] uops_14_imm_packed; // @[util.scala:505:22] reg [1:0] uops_14_op1_sel; // @[util.scala:505:22] reg [2:0] uops_14_op2_sel; // @[util.scala:505:22] reg uops_14_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_14_fp_ctrl_wen; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_14_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_14_fp_ctrl_toint; // @[util.scala:505:22] reg uops_14_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_14_fp_ctrl_fma; // @[util.scala:505:22] reg uops_14_fp_ctrl_div; // @[util.scala:505:22] reg uops_14_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_14_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_14_fp_ctrl_vec; // @[util.scala:505:22] reg [5:0] uops_14_rob_idx; // @[util.scala:505:22] reg [3:0] uops_14_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_14_stq_idx; // @[util.scala:505:22] reg [1:0] uops_14_rxq_idx; // @[util.scala:505:22] reg [6:0] uops_14_pdst; // @[util.scala:505:22] reg [6:0] uops_14_prs1; // @[util.scala:505:22] reg [6:0] uops_14_prs2; // @[util.scala:505:22] reg [6:0] uops_14_prs3; // @[util.scala:505:22] reg [4:0] uops_14_ppred; // @[util.scala:505:22] reg uops_14_prs1_busy; // @[util.scala:505:22] reg uops_14_prs2_busy; // @[util.scala:505:22] reg uops_14_prs3_busy; // @[util.scala:505:22] reg uops_14_ppred_busy; // @[util.scala:505:22] reg [6:0] uops_14_stale_pdst; // @[util.scala:505:22] reg uops_14_exception; // @[util.scala:505:22] reg [63:0] uops_14_exc_cause; // @[util.scala:505:22] reg [4:0] uops_14_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_14_mem_size; // @[util.scala:505:22] reg uops_14_mem_signed; // @[util.scala:505:22] reg uops_14_uses_ldq; // @[util.scala:505:22] reg uops_14_uses_stq; // @[util.scala:505:22] reg uops_14_is_unique; // @[util.scala:505:22] reg uops_14_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_14_csr_cmd; // @[util.scala:505:22] reg uops_14_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_14_ldst; // @[util.scala:505:22] reg [5:0] uops_14_lrs1; // @[util.scala:505:22] reg [5:0] uops_14_lrs2; // @[util.scala:505:22] reg [5:0] uops_14_lrs3; // @[util.scala:505:22] reg [1:0] uops_14_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:505:22] reg uops_14_frs3_en; // @[util.scala:505:22] reg uops_14_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_14_fcn_op; // @[util.scala:505:22] reg uops_14_fp_val; // @[util.scala:505:22] reg [2:0] uops_14_fp_rm; // @[util.scala:505:22] reg [1:0] uops_14_fp_typ; // @[util.scala:505:22] reg uops_14_xcpt_pf_if; // @[util.scala:505:22] reg uops_14_xcpt_ae_if; // @[util.scala:505:22] reg uops_14_xcpt_ma_if; // @[util.scala:505:22] reg uops_14_bp_debug_if; // @[util.scala:505:22] reg uops_14_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_14_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_14_debug_tsrc; // @[util.scala:505:22] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:509:29] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:509:29, :512:30] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:511:35, :512:{27,30}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :512:27] wire full = ptr_match & maybe_full; // @[util.scala:509:29, :511:35, :513:26] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire [11:0] _do_enq_T_1 = io_brupdate_b1_mispredict_mask_0 & io_enq_bits_uop_br_mask_0; // @[util.scala:126:51, :458:7] wire _do_enq_T_2 = |_do_enq_T_1; // @[util.scala:126:{51,59}] wire _do_enq_T_3 = _do_enq_T_2; // @[util.scala:61:61, :126:59] wire _do_enq_T_4 = ~_do_enq_T_3; // @[util.scala:61:61, :514:42] wire _do_enq_T_5 = _do_enq_T & _do_enq_T_4; // @[Decoupled.scala:51:35] wire _do_enq_T_6 = io_flush_0 & io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :514:113] wire _do_enq_T_7 = ~_do_enq_T_6; // @[util.scala:514:{102,113}] wire _do_enq_T_8 = _do_enq_T_5 & _do_enq_T_7; // @[util.scala:514:{39,99,102}] wire do_enq = _do_enq_T_8; // @[util.scala:514:{26,99}] wire [15:0] _GEN = {{valids_0}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:504:26, :515:44] wire _GEN_0 = _GEN[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_0; // @[util.scala:515:44] wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:458:7, :515:{41,44}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:458:7, :515:71] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:515:{41,68,71}] wire do_deq = _do_deq_T_3; // @[util.scala:515:{26,68}] wire [11:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:126:51, :458:7, :505:22] wire _valids_0_T_1 = |_valids_0_T; // @[util.scala:126:{51,59}] wire _valids_0_T_2 = _valids_0_T_1; // @[util.scala:61:61, :126:59] wire _valids_0_T_3 = ~_valids_0_T_2; // @[util.scala:61:61, :520:34] wire _valids_0_T_4 = valids_0 & _valids_0_T_3; // @[util.scala:504:26, :520:{31,34}] wire _valids_0_T_5 = io_flush_0 & uops_0_uses_ldq; // @[util.scala:458:7, :505:22, :520:94] wire _valids_0_T_6 = ~_valids_0_T_5; // @[util.scala:520:{83,94}] wire _valids_0_T_7 = _valids_0_T_4 & _valids_0_T_6; // @[util.scala:520:{31,80,83}] wire [11:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7] wire [11:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:97:{21,23}, :505:22] wire [11:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:126:51, :458:7, :505:22] wire _valids_1_T_1 = |_valids_1_T; // @[util.scala:126:{51,59}] wire _valids_1_T_2 = _valids_1_T_1; // @[util.scala:61:61, :126:59] wire _valids_1_T_3 = ~_valids_1_T_2; // @[util.scala:61:61, :520:34] wire _valids_1_T_4 = valids_1 & _valids_1_T_3; // @[util.scala:504:26, :520:{31,34}] wire _valids_1_T_5 = io_flush_0 & uops_1_uses_ldq; // @[util.scala:458:7, :505:22, :520:94] wire _valids_1_T_6 = ~_valids_1_T_5; // @[util.scala:520:{83,94}] wire _valids_1_T_7 = _valids_1_T_4 & _valids_1_T_6; // @[util.scala:520:{31,80,83}] wire [11:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7] wire [11:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:97:{21,23}, :505:22] wire [11:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:126:51, :458:7, :505:22] wire _valids_2_T_1 = |_valids_2_T; // @[util.scala:126:{51,59}] wire _valids_2_T_2 = _valids_2_T_1; // @[util.scala:61:61, :126:59] wire _valids_2_T_3 = ~_valids_2_T_2; // @[util.scala:61:61, :520:34] wire _valids_2_T_4 = valids_2 & _valids_2_T_3; // @[util.scala:504:26, :520:{31,34}] wire _valids_2_T_5 = io_flush_0 & uops_2_uses_ldq; // @[util.scala:458:7, :505:22, :520:94] wire _valids_2_T_6 = ~_valids_2_T_5; // @[util.scala:520:{83,94}] wire _valids_2_T_7 = _valids_2_T_4 & _valids_2_T_6; // @[util.scala:520:{31,80,83}] wire [11:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7] wire [11:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:97:{21,23}, :505:22] wire [11:0] _valids_3_T = io_brupdate_b1_mispredict_mask_0 & uops_3_br_mask; // @[util.scala:126:51, :458:7, :505:22] wire _valids_3_T_1 = |_valids_3_T; // @[util.scala:126:{51,59}] wire _valids_3_T_2 = _valids_3_T_1; // @[util.scala:61:61, :126:59] wire _valids_3_T_3 = ~_valids_3_T_2; // @[util.scala:61:61, :520:34] wire _valids_3_T_4 = valids_3 & _valids_3_T_3; // @[util.scala:504:26, :520:{31,34}] wire _valids_3_T_5 = io_flush_0 & uops_3_uses_ldq; // @[util.scala:458:7, :505:22, :520:94] wire _valids_3_T_6 = ~_valids_3_T_5; // @[util.scala:520:{83,94}] wire _valids_3_T_7 = _valids_3_T_4 & _valids_3_T_6; // @[util.scala:520:{31,80,83}] wire [11:0] _uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7] wire [11:0] _uops_3_br_mask_T_1 = uops_3_br_mask & _uops_3_br_mask_T; // @[util.scala:97:{21,23}, :505:22] wire [11:0] _valids_4_T = io_brupdate_b1_mispredict_mask_0 & uops_4_br_mask; // @[util.scala:126:51, :458:7, :505:22] wire _valids_4_T_1 = |_valids_4_T; // @[util.scala:126:{51,59}] wire _valids_4_T_2 = _valids_4_T_1; // @[util.scala:61:61, :126:59] wire _valids_4_T_3 = ~_valids_4_T_2; // @[util.scala:61:61, :520:34] wire _valids_4_T_4 = valids_4 & _valids_4_T_3; // @[util.scala:504:26, :520:{31,34}] wire _valids_4_T_5 = io_flush_0 & uops_4_uses_ldq; // @[util.scala:458:7, :505:22, :520:94] wire _valids_4_T_6 = ~_valids_4_T_5; // @[util.scala:520:{83,94}] wire _valids_4_T_7 = _valids_4_T_4 & _valids_4_T_6; // @[util.scala:520:{31,80,83}] wire [11:0] _uops_4_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7] wire [11:0] _uops_4_br_mask_T_1 = uops_4_br_mask & _uops_4_br_mask_T; // @[util.scala:97:{21,23}, :505:22] wire [11:0] _valids_5_T = io_brupdate_b1_mispredict_mask_0 & uops_5_br_mask; // @[util.scala:126:51, :458:7, :505:22] wire _valids_5_T_1 = |_valids_5_T; // @[util.scala:126:{51,59}] wire _valids_5_T_2 = _valids_5_T_1; // @[util.scala:61:61, :126:59] wire _valids_5_T_3 = ~_valids_5_T_2; // @[util.scala:61:61, :520:34] wire _valids_5_T_4 = valids_5 & _valids_5_T_3; // @[util.scala:504:26, :520:{31,34}] wire _valids_5_T_5 = io_flush_0 & uops_5_uses_ldq; // @[util.scala:458:7, :505:22, :520:94] wire _valids_5_T_6 = ~_valids_5_T_5; // @[util.scala:520:{83,94}] wire _valids_5_T_7 = _valids_5_T_4 & _valids_5_T_6; // @[util.scala:520:{31,80,83}] wire [11:0] _uops_5_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7] wire [11:0] _uops_5_br_mask_T_1 = uops_5_br_mask & _uops_5_br_mask_T; // @[util.scala:97:{21,23}, :505:22] wire [11:0] _valids_6_T = io_brupdate_b1_mispredict_mask_0 & uops_6_br_mask; // @[util.scala:126:51, :458:7, :505:22] wire _valids_6_T_1 = |_valids_6_T; // @[util.scala:126:{51,59}] wire _valids_6_T_2 = _valids_6_T_1; // @[util.scala:61:61, :126:59] wire _valids_6_T_3 = ~_valids_6_T_2; // @[util.scala:61:61, :520:34] wire _valids_6_T_4 = valids_6 & _valids_6_T_3; // @[util.scala:504:26, :520:{31,34}] wire _valids_6_T_5 = io_flush_0 & uops_6_uses_ldq; // @[util.scala:458:7, :505:22, :520:94] wire _valids_6_T_6 = ~_valids_6_T_5; // @[util.scala:520:{83,94}] wire _valids_6_T_7 = _valids_6_T_4 & _valids_6_T_6; // @[util.scala:520:{31,80,83}] wire [11:0] _uops_6_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7] wire [11:0] _uops_6_br_mask_T_1 = uops_6_br_mask & _uops_6_br_mask_T; // @[util.scala:97:{21,23}, :505:22] wire [11:0] _valids_7_T = io_brupdate_b1_mispredict_mask_0 & uops_7_br_mask; // @[util.scala:126:51, :458:7, :505:22] wire _valids_7_T_1 = |_valids_7_T; // @[util.scala:126:{51,59}] wire _valids_7_T_2 = _valids_7_T_1; // @[util.scala:61:61, :126:59] wire _valids_7_T_3 = ~_valids_7_T_2; // @[util.scala:61:61, :520:34] wire _valids_7_T_4 = valids_7 & _valids_7_T_3; // @[util.scala:504:26, :520:{31,34}] wire _valids_7_T_5 = io_flush_0 & uops_7_uses_ldq; // @[util.scala:458:7, :505:22, :520:94] wire _valids_7_T_6 = ~_valids_7_T_5; // @[util.scala:520:{83,94}] wire _valids_7_T_7 = _valids_7_T_4 & _valids_7_T_6; // @[util.scala:520:{31,80,83}] wire [11:0] _uops_7_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7] wire [11:0] _uops_7_br_mask_T_1 = uops_7_br_mask & _uops_7_br_mask_T; // @[util.scala:97:{21,23}, :505:22] wire [11:0] _valids_8_T = io_brupdate_b1_mispredict_mask_0 & uops_8_br_mask; // @[util.scala:126:51, :458:7, :505:22] wire _valids_8_T_1 = |_valids_8_T; // @[util.scala:126:{51,59}] wire _valids_8_T_2 = _valids_8_T_1; // @[util.scala:61:61, :126:59] wire _valids_8_T_3 = ~_valids_8_T_2; // @[util.scala:61:61, :520:34] wire _valids_8_T_4 = valids_8 & _valids_8_T_3; // @[util.scala:504:26, :520:{31,34}] wire _valids_8_T_5 = io_flush_0 & uops_8_uses_ldq; // @[util.scala:458:7, :505:22, :520:94] wire _valids_8_T_6 = ~_valids_8_T_5; // @[util.scala:520:{83,94}] wire _valids_8_T_7 = _valids_8_T_4 & _valids_8_T_6; // @[util.scala:520:{31,80,83}] wire [11:0] _uops_8_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7] wire [11:0] _uops_8_br_mask_T_1 = uops_8_br_mask & _uops_8_br_mask_T; // @[util.scala:97:{21,23}, :505:22] wire [11:0] _valids_9_T = io_brupdate_b1_mispredict_mask_0 & uops_9_br_mask; // @[util.scala:126:51, :458:7, :505:22] wire _valids_9_T_1 = |_valids_9_T; // @[util.scala:126:{51,59}] wire _valids_9_T_2 = _valids_9_T_1; // @[util.scala:61:61, :126:59] wire _valids_9_T_3 = ~_valids_9_T_2; // @[util.scala:61:61, :520:34] wire _valids_9_T_4 = valids_9 & _valids_9_T_3; // @[util.scala:504:26, :520:{31,34}] wire _valids_9_T_5 = io_flush_0 & uops_9_uses_ldq; // @[util.scala:458:7, :505:22, :520:94] wire _valids_9_T_6 = ~_valids_9_T_5; // @[util.scala:520:{83,94}] wire _valids_9_T_7 = _valids_9_T_4 & _valids_9_T_6; // @[util.scala:520:{31,80,83}] wire [11:0] _uops_9_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7] wire [11:0] _uops_9_br_mask_T_1 = uops_9_br_mask & _uops_9_br_mask_T; // @[util.scala:97:{21,23}, :505:22] wire [11:0] _valids_10_T = io_brupdate_b1_mispredict_mask_0 & uops_10_br_mask; // @[util.scala:126:51, :458:7, :505:22] wire _valids_10_T_1 = |_valids_10_T; // @[util.scala:126:{51,59}] wire _valids_10_T_2 = _valids_10_T_1; // @[util.scala:61:61, :126:59] wire _valids_10_T_3 = ~_valids_10_T_2; // @[util.scala:61:61, :520:34] wire _valids_10_T_4 = valids_10 & _valids_10_T_3; // @[util.scala:504:26, :520:{31,34}] wire _valids_10_T_5 = io_flush_0 & uops_10_uses_ldq; // @[util.scala:458:7, :505:22, :520:94] wire _valids_10_T_6 = ~_valids_10_T_5; // @[util.scala:520:{83,94}] wire _valids_10_T_7 = _valids_10_T_4 & _valids_10_T_6; // @[util.scala:520:{31,80,83}] wire [11:0] _uops_10_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7] wire [11:0] _uops_10_br_mask_T_1 = uops_10_br_mask & _uops_10_br_mask_T; // @[util.scala:97:{21,23}, :505:22] wire [11:0] _valids_11_T = io_brupdate_b1_mispredict_mask_0 & uops_11_br_mask; // @[util.scala:126:51, :458:7, :505:22] wire _valids_11_T_1 = |_valids_11_T; // @[util.scala:126:{51,59}] wire _valids_11_T_2 = _valids_11_T_1; // @[util.scala:61:61, :126:59] wire _valids_11_T_3 = ~_valids_11_T_2; // @[util.scala:61:61, :520:34] wire _valids_11_T_4 = valids_11 & _valids_11_T_3; // @[util.scala:504:26, :520:{31,34}] wire _valids_11_T_5 = io_flush_0 & uops_11_uses_ldq; // @[util.scala:458:7, :505:22, :520:94] wire _valids_11_T_6 = ~_valids_11_T_5; // @[util.scala:520:{83,94}] wire _valids_11_T_7 = _valids_11_T_4 & _valids_11_T_6; // @[util.scala:520:{31,80,83}] wire [11:0] _uops_11_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7] wire [11:0] _uops_11_br_mask_T_1 = uops_11_br_mask & _uops_11_br_mask_T; // @[util.scala:97:{21,23}, :505:22] wire [11:0] _valids_12_T = io_brupdate_b1_mispredict_mask_0 & uops_12_br_mask; // @[util.scala:126:51, :458:7, :505:22] wire _valids_12_T_1 = |_valids_12_T; // @[util.scala:126:{51,59}] wire _valids_12_T_2 = _valids_12_T_1; // @[util.scala:61:61, :126:59] wire _valids_12_T_3 = ~_valids_12_T_2; // @[util.scala:61:61, :520:34] wire _valids_12_T_4 = valids_12 & _valids_12_T_3; // @[util.scala:504:26, :520:{31,34}] wire _valids_12_T_5 = io_flush_0 & uops_12_uses_ldq; // @[util.scala:458:7, :505:22, :520:94] wire _valids_12_T_6 = ~_valids_12_T_5; // @[util.scala:520:{83,94}] wire _valids_12_T_7 = _valids_12_T_4 & _valids_12_T_6; // @[util.scala:520:{31,80,83}] wire [11:0] _uops_12_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7] wire [11:0] _uops_12_br_mask_T_1 = uops_12_br_mask & _uops_12_br_mask_T; // @[util.scala:97:{21,23}, :505:22] wire [11:0] _valids_13_T = io_brupdate_b1_mispredict_mask_0 & uops_13_br_mask; // @[util.scala:126:51, :458:7, :505:22] wire _valids_13_T_1 = |_valids_13_T; // @[util.scala:126:{51,59}] wire _valids_13_T_2 = _valids_13_T_1; // @[util.scala:61:61, :126:59] wire _valids_13_T_3 = ~_valids_13_T_2; // @[util.scala:61:61, :520:34] wire _valids_13_T_4 = valids_13 & _valids_13_T_3; // @[util.scala:504:26, :520:{31,34}] wire _valids_13_T_5 = io_flush_0 & uops_13_uses_ldq; // @[util.scala:458:7, :505:22, :520:94] wire _valids_13_T_6 = ~_valids_13_T_5; // @[util.scala:520:{83,94}] wire _valids_13_T_7 = _valids_13_T_4 & _valids_13_T_6; // @[util.scala:520:{31,80,83}] wire [11:0] _uops_13_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7] wire [11:0] _uops_13_br_mask_T_1 = uops_13_br_mask & _uops_13_br_mask_T; // @[util.scala:97:{21,23}, :505:22] wire [11:0] _valids_14_T = io_brupdate_b1_mispredict_mask_0 & uops_14_br_mask; // @[util.scala:126:51, :458:7, :505:22] wire _valids_14_T_1 = |_valids_14_T; // @[util.scala:126:{51,59}] wire _valids_14_T_2 = _valids_14_T_1; // @[util.scala:61:61, :126:59] wire _valids_14_T_3 = ~_valids_14_T_2; // @[util.scala:61:61, :520:34] wire _valids_14_T_4 = valids_14 & _valids_14_T_3; // @[util.scala:504:26, :520:{31,34}] wire _valids_14_T_5 = io_flush_0 & uops_14_uses_ldq; // @[util.scala:458:7, :505:22, :520:94] wire _valids_14_T_6 = ~_valids_14_T_5; // @[util.scala:520:{83,94}] wire _valids_14_T_7 = _valids_14_T_4 & _valids_14_T_6; // @[util.scala:520:{31,80,83}] wire [11:0] _uops_14_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7] wire [11:0] _uops_14_br_mask_T_1 = uops_14_br_mask & _uops_14_br_mask_T; // @[util.scala:97:{21,23}, :505:22] wire wrap = enq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [11:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23, :458:7] wire [11:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:93:{25,27}, :458:7] wire [4:0] _GEN_1 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_1 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = deq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:513:26, :543:21] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:458:7, :543:21] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:458:7, :545:19] assign io_deq_bits_data_0 = out_data; // @[util.scala:458:7, :545:19] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:458:7, :545:19] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_way_en_0 = out_way_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:458:7, :545:19] wire [15:0][31:0] _GEN_3 = {{uops_0_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_inst = _GEN_3[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_4 = {{uops_0_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_5 = {{uops_0_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rvc = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][39:0] _GEN_6 = {{uops_0_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_pc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_0_iq_type_0}, {uops_14_iq_type_0}, {uops_13_iq_type_0}, {uops_12_iq_type_0}, {uops_11_iq_type_0}, {uops_10_iq_type_0}, {uops_9_iq_type_0}, {uops_8_iq_type_0}, {uops_7_iq_type_0}, {uops_6_iq_type_0}, {uops_5_iq_type_0}, {uops_4_iq_type_0}, {uops_3_iq_type_0}, {uops_2_iq_type_0}, {uops_1_iq_type_0}, {uops_0_iq_type_0}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_0 = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_8 = {{uops_0_iq_type_1}, {uops_14_iq_type_1}, {uops_13_iq_type_1}, {uops_12_iq_type_1}, {uops_11_iq_type_1}, {uops_10_iq_type_1}, {uops_9_iq_type_1}, {uops_8_iq_type_1}, {uops_7_iq_type_1}, {uops_6_iq_type_1}, {uops_5_iq_type_1}, {uops_4_iq_type_1}, {uops_3_iq_type_1}, {uops_2_iq_type_1}, {uops_1_iq_type_1}, {uops_0_iq_type_1}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_1 = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_9 = {{uops_0_iq_type_2}, {uops_14_iq_type_2}, {uops_13_iq_type_2}, {uops_12_iq_type_2}, {uops_11_iq_type_2}, {uops_10_iq_type_2}, {uops_9_iq_type_2}, {uops_8_iq_type_2}, {uops_7_iq_type_2}, {uops_6_iq_type_2}, {uops_5_iq_type_2}, {uops_4_iq_type_2}, {uops_3_iq_type_2}, {uops_2_iq_type_2}, {uops_1_iq_type_2}, {uops_0_iq_type_2}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_2 = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_10 = {{uops_0_iq_type_3}, {uops_14_iq_type_3}, {uops_13_iq_type_3}, {uops_12_iq_type_3}, {uops_11_iq_type_3}, {uops_10_iq_type_3}, {uops_9_iq_type_3}, {uops_8_iq_type_3}, {uops_7_iq_type_3}, {uops_6_iq_type_3}, {uops_5_iq_type_3}, {uops_4_iq_type_3}, {uops_3_iq_type_3}, {uops_2_iq_type_3}, {uops_1_iq_type_3}, {uops_0_iq_type_3}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_3 = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_11 = {{uops_0_fu_code_0}, {uops_14_fu_code_0}, {uops_13_fu_code_0}, {uops_12_fu_code_0}, {uops_11_fu_code_0}, {uops_10_fu_code_0}, {uops_9_fu_code_0}, {uops_8_fu_code_0}, {uops_7_fu_code_0}, {uops_6_fu_code_0}, {uops_5_fu_code_0}, {uops_4_fu_code_0}, {uops_3_fu_code_0}, {uops_2_fu_code_0}, {uops_1_fu_code_0}, {uops_0_fu_code_0}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_0 = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_12 = {{uops_0_fu_code_1}, {uops_14_fu_code_1}, {uops_13_fu_code_1}, {uops_12_fu_code_1}, {uops_11_fu_code_1}, {uops_10_fu_code_1}, {uops_9_fu_code_1}, {uops_8_fu_code_1}, {uops_7_fu_code_1}, {uops_6_fu_code_1}, {uops_5_fu_code_1}, {uops_4_fu_code_1}, {uops_3_fu_code_1}, {uops_2_fu_code_1}, {uops_1_fu_code_1}, {uops_0_fu_code_1}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_1 = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_13 = {{uops_0_fu_code_2}, {uops_14_fu_code_2}, {uops_13_fu_code_2}, {uops_12_fu_code_2}, {uops_11_fu_code_2}, {uops_10_fu_code_2}, {uops_9_fu_code_2}, {uops_8_fu_code_2}, {uops_7_fu_code_2}, {uops_6_fu_code_2}, {uops_5_fu_code_2}, {uops_4_fu_code_2}, {uops_3_fu_code_2}, {uops_2_fu_code_2}, {uops_1_fu_code_2}, {uops_0_fu_code_2}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_2 = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_14 = {{uops_0_fu_code_3}, {uops_14_fu_code_3}, {uops_13_fu_code_3}, {uops_12_fu_code_3}, {uops_11_fu_code_3}, {uops_10_fu_code_3}, {uops_9_fu_code_3}, {uops_8_fu_code_3}, {uops_7_fu_code_3}, {uops_6_fu_code_3}, {uops_5_fu_code_3}, {uops_4_fu_code_3}, {uops_3_fu_code_3}, {uops_2_fu_code_3}, {uops_1_fu_code_3}, {uops_0_fu_code_3}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_3 = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_15 = {{uops_0_fu_code_4}, {uops_14_fu_code_4}, {uops_13_fu_code_4}, {uops_12_fu_code_4}, {uops_11_fu_code_4}, {uops_10_fu_code_4}, {uops_9_fu_code_4}, {uops_8_fu_code_4}, {uops_7_fu_code_4}, {uops_6_fu_code_4}, {uops_5_fu_code_4}, {uops_4_fu_code_4}, {uops_3_fu_code_4}, {uops_2_fu_code_4}, {uops_1_fu_code_4}, {uops_0_fu_code_4}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_4 = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_0_fu_code_5}, {uops_14_fu_code_5}, {uops_13_fu_code_5}, {uops_12_fu_code_5}, {uops_11_fu_code_5}, {uops_10_fu_code_5}, {uops_9_fu_code_5}, {uops_8_fu_code_5}, {uops_7_fu_code_5}, {uops_6_fu_code_5}, {uops_5_fu_code_5}, {uops_4_fu_code_5}, {uops_3_fu_code_5}, {uops_2_fu_code_5}, {uops_1_fu_code_5}, {uops_0_fu_code_5}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_5 = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_17 = {{uops_0_fu_code_6}, {uops_14_fu_code_6}, {uops_13_fu_code_6}, {uops_12_fu_code_6}, {uops_11_fu_code_6}, {uops_10_fu_code_6}, {uops_9_fu_code_6}, {uops_8_fu_code_6}, {uops_7_fu_code_6}, {uops_6_fu_code_6}, {uops_5_fu_code_6}, {uops_4_fu_code_6}, {uops_3_fu_code_6}, {uops_2_fu_code_6}, {uops_1_fu_code_6}, {uops_0_fu_code_6}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_6 = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_0_fu_code_7}, {uops_14_fu_code_7}, {uops_13_fu_code_7}, {uops_12_fu_code_7}, {uops_11_fu_code_7}, {uops_10_fu_code_7}, {uops_9_fu_code_7}, {uops_8_fu_code_7}, {uops_7_fu_code_7}, {uops_6_fu_code_7}, {uops_5_fu_code_7}, {uops_4_fu_code_7}, {uops_3_fu_code_7}, {uops_2_fu_code_7}, {uops_1_fu_code_7}, {uops_0_fu_code_7}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_7 = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_0_fu_code_8}, {uops_14_fu_code_8}, {uops_13_fu_code_8}, {uops_12_fu_code_8}, {uops_11_fu_code_8}, {uops_10_fu_code_8}, {uops_9_fu_code_8}, {uops_8_fu_code_8}, {uops_7_fu_code_8}, {uops_6_fu_code_8}, {uops_5_fu_code_8}, {uops_4_fu_code_8}, {uops_3_fu_code_8}, {uops_2_fu_code_8}, {uops_1_fu_code_8}, {uops_0_fu_code_8}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_8 = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_0_fu_code_9}, {uops_14_fu_code_9}, {uops_13_fu_code_9}, {uops_12_fu_code_9}, {uops_11_fu_code_9}, {uops_10_fu_code_9}, {uops_9_fu_code_9}, {uops_8_fu_code_9}, {uops_7_fu_code_9}, {uops_6_fu_code_9}, {uops_5_fu_code_9}, {uops_4_fu_code_9}, {uops_3_fu_code_9}, {uops_2_fu_code_9}, {uops_1_fu_code_9}, {uops_0_fu_code_9}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_9 = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_21 = {{uops_0_iw_issued}, {uops_14_iw_issued}, {uops_13_iw_issued}, {uops_12_iw_issued}, {uops_11_iw_issued}, {uops_10_iw_issued}, {uops_9_iw_issued}, {uops_8_iw_issued}, {uops_7_iw_issued}, {uops_6_iw_issued}, {uops_5_iw_issued}, {uops_4_iw_issued}, {uops_3_iw_issued}, {uops_2_iw_issued}, {uops_1_iw_issued}, {uops_0_iw_issued}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_0_iw_issued_partial_agen}, {uops_14_iw_issued_partial_agen}, {uops_13_iw_issued_partial_agen}, {uops_12_iw_issued_partial_agen}, {uops_11_iw_issued_partial_agen}, {uops_10_iw_issued_partial_agen}, {uops_9_iw_issued_partial_agen}, {uops_8_iw_issued_partial_agen}, {uops_7_iw_issued_partial_agen}, {uops_6_iw_issued_partial_agen}, {uops_5_iw_issued_partial_agen}, {uops_4_iw_issued_partial_agen}, {uops_3_iw_issued_partial_agen}, {uops_2_iw_issued_partial_agen}, {uops_1_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_agen = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_0_iw_issued_partial_dgen}, {uops_14_iw_issued_partial_dgen}, {uops_13_iw_issued_partial_dgen}, {uops_12_iw_issued_partial_dgen}, {uops_11_iw_issued_partial_dgen}, {uops_10_iw_issued_partial_dgen}, {uops_9_iw_issued_partial_dgen}, {uops_8_iw_issued_partial_dgen}, {uops_7_iw_issued_partial_dgen}, {uops_6_iw_issued_partial_dgen}, {uops_5_iw_issued_partial_dgen}, {uops_4_iw_issued_partial_dgen}, {uops_3_iw_issued_partial_dgen}, {uops_2_iw_issued_partial_dgen}, {uops_1_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_dgen = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_24 = {{uops_0_iw_p1_speculative_child}, {uops_14_iw_p1_speculative_child}, {uops_13_iw_p1_speculative_child}, {uops_12_iw_p1_speculative_child}, {uops_11_iw_p1_speculative_child}, {uops_10_iw_p1_speculative_child}, {uops_9_iw_p1_speculative_child}, {uops_8_iw_p1_speculative_child}, {uops_7_iw_p1_speculative_child}, {uops_6_iw_p1_speculative_child}, {uops_5_iw_p1_speculative_child}, {uops_4_iw_p1_speculative_child}, {uops_3_iw_p1_speculative_child}, {uops_2_iw_p1_speculative_child}, {uops_1_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_speculative_child = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_25 = {{uops_0_iw_p2_speculative_child}, {uops_14_iw_p2_speculative_child}, {uops_13_iw_p2_speculative_child}, {uops_12_iw_p2_speculative_child}, {uops_11_iw_p2_speculative_child}, {uops_10_iw_p2_speculative_child}, {uops_9_iw_p2_speculative_child}, {uops_8_iw_p2_speculative_child}, {uops_7_iw_p2_speculative_child}, {uops_6_iw_p2_speculative_child}, {uops_5_iw_p2_speculative_child}, {uops_4_iw_p2_speculative_child}, {uops_3_iw_p2_speculative_child}, {uops_2_iw_p2_speculative_child}, {uops_1_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_speculative_child = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_0_iw_p1_bypass_hint}, {uops_14_iw_p1_bypass_hint}, {uops_13_iw_p1_bypass_hint}, {uops_12_iw_p1_bypass_hint}, {uops_11_iw_p1_bypass_hint}, {uops_10_iw_p1_bypass_hint}, {uops_9_iw_p1_bypass_hint}, {uops_8_iw_p1_bypass_hint}, {uops_7_iw_p1_bypass_hint}, {uops_6_iw_p1_bypass_hint}, {uops_5_iw_p1_bypass_hint}, {uops_4_iw_p1_bypass_hint}, {uops_3_iw_p1_bypass_hint}, {uops_2_iw_p1_bypass_hint}, {uops_1_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_bypass_hint = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_0_iw_p2_bypass_hint}, {uops_14_iw_p2_bypass_hint}, {uops_13_iw_p2_bypass_hint}, {uops_12_iw_p2_bypass_hint}, {uops_11_iw_p2_bypass_hint}, {uops_10_iw_p2_bypass_hint}, {uops_9_iw_p2_bypass_hint}, {uops_8_iw_p2_bypass_hint}, {uops_7_iw_p2_bypass_hint}, {uops_6_iw_p2_bypass_hint}, {uops_5_iw_p2_bypass_hint}, {uops_4_iw_p2_bypass_hint}, {uops_3_iw_p2_bypass_hint}, {uops_2_iw_p2_bypass_hint}, {uops_1_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_bypass_hint = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_28 = {{uops_0_iw_p3_bypass_hint}, {uops_14_iw_p3_bypass_hint}, {uops_13_iw_p3_bypass_hint}, {uops_12_iw_p3_bypass_hint}, {uops_11_iw_p3_bypass_hint}, {uops_10_iw_p3_bypass_hint}, {uops_9_iw_p3_bypass_hint}, {uops_8_iw_p3_bypass_hint}, {uops_7_iw_p3_bypass_hint}, {uops_6_iw_p3_bypass_hint}, {uops_5_iw_p3_bypass_hint}, {uops_4_iw_p3_bypass_hint}, {uops_3_iw_p3_bypass_hint}, {uops_2_iw_p3_bypass_hint}, {uops_1_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p3_bypass_hint = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_29 = {{uops_0_dis_col_sel}, {uops_14_dis_col_sel}, {uops_13_dis_col_sel}, {uops_12_dis_col_sel}, {uops_11_dis_col_sel}, {uops_10_dis_col_sel}, {uops_9_dis_col_sel}, {uops_8_dis_col_sel}, {uops_7_dis_col_sel}, {uops_6_dis_col_sel}, {uops_5_dis_col_sel}, {uops_4_dis_col_sel}, {uops_3_dis_col_sel}, {uops_2_dis_col_sel}, {uops_1_dis_col_sel}, {uops_0_dis_col_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_dis_col_sel = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][11:0] _GEN_30 = {{uops_0_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:505:22, :547:21] assign out_uop_br_mask = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_31 = {{uops_0_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:505:22, :547:21] assign out_uop_br_tag = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_32 = {{uops_0_br_type}, {uops_14_br_type}, {uops_13_br_type}, {uops_12_br_type}, {uops_11_br_type}, {uops_10_br_type}, {uops_9_br_type}, {uops_8_br_type}, {uops_7_br_type}, {uops_6_br_type}, {uops_5_br_type}, {uops_4_br_type}, {uops_3_br_type}, {uops_2_br_type}, {uops_1_br_type}, {uops_0_br_type}}; // @[util.scala:505:22, :547:21] assign out_uop_br_type = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_0_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfb = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_34 = {{uops_0_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fence = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_35 = {{uops_0_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fencei = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_36 = {{uops_0_is_sfence}, {uops_14_is_sfence}, {uops_13_is_sfence}, {uops_12_is_sfence}, {uops_11_is_sfence}, {uops_10_is_sfence}, {uops_9_is_sfence}, {uops_8_is_sfence}, {uops_7_is_sfence}, {uops_6_is_sfence}, {uops_5_is_sfence}, {uops_4_is_sfence}, {uops_3_is_sfence}, {uops_2_is_sfence}, {uops_1_is_sfence}, {uops_0_is_sfence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfence = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_37 = {{uops_0_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:505:22, :547:21] assign out_uop_is_amo = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_38 = {{uops_0_is_eret}, {uops_14_is_eret}, {uops_13_is_eret}, {uops_12_is_eret}, {uops_11_is_eret}, {uops_10_is_eret}, {uops_9_is_eret}, {uops_8_is_eret}, {uops_7_is_eret}, {uops_6_is_eret}, {uops_5_is_eret}, {uops_4_is_eret}, {uops_3_is_eret}, {uops_2_is_eret}, {uops_1_is_eret}, {uops_0_is_eret}}; // @[util.scala:505:22, :547:21] assign out_uop_is_eret = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_39 = {{uops_0_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sys_pc2epc = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_40 = {{uops_0_is_rocc}, {uops_14_is_rocc}, {uops_13_is_rocc}, {uops_12_is_rocc}, {uops_11_is_rocc}, {uops_10_is_rocc}, {uops_9_is_rocc}, {uops_8_is_rocc}, {uops_7_is_rocc}, {uops_6_is_rocc}, {uops_5_is_rocc}, {uops_4_is_rocc}, {uops_3_is_rocc}, {uops_2_is_rocc}, {uops_1_is_rocc}, {uops_0_is_rocc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rocc = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_41 = {{uops_0_is_mov}, {uops_14_is_mov}, {uops_13_is_mov}, {uops_12_is_mov}, {uops_11_is_mov}, {uops_10_is_mov}, {uops_9_is_mov}, {uops_8_is_mov}, {uops_7_is_mov}, {uops_6_is_mov}, {uops_5_is_mov}, {uops_4_is_mov}, {uops_3_is_mov}, {uops_2_is_mov}, {uops_1_is_mov}, {uops_0_is_mov}}; // @[util.scala:505:22, :547:21] assign out_uop_is_mov = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_42 = {{uops_0_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ftq_idx = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_43 = {{uops_0_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_edge_inst = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_44 = {{uops_0_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:505:22, :547:21] assign out_uop_pc_lob = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_0_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:505:22, :547:21] assign out_uop_taken = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_0_imm_rename}, {uops_14_imm_rename}, {uops_13_imm_rename}, {uops_12_imm_rename}, {uops_11_imm_rename}, {uops_10_imm_rename}, {uops_9_imm_rename}, {uops_8_imm_rename}, {uops_7_imm_rename}, {uops_6_imm_rename}, {uops_5_imm_rename}, {uops_4_imm_rename}, {uops_3_imm_rename}, {uops_2_imm_rename}, {uops_1_imm_rename}, {uops_0_imm_rename}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_rename = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_47 = {{uops_0_imm_sel}, {uops_14_imm_sel}, {uops_13_imm_sel}, {uops_12_imm_sel}, {uops_11_imm_sel}, {uops_10_imm_sel}, {uops_9_imm_sel}, {uops_8_imm_sel}, {uops_7_imm_sel}, {uops_6_imm_sel}, {uops_5_imm_sel}, {uops_4_imm_sel}, {uops_3_imm_sel}, {uops_2_imm_sel}, {uops_1_imm_sel}, {uops_0_imm_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_sel = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_48 = {{uops_0_pimm}, {uops_14_pimm}, {uops_13_pimm}, {uops_12_pimm}, {uops_11_pimm}, {uops_10_pimm}, {uops_9_pimm}, {uops_8_pimm}, {uops_7_pimm}, {uops_6_pimm}, {uops_5_pimm}, {uops_4_pimm}, {uops_3_pimm}, {uops_2_pimm}, {uops_1_pimm}, {uops_0_pimm}}; // @[util.scala:505:22, :547:21] assign out_uop_pimm = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_49 = {{uops_0_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_packed = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_50 = {{uops_0_op1_sel}, {uops_14_op1_sel}, {uops_13_op1_sel}, {uops_12_op1_sel}, {uops_11_op1_sel}, {uops_10_op1_sel}, {uops_9_op1_sel}, {uops_8_op1_sel}, {uops_7_op1_sel}, {uops_6_op1_sel}, {uops_5_op1_sel}, {uops_4_op1_sel}, {uops_3_op1_sel}, {uops_2_op1_sel}, {uops_1_op1_sel}, {uops_0_op1_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op1_sel = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_51 = {{uops_0_op2_sel}, {uops_14_op2_sel}, {uops_13_op2_sel}, {uops_12_op2_sel}, {uops_11_op2_sel}, {uops_10_op2_sel}, {uops_9_op2_sel}, {uops_8_op2_sel}, {uops_7_op2_sel}, {uops_6_op2_sel}, {uops_5_op2_sel}, {uops_4_op2_sel}, {uops_3_op2_sel}, {uops_2_op2_sel}, {uops_1_op2_sel}, {uops_0_op2_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op2_sel = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_0_fp_ctrl_ldst}, {uops_14_fp_ctrl_ldst}, {uops_13_fp_ctrl_ldst}, {uops_12_fp_ctrl_ldst}, {uops_11_fp_ctrl_ldst}, {uops_10_fp_ctrl_ldst}, {uops_9_fp_ctrl_ldst}, {uops_8_fp_ctrl_ldst}, {uops_7_fp_ctrl_ldst}, {uops_6_fp_ctrl_ldst}, {uops_5_fp_ctrl_ldst}, {uops_4_fp_ctrl_ldst}, {uops_3_fp_ctrl_ldst}, {uops_2_fp_ctrl_ldst}, {uops_1_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ldst = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_53 = {{uops_0_fp_ctrl_wen}, {uops_14_fp_ctrl_wen}, {uops_13_fp_ctrl_wen}, {uops_12_fp_ctrl_wen}, {uops_11_fp_ctrl_wen}, {uops_10_fp_ctrl_wen}, {uops_9_fp_ctrl_wen}, {uops_8_fp_ctrl_wen}, {uops_7_fp_ctrl_wen}, {uops_6_fp_ctrl_wen}, {uops_5_fp_ctrl_wen}, {uops_4_fp_ctrl_wen}, {uops_3_fp_ctrl_wen}, {uops_2_fp_ctrl_wen}, {uops_1_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wen = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_54 = {{uops_0_fp_ctrl_ren1}, {uops_14_fp_ctrl_ren1}, {uops_13_fp_ctrl_ren1}, {uops_12_fp_ctrl_ren1}, {uops_11_fp_ctrl_ren1}, {uops_10_fp_ctrl_ren1}, {uops_9_fp_ctrl_ren1}, {uops_8_fp_ctrl_ren1}, {uops_7_fp_ctrl_ren1}, {uops_6_fp_ctrl_ren1}, {uops_5_fp_ctrl_ren1}, {uops_4_fp_ctrl_ren1}, {uops_3_fp_ctrl_ren1}, {uops_2_fp_ctrl_ren1}, {uops_1_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren1 = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_0_fp_ctrl_ren2}, {uops_14_fp_ctrl_ren2}, {uops_13_fp_ctrl_ren2}, {uops_12_fp_ctrl_ren2}, {uops_11_fp_ctrl_ren2}, {uops_10_fp_ctrl_ren2}, {uops_9_fp_ctrl_ren2}, {uops_8_fp_ctrl_ren2}, {uops_7_fp_ctrl_ren2}, {uops_6_fp_ctrl_ren2}, {uops_5_fp_ctrl_ren2}, {uops_4_fp_ctrl_ren2}, {uops_3_fp_ctrl_ren2}, {uops_2_fp_ctrl_ren2}, {uops_1_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren2 = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_0_fp_ctrl_ren3}, {uops_14_fp_ctrl_ren3}, {uops_13_fp_ctrl_ren3}, {uops_12_fp_ctrl_ren3}, {uops_11_fp_ctrl_ren3}, {uops_10_fp_ctrl_ren3}, {uops_9_fp_ctrl_ren3}, {uops_8_fp_ctrl_ren3}, {uops_7_fp_ctrl_ren3}, {uops_6_fp_ctrl_ren3}, {uops_5_fp_ctrl_ren3}, {uops_4_fp_ctrl_ren3}, {uops_3_fp_ctrl_ren3}, {uops_2_fp_ctrl_ren3}, {uops_1_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren3 = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_0_fp_ctrl_swap12}, {uops_14_fp_ctrl_swap12}, {uops_13_fp_ctrl_swap12}, {uops_12_fp_ctrl_swap12}, {uops_11_fp_ctrl_swap12}, {uops_10_fp_ctrl_swap12}, {uops_9_fp_ctrl_swap12}, {uops_8_fp_ctrl_swap12}, {uops_7_fp_ctrl_swap12}, {uops_6_fp_ctrl_swap12}, {uops_5_fp_ctrl_swap12}, {uops_4_fp_ctrl_swap12}, {uops_3_fp_ctrl_swap12}, {uops_2_fp_ctrl_swap12}, {uops_1_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap12 = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_0_fp_ctrl_swap23}, {uops_14_fp_ctrl_swap23}, {uops_13_fp_ctrl_swap23}, {uops_12_fp_ctrl_swap23}, {uops_11_fp_ctrl_swap23}, {uops_10_fp_ctrl_swap23}, {uops_9_fp_ctrl_swap23}, {uops_8_fp_ctrl_swap23}, {uops_7_fp_ctrl_swap23}, {uops_6_fp_ctrl_swap23}, {uops_5_fp_ctrl_swap23}, {uops_4_fp_ctrl_swap23}, {uops_3_fp_ctrl_swap23}, {uops_2_fp_ctrl_swap23}, {uops_1_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap23 = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_59 = {{uops_0_fp_ctrl_typeTagIn}, {uops_14_fp_ctrl_typeTagIn}, {uops_13_fp_ctrl_typeTagIn}, {uops_12_fp_ctrl_typeTagIn}, {uops_11_fp_ctrl_typeTagIn}, {uops_10_fp_ctrl_typeTagIn}, {uops_9_fp_ctrl_typeTagIn}, {uops_8_fp_ctrl_typeTagIn}, {uops_7_fp_ctrl_typeTagIn}, {uops_6_fp_ctrl_typeTagIn}, {uops_5_fp_ctrl_typeTagIn}, {uops_4_fp_ctrl_typeTagIn}, {uops_3_fp_ctrl_typeTagIn}, {uops_2_fp_ctrl_typeTagIn}, {uops_1_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagIn = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_60 = {{uops_0_fp_ctrl_typeTagOut}, {uops_14_fp_ctrl_typeTagOut}, {uops_13_fp_ctrl_typeTagOut}, {uops_12_fp_ctrl_typeTagOut}, {uops_11_fp_ctrl_typeTagOut}, {uops_10_fp_ctrl_typeTagOut}, {uops_9_fp_ctrl_typeTagOut}, {uops_8_fp_ctrl_typeTagOut}, {uops_7_fp_ctrl_typeTagOut}, {uops_6_fp_ctrl_typeTagOut}, {uops_5_fp_ctrl_typeTagOut}, {uops_4_fp_ctrl_typeTagOut}, {uops_3_fp_ctrl_typeTagOut}, {uops_2_fp_ctrl_typeTagOut}, {uops_1_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagOut = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_0_fp_ctrl_fromint}, {uops_14_fp_ctrl_fromint}, {uops_13_fp_ctrl_fromint}, {uops_12_fp_ctrl_fromint}, {uops_11_fp_ctrl_fromint}, {uops_10_fp_ctrl_fromint}, {uops_9_fp_ctrl_fromint}, {uops_8_fp_ctrl_fromint}, {uops_7_fp_ctrl_fromint}, {uops_6_fp_ctrl_fromint}, {uops_5_fp_ctrl_fromint}, {uops_4_fp_ctrl_fromint}, {uops_3_fp_ctrl_fromint}, {uops_2_fp_ctrl_fromint}, {uops_1_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fromint = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_0_fp_ctrl_toint}, {uops_14_fp_ctrl_toint}, {uops_13_fp_ctrl_toint}, {uops_12_fp_ctrl_toint}, {uops_11_fp_ctrl_toint}, {uops_10_fp_ctrl_toint}, {uops_9_fp_ctrl_toint}, {uops_8_fp_ctrl_toint}, {uops_7_fp_ctrl_toint}, {uops_6_fp_ctrl_toint}, {uops_5_fp_ctrl_toint}, {uops_4_fp_ctrl_toint}, {uops_3_fp_ctrl_toint}, {uops_2_fp_ctrl_toint}, {uops_1_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_toint = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_0_fp_ctrl_fastpipe}, {uops_14_fp_ctrl_fastpipe}, {uops_13_fp_ctrl_fastpipe}, {uops_12_fp_ctrl_fastpipe}, {uops_11_fp_ctrl_fastpipe}, {uops_10_fp_ctrl_fastpipe}, {uops_9_fp_ctrl_fastpipe}, {uops_8_fp_ctrl_fastpipe}, {uops_7_fp_ctrl_fastpipe}, {uops_6_fp_ctrl_fastpipe}, {uops_5_fp_ctrl_fastpipe}, {uops_4_fp_ctrl_fastpipe}, {uops_3_fp_ctrl_fastpipe}, {uops_2_fp_ctrl_fastpipe}, {uops_1_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fastpipe = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_0_fp_ctrl_fma}, {uops_14_fp_ctrl_fma}, {uops_13_fp_ctrl_fma}, {uops_12_fp_ctrl_fma}, {uops_11_fp_ctrl_fma}, {uops_10_fp_ctrl_fma}, {uops_9_fp_ctrl_fma}, {uops_8_fp_ctrl_fma}, {uops_7_fp_ctrl_fma}, {uops_6_fp_ctrl_fma}, {uops_5_fp_ctrl_fma}, {uops_4_fp_ctrl_fma}, {uops_3_fp_ctrl_fma}, {uops_2_fp_ctrl_fma}, {uops_1_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fma = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_65 = {{uops_0_fp_ctrl_div}, {uops_14_fp_ctrl_div}, {uops_13_fp_ctrl_div}, {uops_12_fp_ctrl_div}, {uops_11_fp_ctrl_div}, {uops_10_fp_ctrl_div}, {uops_9_fp_ctrl_div}, {uops_8_fp_ctrl_div}, {uops_7_fp_ctrl_div}, {uops_6_fp_ctrl_div}, {uops_5_fp_ctrl_div}, {uops_4_fp_ctrl_div}, {uops_3_fp_ctrl_div}, {uops_2_fp_ctrl_div}, {uops_1_fp_ctrl_div}, {uops_0_fp_ctrl_div}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_div = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_66 = {{uops_0_fp_ctrl_sqrt}, {uops_14_fp_ctrl_sqrt}, {uops_13_fp_ctrl_sqrt}, {uops_12_fp_ctrl_sqrt}, {uops_11_fp_ctrl_sqrt}, {uops_10_fp_ctrl_sqrt}, {uops_9_fp_ctrl_sqrt}, {uops_8_fp_ctrl_sqrt}, {uops_7_fp_ctrl_sqrt}, {uops_6_fp_ctrl_sqrt}, {uops_5_fp_ctrl_sqrt}, {uops_4_fp_ctrl_sqrt}, {uops_3_fp_ctrl_sqrt}, {uops_2_fp_ctrl_sqrt}, {uops_1_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_sqrt = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_67 = {{uops_0_fp_ctrl_wflags}, {uops_14_fp_ctrl_wflags}, {uops_13_fp_ctrl_wflags}, {uops_12_fp_ctrl_wflags}, {uops_11_fp_ctrl_wflags}, {uops_10_fp_ctrl_wflags}, {uops_9_fp_ctrl_wflags}, {uops_8_fp_ctrl_wflags}, {uops_7_fp_ctrl_wflags}, {uops_6_fp_ctrl_wflags}, {uops_5_fp_ctrl_wflags}, {uops_4_fp_ctrl_wflags}, {uops_3_fp_ctrl_wflags}, {uops_2_fp_ctrl_wflags}, {uops_1_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wflags = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_68 = {{uops_0_fp_ctrl_vec}, {uops_14_fp_ctrl_vec}, {uops_13_fp_ctrl_vec}, {uops_12_fp_ctrl_vec}, {uops_11_fp_ctrl_vec}, {uops_10_fp_ctrl_vec}, {uops_9_fp_ctrl_vec}, {uops_8_fp_ctrl_vec}, {uops_7_fp_ctrl_vec}, {uops_6_fp_ctrl_vec}, {uops_5_fp_ctrl_vec}, {uops_4_fp_ctrl_vec}, {uops_3_fp_ctrl_vec}, {uops_2_fp_ctrl_vec}, {uops_1_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_vec = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_69 = {{uops_0_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rob_idx = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_70 = {{uops_0_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ldq_idx = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_71 = {{uops_0_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_stq_idx = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_0_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rxq_idx = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_73 = {{uops_0_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_pdst = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_74 = {{uops_0_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1 = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_75 = {{uops_0_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2 = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_76 = {{uops_0_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3 = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_77 = {{uops_0_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_0_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1_busy = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_0_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2_busy = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_0_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3_busy = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_81 = {{uops_0_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred_busy = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_82 = {{uops_0_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_stale_pdst = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_83 = {{uops_0_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:505:22, :547:21] assign out_uop_exception = _GEN_83[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_84 = {{uops_0_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:505:22, :547:21] assign out_uop_exc_cause = _GEN_84[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_85 = {{uops_0_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_cmd = _GEN_85[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_86 = {{uops_0_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_size = _GEN_86[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_87 = {{uops_0_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_signed = _GEN_87[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_88 = {{uops_0_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_ldq = _GEN_88[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_89 = {{uops_0_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_stq = _GEN_89[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_90 = {{uops_0_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:505:22, :547:21] assign out_uop_is_unique = _GEN_90[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_91 = {{uops_0_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:505:22, :547:21] assign out_uop_flush_on_commit = _GEN_91[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_92 = {{uops_0_csr_cmd}, {uops_14_csr_cmd}, {uops_13_csr_cmd}, {uops_12_csr_cmd}, {uops_11_csr_cmd}, {uops_10_csr_cmd}, {uops_9_csr_cmd}, {uops_8_csr_cmd}, {uops_7_csr_cmd}, {uops_6_csr_cmd}, {uops_5_csr_cmd}, {uops_4_csr_cmd}, {uops_3_csr_cmd}, {uops_2_csr_cmd}, {uops_1_csr_cmd}, {uops_0_csr_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_csr_cmd = _GEN_92[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_93 = {{uops_0_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst_is_rs1 = _GEN_93[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_94 = {{uops_0_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst = _GEN_94[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_95 = {{uops_0_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1 = _GEN_95[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_96 = {{uops_0_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2 = _GEN_96[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_97 = {{uops_0_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs3 = _GEN_97[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_98 = {{uops_0_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_dst_rtype = _GEN_98[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_99 = {{uops_0_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1_rtype = _GEN_99[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_100 = {{uops_0_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2_rtype = _GEN_100[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_101 = {{uops_0_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:505:22, :547:21] assign out_uop_frs3_en = _GEN_101[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_102 = {{uops_0_fcn_dw}, {uops_14_fcn_dw}, {uops_13_fcn_dw}, {uops_12_fcn_dw}, {uops_11_fcn_dw}, {uops_10_fcn_dw}, {uops_9_fcn_dw}, {uops_8_fcn_dw}, {uops_7_fcn_dw}, {uops_6_fcn_dw}, {uops_5_fcn_dw}, {uops_4_fcn_dw}, {uops_3_fcn_dw}, {uops_2_fcn_dw}, {uops_1_fcn_dw}, {uops_0_fcn_dw}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_dw = _GEN_102[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_103 = {{uops_0_fcn_op}, {uops_14_fcn_op}, {uops_13_fcn_op}, {uops_12_fcn_op}, {uops_11_fcn_op}, {uops_10_fcn_op}, {uops_9_fcn_op}, {uops_8_fcn_op}, {uops_7_fcn_op}, {uops_6_fcn_op}, {uops_5_fcn_op}, {uops_4_fcn_op}, {uops_3_fcn_op}, {uops_2_fcn_op}, {uops_1_fcn_op}, {uops_0_fcn_op}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_op = _GEN_103[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_104 = {{uops_0_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_val = _GEN_104[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_105 = {{uops_0_fp_rm}, {uops_14_fp_rm}, {uops_13_fp_rm}, {uops_12_fp_rm}, {uops_11_fp_rm}, {uops_10_fp_rm}, {uops_9_fp_rm}, {uops_8_fp_rm}, {uops_7_fp_rm}, {uops_6_fp_rm}, {uops_5_fp_rm}, {uops_4_fp_rm}, {uops_3_fp_rm}, {uops_2_fp_rm}, {uops_1_fp_rm}, {uops_0_fp_rm}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_rm = _GEN_105[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_106 = {{uops_0_fp_typ}, {uops_14_fp_typ}, {uops_13_fp_typ}, {uops_12_fp_typ}, {uops_11_fp_typ}, {uops_10_fp_typ}, {uops_9_fp_typ}, {uops_8_fp_typ}, {uops_7_fp_typ}, {uops_6_fp_typ}, {uops_5_fp_typ}, {uops_4_fp_typ}, {uops_3_fp_typ}, {uops_2_fp_typ}, {uops_1_fp_typ}, {uops_0_fp_typ}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_typ = _GEN_106[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_107 = {{uops_0_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_pf_if = _GEN_107[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_108 = {{uops_0_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ae_if = _GEN_108[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_109 = {{uops_0_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ma_if = _GEN_109[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_110 = {{uops_0_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_debug_if = _GEN_110[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_111 = {{uops_0_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_xcpt_if = _GEN_111[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_112 = {{uops_0_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_fsrc = _GEN_112[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_113 = {{uops_0_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_tsrc = _GEN_113[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:458:7, :515:71, :548:32] assign _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_0; // @[util.scala:515:44, :548:{32,42}] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[util.scala:458:7, :548:42] wire [4:0] _ptr_diff_T = _GEN_1 - _GEN_2; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:551:34] wire [3:0] _io_count_T = {4{maybe_full}}; // @[util.scala:509:29, :557:12] wire _io_count_T_1 = deq_ptr_value > enq_ptr_value; // @[Counter.scala:61:40] wire [4:0] _io_count_T_2 = {1'h0, ptr_diff} + 5'hF; // @[util.scala:551:34, :560:26] wire [3:0] _io_count_T_3 = _io_count_T_2[3:0]; // @[util.scala:560:26] wire [3:0] _io_count_T_4 = _io_count_T_1 ? _io_count_T_3 : ptr_diff; // @[util.scala:551:34, :559:{12,27}, :560:26] assign _io_count_T_5 = ptr_match ? _io_count_T : _io_count_T_4; // @[util.scala:511:35, :556:22, :557:12, :559:12] assign io_count_0 = _io_count_T_5; // @[util.scala:458:7, :556:22] wire _GEN_114 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_115 = do_enq & _GEN_114; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_116 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_117 = do_enq & _GEN_116; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_118 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_119 = do_enq & _GEN_118; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_120 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_121 = do_enq & _GEN_120; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_122 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_123 = do_enq & _GEN_122; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_124 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_125 = do_enq & _GEN_124; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_126 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_127 = do_enq & _GEN_126; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_128 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_129 = do_enq & _GEN_128; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_130 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_131 = do_enq & _GEN_130; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_132 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_133 = do_enq & _GEN_132; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_134 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_135 = do_enq & _GEN_134; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_136 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_137 = do_enq & _GEN_136; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_138 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_139 = do_enq & _GEN_138; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_140 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_141 = do_enq & _GEN_140; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_142 = do_enq & wrap; // @[Counter.scala:73:24] always @(posedge clock) begin // @[util.scala:458:7] if (reset) begin // @[util.scala:458:7] valids_0 <= 1'h0; // @[util.scala:504:26] valids_1 <= 1'h0; // @[util.scala:504:26] valids_2 <= 1'h0; // @[util.scala:504:26] valids_3 <= 1'h0; // @[util.scala:504:26] valids_4 <= 1'h0; // @[util.scala:504:26] valids_5 <= 1'h0; // @[util.scala:504:26] valids_6 <= 1'h0; // @[util.scala:504:26] valids_7 <= 1'h0; // @[util.scala:504:26] valids_8 <= 1'h0; // @[util.scala:504:26] valids_9 <= 1'h0; // @[util.scala:504:26] valids_10 <= 1'h0; // @[util.scala:504:26] valids_11 <= 1'h0; // @[util.scala:504:26] valids_12 <= 1'h0; // @[util.scala:504:26] valids_13 <= 1'h0; // @[util.scala:504:26] valids_14 <= 1'h0; // @[util.scala:504:26] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:509:29] end else begin // @[util.scala:458:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_115 | _valids_0_T_7); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_117 | _valids_1_T_7); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_119 | _valids_2_T_7); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_121 | _valids_3_T_7); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_123 | _valids_4_T_7); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_125 | _valids_5_T_7); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_127 | _valids_6_T_7); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_129 | _valids_7_T_7); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_131 | _valids_8_T_7); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_133 | _valids_9_T_7); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_135 | _valids_10_T_7); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_137 | _valids_11_T_7); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_139 | _valids_12_T_7); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_141 | _valids_13_T_7); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & wrap_1) & (_GEN_142 | _valids_14_T_7); // @[Counter.scala:73:24] if (do_enq) // @[util.scala:514:26] enq_ptr_value <= wrap ? 4'h0 : _value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (do_deq) // @[util.scala:515:26] deq_ptr_value <= wrap_1 ? 4'h0 : _value_T_3; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (~(do_enq == do_deq)) // @[util.scala:509:29, :514:26, :515:26, :539:{18,30}, :540:18] maybe_full <= do_enq; // @[util.scala:509:29, :514:26] end if (_GEN_115) begin // @[util.scala:520:18, :526:19, :528:35] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_0_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_0_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_0_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_0_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_0_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_0_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_0_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_0_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_0_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_0_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_0_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_0_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_0_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_0_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_0_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_114) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_0) // @[util.scala:504:26] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_117) begin // @[util.scala:520:18, :526:19, :528:35] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_1_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_1_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_1_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_1_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_1_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_1_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_1_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_1_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_1_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_1_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_1_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_1_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_1_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_1_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_1_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_116) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_1) // @[util.scala:504:26] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_119) begin // @[util.scala:520:18, :526:19, :528:35] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_2_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_2_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_2_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_2_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_2_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_2_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_2_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_2_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_2_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_2_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_2_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_2_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_2_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_2_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_2_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_118) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_2) // @[util.scala:504:26] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_121) begin // @[util.scala:520:18, :526:19, :528:35] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_3_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_3_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_3_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_3_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_3_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_3_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_3_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_3_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_3_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_3_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_3_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_3_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_3_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_3_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_3_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_120) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_3) // @[util.scala:504:26] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_123) begin // @[util.scala:520:18, :526:19, :528:35] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_4_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_4_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_4_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_4_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_4_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_4_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_4_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_4_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_4_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_4_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_4_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_4_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_4_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_4_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_4_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_122) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_4) // @[util.scala:504:26] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_125) begin // @[util.scala:520:18, :526:19, :528:35] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_5_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_5_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_5_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_5_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_5_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_5_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_5_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_5_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_5_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_5_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_5_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_5_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_5_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_5_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_5_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_124) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_5) // @[util.scala:504:26] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_127) begin // @[util.scala:520:18, :526:19, :528:35] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_6_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_6_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_6_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_6_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_6_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_6_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_6_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_6_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_6_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_6_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_6_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_6_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_6_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_6_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_6_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_126) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_6) // @[util.scala:504:26] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_129) begin // @[util.scala:520:18, :526:19, :528:35] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_7_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_7_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_7_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_7_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_7_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_7_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_7_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_7_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_7_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_7_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_7_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_7_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_7_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_7_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_7_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_128) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_7) // @[util.scala:504:26] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_131) begin // @[util.scala:520:18, :526:19, :528:35] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_8_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_8_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_8_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_8_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_8_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_8_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_8_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_8_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_8_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_8_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_8_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_8_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_8_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_8_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_8_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_130) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_8) // @[util.scala:504:26] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_133) begin // @[util.scala:520:18, :526:19, :528:35] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_9_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_9_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_9_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_9_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_9_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_9_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_9_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_9_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_9_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_9_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_9_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_9_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_9_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_9_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_9_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_132) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_9) // @[util.scala:504:26] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_135) begin // @[util.scala:520:18, :526:19, :528:35] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_10_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_10_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_10_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_10_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_10_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_10_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_10_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_10_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_10_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_10_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_10_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_10_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_10_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_10_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_10_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_134) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_10) // @[util.scala:504:26] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_137) begin // @[util.scala:520:18, :526:19, :528:35] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_11_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_11_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_11_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_11_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_11_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_11_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_11_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_11_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_11_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_11_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_11_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_11_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_11_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_11_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_11_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_136) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_11) // @[util.scala:504:26] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_139) begin // @[util.scala:520:18, :526:19, :528:35] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_12_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_12_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_12_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_12_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_12_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_12_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_12_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_12_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_12_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_12_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_12_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_12_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_12_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_12_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_12_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_138) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_12) // @[util.scala:504:26] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_141) begin // @[util.scala:520:18, :526:19, :528:35] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_13_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_13_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_13_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_13_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_13_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_13_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_13_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_13_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_13_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_13_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_13_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_13_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_13_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_13_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_13_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_140) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_13) // @[util.scala:504:26] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_142) begin // @[util.scala:520:18, :526:19, :528:35] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_14_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_14_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_14_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_14_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_14_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_14_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_14_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_14_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_14_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_14_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_14_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_14_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_14_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_14_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_14_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & wrap) // @[Counter.scala:73:24] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_14) // @[util.scala:504:26] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:97:21, :505:22] always @(posedge) ram_15x137 ram_ext ( // @[util.scala:503:22] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:514:26] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:458:7, :503:22] ); // @[util.scala:503:22] assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7] assign io_empty = io_empty_0; // @[util.scala:458:7] assign io_count = io_count_0; // @[util.scala:458:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BTBBranchPredictorBank_3 : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}} connect io.resp, io.resp_in[0] connect io.f3_meta, UInt<1>(0h0) node s0_idx = shr(io.f0_pc, 4) reg s1_idx : UInt, clock connect s1_idx, s0_idx reg s2_idx : UInt, clock connect s2_idx, s1_idx reg s3_idx : UInt, clock connect s3_idx, s2_idx reg s1_valid : UInt<1>, clock connect s1_valid, io.f0_valid reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid reg s3_valid : UInt<1>, clock connect s3_valid, s2_valid reg s1_mask : UInt, clock connect s1_mask, io.f0_mask reg s2_mask : UInt, clock connect s2_mask, s1_mask reg s3_mask : UInt, clock connect s3_mask, s2_mask reg s1_pc : UInt, clock connect s1_pc, io.f0_pc node s0_update_idx = shr(io.update.bits.pc, 4) reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock connect s1_update.bits.meta, io.update.bits.meta connect s1_update.bits.target, io.update.bits.target connect s1_update.bits.lhist, io.update.bits.lhist connect s1_update.bits.ghist, io.update.bits.ghist connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect s1_update.bits.br_mask, io.update.bits.br_mask connect s1_update.bits.pc, io.update.bits.pc connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect s1_update.valid, io.update.valid reg s1_update_idx : UInt, clock connect s1_update_idx, s0_update_idx reg s1_update_valid : UInt<1>, clock connect s1_update_valid, io.update.valid wire s1_meta : { write_way : UInt<1>} reg f3_meta_REG : { write_way : UInt<1>}, clock connect f3_meta_REG, s1_meta reg f3_meta : { write_way : UInt<1>}, clock connect f3_meta, f3_meta_REG connect io.f3_meta, f3_meta.write_way regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<7>, clock, reset, UInt<7>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<7>(0h7f)) when _T : connect doing_reset, UInt<1>(0h0) smem meta_0 : UInt<30>[4] [128] smem meta_1 : UInt<30>[4] [128] smem btb_0 : UInt<14>[4] [128] smem btb_1 : UInt<14>[4] [128] smem ebtb : UInt<40> [128] wire _s1_req_rbtb_WIRE : UInt<36> invalidate _s1_req_rbtb_WIRE when io.f0_valid : connect _s1_req_rbtb_WIRE, s0_idx node _s1_req_rbtb_T = bits(_s1_req_rbtb_WIRE, 6, 0) read mport s1_req_rbtb_MPORT = btb_0[_s1_req_rbtb_T], clock wire _s1_req_rbtb_WIRE_1 : { offset : SInt<13>, extended : UInt<1>} wire _s1_req_rbtb_WIRE_2 : UInt<14> connect _s1_req_rbtb_WIRE_2, s1_req_rbtb_MPORT[0] node _s1_req_rbtb_T_1 = bits(_s1_req_rbtb_WIRE_2, 0, 0) connect _s1_req_rbtb_WIRE_1.extended, _s1_req_rbtb_T_1 node _s1_req_rbtb_T_2 = bits(_s1_req_rbtb_WIRE_2, 13, 1) node _s1_req_rbtb_T_3 = asSInt(_s1_req_rbtb_T_2) connect _s1_req_rbtb_WIRE_1.offset, _s1_req_rbtb_T_3 wire _s1_req_rbtb_WIRE_3 : { offset : SInt<13>, extended : UInt<1>} wire _s1_req_rbtb_WIRE_4 : UInt<14> connect _s1_req_rbtb_WIRE_4, s1_req_rbtb_MPORT[1] node _s1_req_rbtb_T_4 = bits(_s1_req_rbtb_WIRE_4, 0, 0) connect _s1_req_rbtb_WIRE_3.extended, _s1_req_rbtb_T_4 node _s1_req_rbtb_T_5 = bits(_s1_req_rbtb_WIRE_4, 13, 1) node _s1_req_rbtb_T_6 = asSInt(_s1_req_rbtb_T_5) connect _s1_req_rbtb_WIRE_3.offset, _s1_req_rbtb_T_6 wire _s1_req_rbtb_WIRE_5 : { offset : SInt<13>, extended : UInt<1>} wire _s1_req_rbtb_WIRE_6 : UInt<14> connect _s1_req_rbtb_WIRE_6, s1_req_rbtb_MPORT[2] node _s1_req_rbtb_T_7 = bits(_s1_req_rbtb_WIRE_6, 0, 0) connect _s1_req_rbtb_WIRE_5.extended, _s1_req_rbtb_T_7 node _s1_req_rbtb_T_8 = bits(_s1_req_rbtb_WIRE_6, 13, 1) node _s1_req_rbtb_T_9 = asSInt(_s1_req_rbtb_T_8) connect _s1_req_rbtb_WIRE_5.offset, _s1_req_rbtb_T_9 wire _s1_req_rbtb_WIRE_7 : { offset : SInt<13>, extended : UInt<1>} wire _s1_req_rbtb_WIRE_8 : UInt<14> connect _s1_req_rbtb_WIRE_8, s1_req_rbtb_MPORT[3] node _s1_req_rbtb_T_10 = bits(_s1_req_rbtb_WIRE_8, 0, 0) connect _s1_req_rbtb_WIRE_7.extended, _s1_req_rbtb_T_10 node _s1_req_rbtb_T_11 = bits(_s1_req_rbtb_WIRE_8, 13, 1) node _s1_req_rbtb_T_12 = asSInt(_s1_req_rbtb_T_11) connect _s1_req_rbtb_WIRE_7.offset, _s1_req_rbtb_T_12 wire _s1_req_rbtb_WIRE_9 : { offset : SInt<13>, extended : UInt<1>}[4] connect _s1_req_rbtb_WIRE_9[0].extended, _s1_req_rbtb_WIRE_1.extended connect _s1_req_rbtb_WIRE_9[0].offset, _s1_req_rbtb_WIRE_1.offset connect _s1_req_rbtb_WIRE_9[1].extended, _s1_req_rbtb_WIRE_3.extended connect _s1_req_rbtb_WIRE_9[1].offset, _s1_req_rbtb_WIRE_3.offset connect _s1_req_rbtb_WIRE_9[2].extended, _s1_req_rbtb_WIRE_5.extended connect _s1_req_rbtb_WIRE_9[2].offset, _s1_req_rbtb_WIRE_5.offset connect _s1_req_rbtb_WIRE_9[3].extended, _s1_req_rbtb_WIRE_7.extended connect _s1_req_rbtb_WIRE_9[3].offset, _s1_req_rbtb_WIRE_7.offset wire _s1_req_rbtb_WIRE_10 : UInt<36> invalidate _s1_req_rbtb_WIRE_10 when io.f0_valid : connect _s1_req_rbtb_WIRE_10, s0_idx node _s1_req_rbtb_T_13 = bits(_s1_req_rbtb_WIRE_10, 6, 0) read mport s1_req_rbtb_MPORT_1 = btb_1[_s1_req_rbtb_T_13], clock wire _s1_req_rbtb_WIRE_11 : { offset : SInt<13>, extended : UInt<1>} wire _s1_req_rbtb_WIRE_12 : UInt<14> connect _s1_req_rbtb_WIRE_12, s1_req_rbtb_MPORT_1[0] node _s1_req_rbtb_T_14 = bits(_s1_req_rbtb_WIRE_12, 0, 0) connect _s1_req_rbtb_WIRE_11.extended, _s1_req_rbtb_T_14 node _s1_req_rbtb_T_15 = bits(_s1_req_rbtb_WIRE_12, 13, 1) node _s1_req_rbtb_T_16 = asSInt(_s1_req_rbtb_T_15) connect _s1_req_rbtb_WIRE_11.offset, _s1_req_rbtb_T_16 wire _s1_req_rbtb_WIRE_13 : { offset : SInt<13>, extended : UInt<1>} wire _s1_req_rbtb_WIRE_14 : UInt<14> connect _s1_req_rbtb_WIRE_14, s1_req_rbtb_MPORT_1[1] node _s1_req_rbtb_T_17 = bits(_s1_req_rbtb_WIRE_14, 0, 0) connect _s1_req_rbtb_WIRE_13.extended, _s1_req_rbtb_T_17 node _s1_req_rbtb_T_18 = bits(_s1_req_rbtb_WIRE_14, 13, 1) node _s1_req_rbtb_T_19 = asSInt(_s1_req_rbtb_T_18) connect _s1_req_rbtb_WIRE_13.offset, _s1_req_rbtb_T_19 wire _s1_req_rbtb_WIRE_15 : { offset : SInt<13>, extended : UInt<1>} wire _s1_req_rbtb_WIRE_16 : UInt<14> connect _s1_req_rbtb_WIRE_16, s1_req_rbtb_MPORT_1[2] node _s1_req_rbtb_T_20 = bits(_s1_req_rbtb_WIRE_16, 0, 0) connect _s1_req_rbtb_WIRE_15.extended, _s1_req_rbtb_T_20 node _s1_req_rbtb_T_21 = bits(_s1_req_rbtb_WIRE_16, 13, 1) node _s1_req_rbtb_T_22 = asSInt(_s1_req_rbtb_T_21) connect _s1_req_rbtb_WIRE_15.offset, _s1_req_rbtb_T_22 wire _s1_req_rbtb_WIRE_17 : { offset : SInt<13>, extended : UInt<1>} wire _s1_req_rbtb_WIRE_18 : UInt<14> connect _s1_req_rbtb_WIRE_18, s1_req_rbtb_MPORT_1[3] node _s1_req_rbtb_T_23 = bits(_s1_req_rbtb_WIRE_18, 0, 0) connect _s1_req_rbtb_WIRE_17.extended, _s1_req_rbtb_T_23 node _s1_req_rbtb_T_24 = bits(_s1_req_rbtb_WIRE_18, 13, 1) node _s1_req_rbtb_T_25 = asSInt(_s1_req_rbtb_T_24) connect _s1_req_rbtb_WIRE_17.offset, _s1_req_rbtb_T_25 wire _s1_req_rbtb_WIRE_19 : { offset : SInt<13>, extended : UInt<1>}[4] connect _s1_req_rbtb_WIRE_19[0].extended, _s1_req_rbtb_WIRE_11.extended connect _s1_req_rbtb_WIRE_19[0].offset, _s1_req_rbtb_WIRE_11.offset connect _s1_req_rbtb_WIRE_19[1].extended, _s1_req_rbtb_WIRE_13.extended connect _s1_req_rbtb_WIRE_19[1].offset, _s1_req_rbtb_WIRE_13.offset connect _s1_req_rbtb_WIRE_19[2].extended, _s1_req_rbtb_WIRE_15.extended connect _s1_req_rbtb_WIRE_19[2].offset, _s1_req_rbtb_WIRE_15.offset connect _s1_req_rbtb_WIRE_19[3].extended, _s1_req_rbtb_WIRE_17.extended connect _s1_req_rbtb_WIRE_19[3].offset, _s1_req_rbtb_WIRE_17.offset wire s1_req_rbtb : { offset : SInt<13>, extended : UInt<1>}[4][2] connect s1_req_rbtb[0], _s1_req_rbtb_WIRE_9 connect s1_req_rbtb[1], _s1_req_rbtb_WIRE_19 wire _s1_req_rmeta_WIRE : UInt<36> invalidate _s1_req_rmeta_WIRE when io.f0_valid : connect _s1_req_rmeta_WIRE, s0_idx node _s1_req_rmeta_T = bits(_s1_req_rmeta_WIRE, 6, 0) read mport s1_req_rmeta_MPORT = meta_0[_s1_req_rmeta_T], clock wire _s1_req_rmeta_WIRE_1 : { is_br : UInt<1>, tag : UInt<29>} wire _s1_req_rmeta_WIRE_2 : UInt<30> connect _s1_req_rmeta_WIRE_2, s1_req_rmeta_MPORT[0] node _s1_req_rmeta_T_1 = bits(_s1_req_rmeta_WIRE_2, 28, 0) connect _s1_req_rmeta_WIRE_1.tag, _s1_req_rmeta_T_1 node _s1_req_rmeta_T_2 = bits(_s1_req_rmeta_WIRE_2, 29, 29) connect _s1_req_rmeta_WIRE_1.is_br, _s1_req_rmeta_T_2 wire _s1_req_rmeta_WIRE_3 : { is_br : UInt<1>, tag : UInt<29>} wire _s1_req_rmeta_WIRE_4 : UInt<30> connect _s1_req_rmeta_WIRE_4, s1_req_rmeta_MPORT[1] node _s1_req_rmeta_T_3 = bits(_s1_req_rmeta_WIRE_4, 28, 0) connect _s1_req_rmeta_WIRE_3.tag, _s1_req_rmeta_T_3 node _s1_req_rmeta_T_4 = bits(_s1_req_rmeta_WIRE_4, 29, 29) connect _s1_req_rmeta_WIRE_3.is_br, _s1_req_rmeta_T_4 wire _s1_req_rmeta_WIRE_5 : { is_br : UInt<1>, tag : UInt<29>} wire _s1_req_rmeta_WIRE_6 : UInt<30> connect _s1_req_rmeta_WIRE_6, s1_req_rmeta_MPORT[2] node _s1_req_rmeta_T_5 = bits(_s1_req_rmeta_WIRE_6, 28, 0) connect _s1_req_rmeta_WIRE_5.tag, _s1_req_rmeta_T_5 node _s1_req_rmeta_T_6 = bits(_s1_req_rmeta_WIRE_6, 29, 29) connect _s1_req_rmeta_WIRE_5.is_br, _s1_req_rmeta_T_6 wire _s1_req_rmeta_WIRE_7 : { is_br : UInt<1>, tag : UInt<29>} wire _s1_req_rmeta_WIRE_8 : UInt<30> connect _s1_req_rmeta_WIRE_8, s1_req_rmeta_MPORT[3] node _s1_req_rmeta_T_7 = bits(_s1_req_rmeta_WIRE_8, 28, 0) connect _s1_req_rmeta_WIRE_7.tag, _s1_req_rmeta_T_7 node _s1_req_rmeta_T_8 = bits(_s1_req_rmeta_WIRE_8, 29, 29) connect _s1_req_rmeta_WIRE_7.is_br, _s1_req_rmeta_T_8 wire _s1_req_rmeta_WIRE_9 : { is_br : UInt<1>, tag : UInt<29>}[4] connect _s1_req_rmeta_WIRE_9[0].tag, _s1_req_rmeta_WIRE_1.tag connect _s1_req_rmeta_WIRE_9[0].is_br, _s1_req_rmeta_WIRE_1.is_br connect _s1_req_rmeta_WIRE_9[1].tag, _s1_req_rmeta_WIRE_3.tag connect _s1_req_rmeta_WIRE_9[1].is_br, _s1_req_rmeta_WIRE_3.is_br connect _s1_req_rmeta_WIRE_9[2].tag, _s1_req_rmeta_WIRE_5.tag connect _s1_req_rmeta_WIRE_9[2].is_br, _s1_req_rmeta_WIRE_5.is_br connect _s1_req_rmeta_WIRE_9[3].tag, _s1_req_rmeta_WIRE_7.tag connect _s1_req_rmeta_WIRE_9[3].is_br, _s1_req_rmeta_WIRE_7.is_br wire _s1_req_rmeta_WIRE_10 : UInt<36> invalidate _s1_req_rmeta_WIRE_10 when io.f0_valid : connect _s1_req_rmeta_WIRE_10, s0_idx node _s1_req_rmeta_T_9 = bits(_s1_req_rmeta_WIRE_10, 6, 0) read mport s1_req_rmeta_MPORT_1 = meta_1[_s1_req_rmeta_T_9], clock wire _s1_req_rmeta_WIRE_11 : { is_br : UInt<1>, tag : UInt<29>} wire _s1_req_rmeta_WIRE_12 : UInt<30> connect _s1_req_rmeta_WIRE_12, s1_req_rmeta_MPORT_1[0] node _s1_req_rmeta_T_10 = bits(_s1_req_rmeta_WIRE_12, 28, 0) connect _s1_req_rmeta_WIRE_11.tag, _s1_req_rmeta_T_10 node _s1_req_rmeta_T_11 = bits(_s1_req_rmeta_WIRE_12, 29, 29) connect _s1_req_rmeta_WIRE_11.is_br, _s1_req_rmeta_T_11 wire _s1_req_rmeta_WIRE_13 : { is_br : UInt<1>, tag : UInt<29>} wire _s1_req_rmeta_WIRE_14 : UInt<30> connect _s1_req_rmeta_WIRE_14, s1_req_rmeta_MPORT_1[1] node _s1_req_rmeta_T_12 = bits(_s1_req_rmeta_WIRE_14, 28, 0) connect _s1_req_rmeta_WIRE_13.tag, _s1_req_rmeta_T_12 node _s1_req_rmeta_T_13 = bits(_s1_req_rmeta_WIRE_14, 29, 29) connect _s1_req_rmeta_WIRE_13.is_br, _s1_req_rmeta_T_13 wire _s1_req_rmeta_WIRE_15 : { is_br : UInt<1>, tag : UInt<29>} wire _s1_req_rmeta_WIRE_16 : UInt<30> connect _s1_req_rmeta_WIRE_16, s1_req_rmeta_MPORT_1[2] node _s1_req_rmeta_T_14 = bits(_s1_req_rmeta_WIRE_16, 28, 0) connect _s1_req_rmeta_WIRE_15.tag, _s1_req_rmeta_T_14 node _s1_req_rmeta_T_15 = bits(_s1_req_rmeta_WIRE_16, 29, 29) connect _s1_req_rmeta_WIRE_15.is_br, _s1_req_rmeta_T_15 wire _s1_req_rmeta_WIRE_17 : { is_br : UInt<1>, tag : UInt<29>} wire _s1_req_rmeta_WIRE_18 : UInt<30> connect _s1_req_rmeta_WIRE_18, s1_req_rmeta_MPORT_1[3] node _s1_req_rmeta_T_16 = bits(_s1_req_rmeta_WIRE_18, 28, 0) connect _s1_req_rmeta_WIRE_17.tag, _s1_req_rmeta_T_16 node _s1_req_rmeta_T_17 = bits(_s1_req_rmeta_WIRE_18, 29, 29) connect _s1_req_rmeta_WIRE_17.is_br, _s1_req_rmeta_T_17 wire _s1_req_rmeta_WIRE_19 : { is_br : UInt<1>, tag : UInt<29>}[4] connect _s1_req_rmeta_WIRE_19[0].tag, _s1_req_rmeta_WIRE_11.tag connect _s1_req_rmeta_WIRE_19[0].is_br, _s1_req_rmeta_WIRE_11.is_br connect _s1_req_rmeta_WIRE_19[1].tag, _s1_req_rmeta_WIRE_13.tag connect _s1_req_rmeta_WIRE_19[1].is_br, _s1_req_rmeta_WIRE_13.is_br connect _s1_req_rmeta_WIRE_19[2].tag, _s1_req_rmeta_WIRE_15.tag connect _s1_req_rmeta_WIRE_19[2].is_br, _s1_req_rmeta_WIRE_15.is_br connect _s1_req_rmeta_WIRE_19[3].tag, _s1_req_rmeta_WIRE_17.tag connect _s1_req_rmeta_WIRE_19[3].is_br, _s1_req_rmeta_WIRE_17.is_br wire s1_req_rmeta : { is_br : UInt<1>, tag : UInt<29>}[4][2] connect s1_req_rmeta[0], _s1_req_rmeta_WIRE_9 connect s1_req_rmeta[1], _s1_req_rmeta_WIRE_19 wire _s1_req_rebtb_WIRE : UInt<36> invalidate _s1_req_rebtb_WIRE when io.f0_valid : connect _s1_req_rebtb_WIRE, s0_idx node _s1_req_rebtb_T = bits(_s1_req_rebtb_WIRE, 6, 0) read mport s1_req_rebtb = ebtb[_s1_req_rebtb_T], clock node s1_req_tag = shr(s1_idx, 7) wire s1_resp : { valid : UInt<1>, bits : UInt<40>}[4] wire s1_is_br : UInt<1>[4] wire s1_is_jal : UInt<1>[4] node _s1_hit_ohs_T = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_1 = eq(s1_req_rmeta[0][0].tag, _s1_hit_ohs_T) node _s1_hit_ohs_T_2 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_3 = eq(s1_req_rmeta[1][0].tag, _s1_hit_ohs_T_2) wire _s1_hit_ohs_WIRE : UInt<1>[2] connect _s1_hit_ohs_WIRE[0], _s1_hit_ohs_T_1 connect _s1_hit_ohs_WIRE[1], _s1_hit_ohs_T_3 node _s1_hit_ohs_T_4 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_5 = eq(s1_req_rmeta[0][1].tag, _s1_hit_ohs_T_4) node _s1_hit_ohs_T_6 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_7 = eq(s1_req_rmeta[1][1].tag, _s1_hit_ohs_T_6) wire _s1_hit_ohs_WIRE_1 : UInt<1>[2] connect _s1_hit_ohs_WIRE_1[0], _s1_hit_ohs_T_5 connect _s1_hit_ohs_WIRE_1[1], _s1_hit_ohs_T_7 node _s1_hit_ohs_T_8 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_9 = eq(s1_req_rmeta[0][2].tag, _s1_hit_ohs_T_8) node _s1_hit_ohs_T_10 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_11 = eq(s1_req_rmeta[1][2].tag, _s1_hit_ohs_T_10) wire _s1_hit_ohs_WIRE_2 : UInt<1>[2] connect _s1_hit_ohs_WIRE_2[0], _s1_hit_ohs_T_9 connect _s1_hit_ohs_WIRE_2[1], _s1_hit_ohs_T_11 node _s1_hit_ohs_T_12 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_13 = eq(s1_req_rmeta[0][3].tag, _s1_hit_ohs_T_12) node _s1_hit_ohs_T_14 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_15 = eq(s1_req_rmeta[1][3].tag, _s1_hit_ohs_T_14) wire _s1_hit_ohs_WIRE_3 : UInt<1>[2] connect _s1_hit_ohs_WIRE_3[0], _s1_hit_ohs_T_13 connect _s1_hit_ohs_WIRE_3[1], _s1_hit_ohs_T_15 wire s1_hit_ohs : UInt<1>[2][4] connect s1_hit_ohs[0], _s1_hit_ohs_WIRE connect s1_hit_ohs[1], _s1_hit_ohs_WIRE_1 connect s1_hit_ohs[2], _s1_hit_ohs_WIRE_2 connect s1_hit_ohs[3], _s1_hit_ohs_WIRE_3 node s1_hits_0 = or(s1_hit_ohs[0][0], s1_hit_ohs[0][1]) node s1_hits_1 = or(s1_hit_ohs[1][0], s1_hit_ohs[1][1]) node s1_hits_2 = or(s1_hit_ohs[2][0], s1_hit_ohs[2][1]) node s1_hits_3 = or(s1_hit_ohs[3][0], s1_hit_ohs[3][1]) node s1_hit_ways_0 = mux(s1_hit_ohs[0][0], UInt<1>(0h0), UInt<1>(0h1)) node s1_hit_ways_1 = mux(s1_hit_ohs[1][0], UInt<1>(0h0), UInt<1>(0h1)) node s1_hit_ways_2 = mux(s1_hit_ohs[2][0], UInt<1>(0h0), UInt<1>(0h1)) node s1_hit_ways_3 = mux(s1_hit_ohs[3][0], UInt<1>(0h0), UInt<1>(0h1)) node _s1_resp_0_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_0_valid_T_1 = and(_s1_resp_0_valid_T, s1_valid) node _s1_resp_0_valid_T_2 = and(_s1_resp_0_valid_T_1, s1_hits_0) connect s1_resp[0].valid, _s1_resp_0_valid_T_2 node _s1_resp_0_bits_T = asSInt(s1_pc) node _s1_resp_0_bits_T_1 = add(_s1_resp_0_bits_T, asSInt(UInt<1>(0h0))) node _s1_resp_0_bits_T_2 = tail(_s1_resp_0_bits_T_1, 1) node _s1_resp_0_bits_T_3 = asSInt(_s1_resp_0_bits_T_2) node _s1_resp_0_bits_T_4 = add(_s1_resp_0_bits_T_3, s1_req_rbtb[s1_hit_ways_0][0].offset) node _s1_resp_0_bits_T_5 = tail(_s1_resp_0_bits_T_4, 1) node _s1_resp_0_bits_T_6 = asSInt(_s1_resp_0_bits_T_5) node _s1_resp_0_bits_T_7 = asUInt(_s1_resp_0_bits_T_6) node _s1_resp_0_bits_T_8 = mux(s1_req_rbtb[s1_hit_ways_0][0].extended, s1_req_rebtb, _s1_resp_0_bits_T_7) connect s1_resp[0].bits, _s1_resp_0_bits_T_8 node _s1_is_br_0_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_0_T_1 = and(_s1_is_br_0_T, s1_resp[0].valid) node _s1_is_br_0_T_2 = and(_s1_is_br_0_T_1, s1_req_rmeta[s1_hit_ways_0][0].is_br) connect s1_is_br[0], _s1_is_br_0_T_2 node _s1_is_jal_0_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_0_T_1 = and(_s1_is_jal_0_T, s1_resp[0].valid) node _s1_is_jal_0_T_2 = eq(s1_req_rmeta[s1_hit_ways_0][0].is_br, UInt<1>(0h0)) node _s1_is_jal_0_T_3 = and(_s1_is_jal_0_T_1, _s1_is_jal_0_T_2) connect s1_is_jal[0], _s1_is_jal_0_T_3 connect io.resp.f2[0], io.resp_in[0].f2[0] connect io.resp.f3[0], io.resp_in[0].f3[0] reg REG : UInt<1>, clock connect REG, s1_hits_0 when REG : reg io_resp_f2_0_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_0_predicted_pc_REG, s1_resp[0] connect io.resp.f2[0].predicted_pc, io_resp_f2_0_predicted_pc_REG reg io_resp_f2_0_is_br_REG : UInt<1>, clock connect io_resp_f2_0_is_br_REG, s1_is_br[0] connect io.resp.f2[0].is_br, io_resp_f2_0_is_br_REG reg io_resp_f2_0_is_jal_REG : UInt<1>, clock connect io_resp_f2_0_is_jal_REG, s1_is_jal[0] connect io.resp.f2[0].is_jal, io_resp_f2_0_is_jal_REG reg REG_1 : UInt<1>, clock connect REG_1, s1_is_jal[0] when REG_1 : connect io.resp.f2[0].taken, UInt<1>(0h1) reg REG_2 : UInt<1>, clock connect REG_2, s1_hits_0 reg REG_3 : UInt<1>, clock connect REG_3, REG_2 when REG_3 : reg io_resp_f3_0_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_0_predicted_pc_REG.bits, io.resp.f2[0].predicted_pc.bits connect io_resp_f3_0_predicted_pc_REG.valid, io.resp.f2[0].predicted_pc.valid connect io.resp.f3[0].predicted_pc, io_resp_f3_0_predicted_pc_REG reg io_resp_f3_0_is_br_REG : UInt<1>, clock connect io_resp_f3_0_is_br_REG, io.resp.f2[0].is_br connect io.resp.f3[0].is_br, io_resp_f3_0_is_br_REG reg io_resp_f3_0_is_jal_REG : UInt<1>, clock connect io_resp_f3_0_is_jal_REG, io.resp.f2[0].is_jal connect io.resp.f3[0].is_jal, io_resp_f3_0_is_jal_REG reg REG_4 : UInt<1>, clock connect REG_4, s1_is_jal[0] reg REG_5 : UInt<1>, clock connect REG_5, REG_4 when REG_5 : connect io.resp.f3[0].taken, UInt<1>(0h1) node _s1_resp_1_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_1_valid_T_1 = and(_s1_resp_1_valid_T, s1_valid) node _s1_resp_1_valid_T_2 = and(_s1_resp_1_valid_T_1, s1_hits_1) connect s1_resp[1].valid, _s1_resp_1_valid_T_2 node _s1_resp_1_bits_T = asSInt(s1_pc) node _s1_resp_1_bits_T_1 = add(_s1_resp_1_bits_T, asSInt(UInt<3>(0h2))) node _s1_resp_1_bits_T_2 = tail(_s1_resp_1_bits_T_1, 1) node _s1_resp_1_bits_T_3 = asSInt(_s1_resp_1_bits_T_2) node _s1_resp_1_bits_T_4 = add(_s1_resp_1_bits_T_3, s1_req_rbtb[s1_hit_ways_1][1].offset) node _s1_resp_1_bits_T_5 = tail(_s1_resp_1_bits_T_4, 1) node _s1_resp_1_bits_T_6 = asSInt(_s1_resp_1_bits_T_5) node _s1_resp_1_bits_T_7 = asUInt(_s1_resp_1_bits_T_6) node _s1_resp_1_bits_T_8 = mux(s1_req_rbtb[s1_hit_ways_1][1].extended, s1_req_rebtb, _s1_resp_1_bits_T_7) connect s1_resp[1].bits, _s1_resp_1_bits_T_8 node _s1_is_br_1_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_1_T_1 = and(_s1_is_br_1_T, s1_resp[1].valid) node _s1_is_br_1_T_2 = and(_s1_is_br_1_T_1, s1_req_rmeta[s1_hit_ways_1][1].is_br) connect s1_is_br[1], _s1_is_br_1_T_2 node _s1_is_jal_1_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_1_T_1 = and(_s1_is_jal_1_T, s1_resp[1].valid) node _s1_is_jal_1_T_2 = eq(s1_req_rmeta[s1_hit_ways_1][1].is_br, UInt<1>(0h0)) node _s1_is_jal_1_T_3 = and(_s1_is_jal_1_T_1, _s1_is_jal_1_T_2) connect s1_is_jal[1], _s1_is_jal_1_T_3 connect io.resp.f2[1], io.resp_in[0].f2[1] connect io.resp.f3[1], io.resp_in[0].f3[1] reg REG_6 : UInt<1>, clock connect REG_6, s1_hits_1 when REG_6 : reg io_resp_f2_1_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_1_predicted_pc_REG, s1_resp[1] connect io.resp.f2[1].predicted_pc, io_resp_f2_1_predicted_pc_REG reg io_resp_f2_1_is_br_REG : UInt<1>, clock connect io_resp_f2_1_is_br_REG, s1_is_br[1] connect io.resp.f2[1].is_br, io_resp_f2_1_is_br_REG reg io_resp_f2_1_is_jal_REG : UInt<1>, clock connect io_resp_f2_1_is_jal_REG, s1_is_jal[1] connect io.resp.f2[1].is_jal, io_resp_f2_1_is_jal_REG reg REG_7 : UInt<1>, clock connect REG_7, s1_is_jal[1] when REG_7 : connect io.resp.f2[1].taken, UInt<1>(0h1) reg REG_8 : UInt<1>, clock connect REG_8, s1_hits_1 reg REG_9 : UInt<1>, clock connect REG_9, REG_8 when REG_9 : reg io_resp_f3_1_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_1_predicted_pc_REG.bits, io.resp.f2[1].predicted_pc.bits connect io_resp_f3_1_predicted_pc_REG.valid, io.resp.f2[1].predicted_pc.valid connect io.resp.f3[1].predicted_pc, io_resp_f3_1_predicted_pc_REG reg io_resp_f3_1_is_br_REG : UInt<1>, clock connect io_resp_f3_1_is_br_REG, io.resp.f2[1].is_br connect io.resp.f3[1].is_br, io_resp_f3_1_is_br_REG reg io_resp_f3_1_is_jal_REG : UInt<1>, clock connect io_resp_f3_1_is_jal_REG, io.resp.f2[1].is_jal connect io.resp.f3[1].is_jal, io_resp_f3_1_is_jal_REG reg REG_10 : UInt<1>, clock connect REG_10, s1_is_jal[1] reg REG_11 : UInt<1>, clock connect REG_11, REG_10 when REG_11 : connect io.resp.f3[1].taken, UInt<1>(0h1) node _s1_resp_2_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_2_valid_T_1 = and(_s1_resp_2_valid_T, s1_valid) node _s1_resp_2_valid_T_2 = and(_s1_resp_2_valid_T_1, s1_hits_2) connect s1_resp[2].valid, _s1_resp_2_valid_T_2 node _s1_resp_2_bits_T = asSInt(s1_pc) node _s1_resp_2_bits_T_1 = add(_s1_resp_2_bits_T, asSInt(UInt<4>(0h4))) node _s1_resp_2_bits_T_2 = tail(_s1_resp_2_bits_T_1, 1) node _s1_resp_2_bits_T_3 = asSInt(_s1_resp_2_bits_T_2) node _s1_resp_2_bits_T_4 = add(_s1_resp_2_bits_T_3, s1_req_rbtb[s1_hit_ways_2][2].offset) node _s1_resp_2_bits_T_5 = tail(_s1_resp_2_bits_T_4, 1) node _s1_resp_2_bits_T_6 = asSInt(_s1_resp_2_bits_T_5) node _s1_resp_2_bits_T_7 = asUInt(_s1_resp_2_bits_T_6) node _s1_resp_2_bits_T_8 = mux(s1_req_rbtb[s1_hit_ways_2][2].extended, s1_req_rebtb, _s1_resp_2_bits_T_7) connect s1_resp[2].bits, _s1_resp_2_bits_T_8 node _s1_is_br_2_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_2_T_1 = and(_s1_is_br_2_T, s1_resp[2].valid) node _s1_is_br_2_T_2 = and(_s1_is_br_2_T_1, s1_req_rmeta[s1_hit_ways_2][2].is_br) connect s1_is_br[2], _s1_is_br_2_T_2 node _s1_is_jal_2_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_2_T_1 = and(_s1_is_jal_2_T, s1_resp[2].valid) node _s1_is_jal_2_T_2 = eq(s1_req_rmeta[s1_hit_ways_2][2].is_br, UInt<1>(0h0)) node _s1_is_jal_2_T_3 = and(_s1_is_jal_2_T_1, _s1_is_jal_2_T_2) connect s1_is_jal[2], _s1_is_jal_2_T_3 connect io.resp.f2[2], io.resp_in[0].f2[2] connect io.resp.f3[2], io.resp_in[0].f3[2] reg REG_12 : UInt<1>, clock connect REG_12, s1_hits_2 when REG_12 : reg io_resp_f2_2_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_2_predicted_pc_REG, s1_resp[2] connect io.resp.f2[2].predicted_pc, io_resp_f2_2_predicted_pc_REG reg io_resp_f2_2_is_br_REG : UInt<1>, clock connect io_resp_f2_2_is_br_REG, s1_is_br[2] connect io.resp.f2[2].is_br, io_resp_f2_2_is_br_REG reg io_resp_f2_2_is_jal_REG : UInt<1>, clock connect io_resp_f2_2_is_jal_REG, s1_is_jal[2] connect io.resp.f2[2].is_jal, io_resp_f2_2_is_jal_REG reg REG_13 : UInt<1>, clock connect REG_13, s1_is_jal[2] when REG_13 : connect io.resp.f2[2].taken, UInt<1>(0h1) reg REG_14 : UInt<1>, clock connect REG_14, s1_hits_2 reg REG_15 : UInt<1>, clock connect REG_15, REG_14 when REG_15 : reg io_resp_f3_2_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_2_predicted_pc_REG.bits, io.resp.f2[2].predicted_pc.bits connect io_resp_f3_2_predicted_pc_REG.valid, io.resp.f2[2].predicted_pc.valid connect io.resp.f3[2].predicted_pc, io_resp_f3_2_predicted_pc_REG reg io_resp_f3_2_is_br_REG : UInt<1>, clock connect io_resp_f3_2_is_br_REG, io.resp.f2[2].is_br connect io.resp.f3[2].is_br, io_resp_f3_2_is_br_REG reg io_resp_f3_2_is_jal_REG : UInt<1>, clock connect io_resp_f3_2_is_jal_REG, io.resp.f2[2].is_jal connect io.resp.f3[2].is_jal, io_resp_f3_2_is_jal_REG reg REG_16 : UInt<1>, clock connect REG_16, s1_is_jal[2] reg REG_17 : UInt<1>, clock connect REG_17, REG_16 when REG_17 : connect io.resp.f3[2].taken, UInt<1>(0h1) node _s1_resp_3_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_3_valid_T_1 = and(_s1_resp_3_valid_T, s1_valid) node _s1_resp_3_valid_T_2 = and(_s1_resp_3_valid_T_1, s1_hits_3) connect s1_resp[3].valid, _s1_resp_3_valid_T_2 node _s1_resp_3_bits_T = asSInt(s1_pc) node _s1_resp_3_bits_T_1 = add(_s1_resp_3_bits_T, asSInt(UInt<4>(0h6))) node _s1_resp_3_bits_T_2 = tail(_s1_resp_3_bits_T_1, 1) node _s1_resp_3_bits_T_3 = asSInt(_s1_resp_3_bits_T_2) node _s1_resp_3_bits_T_4 = add(_s1_resp_3_bits_T_3, s1_req_rbtb[s1_hit_ways_3][3].offset) node _s1_resp_3_bits_T_5 = tail(_s1_resp_3_bits_T_4, 1) node _s1_resp_3_bits_T_6 = asSInt(_s1_resp_3_bits_T_5) node _s1_resp_3_bits_T_7 = asUInt(_s1_resp_3_bits_T_6) node _s1_resp_3_bits_T_8 = mux(s1_req_rbtb[s1_hit_ways_3][3].extended, s1_req_rebtb, _s1_resp_3_bits_T_7) connect s1_resp[3].bits, _s1_resp_3_bits_T_8 node _s1_is_br_3_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_3_T_1 = and(_s1_is_br_3_T, s1_resp[3].valid) node _s1_is_br_3_T_2 = and(_s1_is_br_3_T_1, s1_req_rmeta[s1_hit_ways_3][3].is_br) connect s1_is_br[3], _s1_is_br_3_T_2 node _s1_is_jal_3_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_3_T_1 = and(_s1_is_jal_3_T, s1_resp[3].valid) node _s1_is_jal_3_T_2 = eq(s1_req_rmeta[s1_hit_ways_3][3].is_br, UInt<1>(0h0)) node _s1_is_jal_3_T_3 = and(_s1_is_jal_3_T_1, _s1_is_jal_3_T_2) connect s1_is_jal[3], _s1_is_jal_3_T_3 connect io.resp.f2[3], io.resp_in[0].f2[3] connect io.resp.f3[3], io.resp_in[0].f3[3] reg REG_18 : UInt<1>, clock connect REG_18, s1_hits_3 when REG_18 : reg io_resp_f2_3_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_3_predicted_pc_REG, s1_resp[3] connect io.resp.f2[3].predicted_pc, io_resp_f2_3_predicted_pc_REG reg io_resp_f2_3_is_br_REG : UInt<1>, clock connect io_resp_f2_3_is_br_REG, s1_is_br[3] connect io.resp.f2[3].is_br, io_resp_f2_3_is_br_REG reg io_resp_f2_3_is_jal_REG : UInt<1>, clock connect io_resp_f2_3_is_jal_REG, s1_is_jal[3] connect io.resp.f2[3].is_jal, io_resp_f2_3_is_jal_REG reg REG_19 : UInt<1>, clock connect REG_19, s1_is_jal[3] when REG_19 : connect io.resp.f2[3].taken, UInt<1>(0h1) reg REG_20 : UInt<1>, clock connect REG_20, s1_hits_3 reg REG_21 : UInt<1>, clock connect REG_21, REG_20 when REG_21 : reg io_resp_f3_3_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_3_predicted_pc_REG.bits, io.resp.f2[3].predicted_pc.bits connect io_resp_f3_3_predicted_pc_REG.valid, io.resp.f2[3].predicted_pc.valid connect io.resp.f3[3].predicted_pc, io_resp_f3_3_predicted_pc_REG reg io_resp_f3_3_is_br_REG : UInt<1>, clock connect io_resp_f3_3_is_br_REG, io.resp.f2[3].is_br connect io.resp.f3[3].is_br, io_resp_f3_3_is_br_REG reg io_resp_f3_3_is_jal_REG : UInt<1>, clock connect io_resp_f3_3_is_jal_REG, io.resp.f2[3].is_jal connect io.resp.f3[3].is_jal, io_resp_f3_3_is_jal_REG reg REG_22 : UInt<1>, clock connect REG_22, s1_is_jal[3] reg REG_23 : UInt<1>, clock connect REG_23, REG_22 when REG_23 : connect io.resp.f3[3].taken, UInt<1>(0h1) wire _alloc_way_r_metas_WIRE : UInt<29>[4] connect _alloc_way_r_metas_WIRE[0], s1_req_rmeta[0][0].tag connect _alloc_way_r_metas_WIRE[1], s1_req_rmeta[0][1].tag connect _alloc_way_r_metas_WIRE[2], s1_req_rmeta[0][2].tag connect _alloc_way_r_metas_WIRE[3], s1_req_rmeta[0][3].tag wire _alloc_way_r_metas_WIRE_1 : UInt<29>[4] connect _alloc_way_r_metas_WIRE_1[0], s1_req_rmeta[1][0].tag connect _alloc_way_r_metas_WIRE_1[1], s1_req_rmeta[1][1].tag connect _alloc_way_r_metas_WIRE_1[2], s1_req_rmeta[1][2].tag connect _alloc_way_r_metas_WIRE_1[3], s1_req_rmeta[1][3].tag wire _alloc_way_r_metas_WIRE_2 : UInt<29>[4][2] connect _alloc_way_r_metas_WIRE_2[0], _alloc_way_r_metas_WIRE connect _alloc_way_r_metas_WIRE_2[1], _alloc_way_r_metas_WIRE_1 node alloc_way_r_metas_lo = cat(_alloc_way_r_metas_WIRE_2[0][1], _alloc_way_r_metas_WIRE_2[0][0]) node alloc_way_r_metas_hi = cat(_alloc_way_r_metas_WIRE_2[0][3], _alloc_way_r_metas_WIRE_2[0][2]) node _alloc_way_r_metas_T = cat(alloc_way_r_metas_hi, alloc_way_r_metas_lo) node alloc_way_r_metas_lo_1 = cat(_alloc_way_r_metas_WIRE_2[1][1], _alloc_way_r_metas_WIRE_2[1][0]) node alloc_way_r_metas_hi_1 = cat(_alloc_way_r_metas_WIRE_2[1][3], _alloc_way_r_metas_WIRE_2[1][2]) node _alloc_way_r_metas_T_1 = cat(alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1) node _alloc_way_r_metas_T_2 = cat(_alloc_way_r_metas_T_1, _alloc_way_r_metas_T) node _alloc_way_r_metas_T_3 = bits(s1_req_tag, 28, 0) node alloc_way_r_metas = cat(_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3) node alloc_way_chunks_0 = bits(alloc_way_r_metas, 0, 0) node alloc_way_chunks_1 = bits(alloc_way_r_metas, 1, 1) node alloc_way_chunks_2 = bits(alloc_way_r_metas, 2, 2) node alloc_way_chunks_3 = bits(alloc_way_r_metas, 3, 3) node alloc_way_chunks_4 = bits(alloc_way_r_metas, 4, 4) node alloc_way_chunks_5 = bits(alloc_way_r_metas, 5, 5) node alloc_way_chunks_6 = bits(alloc_way_r_metas, 6, 6) node alloc_way_chunks_7 = bits(alloc_way_r_metas, 7, 7) node alloc_way_chunks_8 = bits(alloc_way_r_metas, 8, 8) node alloc_way_chunks_9 = bits(alloc_way_r_metas, 9, 9) node alloc_way_chunks_10 = bits(alloc_way_r_metas, 10, 10) node alloc_way_chunks_11 = bits(alloc_way_r_metas, 11, 11) node alloc_way_chunks_12 = bits(alloc_way_r_metas, 12, 12) node alloc_way_chunks_13 = bits(alloc_way_r_metas, 13, 13) node alloc_way_chunks_14 = bits(alloc_way_r_metas, 14, 14) node alloc_way_chunks_15 = bits(alloc_way_r_metas, 15, 15) node alloc_way_chunks_16 = bits(alloc_way_r_metas, 16, 16) node alloc_way_chunks_17 = bits(alloc_way_r_metas, 17, 17) node alloc_way_chunks_18 = bits(alloc_way_r_metas, 18, 18) node alloc_way_chunks_19 = bits(alloc_way_r_metas, 19, 19) node alloc_way_chunks_20 = bits(alloc_way_r_metas, 20, 20) node alloc_way_chunks_21 = bits(alloc_way_r_metas, 21, 21) node alloc_way_chunks_22 = bits(alloc_way_r_metas, 22, 22) node alloc_way_chunks_23 = bits(alloc_way_r_metas, 23, 23) node alloc_way_chunks_24 = bits(alloc_way_r_metas, 24, 24) node alloc_way_chunks_25 = bits(alloc_way_r_metas, 25, 25) node alloc_way_chunks_26 = bits(alloc_way_r_metas, 26, 26) node alloc_way_chunks_27 = bits(alloc_way_r_metas, 27, 27) node alloc_way_chunks_28 = bits(alloc_way_r_metas, 28, 28) node alloc_way_chunks_29 = bits(alloc_way_r_metas, 29, 29) node alloc_way_chunks_30 = bits(alloc_way_r_metas, 30, 30) node alloc_way_chunks_31 = bits(alloc_way_r_metas, 31, 31) node alloc_way_chunks_32 = bits(alloc_way_r_metas, 32, 32) node alloc_way_chunks_33 = bits(alloc_way_r_metas, 33, 33) node alloc_way_chunks_34 = bits(alloc_way_r_metas, 34, 34) node alloc_way_chunks_35 = bits(alloc_way_r_metas, 35, 35) node alloc_way_chunks_36 = bits(alloc_way_r_metas, 36, 36) node alloc_way_chunks_37 = bits(alloc_way_r_metas, 37, 37) node alloc_way_chunks_38 = bits(alloc_way_r_metas, 38, 38) node alloc_way_chunks_39 = bits(alloc_way_r_metas, 39, 39) node alloc_way_chunks_40 = bits(alloc_way_r_metas, 40, 40) node alloc_way_chunks_41 = bits(alloc_way_r_metas, 41, 41) node alloc_way_chunks_42 = bits(alloc_way_r_metas, 42, 42) node alloc_way_chunks_43 = bits(alloc_way_r_metas, 43, 43) node alloc_way_chunks_44 = bits(alloc_way_r_metas, 44, 44) node alloc_way_chunks_45 = bits(alloc_way_r_metas, 45, 45) node alloc_way_chunks_46 = bits(alloc_way_r_metas, 46, 46) node alloc_way_chunks_47 = bits(alloc_way_r_metas, 47, 47) node alloc_way_chunks_48 = bits(alloc_way_r_metas, 48, 48) node alloc_way_chunks_49 = bits(alloc_way_r_metas, 49, 49) node alloc_way_chunks_50 = bits(alloc_way_r_metas, 50, 50) node alloc_way_chunks_51 = bits(alloc_way_r_metas, 51, 51) node alloc_way_chunks_52 = bits(alloc_way_r_metas, 52, 52) node alloc_way_chunks_53 = bits(alloc_way_r_metas, 53, 53) node alloc_way_chunks_54 = bits(alloc_way_r_metas, 54, 54) node alloc_way_chunks_55 = bits(alloc_way_r_metas, 55, 55) node alloc_way_chunks_56 = bits(alloc_way_r_metas, 56, 56) node alloc_way_chunks_57 = bits(alloc_way_r_metas, 57, 57) node alloc_way_chunks_58 = bits(alloc_way_r_metas, 58, 58) node alloc_way_chunks_59 = bits(alloc_way_r_metas, 59, 59) node alloc_way_chunks_60 = bits(alloc_way_r_metas, 60, 60) node alloc_way_chunks_61 = bits(alloc_way_r_metas, 61, 61) node alloc_way_chunks_62 = bits(alloc_way_r_metas, 62, 62) node alloc_way_chunks_63 = bits(alloc_way_r_metas, 63, 63) node alloc_way_chunks_64 = bits(alloc_way_r_metas, 64, 64) node alloc_way_chunks_65 = bits(alloc_way_r_metas, 65, 65) node alloc_way_chunks_66 = bits(alloc_way_r_metas, 66, 66) node alloc_way_chunks_67 = bits(alloc_way_r_metas, 67, 67) node alloc_way_chunks_68 = bits(alloc_way_r_metas, 68, 68) node alloc_way_chunks_69 = bits(alloc_way_r_metas, 69, 69) node alloc_way_chunks_70 = bits(alloc_way_r_metas, 70, 70) node alloc_way_chunks_71 = bits(alloc_way_r_metas, 71, 71) node alloc_way_chunks_72 = bits(alloc_way_r_metas, 72, 72) node alloc_way_chunks_73 = bits(alloc_way_r_metas, 73, 73) node alloc_way_chunks_74 = bits(alloc_way_r_metas, 74, 74) node alloc_way_chunks_75 = bits(alloc_way_r_metas, 75, 75) node alloc_way_chunks_76 = bits(alloc_way_r_metas, 76, 76) node alloc_way_chunks_77 = bits(alloc_way_r_metas, 77, 77) node alloc_way_chunks_78 = bits(alloc_way_r_metas, 78, 78) node alloc_way_chunks_79 = bits(alloc_way_r_metas, 79, 79) node alloc_way_chunks_80 = bits(alloc_way_r_metas, 80, 80) node alloc_way_chunks_81 = bits(alloc_way_r_metas, 81, 81) node alloc_way_chunks_82 = bits(alloc_way_r_metas, 82, 82) node alloc_way_chunks_83 = bits(alloc_way_r_metas, 83, 83) node alloc_way_chunks_84 = bits(alloc_way_r_metas, 84, 84) node alloc_way_chunks_85 = bits(alloc_way_r_metas, 85, 85) node alloc_way_chunks_86 = bits(alloc_way_r_metas, 86, 86) node alloc_way_chunks_87 = bits(alloc_way_r_metas, 87, 87) node alloc_way_chunks_88 = bits(alloc_way_r_metas, 88, 88) node alloc_way_chunks_89 = bits(alloc_way_r_metas, 89, 89) node alloc_way_chunks_90 = bits(alloc_way_r_metas, 90, 90) node alloc_way_chunks_91 = bits(alloc_way_r_metas, 91, 91) node alloc_way_chunks_92 = bits(alloc_way_r_metas, 92, 92) node alloc_way_chunks_93 = bits(alloc_way_r_metas, 93, 93) node alloc_way_chunks_94 = bits(alloc_way_r_metas, 94, 94) node alloc_way_chunks_95 = bits(alloc_way_r_metas, 95, 95) node alloc_way_chunks_96 = bits(alloc_way_r_metas, 96, 96) node alloc_way_chunks_97 = bits(alloc_way_r_metas, 97, 97) node alloc_way_chunks_98 = bits(alloc_way_r_metas, 98, 98) node alloc_way_chunks_99 = bits(alloc_way_r_metas, 99, 99) node alloc_way_chunks_100 = bits(alloc_way_r_metas, 100, 100) node alloc_way_chunks_101 = bits(alloc_way_r_metas, 101, 101) node alloc_way_chunks_102 = bits(alloc_way_r_metas, 102, 102) node alloc_way_chunks_103 = bits(alloc_way_r_metas, 103, 103) node alloc_way_chunks_104 = bits(alloc_way_r_metas, 104, 104) node alloc_way_chunks_105 = bits(alloc_way_r_metas, 105, 105) node alloc_way_chunks_106 = bits(alloc_way_r_metas, 106, 106) node alloc_way_chunks_107 = bits(alloc_way_r_metas, 107, 107) node alloc_way_chunks_108 = bits(alloc_way_r_metas, 108, 108) node alloc_way_chunks_109 = bits(alloc_way_r_metas, 109, 109) node alloc_way_chunks_110 = bits(alloc_way_r_metas, 110, 110) node alloc_way_chunks_111 = bits(alloc_way_r_metas, 111, 111) node alloc_way_chunks_112 = bits(alloc_way_r_metas, 112, 112) node alloc_way_chunks_113 = bits(alloc_way_r_metas, 113, 113) node alloc_way_chunks_114 = bits(alloc_way_r_metas, 114, 114) node alloc_way_chunks_115 = bits(alloc_way_r_metas, 115, 115) node alloc_way_chunks_116 = bits(alloc_way_r_metas, 116, 116) node alloc_way_chunks_117 = bits(alloc_way_r_metas, 117, 117) node alloc_way_chunks_118 = bits(alloc_way_r_metas, 118, 118) node alloc_way_chunks_119 = bits(alloc_way_r_metas, 119, 119) node alloc_way_chunks_120 = bits(alloc_way_r_metas, 120, 120) node alloc_way_chunks_121 = bits(alloc_way_r_metas, 121, 121) node alloc_way_chunks_122 = bits(alloc_way_r_metas, 122, 122) node alloc_way_chunks_123 = bits(alloc_way_r_metas, 123, 123) node alloc_way_chunks_124 = bits(alloc_way_r_metas, 124, 124) node alloc_way_chunks_125 = bits(alloc_way_r_metas, 125, 125) node alloc_way_chunks_126 = bits(alloc_way_r_metas, 126, 126) node alloc_way_chunks_127 = bits(alloc_way_r_metas, 127, 127) node alloc_way_chunks_128 = bits(alloc_way_r_metas, 128, 128) node alloc_way_chunks_129 = bits(alloc_way_r_metas, 129, 129) node alloc_way_chunks_130 = bits(alloc_way_r_metas, 130, 130) node alloc_way_chunks_131 = bits(alloc_way_r_metas, 131, 131) node alloc_way_chunks_132 = bits(alloc_way_r_metas, 132, 132) node alloc_way_chunks_133 = bits(alloc_way_r_metas, 133, 133) node alloc_way_chunks_134 = bits(alloc_way_r_metas, 134, 134) node alloc_way_chunks_135 = bits(alloc_way_r_metas, 135, 135) node alloc_way_chunks_136 = bits(alloc_way_r_metas, 136, 136) node alloc_way_chunks_137 = bits(alloc_way_r_metas, 137, 137) node alloc_way_chunks_138 = bits(alloc_way_r_metas, 138, 138) node alloc_way_chunks_139 = bits(alloc_way_r_metas, 139, 139) node alloc_way_chunks_140 = bits(alloc_way_r_metas, 140, 140) node alloc_way_chunks_141 = bits(alloc_way_r_metas, 141, 141) node alloc_way_chunks_142 = bits(alloc_way_r_metas, 142, 142) node alloc_way_chunks_143 = bits(alloc_way_r_metas, 143, 143) node alloc_way_chunks_144 = bits(alloc_way_r_metas, 144, 144) node alloc_way_chunks_145 = bits(alloc_way_r_metas, 145, 145) node alloc_way_chunks_146 = bits(alloc_way_r_metas, 146, 146) node alloc_way_chunks_147 = bits(alloc_way_r_metas, 147, 147) node alloc_way_chunks_148 = bits(alloc_way_r_metas, 148, 148) node alloc_way_chunks_149 = bits(alloc_way_r_metas, 149, 149) node alloc_way_chunks_150 = bits(alloc_way_r_metas, 150, 150) node alloc_way_chunks_151 = bits(alloc_way_r_metas, 151, 151) node alloc_way_chunks_152 = bits(alloc_way_r_metas, 152, 152) node alloc_way_chunks_153 = bits(alloc_way_r_metas, 153, 153) node alloc_way_chunks_154 = bits(alloc_way_r_metas, 154, 154) node alloc_way_chunks_155 = bits(alloc_way_r_metas, 155, 155) node alloc_way_chunks_156 = bits(alloc_way_r_metas, 156, 156) node alloc_way_chunks_157 = bits(alloc_way_r_metas, 157, 157) node alloc_way_chunks_158 = bits(alloc_way_r_metas, 158, 158) node alloc_way_chunks_159 = bits(alloc_way_r_metas, 159, 159) node alloc_way_chunks_160 = bits(alloc_way_r_metas, 160, 160) node alloc_way_chunks_161 = bits(alloc_way_r_metas, 161, 161) node alloc_way_chunks_162 = bits(alloc_way_r_metas, 162, 162) node alloc_way_chunks_163 = bits(alloc_way_r_metas, 163, 163) node alloc_way_chunks_164 = bits(alloc_way_r_metas, 164, 164) node alloc_way_chunks_165 = bits(alloc_way_r_metas, 165, 165) node alloc_way_chunks_166 = bits(alloc_way_r_metas, 166, 166) node alloc_way_chunks_167 = bits(alloc_way_r_metas, 167, 167) node alloc_way_chunks_168 = bits(alloc_way_r_metas, 168, 168) node alloc_way_chunks_169 = bits(alloc_way_r_metas, 169, 169) node alloc_way_chunks_170 = bits(alloc_way_r_metas, 170, 170) node alloc_way_chunks_171 = bits(alloc_way_r_metas, 171, 171) node alloc_way_chunks_172 = bits(alloc_way_r_metas, 172, 172) node alloc_way_chunks_173 = bits(alloc_way_r_metas, 173, 173) node alloc_way_chunks_174 = bits(alloc_way_r_metas, 174, 174) node alloc_way_chunks_175 = bits(alloc_way_r_metas, 175, 175) node alloc_way_chunks_176 = bits(alloc_way_r_metas, 176, 176) node alloc_way_chunks_177 = bits(alloc_way_r_metas, 177, 177) node alloc_way_chunks_178 = bits(alloc_way_r_metas, 178, 178) node alloc_way_chunks_179 = bits(alloc_way_r_metas, 179, 179) node alloc_way_chunks_180 = bits(alloc_way_r_metas, 180, 180) node alloc_way_chunks_181 = bits(alloc_way_r_metas, 181, 181) node alloc_way_chunks_182 = bits(alloc_way_r_metas, 182, 182) node alloc_way_chunks_183 = bits(alloc_way_r_metas, 183, 183) node alloc_way_chunks_184 = bits(alloc_way_r_metas, 184, 184) node alloc_way_chunks_185 = bits(alloc_way_r_metas, 185, 185) node alloc_way_chunks_186 = bits(alloc_way_r_metas, 186, 186) node alloc_way_chunks_187 = bits(alloc_way_r_metas, 187, 187) node alloc_way_chunks_188 = bits(alloc_way_r_metas, 188, 188) node alloc_way_chunks_189 = bits(alloc_way_r_metas, 189, 189) node alloc_way_chunks_190 = bits(alloc_way_r_metas, 190, 190) node alloc_way_chunks_191 = bits(alloc_way_r_metas, 191, 191) node alloc_way_chunks_192 = bits(alloc_way_r_metas, 192, 192) node alloc_way_chunks_193 = bits(alloc_way_r_metas, 193, 193) node alloc_way_chunks_194 = bits(alloc_way_r_metas, 194, 194) node alloc_way_chunks_195 = bits(alloc_way_r_metas, 195, 195) node alloc_way_chunks_196 = bits(alloc_way_r_metas, 196, 196) node alloc_way_chunks_197 = bits(alloc_way_r_metas, 197, 197) node alloc_way_chunks_198 = bits(alloc_way_r_metas, 198, 198) node alloc_way_chunks_199 = bits(alloc_way_r_metas, 199, 199) node alloc_way_chunks_200 = bits(alloc_way_r_metas, 200, 200) node alloc_way_chunks_201 = bits(alloc_way_r_metas, 201, 201) node alloc_way_chunks_202 = bits(alloc_way_r_metas, 202, 202) node alloc_way_chunks_203 = bits(alloc_way_r_metas, 203, 203) node alloc_way_chunks_204 = bits(alloc_way_r_metas, 204, 204) node alloc_way_chunks_205 = bits(alloc_way_r_metas, 205, 205) node alloc_way_chunks_206 = bits(alloc_way_r_metas, 206, 206) node alloc_way_chunks_207 = bits(alloc_way_r_metas, 207, 207) node alloc_way_chunks_208 = bits(alloc_way_r_metas, 208, 208) node alloc_way_chunks_209 = bits(alloc_way_r_metas, 209, 209) node alloc_way_chunks_210 = bits(alloc_way_r_metas, 210, 210) node alloc_way_chunks_211 = bits(alloc_way_r_metas, 211, 211) node alloc_way_chunks_212 = bits(alloc_way_r_metas, 212, 212) node alloc_way_chunks_213 = bits(alloc_way_r_metas, 213, 213) node alloc_way_chunks_214 = bits(alloc_way_r_metas, 214, 214) node alloc_way_chunks_215 = bits(alloc_way_r_metas, 215, 215) node alloc_way_chunks_216 = bits(alloc_way_r_metas, 216, 216) node alloc_way_chunks_217 = bits(alloc_way_r_metas, 217, 217) node alloc_way_chunks_218 = bits(alloc_way_r_metas, 218, 218) node alloc_way_chunks_219 = bits(alloc_way_r_metas, 219, 219) node alloc_way_chunks_220 = bits(alloc_way_r_metas, 220, 220) node alloc_way_chunks_221 = bits(alloc_way_r_metas, 221, 221) node alloc_way_chunks_222 = bits(alloc_way_r_metas, 222, 222) node alloc_way_chunks_223 = bits(alloc_way_r_metas, 223, 223) node alloc_way_chunks_224 = bits(alloc_way_r_metas, 224, 224) node alloc_way_chunks_225 = bits(alloc_way_r_metas, 225, 225) node alloc_way_chunks_226 = bits(alloc_way_r_metas, 226, 226) node alloc_way_chunks_227 = bits(alloc_way_r_metas, 227, 227) node alloc_way_chunks_228 = bits(alloc_way_r_metas, 228, 228) node alloc_way_chunks_229 = bits(alloc_way_r_metas, 229, 229) node alloc_way_chunks_230 = bits(alloc_way_r_metas, 230, 230) node alloc_way_chunks_231 = bits(alloc_way_r_metas, 231, 231) node alloc_way_chunks_232 = bits(alloc_way_r_metas, 232, 232) node alloc_way_chunks_233 = bits(alloc_way_r_metas, 233, 233) node alloc_way_chunks_234 = bits(alloc_way_r_metas, 234, 234) node alloc_way_chunks_235 = bits(alloc_way_r_metas, 235, 235) node alloc_way_chunks_236 = bits(alloc_way_r_metas, 236, 236) node alloc_way_chunks_237 = bits(alloc_way_r_metas, 237, 237) node alloc_way_chunks_238 = bits(alloc_way_r_metas, 238, 238) node alloc_way_chunks_239 = bits(alloc_way_r_metas, 239, 239) node alloc_way_chunks_240 = bits(alloc_way_r_metas, 240, 240) node alloc_way_chunks_241 = bits(alloc_way_r_metas, 241, 241) node alloc_way_chunks_242 = bits(alloc_way_r_metas, 242, 242) node alloc_way_chunks_243 = bits(alloc_way_r_metas, 243, 243) node alloc_way_chunks_244 = bits(alloc_way_r_metas, 244, 244) node alloc_way_chunks_245 = bits(alloc_way_r_metas, 245, 245) node alloc_way_chunks_246 = bits(alloc_way_r_metas, 246, 246) node alloc_way_chunks_247 = bits(alloc_way_r_metas, 247, 247) node alloc_way_chunks_248 = bits(alloc_way_r_metas, 248, 248) node alloc_way_chunks_249 = bits(alloc_way_r_metas, 249, 249) node alloc_way_chunks_250 = bits(alloc_way_r_metas, 250, 250) node alloc_way_chunks_251 = bits(alloc_way_r_metas, 251, 251) node alloc_way_chunks_252 = bits(alloc_way_r_metas, 252, 252) node alloc_way_chunks_253 = bits(alloc_way_r_metas, 253, 253) node alloc_way_chunks_254 = bits(alloc_way_r_metas, 254, 254) node alloc_way_chunks_255 = bits(alloc_way_r_metas, 255, 255) node alloc_way_chunks_256 = bits(alloc_way_r_metas, 256, 256) node alloc_way_chunks_257 = bits(alloc_way_r_metas, 257, 257) node alloc_way_chunks_258 = bits(alloc_way_r_metas, 258, 258) node alloc_way_chunks_259 = bits(alloc_way_r_metas, 259, 259) node alloc_way_chunks_260 = bits(alloc_way_r_metas, 260, 260) node _alloc_way_T = xor(alloc_way_chunks_0, alloc_way_chunks_1) node _alloc_way_T_1 = xor(_alloc_way_T, alloc_way_chunks_2) node _alloc_way_T_2 = xor(_alloc_way_T_1, alloc_way_chunks_3) node _alloc_way_T_3 = xor(_alloc_way_T_2, alloc_way_chunks_4) node _alloc_way_T_4 = xor(_alloc_way_T_3, alloc_way_chunks_5) node _alloc_way_T_5 = xor(_alloc_way_T_4, alloc_way_chunks_6) node _alloc_way_T_6 = xor(_alloc_way_T_5, alloc_way_chunks_7) node _alloc_way_T_7 = xor(_alloc_way_T_6, alloc_way_chunks_8) node _alloc_way_T_8 = xor(_alloc_way_T_7, alloc_way_chunks_9) node _alloc_way_T_9 = xor(_alloc_way_T_8, alloc_way_chunks_10) node _alloc_way_T_10 = xor(_alloc_way_T_9, alloc_way_chunks_11) node _alloc_way_T_11 = xor(_alloc_way_T_10, alloc_way_chunks_12) node _alloc_way_T_12 = xor(_alloc_way_T_11, alloc_way_chunks_13) node _alloc_way_T_13 = xor(_alloc_way_T_12, alloc_way_chunks_14) node _alloc_way_T_14 = xor(_alloc_way_T_13, alloc_way_chunks_15) node _alloc_way_T_15 = xor(_alloc_way_T_14, alloc_way_chunks_16) node _alloc_way_T_16 = xor(_alloc_way_T_15, alloc_way_chunks_17) node _alloc_way_T_17 = xor(_alloc_way_T_16, alloc_way_chunks_18) node _alloc_way_T_18 = xor(_alloc_way_T_17, alloc_way_chunks_19) node _alloc_way_T_19 = xor(_alloc_way_T_18, alloc_way_chunks_20) node _alloc_way_T_20 = xor(_alloc_way_T_19, alloc_way_chunks_21) node _alloc_way_T_21 = xor(_alloc_way_T_20, alloc_way_chunks_22) node _alloc_way_T_22 = xor(_alloc_way_T_21, alloc_way_chunks_23) node _alloc_way_T_23 = xor(_alloc_way_T_22, alloc_way_chunks_24) node _alloc_way_T_24 = xor(_alloc_way_T_23, alloc_way_chunks_25) node _alloc_way_T_25 = xor(_alloc_way_T_24, alloc_way_chunks_26) node _alloc_way_T_26 = xor(_alloc_way_T_25, alloc_way_chunks_27) node _alloc_way_T_27 = xor(_alloc_way_T_26, alloc_way_chunks_28) node _alloc_way_T_28 = xor(_alloc_way_T_27, alloc_way_chunks_29) node _alloc_way_T_29 = xor(_alloc_way_T_28, alloc_way_chunks_30) node _alloc_way_T_30 = xor(_alloc_way_T_29, alloc_way_chunks_31) node _alloc_way_T_31 = xor(_alloc_way_T_30, alloc_way_chunks_32) node _alloc_way_T_32 = xor(_alloc_way_T_31, alloc_way_chunks_33) node _alloc_way_T_33 = xor(_alloc_way_T_32, alloc_way_chunks_34) node _alloc_way_T_34 = xor(_alloc_way_T_33, alloc_way_chunks_35) node _alloc_way_T_35 = xor(_alloc_way_T_34, alloc_way_chunks_36) node _alloc_way_T_36 = xor(_alloc_way_T_35, alloc_way_chunks_37) node _alloc_way_T_37 = xor(_alloc_way_T_36, alloc_way_chunks_38) node _alloc_way_T_38 = xor(_alloc_way_T_37, alloc_way_chunks_39) node _alloc_way_T_39 = xor(_alloc_way_T_38, alloc_way_chunks_40) node _alloc_way_T_40 = xor(_alloc_way_T_39, alloc_way_chunks_41) node _alloc_way_T_41 = xor(_alloc_way_T_40, alloc_way_chunks_42) node _alloc_way_T_42 = xor(_alloc_way_T_41, alloc_way_chunks_43) node _alloc_way_T_43 = xor(_alloc_way_T_42, alloc_way_chunks_44) node _alloc_way_T_44 = xor(_alloc_way_T_43, alloc_way_chunks_45) node _alloc_way_T_45 = xor(_alloc_way_T_44, alloc_way_chunks_46) node _alloc_way_T_46 = xor(_alloc_way_T_45, alloc_way_chunks_47) node _alloc_way_T_47 = xor(_alloc_way_T_46, alloc_way_chunks_48) node _alloc_way_T_48 = xor(_alloc_way_T_47, alloc_way_chunks_49) node _alloc_way_T_49 = xor(_alloc_way_T_48, alloc_way_chunks_50) node _alloc_way_T_50 = xor(_alloc_way_T_49, alloc_way_chunks_51) node _alloc_way_T_51 = xor(_alloc_way_T_50, alloc_way_chunks_52) node _alloc_way_T_52 = xor(_alloc_way_T_51, alloc_way_chunks_53) node _alloc_way_T_53 = xor(_alloc_way_T_52, alloc_way_chunks_54) node _alloc_way_T_54 = xor(_alloc_way_T_53, alloc_way_chunks_55) node _alloc_way_T_55 = xor(_alloc_way_T_54, alloc_way_chunks_56) node _alloc_way_T_56 = xor(_alloc_way_T_55, alloc_way_chunks_57) node _alloc_way_T_57 = xor(_alloc_way_T_56, alloc_way_chunks_58) node _alloc_way_T_58 = xor(_alloc_way_T_57, alloc_way_chunks_59) node _alloc_way_T_59 = xor(_alloc_way_T_58, alloc_way_chunks_60) node _alloc_way_T_60 = xor(_alloc_way_T_59, alloc_way_chunks_61) node _alloc_way_T_61 = xor(_alloc_way_T_60, alloc_way_chunks_62) node _alloc_way_T_62 = xor(_alloc_way_T_61, alloc_way_chunks_63) node _alloc_way_T_63 = xor(_alloc_way_T_62, alloc_way_chunks_64) node _alloc_way_T_64 = xor(_alloc_way_T_63, alloc_way_chunks_65) node _alloc_way_T_65 = xor(_alloc_way_T_64, alloc_way_chunks_66) node _alloc_way_T_66 = xor(_alloc_way_T_65, alloc_way_chunks_67) node _alloc_way_T_67 = xor(_alloc_way_T_66, alloc_way_chunks_68) node _alloc_way_T_68 = xor(_alloc_way_T_67, alloc_way_chunks_69) node _alloc_way_T_69 = xor(_alloc_way_T_68, alloc_way_chunks_70) node _alloc_way_T_70 = xor(_alloc_way_T_69, alloc_way_chunks_71) node _alloc_way_T_71 = xor(_alloc_way_T_70, alloc_way_chunks_72) node _alloc_way_T_72 = xor(_alloc_way_T_71, alloc_way_chunks_73) node _alloc_way_T_73 = xor(_alloc_way_T_72, alloc_way_chunks_74) node _alloc_way_T_74 = xor(_alloc_way_T_73, alloc_way_chunks_75) node _alloc_way_T_75 = xor(_alloc_way_T_74, alloc_way_chunks_76) node _alloc_way_T_76 = xor(_alloc_way_T_75, alloc_way_chunks_77) node _alloc_way_T_77 = xor(_alloc_way_T_76, alloc_way_chunks_78) node _alloc_way_T_78 = xor(_alloc_way_T_77, alloc_way_chunks_79) node _alloc_way_T_79 = xor(_alloc_way_T_78, alloc_way_chunks_80) node _alloc_way_T_80 = xor(_alloc_way_T_79, alloc_way_chunks_81) node _alloc_way_T_81 = xor(_alloc_way_T_80, alloc_way_chunks_82) node _alloc_way_T_82 = xor(_alloc_way_T_81, alloc_way_chunks_83) node _alloc_way_T_83 = xor(_alloc_way_T_82, alloc_way_chunks_84) node _alloc_way_T_84 = xor(_alloc_way_T_83, alloc_way_chunks_85) node _alloc_way_T_85 = xor(_alloc_way_T_84, alloc_way_chunks_86) node _alloc_way_T_86 = xor(_alloc_way_T_85, alloc_way_chunks_87) node _alloc_way_T_87 = xor(_alloc_way_T_86, alloc_way_chunks_88) node _alloc_way_T_88 = xor(_alloc_way_T_87, alloc_way_chunks_89) node _alloc_way_T_89 = xor(_alloc_way_T_88, alloc_way_chunks_90) node _alloc_way_T_90 = xor(_alloc_way_T_89, alloc_way_chunks_91) node _alloc_way_T_91 = xor(_alloc_way_T_90, alloc_way_chunks_92) node _alloc_way_T_92 = xor(_alloc_way_T_91, alloc_way_chunks_93) node _alloc_way_T_93 = xor(_alloc_way_T_92, alloc_way_chunks_94) node _alloc_way_T_94 = xor(_alloc_way_T_93, alloc_way_chunks_95) node _alloc_way_T_95 = xor(_alloc_way_T_94, alloc_way_chunks_96) node _alloc_way_T_96 = xor(_alloc_way_T_95, alloc_way_chunks_97) node _alloc_way_T_97 = xor(_alloc_way_T_96, alloc_way_chunks_98) node _alloc_way_T_98 = xor(_alloc_way_T_97, alloc_way_chunks_99) node _alloc_way_T_99 = xor(_alloc_way_T_98, alloc_way_chunks_100) node _alloc_way_T_100 = xor(_alloc_way_T_99, alloc_way_chunks_101) node _alloc_way_T_101 = xor(_alloc_way_T_100, alloc_way_chunks_102) node _alloc_way_T_102 = xor(_alloc_way_T_101, alloc_way_chunks_103) node _alloc_way_T_103 = xor(_alloc_way_T_102, alloc_way_chunks_104) node _alloc_way_T_104 = xor(_alloc_way_T_103, alloc_way_chunks_105) node _alloc_way_T_105 = xor(_alloc_way_T_104, alloc_way_chunks_106) node _alloc_way_T_106 = xor(_alloc_way_T_105, alloc_way_chunks_107) node _alloc_way_T_107 = xor(_alloc_way_T_106, alloc_way_chunks_108) node _alloc_way_T_108 = xor(_alloc_way_T_107, alloc_way_chunks_109) node _alloc_way_T_109 = xor(_alloc_way_T_108, alloc_way_chunks_110) node _alloc_way_T_110 = xor(_alloc_way_T_109, alloc_way_chunks_111) node _alloc_way_T_111 = xor(_alloc_way_T_110, alloc_way_chunks_112) node _alloc_way_T_112 = xor(_alloc_way_T_111, alloc_way_chunks_113) node _alloc_way_T_113 = xor(_alloc_way_T_112, alloc_way_chunks_114) node _alloc_way_T_114 = xor(_alloc_way_T_113, alloc_way_chunks_115) node _alloc_way_T_115 = xor(_alloc_way_T_114, alloc_way_chunks_116) node _alloc_way_T_116 = xor(_alloc_way_T_115, alloc_way_chunks_117) node _alloc_way_T_117 = xor(_alloc_way_T_116, alloc_way_chunks_118) node _alloc_way_T_118 = xor(_alloc_way_T_117, alloc_way_chunks_119) node _alloc_way_T_119 = xor(_alloc_way_T_118, alloc_way_chunks_120) node _alloc_way_T_120 = xor(_alloc_way_T_119, alloc_way_chunks_121) node _alloc_way_T_121 = xor(_alloc_way_T_120, alloc_way_chunks_122) node _alloc_way_T_122 = xor(_alloc_way_T_121, alloc_way_chunks_123) node _alloc_way_T_123 = xor(_alloc_way_T_122, alloc_way_chunks_124) node _alloc_way_T_124 = xor(_alloc_way_T_123, alloc_way_chunks_125) node _alloc_way_T_125 = xor(_alloc_way_T_124, alloc_way_chunks_126) node _alloc_way_T_126 = xor(_alloc_way_T_125, alloc_way_chunks_127) node _alloc_way_T_127 = xor(_alloc_way_T_126, alloc_way_chunks_128) node _alloc_way_T_128 = xor(_alloc_way_T_127, alloc_way_chunks_129) node _alloc_way_T_129 = xor(_alloc_way_T_128, alloc_way_chunks_130) node _alloc_way_T_130 = xor(_alloc_way_T_129, alloc_way_chunks_131) node _alloc_way_T_131 = xor(_alloc_way_T_130, alloc_way_chunks_132) node _alloc_way_T_132 = xor(_alloc_way_T_131, alloc_way_chunks_133) node _alloc_way_T_133 = xor(_alloc_way_T_132, alloc_way_chunks_134) node _alloc_way_T_134 = xor(_alloc_way_T_133, alloc_way_chunks_135) node _alloc_way_T_135 = xor(_alloc_way_T_134, alloc_way_chunks_136) node _alloc_way_T_136 = xor(_alloc_way_T_135, alloc_way_chunks_137) node _alloc_way_T_137 = xor(_alloc_way_T_136, alloc_way_chunks_138) node _alloc_way_T_138 = xor(_alloc_way_T_137, alloc_way_chunks_139) node _alloc_way_T_139 = xor(_alloc_way_T_138, alloc_way_chunks_140) node _alloc_way_T_140 = xor(_alloc_way_T_139, alloc_way_chunks_141) node _alloc_way_T_141 = xor(_alloc_way_T_140, alloc_way_chunks_142) node _alloc_way_T_142 = xor(_alloc_way_T_141, alloc_way_chunks_143) node _alloc_way_T_143 = xor(_alloc_way_T_142, alloc_way_chunks_144) node _alloc_way_T_144 = xor(_alloc_way_T_143, alloc_way_chunks_145) node _alloc_way_T_145 = xor(_alloc_way_T_144, alloc_way_chunks_146) node _alloc_way_T_146 = xor(_alloc_way_T_145, alloc_way_chunks_147) node _alloc_way_T_147 = xor(_alloc_way_T_146, alloc_way_chunks_148) node _alloc_way_T_148 = xor(_alloc_way_T_147, alloc_way_chunks_149) node _alloc_way_T_149 = xor(_alloc_way_T_148, alloc_way_chunks_150) node _alloc_way_T_150 = xor(_alloc_way_T_149, alloc_way_chunks_151) node _alloc_way_T_151 = xor(_alloc_way_T_150, alloc_way_chunks_152) node _alloc_way_T_152 = xor(_alloc_way_T_151, alloc_way_chunks_153) node _alloc_way_T_153 = xor(_alloc_way_T_152, alloc_way_chunks_154) node _alloc_way_T_154 = xor(_alloc_way_T_153, alloc_way_chunks_155) node _alloc_way_T_155 = xor(_alloc_way_T_154, alloc_way_chunks_156) node _alloc_way_T_156 = xor(_alloc_way_T_155, alloc_way_chunks_157) node _alloc_way_T_157 = xor(_alloc_way_T_156, alloc_way_chunks_158) node _alloc_way_T_158 = xor(_alloc_way_T_157, alloc_way_chunks_159) node _alloc_way_T_159 = xor(_alloc_way_T_158, alloc_way_chunks_160) node _alloc_way_T_160 = xor(_alloc_way_T_159, alloc_way_chunks_161) node _alloc_way_T_161 = xor(_alloc_way_T_160, alloc_way_chunks_162) node _alloc_way_T_162 = xor(_alloc_way_T_161, alloc_way_chunks_163) node _alloc_way_T_163 = xor(_alloc_way_T_162, alloc_way_chunks_164) node _alloc_way_T_164 = xor(_alloc_way_T_163, alloc_way_chunks_165) node _alloc_way_T_165 = xor(_alloc_way_T_164, alloc_way_chunks_166) node _alloc_way_T_166 = xor(_alloc_way_T_165, alloc_way_chunks_167) node _alloc_way_T_167 = xor(_alloc_way_T_166, alloc_way_chunks_168) node _alloc_way_T_168 = xor(_alloc_way_T_167, alloc_way_chunks_169) node _alloc_way_T_169 = xor(_alloc_way_T_168, alloc_way_chunks_170) node _alloc_way_T_170 = xor(_alloc_way_T_169, alloc_way_chunks_171) node _alloc_way_T_171 = xor(_alloc_way_T_170, alloc_way_chunks_172) node _alloc_way_T_172 = xor(_alloc_way_T_171, alloc_way_chunks_173) node _alloc_way_T_173 = xor(_alloc_way_T_172, alloc_way_chunks_174) node _alloc_way_T_174 = xor(_alloc_way_T_173, alloc_way_chunks_175) node _alloc_way_T_175 = xor(_alloc_way_T_174, alloc_way_chunks_176) node _alloc_way_T_176 = xor(_alloc_way_T_175, alloc_way_chunks_177) node _alloc_way_T_177 = xor(_alloc_way_T_176, alloc_way_chunks_178) node _alloc_way_T_178 = xor(_alloc_way_T_177, alloc_way_chunks_179) node _alloc_way_T_179 = xor(_alloc_way_T_178, alloc_way_chunks_180) node _alloc_way_T_180 = xor(_alloc_way_T_179, alloc_way_chunks_181) node _alloc_way_T_181 = xor(_alloc_way_T_180, alloc_way_chunks_182) node _alloc_way_T_182 = xor(_alloc_way_T_181, alloc_way_chunks_183) node _alloc_way_T_183 = xor(_alloc_way_T_182, alloc_way_chunks_184) node _alloc_way_T_184 = xor(_alloc_way_T_183, alloc_way_chunks_185) node _alloc_way_T_185 = xor(_alloc_way_T_184, alloc_way_chunks_186) node _alloc_way_T_186 = xor(_alloc_way_T_185, alloc_way_chunks_187) node _alloc_way_T_187 = xor(_alloc_way_T_186, alloc_way_chunks_188) node _alloc_way_T_188 = xor(_alloc_way_T_187, alloc_way_chunks_189) node _alloc_way_T_189 = xor(_alloc_way_T_188, alloc_way_chunks_190) node _alloc_way_T_190 = xor(_alloc_way_T_189, alloc_way_chunks_191) node _alloc_way_T_191 = xor(_alloc_way_T_190, alloc_way_chunks_192) node _alloc_way_T_192 = xor(_alloc_way_T_191, alloc_way_chunks_193) node _alloc_way_T_193 = xor(_alloc_way_T_192, alloc_way_chunks_194) node _alloc_way_T_194 = xor(_alloc_way_T_193, alloc_way_chunks_195) node _alloc_way_T_195 = xor(_alloc_way_T_194, alloc_way_chunks_196) node _alloc_way_T_196 = xor(_alloc_way_T_195, alloc_way_chunks_197) node _alloc_way_T_197 = xor(_alloc_way_T_196, alloc_way_chunks_198) node _alloc_way_T_198 = xor(_alloc_way_T_197, alloc_way_chunks_199) node _alloc_way_T_199 = xor(_alloc_way_T_198, alloc_way_chunks_200) node _alloc_way_T_200 = xor(_alloc_way_T_199, alloc_way_chunks_201) node _alloc_way_T_201 = xor(_alloc_way_T_200, alloc_way_chunks_202) node _alloc_way_T_202 = xor(_alloc_way_T_201, alloc_way_chunks_203) node _alloc_way_T_203 = xor(_alloc_way_T_202, alloc_way_chunks_204) node _alloc_way_T_204 = xor(_alloc_way_T_203, alloc_way_chunks_205) node _alloc_way_T_205 = xor(_alloc_way_T_204, alloc_way_chunks_206) node _alloc_way_T_206 = xor(_alloc_way_T_205, alloc_way_chunks_207) node _alloc_way_T_207 = xor(_alloc_way_T_206, alloc_way_chunks_208) node _alloc_way_T_208 = xor(_alloc_way_T_207, alloc_way_chunks_209) node _alloc_way_T_209 = xor(_alloc_way_T_208, alloc_way_chunks_210) node _alloc_way_T_210 = xor(_alloc_way_T_209, alloc_way_chunks_211) node _alloc_way_T_211 = xor(_alloc_way_T_210, alloc_way_chunks_212) node _alloc_way_T_212 = xor(_alloc_way_T_211, alloc_way_chunks_213) node _alloc_way_T_213 = xor(_alloc_way_T_212, alloc_way_chunks_214) node _alloc_way_T_214 = xor(_alloc_way_T_213, alloc_way_chunks_215) node _alloc_way_T_215 = xor(_alloc_way_T_214, alloc_way_chunks_216) node _alloc_way_T_216 = xor(_alloc_way_T_215, alloc_way_chunks_217) node _alloc_way_T_217 = xor(_alloc_way_T_216, alloc_way_chunks_218) node _alloc_way_T_218 = xor(_alloc_way_T_217, alloc_way_chunks_219) node _alloc_way_T_219 = xor(_alloc_way_T_218, alloc_way_chunks_220) node _alloc_way_T_220 = xor(_alloc_way_T_219, alloc_way_chunks_221) node _alloc_way_T_221 = xor(_alloc_way_T_220, alloc_way_chunks_222) node _alloc_way_T_222 = xor(_alloc_way_T_221, alloc_way_chunks_223) node _alloc_way_T_223 = xor(_alloc_way_T_222, alloc_way_chunks_224) node _alloc_way_T_224 = xor(_alloc_way_T_223, alloc_way_chunks_225) node _alloc_way_T_225 = xor(_alloc_way_T_224, alloc_way_chunks_226) node _alloc_way_T_226 = xor(_alloc_way_T_225, alloc_way_chunks_227) node _alloc_way_T_227 = xor(_alloc_way_T_226, alloc_way_chunks_228) node _alloc_way_T_228 = xor(_alloc_way_T_227, alloc_way_chunks_229) node _alloc_way_T_229 = xor(_alloc_way_T_228, alloc_way_chunks_230) node _alloc_way_T_230 = xor(_alloc_way_T_229, alloc_way_chunks_231) node _alloc_way_T_231 = xor(_alloc_way_T_230, alloc_way_chunks_232) node _alloc_way_T_232 = xor(_alloc_way_T_231, alloc_way_chunks_233) node _alloc_way_T_233 = xor(_alloc_way_T_232, alloc_way_chunks_234) node _alloc_way_T_234 = xor(_alloc_way_T_233, alloc_way_chunks_235) node _alloc_way_T_235 = xor(_alloc_way_T_234, alloc_way_chunks_236) node _alloc_way_T_236 = xor(_alloc_way_T_235, alloc_way_chunks_237) node _alloc_way_T_237 = xor(_alloc_way_T_236, alloc_way_chunks_238) node _alloc_way_T_238 = xor(_alloc_way_T_237, alloc_way_chunks_239) node _alloc_way_T_239 = xor(_alloc_way_T_238, alloc_way_chunks_240) node _alloc_way_T_240 = xor(_alloc_way_T_239, alloc_way_chunks_241) node _alloc_way_T_241 = xor(_alloc_way_T_240, alloc_way_chunks_242) node _alloc_way_T_242 = xor(_alloc_way_T_241, alloc_way_chunks_243) node _alloc_way_T_243 = xor(_alloc_way_T_242, alloc_way_chunks_244) node _alloc_way_T_244 = xor(_alloc_way_T_243, alloc_way_chunks_245) node _alloc_way_T_245 = xor(_alloc_way_T_244, alloc_way_chunks_246) node _alloc_way_T_246 = xor(_alloc_way_T_245, alloc_way_chunks_247) node _alloc_way_T_247 = xor(_alloc_way_T_246, alloc_way_chunks_248) node _alloc_way_T_248 = xor(_alloc_way_T_247, alloc_way_chunks_249) node _alloc_way_T_249 = xor(_alloc_way_T_248, alloc_way_chunks_250) node _alloc_way_T_250 = xor(_alloc_way_T_249, alloc_way_chunks_251) node _alloc_way_T_251 = xor(_alloc_way_T_250, alloc_way_chunks_252) node _alloc_way_T_252 = xor(_alloc_way_T_251, alloc_way_chunks_253) node _alloc_way_T_253 = xor(_alloc_way_T_252, alloc_way_chunks_254) node _alloc_way_T_254 = xor(_alloc_way_T_253, alloc_way_chunks_255) node _alloc_way_T_255 = xor(_alloc_way_T_254, alloc_way_chunks_256) node _alloc_way_T_256 = xor(_alloc_way_T_255, alloc_way_chunks_257) node _alloc_way_T_257 = xor(_alloc_way_T_256, alloc_way_chunks_258) node _alloc_way_T_258 = xor(_alloc_way_T_257, alloc_way_chunks_259) node alloc_way = xor(_alloc_way_T_258, alloc_way_chunks_260) node _s1_meta_write_way_T = or(s1_hits_0, s1_hits_1) node _s1_meta_write_way_T_1 = or(_s1_meta_write_way_T, s1_hits_2) node _s1_meta_write_way_T_2 = or(_s1_meta_write_way_T_1, s1_hits_3) node _s1_meta_write_way_T_3 = cat(s1_hit_ohs[0][1], s1_hit_ohs[0][0]) node _s1_meta_write_way_T_4 = cat(s1_hit_ohs[1][1], s1_hit_ohs[1][0]) node _s1_meta_write_way_T_5 = cat(s1_hit_ohs[2][1], s1_hit_ohs[2][0]) node _s1_meta_write_way_T_6 = cat(s1_hit_ohs[3][1], s1_hit_ohs[3][0]) node _s1_meta_write_way_T_7 = or(_s1_meta_write_way_T_3, _s1_meta_write_way_T_4) node _s1_meta_write_way_T_8 = or(_s1_meta_write_way_T_7, _s1_meta_write_way_T_5) node _s1_meta_write_way_T_9 = or(_s1_meta_write_way_T_8, _s1_meta_write_way_T_6) node _s1_meta_write_way_T_10 = bits(_s1_meta_write_way_T_9, 0, 0) node _s1_meta_write_way_T_11 = bits(_s1_meta_write_way_T_9, 1, 1) node _s1_meta_write_way_T_12 = mux(_s1_meta_write_way_T_10, UInt<1>(0h0), UInt<1>(0h1)) node _s1_meta_write_way_T_13 = mux(_s1_meta_write_way_T_2, _s1_meta_write_way_T_12, alloc_way) connect s1_meta.write_way, _s1_meta_write_way_T_13 wire s1_update_meta : { write_way : UInt<1>} wire _s1_update_meta_WIRE : UInt<1> connect _s1_update_meta_WIRE, s1_update.bits.meta node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 0, 0) connect s1_update_meta.write_way, _s1_update_meta_T node _max_offset_value_T = not(UInt<12>(0h0)) node _max_offset_value_T_1 = cat(UInt<1>(0h0), _max_offset_value_T) node max_offset_value = asSInt(_max_offset_value_T_1) node _min_offset_value_T = cat(UInt<1>(0h1), UInt<12>(0h0)) node min_offset_value = asSInt(_min_offset_value_T) node _new_offset_value_T = asSInt(s1_update.bits.target) node _new_offset_value_T_1 = shl(s1_update.bits.cfi_idx.bits, 1) node _new_offset_value_T_2 = add(s1_update.bits.pc, _new_offset_value_T_1) node _new_offset_value_T_3 = tail(_new_offset_value_T_2, 1) node _new_offset_value_T_4 = asSInt(_new_offset_value_T_3) node _new_offset_value_T_5 = sub(_new_offset_value_T, _new_offset_value_T_4) node _new_offset_value_T_6 = tail(_new_offset_value_T_5, 1) node new_offset_value = asSInt(_new_offset_value_T_6) node _offset_is_extended_T = gt(new_offset_value, max_offset_value) node _offset_is_extended_T_1 = lt(new_offset_value, min_offset_value) node offset_is_extended = or(_offset_is_extended_T, _offset_is_extended_T_1) wire s1_update_wbtb_data : { offset : SInt<13>, extended : UInt<1>} connect s1_update_wbtb_data.extended, offset_is_extended connect s1_update_wbtb_data.offset, new_offset_value node _s1_update_wbtb_mask_T = dshl(UInt<1>(0h1), s1_update.bits.cfi_idx.bits) node _s1_update_wbtb_mask_T_1 = and(s1_update.bits.cfi_idx.valid, s1_update.valid) node _s1_update_wbtb_mask_T_2 = and(_s1_update_wbtb_mask_T_1, s1_update.bits.cfi_taken) node _s1_update_wbtb_mask_T_3 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _s1_update_wbtb_mask_T_4 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _s1_update_wbtb_mask_T_5 = or(_s1_update_wbtb_mask_T_3, _s1_update_wbtb_mask_T_4) node _s1_update_wbtb_mask_T_6 = eq(_s1_update_wbtb_mask_T_5, UInt<1>(0h0)) node _s1_update_wbtb_mask_T_7 = and(_s1_update_wbtb_mask_T_2, _s1_update_wbtb_mask_T_6) node _s1_update_wbtb_mask_T_8 = mux(_s1_update_wbtb_mask_T_7, UInt<4>(0hf), UInt<4>(0h0)) node s1_update_wbtb_mask = and(_s1_update_wbtb_mask_T, _s1_update_wbtb_mask_T_8) node _s1_update_wmeta_mask_T = or(s1_update_wbtb_mask, s1_update.bits.br_mask) node _s1_update_wmeta_mask_T_1 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _s1_update_wmeta_mask_T_2 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _s1_update_wmeta_mask_T_3 = or(_s1_update_wmeta_mask_T_1, _s1_update_wmeta_mask_T_2) node _s1_update_wmeta_mask_T_4 = eq(_s1_update_wmeta_mask_T_3, UInt<1>(0h0)) node _s1_update_wmeta_mask_T_5 = and(s1_update.valid, _s1_update_wmeta_mask_T_4) node _s1_update_wmeta_mask_T_6 = mux(_s1_update_wmeta_mask_T_5, UInt<4>(0hf), UInt<4>(0h0)) node _s1_update_wmeta_mask_T_7 = mux(s1_update.valid, UInt<4>(0hf), UInt<4>(0h0)) node _s1_update_wmeta_mask_T_8 = and(_s1_update_wmeta_mask_T_7, s1_update.bits.btb_mispredicts) node _s1_update_wmeta_mask_T_9 = or(_s1_update_wmeta_mask_T_6, _s1_update_wmeta_mask_T_8) node s1_update_wmeta_mask = and(_s1_update_wmeta_mask_T, _s1_update_wmeta_mask_T_9) wire s1_update_wmeta_data : { is_br : UInt<1>, tag : UInt<29>}[4] node _s1_update_wmeta_data_0_tag_T = bits(s1_update.bits.btb_mispredicts, 0, 0) node _s1_update_wmeta_data_0_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_0_tag_T_2 = mux(_s1_update_wmeta_data_0_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_0_tag_T_1) connect s1_update_wmeta_data[0].tag, _s1_update_wmeta_data_0_tag_T_2 node _s1_update_wmeta_data_0_is_br_T = bits(s1_update.bits.br_mask, 0, 0) connect s1_update_wmeta_data[0].is_br, _s1_update_wmeta_data_0_is_br_T node _s1_update_wmeta_data_1_tag_T = bits(s1_update.bits.btb_mispredicts, 1, 1) node _s1_update_wmeta_data_1_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_1_tag_T_2 = mux(_s1_update_wmeta_data_1_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_1_tag_T_1) connect s1_update_wmeta_data[1].tag, _s1_update_wmeta_data_1_tag_T_2 node _s1_update_wmeta_data_1_is_br_T = bits(s1_update.bits.br_mask, 1, 1) connect s1_update_wmeta_data[1].is_br, _s1_update_wmeta_data_1_is_br_T node _s1_update_wmeta_data_2_tag_T = bits(s1_update.bits.btb_mispredicts, 2, 2) node _s1_update_wmeta_data_2_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_2_tag_T_2 = mux(_s1_update_wmeta_data_2_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_2_tag_T_1) connect s1_update_wmeta_data[2].tag, _s1_update_wmeta_data_2_tag_T_2 node _s1_update_wmeta_data_2_is_br_T = bits(s1_update.bits.br_mask, 2, 2) connect s1_update_wmeta_data[2].is_br, _s1_update_wmeta_data_2_is_br_T node _s1_update_wmeta_data_3_tag_T = bits(s1_update.bits.btb_mispredicts, 3, 3) node _s1_update_wmeta_data_3_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_3_tag_T_2 = mux(_s1_update_wmeta_data_3_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_3_tag_T_1) connect s1_update_wmeta_data[3].tag, _s1_update_wmeta_data_3_tag_T_2 node _s1_update_wmeta_data_3_is_br_T = bits(s1_update.bits.br_mask, 3, 3) connect s1_update_wmeta_data[3].is_br, _s1_update_wmeta_data_3_is_br_T node _T_1 = eq(s1_update_meta.write_way, UInt<1>(0h0)) node _T_2 = or(doing_reset, _T_1) node _T_3 = or(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE : UInt<14>[4] connect _WIRE[0], UInt<14>(0h0) connect _WIRE[1], UInt<14>(0h0) connect _WIRE[2], UInt<14>(0h0) connect _WIRE[3], UInt<14>(0h0) node _T_5 = asUInt(s1_update_wbtb_data.offset) node _T_6 = cat(_T_5, s1_update_wbtb_data.extended) node _T_7 = asUInt(s1_update_wbtb_data.offset) node _T_8 = cat(_T_7, s1_update_wbtb_data.extended) node _T_9 = asUInt(s1_update_wbtb_data.offset) node _T_10 = cat(_T_9, s1_update_wbtb_data.extended) node _T_11 = asUInt(s1_update_wbtb_data.offset) node _T_12 = cat(_T_11, s1_update_wbtb_data.extended) wire _WIRE_1 : UInt<14>[4] connect _WIRE_1[0], _T_6 connect _WIRE_1[1], _T_8 connect _WIRE_1[2], _T_10 connect _WIRE_1[3], _T_12 node _T_13 = mux(doing_reset, _WIRE, _WIRE_1) node _T_14 = not(UInt<4>(0h0)) node _T_15 = mux(doing_reset, _T_14, s1_update_wbtb_mask) node _T_16 = bits(_T_15, 0, 0) node _T_17 = bits(_T_15, 1, 1) node _T_18 = bits(_T_15, 2, 2) node _T_19 = bits(_T_15, 3, 3) node _T_20 = or(_T_4, UInt<7>(0h0)) node _T_21 = bits(_T_20, 6, 0) write mport MPORT = btb_0[_T_21], clock when _T_16 : connect MPORT[0], _T_13[0] when _T_17 : connect MPORT[1], _T_13[1] when _T_18 : connect MPORT[2], _T_13[2] when _T_19 : connect MPORT[3], _T_13[3] node _T_22 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_2 : UInt<30>[4] connect _WIRE_2[0], UInt<30>(0h0) connect _WIRE_2[1], UInt<30>(0h0) connect _WIRE_2[2], UInt<30>(0h0) connect _WIRE_2[3], UInt<30>(0h0) node _T_23 = cat(s1_update_wmeta_data[0].is_br, s1_update_wmeta_data[0].tag) node _T_24 = cat(s1_update_wmeta_data[1].is_br, s1_update_wmeta_data[1].tag) node _T_25 = cat(s1_update_wmeta_data[2].is_br, s1_update_wmeta_data[2].tag) node _T_26 = cat(s1_update_wmeta_data[3].is_br, s1_update_wmeta_data[3].tag) wire _WIRE_3 : UInt<30>[4] connect _WIRE_3[0], _T_23 connect _WIRE_3[1], _T_24 connect _WIRE_3[2], _T_25 connect _WIRE_3[3], _T_26 node _T_27 = mux(doing_reset, _WIRE_2, _WIRE_3) node _T_28 = not(UInt<4>(0h0)) node _T_29 = mux(doing_reset, _T_28, s1_update_wmeta_mask) node _T_30 = bits(_T_29, 0, 0) node _T_31 = bits(_T_29, 1, 1) node _T_32 = bits(_T_29, 2, 2) node _T_33 = bits(_T_29, 3, 3) node _T_34 = or(_T_22, UInt<7>(0h0)) node _T_35 = bits(_T_34, 6, 0) write mport MPORT_1 = meta_0[_T_35], clock when _T_30 : connect MPORT_1[0], _T_27[0] when _T_31 : connect MPORT_1[1], _T_27[1] when _T_32 : connect MPORT_1[2], _T_27[2] when _T_33 : connect MPORT_1[3], _T_27[3] node _T_36 = eq(s1_update_meta.write_way, UInt<1>(0h1)) node _T_37 = or(doing_reset, _T_36) node _T_38 = or(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_4 : UInt<14>[4] connect _WIRE_4[0], UInt<14>(0h0) connect _WIRE_4[1], UInt<14>(0h0) connect _WIRE_4[2], UInt<14>(0h0) connect _WIRE_4[3], UInt<14>(0h0) node _T_40 = asUInt(s1_update_wbtb_data.offset) node _T_41 = cat(_T_40, s1_update_wbtb_data.extended) node _T_42 = asUInt(s1_update_wbtb_data.offset) node _T_43 = cat(_T_42, s1_update_wbtb_data.extended) node _T_44 = asUInt(s1_update_wbtb_data.offset) node _T_45 = cat(_T_44, s1_update_wbtb_data.extended) node _T_46 = asUInt(s1_update_wbtb_data.offset) node _T_47 = cat(_T_46, s1_update_wbtb_data.extended) wire _WIRE_5 : UInt<14>[4] connect _WIRE_5[0], _T_41 connect _WIRE_5[1], _T_43 connect _WIRE_5[2], _T_45 connect _WIRE_5[3], _T_47 node _T_48 = mux(doing_reset, _WIRE_4, _WIRE_5) node _T_49 = not(UInt<4>(0h0)) node _T_50 = mux(doing_reset, _T_49, s1_update_wbtb_mask) node _T_51 = bits(_T_50, 0, 0) node _T_52 = bits(_T_50, 1, 1) node _T_53 = bits(_T_50, 2, 2) node _T_54 = bits(_T_50, 3, 3) node _T_55 = or(_T_39, UInt<7>(0h0)) node _T_56 = bits(_T_55, 6, 0) write mport MPORT_2 = btb_1[_T_56], clock when _T_51 : connect MPORT_2[0], _T_48[0] when _T_52 : connect MPORT_2[1], _T_48[1] when _T_53 : connect MPORT_2[2], _T_48[2] when _T_54 : connect MPORT_2[3], _T_48[3] node _T_57 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_6 : UInt<30>[4] connect _WIRE_6[0], UInt<30>(0h0) connect _WIRE_6[1], UInt<30>(0h0) connect _WIRE_6[2], UInt<30>(0h0) connect _WIRE_6[3], UInt<30>(0h0) node _T_58 = cat(s1_update_wmeta_data[0].is_br, s1_update_wmeta_data[0].tag) node _T_59 = cat(s1_update_wmeta_data[1].is_br, s1_update_wmeta_data[1].tag) node _T_60 = cat(s1_update_wmeta_data[2].is_br, s1_update_wmeta_data[2].tag) node _T_61 = cat(s1_update_wmeta_data[3].is_br, s1_update_wmeta_data[3].tag) wire _WIRE_7 : UInt<30>[4] connect _WIRE_7[0], _T_58 connect _WIRE_7[1], _T_59 connect _WIRE_7[2], _T_60 connect _WIRE_7[3], _T_61 node _T_62 = mux(doing_reset, _WIRE_6, _WIRE_7) node _T_63 = not(UInt<4>(0h0)) node _T_64 = mux(doing_reset, _T_63, s1_update_wmeta_mask) node _T_65 = bits(_T_64, 0, 0) node _T_66 = bits(_T_64, 1, 1) node _T_67 = bits(_T_64, 2, 2) node _T_68 = bits(_T_64, 3, 3) node _T_69 = or(_T_57, UInt<7>(0h0)) node _T_70 = bits(_T_69, 6, 0) write mport MPORT_3 = meta_1[_T_70], clock when _T_65 : connect MPORT_3[0], _T_62[0] when _T_66 : connect MPORT_3[1], _T_62[1] when _T_67 : connect MPORT_3[2], _T_62[2] when _T_68 : connect MPORT_3[3], _T_62[3] node _T_71 = neq(s1_update_wbtb_mask, UInt<1>(0h0)) node _T_72 = and(_T_71, offset_is_extended) when _T_72 : node _T_73 = or(s1_update_idx, UInt<7>(0h0)) node _T_74 = bits(_T_73, 6, 0) write mport MPORT_4 = ebtb[_T_74], clock connect MPORT_4, s1_update.bits.target
module BTBBranchPredictorBank_3( // @[btb.scala:23:7] input clock, // @[btb.scala:23:7] input reset, // @[btb.scala:23:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire [29:0] meta_1_MPORT_3_data_3; // @[btb.scala:183:12] wire [29:0] meta_1_MPORT_3_data_2; // @[btb.scala:183:12] wire [29:0] meta_1_MPORT_3_data_1; // @[btb.scala:183:12] wire [29:0] meta_1_MPORT_3_data_0; // @[btb.scala:183:12] wire [13:0] btb_1_MPORT_2_data_3; // @[btb.scala:172:12] wire [13:0] btb_1_MPORT_2_data_2; // @[btb.scala:172:12] wire [13:0] btb_1_MPORT_2_data_1; // @[btb.scala:172:12] wire [13:0] btb_1_MPORT_2_data_0; // @[btb.scala:172:12] wire [29:0] meta_0_MPORT_1_data_3; // @[btb.scala:183:12] wire [29:0] meta_0_MPORT_1_data_2; // @[btb.scala:183:12] wire [29:0] meta_0_MPORT_1_data_1; // @[btb.scala:183:12] wire [29:0] meta_0_MPORT_1_data_0; // @[btb.scala:183:12] wire [13:0] btb_0_MPORT_data_3; // @[btb.scala:172:12] wire [13:0] btb_0_MPORT_data_2; // @[btb.scala:172:12] wire [13:0] btb_0_MPORT_data_1; // @[btb.scala:172:12] wire [13:0] btb_0_MPORT_data_0; // @[btb.scala:172:12] wire _s1_update_meta_WIRE; // @[btb.scala:138:55] wire _s1_req_rmeta_WIRE_17_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_17_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_15_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_15_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_13_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_13_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_11_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_11_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_7_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_7_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_5_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_5_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_3_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_3_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_1_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_1_tag; // @[btb.scala:74:93] wire [12:0] _s1_req_rbtb_WIRE_17_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_17_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_15_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_15_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_13_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_13_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_11_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_11_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_7_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_7_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_5_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_5_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_3_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_3_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_1_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_1_extended; // @[btb.scala:73:93] wire [39:0] _ebtb_R0_data; // @[btb.scala:67:29] wire [55:0] _btb_1_R0_data; // @[btb.scala:66:47] wire [55:0] _btb_0_R0_data; // @[btb.scala:66:47] wire [119:0] _meta_1_R0_data; // @[btb.scala:65:47] wire [119:0] _meta_0_R0_data; // @[btb.scala:65:47] wire io_f0_valid_0 = io_f0_valid; // @[btb.scala:23:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[btb.scala:23:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[btb.scala:23:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[btb.scala:23:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[btb.scala:23:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[btb.scala:23:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[btb.scala:23:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[btb.scala:23:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[btb.scala:23:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[btb.scala:23:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[btb.scala:23:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[btb.scala:23:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[btb.scala:23:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[btb.scala:23:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[btb.scala:23:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[btb.scala:23:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[btb.scala:23:7] wire io_f3_fire_0 = io_f3_fire; // @[btb.scala:23:7] wire io_update_valid_0 = io_update_valid; // @[btb.scala:23:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[btb.scala:23:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[btb.scala:23:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[btb.scala:23:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[btb.scala:23:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[btb.scala:23:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[btb.scala:23:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[btb.scala:23:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[btb.scala:23:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[btb.scala:23:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[btb.scala:23:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[btb.scala:23:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[btb.scala:23:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[btb.scala:23:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[btb.scala:23:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[btb.scala:23:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[btb.scala:23:7] wire [11:0] _max_offset_value_T = 12'hFFF; // @[btb.scala:140:35] wire [12:0] _max_offset_value_T_1 = 13'hFFF; // @[btb.scala:140:{29,59}] wire [12:0] max_offset_value = 13'hFFF; // @[btb.scala:140:59] wire [12:0] _min_offset_value_T = 13'h1000; // @[btb.scala:141:{29,59}] wire [12:0] min_offset_value = 13'h1000; // @[btb.scala:141:59] wire io_f1_lhist = 1'h0; // @[btb.scala:23:7] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[btb.scala:23:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[btb.scala:23:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[btb.scala:23:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[btb.scala:23:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[btb.scala:23:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[btb.scala:23:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[btb.scala:23:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[btb.scala:23:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[btb.scala:23:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[btb.scala:23:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[btb.scala:23:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[btb.scala:23:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f2_0_taken_0; // @[btb.scala:23:7] wire io_resp_f2_0_is_br_0; // @[btb.scala:23:7] wire io_resp_f2_0_is_jal_0; // @[btb.scala:23:7] wire io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f2_1_taken_0; // @[btb.scala:23:7] wire io_resp_f2_1_is_br_0; // @[btb.scala:23:7] wire io_resp_f2_1_is_jal_0; // @[btb.scala:23:7] wire io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f2_2_taken_0; // @[btb.scala:23:7] wire io_resp_f2_2_is_br_0; // @[btb.scala:23:7] wire io_resp_f2_2_is_jal_0; // @[btb.scala:23:7] wire io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f2_3_taken_0; // @[btb.scala:23:7] wire io_resp_f2_3_is_br_0; // @[btb.scala:23:7] wire io_resp_f2_3_is_jal_0; // @[btb.scala:23:7] wire io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f3_0_taken_0; // @[btb.scala:23:7] wire io_resp_f3_0_is_br_0; // @[btb.scala:23:7] wire io_resp_f3_0_is_jal_0; // @[btb.scala:23:7] wire io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f3_1_taken_0; // @[btb.scala:23:7] wire io_resp_f3_1_is_br_0; // @[btb.scala:23:7] wire io_resp_f3_1_is_jal_0; // @[btb.scala:23:7] wire io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f3_2_taken_0; // @[btb.scala:23:7] wire io_resp_f3_2_is_br_0; // @[btb.scala:23:7] wire io_resp_f3_2_is_jal_0; // @[btb.scala:23:7] wire io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f3_3_taken_0; // @[btb.scala:23:7] wire io_resp_f3_3_is_br_0; // @[btb.scala:23:7] wire io_resp_f3_3_is_jal_0; // @[btb.scala:23:7] wire [119:0] io_f3_meta_0; // @[btb.scala:23:7] wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35] wire [35:0] _s1_req_rbtb_WIRE = s0_idx; // @[frontend.scala:162:35] wire [35:0] _s1_req_rbtb_WIRE_10 = s0_idx; // @[frontend.scala:162:35] wire [35:0] _s1_req_rmeta_WIRE = s0_idx; // @[frontend.scala:162:35] wire [35:0] _s1_req_rmeta_WIRE_10 = s0_idx; // @[frontend.scala:162:35] wire [35:0] _s1_req_rebtb_WIRE = s0_idx; // @[frontend.scala:162:35] reg [35:0] s1_idx; // @[predictor.scala:163:29] reg [35:0] s2_idx; // @[predictor.scala:164:29] reg [35:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_resp_0_bits_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_resp_1_bits_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_resp_2_bits_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_resp_3_bits_T = s1_pc; // @[predictor.scala:178:22] wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] wire [39:0] _new_offset_value_T = s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [35:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] wire _s1_meta_write_way_T_13; // @[btb.scala:133:27] wire s1_meta_write_way; // @[btb.scala:52:21] reg f3_meta_REG_write_way; // @[btb.scala:53:32] reg f3_meta_write_way; // @[btb.scala:53:24] assign io_f3_meta_0 = {119'h0, f3_meta_write_way}; // @[btb.scala:23:7, :53:24, :56:14] reg doing_reset; // @[btb.scala:60:28] reg [6:0] reset_idx; // @[btb.scala:61:28] wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[btb.scala:60:28, :61:28, :62:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[btb.scala:62:26] wire [29:0] _s1_req_rmeta_WIRE_2 = _meta_0_R0_data[29:0]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_4 = _meta_0_R0_data[59:30]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_6 = _meta_0_R0_data[89:60]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_8 = _meta_0_R0_data[119:90]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_12 = _meta_1_R0_data[29:0]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_14 = _meta_1_R0_data[59:30]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_16 = _meta_1_R0_data[89:60]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_18 = _meta_1_R0_data[119:90]; // @[btb.scala:65:47, :74:93] wire [13:0] _s1_req_rbtb_WIRE_2 = _btb_0_R0_data[13:0]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_4 = _btb_0_R0_data[27:14]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_6 = _btb_0_R0_data[41:28]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_8 = _btb_0_R0_data[55:42]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_12 = _btb_1_R0_data[13:0]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_14 = _btb_1_R0_data[27:14]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_16 = _btb_1_R0_data[41:28]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_18 = _btb_1_R0_data[55:42]; // @[btb.scala:66:47, :73:93] wire [6:0] _s1_req_rbtb_T = _s1_req_rbtb_WIRE[6:0]; // @[btb.scala:73:59] wire [12:0] _s1_req_rbtb_T_3; // @[btb.scala:73:93] wire _s1_req_rbtb_T_1; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_9_0_offset = _s1_req_rbtb_WIRE_1_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_9_0_extended = _s1_req_rbtb_WIRE_1_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_1 = _s1_req_rbtb_WIRE_2[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_1_extended = _s1_req_rbtb_T_1; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_2 = _s1_req_rbtb_WIRE_2[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_3 = _s1_req_rbtb_T_2; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_1_offset = _s1_req_rbtb_T_3; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_6; // @[btb.scala:73:93] wire _s1_req_rbtb_T_4; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_9_1_offset = _s1_req_rbtb_WIRE_3_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_9_1_extended = _s1_req_rbtb_WIRE_3_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_4 = _s1_req_rbtb_WIRE_4[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_3_extended = _s1_req_rbtb_T_4; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_5 = _s1_req_rbtb_WIRE_4[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_6 = _s1_req_rbtb_T_5; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_3_offset = _s1_req_rbtb_T_6; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_9; // @[btb.scala:73:93] wire _s1_req_rbtb_T_7; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_9_2_offset = _s1_req_rbtb_WIRE_5_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_9_2_extended = _s1_req_rbtb_WIRE_5_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_7 = _s1_req_rbtb_WIRE_6[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_5_extended = _s1_req_rbtb_T_7; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_8 = _s1_req_rbtb_WIRE_6[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_9 = _s1_req_rbtb_T_8; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_5_offset = _s1_req_rbtb_T_9; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_12; // @[btb.scala:73:93] wire _s1_req_rbtb_T_10; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_9_3_offset = _s1_req_rbtb_WIRE_7_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_9_3_extended = _s1_req_rbtb_WIRE_7_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_10 = _s1_req_rbtb_WIRE_8[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_7_extended = _s1_req_rbtb_T_10; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_11 = _s1_req_rbtb_WIRE_8[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_12 = _s1_req_rbtb_T_11; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_7_offset = _s1_req_rbtb_T_12; // @[btb.scala:73:93] wire [12:0] s1_req_rbtb_0_0_offset = _s1_req_rbtb_WIRE_9_0_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_0_0_extended = _s1_req_rbtb_WIRE_9_0_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_0_1_offset = _s1_req_rbtb_WIRE_9_1_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_0_1_extended = _s1_req_rbtb_WIRE_9_1_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_0_2_offset = _s1_req_rbtb_WIRE_9_2_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_0_2_extended = _s1_req_rbtb_WIRE_9_2_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_0_3_offset = _s1_req_rbtb_WIRE_9_3_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_0_3_extended = _s1_req_rbtb_WIRE_9_3_extended; // @[btb.scala:73:{29,52}] wire [6:0] _s1_req_rbtb_T_13 = _s1_req_rbtb_WIRE_10[6:0]; // @[btb.scala:73:59] wire [12:0] _s1_req_rbtb_T_16; // @[btb.scala:73:93] wire _s1_req_rbtb_T_14; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_19_0_offset = _s1_req_rbtb_WIRE_11_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_19_0_extended = _s1_req_rbtb_WIRE_11_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_14 = _s1_req_rbtb_WIRE_12[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_11_extended = _s1_req_rbtb_T_14; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_15 = _s1_req_rbtb_WIRE_12[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_16 = _s1_req_rbtb_T_15; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_11_offset = _s1_req_rbtb_T_16; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_19; // @[btb.scala:73:93] wire _s1_req_rbtb_T_17; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_19_1_offset = _s1_req_rbtb_WIRE_13_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_19_1_extended = _s1_req_rbtb_WIRE_13_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_17 = _s1_req_rbtb_WIRE_14[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_13_extended = _s1_req_rbtb_T_17; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_18 = _s1_req_rbtb_WIRE_14[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_19 = _s1_req_rbtb_T_18; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_13_offset = _s1_req_rbtb_T_19; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_22; // @[btb.scala:73:93] wire _s1_req_rbtb_T_20; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_19_2_offset = _s1_req_rbtb_WIRE_15_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_19_2_extended = _s1_req_rbtb_WIRE_15_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_20 = _s1_req_rbtb_WIRE_16[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_15_extended = _s1_req_rbtb_T_20; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_21 = _s1_req_rbtb_WIRE_16[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_22 = _s1_req_rbtb_T_21; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_15_offset = _s1_req_rbtb_T_22; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_25; // @[btb.scala:73:93] wire _s1_req_rbtb_T_23; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_19_3_offset = _s1_req_rbtb_WIRE_17_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_19_3_extended = _s1_req_rbtb_WIRE_17_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_23 = _s1_req_rbtb_WIRE_18[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_17_extended = _s1_req_rbtb_T_23; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_24 = _s1_req_rbtb_WIRE_18[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_25 = _s1_req_rbtb_T_24; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_17_offset = _s1_req_rbtb_T_25; // @[btb.scala:73:93] wire [12:0] s1_req_rbtb_1_0_offset = _s1_req_rbtb_WIRE_19_0_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_1_0_extended = _s1_req_rbtb_WIRE_19_0_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_1_1_offset = _s1_req_rbtb_WIRE_19_1_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_1_1_extended = _s1_req_rbtb_WIRE_19_1_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_1_2_offset = _s1_req_rbtb_WIRE_19_2_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_1_2_extended = _s1_req_rbtb_WIRE_19_2_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_1_3_offset = _s1_req_rbtb_WIRE_19_3_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_1_3_extended = _s1_req_rbtb_WIRE_19_3_extended; // @[btb.scala:73:{29,52}] wire [6:0] _s1_req_rmeta_T = _s1_req_rmeta_WIRE[6:0]; // @[btb.scala:74:60] wire _s1_req_rmeta_T_2; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_1; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_9_0_is_br = _s1_req_rmeta_WIRE_1_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_9_0_tag = _s1_req_rmeta_WIRE_1_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_1 = _s1_req_rmeta_WIRE_2[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_1_tag = _s1_req_rmeta_T_1; // @[btb.scala:74:93] assign _s1_req_rmeta_T_2 = _s1_req_rmeta_WIRE_2[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_1_is_br = _s1_req_rmeta_T_2; // @[btb.scala:74:93] wire _s1_req_rmeta_T_4; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_3; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_9_1_is_br = _s1_req_rmeta_WIRE_3_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_9_1_tag = _s1_req_rmeta_WIRE_3_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_3 = _s1_req_rmeta_WIRE_4[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_3_tag = _s1_req_rmeta_T_3; // @[btb.scala:74:93] assign _s1_req_rmeta_T_4 = _s1_req_rmeta_WIRE_4[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_3_is_br = _s1_req_rmeta_T_4; // @[btb.scala:74:93] wire _s1_req_rmeta_T_6; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_5; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_9_2_is_br = _s1_req_rmeta_WIRE_5_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_9_2_tag = _s1_req_rmeta_WIRE_5_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_5 = _s1_req_rmeta_WIRE_6[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_5_tag = _s1_req_rmeta_T_5; // @[btb.scala:74:93] assign _s1_req_rmeta_T_6 = _s1_req_rmeta_WIRE_6[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_5_is_br = _s1_req_rmeta_T_6; // @[btb.scala:74:93] wire _s1_req_rmeta_T_8; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_7; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_9_3_is_br = _s1_req_rmeta_WIRE_7_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_9_3_tag = _s1_req_rmeta_WIRE_7_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_7 = _s1_req_rmeta_WIRE_8[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_7_tag = _s1_req_rmeta_T_7; // @[btb.scala:74:93] assign _s1_req_rmeta_T_8 = _s1_req_rmeta_WIRE_8[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_7_is_br = _s1_req_rmeta_T_8; // @[btb.scala:74:93] wire s1_req_rmeta_0_0_is_br = _s1_req_rmeta_WIRE_9_0_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_0_0_tag = _s1_req_rmeta_WIRE_9_0_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_0_1_is_br = _s1_req_rmeta_WIRE_9_1_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_0_1_tag = _s1_req_rmeta_WIRE_9_1_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_0_2_is_br = _s1_req_rmeta_WIRE_9_2_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_0_2_tag = _s1_req_rmeta_WIRE_9_2_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_0_3_is_br = _s1_req_rmeta_WIRE_9_3_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_0_3_tag = _s1_req_rmeta_WIRE_9_3_tag; // @[btb.scala:74:{29,53}] wire [6:0] _s1_req_rmeta_T_9 = _s1_req_rmeta_WIRE_10[6:0]; // @[btb.scala:74:60] wire _s1_req_rmeta_T_11; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_10; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_19_0_is_br = _s1_req_rmeta_WIRE_11_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_19_0_tag = _s1_req_rmeta_WIRE_11_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_10 = _s1_req_rmeta_WIRE_12[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_11_tag = _s1_req_rmeta_T_10; // @[btb.scala:74:93] assign _s1_req_rmeta_T_11 = _s1_req_rmeta_WIRE_12[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_11_is_br = _s1_req_rmeta_T_11; // @[btb.scala:74:93] wire _s1_req_rmeta_T_13; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_12; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_19_1_is_br = _s1_req_rmeta_WIRE_13_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_19_1_tag = _s1_req_rmeta_WIRE_13_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_12 = _s1_req_rmeta_WIRE_14[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_13_tag = _s1_req_rmeta_T_12; // @[btb.scala:74:93] assign _s1_req_rmeta_T_13 = _s1_req_rmeta_WIRE_14[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_13_is_br = _s1_req_rmeta_T_13; // @[btb.scala:74:93] wire _s1_req_rmeta_T_15; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_14; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_19_2_is_br = _s1_req_rmeta_WIRE_15_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_19_2_tag = _s1_req_rmeta_WIRE_15_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_14 = _s1_req_rmeta_WIRE_16[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_15_tag = _s1_req_rmeta_T_14; // @[btb.scala:74:93] assign _s1_req_rmeta_T_15 = _s1_req_rmeta_WIRE_16[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_15_is_br = _s1_req_rmeta_T_15; // @[btb.scala:74:93] wire _s1_req_rmeta_T_17; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_16; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_19_3_is_br = _s1_req_rmeta_WIRE_17_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_19_3_tag = _s1_req_rmeta_WIRE_17_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_16 = _s1_req_rmeta_WIRE_18[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_17_tag = _s1_req_rmeta_T_16; // @[btb.scala:74:93] assign _s1_req_rmeta_T_17 = _s1_req_rmeta_WIRE_18[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_17_is_br = _s1_req_rmeta_T_17; // @[btb.scala:74:93] wire s1_req_rmeta_1_0_is_br = _s1_req_rmeta_WIRE_19_0_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_1_0_tag = _s1_req_rmeta_WIRE_19_0_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_1_1_is_br = _s1_req_rmeta_WIRE_19_1_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_1_1_tag = _s1_req_rmeta_WIRE_19_1_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_1_2_is_br = _s1_req_rmeta_WIRE_19_2_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_1_2_tag = _s1_req_rmeta_WIRE_19_2_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_1_3_is_br = _s1_req_rmeta_WIRE_19_3_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_1_3_tag = _s1_req_rmeta_WIRE_19_3_tag; // @[btb.scala:74:{29,53}] wire [28:0] _alloc_way_r_metas_WIRE_0 = s1_req_rmeta_0_0_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_1 = s1_req_rmeta_0_1_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_2 = s1_req_rmeta_0_2_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_3 = s1_req_rmeta_0_3_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_1_0 = s1_req_rmeta_1_0_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_1_1 = s1_req_rmeta_1_1_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_1_2 = s1_req_rmeta_1_2_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_1_3 = s1_req_rmeta_1_3_tag; // @[btb.scala:74:29, :123:62] wire [6:0] _s1_req_rebtb_T = _s1_req_rebtb_WIRE[6:0]; // @[btb.scala:75:31] wire [28:0] s1_req_tag = s1_idx[35:7]; // @[predictor.scala:163:29] wire [28:0] _s1_hit_ohs_T = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_2 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_4 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_6 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_8 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_10 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_12 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_14 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _alloc_way_r_metas_T_3 = s1_req_tag; // @[btb.scala:76:29, :123:98] wire _s1_resp_0_valid_T_2; // @[btb.scala:93:50] wire [39:0] _s1_resp_0_bits_T_8; // @[btb.scala:94:28] wire _s1_resp_1_valid_T_2; // @[btb.scala:93:50] wire [39:0] _s1_resp_1_bits_T_8; // @[btb.scala:94:28] wire _s1_resp_2_valid_T_2; // @[btb.scala:93:50] wire [39:0] _s1_resp_2_bits_T_8; // @[btb.scala:94:28] wire _s1_resp_3_valid_T_2; // @[btb.scala:93:50] wire [39:0] _s1_resp_3_bits_T_8; // @[btb.scala:94:28] wire s1_resp_0_valid; // @[btb.scala:78:23] wire [39:0] s1_resp_0_bits; // @[btb.scala:78:23] wire s1_resp_1_valid; // @[btb.scala:78:23] wire [39:0] s1_resp_1_bits; // @[btb.scala:78:23] wire s1_resp_2_valid; // @[btb.scala:78:23] wire [39:0] s1_resp_2_bits; // @[btb.scala:78:23] wire s1_resp_3_valid; // @[btb.scala:78:23] wire [39:0] s1_resp_3_bits; // @[btb.scala:78:23] wire _s1_is_br_0_T_2; // @[btb.scala:98:54] wire _s1_is_br_1_T_2; // @[btb.scala:98:54] wire _s1_is_br_2_T_2; // @[btb.scala:98:54] wire _s1_is_br_3_T_2; // @[btb.scala:98:54] wire s1_is_br_0; // @[btb.scala:79:23] wire s1_is_br_1; // @[btb.scala:79:23] wire s1_is_br_2; // @[btb.scala:79:23] wire s1_is_br_3; // @[btb.scala:79:23] wire _s1_is_jal_0_T_3; // @[btb.scala:99:54] wire _s1_is_jal_1_T_3; // @[btb.scala:99:54] wire _s1_is_jal_2_T_3; // @[btb.scala:99:54] wire _s1_is_jal_3_T_3; // @[btb.scala:99:54] wire s1_is_jal_0; // @[btb.scala:80:23] wire s1_is_jal_1; // @[btb.scala:80:23] wire s1_is_jal_2; // @[btb.scala:80:23] wire s1_is_jal_3; // @[btb.scala:80:23] wire _s1_hit_ohs_T_1 = s1_req_rmeta_0_0_tag == _s1_hit_ohs_T; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_0 = _s1_hit_ohs_T_1; // @[btb.scala:83:12, :84:30] wire _s1_hit_ohs_T_3 = s1_req_rmeta_1_0_tag == _s1_hit_ohs_T_2; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_1 = _s1_hit_ohs_T_3; // @[btb.scala:83:12, :84:30] wire s1_hit_ohs_0_0 = _s1_hit_ohs_WIRE_0; // @[btb.scala:82:27, :83:12] wire s1_hit_ohs_0_1 = _s1_hit_ohs_WIRE_1; // @[btb.scala:82:27, :83:12] wire _s1_hit_ohs_T_5 = s1_req_rmeta_0_1_tag == _s1_hit_ohs_T_4; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_1_0 = _s1_hit_ohs_T_5; // @[btb.scala:83:12, :84:30] wire _s1_hit_ohs_T_7 = s1_req_rmeta_1_1_tag == _s1_hit_ohs_T_6; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_1_1 = _s1_hit_ohs_T_7; // @[btb.scala:83:12, :84:30] wire s1_hit_ohs_1_0 = _s1_hit_ohs_WIRE_1_0; // @[btb.scala:82:27, :83:12] wire s1_hit_ohs_1_1 = _s1_hit_ohs_WIRE_1_1; // @[btb.scala:82:27, :83:12] wire _s1_hit_ohs_T_9 = s1_req_rmeta_0_2_tag == _s1_hit_ohs_T_8; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_2_0 = _s1_hit_ohs_T_9; // @[btb.scala:83:12, :84:30] wire _s1_hit_ohs_T_11 = s1_req_rmeta_1_2_tag == _s1_hit_ohs_T_10; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_2_1 = _s1_hit_ohs_T_11; // @[btb.scala:83:12, :84:30] wire s1_hit_ohs_2_0 = _s1_hit_ohs_WIRE_2_0; // @[btb.scala:82:27, :83:12] wire s1_hit_ohs_2_1 = _s1_hit_ohs_WIRE_2_1; // @[btb.scala:82:27, :83:12] wire _s1_hit_ohs_T_13 = s1_req_rmeta_0_3_tag == _s1_hit_ohs_T_12; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_3_0 = _s1_hit_ohs_T_13; // @[btb.scala:83:12, :84:30] wire _s1_hit_ohs_T_15 = s1_req_rmeta_1_3_tag == _s1_hit_ohs_T_14; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_3_1 = _s1_hit_ohs_T_15; // @[btb.scala:83:12, :84:30] wire s1_hit_ohs_3_0 = _s1_hit_ohs_WIRE_3_0; // @[btb.scala:82:27, :83:12] wire s1_hit_ohs_3_1 = _s1_hit_ohs_WIRE_3_1; // @[btb.scala:82:27, :83:12] wire s1_hits_0 = s1_hit_ohs_0_0 | s1_hit_ohs_0_1; // @[btb.scala:82:27, :87:55] wire s1_hits_1 = s1_hit_ohs_1_0 | s1_hit_ohs_1_1; // @[btb.scala:82:27, :87:55] wire s1_hits_2 = s1_hit_ohs_2_0 | s1_hit_ohs_2_1; // @[btb.scala:82:27, :87:55] wire s1_hits_3 = s1_hit_ohs_3_0 | s1_hit_ohs_3_1; // @[btb.scala:82:27, :87:55] wire s1_hit_ways_0 = ~s1_hit_ohs_0_0; // @[Mux.scala:50:70] wire s1_hit_ways_1 = ~s1_hit_ohs_1_0; // @[Mux.scala:50:70] wire s1_hit_ways_2 = ~s1_hit_ohs_2_0; // @[Mux.scala:50:70] wire s1_hit_ways_3 = ~s1_hit_ohs_3_0; // @[Mux.scala:50:70] wire _s1_resp_0_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25] wire _s1_resp_0_valid_T_1 = _s1_resp_0_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_0_valid_T_2 = _s1_resp_0_valid_T_1 & s1_hits_0; // @[btb.scala:87:55, :93:{38,50}] assign s1_resp_0_valid = _s1_resp_0_valid_T_2; // @[btb.scala:78:23, :93:50] wire [40:0] _s1_resp_0_bits_T_1 = {_s1_resp_0_bits_T[39], _s1_resp_0_bits_T}; // @[btb.scala:97:{14,21}] wire [39:0] _s1_resp_0_bits_T_2 = _s1_resp_0_bits_T_1[39:0]; // @[btb.scala:97:21] wire [39:0] _s1_resp_0_bits_T_3 = _s1_resp_0_bits_T_2; // @[btb.scala:97:21] wire [12:0] _GEN = s1_hit_ways_0 ? s1_req_rbtb_1_0_offset : s1_req_rbtb_0_0_offset; // @[Mux.scala:50:70] wire [40:0] _s1_resp_0_bits_T_4 = {_s1_resp_0_bits_T_3[39], _s1_resp_0_bits_T_3} + {{28{_GEN[12]}}, _GEN}; // @[btb.scala:97:{21,34}] wire [39:0] _s1_resp_0_bits_T_5 = _s1_resp_0_bits_T_4[39:0]; // @[btb.scala:97:34] wire [39:0] _s1_resp_0_bits_T_6 = _s1_resp_0_bits_T_5; // @[btb.scala:97:34] wire [39:0] _s1_resp_0_bits_T_7 = _s1_resp_0_bits_T_6; // @[btb.scala:97:{34,54}] assign _s1_resp_0_bits_T_8 = (s1_hit_ways_0 ? s1_req_rbtb_1_0_extended : s1_req_rbtb_0_0_extended) ? _ebtb_R0_data : _s1_resp_0_bits_T_7; // @[Mux.scala:50:70] assign s1_resp_0_bits = _s1_resp_0_bits_T_8; // @[btb.scala:78:23, :94:28] wire _s1_is_br_0_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21] wire _s1_is_br_0_T_1 = _s1_is_br_0_T & s1_resp_0_valid; // @[btb.scala:78:23, :98:{21,34}] wire _GEN_0 = s1_hit_ways_0 ? s1_req_rmeta_1_0_is_br : s1_req_rmeta_0_0_is_br; // @[Mux.scala:50:70] assign _s1_is_br_0_T_2 = _s1_is_br_0_T_1 & _GEN_0; // @[btb.scala:98:{34,54}] assign s1_is_br_0 = _s1_is_br_0_T_2; // @[btb.scala:79:23, :98:54] wire _s1_is_jal_0_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21] wire _s1_is_jal_0_T_1 = _s1_is_jal_0_T & s1_resp_0_valid; // @[btb.scala:78:23, :99:{21,34}] wire _s1_is_jal_0_T_2 = ~_GEN_0; // @[btb.scala:98:54, :99:57] assign _s1_is_jal_0_T_3 = _s1_is_jal_0_T_1 & _s1_is_jal_0_T_2; // @[btb.scala:99:{34,54,57}] assign s1_is_jal_0 = _s1_is_jal_0_T_3; // @[btb.scala:80:23, :99:54] reg REG; // @[btb.scala:104:18] reg io_resp_f2_0_predicted_pc_REG_valid; // @[btb.scala:105:44] reg [39:0] io_resp_f2_0_predicted_pc_REG_bits; // @[btb.scala:105:44] assign io_resp_f2_0_predicted_pc_valid_0 = REG ? io_resp_f2_0_predicted_pc_REG_valid : io_resp_in_0_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] assign io_resp_f2_0_predicted_pc_bits_0 = REG ? io_resp_f2_0_predicted_pc_REG_bits : io_resp_in_0_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] reg io_resp_f2_0_is_br_REG; // @[btb.scala:106:44] assign io_resp_f2_0_is_br_0 = REG ? io_resp_f2_0_is_br_REG : io_resp_in_0_f2_0_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}] reg io_resp_f2_0_is_jal_REG; // @[btb.scala:107:44] assign io_resp_f2_0_is_jal_0 = REG ? io_resp_f2_0_is_jal_REG : io_resp_in_0_f2_0_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}] reg REG_1; // @[btb.scala:108:20] assign io_resp_f2_0_taken_0 = REG & REG_1 | io_resp_in_0_f2_0_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34] reg REG_2; // @[btb.scala:112:26] reg REG_3; // @[btb.scala:112:18] reg io_resp_f3_0_predicted_pc_REG_valid; // @[btb.scala:113:44] reg [39:0] io_resp_f3_0_predicted_pc_REG_bits; // @[btb.scala:113:44] assign io_resp_f3_0_predicted_pc_valid_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_valid : io_resp_in_0_f3_0_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] assign io_resp_f3_0_predicted_pc_bits_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_bits : io_resp_in_0_f3_0_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] reg io_resp_f3_0_is_br_REG; // @[btb.scala:114:44] assign io_resp_f3_0_is_br_0 = REG_3 ? io_resp_f3_0_is_br_REG : io_resp_in_0_f3_0_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}] reg io_resp_f3_0_is_jal_REG; // @[btb.scala:115:44] assign io_resp_f3_0_is_jal_0 = REG_3 ? io_resp_f3_0_is_jal_REG : io_resp_in_0_f3_0_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}] reg REG_4; // @[btb.scala:116:28] reg REG_5; // @[btb.scala:116:20] assign io_resp_f3_0_taken_0 = REG_3 & REG_5 | io_resp_in_0_f3_0_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34] wire _s1_resp_1_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25] wire _s1_resp_1_valid_T_1 = _s1_resp_1_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_1_valid_T_2 = _s1_resp_1_valid_T_1 & s1_hits_1; // @[btb.scala:87:55, :93:{38,50}] assign s1_resp_1_valid = _s1_resp_1_valid_T_2; // @[btb.scala:78:23, :93:50] wire [40:0] _s1_resp_1_bits_T_1 = {_s1_resp_1_bits_T[39], _s1_resp_1_bits_T} + 41'h2; // @[btb.scala:97:{14,21}] wire [39:0] _s1_resp_1_bits_T_2 = _s1_resp_1_bits_T_1[39:0]; // @[btb.scala:97:21] wire [39:0] _s1_resp_1_bits_T_3 = _s1_resp_1_bits_T_2; // @[btb.scala:97:21] wire [12:0] _GEN_1 = s1_hit_ways_1 ? s1_req_rbtb_1_1_offset : s1_req_rbtb_0_1_offset; // @[Mux.scala:50:70] wire [40:0] _s1_resp_1_bits_T_4 = {_s1_resp_1_bits_T_3[39], _s1_resp_1_bits_T_3} + {{28{_GEN_1[12]}}, _GEN_1}; // @[btb.scala:97:{21,34}] wire [39:0] _s1_resp_1_bits_T_5 = _s1_resp_1_bits_T_4[39:0]; // @[btb.scala:97:34] wire [39:0] _s1_resp_1_bits_T_6 = _s1_resp_1_bits_T_5; // @[btb.scala:97:34] wire [39:0] _s1_resp_1_bits_T_7 = _s1_resp_1_bits_T_6; // @[btb.scala:97:{34,54}] assign _s1_resp_1_bits_T_8 = (s1_hit_ways_1 ? s1_req_rbtb_1_1_extended : s1_req_rbtb_0_1_extended) ? _ebtb_R0_data : _s1_resp_1_bits_T_7; // @[Mux.scala:50:70] assign s1_resp_1_bits = _s1_resp_1_bits_T_8; // @[btb.scala:78:23, :94:28] wire _s1_is_br_1_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21] wire _s1_is_br_1_T_1 = _s1_is_br_1_T & s1_resp_1_valid; // @[btb.scala:78:23, :98:{21,34}] wire _GEN_2 = s1_hit_ways_1 ? s1_req_rmeta_1_1_is_br : s1_req_rmeta_0_1_is_br; // @[Mux.scala:50:70] assign _s1_is_br_1_T_2 = _s1_is_br_1_T_1 & _GEN_2; // @[btb.scala:98:{34,54}] assign s1_is_br_1 = _s1_is_br_1_T_2; // @[btb.scala:79:23, :98:54] wire _s1_is_jal_1_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21] wire _s1_is_jal_1_T_1 = _s1_is_jal_1_T & s1_resp_1_valid; // @[btb.scala:78:23, :99:{21,34}] wire _s1_is_jal_1_T_2 = ~_GEN_2; // @[btb.scala:98:54, :99:57] assign _s1_is_jal_1_T_3 = _s1_is_jal_1_T_1 & _s1_is_jal_1_T_2; // @[btb.scala:99:{34,54,57}] assign s1_is_jal_1 = _s1_is_jal_1_T_3; // @[btb.scala:80:23, :99:54] reg REG_6; // @[btb.scala:104:18] reg io_resp_f2_1_predicted_pc_REG_valid; // @[btb.scala:105:44] reg [39:0] io_resp_f2_1_predicted_pc_REG_bits; // @[btb.scala:105:44] assign io_resp_f2_1_predicted_pc_valid_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_valid : io_resp_in_0_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] assign io_resp_f2_1_predicted_pc_bits_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_bits : io_resp_in_0_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] reg io_resp_f2_1_is_br_REG; // @[btb.scala:106:44] assign io_resp_f2_1_is_br_0 = REG_6 ? io_resp_f2_1_is_br_REG : io_resp_in_0_f2_1_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}] reg io_resp_f2_1_is_jal_REG; // @[btb.scala:107:44] assign io_resp_f2_1_is_jal_0 = REG_6 ? io_resp_f2_1_is_jal_REG : io_resp_in_0_f2_1_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}] reg REG_7; // @[btb.scala:108:20] assign io_resp_f2_1_taken_0 = REG_6 & REG_7 | io_resp_in_0_f2_1_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34] reg REG_8; // @[btb.scala:112:26] reg REG_9; // @[btb.scala:112:18] reg io_resp_f3_1_predicted_pc_REG_valid; // @[btb.scala:113:44] reg [39:0] io_resp_f3_1_predicted_pc_REG_bits; // @[btb.scala:113:44] assign io_resp_f3_1_predicted_pc_valid_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_valid : io_resp_in_0_f3_1_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] assign io_resp_f3_1_predicted_pc_bits_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_bits : io_resp_in_0_f3_1_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] reg io_resp_f3_1_is_br_REG; // @[btb.scala:114:44] assign io_resp_f3_1_is_br_0 = REG_9 ? io_resp_f3_1_is_br_REG : io_resp_in_0_f3_1_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}] reg io_resp_f3_1_is_jal_REG; // @[btb.scala:115:44] assign io_resp_f3_1_is_jal_0 = REG_9 ? io_resp_f3_1_is_jal_REG : io_resp_in_0_f3_1_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}] reg REG_10; // @[btb.scala:116:28] reg REG_11; // @[btb.scala:116:20] assign io_resp_f3_1_taken_0 = REG_9 & REG_11 | io_resp_in_0_f3_1_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34] wire _s1_resp_2_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25] wire _s1_resp_2_valid_T_1 = _s1_resp_2_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_2_valid_T_2 = _s1_resp_2_valid_T_1 & s1_hits_2; // @[btb.scala:87:55, :93:{38,50}] assign s1_resp_2_valid = _s1_resp_2_valid_T_2; // @[btb.scala:78:23, :93:50] wire [40:0] _s1_resp_2_bits_T_1 = {_s1_resp_2_bits_T[39], _s1_resp_2_bits_T} + 41'h4; // @[btb.scala:97:{14,21}] wire [39:0] _s1_resp_2_bits_T_2 = _s1_resp_2_bits_T_1[39:0]; // @[btb.scala:97:21] wire [39:0] _s1_resp_2_bits_T_3 = _s1_resp_2_bits_T_2; // @[btb.scala:97:21] wire [12:0] _GEN_3 = s1_hit_ways_2 ? s1_req_rbtb_1_2_offset : s1_req_rbtb_0_2_offset; // @[Mux.scala:50:70] wire [40:0] _s1_resp_2_bits_T_4 = {_s1_resp_2_bits_T_3[39], _s1_resp_2_bits_T_3} + {{28{_GEN_3[12]}}, _GEN_3}; // @[btb.scala:97:{21,34}] wire [39:0] _s1_resp_2_bits_T_5 = _s1_resp_2_bits_T_4[39:0]; // @[btb.scala:97:34] wire [39:0] _s1_resp_2_bits_T_6 = _s1_resp_2_bits_T_5; // @[btb.scala:97:34] wire [39:0] _s1_resp_2_bits_T_7 = _s1_resp_2_bits_T_6; // @[btb.scala:97:{34,54}] assign _s1_resp_2_bits_T_8 = (s1_hit_ways_2 ? s1_req_rbtb_1_2_extended : s1_req_rbtb_0_2_extended) ? _ebtb_R0_data : _s1_resp_2_bits_T_7; // @[Mux.scala:50:70] assign s1_resp_2_bits = _s1_resp_2_bits_T_8; // @[btb.scala:78:23, :94:28] wire _s1_is_br_2_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21] wire _s1_is_br_2_T_1 = _s1_is_br_2_T & s1_resp_2_valid; // @[btb.scala:78:23, :98:{21,34}] wire _GEN_4 = s1_hit_ways_2 ? s1_req_rmeta_1_2_is_br : s1_req_rmeta_0_2_is_br; // @[Mux.scala:50:70] assign _s1_is_br_2_T_2 = _s1_is_br_2_T_1 & _GEN_4; // @[btb.scala:98:{34,54}] assign s1_is_br_2 = _s1_is_br_2_T_2; // @[btb.scala:79:23, :98:54] wire _s1_is_jal_2_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21] wire _s1_is_jal_2_T_1 = _s1_is_jal_2_T & s1_resp_2_valid; // @[btb.scala:78:23, :99:{21,34}] wire _s1_is_jal_2_T_2 = ~_GEN_4; // @[btb.scala:98:54, :99:57] assign _s1_is_jal_2_T_3 = _s1_is_jal_2_T_1 & _s1_is_jal_2_T_2; // @[btb.scala:99:{34,54,57}] assign s1_is_jal_2 = _s1_is_jal_2_T_3; // @[btb.scala:80:23, :99:54] reg REG_12; // @[btb.scala:104:18] reg io_resp_f2_2_predicted_pc_REG_valid; // @[btb.scala:105:44] reg [39:0] io_resp_f2_2_predicted_pc_REG_bits; // @[btb.scala:105:44] assign io_resp_f2_2_predicted_pc_valid_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_valid : io_resp_in_0_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] assign io_resp_f2_2_predicted_pc_bits_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_bits : io_resp_in_0_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] reg io_resp_f2_2_is_br_REG; // @[btb.scala:106:44] assign io_resp_f2_2_is_br_0 = REG_12 ? io_resp_f2_2_is_br_REG : io_resp_in_0_f2_2_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}] reg io_resp_f2_2_is_jal_REG; // @[btb.scala:107:44] assign io_resp_f2_2_is_jal_0 = REG_12 ? io_resp_f2_2_is_jal_REG : io_resp_in_0_f2_2_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}] reg REG_13; // @[btb.scala:108:20] assign io_resp_f2_2_taken_0 = REG_12 & REG_13 | io_resp_in_0_f2_2_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34] reg REG_14; // @[btb.scala:112:26] reg REG_15; // @[btb.scala:112:18] reg io_resp_f3_2_predicted_pc_REG_valid; // @[btb.scala:113:44] reg [39:0] io_resp_f3_2_predicted_pc_REG_bits; // @[btb.scala:113:44] assign io_resp_f3_2_predicted_pc_valid_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_valid : io_resp_in_0_f3_2_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] assign io_resp_f3_2_predicted_pc_bits_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_bits : io_resp_in_0_f3_2_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] reg io_resp_f3_2_is_br_REG; // @[btb.scala:114:44] assign io_resp_f3_2_is_br_0 = REG_15 ? io_resp_f3_2_is_br_REG : io_resp_in_0_f3_2_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}] reg io_resp_f3_2_is_jal_REG; // @[btb.scala:115:44] assign io_resp_f3_2_is_jal_0 = REG_15 ? io_resp_f3_2_is_jal_REG : io_resp_in_0_f3_2_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}] reg REG_16; // @[btb.scala:116:28] reg REG_17; // @[btb.scala:116:20] assign io_resp_f3_2_taken_0 = REG_15 & REG_17 | io_resp_in_0_f3_2_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34] wire _s1_resp_3_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25] wire _s1_resp_3_valid_T_1 = _s1_resp_3_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_3_valid_T_2 = _s1_resp_3_valid_T_1 & s1_hits_3; // @[btb.scala:87:55, :93:{38,50}] assign s1_resp_3_valid = _s1_resp_3_valid_T_2; // @[btb.scala:78:23, :93:50] wire [40:0] _s1_resp_3_bits_T_1 = {_s1_resp_3_bits_T[39], _s1_resp_3_bits_T} + 41'h6; // @[btb.scala:97:{14,21}] wire [39:0] _s1_resp_3_bits_T_2 = _s1_resp_3_bits_T_1[39:0]; // @[btb.scala:97:21] wire [39:0] _s1_resp_3_bits_T_3 = _s1_resp_3_bits_T_2; // @[btb.scala:97:21] wire [12:0] _GEN_5 = s1_hit_ways_3 ? s1_req_rbtb_1_3_offset : s1_req_rbtb_0_3_offset; // @[Mux.scala:50:70] wire [40:0] _s1_resp_3_bits_T_4 = {_s1_resp_3_bits_T_3[39], _s1_resp_3_bits_T_3} + {{28{_GEN_5[12]}}, _GEN_5}; // @[btb.scala:97:{21,34}] wire [39:0] _s1_resp_3_bits_T_5 = _s1_resp_3_bits_T_4[39:0]; // @[btb.scala:97:34] wire [39:0] _s1_resp_3_bits_T_6 = _s1_resp_3_bits_T_5; // @[btb.scala:97:34] wire [39:0] _s1_resp_3_bits_T_7 = _s1_resp_3_bits_T_6; // @[btb.scala:97:{34,54}] assign _s1_resp_3_bits_T_8 = (s1_hit_ways_3 ? s1_req_rbtb_1_3_extended : s1_req_rbtb_0_3_extended) ? _ebtb_R0_data : _s1_resp_3_bits_T_7; // @[Mux.scala:50:70] assign s1_resp_3_bits = _s1_resp_3_bits_T_8; // @[btb.scala:78:23, :94:28] wire _s1_is_br_3_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21] wire _s1_is_br_3_T_1 = _s1_is_br_3_T & s1_resp_3_valid; // @[btb.scala:78:23, :98:{21,34}] wire _GEN_6 = s1_hit_ways_3 ? s1_req_rmeta_1_3_is_br : s1_req_rmeta_0_3_is_br; // @[Mux.scala:50:70] assign _s1_is_br_3_T_2 = _s1_is_br_3_T_1 & _GEN_6; // @[btb.scala:98:{34,54}] assign s1_is_br_3 = _s1_is_br_3_T_2; // @[btb.scala:79:23, :98:54] wire _s1_is_jal_3_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21] wire _s1_is_jal_3_T_1 = _s1_is_jal_3_T & s1_resp_3_valid; // @[btb.scala:78:23, :99:{21,34}] wire _s1_is_jal_3_T_2 = ~_GEN_6; // @[btb.scala:98:54, :99:57] assign _s1_is_jal_3_T_3 = _s1_is_jal_3_T_1 & _s1_is_jal_3_T_2; // @[btb.scala:99:{34,54,57}] assign s1_is_jal_3 = _s1_is_jal_3_T_3; // @[btb.scala:80:23, :99:54] reg REG_18; // @[btb.scala:104:18] reg io_resp_f2_3_predicted_pc_REG_valid; // @[btb.scala:105:44] reg [39:0] io_resp_f2_3_predicted_pc_REG_bits; // @[btb.scala:105:44] assign io_resp_f2_3_predicted_pc_valid_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_valid : io_resp_in_0_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] assign io_resp_f2_3_predicted_pc_bits_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_bits : io_resp_in_0_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] reg io_resp_f2_3_is_br_REG; // @[btb.scala:106:44] assign io_resp_f2_3_is_br_0 = REG_18 ? io_resp_f2_3_is_br_REG : io_resp_in_0_f2_3_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}] reg io_resp_f2_3_is_jal_REG; // @[btb.scala:107:44] assign io_resp_f2_3_is_jal_0 = REG_18 ? io_resp_f2_3_is_jal_REG : io_resp_in_0_f2_3_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}] reg REG_19; // @[btb.scala:108:20] assign io_resp_f2_3_taken_0 = REG_18 & REG_19 | io_resp_in_0_f2_3_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34] reg REG_20; // @[btb.scala:112:26] reg REG_21; // @[btb.scala:112:18] reg io_resp_f3_3_predicted_pc_REG_valid; // @[btb.scala:113:44] reg [39:0] io_resp_f3_3_predicted_pc_REG_bits; // @[btb.scala:113:44] assign io_resp_f3_3_predicted_pc_valid_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_valid : io_resp_in_0_f3_3_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] assign io_resp_f3_3_predicted_pc_bits_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_bits : io_resp_in_0_f3_3_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] reg io_resp_f3_3_is_br_REG; // @[btb.scala:114:44] assign io_resp_f3_3_is_br_0 = REG_21 ? io_resp_f3_3_is_br_REG : io_resp_in_0_f3_3_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}] reg io_resp_f3_3_is_jal_REG; // @[btb.scala:115:44] assign io_resp_f3_3_is_jal_0 = REG_21 ? io_resp_f3_3_is_jal_REG : io_resp_in_0_f3_3_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}] reg REG_22; // @[btb.scala:116:28] reg REG_23; // @[btb.scala:116:20] assign io_resp_f3_3_taken_0 = REG_21 & REG_23 | io_resp_in_0_f3_3_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34] wire [28:0] _alloc_way_r_metas_WIRE_2_0_0 = _alloc_way_r_metas_WIRE_0; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_1 = _alloc_way_r_metas_WIRE_1; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_2 = _alloc_way_r_metas_WIRE_2; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_3 = _alloc_way_r_metas_WIRE_3; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_0 = _alloc_way_r_metas_WIRE_1_0; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_1 = _alloc_way_r_metas_WIRE_1_1; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_2 = _alloc_way_r_metas_WIRE_1_2; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_3 = _alloc_way_r_metas_WIRE_1_3; // @[btb.scala:123:{30,62}] wire [57:0] alloc_way_r_metas_lo = {_alloc_way_r_metas_WIRE_2_0_1, _alloc_way_r_metas_WIRE_2_0_0}; // @[btb.scala:123:{30,80}] wire [57:0] alloc_way_r_metas_hi = {_alloc_way_r_metas_WIRE_2_0_3, _alloc_way_r_metas_WIRE_2_0_2}; // @[btb.scala:123:{30,80}] wire [115:0] _alloc_way_r_metas_T = {alloc_way_r_metas_hi, alloc_way_r_metas_lo}; // @[btb.scala:123:80] wire [57:0] alloc_way_r_metas_lo_1 = {_alloc_way_r_metas_WIRE_2_1_1, _alloc_way_r_metas_WIRE_2_1_0}; // @[btb.scala:123:{30,80}] wire [57:0] alloc_way_r_metas_hi_1 = {_alloc_way_r_metas_WIRE_2_1_3, _alloc_way_r_metas_WIRE_2_1_2}; // @[btb.scala:123:{30,80}] wire [115:0] _alloc_way_r_metas_T_1 = {alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1}; // @[btb.scala:123:80] wire [231:0] _alloc_way_r_metas_T_2 = {_alloc_way_r_metas_T_1, _alloc_way_r_metas_T}; // @[btb.scala:123:80] wire [260:0] alloc_way_r_metas = {_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3}; // @[btb.scala:123:{22,80,98}] wire alloc_way_chunks_0 = alloc_way_r_metas[0]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_1 = alloc_way_r_metas[1]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_2 = alloc_way_r_metas[2]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_3 = alloc_way_r_metas[3]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_4 = alloc_way_r_metas[4]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_5 = alloc_way_r_metas[5]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_6 = alloc_way_r_metas[6]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_7 = alloc_way_r_metas[7]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_8 = alloc_way_r_metas[8]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_9 = alloc_way_r_metas[9]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_10 = alloc_way_r_metas[10]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_11 = alloc_way_r_metas[11]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_12 = alloc_way_r_metas[12]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_13 = alloc_way_r_metas[13]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_14 = alloc_way_r_metas[14]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_15 = alloc_way_r_metas[15]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_16 = alloc_way_r_metas[16]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_17 = alloc_way_r_metas[17]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_18 = alloc_way_r_metas[18]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_19 = alloc_way_r_metas[19]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_20 = alloc_way_r_metas[20]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_21 = alloc_way_r_metas[21]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_22 = alloc_way_r_metas[22]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_23 = alloc_way_r_metas[23]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_24 = alloc_way_r_metas[24]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_25 = alloc_way_r_metas[25]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_26 = alloc_way_r_metas[26]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_27 = alloc_way_r_metas[27]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_28 = alloc_way_r_metas[28]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_29 = alloc_way_r_metas[29]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_30 = alloc_way_r_metas[30]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_31 = alloc_way_r_metas[31]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_32 = alloc_way_r_metas[32]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_33 = alloc_way_r_metas[33]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_34 = alloc_way_r_metas[34]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_35 = alloc_way_r_metas[35]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_36 = alloc_way_r_metas[36]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_37 = alloc_way_r_metas[37]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_38 = alloc_way_r_metas[38]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_39 = alloc_way_r_metas[39]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_40 = alloc_way_r_metas[40]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_41 = alloc_way_r_metas[41]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_42 = alloc_way_r_metas[42]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_43 = alloc_way_r_metas[43]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_44 = alloc_way_r_metas[44]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_45 = alloc_way_r_metas[45]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_46 = alloc_way_r_metas[46]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_47 = alloc_way_r_metas[47]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_48 = alloc_way_r_metas[48]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_49 = alloc_way_r_metas[49]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_50 = alloc_way_r_metas[50]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_51 = alloc_way_r_metas[51]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_52 = alloc_way_r_metas[52]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_53 = alloc_way_r_metas[53]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_54 = alloc_way_r_metas[54]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_55 = alloc_way_r_metas[55]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_56 = alloc_way_r_metas[56]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_57 = alloc_way_r_metas[57]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_58 = alloc_way_r_metas[58]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_59 = alloc_way_r_metas[59]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_60 = alloc_way_r_metas[60]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_61 = alloc_way_r_metas[61]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_62 = alloc_way_r_metas[62]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_63 = alloc_way_r_metas[63]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_64 = alloc_way_r_metas[64]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_65 = alloc_way_r_metas[65]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_66 = alloc_way_r_metas[66]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_67 = alloc_way_r_metas[67]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_68 = alloc_way_r_metas[68]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_69 = alloc_way_r_metas[69]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_70 = alloc_way_r_metas[70]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_71 = alloc_way_r_metas[71]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_72 = alloc_way_r_metas[72]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_73 = alloc_way_r_metas[73]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_74 = alloc_way_r_metas[74]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_75 = alloc_way_r_metas[75]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_76 = alloc_way_r_metas[76]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_77 = alloc_way_r_metas[77]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_78 = alloc_way_r_metas[78]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_79 = alloc_way_r_metas[79]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_80 = alloc_way_r_metas[80]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_81 = alloc_way_r_metas[81]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_82 = alloc_way_r_metas[82]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_83 = alloc_way_r_metas[83]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_84 = alloc_way_r_metas[84]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_85 = alloc_way_r_metas[85]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_86 = alloc_way_r_metas[86]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_87 = alloc_way_r_metas[87]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_88 = alloc_way_r_metas[88]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_89 = alloc_way_r_metas[89]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_90 = alloc_way_r_metas[90]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_91 = alloc_way_r_metas[91]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_92 = alloc_way_r_metas[92]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_93 = alloc_way_r_metas[93]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_94 = alloc_way_r_metas[94]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_95 = alloc_way_r_metas[95]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_96 = alloc_way_r_metas[96]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_97 = alloc_way_r_metas[97]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_98 = alloc_way_r_metas[98]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_99 = alloc_way_r_metas[99]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_100 = alloc_way_r_metas[100]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_101 = alloc_way_r_metas[101]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_102 = alloc_way_r_metas[102]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_103 = alloc_way_r_metas[103]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_104 = alloc_way_r_metas[104]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_105 = alloc_way_r_metas[105]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_106 = alloc_way_r_metas[106]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_107 = alloc_way_r_metas[107]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_108 = alloc_way_r_metas[108]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_109 = alloc_way_r_metas[109]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_110 = alloc_way_r_metas[110]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_111 = alloc_way_r_metas[111]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_112 = alloc_way_r_metas[112]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_113 = alloc_way_r_metas[113]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_114 = alloc_way_r_metas[114]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_115 = alloc_way_r_metas[115]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_116 = alloc_way_r_metas[116]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_117 = alloc_way_r_metas[117]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_118 = alloc_way_r_metas[118]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_119 = alloc_way_r_metas[119]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_120 = alloc_way_r_metas[120]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_121 = alloc_way_r_metas[121]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_122 = alloc_way_r_metas[122]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_123 = alloc_way_r_metas[123]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_124 = alloc_way_r_metas[124]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_125 = alloc_way_r_metas[125]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_126 = alloc_way_r_metas[126]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_127 = alloc_way_r_metas[127]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_128 = alloc_way_r_metas[128]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_129 = alloc_way_r_metas[129]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_130 = alloc_way_r_metas[130]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_131 = alloc_way_r_metas[131]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_132 = alloc_way_r_metas[132]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_133 = alloc_way_r_metas[133]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_134 = alloc_way_r_metas[134]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_135 = alloc_way_r_metas[135]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_136 = alloc_way_r_metas[136]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_137 = alloc_way_r_metas[137]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_138 = alloc_way_r_metas[138]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_139 = alloc_way_r_metas[139]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_140 = alloc_way_r_metas[140]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_141 = alloc_way_r_metas[141]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_142 = alloc_way_r_metas[142]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_143 = alloc_way_r_metas[143]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_144 = alloc_way_r_metas[144]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_145 = alloc_way_r_metas[145]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_146 = alloc_way_r_metas[146]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_147 = alloc_way_r_metas[147]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_148 = alloc_way_r_metas[148]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_149 = alloc_way_r_metas[149]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_150 = alloc_way_r_metas[150]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_151 = alloc_way_r_metas[151]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_152 = alloc_way_r_metas[152]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_153 = alloc_way_r_metas[153]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_154 = alloc_way_r_metas[154]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_155 = alloc_way_r_metas[155]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_156 = alloc_way_r_metas[156]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_157 = alloc_way_r_metas[157]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_158 = alloc_way_r_metas[158]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_159 = alloc_way_r_metas[159]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_160 = alloc_way_r_metas[160]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_161 = alloc_way_r_metas[161]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_162 = alloc_way_r_metas[162]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_163 = alloc_way_r_metas[163]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_164 = alloc_way_r_metas[164]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_165 = alloc_way_r_metas[165]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_166 = alloc_way_r_metas[166]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_167 = alloc_way_r_metas[167]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_168 = alloc_way_r_metas[168]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_169 = alloc_way_r_metas[169]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_170 = alloc_way_r_metas[170]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_171 = alloc_way_r_metas[171]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_172 = alloc_way_r_metas[172]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_173 = alloc_way_r_metas[173]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_174 = alloc_way_r_metas[174]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_175 = alloc_way_r_metas[175]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_176 = alloc_way_r_metas[176]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_177 = alloc_way_r_metas[177]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_178 = alloc_way_r_metas[178]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_179 = alloc_way_r_metas[179]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_180 = alloc_way_r_metas[180]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_181 = alloc_way_r_metas[181]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_182 = alloc_way_r_metas[182]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_183 = alloc_way_r_metas[183]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_184 = alloc_way_r_metas[184]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_185 = alloc_way_r_metas[185]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_186 = alloc_way_r_metas[186]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_187 = alloc_way_r_metas[187]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_188 = alloc_way_r_metas[188]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_189 = alloc_way_r_metas[189]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_190 = alloc_way_r_metas[190]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_191 = alloc_way_r_metas[191]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_192 = alloc_way_r_metas[192]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_193 = alloc_way_r_metas[193]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_194 = alloc_way_r_metas[194]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_195 = alloc_way_r_metas[195]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_196 = alloc_way_r_metas[196]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_197 = alloc_way_r_metas[197]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_198 = alloc_way_r_metas[198]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_199 = alloc_way_r_metas[199]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_200 = alloc_way_r_metas[200]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_201 = alloc_way_r_metas[201]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_202 = alloc_way_r_metas[202]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_203 = alloc_way_r_metas[203]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_204 = alloc_way_r_metas[204]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_205 = alloc_way_r_metas[205]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_206 = alloc_way_r_metas[206]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_207 = alloc_way_r_metas[207]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_208 = alloc_way_r_metas[208]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_209 = alloc_way_r_metas[209]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_210 = alloc_way_r_metas[210]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_211 = alloc_way_r_metas[211]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_212 = alloc_way_r_metas[212]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_213 = alloc_way_r_metas[213]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_214 = alloc_way_r_metas[214]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_215 = alloc_way_r_metas[215]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_216 = alloc_way_r_metas[216]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_217 = alloc_way_r_metas[217]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_218 = alloc_way_r_metas[218]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_219 = alloc_way_r_metas[219]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_220 = alloc_way_r_metas[220]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_221 = alloc_way_r_metas[221]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_222 = alloc_way_r_metas[222]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_223 = alloc_way_r_metas[223]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_224 = alloc_way_r_metas[224]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_225 = alloc_way_r_metas[225]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_226 = alloc_way_r_metas[226]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_227 = alloc_way_r_metas[227]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_228 = alloc_way_r_metas[228]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_229 = alloc_way_r_metas[229]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_230 = alloc_way_r_metas[230]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_231 = alloc_way_r_metas[231]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_232 = alloc_way_r_metas[232]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_233 = alloc_way_r_metas[233]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_234 = alloc_way_r_metas[234]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_235 = alloc_way_r_metas[235]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_236 = alloc_way_r_metas[236]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_237 = alloc_way_r_metas[237]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_238 = alloc_way_r_metas[238]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_239 = alloc_way_r_metas[239]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_240 = alloc_way_r_metas[240]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_241 = alloc_way_r_metas[241]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_242 = alloc_way_r_metas[242]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_243 = alloc_way_r_metas[243]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_244 = alloc_way_r_metas[244]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_245 = alloc_way_r_metas[245]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_246 = alloc_way_r_metas[246]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_247 = alloc_way_r_metas[247]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_248 = alloc_way_r_metas[248]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_249 = alloc_way_r_metas[249]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_250 = alloc_way_r_metas[250]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_251 = alloc_way_r_metas[251]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_252 = alloc_way_r_metas[252]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_253 = alloc_way_r_metas[253]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_254 = alloc_way_r_metas[254]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_255 = alloc_way_r_metas[255]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_256 = alloc_way_r_metas[256]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_257 = alloc_way_r_metas[257]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_258 = alloc_way_r_metas[258]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_259 = alloc_way_r_metas[259]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_260 = alloc_way_r_metas[260]; // @[btb.scala:123:22, :127:14] wire _alloc_way_T = alloc_way_chunks_0 ^ alloc_way_chunks_1; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_1 = _alloc_way_T ^ alloc_way_chunks_2; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_2 = _alloc_way_T_1 ^ alloc_way_chunks_3; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_3 = _alloc_way_T_2 ^ alloc_way_chunks_4; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_4 = _alloc_way_T_3 ^ alloc_way_chunks_5; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_5 = _alloc_way_T_4 ^ alloc_way_chunks_6; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_6 = _alloc_way_T_5 ^ alloc_way_chunks_7; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_7 = _alloc_way_T_6 ^ alloc_way_chunks_8; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_8 = _alloc_way_T_7 ^ alloc_way_chunks_9; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_9 = _alloc_way_T_8 ^ alloc_way_chunks_10; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_10 = _alloc_way_T_9 ^ alloc_way_chunks_11; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_11 = _alloc_way_T_10 ^ alloc_way_chunks_12; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_12 = _alloc_way_T_11 ^ alloc_way_chunks_13; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_13 = _alloc_way_T_12 ^ alloc_way_chunks_14; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_14 = _alloc_way_T_13 ^ alloc_way_chunks_15; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_15 = _alloc_way_T_14 ^ alloc_way_chunks_16; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_16 = _alloc_way_T_15 ^ alloc_way_chunks_17; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_17 = _alloc_way_T_16 ^ alloc_way_chunks_18; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_18 = _alloc_way_T_17 ^ alloc_way_chunks_19; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_19 = _alloc_way_T_18 ^ alloc_way_chunks_20; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_20 = _alloc_way_T_19 ^ alloc_way_chunks_21; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_21 = _alloc_way_T_20 ^ alloc_way_chunks_22; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_22 = _alloc_way_T_21 ^ alloc_way_chunks_23; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_23 = _alloc_way_T_22 ^ alloc_way_chunks_24; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_24 = _alloc_way_T_23 ^ alloc_way_chunks_25; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_25 = _alloc_way_T_24 ^ alloc_way_chunks_26; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_26 = _alloc_way_T_25 ^ alloc_way_chunks_27; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_27 = _alloc_way_T_26 ^ alloc_way_chunks_28; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_28 = _alloc_way_T_27 ^ alloc_way_chunks_29; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_29 = _alloc_way_T_28 ^ alloc_way_chunks_30; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_30 = _alloc_way_T_29 ^ alloc_way_chunks_31; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_31 = _alloc_way_T_30 ^ alloc_way_chunks_32; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_32 = _alloc_way_T_31 ^ alloc_way_chunks_33; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_33 = _alloc_way_T_32 ^ alloc_way_chunks_34; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_34 = _alloc_way_T_33 ^ alloc_way_chunks_35; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_35 = _alloc_way_T_34 ^ alloc_way_chunks_36; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_36 = _alloc_way_T_35 ^ alloc_way_chunks_37; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_37 = _alloc_way_T_36 ^ alloc_way_chunks_38; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_38 = _alloc_way_T_37 ^ alloc_way_chunks_39; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_39 = _alloc_way_T_38 ^ alloc_way_chunks_40; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_40 = _alloc_way_T_39 ^ alloc_way_chunks_41; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_41 = _alloc_way_T_40 ^ alloc_way_chunks_42; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_42 = _alloc_way_T_41 ^ alloc_way_chunks_43; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_43 = _alloc_way_T_42 ^ alloc_way_chunks_44; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_44 = _alloc_way_T_43 ^ alloc_way_chunks_45; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_45 = _alloc_way_T_44 ^ alloc_way_chunks_46; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_46 = _alloc_way_T_45 ^ alloc_way_chunks_47; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_47 = _alloc_way_T_46 ^ alloc_way_chunks_48; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_48 = _alloc_way_T_47 ^ alloc_way_chunks_49; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_49 = _alloc_way_T_48 ^ alloc_way_chunks_50; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_50 = _alloc_way_T_49 ^ alloc_way_chunks_51; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_51 = _alloc_way_T_50 ^ alloc_way_chunks_52; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_52 = _alloc_way_T_51 ^ alloc_way_chunks_53; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_53 = _alloc_way_T_52 ^ alloc_way_chunks_54; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_54 = _alloc_way_T_53 ^ alloc_way_chunks_55; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_55 = _alloc_way_T_54 ^ alloc_way_chunks_56; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_56 = _alloc_way_T_55 ^ alloc_way_chunks_57; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_57 = _alloc_way_T_56 ^ alloc_way_chunks_58; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_58 = _alloc_way_T_57 ^ alloc_way_chunks_59; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_59 = _alloc_way_T_58 ^ alloc_way_chunks_60; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_60 = _alloc_way_T_59 ^ alloc_way_chunks_61; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_61 = _alloc_way_T_60 ^ alloc_way_chunks_62; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_62 = _alloc_way_T_61 ^ alloc_way_chunks_63; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_63 = _alloc_way_T_62 ^ alloc_way_chunks_64; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_64 = _alloc_way_T_63 ^ alloc_way_chunks_65; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_65 = _alloc_way_T_64 ^ alloc_way_chunks_66; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_66 = _alloc_way_T_65 ^ alloc_way_chunks_67; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_67 = _alloc_way_T_66 ^ alloc_way_chunks_68; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_68 = _alloc_way_T_67 ^ alloc_way_chunks_69; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_69 = _alloc_way_T_68 ^ alloc_way_chunks_70; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_70 = _alloc_way_T_69 ^ alloc_way_chunks_71; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_71 = _alloc_way_T_70 ^ alloc_way_chunks_72; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_72 = _alloc_way_T_71 ^ alloc_way_chunks_73; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_73 = _alloc_way_T_72 ^ alloc_way_chunks_74; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_74 = _alloc_way_T_73 ^ alloc_way_chunks_75; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_75 = _alloc_way_T_74 ^ alloc_way_chunks_76; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_76 = _alloc_way_T_75 ^ alloc_way_chunks_77; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_77 = _alloc_way_T_76 ^ alloc_way_chunks_78; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_78 = _alloc_way_T_77 ^ alloc_way_chunks_79; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_79 = _alloc_way_T_78 ^ alloc_way_chunks_80; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_80 = _alloc_way_T_79 ^ alloc_way_chunks_81; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_81 = _alloc_way_T_80 ^ alloc_way_chunks_82; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_82 = _alloc_way_T_81 ^ alloc_way_chunks_83; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_83 = _alloc_way_T_82 ^ alloc_way_chunks_84; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_84 = _alloc_way_T_83 ^ alloc_way_chunks_85; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_85 = _alloc_way_T_84 ^ alloc_way_chunks_86; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_86 = _alloc_way_T_85 ^ alloc_way_chunks_87; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_87 = _alloc_way_T_86 ^ alloc_way_chunks_88; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_88 = _alloc_way_T_87 ^ alloc_way_chunks_89; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_89 = _alloc_way_T_88 ^ alloc_way_chunks_90; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_90 = _alloc_way_T_89 ^ alloc_way_chunks_91; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_91 = _alloc_way_T_90 ^ alloc_way_chunks_92; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_92 = _alloc_way_T_91 ^ alloc_way_chunks_93; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_93 = _alloc_way_T_92 ^ alloc_way_chunks_94; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_94 = _alloc_way_T_93 ^ alloc_way_chunks_95; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_95 = _alloc_way_T_94 ^ alloc_way_chunks_96; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_96 = _alloc_way_T_95 ^ alloc_way_chunks_97; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_97 = _alloc_way_T_96 ^ alloc_way_chunks_98; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_98 = _alloc_way_T_97 ^ alloc_way_chunks_99; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_99 = _alloc_way_T_98 ^ alloc_way_chunks_100; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_100 = _alloc_way_T_99 ^ alloc_way_chunks_101; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_101 = _alloc_way_T_100 ^ alloc_way_chunks_102; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_102 = _alloc_way_T_101 ^ alloc_way_chunks_103; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_103 = _alloc_way_T_102 ^ alloc_way_chunks_104; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_104 = _alloc_way_T_103 ^ alloc_way_chunks_105; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_105 = _alloc_way_T_104 ^ alloc_way_chunks_106; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_106 = _alloc_way_T_105 ^ alloc_way_chunks_107; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_107 = _alloc_way_T_106 ^ alloc_way_chunks_108; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_108 = _alloc_way_T_107 ^ alloc_way_chunks_109; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_109 = _alloc_way_T_108 ^ alloc_way_chunks_110; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_110 = _alloc_way_T_109 ^ alloc_way_chunks_111; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_111 = _alloc_way_T_110 ^ alloc_way_chunks_112; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_112 = _alloc_way_T_111 ^ alloc_way_chunks_113; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_113 = _alloc_way_T_112 ^ alloc_way_chunks_114; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_114 = _alloc_way_T_113 ^ alloc_way_chunks_115; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_115 = _alloc_way_T_114 ^ alloc_way_chunks_116; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_116 = _alloc_way_T_115 ^ alloc_way_chunks_117; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_117 = _alloc_way_T_116 ^ alloc_way_chunks_118; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_118 = _alloc_way_T_117 ^ alloc_way_chunks_119; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_119 = _alloc_way_T_118 ^ alloc_way_chunks_120; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_120 = _alloc_way_T_119 ^ alloc_way_chunks_121; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_121 = _alloc_way_T_120 ^ alloc_way_chunks_122; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_122 = _alloc_way_T_121 ^ alloc_way_chunks_123; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_123 = _alloc_way_T_122 ^ alloc_way_chunks_124; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_124 = _alloc_way_T_123 ^ alloc_way_chunks_125; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_125 = _alloc_way_T_124 ^ alloc_way_chunks_126; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_126 = _alloc_way_T_125 ^ alloc_way_chunks_127; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_127 = _alloc_way_T_126 ^ alloc_way_chunks_128; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_128 = _alloc_way_T_127 ^ alloc_way_chunks_129; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_129 = _alloc_way_T_128 ^ alloc_way_chunks_130; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_130 = _alloc_way_T_129 ^ alloc_way_chunks_131; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_131 = _alloc_way_T_130 ^ alloc_way_chunks_132; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_132 = _alloc_way_T_131 ^ alloc_way_chunks_133; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_133 = _alloc_way_T_132 ^ alloc_way_chunks_134; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_134 = _alloc_way_T_133 ^ alloc_way_chunks_135; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_135 = _alloc_way_T_134 ^ alloc_way_chunks_136; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_136 = _alloc_way_T_135 ^ alloc_way_chunks_137; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_137 = _alloc_way_T_136 ^ alloc_way_chunks_138; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_138 = _alloc_way_T_137 ^ alloc_way_chunks_139; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_139 = _alloc_way_T_138 ^ alloc_way_chunks_140; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_140 = _alloc_way_T_139 ^ alloc_way_chunks_141; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_141 = _alloc_way_T_140 ^ alloc_way_chunks_142; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_142 = _alloc_way_T_141 ^ alloc_way_chunks_143; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_143 = _alloc_way_T_142 ^ alloc_way_chunks_144; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_144 = _alloc_way_T_143 ^ alloc_way_chunks_145; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_145 = _alloc_way_T_144 ^ alloc_way_chunks_146; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_146 = _alloc_way_T_145 ^ alloc_way_chunks_147; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_147 = _alloc_way_T_146 ^ alloc_way_chunks_148; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_148 = _alloc_way_T_147 ^ alloc_way_chunks_149; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_149 = _alloc_way_T_148 ^ alloc_way_chunks_150; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_150 = _alloc_way_T_149 ^ alloc_way_chunks_151; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_151 = _alloc_way_T_150 ^ alloc_way_chunks_152; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_152 = _alloc_way_T_151 ^ alloc_way_chunks_153; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_153 = _alloc_way_T_152 ^ alloc_way_chunks_154; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_154 = _alloc_way_T_153 ^ alloc_way_chunks_155; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_155 = _alloc_way_T_154 ^ alloc_way_chunks_156; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_156 = _alloc_way_T_155 ^ alloc_way_chunks_157; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_157 = _alloc_way_T_156 ^ alloc_way_chunks_158; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_158 = _alloc_way_T_157 ^ alloc_way_chunks_159; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_159 = _alloc_way_T_158 ^ alloc_way_chunks_160; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_160 = _alloc_way_T_159 ^ alloc_way_chunks_161; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_161 = _alloc_way_T_160 ^ alloc_way_chunks_162; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_162 = _alloc_way_T_161 ^ alloc_way_chunks_163; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_163 = _alloc_way_T_162 ^ alloc_way_chunks_164; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_164 = _alloc_way_T_163 ^ alloc_way_chunks_165; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_165 = _alloc_way_T_164 ^ alloc_way_chunks_166; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_166 = _alloc_way_T_165 ^ alloc_way_chunks_167; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_167 = _alloc_way_T_166 ^ alloc_way_chunks_168; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_168 = _alloc_way_T_167 ^ alloc_way_chunks_169; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_169 = _alloc_way_T_168 ^ alloc_way_chunks_170; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_170 = _alloc_way_T_169 ^ alloc_way_chunks_171; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_171 = _alloc_way_T_170 ^ alloc_way_chunks_172; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_172 = _alloc_way_T_171 ^ alloc_way_chunks_173; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_173 = _alloc_way_T_172 ^ alloc_way_chunks_174; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_174 = _alloc_way_T_173 ^ alloc_way_chunks_175; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_175 = _alloc_way_T_174 ^ alloc_way_chunks_176; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_176 = _alloc_way_T_175 ^ alloc_way_chunks_177; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_177 = _alloc_way_T_176 ^ alloc_way_chunks_178; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_178 = _alloc_way_T_177 ^ alloc_way_chunks_179; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_179 = _alloc_way_T_178 ^ alloc_way_chunks_180; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_180 = _alloc_way_T_179 ^ alloc_way_chunks_181; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_181 = _alloc_way_T_180 ^ alloc_way_chunks_182; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_182 = _alloc_way_T_181 ^ alloc_way_chunks_183; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_183 = _alloc_way_T_182 ^ alloc_way_chunks_184; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_184 = _alloc_way_T_183 ^ alloc_way_chunks_185; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_185 = _alloc_way_T_184 ^ alloc_way_chunks_186; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_186 = _alloc_way_T_185 ^ alloc_way_chunks_187; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_187 = _alloc_way_T_186 ^ alloc_way_chunks_188; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_188 = _alloc_way_T_187 ^ alloc_way_chunks_189; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_189 = _alloc_way_T_188 ^ alloc_way_chunks_190; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_190 = _alloc_way_T_189 ^ alloc_way_chunks_191; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_191 = _alloc_way_T_190 ^ alloc_way_chunks_192; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_192 = _alloc_way_T_191 ^ alloc_way_chunks_193; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_193 = _alloc_way_T_192 ^ alloc_way_chunks_194; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_194 = _alloc_way_T_193 ^ alloc_way_chunks_195; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_195 = _alloc_way_T_194 ^ alloc_way_chunks_196; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_196 = _alloc_way_T_195 ^ alloc_way_chunks_197; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_197 = _alloc_way_T_196 ^ alloc_way_chunks_198; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_198 = _alloc_way_T_197 ^ alloc_way_chunks_199; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_199 = _alloc_way_T_198 ^ alloc_way_chunks_200; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_200 = _alloc_way_T_199 ^ alloc_way_chunks_201; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_201 = _alloc_way_T_200 ^ alloc_way_chunks_202; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_202 = _alloc_way_T_201 ^ alloc_way_chunks_203; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_203 = _alloc_way_T_202 ^ alloc_way_chunks_204; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_204 = _alloc_way_T_203 ^ alloc_way_chunks_205; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_205 = _alloc_way_T_204 ^ alloc_way_chunks_206; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_206 = _alloc_way_T_205 ^ alloc_way_chunks_207; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_207 = _alloc_way_T_206 ^ alloc_way_chunks_208; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_208 = _alloc_way_T_207 ^ alloc_way_chunks_209; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_209 = _alloc_way_T_208 ^ alloc_way_chunks_210; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_210 = _alloc_way_T_209 ^ alloc_way_chunks_211; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_211 = _alloc_way_T_210 ^ alloc_way_chunks_212; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_212 = _alloc_way_T_211 ^ alloc_way_chunks_213; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_213 = _alloc_way_T_212 ^ alloc_way_chunks_214; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_214 = _alloc_way_T_213 ^ alloc_way_chunks_215; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_215 = _alloc_way_T_214 ^ alloc_way_chunks_216; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_216 = _alloc_way_T_215 ^ alloc_way_chunks_217; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_217 = _alloc_way_T_216 ^ alloc_way_chunks_218; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_218 = _alloc_way_T_217 ^ alloc_way_chunks_219; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_219 = _alloc_way_T_218 ^ alloc_way_chunks_220; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_220 = _alloc_way_T_219 ^ alloc_way_chunks_221; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_221 = _alloc_way_T_220 ^ alloc_way_chunks_222; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_222 = _alloc_way_T_221 ^ alloc_way_chunks_223; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_223 = _alloc_way_T_222 ^ alloc_way_chunks_224; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_224 = _alloc_way_T_223 ^ alloc_way_chunks_225; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_225 = _alloc_way_T_224 ^ alloc_way_chunks_226; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_226 = _alloc_way_T_225 ^ alloc_way_chunks_227; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_227 = _alloc_way_T_226 ^ alloc_way_chunks_228; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_228 = _alloc_way_T_227 ^ alloc_way_chunks_229; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_229 = _alloc_way_T_228 ^ alloc_way_chunks_230; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_230 = _alloc_way_T_229 ^ alloc_way_chunks_231; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_231 = _alloc_way_T_230 ^ alloc_way_chunks_232; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_232 = _alloc_way_T_231 ^ alloc_way_chunks_233; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_233 = _alloc_way_T_232 ^ alloc_way_chunks_234; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_234 = _alloc_way_T_233 ^ alloc_way_chunks_235; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_235 = _alloc_way_T_234 ^ alloc_way_chunks_236; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_236 = _alloc_way_T_235 ^ alloc_way_chunks_237; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_237 = _alloc_way_T_236 ^ alloc_way_chunks_238; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_238 = _alloc_way_T_237 ^ alloc_way_chunks_239; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_239 = _alloc_way_T_238 ^ alloc_way_chunks_240; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_240 = _alloc_way_T_239 ^ alloc_way_chunks_241; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_241 = _alloc_way_T_240 ^ alloc_way_chunks_242; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_242 = _alloc_way_T_241 ^ alloc_way_chunks_243; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_243 = _alloc_way_T_242 ^ alloc_way_chunks_244; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_244 = _alloc_way_T_243 ^ alloc_way_chunks_245; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_245 = _alloc_way_T_244 ^ alloc_way_chunks_246; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_246 = _alloc_way_T_245 ^ alloc_way_chunks_247; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_247 = _alloc_way_T_246 ^ alloc_way_chunks_248; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_248 = _alloc_way_T_247 ^ alloc_way_chunks_249; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_249 = _alloc_way_T_248 ^ alloc_way_chunks_250; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_250 = _alloc_way_T_249 ^ alloc_way_chunks_251; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_251 = _alloc_way_T_250 ^ alloc_way_chunks_252; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_252 = _alloc_way_T_251 ^ alloc_way_chunks_253; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_253 = _alloc_way_T_252 ^ alloc_way_chunks_254; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_254 = _alloc_way_T_253 ^ alloc_way_chunks_255; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_255 = _alloc_way_T_254 ^ alloc_way_chunks_256; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_256 = _alloc_way_T_255 ^ alloc_way_chunks_257; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_257 = _alloc_way_T_256 ^ alloc_way_chunks_258; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_258 = _alloc_way_T_257 ^ alloc_way_chunks_259; // @[btb.scala:127:14, :129:20] wire alloc_way = _alloc_way_T_258 ^ alloc_way_chunks_260; // @[btb.scala:127:14, :129:20] wire _s1_meta_write_way_T = s1_hits_0 | s1_hits_1; // @[btb.scala:87:55, :133:44] wire _s1_meta_write_way_T_1 = _s1_meta_write_way_T | s1_hits_2; // @[btb.scala:87:55, :133:44] wire _s1_meta_write_way_T_2 = _s1_meta_write_way_T_1 | s1_hits_3; // @[btb.scala:87:55, :133:44] wire [1:0] _s1_meta_write_way_T_3 = {s1_hit_ohs_0_1, s1_hit_ohs_0_0}; // @[btb.scala:82:27, :134:38] wire [1:0] _s1_meta_write_way_T_4 = {s1_hit_ohs_1_1, s1_hit_ohs_1_0}; // @[btb.scala:82:27, :134:38] wire [1:0] _s1_meta_write_way_T_5 = {s1_hit_ohs_2_1, s1_hit_ohs_2_0}; // @[btb.scala:82:27, :134:38] wire [1:0] _s1_meta_write_way_T_6 = {s1_hit_ohs_3_1, s1_hit_ohs_3_0}; // @[btb.scala:82:27, :134:38] wire [1:0] _s1_meta_write_way_T_7 = _s1_meta_write_way_T_3 | _s1_meta_write_way_T_4; // @[btb.scala:134:{38,54}] wire [1:0] _s1_meta_write_way_T_8 = _s1_meta_write_way_T_7 | _s1_meta_write_way_T_5; // @[btb.scala:134:{38,54}] wire [1:0] _s1_meta_write_way_T_9 = _s1_meta_write_way_T_8 | _s1_meta_write_way_T_6; // @[btb.scala:134:{38,54}] wire _s1_meta_write_way_T_10 = _s1_meta_write_way_T_9[0]; // @[OneHot.scala:48:45] wire _s1_meta_write_way_T_11 = _s1_meta_write_way_T_9[1]; // @[OneHot.scala:48:45] wire _s1_meta_write_way_T_12 = ~_s1_meta_write_way_T_10; // @[OneHot.scala:48:45] assign _s1_meta_write_way_T_13 = _s1_meta_write_way_T_2 ? _s1_meta_write_way_T_12 : alloc_way; // @[Mux.scala:50:70] assign s1_meta_write_way = _s1_meta_write_way_T_13; // @[btb.scala:52:21, :133:27] wire _s1_update_meta_T; // @[btb.scala:138:55] wire s1_update_meta_write_way; // @[btb.scala:138:55] assign _s1_update_meta_T = _s1_update_meta_WIRE; // @[btb.scala:138:55] assign _s1_update_meta_WIRE = s1_update_bits_meta[0]; // @[predictor.scala:184:30] assign s1_update_meta_write_way = _s1_update_meta_T; // @[btb.scala:138:55] wire [2:0] _new_offset_value_T_1 = {s1_update_bits_cfi_idx_bits, 1'h0}; // @[predictor.scala:184:30] wire [40:0] _new_offset_value_T_2 = {1'h0, s1_update_bits_pc} + {38'h0, _new_offset_value_T_1}; // @[predictor.scala:184:30] wire [39:0] _new_offset_value_T_3 = _new_offset_value_T_2[39:0]; // @[btb.scala:143:24] wire [39:0] _new_offset_value_T_4 = _new_offset_value_T_3; // @[btb.scala:143:{24,62}] wire [40:0] _new_offset_value_T_5 = {_new_offset_value_T[39], _new_offset_value_T} - {_new_offset_value_T_4[39], _new_offset_value_T_4}; // @[btb.scala:142:{49,56}, :143:62] wire [39:0] _new_offset_value_T_6 = _new_offset_value_T_5[39:0]; // @[btb.scala:142:56] wire [39:0] new_offset_value = _new_offset_value_T_6; // @[btb.scala:142:56] wire _offset_is_extended_T = $signed(new_offset_value) > 40'shFFF; // @[btb.scala:142:56, :144:46] wire _offset_is_extended_T_1 = $signed(new_offset_value) < -40'sh1000; // @[btb.scala:142:56, :145:46] wire offset_is_extended = _offset_is_extended_T | _offset_is_extended_T_1; // @[btb.scala:144:{46,65}, :145:46] wire s1_update_wbtb_data_extended = offset_is_extended; // @[btb.scala:144:65, :148:34] wire [12:0] s1_update_wbtb_data_offset; // @[btb.scala:148:34] assign s1_update_wbtb_data_offset = new_offset_value[12:0]; // @[btb.scala:142:56, :148:34, :150:32] wire [3:0] _s1_update_wbtb_mask_T = 4'h1 << s1_update_bits_cfi_idx_bits; // @[OneHot.scala:58:35] wire _s1_update_wbtb_mask_T_1 = s1_update_bits_cfi_idx_valid & s1_update_valid; // @[predictor.scala:184:30] wire _s1_update_wbtb_mask_T_2 = _s1_update_wbtb_mask_T_1 & s1_update_bits_cfi_taken; // @[predictor.scala:184:30] wire _GEN_7 = s1_update_bits_is_mispredict_update | s1_update_bits_is_repair_update; // @[predictor.scala:96:49, :184:30] wire _s1_update_wbtb_mask_T_3; // @[predictor.scala:96:49] assign _s1_update_wbtb_mask_T_3 = _GEN_7; // @[predictor.scala:96:49] wire _s1_update_wmeta_mask_T_1; // @[predictor.scala:96:49] assign _s1_update_wmeta_mask_T_1 = _GEN_7; // @[predictor.scala:96:49] wire _s1_update_wbtb_mask_T_4 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :184:30] wire _s1_update_wbtb_mask_T_5 = _s1_update_wbtb_mask_T_3 | _s1_update_wbtb_mask_T_4; // @[predictor.scala:94:50, :96:{49,69}] wire _s1_update_wbtb_mask_T_6 = ~_s1_update_wbtb_mask_T_5; // @[predictor.scala:96:{26,69}] wire _s1_update_wbtb_mask_T_7 = _s1_update_wbtb_mask_T_2 & _s1_update_wbtb_mask_T_6; // @[predictor.scala:96:26] wire [3:0] _s1_update_wbtb_mask_T_8 = {4{_s1_update_wbtb_mask_T_7}}; // @[btb.scala:152:{9,97}] wire [3:0] s1_update_wbtb_mask = _s1_update_wbtb_mask_T & _s1_update_wbtb_mask_T_8; // @[OneHot.scala:58:35] wire [3:0] _s1_update_wmeta_mask_T = s1_update_wbtb_mask | s1_update_bits_br_mask; // @[predictor.scala:184:30] wire _s1_update_wmeta_mask_T_2 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :184:30] wire _s1_update_wmeta_mask_T_3 = _s1_update_wmeta_mask_T_1 | _s1_update_wmeta_mask_T_2; // @[predictor.scala:94:50, :96:{49,69}] wire _s1_update_wmeta_mask_T_4 = ~_s1_update_wmeta_mask_T_3; // @[predictor.scala:96:{26,69}] wire _s1_update_wmeta_mask_T_5 = s1_update_valid & _s1_update_wmeta_mask_T_4; // @[predictor.scala:96:26, :184:30] wire [3:0] _s1_update_wmeta_mask_T_6 = {4{_s1_update_wmeta_mask_T_5}}; // @[btb.scala:155:{10,38}] wire [3:0] _s1_update_wmeta_mask_T_7 = {4{s1_update_valid}}; // @[predictor.scala:184:30] wire [3:0] _s1_update_wmeta_mask_T_8 = _s1_update_wmeta_mask_T_7 & s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] wire [3:0] _s1_update_wmeta_mask_T_9 = _s1_update_wmeta_mask_T_6 | _s1_update_wmeta_mask_T_8; // @[btb.scala:155:{10,74}, :156:40] wire [3:0] s1_update_wmeta_mask = _s1_update_wmeta_mask_T & _s1_update_wmeta_mask_T_9; // @[btb.scala:154:{52,78}, :155:74] wire _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:163:62] wire [28:0] _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:162:43] wire _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:163:62] wire [28:0] _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:162:43] wire _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:163:62] wire [28:0] _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:162:43] wire _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:163:62] wire [28:0] _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:162:43] wire s1_update_wmeta_data_0_is_br; // @[btb.scala:159:34] wire [28:0] s1_update_wmeta_data_0_tag; // @[btb.scala:159:34] wire s1_update_wmeta_data_1_is_br; // @[btb.scala:159:34] wire [28:0] s1_update_wmeta_data_1_tag; // @[btb.scala:159:34] wire s1_update_wmeta_data_2_is_br; // @[btb.scala:159:34] wire [28:0] s1_update_wmeta_data_2_tag; // @[btb.scala:159:34] wire s1_update_wmeta_data_3_is_br; // @[btb.scala:159:34] wire [28:0] s1_update_wmeta_data_3_tag; // @[btb.scala:159:34] wire _s1_update_wmeta_data_0_tag_T = s1_update_bits_btb_mispredicts[0]; // @[predictor.scala:184:30] wire [28:0] _s1_update_wmeta_data_0_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30] wire [28:0] _s1_update_wmeta_data_1_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30] wire [28:0] _s1_update_wmeta_data_2_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30] wire [28:0] _s1_update_wmeta_data_3_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30] assign _s1_update_wmeta_data_0_tag_T_2 = _s1_update_wmeta_data_0_tag_T ? 29'h0 : _s1_update_wmeta_data_0_tag_T_1; // @[btb.scala:162:{43,74,98}] assign s1_update_wmeta_data_0_tag = _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:159:34, :162:43] assign _s1_update_wmeta_data_0_is_br_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30] assign s1_update_wmeta_data_0_is_br = _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:159:34, :163:62] wire _s1_update_wmeta_data_1_tag_T = s1_update_bits_btb_mispredicts[1]; // @[predictor.scala:184:30] assign _s1_update_wmeta_data_1_tag_T_2 = _s1_update_wmeta_data_1_tag_T ? 29'h0 : _s1_update_wmeta_data_1_tag_T_1; // @[btb.scala:162:{43,74,98}] assign s1_update_wmeta_data_1_tag = _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:159:34, :162:43] assign _s1_update_wmeta_data_1_is_br_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30] assign s1_update_wmeta_data_1_is_br = _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:159:34, :163:62] wire _s1_update_wmeta_data_2_tag_T = s1_update_bits_btb_mispredicts[2]; // @[predictor.scala:184:30] assign _s1_update_wmeta_data_2_tag_T_2 = _s1_update_wmeta_data_2_tag_T ? 29'h0 : _s1_update_wmeta_data_2_tag_T_1; // @[btb.scala:162:{43,74,98}] assign s1_update_wmeta_data_2_tag = _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:159:34, :162:43] assign _s1_update_wmeta_data_2_is_br_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30] assign s1_update_wmeta_data_2_is_br = _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:159:34, :163:62] wire _s1_update_wmeta_data_3_tag_T = s1_update_bits_btb_mispredicts[3]; // @[predictor.scala:184:30] assign _s1_update_wmeta_data_3_tag_T_2 = _s1_update_wmeta_data_3_tag_T ? 29'h0 : _s1_update_wmeta_data_3_tag_T_1; // @[btb.scala:162:{43,74,98}] assign s1_update_wmeta_data_3_tag = _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:159:34, :162:43] assign _s1_update_wmeta_data_3_is_br_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30] assign s1_update_wmeta_data_3_is_br = _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:159:34, :163:62] wire btb_0_MPORT_en = doing_reset | ~s1_update_meta_write_way; // @[btb.scala:60:28, :138:55, :167:{23,51}] wire [6:0] _T_34 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:185:30] assign btb_0_MPORT_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_0_MPORT_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_0_MPORT_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_0_MPORT_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign meta_0_MPORT_1_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_0_MPORT_1_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_0_MPORT_1_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_0_MPORT_1_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] wire btb_1_MPORT_2_en = doing_reset | s1_update_meta_write_way; // @[btb.scala:60:28, :138:55, :167:23] wire [6:0] _T_69 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:185:30] assign btb_1_MPORT_2_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_1_MPORT_2_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_1_MPORT_2_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_1_MPORT_2_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign meta_1_MPORT_3_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_1_MPORT_3_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_1_MPORT_3_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_1_MPORT_3_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] always @(posedge clock) begin // @[btb.scala:23:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30] s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32] f3_meta_REG_write_way <= s1_meta_write_way; // @[btb.scala:52:21, :53:32] f3_meta_write_way <= f3_meta_REG_write_way; // @[btb.scala:53:{24,32}] REG <= s1_hits_0; // @[btb.scala:87:55, :104:18] io_resp_f2_0_predicted_pc_REG_valid <= s1_resp_0_valid; // @[btb.scala:78:23, :105:44] io_resp_f2_0_predicted_pc_REG_bits <= s1_resp_0_bits; // @[btb.scala:78:23, :105:44] io_resp_f2_0_is_br_REG <= s1_is_br_0; // @[btb.scala:79:23, :106:44] io_resp_f2_0_is_jal_REG <= s1_is_jal_0; // @[btb.scala:80:23, :107:44] REG_1 <= s1_is_jal_0; // @[btb.scala:80:23, :108:20] REG_2 <= s1_hits_0; // @[btb.scala:87:55, :112:26] REG_3 <= REG_2; // @[btb.scala:112:{18,26}] io_resp_f3_0_predicted_pc_REG_valid <= io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44] io_resp_f3_0_predicted_pc_REG_bits <= io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44] io_resp_f3_0_is_br_REG <= io_resp_f2_0_is_br_0; // @[btb.scala:23:7, :114:44] io_resp_f3_0_is_jal_REG <= io_resp_f2_0_is_jal_0; // @[btb.scala:23:7, :115:44] REG_4 <= s1_is_jal_0; // @[btb.scala:80:23, :116:28] REG_5 <= REG_4; // @[btb.scala:116:{20,28}] REG_6 <= s1_hits_1; // @[btb.scala:87:55, :104:18] io_resp_f2_1_predicted_pc_REG_valid <= s1_resp_1_valid; // @[btb.scala:78:23, :105:44] io_resp_f2_1_predicted_pc_REG_bits <= s1_resp_1_bits; // @[btb.scala:78:23, :105:44] io_resp_f2_1_is_br_REG <= s1_is_br_1; // @[btb.scala:79:23, :106:44] io_resp_f2_1_is_jal_REG <= s1_is_jal_1; // @[btb.scala:80:23, :107:44] REG_7 <= s1_is_jal_1; // @[btb.scala:80:23, :108:20] REG_8 <= s1_hits_1; // @[btb.scala:87:55, :112:26] REG_9 <= REG_8; // @[btb.scala:112:{18,26}] io_resp_f3_1_predicted_pc_REG_valid <= io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44] io_resp_f3_1_predicted_pc_REG_bits <= io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44] io_resp_f3_1_is_br_REG <= io_resp_f2_1_is_br_0; // @[btb.scala:23:7, :114:44] io_resp_f3_1_is_jal_REG <= io_resp_f2_1_is_jal_0; // @[btb.scala:23:7, :115:44] REG_10 <= s1_is_jal_1; // @[btb.scala:80:23, :116:28] REG_11 <= REG_10; // @[btb.scala:116:{20,28}] REG_12 <= s1_hits_2; // @[btb.scala:87:55, :104:18] io_resp_f2_2_predicted_pc_REG_valid <= s1_resp_2_valid; // @[btb.scala:78:23, :105:44] io_resp_f2_2_predicted_pc_REG_bits <= s1_resp_2_bits; // @[btb.scala:78:23, :105:44] io_resp_f2_2_is_br_REG <= s1_is_br_2; // @[btb.scala:79:23, :106:44] io_resp_f2_2_is_jal_REG <= s1_is_jal_2; // @[btb.scala:80:23, :107:44] REG_13 <= s1_is_jal_2; // @[btb.scala:80:23, :108:20] REG_14 <= s1_hits_2; // @[btb.scala:87:55, :112:26] REG_15 <= REG_14; // @[btb.scala:112:{18,26}] io_resp_f3_2_predicted_pc_REG_valid <= io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44] io_resp_f3_2_predicted_pc_REG_bits <= io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44] io_resp_f3_2_is_br_REG <= io_resp_f2_2_is_br_0; // @[btb.scala:23:7, :114:44] io_resp_f3_2_is_jal_REG <= io_resp_f2_2_is_jal_0; // @[btb.scala:23:7, :115:44] REG_16 <= s1_is_jal_2; // @[btb.scala:80:23, :116:28] REG_17 <= REG_16; // @[btb.scala:116:{20,28}] REG_18 <= s1_hits_3; // @[btb.scala:87:55, :104:18] io_resp_f2_3_predicted_pc_REG_valid <= s1_resp_3_valid; // @[btb.scala:78:23, :105:44] io_resp_f2_3_predicted_pc_REG_bits <= s1_resp_3_bits; // @[btb.scala:78:23, :105:44] io_resp_f2_3_is_br_REG <= s1_is_br_3; // @[btb.scala:79:23, :106:44] io_resp_f2_3_is_jal_REG <= s1_is_jal_3; // @[btb.scala:80:23, :107:44] REG_19 <= s1_is_jal_3; // @[btb.scala:80:23, :108:20] REG_20 <= s1_hits_3; // @[btb.scala:87:55, :112:26] REG_21 <= REG_20; // @[btb.scala:112:{18,26}] io_resp_f3_3_predicted_pc_REG_valid <= io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44] io_resp_f3_3_predicted_pc_REG_bits <= io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44] io_resp_f3_3_is_br_REG <= io_resp_f2_3_is_br_0; // @[btb.scala:23:7, :114:44] io_resp_f3_3_is_jal_REG <= io_resp_f2_3_is_jal_0; // @[btb.scala:23:7, :115:44] REG_22 <= s1_is_jal_3; // @[btb.scala:80:23, :116:28] REG_23 <= REG_22; // @[btb.scala:116:{20,28}] if (reset) begin // @[btb.scala:23:7] doing_reset <= 1'h1; // @[btb.scala:60:28] reset_idx <= 7'h0; // @[btb.scala:61:28] end else begin // @[btb.scala:23:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[btb.scala:60:28, :61:28, :63:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[btb.scala:61:28, :62:26] end always @(posedge) meta_0_2 meta_0 ( // @[btb.scala:65:47] .R0_addr (_s1_req_rmeta_T), // @[btb.scala:74:60] .R0_en (io_f0_valid_0), // @[btb.scala:23:7] .R0_clk (clock), .R0_data (_meta_0_R0_data), .W0_addr (_T_34), // @[btb.scala:169:12] .W0_en (btb_0_MPORT_en), // @[btb.scala:167:23] .W0_clk (clock), .W0_data ({meta_0_MPORT_1_data_3, meta_0_MPORT_1_data_2, meta_0_MPORT_1_data_1, meta_0_MPORT_1_data_0}), // @[btb.scala:65:47, :183:12] .W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:60:28, :154:78, :186:12] ); // @[btb.scala:65:47] meta_1_2 meta_1 ( // @[btb.scala:65:47] .R0_addr (_s1_req_rmeta_T_9), // @[btb.scala:74:60] .R0_en (io_f0_valid_0), // @[btb.scala:23:7] .R0_clk (clock), .R0_data (_meta_1_R0_data), .W0_addr (_T_69), // @[btb.scala:169:12] .W0_en (btb_1_MPORT_2_en), // @[btb.scala:167:23] .W0_clk (clock), .W0_data ({meta_1_MPORT_3_data_3, meta_1_MPORT_3_data_2, meta_1_MPORT_3_data_1, meta_1_MPORT_3_data_0}), // @[btb.scala:65:47, :183:12] .W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:60:28, :154:78, :186:12] ); // @[btb.scala:65:47] btb_0_2 btb_0 ( // @[btb.scala:66:47] .R0_addr (_s1_req_rbtb_T), // @[btb.scala:73:59] .R0_en (io_f0_valid_0), // @[btb.scala:23:7] .R0_clk (clock), .R0_data (_btb_0_R0_data), .W0_addr (_T_34), // @[btb.scala:169:12] .W0_en (btb_0_MPORT_en), // @[btb.scala:167:23] .W0_clk (clock), .W0_data ({btb_0_MPORT_data_3, btb_0_MPORT_data_2, btb_0_MPORT_data_1, btb_0_MPORT_data_0}), // @[btb.scala:66:47, :172:12] .W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:60:28, :151:58, :175:12] ); // @[btb.scala:66:47] btb_1_2 btb_1 ( // @[btb.scala:66:47] .R0_addr (_s1_req_rbtb_T_13), // @[btb.scala:73:59] .R0_en (io_f0_valid_0), // @[btb.scala:23:7] .R0_clk (clock), .R0_data (_btb_1_R0_data), .W0_addr (_T_69), // @[btb.scala:169:12] .W0_en (btb_1_MPORT_2_en), // @[btb.scala:167:23] .W0_clk (clock), .W0_data ({btb_1_MPORT_2_data_3, btb_1_MPORT_2_data_2, btb_1_MPORT_2_data_1, btb_1_MPORT_2_data_0}), // @[btb.scala:66:47, :172:12] .W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:60:28, :151:58, :175:12] ); // @[btb.scala:66:47] ebtb_2 ebtb ( // @[btb.scala:67:29] .R0_addr (_s1_req_rebtb_T), // @[btb.scala:75:31] .R0_en (io_f0_valid_0), // @[btb.scala:23:7] .R0_clk (clock), .R0_data (_ebtb_R0_data), .W0_addr (s1_update_idx[6:0]), // @[predictor.scala:185:30] .W0_en ((|s1_update_wbtb_mask) & offset_is_extended), // @[btb.scala:144:65, :151:58, :194:{29,37}] .W0_clk (clock), .W0_data (s1_update_bits_target) // @[predictor.scala:184:30] ); // @[btb.scala:67:29] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[btb.scala:23:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[btb.scala:23:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[btb.scala:23:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[btb.scala:23:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[btb.scala:23:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[btb.scala:23:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[btb.scala:23:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[btb.scala:23:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[btb.scala:23:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[btb.scala:23:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[btb.scala:23:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[btb.scala:23:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[btb.scala:23:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[btb.scala:23:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[btb.scala:23:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[btb.scala:23:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[btb.scala:23:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[btb.scala:23:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[btb.scala:23:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[btb.scala:23:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[btb.scala:23:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[btb.scala:23:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[btb.scala:23:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[btb.scala:23:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[btb.scala:23:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[btb.scala:23:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[btb.scala:23:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[btb.scala:23:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[btb.scala:23:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[btb.scala:23:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[btb.scala:23:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[btb.scala:23:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[btb.scala:23:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[btb.scala:23:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[btb.scala:23:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[btb.scala:23:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_f3_meta = io_f3_meta_0; // @[btb.scala:23:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SourceA_4 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} wire a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} inst io_a_q of Queue2_TLBundleA_a32d64s4k3z3c_4 connect io_a_q.clock, clock connect io_a_q.reset, reset connect io_a_q.io.enq.valid, a.valid connect io_a_q.io.enq.bits.corrupt, a.bits.corrupt connect io_a_q.io.enq.bits.data, a.bits.data connect io_a_q.io.enq.bits.mask, a.bits.mask connect io_a_q.io.enq.bits.address, a.bits.address connect io_a_q.io.enq.bits.source, a.bits.source connect io_a_q.io.enq.bits.size, a.bits.size connect io_a_q.io.enq.bits.param, a.bits.param connect io_a_q.io.enq.bits.opcode, a.bits.opcode connect a.ready, io_a_q.io.enq.ready connect io.a.bits, io_a_q.io.deq.bits connect io.a.valid, io_a_q.io.deq.valid connect io_a_q.io.deq.ready, io.a.ready connect io.req.ready, a.ready connect a.valid, io.req.valid node _T = eq(a.ready, UInt<1>(0h0)) node _T_1 = and(a.valid, _T) node _a_bits_opcode_T = mux(io.req.bits.block, UInt<3>(0h6), UInt<3>(0h7)) connect a.bits.opcode, _a_bits_opcode_T connect a.bits.param, io.req.bits.param connect a.bits.size, UInt<3>(0h6) connect a.bits.source, io.req.bits.source node a_bits_address_base_y = or(io.req.bits.tag, UInt<9>(0h0)) node _a_bits_address_base_T = shr(a_bits_address_base_y, 9) node _a_bits_address_base_T_1 = eq(_a_bits_address_base_T, UInt<1>(0h0)) node _a_bits_address_base_T_2 = asUInt(reset) node _a_bits_address_base_T_3 = eq(_a_bits_address_base_T_2, UInt<1>(0h0)) when _a_bits_address_base_T_3 : node _a_bits_address_base_T_4 = eq(_a_bits_address_base_T_1, UInt<1>(0h0)) when _a_bits_address_base_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : a_bits_address_base_printf assert(clock, _a_bits_address_base_T_1, UInt<1>(0h1), "") : a_bits_address_base_assert node _a_bits_address_base_T_5 = bits(a_bits_address_base_y, 8, 0) node a_bits_address_base_y_1 = or(io.req.bits.set, UInt<11>(0h0)) node _a_bits_address_base_T_6 = shr(a_bits_address_base_y_1, 11) node _a_bits_address_base_T_7 = eq(_a_bits_address_base_T_6, UInt<1>(0h0)) node _a_bits_address_base_T_8 = asUInt(reset) node _a_bits_address_base_T_9 = eq(_a_bits_address_base_T_8, UInt<1>(0h0)) when _a_bits_address_base_T_9 : node _a_bits_address_base_T_10 = eq(_a_bits_address_base_T_7, UInt<1>(0h0)) when _a_bits_address_base_T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : a_bits_address_base_printf_1 assert(clock, _a_bits_address_base_T_7, UInt<1>(0h1), "") : a_bits_address_base_assert_1 node _a_bits_address_base_T_11 = bits(a_bits_address_base_y_1, 10, 0) node a_bits_address_base_y_2 = or(UInt<1>(0h0), UInt<6>(0h0)) node _a_bits_address_base_T_12 = shr(a_bits_address_base_y_2, 6) node _a_bits_address_base_T_13 = eq(_a_bits_address_base_T_12, UInt<1>(0h0)) node _a_bits_address_base_T_14 = asUInt(reset) node _a_bits_address_base_T_15 = eq(_a_bits_address_base_T_14, UInt<1>(0h0)) when _a_bits_address_base_T_15 : node _a_bits_address_base_T_16 = eq(_a_bits_address_base_T_13, UInt<1>(0h0)) when _a_bits_address_base_T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : a_bits_address_base_printf_2 assert(clock, _a_bits_address_base_T_13, UInt<1>(0h1), "") : a_bits_address_base_assert_2 node _a_bits_address_base_T_17 = bits(a_bits_address_base_y_2, 5, 0) node a_bits_address_base_hi = cat(_a_bits_address_base_T_5, _a_bits_address_base_T_11) node a_bits_address_base = cat(a_bits_address_base_hi, _a_bits_address_base_T_17) node _a_bits_address_T = bits(a_bits_address_base, 0, 0) node _a_bits_address_T_1 = bits(a_bits_address_base, 1, 1) node _a_bits_address_T_2 = bits(a_bits_address_base, 2, 2) node _a_bits_address_T_3 = bits(a_bits_address_base, 3, 3) node _a_bits_address_T_4 = bits(a_bits_address_base, 4, 4) node _a_bits_address_T_5 = bits(a_bits_address_base, 5, 5) node _a_bits_address_T_6 = bits(a_bits_address_base, 6, 6) node _a_bits_address_T_7 = bits(a_bits_address_base, 7, 7) node _a_bits_address_T_8 = bits(a_bits_address_base, 8, 8) node _a_bits_address_T_9 = bits(a_bits_address_base, 9, 9) node _a_bits_address_T_10 = bits(a_bits_address_base, 10, 10) node _a_bits_address_T_11 = bits(a_bits_address_base, 11, 11) node _a_bits_address_T_12 = bits(a_bits_address_base, 12, 12) node _a_bits_address_T_13 = bits(a_bits_address_base, 13, 13) node _a_bits_address_T_14 = bits(a_bits_address_base, 14, 14) node _a_bits_address_T_15 = bits(a_bits_address_base, 15, 15) node _a_bits_address_T_16 = bits(a_bits_address_base, 16, 16) node _a_bits_address_T_17 = bits(a_bits_address_base, 17, 17) node _a_bits_address_T_18 = bits(a_bits_address_base, 18, 18) node _a_bits_address_T_19 = bits(a_bits_address_base, 19, 19) node _a_bits_address_T_20 = bits(a_bits_address_base, 20, 20) node _a_bits_address_T_21 = bits(a_bits_address_base, 21, 21) node _a_bits_address_T_22 = bits(a_bits_address_base, 22, 22) node _a_bits_address_T_23 = bits(a_bits_address_base, 23, 23) node _a_bits_address_T_24 = bits(a_bits_address_base, 24, 24) node _a_bits_address_T_25 = bits(a_bits_address_base, 25, 25) node a_bits_address_lo_lo_lo_lo = cat(_a_bits_address_T_1, _a_bits_address_T) node a_bits_address_lo_lo_lo_hi = cat(_a_bits_address_T_3, _a_bits_address_T_2) node a_bits_address_lo_lo_lo = cat(a_bits_address_lo_lo_lo_hi, a_bits_address_lo_lo_lo_lo) node a_bits_address_lo_lo_hi_lo = cat(_a_bits_address_T_5, _a_bits_address_T_4) node a_bits_address_lo_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node a_bits_address_lo_lo_hi = cat(a_bits_address_lo_lo_hi_hi, a_bits_address_lo_lo_hi_lo) node a_bits_address_lo_lo = cat(a_bits_address_lo_lo_hi, a_bits_address_lo_lo_lo) node a_bits_address_lo_hi_lo_lo = cat(_a_bits_address_T_6, UInt<1>(0h0)) node a_bits_address_lo_hi_lo_hi = cat(_a_bits_address_T_8, _a_bits_address_T_7) node a_bits_address_lo_hi_lo = cat(a_bits_address_lo_hi_lo_hi, a_bits_address_lo_hi_lo_lo) node a_bits_address_lo_hi_hi_lo = cat(_a_bits_address_T_10, _a_bits_address_T_9) node a_bits_address_lo_hi_hi_hi = cat(_a_bits_address_T_12, _a_bits_address_T_11) node a_bits_address_lo_hi_hi = cat(a_bits_address_lo_hi_hi_hi, a_bits_address_lo_hi_hi_lo) node a_bits_address_lo_hi = cat(a_bits_address_lo_hi_hi, a_bits_address_lo_hi_lo) node a_bits_address_lo = cat(a_bits_address_lo_hi, a_bits_address_lo_lo) node a_bits_address_hi_lo_lo_lo = cat(_a_bits_address_T_14, _a_bits_address_T_13) node a_bits_address_hi_lo_lo_hi = cat(_a_bits_address_T_16, _a_bits_address_T_15) node a_bits_address_hi_lo_lo = cat(a_bits_address_hi_lo_lo_hi, a_bits_address_hi_lo_lo_lo) node a_bits_address_hi_lo_hi_lo = cat(_a_bits_address_T_18, _a_bits_address_T_17) node a_bits_address_hi_lo_hi_hi = cat(_a_bits_address_T_20, _a_bits_address_T_19) node a_bits_address_hi_lo_hi = cat(a_bits_address_hi_lo_hi_hi, a_bits_address_hi_lo_hi_lo) node a_bits_address_hi_lo = cat(a_bits_address_hi_lo_hi, a_bits_address_hi_lo_lo) node a_bits_address_hi_hi_lo_lo = cat(_a_bits_address_T_22, _a_bits_address_T_21) node a_bits_address_hi_hi_lo_hi = cat(_a_bits_address_T_24, _a_bits_address_T_23) node a_bits_address_hi_hi_lo = cat(a_bits_address_hi_hi_lo_hi, a_bits_address_hi_hi_lo_lo) node a_bits_address_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node a_bits_address_hi_hi_hi_hi = cat(_a_bits_address_T_25, UInt<1>(0h0)) node a_bits_address_hi_hi_hi = cat(a_bits_address_hi_hi_hi_hi, a_bits_address_hi_hi_hi_lo) node a_bits_address_hi_hi = cat(a_bits_address_hi_hi_hi, a_bits_address_hi_hi_lo) node a_bits_address_hi = cat(a_bits_address_hi_hi, a_bits_address_hi_lo) node _a_bits_address_T_26 = cat(a_bits_address_hi, a_bits_address_lo) connect a.bits.address, _a_bits_address_T_26 node _a_bits_mask_T = not(UInt<8>(0h0)) connect a.bits.mask, _a_bits_mask_T connect a.bits.data, UInt<1>(0h0) connect a.bits.corrupt, UInt<1>(0h0)
module SourceA_4( // @[SourceA.scala:33:7] input clock, // @[SourceA.scala:33:7] input reset, // @[SourceA.scala:33:7] output io_req_ready, // @[SourceA.scala:35:14] input io_req_valid, // @[SourceA.scala:35:14] input [8:0] io_req_bits_tag, // @[SourceA.scala:35:14] input [10:0] io_req_bits_set, // @[SourceA.scala:35:14] input [2:0] io_req_bits_param, // @[SourceA.scala:35:14] input [3:0] io_req_bits_source, // @[SourceA.scala:35:14] input io_req_bits_block, // @[SourceA.scala:35:14] input io_a_ready, // @[SourceA.scala:35:14] output io_a_valid, // @[SourceA.scala:35:14] output [2:0] io_a_bits_opcode, // @[SourceA.scala:35:14] output [2:0] io_a_bits_param, // @[SourceA.scala:35:14] output [2:0] io_a_bits_size, // @[SourceA.scala:35:14] output [3:0] io_a_bits_source, // @[SourceA.scala:35:14] output [31:0] io_a_bits_address, // @[SourceA.scala:35:14] output [7:0] io_a_bits_mask, // @[SourceA.scala:35:14] output [63:0] io_a_bits_data, // @[SourceA.scala:35:14] output io_a_bits_corrupt // @[SourceA.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceA.scala:33:7] wire [8:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceA.scala:33:7] wire [10:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceA.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceA.scala:33:7] wire [3:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceA.scala:33:7] wire io_req_bits_block_0 = io_req_bits_block; // @[SourceA.scala:33:7] wire io_a_ready_0 = io_a_ready; // @[SourceA.scala:33:7] wire _a_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] a_bits_size = 3'h6; // @[SourceA.scala:43:15] wire [63:0] a_bits_data = 64'h0; // @[SourceA.scala:43:15] wire a_bits_corrupt = 1'h0; // @[SourceA.scala:43:15] wire _a_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _a_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _a_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _a_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _a_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _a_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire [5:0] a_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _a_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire [1:0] a_bits_address_lo_lo_hi_hi = 2'h0; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire a_ready; // @[SourceA.scala:43:15] wire [7:0] a_bits_mask = 8'hFF; // @[SourceA.scala:43:15] wire [7:0] _a_bits_mask_T = 8'hFF; // @[SourceA.scala:55:21] wire a_valid = io_req_valid_0; // @[SourceA.scala:33:7, :43:15] wire [8:0] a_bits_address_base_y = io_req_bits_tag_0; // @[SourceA.scala:33:7] wire [10:0] a_bits_address_base_y_1 = io_req_bits_set_0; // @[SourceA.scala:33:7] wire [2:0] a_bits_param = io_req_bits_param_0; // @[SourceA.scala:33:7, :43:15] wire [3:0] a_bits_source = io_req_bits_source_0; // @[SourceA.scala:33:7, :43:15] wire io_req_ready_0; // @[SourceA.scala:33:7] wire [2:0] io_a_bits_opcode_0; // @[SourceA.scala:33:7] wire [2:0] io_a_bits_param_0; // @[SourceA.scala:33:7] wire [2:0] io_a_bits_size_0; // @[SourceA.scala:33:7] wire [3:0] io_a_bits_source_0; // @[SourceA.scala:33:7] wire [31:0] io_a_bits_address_0; // @[SourceA.scala:33:7] wire [7:0] io_a_bits_mask_0; // @[SourceA.scala:33:7] wire [63:0] io_a_bits_data_0; // @[SourceA.scala:33:7] wire io_a_bits_corrupt_0; // @[SourceA.scala:33:7] wire io_a_valid_0; // @[SourceA.scala:33:7] assign io_req_ready_0 = a_ready; // @[SourceA.scala:33:7, :43:15] wire [2:0] _a_bits_opcode_T; // @[SourceA.scala:50:24] wire [31:0] _a_bits_address_T_26; // @[Parameters.scala:230:8] wire [2:0] a_bits_opcode; // @[SourceA.scala:43:15] wire [31:0] a_bits_address; // @[SourceA.scala:43:15] assign _a_bits_opcode_T = {2'h3, ~io_req_bits_block_0}; // @[SourceA.scala:33:7, :50:24] assign a_bits_opcode = _a_bits_opcode_T; // @[SourceA.scala:43:15, :50:24] wire [8:0] _a_bits_address_base_T_5 = a_bits_address_base_y; // @[Parameters.scala:221:15, :223:6] wire _a_bits_address_base_T_3 = ~_a_bits_address_base_T_2; // @[Parameters.scala:222:12] wire [10:0] _a_bits_address_base_T_11 = a_bits_address_base_y_1; // @[Parameters.scala:221:15, :223:6] wire _a_bits_address_base_T_9 = ~_a_bits_address_base_T_8; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_15 = ~_a_bits_address_base_T_14; // @[Parameters.scala:222:12] wire [19:0] a_bits_address_base_hi = {_a_bits_address_base_T_5, _a_bits_address_base_T_11}; // @[Parameters.scala:223:6, :227:19] wire [25:0] a_bits_address_base = {a_bits_address_base_hi, 6'h0}; // @[Parameters.scala:227:19] wire _a_bits_address_T = a_bits_address_base[0]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_1 = a_bits_address_base[1]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_2 = a_bits_address_base[2]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_3 = a_bits_address_base[3]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_4 = a_bits_address_base[4]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_5 = a_bits_address_base[5]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_6 = a_bits_address_base[6]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_7 = a_bits_address_base[7]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_8 = a_bits_address_base[8]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_9 = a_bits_address_base[9]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_10 = a_bits_address_base[10]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_11 = a_bits_address_base[11]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_12 = a_bits_address_base[12]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_13 = a_bits_address_base[13]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_14 = a_bits_address_base[14]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_15 = a_bits_address_base[15]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_16 = a_bits_address_base[16]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_17 = a_bits_address_base[17]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_18 = a_bits_address_base[18]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_19 = a_bits_address_base[19]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_20 = a_bits_address_base[20]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_21 = a_bits_address_base[21]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_22 = a_bits_address_base[22]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_23 = a_bits_address_base[23]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_24 = a_bits_address_base[24]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_25 = a_bits_address_base[25]; // @[Parameters.scala:227:19, :229:72] wire [1:0] a_bits_address_lo_lo_lo_lo = {_a_bits_address_T_1, _a_bits_address_T}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_lo_lo_lo_hi = {_a_bits_address_T_3, _a_bits_address_T_2}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_lo_lo_lo = {a_bits_address_lo_lo_lo_hi, a_bits_address_lo_lo_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_lo_lo_hi_lo = {_a_bits_address_T_5, _a_bits_address_T_4}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_lo_lo_hi = {2'h0, a_bits_address_lo_lo_hi_lo}; // @[Parameters.scala:230:8] wire [7:0] a_bits_address_lo_lo = {a_bits_address_lo_lo_hi, a_bits_address_lo_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_lo_hi_lo_lo = {_a_bits_address_T_6, 1'h0}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_lo_hi_lo_hi = {_a_bits_address_T_8, _a_bits_address_T_7}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_lo_hi_lo = {a_bits_address_lo_hi_lo_hi, a_bits_address_lo_hi_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_lo_hi_hi_lo = {_a_bits_address_T_10, _a_bits_address_T_9}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_lo_hi_hi_hi = {_a_bits_address_T_12, _a_bits_address_T_11}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_lo_hi_hi = {a_bits_address_lo_hi_hi_hi, a_bits_address_lo_hi_hi_lo}; // @[Parameters.scala:230:8] wire [7:0] a_bits_address_lo_hi = {a_bits_address_lo_hi_hi, a_bits_address_lo_hi_lo}; // @[Parameters.scala:230:8] wire [15:0] a_bits_address_lo = {a_bits_address_lo_hi, a_bits_address_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_hi_lo_lo_lo = {_a_bits_address_T_14, _a_bits_address_T_13}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_hi_lo_lo_hi = {_a_bits_address_T_16, _a_bits_address_T_15}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_hi_lo_lo = {a_bits_address_hi_lo_lo_hi, a_bits_address_hi_lo_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_hi_lo_hi_lo = {_a_bits_address_T_18, _a_bits_address_T_17}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_hi_lo_hi_hi = {_a_bits_address_T_20, _a_bits_address_T_19}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_hi_lo_hi = {a_bits_address_hi_lo_hi_hi, a_bits_address_hi_lo_hi_lo}; // @[Parameters.scala:230:8] wire [7:0] a_bits_address_hi_lo = {a_bits_address_hi_lo_hi, a_bits_address_hi_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_hi_hi_lo_lo = {_a_bits_address_T_22, _a_bits_address_T_21}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_hi_hi_lo_hi = {_a_bits_address_T_24, _a_bits_address_T_23}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_hi_hi_lo = {a_bits_address_hi_hi_lo_hi, a_bits_address_hi_hi_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_hi_hi_hi_hi = {_a_bits_address_T_25, 1'h0}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_hi_hi_hi = {a_bits_address_hi_hi_hi_hi, 2'h0}; // @[Parameters.scala:230:8] wire [7:0] a_bits_address_hi_hi = {a_bits_address_hi_hi_hi, a_bits_address_hi_hi_lo}; // @[Parameters.scala:230:8] wire [15:0] a_bits_address_hi = {a_bits_address_hi_hi, a_bits_address_hi_lo}; // @[Parameters.scala:230:8] assign _a_bits_address_T_26 = {a_bits_address_hi, a_bits_address_lo}; // @[Parameters.scala:230:8] assign a_bits_address = _a_bits_address_T_26; // @[SourceA.scala:43:15] Queue2_TLBundleA_a32d64s4k3z3c_4 io_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (a_ready), .io_enq_valid (a_valid), // @[SourceA.scala:43:15] .io_enq_bits_opcode (a_bits_opcode), // @[SourceA.scala:43:15] .io_enq_bits_param (a_bits_param), // @[SourceA.scala:43:15] .io_enq_bits_source (a_bits_source), // @[SourceA.scala:43:15] .io_enq_bits_address (a_bits_address), // @[SourceA.scala:43:15] .io_deq_ready (io_a_ready_0), // @[SourceA.scala:33:7] .io_deq_valid (io_a_valid_0), .io_deq_bits_opcode (io_a_bits_opcode_0), .io_deq_bits_param (io_a_bits_param_0), .io_deq_bits_size (io_a_bits_size_0), .io_deq_bits_source (io_a_bits_source_0), .io_deq_bits_address (io_a_bits_address_0), .io_deq_bits_mask (io_a_bits_mask_0), .io_deq_bits_data (io_a_bits_data_0), .io_deq_bits_corrupt (io_a_bits_corrupt_0) ); // @[Decoupled.scala:362:21] assign io_req_ready = io_req_ready_0; // @[SourceA.scala:33:7] assign io_a_valid = io_a_valid_0; // @[SourceA.scala:33:7] assign io_a_bits_opcode = io_a_bits_opcode_0; // @[SourceA.scala:33:7] assign io_a_bits_param = io_a_bits_param_0; // @[SourceA.scala:33:7] assign io_a_bits_size = io_a_bits_size_0; // @[SourceA.scala:33:7] assign io_a_bits_source = io_a_bits_source_0; // @[SourceA.scala:33:7] assign io_a_bits_address = io_a_bits_address_0; // @[SourceA.scala:33:7] assign io_a_bits_mask = io_a_bits_mask_0; // @[SourceA.scala:33:7] assign io_a_bits_data = io_a_bits_data_0; // @[SourceA.scala:33:7] assign io_a_bits_corrupt = io_a_bits_corrupt_0; // @[SourceA.scala:33:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_202 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_202( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_54 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_109 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_110 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_54( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_46 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_46( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_39 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_33 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_34 = and(_T_32, _T_33) node _T_35 = or(UInt<1>(0h0), _T_34) node _T_36 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_37 = cvt(_T_36) node _T_38 = and(_T_37, asSInt(UInt<17>(0h10000))) node _T_39 = asSInt(_T_38) node _T_40 = eq(_T_39, asSInt(UInt<1>(0h0))) node _T_41 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_42 = cvt(_T_41) node _T_43 = and(_T_42, asSInt(UInt<29>(0h10000000))) node _T_44 = asSInt(_T_43) node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0))) node _T_46 = or(_T_40, _T_45) node _T_47 = and(_T_35, _T_46) node _T_48 = or(UInt<1>(0h0), _T_47) node _T_49 = and(_T_31, _T_48) node _T_50 = asUInt(reset) node _T_51 = eq(_T_50, UInt<1>(0h0)) when _T_51 : node _T_52 = eq(_T_49, UInt<1>(0h0)) when _T_52 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_49, UInt<1>(0h1), "") : assert_2 node _T_53 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_54 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_55 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_56 = and(_T_54, _T_55) node _T_57 = or(UInt<1>(0h0), _T_56) node _T_58 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<17>(0h10000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<29>(0h10000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_62, _T_67) node _T_69 = and(_T_57, _T_68) node _T_70 = or(UInt<1>(0h0), _T_69) node _T_71 = and(_T_53, _T_70) node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(_T_71, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_71, UInt<1>(0h1), "") : assert_3 node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_78 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_78, UInt<1>(0h1), "") : assert_5 node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(is_aligned, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_85 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_85, UInt<1>(0h1), "") : assert_7 node _T_89 = not(io.in.a.bits.mask) node _T_90 = eq(_T_89, UInt<1>(0h0)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_90, UInt<1>(0h1), "") : assert_8 node _T_94 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_94, UInt<1>(0h1), "") : assert_9 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_102 = shr(io.in.a.bits.source, 4) node _T_103 = eq(_T_102, UInt<1>(0h0)) node _T_104 = leq(UInt<1>(0h0), uncommonBits_2) node _T_105 = and(_T_103, _T_104) node _T_106 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_107 = and(_T_105, _T_106) node _T_108 = and(_T_101, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_111 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_112 = and(_T_110, _T_111) node _T_113 = or(UInt<1>(0h0), _T_112) node _T_114 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<17>(0h10000))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_120 = cvt(_T_119) node _T_121 = and(_T_120, asSInt(UInt<29>(0h10000000))) node _T_122 = asSInt(_T_121) node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = or(_T_118, _T_123) node _T_125 = and(_T_113, _T_124) node _T_126 = or(UInt<1>(0h0), _T_125) node _T_127 = and(_T_109, _T_126) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_127, UInt<1>(0h1), "") : assert_10 node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_132 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_133 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_134 = and(_T_132, _T_133) node _T_135 = or(UInt<1>(0h0), _T_134) node _T_136 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<29>(0h10000000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = or(_T_140, _T_145) node _T_147 = and(_T_135, _T_146) node _T_148 = or(UInt<1>(0h0), _T_147) node _T_149 = and(_T_131, _T_148) node _T_150 = asUInt(reset) node _T_151 = eq(_T_150, UInt<1>(0h0)) when _T_151 : node _T_152 = eq(_T_149, UInt<1>(0h0)) when _T_152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_149, UInt<1>(0h1), "") : assert_11 node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_156 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_156, UInt<1>(0h1), "") : assert_13 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(is_aligned, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_163 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_163, UInt<1>(0h1), "") : assert_15 node _T_167 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_168 = asUInt(reset) node _T_169 = eq(_T_168, UInt<1>(0h0)) when _T_169 : node _T_170 = eq(_T_167, UInt<1>(0h0)) when _T_170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_167, UInt<1>(0h1), "") : assert_16 node _T_171 = not(io.in.a.bits.mask) node _T_172 = eq(_T_171, UInt<1>(0h0)) node _T_173 = asUInt(reset) node _T_174 = eq(_T_173, UInt<1>(0h0)) when _T_174 : node _T_175 = eq(_T_172, UInt<1>(0h0)) when _T_175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_172, UInt<1>(0h1), "") : assert_17 node _T_176 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_176, UInt<1>(0h1), "") : assert_18 node _T_180 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_180 : node _T_181 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_182 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_183 = and(_T_181, _T_182) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_184 = shr(io.in.a.bits.source, 4) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = leq(UInt<1>(0h0), uncommonBits_3) node _T_187 = and(_T_185, _T_186) node _T_188 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_189 = and(_T_187, _T_188) node _T_190 = and(_T_183, _T_189) node _T_191 = or(UInt<1>(0h0), _T_190) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_191, UInt<1>(0h1), "") : assert_19 node _T_195 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_196 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_197 = and(_T_195, _T_196) node _T_198 = or(UInt<1>(0h0), _T_197) node _T_199 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<17>(0h10000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<29>(0h10000000))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_203, _T_208) node _T_210 = and(_T_198, _T_209) node _T_211 = or(UInt<1>(0h0), _T_210) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_211, UInt<1>(0h1), "") : assert_20 node _T_215 = asUInt(reset) node _T_216 = eq(_T_215, UInt<1>(0h0)) when _T_216 : node _T_217 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_218 = asUInt(reset) node _T_219 = eq(_T_218, UInt<1>(0h0)) when _T_219 : node _T_220 = eq(is_aligned, UInt<1>(0h0)) when _T_220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_221 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_221, UInt<1>(0h1), "") : assert_23 node _T_225 = eq(io.in.a.bits.mask, mask) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_225, UInt<1>(0h1), "") : assert_24 node _T_229 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_229, UInt<1>(0h1), "") : assert_25 node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_233 : node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_237 = shr(io.in.a.bits.source, 4) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_4) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_242 = and(_T_240, _T_241) node _T_243 = and(_T_236, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_246 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_247 = and(_T_245, _T_246) node _T_248 = or(UInt<1>(0h0), _T_247) node _T_249 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_250 = cvt(_T_249) node _T_251 = and(_T_250, asSInt(UInt<17>(0h10000))) node _T_252 = asSInt(_T_251) node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0))) node _T_254 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_255 = cvt(_T_254) node _T_256 = and(_T_255, asSInt(UInt<29>(0h10000000))) node _T_257 = asSInt(_T_256) node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0))) node _T_259 = or(_T_253, _T_258) node _T_260 = and(_T_248, _T_259) node _T_261 = or(UInt<1>(0h0), _T_260) node _T_262 = and(_T_244, _T_261) node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_T_262, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_262, UInt<1>(0h1), "") : assert_26 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(is_aligned, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_272 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_273 = asUInt(reset) node _T_274 = eq(_T_273, UInt<1>(0h0)) when _T_274 : node _T_275 = eq(_T_272, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_272, UInt<1>(0h1), "") : assert_29 node _T_276 = eq(io.in.a.bits.mask, mask) node _T_277 = asUInt(reset) node _T_278 = eq(_T_277, UInt<1>(0h0)) when _T_278 : node _T_279 = eq(_T_276, UInt<1>(0h0)) when _T_279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_276, UInt<1>(0h1), "") : assert_30 node _T_280 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_280 : node _T_281 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_282 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_284 = shr(io.in.a.bits.source, 4) node _T_285 = eq(_T_284, UInt<1>(0h0)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_5) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_289 = and(_T_287, _T_288) node _T_290 = and(_T_283, _T_289) node _T_291 = or(UInt<1>(0h0), _T_290) node _T_292 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_293 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_294 = and(_T_292, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_307) node _T_309 = and(_T_291, _T_308) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_309, UInt<1>(0h1), "") : assert_31 node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(is_aligned, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_319 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_320 = asUInt(reset) node _T_321 = eq(_T_320, UInt<1>(0h0)) when _T_321 : node _T_322 = eq(_T_319, UInt<1>(0h0)) when _T_322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_319, UInt<1>(0h1), "") : assert_34 node _T_323 = not(mask) node _T_324 = and(io.in.a.bits.mask, _T_323) node _T_325 = eq(_T_324, UInt<1>(0h0)) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_325, UInt<1>(0h1), "") : assert_35 node _T_329 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_329 : node _T_330 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_331 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_332 = and(_T_330, _T_331) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_333 = shr(io.in.a.bits.source, 4) node _T_334 = eq(_T_333, UInt<1>(0h0)) node _T_335 = leq(UInt<1>(0h0), uncommonBits_6) node _T_336 = and(_T_334, _T_335) node _T_337 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_338 = and(_T_336, _T_337) node _T_339 = and(_T_332, _T_338) node _T_340 = or(UInt<1>(0h0), _T_339) node _T_341 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_342 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<29>(0h10000000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = or(_T_346, _T_351) node _T_353 = and(_T_341, _T_352) node _T_354 = or(UInt<1>(0h0), _T_353) node _T_355 = and(_T_340, _T_354) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_355, UInt<1>(0h1), "") : assert_36 node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(is_aligned, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_365 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(_T_365, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_365, UInt<1>(0h1), "") : assert_39 node _T_369 = eq(io.in.a.bits.mask, mask) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_369, UInt<1>(0h1), "") : assert_40 node _T_373 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_373 : node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_377 = shr(io.in.a.bits.source, 4) node _T_378 = eq(_T_377, UInt<1>(0h0)) node _T_379 = leq(UInt<1>(0h0), uncommonBits_7) node _T_380 = and(_T_378, _T_379) node _T_381 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_382 = and(_T_380, _T_381) node _T_383 = and(_T_376, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_386 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_387 = cvt(_T_386) node _T_388 = and(_T_387, asSInt(UInt<17>(0h10000))) node _T_389 = asSInt(_T_388) node _T_390 = eq(_T_389, asSInt(UInt<1>(0h0))) node _T_391 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_392 = cvt(_T_391) node _T_393 = and(_T_392, asSInt(UInt<29>(0h10000000))) node _T_394 = asSInt(_T_393) node _T_395 = eq(_T_394, asSInt(UInt<1>(0h0))) node _T_396 = or(_T_390, _T_395) node _T_397 = and(_T_385, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = and(_T_384, _T_398) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_399, UInt<1>(0h1), "") : assert_41 node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(is_aligned, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_409 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_409, UInt<1>(0h1), "") : assert_44 node _T_413 = eq(io.in.a.bits.mask, mask) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_413, UInt<1>(0h1), "") : assert_45 node _T_417 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_417 : node _T_418 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_419 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_421 = shr(io.in.a.bits.source, 4) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_8) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_426 = and(_T_424, _T_425) node _T_427 = and(_T_420, _T_426) node _T_428 = or(UInt<1>(0h0), _T_427) node _T_429 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_430 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_431 = cvt(_T_430) node _T_432 = and(_T_431, asSInt(UInt<17>(0h10000))) node _T_433 = asSInt(_T_432) node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0))) node _T_435 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_436 = cvt(_T_435) node _T_437 = and(_T_436, asSInt(UInt<29>(0h10000000))) node _T_438 = asSInt(_T_437) node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0))) node _T_440 = or(_T_434, _T_439) node _T_441 = and(_T_429, _T_440) node _T_442 = or(UInt<1>(0h0), _T_441) node _T_443 = and(_T_428, _T_442) node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_T_443, UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_443, UInt<1>(0h1), "") : assert_46 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(is_aligned, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_453 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_453, UInt<1>(0h1), "") : assert_49 node _T_457 = eq(io.in.a.bits.mask, mask) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_457, UInt<1>(0h1), "") : assert_50 node _T_461 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_461, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_465 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_465, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_469 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_469 : node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_473 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_473, UInt<1>(0h1), "") : assert_54 node _T_477 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_477, UInt<1>(0h1), "") : assert_55 node _T_481 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_481, UInt<1>(0h1), "") : assert_56 node _T_485 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_485, UInt<1>(0h1), "") : assert_57 node _T_489 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_489 : node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(sink_ok, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_496 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_496, UInt<1>(0h1), "") : assert_60 node _T_500 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_500, UInt<1>(0h1), "") : assert_61 node _T_504 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_504, UInt<1>(0h1), "") : assert_62 node _T_508 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_509 = asUInt(reset) node _T_510 = eq(_T_509, UInt<1>(0h0)) when _T_510 : node _T_511 = eq(_T_508, UInt<1>(0h0)) when _T_511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_508, UInt<1>(0h1), "") : assert_63 node _T_512 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_513 = or(UInt<1>(0h1), _T_512) node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_T_513, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_513, UInt<1>(0h1), "") : assert_64 node _T_517 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_517 : node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(sink_ok, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_524 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_524, UInt<1>(0h1), "") : assert_67 node _T_528 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_528, UInt<1>(0h1), "") : assert_68 node _T_532 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(_T_532, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_532, UInt<1>(0h1), "") : assert_69 node _T_536 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_537 = or(_T_536, io.in.d.bits.corrupt) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_537, UInt<1>(0h1), "") : assert_70 node _T_541 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_542 = or(UInt<1>(0h1), _T_541) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_542, UInt<1>(0h1), "") : assert_71 node _T_546 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_546 : node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_550 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_551 = asUInt(reset) node _T_552 = eq(_T_551, UInt<1>(0h0)) when _T_552 : node _T_553 = eq(_T_550, UInt<1>(0h0)) when _T_553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_550, UInt<1>(0h1), "") : assert_73 node _T_554 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(_T_554, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_554, UInt<1>(0h1), "") : assert_74 node _T_558 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_559 = or(UInt<1>(0h1), _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_559, UInt<1>(0h1), "") : assert_75 node _T_563 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_563 : node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_567 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_567, UInt<1>(0h1), "") : assert_77 node _T_571 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_572 = or(_T_571, io.in.d.bits.corrupt) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_572, UInt<1>(0h1), "") : assert_78 node _T_576 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_577 = or(UInt<1>(0h1), _T_576) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_577, UInt<1>(0h1), "") : assert_79 node _T_581 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_581 : node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_585 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_585, UInt<1>(0h1), "") : assert_81 node _T_589 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_590 = asUInt(reset) node _T_591 = eq(_T_590, UInt<1>(0h0)) when _T_591 : node _T_592 = eq(_T_589, UInt<1>(0h0)) when _T_592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_589, UInt<1>(0h1), "") : assert_82 node _T_593 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_594 = or(UInt<1>(0h1), _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_594, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_598 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(_T_598, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_598, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_9 = or(io.in.b.bits.source, UInt<4>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0) node _T_602 = shr(io.in.b.bits.source, 4) node _T_603 = eq(_T_602, UInt<1>(0h0)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_9) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_9, UInt<4>(0h9)) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(_T_607, UInt<1>(0h0)) node _T_609 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<1>(0h0))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_608, _T_613) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_614, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h10000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h10000000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<4>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 3, 0) node _legal_source_T = shr(io.in.b.bits.source, 4) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<4>(0h9)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) wire _legal_source_WIRE : UInt<1>[1] connect _legal_source_WIRE[0], _legal_source_T_5 node legal_source = eq(UInt<1>(0h0), io.in.b.bits.source) node _T_618 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_618 : node _T_619 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_620 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_621 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_622 = and(_T_620, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<29>(0h10000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = or(_T_628, _T_633) node _T_635 = and(_T_623, _T_634) node _T_636 = or(UInt<1>(0h0), _T_635) node _T_637 = and(_T_619, _T_636) node _T_638 = asUInt(reset) node _T_639 = eq(_T_638, UInt<1>(0h0)) when _T_639 : node _T_640 = eq(_T_637, UInt<1>(0h0)) when _T_640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_637, UInt<1>(0h1), "") : assert_86 node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(address_ok, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(legal_source, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(is_aligned_1, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_650 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_650, UInt<1>(0h1), "") : assert_90 node _T_654 = eq(io.in.b.bits.mask, mask_1) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_654, UInt<1>(0h1), "") : assert_91 node _T_658 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_659 = asUInt(reset) node _T_660 = eq(_T_659, UInt<1>(0h0)) when _T_660 : node _T_661 = eq(_T_658, UInt<1>(0h0)) when _T_661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_658, UInt<1>(0h1), "") : assert_92 node _T_662 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_662 : node _T_663 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_664 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_665 = and(_T_663, _T_664) node _T_666 = or(UInt<1>(0h0), _T_665) node _T_667 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<17>(0h10000))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_673 = cvt(_T_672) node _T_674 = and(_T_673, asSInt(UInt<29>(0h10000000))) node _T_675 = asSInt(_T_674) node _T_676 = eq(_T_675, asSInt(UInt<1>(0h0))) node _T_677 = or(_T_671, _T_676) node _T_678 = and(_T_666, _T_677) node _T_679 = or(UInt<1>(0h0), _T_678) node _T_680 = and(UInt<1>(0h0), _T_679) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_680, UInt<1>(0h1), "") : assert_93 node _T_684 = asUInt(reset) node _T_685 = eq(_T_684, UInt<1>(0h0)) when _T_685 : node _T_686 = eq(address_ok, UInt<1>(0h0)) when _T_686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(legal_source, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(is_aligned_1, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_693 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_693, UInt<1>(0h1), "") : assert_97 node _T_697 = eq(io.in.b.bits.mask, mask_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_697, UInt<1>(0h1), "") : assert_98 node _T_701 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_701, UInt<1>(0h1), "") : assert_99 node _T_705 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_705 : node _T_706 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_707 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_708 = and(_T_706, _T_707) node _T_709 = or(UInt<1>(0h0), _T_708) node _T_710 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<17>(0h10000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<29>(0h10000000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = or(_T_714, _T_719) node _T_721 = and(_T_709, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = and(UInt<1>(0h0), _T_722) node _T_724 = asUInt(reset) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(_T_723, UInt<1>(0h0)) when _T_726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_723, UInt<1>(0h1), "") : assert_100 node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(address_ok, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(legal_source, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned_1, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_736 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_736, UInt<1>(0h1), "") : assert_104 node _T_740 = eq(io.in.b.bits.mask, mask_1) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_740, UInt<1>(0h1), "") : assert_105 node _T_744 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_746 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<17>(0h10000))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<29>(0h10000000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = or(_T_753, _T_758) node _T_760 = and(_T_748, _T_759) node _T_761 = or(UInt<1>(0h0), _T_760) node _T_762 = and(UInt<1>(0h0), _T_761) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_762, UInt<1>(0h1), "") : assert_106 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(address_ok, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(legal_source, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(is_aligned_1, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_775 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_775, UInt<1>(0h1), "") : assert_110 node _T_779 = not(mask_1) node _T_780 = and(io.in.b.bits.mask, _T_779) node _T_781 = eq(_T_780, UInt<1>(0h0)) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_781, UInt<1>(0h1), "") : assert_111 node _T_785 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_785 : node _T_786 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_787 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_788 = and(_T_786, _T_787) node _T_789 = or(UInt<1>(0h0), _T_788) node _T_790 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<17>(0h10000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_794, _T_799) node _T_801 = and(_T_789, _T_800) node _T_802 = or(UInt<1>(0h0), _T_801) node _T_803 = and(UInt<1>(0h0), _T_802) node _T_804 = asUInt(reset) node _T_805 = eq(_T_804, UInt<1>(0h0)) when _T_805 : node _T_806 = eq(_T_803, UInt<1>(0h0)) when _T_806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_803, UInt<1>(0h1), "") : assert_112 node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(address_ok, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(legal_source, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_813 = asUInt(reset) node _T_814 = eq(_T_813, UInt<1>(0h0)) when _T_814 : node _T_815 = eq(is_aligned_1, UInt<1>(0h0)) when _T_815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_816 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_817 = asUInt(reset) node _T_818 = eq(_T_817, UInt<1>(0h0)) when _T_818 : node _T_819 = eq(_T_816, UInt<1>(0h0)) when _T_819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_816, UInt<1>(0h1), "") : assert_116 node _T_820 = eq(io.in.b.bits.mask, mask_1) node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(_T_820, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_820, UInt<1>(0h1), "") : assert_117 node _T_824 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_824 : node _T_825 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_826 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_827 = and(_T_825, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<17>(0h10000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<29>(0h10000000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = or(_T_833, _T_838) node _T_840 = and(_T_828, _T_839) node _T_841 = or(UInt<1>(0h0), _T_840) node _T_842 = and(UInt<1>(0h0), _T_841) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_842, UInt<1>(0h1), "") : assert_118 node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(address_ok, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_849 = asUInt(reset) node _T_850 = eq(_T_849, UInt<1>(0h0)) when _T_850 : node _T_851 = eq(legal_source, UInt<1>(0h0)) when _T_851 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_852 = asUInt(reset) node _T_853 = eq(_T_852, UInt<1>(0h0)) when _T_853 : node _T_854 = eq(is_aligned_1, UInt<1>(0h0)) when _T_854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_855 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(_T_855, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_855, UInt<1>(0h1), "") : assert_122 node _T_859 = eq(io.in.b.bits.mask, mask_1) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_859, UInt<1>(0h1), "") : assert_123 node _T_863 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_863 : node _T_864 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_865 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_866 = and(_T_864, _T_865) node _T_867 = or(UInt<1>(0h0), _T_866) node _T_868 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_869 = cvt(_T_868) node _T_870 = and(_T_869, asSInt(UInt<17>(0h10000))) node _T_871 = asSInt(_T_870) node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0))) node _T_873 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<29>(0h10000000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = or(_T_872, _T_877) node _T_879 = and(_T_867, _T_878) node _T_880 = or(UInt<1>(0h0), _T_879) node _T_881 = and(UInt<1>(0h0), _T_880) node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(_T_881, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_881, UInt<1>(0h1), "") : assert_124 node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(address_ok, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(legal_source, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(is_aligned_1, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_894 = eq(io.in.b.bits.mask, mask_1) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_894, UInt<1>(0h1), "") : assert_128 node _T_898 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_898, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_902 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_902, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0) node _source_ok_T_12 = shr(io.in.c.bits.source, 4) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h0)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<4>(0h9)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) wire _source_ok_WIRE_2 : UInt<1>[1] connect _source_ok_WIRE_2[0], _source_ok_T_17 node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h10000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h10000000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _uncommonBits_T_10 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_906 = shr(io.in.c.bits.source, 4) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = leq(UInt<1>(0h0), uncommonBits_10) node _T_909 = and(_T_907, _T_908) node _T_910 = leq(uncommonBits_10, UInt<4>(0h9)) node _T_911 = and(_T_909, _T_910) node _T_912 = eq(_T_911, UInt<1>(0h0)) node _T_913 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_914 = cvt(_T_913) node _T_915 = and(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = asSInt(_T_915) node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0))) node _T_918 = or(_T_912, _T_917) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_918, UInt<1>(0h1), "") : assert_131 node _T_922 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_922 : node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(address_ok_1, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_133 node _T_929 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_929, UInt<1>(0h1), "") : assert_134 node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(is_aligned_2, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_936 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_936, UInt<1>(0h1), "") : assert_136 node _T_940 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_940, UInt<1>(0h1), "") : assert_137 node _T_944 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_944 : node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(address_ok_1, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_139 node _T_951 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_951, UInt<1>(0h1), "") : assert_140 node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(is_aligned_2, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_958 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_958, UInt<1>(0h1), "") : assert_142 node _T_962 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_962 : node _T_963 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_964 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_965 = and(_T_963, _T_964) node _uncommonBits_T_11 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_966 = shr(io.in.c.bits.source, 4) node _T_967 = eq(_T_966, UInt<1>(0h0)) node _T_968 = leq(UInt<1>(0h0), uncommonBits_11) node _T_969 = and(_T_967, _T_968) node _T_970 = leq(uncommonBits_11, UInt<4>(0h9)) node _T_971 = and(_T_969, _T_970) node _T_972 = and(_T_965, _T_971) node _T_973 = or(UInt<1>(0h0), _T_972) node _T_974 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_975 = leq(io.in.c.bits.size, UInt<3>(0h6)) node _T_976 = and(_T_974, _T_975) node _T_977 = or(UInt<1>(0h0), _T_976) node _T_978 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_979 = cvt(_T_978) node _T_980 = and(_T_979, asSInt(UInt<17>(0h10000))) node _T_981 = asSInt(_T_980) node _T_982 = eq(_T_981, asSInt(UInt<1>(0h0))) node _T_983 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_984 = cvt(_T_983) node _T_985 = and(_T_984, asSInt(UInt<29>(0h10000000))) node _T_986 = asSInt(_T_985) node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0))) node _T_988 = or(_T_982, _T_987) node _T_989 = and(_T_977, _T_988) node _T_990 = or(UInt<1>(0h0), _T_989) node _T_991 = and(_T_973, _T_990) node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(_T_991, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_991, UInt<1>(0h1), "") : assert_143 node _T_995 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_996 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_997 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_998 = and(_T_996, _T_997) node _T_999 = or(UInt<1>(0h0), _T_998) node _T_1000 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1001 = cvt(_T_1000) node _T_1002 = and(_T_1001, asSInt(UInt<17>(0h10000))) node _T_1003 = asSInt(_T_1002) node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0))) node _T_1005 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1006 = cvt(_T_1005) node _T_1007 = and(_T_1006, asSInt(UInt<29>(0h10000000))) node _T_1008 = asSInt(_T_1007) node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0))) node _T_1010 = or(_T_1004, _T_1009) node _T_1011 = and(_T_999, _T_1010) node _T_1012 = or(UInt<1>(0h0), _T_1011) node _T_1013 = and(_T_995, _T_1012) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_144 node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_145 node _T_1020 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_146 node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1027 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_148 node _T_1031 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_149 node _T_1035 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1035 : node _T_1036 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1037 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1038 = and(_T_1036, _T_1037) node _uncommonBits_T_12 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0) node _T_1039 = shr(io.in.c.bits.source, 4) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) node _T_1041 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1042 = and(_T_1040, _T_1041) node _T_1043 = leq(uncommonBits_12, UInt<4>(0h9)) node _T_1044 = and(_T_1042, _T_1043) node _T_1045 = and(_T_1038, _T_1044) node _T_1046 = or(UInt<1>(0h0), _T_1045) node _T_1047 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1048 = leq(io.in.c.bits.size, UInt<3>(0h6)) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = or(UInt<1>(0h0), _T_1049) node _T_1051 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1052 = cvt(_T_1051) node _T_1053 = and(_T_1052, asSInt(UInt<17>(0h10000))) node _T_1054 = asSInt(_T_1053) node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0))) node _T_1056 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1057 = cvt(_T_1056) node _T_1058 = and(_T_1057, asSInt(UInt<29>(0h10000000))) node _T_1059 = asSInt(_T_1058) node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0))) node _T_1061 = or(_T_1055, _T_1060) node _T_1062 = and(_T_1050, _T_1061) node _T_1063 = or(UInt<1>(0h0), _T_1062) node _T_1064 = and(_T_1046, _T_1063) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_150 node _T_1068 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1069 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1070 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = or(UInt<1>(0h0), _T_1071) node _T_1073 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1074 = cvt(_T_1073) node _T_1075 = and(_T_1074, asSInt(UInt<17>(0h10000))) node _T_1076 = asSInt(_T_1075) node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0))) node _T_1078 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1079 = cvt(_T_1078) node _T_1080 = and(_T_1079, asSInt(UInt<29>(0h10000000))) node _T_1081 = asSInt(_T_1080) node _T_1082 = eq(_T_1081, asSInt(UInt<1>(0h0))) node _T_1083 = or(_T_1077, _T_1082) node _T_1084 = and(_T_1072, _T_1083) node _T_1085 = or(UInt<1>(0h0), _T_1084) node _T_1086 = and(_T_1068, _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_151 node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_152 node _T_1093 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1094 = asUInt(reset) node _T_1095 = eq(_T_1094, UInt<1>(0h0)) when _T_1095 : node _T_1096 = eq(_T_1093, UInt<1>(0h0)) when _T_1096 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1093, UInt<1>(0h1), "") : assert_153 node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1100 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_155 node _T_1104 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1104 : node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(address_ok_1, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_157 node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1114 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_159 node _T_1118 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_160 node _T_1122 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1122 : node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(address_ok_1, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_162 node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1132 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(_T_1132, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1132, UInt<1>(0h1), "") : assert_164 node _T_1136 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1136 : node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(address_ok_1, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_166 node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1146 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_168 node _T_1150 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1157 = eq(a_first, UInt<1>(0h0)) node _T_1158 = and(io.in.a.valid, _T_1157) when _T_1158 : node _T_1159 = eq(io.in.a.bits.opcode, opcode) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_171 node _T_1163 = eq(io.in.a.bits.param, param) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_172 node _T_1167 = eq(io.in.a.bits.size, size) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_173 node _T_1171 = eq(io.in.a.bits.source, source) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_174 node _T_1175 = eq(io.in.a.bits.address, address) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_175 node _T_1179 = and(io.in.a.ready, io.in.a.valid) node _T_1180 = and(_T_1179, a_first) when _T_1180 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1181 = eq(d_first, UInt<1>(0h0)) node _T_1182 = and(io.in.d.valid, _T_1181) when _T_1182 : node _T_1183 = eq(io.in.d.bits.opcode, opcode_1) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_176 node _T_1187 = eq(io.in.d.bits.param, param_1) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_177 node _T_1191 = eq(io.in.d.bits.size, size_1) node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(_T_1191, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_1191, UInt<1>(0h1), "") : assert_178 node _T_1195 = eq(io.in.d.bits.source, source_1) node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(_T_1195, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_1195, UInt<1>(0h1), "") : assert_179 node _T_1199 = eq(io.in.d.bits.sink, sink) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_180 node _T_1203 = eq(io.in.d.bits.denied, denied) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_181 node _T_1207 = and(io.in.d.ready, io.in.d.valid) node _T_1208 = and(_T_1207, d_first) when _T_1208 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_1209 = eq(b_first, UInt<1>(0h0)) node _T_1210 = and(io.in.b.valid, _T_1209) when _T_1210 : node _T_1211 = eq(io.in.b.bits.opcode, opcode_2) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_182 node _T_1215 = eq(io.in.b.bits.param, param_2) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_183 node _T_1219 = eq(io.in.b.bits.size, size_2) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_184 node _T_1223 = eq(io.in.b.bits.source, source_2) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_185 node _T_1227 = eq(io.in.b.bits.address, address_1) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_186 node _T_1231 = and(io.in.b.ready, io.in.b.valid) node _T_1232 = and(_T_1231, b_first) when _T_1232 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_1233 = eq(c_first, UInt<1>(0h0)) node _T_1234 = and(io.in.c.valid, _T_1233) when _T_1234 : node _T_1235 = eq(io.in.c.bits.opcode, opcode_3) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_187 node _T_1239 = eq(io.in.c.bits.param, param_3) node _T_1240 = asUInt(reset) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(_T_1239, UInt<1>(0h0)) when _T_1242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_1239, UInt<1>(0h1), "") : assert_188 node _T_1243 = eq(io.in.c.bits.size, size_3) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_189 node _T_1247 = eq(io.in.c.bits.source, source_3) node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(_T_1247, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_1247, UInt<1>(0h1), "") : assert_190 node _T_1251 = eq(io.in.c.bits.address, address_2) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_191 node _T_1255 = and(io.in.c.ready, io.in.c.valid) node _T_1256 = and(_T_1255, c_first) when _T_1256 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1257 = and(io.in.a.valid, a_first_1) node _T_1258 = and(_T_1257, UInt<1>(0h1)) when _T_1258 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1259 = and(io.in.a.ready, io.in.a.valid) node _T_1260 = and(_T_1259, a_first_1) node _T_1261 = and(_T_1260, UInt<1>(0h1)) when _T_1261 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1262 = dshr(inflight, io.in.a.bits.source) node _T_1263 = bits(_T_1262, 0, 0) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1268 = and(io.in.d.valid, d_first_1) node _T_1269 = and(_T_1268, UInt<1>(0h1)) node _T_1270 = eq(d_release_ack, UInt<1>(0h0)) node _T_1271 = and(_T_1269, _T_1270) when _T_1271 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1272 = and(io.in.d.ready, io.in.d.valid) node _T_1273 = and(_T_1272, d_first_1) node _T_1274 = and(_T_1273, UInt<1>(0h1)) node _T_1275 = eq(d_release_ack, UInt<1>(0h0)) node _T_1276 = and(_T_1274, _T_1275) when _T_1276 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1277 = and(io.in.d.valid, d_first_1) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = eq(d_release_ack, UInt<1>(0h0)) node _T_1280 = and(_T_1278, _T_1279) when _T_1280 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1281 = dshr(inflight, io.in.d.bits.source) node _T_1282 = bits(_T_1281, 0, 0) node _T_1283 = or(_T_1282, same_cycle_resp) node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(_T_1283, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_1283, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_1287 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1288 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_194 node _T_1293 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_195 else : node _T_1297 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1298 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1299 = or(_T_1297, _T_1298) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_196 node _T_1303 = eq(io.in.d.bits.size, a_size_lookup) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_197 node _T_1307 = and(io.in.d.valid, d_first_1) node _T_1308 = and(_T_1307, a_first_1) node _T_1309 = and(_T_1308, io.in.a.valid) node _T_1310 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = eq(d_release_ack, UInt<1>(0h0)) node _T_1313 = and(_T_1311, _T_1312) when _T_1313 : node _T_1314 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1315 = or(_T_1314, io.in.a.ready) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_198 node _T_1319 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1320 = orr(a_set_wo_ready) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) node _T_1322 = or(_T_1319, _T_1321) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_78 node _T_1326 = orr(inflight) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) node _T_1328 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1329 = or(_T_1327, _T_1328) node _T_1330 = lt(watchdog, plusarg_reader.out) node _T_1331 = or(_T_1329, _T_1330) node _T_1332 = asUInt(reset) node _T_1333 = eq(_T_1332, UInt<1>(0h0)) when _T_1333 : node _T_1334 = eq(_T_1331, UInt<1>(0h0)) when _T_1334 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_1331, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1335 = and(io.in.a.ready, io.in.a.valid) node _T_1336 = and(io.in.d.ready, io.in.d.valid) node _T_1337 = or(_T_1335, _T_1336) when _T_1337 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_1338 = and(io.in.c.valid, c_first_1) node _T_1339 = bits(io.in.c.bits.opcode, 2, 2) node _T_1340 = bits(io.in.c.bits.opcode, 1, 1) node _T_1341 = and(_T_1339, _T_1340) node _T_1342 = and(_T_1338, _T_1341) when _T_1342 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_1343 = and(io.in.c.ready, io.in.c.valid) node _T_1344 = and(_T_1343, c_first_1) node _T_1345 = bits(io.in.c.bits.opcode, 2, 2) node _T_1346 = bits(io.in.c.bits.opcode, 1, 1) node _T_1347 = and(_T_1345, _T_1346) node _T_1348 = and(_T_1344, _T_1347) when _T_1348 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_1349 = dshr(inflight_1, io.in.c.bits.source) node _T_1350 = bits(_T_1349, 0, 0) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1355 = and(io.in.d.valid, d_first_2) node _T_1356 = and(_T_1355, UInt<1>(0h1)) node _T_1357 = and(_T_1356, d_release_ack_1) when _T_1357 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1358 = and(io.in.d.ready, io.in.d.valid) node _T_1359 = and(_T_1358, d_first_2) node _T_1360 = and(_T_1359, UInt<1>(0h1)) node _T_1361 = and(_T_1360, d_release_ack_1) when _T_1361 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1362 = and(io.in.d.valid, d_first_2) node _T_1363 = and(_T_1362, UInt<1>(0h1)) node _T_1364 = and(_T_1363, d_release_ack_1) when _T_1364 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1365 = dshr(inflight_1, io.in.d.bits.source) node _T_1366 = bits(_T_1365, 0, 0) node _T_1367 = or(_T_1366, same_cycle_resp_1) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_1371 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_203 else : node _T_1375 = eq(io.in.d.bits.size, c_size_lookup) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_204 node _T_1379 = and(io.in.d.valid, d_first_2) node _T_1380 = and(_T_1379, c_first_1) node _T_1381 = and(_T_1380, io.in.c.valid) node _T_1382 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_1383 = and(_T_1381, _T_1382) node _T_1384 = and(_T_1383, d_release_ack_1) node _T_1385 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1386 = and(_T_1384, _T_1385) when _T_1386 : node _T_1387 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1388 = or(_T_1387, io.in.c.ready) node _T_1389 = asUInt(reset) node _T_1390 = eq(_T_1389, UInt<1>(0h0)) when _T_1390 : node _T_1391 = eq(_T_1388, UInt<1>(0h0)) when _T_1391 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_1388, UInt<1>(0h1), "") : assert_205 node _T_1392 = orr(c_set_wo_ready) when _T_1392 : node _T_1393 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(_T_1393, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_1393, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_79 node _T_1397 = orr(inflight_1) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) node _T_1399 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1400 = or(_T_1398, _T_1399) node _T_1401 = lt(watchdog_1, plusarg_reader_1.out) node _T_1402 = or(_T_1400, _T_1401) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_1406 = and(io.in.c.ready, io.in.c.valid) node _T_1407 = and(io.in.d.ready, io.in.d.valid) node _T_1408 = or(_T_1406, _T_1407) when _T_1408 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_1409 = and(io.in.d.ready, io.in.d.valid) node _T_1410 = and(_T_1409, d_first_3) node _T_1411 = bits(io.in.d.bits.opcode, 2, 2) node _T_1412 = bits(io.in.d.bits.opcode, 1, 1) node _T_1413 = eq(_T_1412, UInt<1>(0h0)) node _T_1414 = and(_T_1411, _T_1413) node _T_1415 = and(_T_1410, _T_1414) when _T_1415 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_1416 = dshr(inflight_2, io.in.d.bits.sink) node _T_1417 = bits(_T_1416, 0, 0) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(_T_1418, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_1418, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_1422 = and(io.in.e.ready, io.in.e.valid) node _T_1423 = and(_T_1422, UInt<1>(0h1)) node _T_1424 = and(_T_1423, UInt<1>(0h1)) when _T_1424 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_1425 = or(d_set, inflight_2) node _T_1426 = dshr(_T_1425, io.in.e.bits.sink) node _T_1427 = bits(_T_1426, 0, 0) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8
module TLMonitor_39( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode = 3'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h0; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_3 = 3'h0; // @[Misc.scala:202:34] wire [2:0] b_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _b_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _b_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire io_in_b_valid = 1'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _address_ok_T_4 = 1'h0; // @[Parameters.scala:137:59] wire _address_ok_T_9 = 1'h0; // @[Parameters.scala:137:59] wire _address_ok_WIRE_0 = 1'h0; // @[Parameters.scala:612:40] wire _address_ok_WIRE_1 = 1'h0; // @[Parameters.scala:612:40] wire address_ok = 1'h0; // @[Parameters.scala:636:64] wire mask_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire mask_sub_sub_bit_1 = 1'h0; // @[Misc.scala:210:26] wire _mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire mask_sub_bit_1 = 1'h0; // @[Misc.scala:210:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_0_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_2_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_2_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_3_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_3_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_bit_1 = 1'h0; // @[Misc.scala:210:26] wire mask_eq_9 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_9 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_10 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_10 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_11 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_11 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_12 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_12 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_13 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_13 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_14 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_14 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_15 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_15 = 1'h0; // @[Misc.scala:215:29] wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_12 = 1'h0; // @[Parameters.scala:54:10] wire _b_first_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_first_beats1_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _b_first_last_T = 1'h0; // @[Edges.scala:232:25] wire b_first_done = 1'h0; // @[Edges.scala:233:22] wire io_in_b_ready = 1'h1; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire is_aligned_1 = 1'h1; // @[Edges.scala:21:24] wire mask_sub_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire mask_sub_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire mask_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire mask_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire mask_eq_8 = 1'h1; // @[Misc.scala:214:27] wire _mask_acc_T_8 = 1'h1; // @[Misc.scala:215:38] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _legal_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _legal_source_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_13 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire b_first_beats1_opdata = 1'h1; // @[Edges.scala:97:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] b_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _b_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [31:0] io_in_b_bits_address = 32'h0; // @[Monitor.scala:36:7] wire [31:0] _is_aligned_T_1 = 32'h0; // @[Edges.scala:21:16] wire [3:0] io_in_b_bits_source = 4'h0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = 4'h0; // @[Parameters.scala:52:29] wire [3:0] uncommonBits_9 = 4'h0; // @[Parameters.scala:52:56] wire [3:0] mask_hi_1 = 4'h0; // @[Misc.scala:222:10] wire [3:0] _legal_source_uncommonBits_T = 4'h0; // @[Parameters.scala:52:29] wire [3:0] legal_source_uncommonBits = 4'h0; // @[Parameters.scala:52:56] wire [1:0] io_in_b_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h0; // @[OneHot.scala:64:49] wire [1:0] mask_lo_hi_1 = 2'h0; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h0; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h0; // @[Misc.scala:222:10] wire [7:0] io_in_b_bits_mask = 8'h0; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] _mask_sizeOH_T_5 = 3'h1; // @[OneHot.scala:65:27] wire [2:0] mask_sizeOH_1 = 3'h1; // @[Misc.scala:202:81] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [5:0] is_aligned_mask_1 = 6'h0; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h3F; // @[package.scala:243:76] wire [5:0] _b_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'h3F; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [7:0] mask_1 = 8'h1; // @[Misc.scala:222:10] wire [3:0] _mask_sizeOH_T_4 = 4'h1; // @[OneHot.scala:65:12] wire [3:0] mask_lo_1 = 4'h1; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h1; // @[Misc.scala:222:10] wire [32:0] _address_ok_T_6 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _address_ok_T_7 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _address_ok_T_8 = 33'h80000000; // @[Parameters.scala:137:46] wire [31:0] _address_ok_T_5 = 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _address_ok_T_1 = 33'h8000000; // @[Parameters.scala:137:41] wire [32:0] _address_ok_T_2 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _address_ok_T_3 = 33'h8000000; // @[Parameters.scala:137:46] wire [31:0] _address_ok_T = 32'h8000000; // @[Parameters.scala:137:31] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_16 = source_ok_uncommonBits_2 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_17 = _source_ok_T_16; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [12:0] _GEN_0 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_0; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_1 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [3:0] uncommonBits_10 = _uncommonBits_T_10; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_12 = _uncommonBits_T_12; // @[Parameters.scala:52:{29,56}] wire _T_1335 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1335; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1335; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1409 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1409; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1409; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1409; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_1409; // @[Decoupled.scala:51:35] wire [12:0] _GEN_2 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_2; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_2; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_2; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_2; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _T_1406 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_1406; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_1406; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [3:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_3 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_3; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_3; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_3; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_3; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_3; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_4 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1261 = _T_1335 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1261 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1261 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1261 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_5 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_5; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_5; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1261 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1261 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_6 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_6; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_6; // @[Monitor.scala:673:46, :783:46] wire _T_1307 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_7 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1307 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1276 = _T_1409 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1276 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1276 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1276 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] c_set; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [39:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [15:0] _GEN_8 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [15:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_8; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1348 = _T_1406 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_1348 ? _c_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_1348 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_1348 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [6:0] _GEN_9 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [6:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_9; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_9; // @[Monitor.scala:767:79, :768:77] wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_1348 ? _c_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [130:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_1348 ? _c_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1379 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1379 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1361 = _T_1409 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1361 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1361 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1361 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [9:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_1415 = _T_1409 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_10 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_10; // @[OneHot.scala:58:35] assign d_set = _T_1415 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _GEN_11 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_11; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_22 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, clock inst q of Queue3_EgressFlit_22 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<4>(0hb), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<4>(0he), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19) node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<4>(0hd), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22) node _q_io_enq_bits_ingress_id_T_24 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<6>(0h13), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_25 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<6>(0h10), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_26 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<6>(0ha), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_27 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<6>(0h19), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_28 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<6>(0h4), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_29 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<6>(0hd), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_30 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<6>(0h7), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_31 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<6>(0h16), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_32 = or(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25) node _q_io_enq_bits_ingress_id_T_33 = or(_q_io_enq_bits_ingress_id_T_32, _q_io_enq_bits_ingress_id_T_26) node _q_io_enq_bits_ingress_id_T_34 = or(_q_io_enq_bits_ingress_id_T_33, _q_io_enq_bits_ingress_id_T_27) node _q_io_enq_bits_ingress_id_T_35 = or(_q_io_enq_bits_ingress_id_T_34, _q_io_enq_bits_ingress_id_T_28) node _q_io_enq_bits_ingress_id_T_36 = or(_q_io_enq_bits_ingress_id_T_35, _q_io_enq_bits_ingress_id_T_29) node _q_io_enq_bits_ingress_id_T_37 = or(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_30) node _q_io_enq_bits_ingress_id_T_38 = or(_q_io_enq_bits_ingress_id_T_37, _q_io_enq_bits_ingress_id_T_31) wire _q_io_enq_bits_ingress_id_WIRE : UInt<6> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_38 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow
module EgressUnit_22( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [4:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_22 = io_in_0_bits_flow_ingress_node_id == 2'h1; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_8 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} cmem ram : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>} [16] wire _valids_WIRE : UInt<1>[16] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) connect _valids_WIRE[8], UInt<1>(0h0) connect _valids_WIRE[9], UInt<1>(0h0) connect _valids_WIRE[10], UInt<1>(0h0) connect _valids_WIRE[11], UInt<1>(0h0) connect _valids_WIRE[12], UInt<1>(0h0) connect _valids_WIRE[13], UInt<1>(0h0) connect _valids_WIRE[14], UInt<1>(0h0) connect _valids_WIRE[15], UInt<1>(0h0) regreset valids : UInt<1>[16], clock, reset, _valids_WIRE reg uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[16], clock regreset enq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset deq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _io_empty_T = eq(maybe_full, UInt<1>(0h0)) node _io_empty_T_1 = and(ptr_match, _io_empty_T) connect io.empty, _io_empty_T_1 node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> connect do_enq, _do_enq_T node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0)) node _do_deq_T_1 = or(io.deq.ready, _do_deq_T) node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0)) node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2) wire do_deq : UInt<1> connect do_deq, _do_deq_T_3 node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask) node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0)) node _valids_0_T_2 = eq(_valids_0_T_1, UInt<1>(0h0)) node _valids_0_T_3 = and(valids[0], _valids_0_T_2) node _valids_0_T_4 = and(io.flush, uops[0].uses_ldq) node _valids_0_T_5 = eq(_valids_0_T_4, UInt<1>(0h0)) node _valids_0_T_6 = and(_valids_0_T_3, _valids_0_T_5) connect valids[0], _valids_0_T_6 when valids[0] : node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T) connect uops[0].br_mask, _uops_0_br_mask_T_1 node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask) node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0)) node _valids_1_T_2 = eq(_valids_1_T_1, UInt<1>(0h0)) node _valids_1_T_3 = and(valids[1], _valids_1_T_2) node _valids_1_T_4 = and(io.flush, uops[1].uses_ldq) node _valids_1_T_5 = eq(_valids_1_T_4, UInt<1>(0h0)) node _valids_1_T_6 = and(_valids_1_T_3, _valids_1_T_5) connect valids[1], _valids_1_T_6 when valids[1] : node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T) connect uops[1].br_mask, _uops_1_br_mask_T_1 node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask) node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0)) node _valids_2_T_2 = eq(_valids_2_T_1, UInt<1>(0h0)) node _valids_2_T_3 = and(valids[2], _valids_2_T_2) node _valids_2_T_4 = and(io.flush, uops[2].uses_ldq) node _valids_2_T_5 = eq(_valids_2_T_4, UInt<1>(0h0)) node _valids_2_T_6 = and(_valids_2_T_3, _valids_2_T_5) connect valids[2], _valids_2_T_6 when valids[2] : node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T) connect uops[2].br_mask, _uops_2_br_mask_T_1 node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask) node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0)) node _valids_3_T_2 = eq(_valids_3_T_1, UInt<1>(0h0)) node _valids_3_T_3 = and(valids[3], _valids_3_T_2) node _valids_3_T_4 = and(io.flush, uops[3].uses_ldq) node _valids_3_T_5 = eq(_valids_3_T_4, UInt<1>(0h0)) node _valids_3_T_6 = and(_valids_3_T_3, _valids_3_T_5) connect valids[3], _valids_3_T_6 when valids[3] : node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T) connect uops[3].br_mask, _uops_3_br_mask_T_1 node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask) node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0)) node _valids_4_T_2 = eq(_valids_4_T_1, UInt<1>(0h0)) node _valids_4_T_3 = and(valids[4], _valids_4_T_2) node _valids_4_T_4 = and(io.flush, uops[4].uses_ldq) node _valids_4_T_5 = eq(_valids_4_T_4, UInt<1>(0h0)) node _valids_4_T_6 = and(_valids_4_T_3, _valids_4_T_5) connect valids[4], _valids_4_T_6 when valids[4] : node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T) connect uops[4].br_mask, _uops_4_br_mask_T_1 node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask) node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0)) node _valids_5_T_2 = eq(_valids_5_T_1, UInt<1>(0h0)) node _valids_5_T_3 = and(valids[5], _valids_5_T_2) node _valids_5_T_4 = and(io.flush, uops[5].uses_ldq) node _valids_5_T_5 = eq(_valids_5_T_4, UInt<1>(0h0)) node _valids_5_T_6 = and(_valids_5_T_3, _valids_5_T_5) connect valids[5], _valids_5_T_6 when valids[5] : node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T) connect uops[5].br_mask, _uops_5_br_mask_T_1 node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask) node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0)) node _valids_6_T_2 = eq(_valids_6_T_1, UInt<1>(0h0)) node _valids_6_T_3 = and(valids[6], _valids_6_T_2) node _valids_6_T_4 = and(io.flush, uops[6].uses_ldq) node _valids_6_T_5 = eq(_valids_6_T_4, UInt<1>(0h0)) node _valids_6_T_6 = and(_valids_6_T_3, _valids_6_T_5) connect valids[6], _valids_6_T_6 when valids[6] : node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T) connect uops[6].br_mask, _uops_6_br_mask_T_1 node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask) node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0)) node _valids_7_T_2 = eq(_valids_7_T_1, UInt<1>(0h0)) node _valids_7_T_3 = and(valids[7], _valids_7_T_2) node _valids_7_T_4 = and(io.flush, uops[7].uses_ldq) node _valids_7_T_5 = eq(_valids_7_T_4, UInt<1>(0h0)) node _valids_7_T_6 = and(_valids_7_T_3, _valids_7_T_5) connect valids[7], _valids_7_T_6 when valids[7] : node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T) connect uops[7].br_mask, _uops_7_br_mask_T_1 node _valids_8_T = and(io.brupdate.b1.mispredict_mask, uops[8].br_mask) node _valids_8_T_1 = neq(_valids_8_T, UInt<1>(0h0)) node _valids_8_T_2 = eq(_valids_8_T_1, UInt<1>(0h0)) node _valids_8_T_3 = and(valids[8], _valids_8_T_2) node _valids_8_T_4 = and(io.flush, uops[8].uses_ldq) node _valids_8_T_5 = eq(_valids_8_T_4, UInt<1>(0h0)) node _valids_8_T_6 = and(_valids_8_T_3, _valids_8_T_5) connect valids[8], _valids_8_T_6 when valids[8] : node _uops_8_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_8_br_mask_T_1 = and(uops[8].br_mask, _uops_8_br_mask_T) connect uops[8].br_mask, _uops_8_br_mask_T_1 node _valids_9_T = and(io.brupdate.b1.mispredict_mask, uops[9].br_mask) node _valids_9_T_1 = neq(_valids_9_T, UInt<1>(0h0)) node _valids_9_T_2 = eq(_valids_9_T_1, UInt<1>(0h0)) node _valids_9_T_3 = and(valids[9], _valids_9_T_2) node _valids_9_T_4 = and(io.flush, uops[9].uses_ldq) node _valids_9_T_5 = eq(_valids_9_T_4, UInt<1>(0h0)) node _valids_9_T_6 = and(_valids_9_T_3, _valids_9_T_5) connect valids[9], _valids_9_T_6 when valids[9] : node _uops_9_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_9_br_mask_T_1 = and(uops[9].br_mask, _uops_9_br_mask_T) connect uops[9].br_mask, _uops_9_br_mask_T_1 node _valids_10_T = and(io.brupdate.b1.mispredict_mask, uops[10].br_mask) node _valids_10_T_1 = neq(_valids_10_T, UInt<1>(0h0)) node _valids_10_T_2 = eq(_valids_10_T_1, UInt<1>(0h0)) node _valids_10_T_3 = and(valids[10], _valids_10_T_2) node _valids_10_T_4 = and(io.flush, uops[10].uses_ldq) node _valids_10_T_5 = eq(_valids_10_T_4, UInt<1>(0h0)) node _valids_10_T_6 = and(_valids_10_T_3, _valids_10_T_5) connect valids[10], _valids_10_T_6 when valids[10] : node _uops_10_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_10_br_mask_T_1 = and(uops[10].br_mask, _uops_10_br_mask_T) connect uops[10].br_mask, _uops_10_br_mask_T_1 node _valids_11_T = and(io.brupdate.b1.mispredict_mask, uops[11].br_mask) node _valids_11_T_1 = neq(_valids_11_T, UInt<1>(0h0)) node _valids_11_T_2 = eq(_valids_11_T_1, UInt<1>(0h0)) node _valids_11_T_3 = and(valids[11], _valids_11_T_2) node _valids_11_T_4 = and(io.flush, uops[11].uses_ldq) node _valids_11_T_5 = eq(_valids_11_T_4, UInt<1>(0h0)) node _valids_11_T_6 = and(_valids_11_T_3, _valids_11_T_5) connect valids[11], _valids_11_T_6 when valids[11] : node _uops_11_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_11_br_mask_T_1 = and(uops[11].br_mask, _uops_11_br_mask_T) connect uops[11].br_mask, _uops_11_br_mask_T_1 node _valids_12_T = and(io.brupdate.b1.mispredict_mask, uops[12].br_mask) node _valids_12_T_1 = neq(_valids_12_T, UInt<1>(0h0)) node _valids_12_T_2 = eq(_valids_12_T_1, UInt<1>(0h0)) node _valids_12_T_3 = and(valids[12], _valids_12_T_2) node _valids_12_T_4 = and(io.flush, uops[12].uses_ldq) node _valids_12_T_5 = eq(_valids_12_T_4, UInt<1>(0h0)) node _valids_12_T_6 = and(_valids_12_T_3, _valids_12_T_5) connect valids[12], _valids_12_T_6 when valids[12] : node _uops_12_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_12_br_mask_T_1 = and(uops[12].br_mask, _uops_12_br_mask_T) connect uops[12].br_mask, _uops_12_br_mask_T_1 node _valids_13_T = and(io.brupdate.b1.mispredict_mask, uops[13].br_mask) node _valids_13_T_1 = neq(_valids_13_T, UInt<1>(0h0)) node _valids_13_T_2 = eq(_valids_13_T_1, UInt<1>(0h0)) node _valids_13_T_3 = and(valids[13], _valids_13_T_2) node _valids_13_T_4 = and(io.flush, uops[13].uses_ldq) node _valids_13_T_5 = eq(_valids_13_T_4, UInt<1>(0h0)) node _valids_13_T_6 = and(_valids_13_T_3, _valids_13_T_5) connect valids[13], _valids_13_T_6 when valids[13] : node _uops_13_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_13_br_mask_T_1 = and(uops[13].br_mask, _uops_13_br_mask_T) connect uops[13].br_mask, _uops_13_br_mask_T_1 node _valids_14_T = and(io.brupdate.b1.mispredict_mask, uops[14].br_mask) node _valids_14_T_1 = neq(_valids_14_T, UInt<1>(0h0)) node _valids_14_T_2 = eq(_valids_14_T_1, UInt<1>(0h0)) node _valids_14_T_3 = and(valids[14], _valids_14_T_2) node _valids_14_T_4 = and(io.flush, uops[14].uses_ldq) node _valids_14_T_5 = eq(_valids_14_T_4, UInt<1>(0h0)) node _valids_14_T_6 = and(_valids_14_T_3, _valids_14_T_5) connect valids[14], _valids_14_T_6 when valids[14] : node _uops_14_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_14_br_mask_T_1 = and(uops[14].br_mask, _uops_14_br_mask_T) connect uops[14].br_mask, _uops_14_br_mask_T_1 node _valids_15_T = and(io.brupdate.b1.mispredict_mask, uops[15].br_mask) node _valids_15_T_1 = neq(_valids_15_T, UInt<1>(0h0)) node _valids_15_T_2 = eq(_valids_15_T_1, UInt<1>(0h0)) node _valids_15_T_3 = and(valids[15], _valids_15_T_2) node _valids_15_T_4 = and(io.flush, uops[15].uses_ldq) node _valids_15_T_5 = eq(_valids_15_T_4, UInt<1>(0h0)) node _valids_15_T_6 = and(_valids_15_T_3, _valids_15_T_5) connect valids[15], _valids_15_T_6 when valids[15] : node _uops_15_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_15_br_mask_T_1 = and(uops[15].br_mask, _uops_15_br_mask_T) connect uops[15].br_mask, _uops_15_br_mask_T_1 when do_enq : infer mport MPORT = ram[enq_ptr_value], clock connect MPORT, io.enq.bits connect valids[enq_ptr_value], UInt<1>(0h1) connect uops[enq_ptr_value], io.enq.bits.uop node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T) connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1 node wrap = eq(enq_ptr_value, UInt<4>(0hf)) node _value_T = add(enq_ptr_value, UInt<1>(0h1)) node _value_T_1 = tail(_value_T, 1) connect enq_ptr_value, _value_T_1 when do_deq : connect valids[deq_ptr_value], UInt<1>(0h0) node wrap_1 = eq(deq_ptr_value, UInt<4>(0hf)) node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) node _value_T_3 = tail(_value_T_2, 1) connect deq_ptr_value, _value_T_3 node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>} infer mport out_MPORT = ram[deq_ptr_value], clock connect out, out_MPORT connect out.uop, uops[deq_ptr_value] node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0)) node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value]) node _io_deq_valid_T_2 = and(io.brupdate.b1.mispredict_mask, out.uop.br_mask) node _io_deq_valid_T_3 = neq(_io_deq_valid_T_2, UInt<1>(0h0)) node _io_deq_valid_T_4 = eq(_io_deq_valid_T_3, UInt<1>(0h0)) node _io_deq_valid_T_5 = and(_io_deq_valid_T_1, _io_deq_valid_T_4) node _io_deq_valid_T_6 = and(io.flush, out.uop.uses_ldq) node _io_deq_valid_T_7 = eq(_io_deq_valid_T_6, UInt<1>(0h0)) node _io_deq_valid_T_8 = and(_io_deq_valid_T_5, _io_deq_valid_T_7) connect io.deq.valid, _io_deq_valid_T_8 connect io.deq.bits, out node _io_deq_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_deq_bits_uop_br_mask_T_1 = and(out.uop.br_mask, _io_deq_bits_uop_br_mask_T) connect io.deq.bits.uop.br_mask, _io_deq_bits_uop_br_mask_T_1 node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = and(maybe_full, ptr_match) node _io_count_T_1 = cat(_io_count_T, ptr_diff) connect io.count, _io_count_T_1
module BranchKillableQueue_8( // @[util.scala:448:7] input clock, // @[util.scala:448:7] input reset, // @[util.scala:448:7] output io_enq_ready, // @[util.scala:453:14] input io_enq_valid, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14] input io_enq_bits_uop_is_rvc, // @[util.scala:453:14] input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14] input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14] input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_is_br, // @[util.scala:453:14] input io_enq_bits_uop_is_jalr, // @[util.scala:453:14] input io_enq_bits_uop_is_jal, // @[util.scala:453:14] input io_enq_bits_uop_is_sfb, // @[util.scala:453:14] input [15:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14] input io_enq_bits_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14] input io_enq_bits_uop_taken, // @[util.scala:453:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_pdst, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs1, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs2, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs3, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ppred, // @[util.scala:453:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14] input io_enq_bits_uop_exception, // @[util.scala:453:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14] input io_enq_bits_uop_bypassable, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14] input io_enq_bits_uop_mem_signed, // @[util.scala:453:14] input io_enq_bits_uop_is_fence, // @[util.scala:453:14] input io_enq_bits_uop_is_fencei, // @[util.scala:453:14] input io_enq_bits_uop_is_amo, // @[util.scala:453:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14] input io_enq_bits_uop_uses_stq, // @[util.scala:453:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_enq_bits_uop_is_unique, // @[util.scala:453:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14] input io_enq_bits_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14] input io_enq_bits_uop_frs3_en, // @[util.scala:453:14] input io_enq_bits_uop_fp_val, // @[util.scala:453:14] input io_enq_bits_uop_fp_single, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14] input [39:0] io_enq_bits_addr, // @[util.scala:453:14] input [63:0] io_enq_bits_data, // @[util.scala:453:14] input io_enq_bits_is_hella, // @[util.scala:453:14] input io_enq_bits_tag_match, // @[util.scala:453:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:453:14] input [19:0] io_enq_bits_old_meta_tag, // @[util.scala:453:14] input [7:0] io_enq_bits_way_en, // @[util.scala:453:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:453:14] input io_deq_ready, // @[util.scala:453:14] output io_deq_valid, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14] output io_deq_bits_uop_is_rvc, // @[util.scala:453:14] output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14] output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14] output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_is_br, // @[util.scala:453:14] output io_deq_bits_uop_is_jalr, // @[util.scala:453:14] output io_deq_bits_uop_is_jal, // @[util.scala:453:14] output io_deq_bits_uop_is_sfb, // @[util.scala:453:14] output [15:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14] output io_deq_bits_uop_edge_inst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14] output io_deq_bits_uop_taken, // @[util.scala:453:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14] output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_pdst, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs1, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs2, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs3, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ppred, // @[util.scala:453:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14] output io_deq_bits_uop_exception, // @[util.scala:453:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14] output io_deq_bits_uop_bypassable, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14] output io_deq_bits_uop_mem_signed, // @[util.scala:453:14] output io_deq_bits_uop_is_fence, // @[util.scala:453:14] output io_deq_bits_uop_is_fencei, // @[util.scala:453:14] output io_deq_bits_uop_is_amo, // @[util.scala:453:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14] output io_deq_bits_uop_uses_stq, // @[util.scala:453:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] output io_deq_bits_uop_is_unique, // @[util.scala:453:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14] output io_deq_bits_uop_ldst_val, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14] output io_deq_bits_uop_frs3_en, // @[util.scala:453:14] output io_deq_bits_uop_fp_val, // @[util.scala:453:14] output io_deq_bits_uop_fp_single, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14] output [39:0] io_deq_bits_addr, // @[util.scala:453:14] output [63:0] io_deq_bits_data, // @[util.scala:453:14] output io_deq_bits_is_hella, // @[util.scala:453:14] output io_deq_bits_tag_match, // @[util.scala:453:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:453:14] output [19:0] io_deq_bits_old_meta_tag, // @[util.scala:453:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:453:14] input [15:0] io_brupdate_b1_resolve_mask, // @[util.scala:453:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_uopc, // @[util.scala:453:14] input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:453:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:453:14] input io_brupdate_b2_uop_is_rvc, // @[util.scala:453:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[util.scala:453:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_load, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[util.scala:453:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_brupdate_b2_uop_is_br, // @[util.scala:453:14] input io_brupdate_b2_uop_is_jalr, // @[util.scala:453:14] input io_brupdate_b2_uop_is_jal, // @[util.scala:453:14] input io_brupdate_b2_uop_is_sfb, // @[util.scala:453:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:453:14] input io_brupdate_b2_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:453:14] input io_brupdate_b2_uop_taken, // @[util.scala:453:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:453:14] input io_brupdate_b2_uop_prs1_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_prs2_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_prs3_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_ppred_busy, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:453:14] input io_brupdate_b2_uop_exception, // @[util.scala:453:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:453:14] input io_brupdate_b2_uop_bypassable, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:453:14] input io_brupdate_b2_uop_mem_signed, // @[util.scala:453:14] input io_brupdate_b2_uop_is_fence, // @[util.scala:453:14] input io_brupdate_b2_uop_is_fencei, // @[util.scala:453:14] input io_brupdate_b2_uop_is_amo, // @[util.scala:453:14] input io_brupdate_b2_uop_uses_ldq, // @[util.scala:453:14] input io_brupdate_b2_uop_uses_stq, // @[util.scala:453:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_brupdate_b2_uop_is_unique, // @[util.scala:453:14] input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:453:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:453:14] input io_brupdate_b2_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:453:14] input io_brupdate_b2_uop_frs3_en, // @[util.scala:453:14] input io_brupdate_b2_uop_fp_val, // @[util.scala:453:14] input io_brupdate_b2_uop_fp_single, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:453:14] input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:453:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:453:14] input io_brupdate_b2_valid, // @[util.scala:453:14] input io_brupdate_b2_mispredict, // @[util.scala:453:14] input io_brupdate_b2_taken, // @[util.scala:453:14] input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:453:14] input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:453:14] input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:453:14] input [20:0] io_brupdate_b2_target_offset, // @[util.scala:453:14] input io_flush, // @[util.scala:453:14] output io_empty // @[util.scala:453:14] ); wire [140:0] _ram_ext_R0_data; // @[util.scala:464:20] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7] wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7] wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7] wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7] wire [15:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7] wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7] wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7] wire [39:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:448:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:448:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:448:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:448:7] wire [19:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:448:7] wire [7:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:448:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:448:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[util.scala:448:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:448:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:448:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:448:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:448:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:448:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:448:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:448:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:448:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:448:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:448:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:448:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:448:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:448:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[util.scala:448:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:448:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:448:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:448:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:448:7] wire io_flush_0 = io_flush; // @[util.scala:448:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_3 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_4 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_5 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_6 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_7 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_8 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_9 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_10 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_11 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_12 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_13 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_14 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_15 = 1'h0; // @[util.scala:465:32] wire _io_enq_ready_T; // @[util.scala:504:19] wire _io_deq_valid_T_8; // @[util.scala:509:108] wire [6:0] out_uop_uopc; // @[util.scala:506:17] wire [31:0] out_uop_inst; // @[util.scala:506:17] wire [31:0] out_uop_debug_inst; // @[util.scala:506:17] wire out_uop_is_rvc; // @[util.scala:506:17] wire [39:0] out_uop_debug_pc; // @[util.scala:506:17] wire [2:0] out_uop_iq_type; // @[util.scala:506:17] wire [9:0] out_uop_fu_code; // @[util.scala:506:17] wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17] wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17] wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17] wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17] wire out_uop_ctrl_is_load; // @[util.scala:506:17] wire out_uop_ctrl_is_sta; // @[util.scala:506:17] wire out_uop_ctrl_is_std; // @[util.scala:506:17] wire [1:0] out_uop_iw_state; // @[util.scala:506:17] wire out_uop_iw_p1_poisoned; // @[util.scala:506:17] wire out_uop_iw_p2_poisoned; // @[util.scala:506:17] wire out_uop_is_br; // @[util.scala:506:17] wire out_uop_is_jalr; // @[util.scala:506:17] wire out_uop_is_jal; // @[util.scala:506:17] wire out_uop_is_sfb; // @[util.scala:506:17] wire [15:0] _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [3:0] out_uop_br_tag; // @[util.scala:506:17] wire [4:0] out_uop_ftq_idx; // @[util.scala:506:17] wire out_uop_edge_inst; // @[util.scala:506:17] wire [5:0] out_uop_pc_lob; // @[util.scala:506:17] wire out_uop_taken; // @[util.scala:506:17] wire [19:0] out_uop_imm_packed; // @[util.scala:506:17] wire [11:0] out_uop_csr_addr; // @[util.scala:506:17] wire [6:0] out_uop_rob_idx; // @[util.scala:506:17] wire [4:0] out_uop_ldq_idx; // @[util.scala:506:17] wire [4:0] out_uop_stq_idx; // @[util.scala:506:17] wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17] wire [6:0] out_uop_pdst; // @[util.scala:506:17] wire [6:0] out_uop_prs1; // @[util.scala:506:17] wire [6:0] out_uop_prs2; // @[util.scala:506:17] wire [6:0] out_uop_prs3; // @[util.scala:506:17] wire [4:0] out_uop_ppred; // @[util.scala:506:17] wire out_uop_prs1_busy; // @[util.scala:506:17] wire out_uop_prs2_busy; // @[util.scala:506:17] wire out_uop_prs3_busy; // @[util.scala:506:17] wire out_uop_ppred_busy; // @[util.scala:506:17] wire [6:0] out_uop_stale_pdst; // @[util.scala:506:17] wire out_uop_exception; // @[util.scala:506:17] wire [63:0] out_uop_exc_cause; // @[util.scala:506:17] wire out_uop_bypassable; // @[util.scala:506:17] wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17] wire [1:0] out_uop_mem_size; // @[util.scala:506:17] wire out_uop_mem_signed; // @[util.scala:506:17] wire out_uop_is_fence; // @[util.scala:506:17] wire out_uop_is_fencei; // @[util.scala:506:17] wire out_uop_is_amo; // @[util.scala:506:17] wire out_uop_uses_ldq; // @[util.scala:506:17] wire out_uop_uses_stq; // @[util.scala:506:17] wire out_uop_is_sys_pc2epc; // @[util.scala:506:17] wire out_uop_is_unique; // @[util.scala:506:17] wire out_uop_flush_on_commit; // @[util.scala:506:17] wire out_uop_ldst_is_rs1; // @[util.scala:506:17] wire [5:0] out_uop_ldst; // @[util.scala:506:17] wire [5:0] out_uop_lrs1; // @[util.scala:506:17] wire [5:0] out_uop_lrs2; // @[util.scala:506:17] wire [5:0] out_uop_lrs3; // @[util.scala:506:17] wire out_uop_ldst_val; // @[util.scala:506:17] wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17] wire out_uop_frs3_en; // @[util.scala:506:17] wire out_uop_fp_val; // @[util.scala:506:17] wire out_uop_fp_single; // @[util.scala:506:17] wire out_uop_xcpt_pf_if; // @[util.scala:506:17] wire out_uop_xcpt_ae_if; // @[util.scala:506:17] wire out_uop_xcpt_ma_if; // @[util.scala:506:17] wire out_uop_bp_debug_if; // @[util.scala:506:17] wire out_uop_bp_xcpt_if; // @[util.scala:506:17] wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17] wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17] wire [39:0] out_addr; // @[util.scala:506:17] wire [63:0] out_data; // @[util.scala:506:17] wire out_is_hella; // @[util.scala:506:17] wire out_tag_match; // @[util.scala:506:17] wire [1:0] out_old_meta_coh_state; // @[util.scala:506:17] wire [19:0] out_old_meta_tag; // @[util.scala:506:17] wire [7:0] out_way_en; // @[util.scala:506:17] wire [4:0] out_sdq_id; // @[util.scala:506:17] wire _io_empty_T_1; // @[util.scala:473:25] wire io_enq_ready_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] wire [15:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] wire io_deq_bits_uop_taken_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] wire io_deq_bits_uop_exception_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] wire [39:0] io_deq_bits_addr_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:448:7] wire io_deq_bits_is_hella_0; // @[util.scala:448:7] wire io_deq_bits_tag_match_0; // @[util.scala:448:7] wire [7:0] io_deq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:448:7] wire io_deq_valid_0; // @[util.scala:448:7] wire io_empty_0; // @[util.scala:448:7] wire [3:0] io_count; // @[util.scala:448:7] assign out_addr = _ram_ext_R0_data[39:0]; // @[util.scala:464:20, :506:17] assign out_data = _ram_ext_R0_data[103:40]; // @[util.scala:464:20, :506:17] assign out_is_hella = _ram_ext_R0_data[104]; // @[util.scala:464:20, :506:17] assign out_tag_match = _ram_ext_R0_data[105]; // @[util.scala:464:20, :506:17] assign out_old_meta_coh_state = _ram_ext_R0_data[107:106]; // @[util.scala:464:20, :506:17] assign out_old_meta_tag = _ram_ext_R0_data[127:108]; // @[util.scala:464:20, :506:17] assign out_way_en = _ram_ext_R0_data[135:128]; // @[util.scala:464:20, :506:17] assign out_sdq_id = _ram_ext_R0_data[140:136]; // @[util.scala:464:20, :506:17] reg valids_0; // @[util.scala:465:24] reg valids_1; // @[util.scala:465:24] reg valids_2; // @[util.scala:465:24] reg valids_3; // @[util.scala:465:24] reg valids_4; // @[util.scala:465:24] reg valids_5; // @[util.scala:465:24] reg valids_6; // @[util.scala:465:24] reg valids_7; // @[util.scala:465:24] reg valids_8; // @[util.scala:465:24] reg valids_9; // @[util.scala:465:24] reg valids_10; // @[util.scala:465:24] reg valids_11; // @[util.scala:465:24] reg valids_12; // @[util.scala:465:24] reg valids_13; // @[util.scala:465:24] reg valids_14; // @[util.scala:465:24] reg valids_15; // @[util.scala:465:24] reg [6:0] uops_0_uopc; // @[util.scala:466:20] reg [31:0] uops_0_inst; // @[util.scala:466:20] reg [31:0] uops_0_debug_inst; // @[util.scala:466:20] reg uops_0_is_rvc; // @[util.scala:466:20] reg [39:0] uops_0_debug_pc; // @[util.scala:466:20] reg [2:0] uops_0_iq_type; // @[util.scala:466:20] reg [9:0] uops_0_fu_code; // @[util.scala:466:20] reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20] reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_0_ctrl_is_load; // @[util.scala:466:20] reg uops_0_ctrl_is_sta; // @[util.scala:466:20] reg uops_0_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_0_iw_state; // @[util.scala:466:20] reg uops_0_iw_p1_poisoned; // @[util.scala:466:20] reg uops_0_iw_p2_poisoned; // @[util.scala:466:20] reg uops_0_is_br; // @[util.scala:466:20] reg uops_0_is_jalr; // @[util.scala:466:20] reg uops_0_is_jal; // @[util.scala:466:20] reg uops_0_is_sfb; // @[util.scala:466:20] reg [15:0] uops_0_br_mask; // @[util.scala:466:20] reg [3:0] uops_0_br_tag; // @[util.scala:466:20] reg [4:0] uops_0_ftq_idx; // @[util.scala:466:20] reg uops_0_edge_inst; // @[util.scala:466:20] reg [5:0] uops_0_pc_lob; // @[util.scala:466:20] reg uops_0_taken; // @[util.scala:466:20] reg [19:0] uops_0_imm_packed; // @[util.scala:466:20] reg [11:0] uops_0_csr_addr; // @[util.scala:466:20] reg [6:0] uops_0_rob_idx; // @[util.scala:466:20] reg [4:0] uops_0_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_0_stq_idx; // @[util.scala:466:20] reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_0_pdst; // @[util.scala:466:20] reg [6:0] uops_0_prs1; // @[util.scala:466:20] reg [6:0] uops_0_prs2; // @[util.scala:466:20] reg [6:0] uops_0_prs3; // @[util.scala:466:20] reg [4:0] uops_0_ppred; // @[util.scala:466:20] reg uops_0_prs1_busy; // @[util.scala:466:20] reg uops_0_prs2_busy; // @[util.scala:466:20] reg uops_0_prs3_busy; // @[util.scala:466:20] reg uops_0_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_0_stale_pdst; // @[util.scala:466:20] reg uops_0_exception; // @[util.scala:466:20] reg [63:0] uops_0_exc_cause; // @[util.scala:466:20] reg uops_0_bypassable; // @[util.scala:466:20] reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_0_mem_size; // @[util.scala:466:20] reg uops_0_mem_signed; // @[util.scala:466:20] reg uops_0_is_fence; // @[util.scala:466:20] reg uops_0_is_fencei; // @[util.scala:466:20] reg uops_0_is_amo; // @[util.scala:466:20] reg uops_0_uses_ldq; // @[util.scala:466:20] reg uops_0_uses_stq; // @[util.scala:466:20] reg uops_0_is_sys_pc2epc; // @[util.scala:466:20] reg uops_0_is_unique; // @[util.scala:466:20] reg uops_0_flush_on_commit; // @[util.scala:466:20] reg uops_0_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_0_ldst; // @[util.scala:466:20] reg [5:0] uops_0_lrs1; // @[util.scala:466:20] reg [5:0] uops_0_lrs2; // @[util.scala:466:20] reg [5:0] uops_0_lrs3; // @[util.scala:466:20] reg uops_0_ldst_val; // @[util.scala:466:20] reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20] reg uops_0_frs3_en; // @[util.scala:466:20] reg uops_0_fp_val; // @[util.scala:466:20] reg uops_0_fp_single; // @[util.scala:466:20] reg uops_0_xcpt_pf_if; // @[util.scala:466:20] reg uops_0_xcpt_ae_if; // @[util.scala:466:20] reg uops_0_xcpt_ma_if; // @[util.scala:466:20] reg uops_0_bp_debug_if; // @[util.scala:466:20] reg uops_0_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_1_uopc; // @[util.scala:466:20] reg [31:0] uops_1_inst; // @[util.scala:466:20] reg [31:0] uops_1_debug_inst; // @[util.scala:466:20] reg uops_1_is_rvc; // @[util.scala:466:20] reg [39:0] uops_1_debug_pc; // @[util.scala:466:20] reg [2:0] uops_1_iq_type; // @[util.scala:466:20] reg [9:0] uops_1_fu_code; // @[util.scala:466:20] reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20] reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_1_ctrl_is_load; // @[util.scala:466:20] reg uops_1_ctrl_is_sta; // @[util.scala:466:20] reg uops_1_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_1_iw_state; // @[util.scala:466:20] reg uops_1_iw_p1_poisoned; // @[util.scala:466:20] reg uops_1_iw_p2_poisoned; // @[util.scala:466:20] reg uops_1_is_br; // @[util.scala:466:20] reg uops_1_is_jalr; // @[util.scala:466:20] reg uops_1_is_jal; // @[util.scala:466:20] reg uops_1_is_sfb; // @[util.scala:466:20] reg [15:0] uops_1_br_mask; // @[util.scala:466:20] reg [3:0] uops_1_br_tag; // @[util.scala:466:20] reg [4:0] uops_1_ftq_idx; // @[util.scala:466:20] reg uops_1_edge_inst; // @[util.scala:466:20] reg [5:0] uops_1_pc_lob; // @[util.scala:466:20] reg uops_1_taken; // @[util.scala:466:20] reg [19:0] uops_1_imm_packed; // @[util.scala:466:20] reg [11:0] uops_1_csr_addr; // @[util.scala:466:20] reg [6:0] uops_1_rob_idx; // @[util.scala:466:20] reg [4:0] uops_1_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_1_stq_idx; // @[util.scala:466:20] reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_1_pdst; // @[util.scala:466:20] reg [6:0] uops_1_prs1; // @[util.scala:466:20] reg [6:0] uops_1_prs2; // @[util.scala:466:20] reg [6:0] uops_1_prs3; // @[util.scala:466:20] reg [4:0] uops_1_ppred; // @[util.scala:466:20] reg uops_1_prs1_busy; // @[util.scala:466:20] reg uops_1_prs2_busy; // @[util.scala:466:20] reg uops_1_prs3_busy; // @[util.scala:466:20] reg uops_1_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_1_stale_pdst; // @[util.scala:466:20] reg uops_1_exception; // @[util.scala:466:20] reg [63:0] uops_1_exc_cause; // @[util.scala:466:20] reg uops_1_bypassable; // @[util.scala:466:20] reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_1_mem_size; // @[util.scala:466:20] reg uops_1_mem_signed; // @[util.scala:466:20] reg uops_1_is_fence; // @[util.scala:466:20] reg uops_1_is_fencei; // @[util.scala:466:20] reg uops_1_is_amo; // @[util.scala:466:20] reg uops_1_uses_ldq; // @[util.scala:466:20] reg uops_1_uses_stq; // @[util.scala:466:20] reg uops_1_is_sys_pc2epc; // @[util.scala:466:20] reg uops_1_is_unique; // @[util.scala:466:20] reg uops_1_flush_on_commit; // @[util.scala:466:20] reg uops_1_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_1_ldst; // @[util.scala:466:20] reg [5:0] uops_1_lrs1; // @[util.scala:466:20] reg [5:0] uops_1_lrs2; // @[util.scala:466:20] reg [5:0] uops_1_lrs3; // @[util.scala:466:20] reg uops_1_ldst_val; // @[util.scala:466:20] reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20] reg uops_1_frs3_en; // @[util.scala:466:20] reg uops_1_fp_val; // @[util.scala:466:20] reg uops_1_fp_single; // @[util.scala:466:20] reg uops_1_xcpt_pf_if; // @[util.scala:466:20] reg uops_1_xcpt_ae_if; // @[util.scala:466:20] reg uops_1_xcpt_ma_if; // @[util.scala:466:20] reg uops_1_bp_debug_if; // @[util.scala:466:20] reg uops_1_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_2_uopc; // @[util.scala:466:20] reg [31:0] uops_2_inst; // @[util.scala:466:20] reg [31:0] uops_2_debug_inst; // @[util.scala:466:20] reg uops_2_is_rvc; // @[util.scala:466:20] reg [39:0] uops_2_debug_pc; // @[util.scala:466:20] reg [2:0] uops_2_iq_type; // @[util.scala:466:20] reg [9:0] uops_2_fu_code; // @[util.scala:466:20] reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20] reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_2_ctrl_is_load; // @[util.scala:466:20] reg uops_2_ctrl_is_sta; // @[util.scala:466:20] reg uops_2_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_2_iw_state; // @[util.scala:466:20] reg uops_2_iw_p1_poisoned; // @[util.scala:466:20] reg uops_2_iw_p2_poisoned; // @[util.scala:466:20] reg uops_2_is_br; // @[util.scala:466:20] reg uops_2_is_jalr; // @[util.scala:466:20] reg uops_2_is_jal; // @[util.scala:466:20] reg uops_2_is_sfb; // @[util.scala:466:20] reg [15:0] uops_2_br_mask; // @[util.scala:466:20] reg [3:0] uops_2_br_tag; // @[util.scala:466:20] reg [4:0] uops_2_ftq_idx; // @[util.scala:466:20] reg uops_2_edge_inst; // @[util.scala:466:20] reg [5:0] uops_2_pc_lob; // @[util.scala:466:20] reg uops_2_taken; // @[util.scala:466:20] reg [19:0] uops_2_imm_packed; // @[util.scala:466:20] reg [11:0] uops_2_csr_addr; // @[util.scala:466:20] reg [6:0] uops_2_rob_idx; // @[util.scala:466:20] reg [4:0] uops_2_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_2_stq_idx; // @[util.scala:466:20] reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_2_pdst; // @[util.scala:466:20] reg [6:0] uops_2_prs1; // @[util.scala:466:20] reg [6:0] uops_2_prs2; // @[util.scala:466:20] reg [6:0] uops_2_prs3; // @[util.scala:466:20] reg [4:0] uops_2_ppred; // @[util.scala:466:20] reg uops_2_prs1_busy; // @[util.scala:466:20] reg uops_2_prs2_busy; // @[util.scala:466:20] reg uops_2_prs3_busy; // @[util.scala:466:20] reg uops_2_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_2_stale_pdst; // @[util.scala:466:20] reg uops_2_exception; // @[util.scala:466:20] reg [63:0] uops_2_exc_cause; // @[util.scala:466:20] reg uops_2_bypassable; // @[util.scala:466:20] reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_2_mem_size; // @[util.scala:466:20] reg uops_2_mem_signed; // @[util.scala:466:20] reg uops_2_is_fence; // @[util.scala:466:20] reg uops_2_is_fencei; // @[util.scala:466:20] reg uops_2_is_amo; // @[util.scala:466:20] reg uops_2_uses_ldq; // @[util.scala:466:20] reg uops_2_uses_stq; // @[util.scala:466:20] reg uops_2_is_sys_pc2epc; // @[util.scala:466:20] reg uops_2_is_unique; // @[util.scala:466:20] reg uops_2_flush_on_commit; // @[util.scala:466:20] reg uops_2_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_2_ldst; // @[util.scala:466:20] reg [5:0] uops_2_lrs1; // @[util.scala:466:20] reg [5:0] uops_2_lrs2; // @[util.scala:466:20] reg [5:0] uops_2_lrs3; // @[util.scala:466:20] reg uops_2_ldst_val; // @[util.scala:466:20] reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20] reg uops_2_frs3_en; // @[util.scala:466:20] reg uops_2_fp_val; // @[util.scala:466:20] reg uops_2_fp_single; // @[util.scala:466:20] reg uops_2_xcpt_pf_if; // @[util.scala:466:20] reg uops_2_xcpt_ae_if; // @[util.scala:466:20] reg uops_2_xcpt_ma_if; // @[util.scala:466:20] reg uops_2_bp_debug_if; // @[util.scala:466:20] reg uops_2_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_3_uopc; // @[util.scala:466:20] reg [31:0] uops_3_inst; // @[util.scala:466:20] reg [31:0] uops_3_debug_inst; // @[util.scala:466:20] reg uops_3_is_rvc; // @[util.scala:466:20] reg [39:0] uops_3_debug_pc; // @[util.scala:466:20] reg [2:0] uops_3_iq_type; // @[util.scala:466:20] reg [9:0] uops_3_fu_code; // @[util.scala:466:20] reg [3:0] uops_3_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_3_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_3_ctrl_op_fcn; // @[util.scala:466:20] reg uops_3_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_3_ctrl_is_load; // @[util.scala:466:20] reg uops_3_ctrl_is_sta; // @[util.scala:466:20] reg uops_3_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_3_iw_state; // @[util.scala:466:20] reg uops_3_iw_p1_poisoned; // @[util.scala:466:20] reg uops_3_iw_p2_poisoned; // @[util.scala:466:20] reg uops_3_is_br; // @[util.scala:466:20] reg uops_3_is_jalr; // @[util.scala:466:20] reg uops_3_is_jal; // @[util.scala:466:20] reg uops_3_is_sfb; // @[util.scala:466:20] reg [15:0] uops_3_br_mask; // @[util.scala:466:20] reg [3:0] uops_3_br_tag; // @[util.scala:466:20] reg [4:0] uops_3_ftq_idx; // @[util.scala:466:20] reg uops_3_edge_inst; // @[util.scala:466:20] reg [5:0] uops_3_pc_lob; // @[util.scala:466:20] reg uops_3_taken; // @[util.scala:466:20] reg [19:0] uops_3_imm_packed; // @[util.scala:466:20] reg [11:0] uops_3_csr_addr; // @[util.scala:466:20] reg [6:0] uops_3_rob_idx; // @[util.scala:466:20] reg [4:0] uops_3_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_3_stq_idx; // @[util.scala:466:20] reg [1:0] uops_3_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_3_pdst; // @[util.scala:466:20] reg [6:0] uops_3_prs1; // @[util.scala:466:20] reg [6:0] uops_3_prs2; // @[util.scala:466:20] reg [6:0] uops_3_prs3; // @[util.scala:466:20] reg [4:0] uops_3_ppred; // @[util.scala:466:20] reg uops_3_prs1_busy; // @[util.scala:466:20] reg uops_3_prs2_busy; // @[util.scala:466:20] reg uops_3_prs3_busy; // @[util.scala:466:20] reg uops_3_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_3_stale_pdst; // @[util.scala:466:20] reg uops_3_exception; // @[util.scala:466:20] reg [63:0] uops_3_exc_cause; // @[util.scala:466:20] reg uops_3_bypassable; // @[util.scala:466:20] reg [4:0] uops_3_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_3_mem_size; // @[util.scala:466:20] reg uops_3_mem_signed; // @[util.scala:466:20] reg uops_3_is_fence; // @[util.scala:466:20] reg uops_3_is_fencei; // @[util.scala:466:20] reg uops_3_is_amo; // @[util.scala:466:20] reg uops_3_uses_ldq; // @[util.scala:466:20] reg uops_3_uses_stq; // @[util.scala:466:20] reg uops_3_is_sys_pc2epc; // @[util.scala:466:20] reg uops_3_is_unique; // @[util.scala:466:20] reg uops_3_flush_on_commit; // @[util.scala:466:20] reg uops_3_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_3_ldst; // @[util.scala:466:20] reg [5:0] uops_3_lrs1; // @[util.scala:466:20] reg [5:0] uops_3_lrs2; // @[util.scala:466:20] reg [5:0] uops_3_lrs3; // @[util.scala:466:20] reg uops_3_ldst_val; // @[util.scala:466:20] reg [1:0] uops_3_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:466:20] reg uops_3_frs3_en; // @[util.scala:466:20] reg uops_3_fp_val; // @[util.scala:466:20] reg uops_3_fp_single; // @[util.scala:466:20] reg uops_3_xcpt_pf_if; // @[util.scala:466:20] reg uops_3_xcpt_ae_if; // @[util.scala:466:20] reg uops_3_xcpt_ma_if; // @[util.scala:466:20] reg uops_3_bp_debug_if; // @[util.scala:466:20] reg uops_3_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_3_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_3_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_4_uopc; // @[util.scala:466:20] reg [31:0] uops_4_inst; // @[util.scala:466:20] reg [31:0] uops_4_debug_inst; // @[util.scala:466:20] reg uops_4_is_rvc; // @[util.scala:466:20] reg [39:0] uops_4_debug_pc; // @[util.scala:466:20] reg [2:0] uops_4_iq_type; // @[util.scala:466:20] reg [9:0] uops_4_fu_code; // @[util.scala:466:20] reg [3:0] uops_4_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_4_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_4_ctrl_op_fcn; // @[util.scala:466:20] reg uops_4_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_4_ctrl_is_load; // @[util.scala:466:20] reg uops_4_ctrl_is_sta; // @[util.scala:466:20] reg uops_4_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_4_iw_state; // @[util.scala:466:20] reg uops_4_iw_p1_poisoned; // @[util.scala:466:20] reg uops_4_iw_p2_poisoned; // @[util.scala:466:20] reg uops_4_is_br; // @[util.scala:466:20] reg uops_4_is_jalr; // @[util.scala:466:20] reg uops_4_is_jal; // @[util.scala:466:20] reg uops_4_is_sfb; // @[util.scala:466:20] reg [15:0] uops_4_br_mask; // @[util.scala:466:20] reg [3:0] uops_4_br_tag; // @[util.scala:466:20] reg [4:0] uops_4_ftq_idx; // @[util.scala:466:20] reg uops_4_edge_inst; // @[util.scala:466:20] reg [5:0] uops_4_pc_lob; // @[util.scala:466:20] reg uops_4_taken; // @[util.scala:466:20] reg [19:0] uops_4_imm_packed; // @[util.scala:466:20] reg [11:0] uops_4_csr_addr; // @[util.scala:466:20] reg [6:0] uops_4_rob_idx; // @[util.scala:466:20] reg [4:0] uops_4_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_4_stq_idx; // @[util.scala:466:20] reg [1:0] uops_4_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_4_pdst; // @[util.scala:466:20] reg [6:0] uops_4_prs1; // @[util.scala:466:20] reg [6:0] uops_4_prs2; // @[util.scala:466:20] reg [6:0] uops_4_prs3; // @[util.scala:466:20] reg [4:0] uops_4_ppred; // @[util.scala:466:20] reg uops_4_prs1_busy; // @[util.scala:466:20] reg uops_4_prs2_busy; // @[util.scala:466:20] reg uops_4_prs3_busy; // @[util.scala:466:20] reg uops_4_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_4_stale_pdst; // @[util.scala:466:20] reg uops_4_exception; // @[util.scala:466:20] reg [63:0] uops_4_exc_cause; // @[util.scala:466:20] reg uops_4_bypassable; // @[util.scala:466:20] reg [4:0] uops_4_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_4_mem_size; // @[util.scala:466:20] reg uops_4_mem_signed; // @[util.scala:466:20] reg uops_4_is_fence; // @[util.scala:466:20] reg uops_4_is_fencei; // @[util.scala:466:20] reg uops_4_is_amo; // @[util.scala:466:20] reg uops_4_uses_ldq; // @[util.scala:466:20] reg uops_4_uses_stq; // @[util.scala:466:20] reg uops_4_is_sys_pc2epc; // @[util.scala:466:20] reg uops_4_is_unique; // @[util.scala:466:20] reg uops_4_flush_on_commit; // @[util.scala:466:20] reg uops_4_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_4_ldst; // @[util.scala:466:20] reg [5:0] uops_4_lrs1; // @[util.scala:466:20] reg [5:0] uops_4_lrs2; // @[util.scala:466:20] reg [5:0] uops_4_lrs3; // @[util.scala:466:20] reg uops_4_ldst_val; // @[util.scala:466:20] reg [1:0] uops_4_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:466:20] reg uops_4_frs3_en; // @[util.scala:466:20] reg uops_4_fp_val; // @[util.scala:466:20] reg uops_4_fp_single; // @[util.scala:466:20] reg uops_4_xcpt_pf_if; // @[util.scala:466:20] reg uops_4_xcpt_ae_if; // @[util.scala:466:20] reg uops_4_xcpt_ma_if; // @[util.scala:466:20] reg uops_4_bp_debug_if; // @[util.scala:466:20] reg uops_4_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_4_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_4_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_5_uopc; // @[util.scala:466:20] reg [31:0] uops_5_inst; // @[util.scala:466:20] reg [31:0] uops_5_debug_inst; // @[util.scala:466:20] reg uops_5_is_rvc; // @[util.scala:466:20] reg [39:0] uops_5_debug_pc; // @[util.scala:466:20] reg [2:0] uops_5_iq_type; // @[util.scala:466:20] reg [9:0] uops_5_fu_code; // @[util.scala:466:20] reg [3:0] uops_5_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_5_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_5_ctrl_op_fcn; // @[util.scala:466:20] reg uops_5_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_5_ctrl_is_load; // @[util.scala:466:20] reg uops_5_ctrl_is_sta; // @[util.scala:466:20] reg uops_5_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_5_iw_state; // @[util.scala:466:20] reg uops_5_iw_p1_poisoned; // @[util.scala:466:20] reg uops_5_iw_p2_poisoned; // @[util.scala:466:20] reg uops_5_is_br; // @[util.scala:466:20] reg uops_5_is_jalr; // @[util.scala:466:20] reg uops_5_is_jal; // @[util.scala:466:20] reg uops_5_is_sfb; // @[util.scala:466:20] reg [15:0] uops_5_br_mask; // @[util.scala:466:20] reg [3:0] uops_5_br_tag; // @[util.scala:466:20] reg [4:0] uops_5_ftq_idx; // @[util.scala:466:20] reg uops_5_edge_inst; // @[util.scala:466:20] reg [5:0] uops_5_pc_lob; // @[util.scala:466:20] reg uops_5_taken; // @[util.scala:466:20] reg [19:0] uops_5_imm_packed; // @[util.scala:466:20] reg [11:0] uops_5_csr_addr; // @[util.scala:466:20] reg [6:0] uops_5_rob_idx; // @[util.scala:466:20] reg [4:0] uops_5_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_5_stq_idx; // @[util.scala:466:20] reg [1:0] uops_5_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_5_pdst; // @[util.scala:466:20] reg [6:0] uops_5_prs1; // @[util.scala:466:20] reg [6:0] uops_5_prs2; // @[util.scala:466:20] reg [6:0] uops_5_prs3; // @[util.scala:466:20] reg [4:0] uops_5_ppred; // @[util.scala:466:20] reg uops_5_prs1_busy; // @[util.scala:466:20] reg uops_5_prs2_busy; // @[util.scala:466:20] reg uops_5_prs3_busy; // @[util.scala:466:20] reg uops_5_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_5_stale_pdst; // @[util.scala:466:20] reg uops_5_exception; // @[util.scala:466:20] reg [63:0] uops_5_exc_cause; // @[util.scala:466:20] reg uops_5_bypassable; // @[util.scala:466:20] reg [4:0] uops_5_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_5_mem_size; // @[util.scala:466:20] reg uops_5_mem_signed; // @[util.scala:466:20] reg uops_5_is_fence; // @[util.scala:466:20] reg uops_5_is_fencei; // @[util.scala:466:20] reg uops_5_is_amo; // @[util.scala:466:20] reg uops_5_uses_ldq; // @[util.scala:466:20] reg uops_5_uses_stq; // @[util.scala:466:20] reg uops_5_is_sys_pc2epc; // @[util.scala:466:20] reg uops_5_is_unique; // @[util.scala:466:20] reg uops_5_flush_on_commit; // @[util.scala:466:20] reg uops_5_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_5_ldst; // @[util.scala:466:20] reg [5:0] uops_5_lrs1; // @[util.scala:466:20] reg [5:0] uops_5_lrs2; // @[util.scala:466:20] reg [5:0] uops_5_lrs3; // @[util.scala:466:20] reg uops_5_ldst_val; // @[util.scala:466:20] reg [1:0] uops_5_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:466:20] reg uops_5_frs3_en; // @[util.scala:466:20] reg uops_5_fp_val; // @[util.scala:466:20] reg uops_5_fp_single; // @[util.scala:466:20] reg uops_5_xcpt_pf_if; // @[util.scala:466:20] reg uops_5_xcpt_ae_if; // @[util.scala:466:20] reg uops_5_xcpt_ma_if; // @[util.scala:466:20] reg uops_5_bp_debug_if; // @[util.scala:466:20] reg uops_5_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_5_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_5_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_6_uopc; // @[util.scala:466:20] reg [31:0] uops_6_inst; // @[util.scala:466:20] reg [31:0] uops_6_debug_inst; // @[util.scala:466:20] reg uops_6_is_rvc; // @[util.scala:466:20] reg [39:0] uops_6_debug_pc; // @[util.scala:466:20] reg [2:0] uops_6_iq_type; // @[util.scala:466:20] reg [9:0] uops_6_fu_code; // @[util.scala:466:20] reg [3:0] uops_6_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_6_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_6_ctrl_op_fcn; // @[util.scala:466:20] reg uops_6_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_6_ctrl_is_load; // @[util.scala:466:20] reg uops_6_ctrl_is_sta; // @[util.scala:466:20] reg uops_6_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_6_iw_state; // @[util.scala:466:20] reg uops_6_iw_p1_poisoned; // @[util.scala:466:20] reg uops_6_iw_p2_poisoned; // @[util.scala:466:20] reg uops_6_is_br; // @[util.scala:466:20] reg uops_6_is_jalr; // @[util.scala:466:20] reg uops_6_is_jal; // @[util.scala:466:20] reg uops_6_is_sfb; // @[util.scala:466:20] reg [15:0] uops_6_br_mask; // @[util.scala:466:20] reg [3:0] uops_6_br_tag; // @[util.scala:466:20] reg [4:0] uops_6_ftq_idx; // @[util.scala:466:20] reg uops_6_edge_inst; // @[util.scala:466:20] reg [5:0] uops_6_pc_lob; // @[util.scala:466:20] reg uops_6_taken; // @[util.scala:466:20] reg [19:0] uops_6_imm_packed; // @[util.scala:466:20] reg [11:0] uops_6_csr_addr; // @[util.scala:466:20] reg [6:0] uops_6_rob_idx; // @[util.scala:466:20] reg [4:0] uops_6_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_6_stq_idx; // @[util.scala:466:20] reg [1:0] uops_6_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_6_pdst; // @[util.scala:466:20] reg [6:0] uops_6_prs1; // @[util.scala:466:20] reg [6:0] uops_6_prs2; // @[util.scala:466:20] reg [6:0] uops_6_prs3; // @[util.scala:466:20] reg [4:0] uops_6_ppred; // @[util.scala:466:20] reg uops_6_prs1_busy; // @[util.scala:466:20] reg uops_6_prs2_busy; // @[util.scala:466:20] reg uops_6_prs3_busy; // @[util.scala:466:20] reg uops_6_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_6_stale_pdst; // @[util.scala:466:20] reg uops_6_exception; // @[util.scala:466:20] reg [63:0] uops_6_exc_cause; // @[util.scala:466:20] reg uops_6_bypassable; // @[util.scala:466:20] reg [4:0] uops_6_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_6_mem_size; // @[util.scala:466:20] reg uops_6_mem_signed; // @[util.scala:466:20] reg uops_6_is_fence; // @[util.scala:466:20] reg uops_6_is_fencei; // @[util.scala:466:20] reg uops_6_is_amo; // @[util.scala:466:20] reg uops_6_uses_ldq; // @[util.scala:466:20] reg uops_6_uses_stq; // @[util.scala:466:20] reg uops_6_is_sys_pc2epc; // @[util.scala:466:20] reg uops_6_is_unique; // @[util.scala:466:20] reg uops_6_flush_on_commit; // @[util.scala:466:20] reg uops_6_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_6_ldst; // @[util.scala:466:20] reg [5:0] uops_6_lrs1; // @[util.scala:466:20] reg [5:0] uops_6_lrs2; // @[util.scala:466:20] reg [5:0] uops_6_lrs3; // @[util.scala:466:20] reg uops_6_ldst_val; // @[util.scala:466:20] reg [1:0] uops_6_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:466:20] reg uops_6_frs3_en; // @[util.scala:466:20] reg uops_6_fp_val; // @[util.scala:466:20] reg uops_6_fp_single; // @[util.scala:466:20] reg uops_6_xcpt_pf_if; // @[util.scala:466:20] reg uops_6_xcpt_ae_if; // @[util.scala:466:20] reg uops_6_xcpt_ma_if; // @[util.scala:466:20] reg uops_6_bp_debug_if; // @[util.scala:466:20] reg uops_6_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_6_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_6_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_7_uopc; // @[util.scala:466:20] reg [31:0] uops_7_inst; // @[util.scala:466:20] reg [31:0] uops_7_debug_inst; // @[util.scala:466:20] reg uops_7_is_rvc; // @[util.scala:466:20] reg [39:0] uops_7_debug_pc; // @[util.scala:466:20] reg [2:0] uops_7_iq_type; // @[util.scala:466:20] reg [9:0] uops_7_fu_code; // @[util.scala:466:20] reg [3:0] uops_7_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_7_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_7_ctrl_op_fcn; // @[util.scala:466:20] reg uops_7_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_7_ctrl_is_load; // @[util.scala:466:20] reg uops_7_ctrl_is_sta; // @[util.scala:466:20] reg uops_7_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_7_iw_state; // @[util.scala:466:20] reg uops_7_iw_p1_poisoned; // @[util.scala:466:20] reg uops_7_iw_p2_poisoned; // @[util.scala:466:20] reg uops_7_is_br; // @[util.scala:466:20] reg uops_7_is_jalr; // @[util.scala:466:20] reg uops_7_is_jal; // @[util.scala:466:20] reg uops_7_is_sfb; // @[util.scala:466:20] reg [15:0] uops_7_br_mask; // @[util.scala:466:20] reg [3:0] uops_7_br_tag; // @[util.scala:466:20] reg [4:0] uops_7_ftq_idx; // @[util.scala:466:20] reg uops_7_edge_inst; // @[util.scala:466:20] reg [5:0] uops_7_pc_lob; // @[util.scala:466:20] reg uops_7_taken; // @[util.scala:466:20] reg [19:0] uops_7_imm_packed; // @[util.scala:466:20] reg [11:0] uops_7_csr_addr; // @[util.scala:466:20] reg [6:0] uops_7_rob_idx; // @[util.scala:466:20] reg [4:0] uops_7_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_7_stq_idx; // @[util.scala:466:20] reg [1:0] uops_7_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_7_pdst; // @[util.scala:466:20] reg [6:0] uops_7_prs1; // @[util.scala:466:20] reg [6:0] uops_7_prs2; // @[util.scala:466:20] reg [6:0] uops_7_prs3; // @[util.scala:466:20] reg [4:0] uops_7_ppred; // @[util.scala:466:20] reg uops_7_prs1_busy; // @[util.scala:466:20] reg uops_7_prs2_busy; // @[util.scala:466:20] reg uops_7_prs3_busy; // @[util.scala:466:20] reg uops_7_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_7_stale_pdst; // @[util.scala:466:20] reg uops_7_exception; // @[util.scala:466:20] reg [63:0] uops_7_exc_cause; // @[util.scala:466:20] reg uops_7_bypassable; // @[util.scala:466:20] reg [4:0] uops_7_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_7_mem_size; // @[util.scala:466:20] reg uops_7_mem_signed; // @[util.scala:466:20] reg uops_7_is_fence; // @[util.scala:466:20] reg uops_7_is_fencei; // @[util.scala:466:20] reg uops_7_is_amo; // @[util.scala:466:20] reg uops_7_uses_ldq; // @[util.scala:466:20] reg uops_7_uses_stq; // @[util.scala:466:20] reg uops_7_is_sys_pc2epc; // @[util.scala:466:20] reg uops_7_is_unique; // @[util.scala:466:20] reg uops_7_flush_on_commit; // @[util.scala:466:20] reg uops_7_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_7_ldst; // @[util.scala:466:20] reg [5:0] uops_7_lrs1; // @[util.scala:466:20] reg [5:0] uops_7_lrs2; // @[util.scala:466:20] reg [5:0] uops_7_lrs3; // @[util.scala:466:20] reg uops_7_ldst_val; // @[util.scala:466:20] reg [1:0] uops_7_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:466:20] reg uops_7_frs3_en; // @[util.scala:466:20] reg uops_7_fp_val; // @[util.scala:466:20] reg uops_7_fp_single; // @[util.scala:466:20] reg uops_7_xcpt_pf_if; // @[util.scala:466:20] reg uops_7_xcpt_ae_if; // @[util.scala:466:20] reg uops_7_xcpt_ma_if; // @[util.scala:466:20] reg uops_7_bp_debug_if; // @[util.scala:466:20] reg uops_7_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_7_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_7_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_8_uopc; // @[util.scala:466:20] reg [31:0] uops_8_inst; // @[util.scala:466:20] reg [31:0] uops_8_debug_inst; // @[util.scala:466:20] reg uops_8_is_rvc; // @[util.scala:466:20] reg [39:0] uops_8_debug_pc; // @[util.scala:466:20] reg [2:0] uops_8_iq_type; // @[util.scala:466:20] reg [9:0] uops_8_fu_code; // @[util.scala:466:20] reg [3:0] uops_8_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_8_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_8_ctrl_op_fcn; // @[util.scala:466:20] reg uops_8_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_8_ctrl_is_load; // @[util.scala:466:20] reg uops_8_ctrl_is_sta; // @[util.scala:466:20] reg uops_8_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_8_iw_state; // @[util.scala:466:20] reg uops_8_iw_p1_poisoned; // @[util.scala:466:20] reg uops_8_iw_p2_poisoned; // @[util.scala:466:20] reg uops_8_is_br; // @[util.scala:466:20] reg uops_8_is_jalr; // @[util.scala:466:20] reg uops_8_is_jal; // @[util.scala:466:20] reg uops_8_is_sfb; // @[util.scala:466:20] reg [15:0] uops_8_br_mask; // @[util.scala:466:20] reg [3:0] uops_8_br_tag; // @[util.scala:466:20] reg [4:0] uops_8_ftq_idx; // @[util.scala:466:20] reg uops_8_edge_inst; // @[util.scala:466:20] reg [5:0] uops_8_pc_lob; // @[util.scala:466:20] reg uops_8_taken; // @[util.scala:466:20] reg [19:0] uops_8_imm_packed; // @[util.scala:466:20] reg [11:0] uops_8_csr_addr; // @[util.scala:466:20] reg [6:0] uops_8_rob_idx; // @[util.scala:466:20] reg [4:0] uops_8_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_8_stq_idx; // @[util.scala:466:20] reg [1:0] uops_8_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_8_pdst; // @[util.scala:466:20] reg [6:0] uops_8_prs1; // @[util.scala:466:20] reg [6:0] uops_8_prs2; // @[util.scala:466:20] reg [6:0] uops_8_prs3; // @[util.scala:466:20] reg [4:0] uops_8_ppred; // @[util.scala:466:20] reg uops_8_prs1_busy; // @[util.scala:466:20] reg uops_8_prs2_busy; // @[util.scala:466:20] reg uops_8_prs3_busy; // @[util.scala:466:20] reg uops_8_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_8_stale_pdst; // @[util.scala:466:20] reg uops_8_exception; // @[util.scala:466:20] reg [63:0] uops_8_exc_cause; // @[util.scala:466:20] reg uops_8_bypassable; // @[util.scala:466:20] reg [4:0] uops_8_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_8_mem_size; // @[util.scala:466:20] reg uops_8_mem_signed; // @[util.scala:466:20] reg uops_8_is_fence; // @[util.scala:466:20] reg uops_8_is_fencei; // @[util.scala:466:20] reg uops_8_is_amo; // @[util.scala:466:20] reg uops_8_uses_ldq; // @[util.scala:466:20] reg uops_8_uses_stq; // @[util.scala:466:20] reg uops_8_is_sys_pc2epc; // @[util.scala:466:20] reg uops_8_is_unique; // @[util.scala:466:20] reg uops_8_flush_on_commit; // @[util.scala:466:20] reg uops_8_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_8_ldst; // @[util.scala:466:20] reg [5:0] uops_8_lrs1; // @[util.scala:466:20] reg [5:0] uops_8_lrs2; // @[util.scala:466:20] reg [5:0] uops_8_lrs3; // @[util.scala:466:20] reg uops_8_ldst_val; // @[util.scala:466:20] reg [1:0] uops_8_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:466:20] reg uops_8_frs3_en; // @[util.scala:466:20] reg uops_8_fp_val; // @[util.scala:466:20] reg uops_8_fp_single; // @[util.scala:466:20] reg uops_8_xcpt_pf_if; // @[util.scala:466:20] reg uops_8_xcpt_ae_if; // @[util.scala:466:20] reg uops_8_xcpt_ma_if; // @[util.scala:466:20] reg uops_8_bp_debug_if; // @[util.scala:466:20] reg uops_8_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_8_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_8_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_9_uopc; // @[util.scala:466:20] reg [31:0] uops_9_inst; // @[util.scala:466:20] reg [31:0] uops_9_debug_inst; // @[util.scala:466:20] reg uops_9_is_rvc; // @[util.scala:466:20] reg [39:0] uops_9_debug_pc; // @[util.scala:466:20] reg [2:0] uops_9_iq_type; // @[util.scala:466:20] reg [9:0] uops_9_fu_code; // @[util.scala:466:20] reg [3:0] uops_9_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_9_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_9_ctrl_op_fcn; // @[util.scala:466:20] reg uops_9_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_9_ctrl_is_load; // @[util.scala:466:20] reg uops_9_ctrl_is_sta; // @[util.scala:466:20] reg uops_9_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_9_iw_state; // @[util.scala:466:20] reg uops_9_iw_p1_poisoned; // @[util.scala:466:20] reg uops_9_iw_p2_poisoned; // @[util.scala:466:20] reg uops_9_is_br; // @[util.scala:466:20] reg uops_9_is_jalr; // @[util.scala:466:20] reg uops_9_is_jal; // @[util.scala:466:20] reg uops_9_is_sfb; // @[util.scala:466:20] reg [15:0] uops_9_br_mask; // @[util.scala:466:20] reg [3:0] uops_9_br_tag; // @[util.scala:466:20] reg [4:0] uops_9_ftq_idx; // @[util.scala:466:20] reg uops_9_edge_inst; // @[util.scala:466:20] reg [5:0] uops_9_pc_lob; // @[util.scala:466:20] reg uops_9_taken; // @[util.scala:466:20] reg [19:0] uops_9_imm_packed; // @[util.scala:466:20] reg [11:0] uops_9_csr_addr; // @[util.scala:466:20] reg [6:0] uops_9_rob_idx; // @[util.scala:466:20] reg [4:0] uops_9_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_9_stq_idx; // @[util.scala:466:20] reg [1:0] uops_9_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_9_pdst; // @[util.scala:466:20] reg [6:0] uops_9_prs1; // @[util.scala:466:20] reg [6:0] uops_9_prs2; // @[util.scala:466:20] reg [6:0] uops_9_prs3; // @[util.scala:466:20] reg [4:0] uops_9_ppred; // @[util.scala:466:20] reg uops_9_prs1_busy; // @[util.scala:466:20] reg uops_9_prs2_busy; // @[util.scala:466:20] reg uops_9_prs3_busy; // @[util.scala:466:20] reg uops_9_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_9_stale_pdst; // @[util.scala:466:20] reg uops_9_exception; // @[util.scala:466:20] reg [63:0] uops_9_exc_cause; // @[util.scala:466:20] reg uops_9_bypassable; // @[util.scala:466:20] reg [4:0] uops_9_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_9_mem_size; // @[util.scala:466:20] reg uops_9_mem_signed; // @[util.scala:466:20] reg uops_9_is_fence; // @[util.scala:466:20] reg uops_9_is_fencei; // @[util.scala:466:20] reg uops_9_is_amo; // @[util.scala:466:20] reg uops_9_uses_ldq; // @[util.scala:466:20] reg uops_9_uses_stq; // @[util.scala:466:20] reg uops_9_is_sys_pc2epc; // @[util.scala:466:20] reg uops_9_is_unique; // @[util.scala:466:20] reg uops_9_flush_on_commit; // @[util.scala:466:20] reg uops_9_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_9_ldst; // @[util.scala:466:20] reg [5:0] uops_9_lrs1; // @[util.scala:466:20] reg [5:0] uops_9_lrs2; // @[util.scala:466:20] reg [5:0] uops_9_lrs3; // @[util.scala:466:20] reg uops_9_ldst_val; // @[util.scala:466:20] reg [1:0] uops_9_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:466:20] reg uops_9_frs3_en; // @[util.scala:466:20] reg uops_9_fp_val; // @[util.scala:466:20] reg uops_9_fp_single; // @[util.scala:466:20] reg uops_9_xcpt_pf_if; // @[util.scala:466:20] reg uops_9_xcpt_ae_if; // @[util.scala:466:20] reg uops_9_xcpt_ma_if; // @[util.scala:466:20] reg uops_9_bp_debug_if; // @[util.scala:466:20] reg uops_9_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_9_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_9_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_10_uopc; // @[util.scala:466:20] reg [31:0] uops_10_inst; // @[util.scala:466:20] reg [31:0] uops_10_debug_inst; // @[util.scala:466:20] reg uops_10_is_rvc; // @[util.scala:466:20] reg [39:0] uops_10_debug_pc; // @[util.scala:466:20] reg [2:0] uops_10_iq_type; // @[util.scala:466:20] reg [9:0] uops_10_fu_code; // @[util.scala:466:20] reg [3:0] uops_10_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_10_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_10_ctrl_op_fcn; // @[util.scala:466:20] reg uops_10_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_10_ctrl_is_load; // @[util.scala:466:20] reg uops_10_ctrl_is_sta; // @[util.scala:466:20] reg uops_10_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_10_iw_state; // @[util.scala:466:20] reg uops_10_iw_p1_poisoned; // @[util.scala:466:20] reg uops_10_iw_p2_poisoned; // @[util.scala:466:20] reg uops_10_is_br; // @[util.scala:466:20] reg uops_10_is_jalr; // @[util.scala:466:20] reg uops_10_is_jal; // @[util.scala:466:20] reg uops_10_is_sfb; // @[util.scala:466:20] reg [15:0] uops_10_br_mask; // @[util.scala:466:20] reg [3:0] uops_10_br_tag; // @[util.scala:466:20] reg [4:0] uops_10_ftq_idx; // @[util.scala:466:20] reg uops_10_edge_inst; // @[util.scala:466:20] reg [5:0] uops_10_pc_lob; // @[util.scala:466:20] reg uops_10_taken; // @[util.scala:466:20] reg [19:0] uops_10_imm_packed; // @[util.scala:466:20] reg [11:0] uops_10_csr_addr; // @[util.scala:466:20] reg [6:0] uops_10_rob_idx; // @[util.scala:466:20] reg [4:0] uops_10_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_10_stq_idx; // @[util.scala:466:20] reg [1:0] uops_10_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_10_pdst; // @[util.scala:466:20] reg [6:0] uops_10_prs1; // @[util.scala:466:20] reg [6:0] uops_10_prs2; // @[util.scala:466:20] reg [6:0] uops_10_prs3; // @[util.scala:466:20] reg [4:0] uops_10_ppred; // @[util.scala:466:20] reg uops_10_prs1_busy; // @[util.scala:466:20] reg uops_10_prs2_busy; // @[util.scala:466:20] reg uops_10_prs3_busy; // @[util.scala:466:20] reg uops_10_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_10_stale_pdst; // @[util.scala:466:20] reg uops_10_exception; // @[util.scala:466:20] reg [63:0] uops_10_exc_cause; // @[util.scala:466:20] reg uops_10_bypassable; // @[util.scala:466:20] reg [4:0] uops_10_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_10_mem_size; // @[util.scala:466:20] reg uops_10_mem_signed; // @[util.scala:466:20] reg uops_10_is_fence; // @[util.scala:466:20] reg uops_10_is_fencei; // @[util.scala:466:20] reg uops_10_is_amo; // @[util.scala:466:20] reg uops_10_uses_ldq; // @[util.scala:466:20] reg uops_10_uses_stq; // @[util.scala:466:20] reg uops_10_is_sys_pc2epc; // @[util.scala:466:20] reg uops_10_is_unique; // @[util.scala:466:20] reg uops_10_flush_on_commit; // @[util.scala:466:20] reg uops_10_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_10_ldst; // @[util.scala:466:20] reg [5:0] uops_10_lrs1; // @[util.scala:466:20] reg [5:0] uops_10_lrs2; // @[util.scala:466:20] reg [5:0] uops_10_lrs3; // @[util.scala:466:20] reg uops_10_ldst_val; // @[util.scala:466:20] reg [1:0] uops_10_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:466:20] reg uops_10_frs3_en; // @[util.scala:466:20] reg uops_10_fp_val; // @[util.scala:466:20] reg uops_10_fp_single; // @[util.scala:466:20] reg uops_10_xcpt_pf_if; // @[util.scala:466:20] reg uops_10_xcpt_ae_if; // @[util.scala:466:20] reg uops_10_xcpt_ma_if; // @[util.scala:466:20] reg uops_10_bp_debug_if; // @[util.scala:466:20] reg uops_10_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_10_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_10_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_11_uopc; // @[util.scala:466:20] reg [31:0] uops_11_inst; // @[util.scala:466:20] reg [31:0] uops_11_debug_inst; // @[util.scala:466:20] reg uops_11_is_rvc; // @[util.scala:466:20] reg [39:0] uops_11_debug_pc; // @[util.scala:466:20] reg [2:0] uops_11_iq_type; // @[util.scala:466:20] reg [9:0] uops_11_fu_code; // @[util.scala:466:20] reg [3:0] uops_11_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_11_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_11_ctrl_op_fcn; // @[util.scala:466:20] reg uops_11_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_11_ctrl_is_load; // @[util.scala:466:20] reg uops_11_ctrl_is_sta; // @[util.scala:466:20] reg uops_11_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_11_iw_state; // @[util.scala:466:20] reg uops_11_iw_p1_poisoned; // @[util.scala:466:20] reg uops_11_iw_p2_poisoned; // @[util.scala:466:20] reg uops_11_is_br; // @[util.scala:466:20] reg uops_11_is_jalr; // @[util.scala:466:20] reg uops_11_is_jal; // @[util.scala:466:20] reg uops_11_is_sfb; // @[util.scala:466:20] reg [15:0] uops_11_br_mask; // @[util.scala:466:20] reg [3:0] uops_11_br_tag; // @[util.scala:466:20] reg [4:0] uops_11_ftq_idx; // @[util.scala:466:20] reg uops_11_edge_inst; // @[util.scala:466:20] reg [5:0] uops_11_pc_lob; // @[util.scala:466:20] reg uops_11_taken; // @[util.scala:466:20] reg [19:0] uops_11_imm_packed; // @[util.scala:466:20] reg [11:0] uops_11_csr_addr; // @[util.scala:466:20] reg [6:0] uops_11_rob_idx; // @[util.scala:466:20] reg [4:0] uops_11_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_11_stq_idx; // @[util.scala:466:20] reg [1:0] uops_11_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_11_pdst; // @[util.scala:466:20] reg [6:0] uops_11_prs1; // @[util.scala:466:20] reg [6:0] uops_11_prs2; // @[util.scala:466:20] reg [6:0] uops_11_prs3; // @[util.scala:466:20] reg [4:0] uops_11_ppred; // @[util.scala:466:20] reg uops_11_prs1_busy; // @[util.scala:466:20] reg uops_11_prs2_busy; // @[util.scala:466:20] reg uops_11_prs3_busy; // @[util.scala:466:20] reg uops_11_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_11_stale_pdst; // @[util.scala:466:20] reg uops_11_exception; // @[util.scala:466:20] reg [63:0] uops_11_exc_cause; // @[util.scala:466:20] reg uops_11_bypassable; // @[util.scala:466:20] reg [4:0] uops_11_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_11_mem_size; // @[util.scala:466:20] reg uops_11_mem_signed; // @[util.scala:466:20] reg uops_11_is_fence; // @[util.scala:466:20] reg uops_11_is_fencei; // @[util.scala:466:20] reg uops_11_is_amo; // @[util.scala:466:20] reg uops_11_uses_ldq; // @[util.scala:466:20] reg uops_11_uses_stq; // @[util.scala:466:20] reg uops_11_is_sys_pc2epc; // @[util.scala:466:20] reg uops_11_is_unique; // @[util.scala:466:20] reg uops_11_flush_on_commit; // @[util.scala:466:20] reg uops_11_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_11_ldst; // @[util.scala:466:20] reg [5:0] uops_11_lrs1; // @[util.scala:466:20] reg [5:0] uops_11_lrs2; // @[util.scala:466:20] reg [5:0] uops_11_lrs3; // @[util.scala:466:20] reg uops_11_ldst_val; // @[util.scala:466:20] reg [1:0] uops_11_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:466:20] reg uops_11_frs3_en; // @[util.scala:466:20] reg uops_11_fp_val; // @[util.scala:466:20] reg uops_11_fp_single; // @[util.scala:466:20] reg uops_11_xcpt_pf_if; // @[util.scala:466:20] reg uops_11_xcpt_ae_if; // @[util.scala:466:20] reg uops_11_xcpt_ma_if; // @[util.scala:466:20] reg uops_11_bp_debug_if; // @[util.scala:466:20] reg uops_11_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_11_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_11_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_12_uopc; // @[util.scala:466:20] reg [31:0] uops_12_inst; // @[util.scala:466:20] reg [31:0] uops_12_debug_inst; // @[util.scala:466:20] reg uops_12_is_rvc; // @[util.scala:466:20] reg [39:0] uops_12_debug_pc; // @[util.scala:466:20] reg [2:0] uops_12_iq_type; // @[util.scala:466:20] reg [9:0] uops_12_fu_code; // @[util.scala:466:20] reg [3:0] uops_12_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_12_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_12_ctrl_op_fcn; // @[util.scala:466:20] reg uops_12_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_12_ctrl_is_load; // @[util.scala:466:20] reg uops_12_ctrl_is_sta; // @[util.scala:466:20] reg uops_12_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_12_iw_state; // @[util.scala:466:20] reg uops_12_iw_p1_poisoned; // @[util.scala:466:20] reg uops_12_iw_p2_poisoned; // @[util.scala:466:20] reg uops_12_is_br; // @[util.scala:466:20] reg uops_12_is_jalr; // @[util.scala:466:20] reg uops_12_is_jal; // @[util.scala:466:20] reg uops_12_is_sfb; // @[util.scala:466:20] reg [15:0] uops_12_br_mask; // @[util.scala:466:20] reg [3:0] uops_12_br_tag; // @[util.scala:466:20] reg [4:0] uops_12_ftq_idx; // @[util.scala:466:20] reg uops_12_edge_inst; // @[util.scala:466:20] reg [5:0] uops_12_pc_lob; // @[util.scala:466:20] reg uops_12_taken; // @[util.scala:466:20] reg [19:0] uops_12_imm_packed; // @[util.scala:466:20] reg [11:0] uops_12_csr_addr; // @[util.scala:466:20] reg [6:0] uops_12_rob_idx; // @[util.scala:466:20] reg [4:0] uops_12_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_12_stq_idx; // @[util.scala:466:20] reg [1:0] uops_12_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_12_pdst; // @[util.scala:466:20] reg [6:0] uops_12_prs1; // @[util.scala:466:20] reg [6:0] uops_12_prs2; // @[util.scala:466:20] reg [6:0] uops_12_prs3; // @[util.scala:466:20] reg [4:0] uops_12_ppred; // @[util.scala:466:20] reg uops_12_prs1_busy; // @[util.scala:466:20] reg uops_12_prs2_busy; // @[util.scala:466:20] reg uops_12_prs3_busy; // @[util.scala:466:20] reg uops_12_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_12_stale_pdst; // @[util.scala:466:20] reg uops_12_exception; // @[util.scala:466:20] reg [63:0] uops_12_exc_cause; // @[util.scala:466:20] reg uops_12_bypassable; // @[util.scala:466:20] reg [4:0] uops_12_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_12_mem_size; // @[util.scala:466:20] reg uops_12_mem_signed; // @[util.scala:466:20] reg uops_12_is_fence; // @[util.scala:466:20] reg uops_12_is_fencei; // @[util.scala:466:20] reg uops_12_is_amo; // @[util.scala:466:20] reg uops_12_uses_ldq; // @[util.scala:466:20] reg uops_12_uses_stq; // @[util.scala:466:20] reg uops_12_is_sys_pc2epc; // @[util.scala:466:20] reg uops_12_is_unique; // @[util.scala:466:20] reg uops_12_flush_on_commit; // @[util.scala:466:20] reg uops_12_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_12_ldst; // @[util.scala:466:20] reg [5:0] uops_12_lrs1; // @[util.scala:466:20] reg [5:0] uops_12_lrs2; // @[util.scala:466:20] reg [5:0] uops_12_lrs3; // @[util.scala:466:20] reg uops_12_ldst_val; // @[util.scala:466:20] reg [1:0] uops_12_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:466:20] reg uops_12_frs3_en; // @[util.scala:466:20] reg uops_12_fp_val; // @[util.scala:466:20] reg uops_12_fp_single; // @[util.scala:466:20] reg uops_12_xcpt_pf_if; // @[util.scala:466:20] reg uops_12_xcpt_ae_if; // @[util.scala:466:20] reg uops_12_xcpt_ma_if; // @[util.scala:466:20] reg uops_12_bp_debug_if; // @[util.scala:466:20] reg uops_12_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_12_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_12_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_13_uopc; // @[util.scala:466:20] reg [31:0] uops_13_inst; // @[util.scala:466:20] reg [31:0] uops_13_debug_inst; // @[util.scala:466:20] reg uops_13_is_rvc; // @[util.scala:466:20] reg [39:0] uops_13_debug_pc; // @[util.scala:466:20] reg [2:0] uops_13_iq_type; // @[util.scala:466:20] reg [9:0] uops_13_fu_code; // @[util.scala:466:20] reg [3:0] uops_13_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_13_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_13_ctrl_op_fcn; // @[util.scala:466:20] reg uops_13_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_13_ctrl_is_load; // @[util.scala:466:20] reg uops_13_ctrl_is_sta; // @[util.scala:466:20] reg uops_13_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_13_iw_state; // @[util.scala:466:20] reg uops_13_iw_p1_poisoned; // @[util.scala:466:20] reg uops_13_iw_p2_poisoned; // @[util.scala:466:20] reg uops_13_is_br; // @[util.scala:466:20] reg uops_13_is_jalr; // @[util.scala:466:20] reg uops_13_is_jal; // @[util.scala:466:20] reg uops_13_is_sfb; // @[util.scala:466:20] reg [15:0] uops_13_br_mask; // @[util.scala:466:20] reg [3:0] uops_13_br_tag; // @[util.scala:466:20] reg [4:0] uops_13_ftq_idx; // @[util.scala:466:20] reg uops_13_edge_inst; // @[util.scala:466:20] reg [5:0] uops_13_pc_lob; // @[util.scala:466:20] reg uops_13_taken; // @[util.scala:466:20] reg [19:0] uops_13_imm_packed; // @[util.scala:466:20] reg [11:0] uops_13_csr_addr; // @[util.scala:466:20] reg [6:0] uops_13_rob_idx; // @[util.scala:466:20] reg [4:0] uops_13_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_13_stq_idx; // @[util.scala:466:20] reg [1:0] uops_13_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_13_pdst; // @[util.scala:466:20] reg [6:0] uops_13_prs1; // @[util.scala:466:20] reg [6:0] uops_13_prs2; // @[util.scala:466:20] reg [6:0] uops_13_prs3; // @[util.scala:466:20] reg [4:0] uops_13_ppred; // @[util.scala:466:20] reg uops_13_prs1_busy; // @[util.scala:466:20] reg uops_13_prs2_busy; // @[util.scala:466:20] reg uops_13_prs3_busy; // @[util.scala:466:20] reg uops_13_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_13_stale_pdst; // @[util.scala:466:20] reg uops_13_exception; // @[util.scala:466:20] reg [63:0] uops_13_exc_cause; // @[util.scala:466:20] reg uops_13_bypassable; // @[util.scala:466:20] reg [4:0] uops_13_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_13_mem_size; // @[util.scala:466:20] reg uops_13_mem_signed; // @[util.scala:466:20] reg uops_13_is_fence; // @[util.scala:466:20] reg uops_13_is_fencei; // @[util.scala:466:20] reg uops_13_is_amo; // @[util.scala:466:20] reg uops_13_uses_ldq; // @[util.scala:466:20] reg uops_13_uses_stq; // @[util.scala:466:20] reg uops_13_is_sys_pc2epc; // @[util.scala:466:20] reg uops_13_is_unique; // @[util.scala:466:20] reg uops_13_flush_on_commit; // @[util.scala:466:20] reg uops_13_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_13_ldst; // @[util.scala:466:20] reg [5:0] uops_13_lrs1; // @[util.scala:466:20] reg [5:0] uops_13_lrs2; // @[util.scala:466:20] reg [5:0] uops_13_lrs3; // @[util.scala:466:20] reg uops_13_ldst_val; // @[util.scala:466:20] reg [1:0] uops_13_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:466:20] reg uops_13_frs3_en; // @[util.scala:466:20] reg uops_13_fp_val; // @[util.scala:466:20] reg uops_13_fp_single; // @[util.scala:466:20] reg uops_13_xcpt_pf_if; // @[util.scala:466:20] reg uops_13_xcpt_ae_if; // @[util.scala:466:20] reg uops_13_xcpt_ma_if; // @[util.scala:466:20] reg uops_13_bp_debug_if; // @[util.scala:466:20] reg uops_13_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_13_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_13_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_14_uopc; // @[util.scala:466:20] reg [31:0] uops_14_inst; // @[util.scala:466:20] reg [31:0] uops_14_debug_inst; // @[util.scala:466:20] reg uops_14_is_rvc; // @[util.scala:466:20] reg [39:0] uops_14_debug_pc; // @[util.scala:466:20] reg [2:0] uops_14_iq_type; // @[util.scala:466:20] reg [9:0] uops_14_fu_code; // @[util.scala:466:20] reg [3:0] uops_14_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_14_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_14_ctrl_op_fcn; // @[util.scala:466:20] reg uops_14_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_14_ctrl_is_load; // @[util.scala:466:20] reg uops_14_ctrl_is_sta; // @[util.scala:466:20] reg uops_14_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_14_iw_state; // @[util.scala:466:20] reg uops_14_iw_p1_poisoned; // @[util.scala:466:20] reg uops_14_iw_p2_poisoned; // @[util.scala:466:20] reg uops_14_is_br; // @[util.scala:466:20] reg uops_14_is_jalr; // @[util.scala:466:20] reg uops_14_is_jal; // @[util.scala:466:20] reg uops_14_is_sfb; // @[util.scala:466:20] reg [15:0] uops_14_br_mask; // @[util.scala:466:20] reg [3:0] uops_14_br_tag; // @[util.scala:466:20] reg [4:0] uops_14_ftq_idx; // @[util.scala:466:20] reg uops_14_edge_inst; // @[util.scala:466:20] reg [5:0] uops_14_pc_lob; // @[util.scala:466:20] reg uops_14_taken; // @[util.scala:466:20] reg [19:0] uops_14_imm_packed; // @[util.scala:466:20] reg [11:0] uops_14_csr_addr; // @[util.scala:466:20] reg [6:0] uops_14_rob_idx; // @[util.scala:466:20] reg [4:0] uops_14_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_14_stq_idx; // @[util.scala:466:20] reg [1:0] uops_14_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_14_pdst; // @[util.scala:466:20] reg [6:0] uops_14_prs1; // @[util.scala:466:20] reg [6:0] uops_14_prs2; // @[util.scala:466:20] reg [6:0] uops_14_prs3; // @[util.scala:466:20] reg [4:0] uops_14_ppred; // @[util.scala:466:20] reg uops_14_prs1_busy; // @[util.scala:466:20] reg uops_14_prs2_busy; // @[util.scala:466:20] reg uops_14_prs3_busy; // @[util.scala:466:20] reg uops_14_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_14_stale_pdst; // @[util.scala:466:20] reg uops_14_exception; // @[util.scala:466:20] reg [63:0] uops_14_exc_cause; // @[util.scala:466:20] reg uops_14_bypassable; // @[util.scala:466:20] reg [4:0] uops_14_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_14_mem_size; // @[util.scala:466:20] reg uops_14_mem_signed; // @[util.scala:466:20] reg uops_14_is_fence; // @[util.scala:466:20] reg uops_14_is_fencei; // @[util.scala:466:20] reg uops_14_is_amo; // @[util.scala:466:20] reg uops_14_uses_ldq; // @[util.scala:466:20] reg uops_14_uses_stq; // @[util.scala:466:20] reg uops_14_is_sys_pc2epc; // @[util.scala:466:20] reg uops_14_is_unique; // @[util.scala:466:20] reg uops_14_flush_on_commit; // @[util.scala:466:20] reg uops_14_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_14_ldst; // @[util.scala:466:20] reg [5:0] uops_14_lrs1; // @[util.scala:466:20] reg [5:0] uops_14_lrs2; // @[util.scala:466:20] reg [5:0] uops_14_lrs3; // @[util.scala:466:20] reg uops_14_ldst_val; // @[util.scala:466:20] reg [1:0] uops_14_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:466:20] reg uops_14_frs3_en; // @[util.scala:466:20] reg uops_14_fp_val; // @[util.scala:466:20] reg uops_14_fp_single; // @[util.scala:466:20] reg uops_14_xcpt_pf_if; // @[util.scala:466:20] reg uops_14_xcpt_ae_if; // @[util.scala:466:20] reg uops_14_xcpt_ma_if; // @[util.scala:466:20] reg uops_14_bp_debug_if; // @[util.scala:466:20] reg uops_14_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_14_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_14_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_15_uopc; // @[util.scala:466:20] reg [31:0] uops_15_inst; // @[util.scala:466:20] reg [31:0] uops_15_debug_inst; // @[util.scala:466:20] reg uops_15_is_rvc; // @[util.scala:466:20] reg [39:0] uops_15_debug_pc; // @[util.scala:466:20] reg [2:0] uops_15_iq_type; // @[util.scala:466:20] reg [9:0] uops_15_fu_code; // @[util.scala:466:20] reg [3:0] uops_15_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_15_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_15_ctrl_op_fcn; // @[util.scala:466:20] reg uops_15_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_15_ctrl_is_load; // @[util.scala:466:20] reg uops_15_ctrl_is_sta; // @[util.scala:466:20] reg uops_15_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_15_iw_state; // @[util.scala:466:20] reg uops_15_iw_p1_poisoned; // @[util.scala:466:20] reg uops_15_iw_p2_poisoned; // @[util.scala:466:20] reg uops_15_is_br; // @[util.scala:466:20] reg uops_15_is_jalr; // @[util.scala:466:20] reg uops_15_is_jal; // @[util.scala:466:20] reg uops_15_is_sfb; // @[util.scala:466:20] reg [15:0] uops_15_br_mask; // @[util.scala:466:20] reg [3:0] uops_15_br_tag; // @[util.scala:466:20] reg [4:0] uops_15_ftq_idx; // @[util.scala:466:20] reg uops_15_edge_inst; // @[util.scala:466:20] reg [5:0] uops_15_pc_lob; // @[util.scala:466:20] reg uops_15_taken; // @[util.scala:466:20] reg [19:0] uops_15_imm_packed; // @[util.scala:466:20] reg [11:0] uops_15_csr_addr; // @[util.scala:466:20] reg [6:0] uops_15_rob_idx; // @[util.scala:466:20] reg [4:0] uops_15_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_15_stq_idx; // @[util.scala:466:20] reg [1:0] uops_15_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_15_pdst; // @[util.scala:466:20] reg [6:0] uops_15_prs1; // @[util.scala:466:20] reg [6:0] uops_15_prs2; // @[util.scala:466:20] reg [6:0] uops_15_prs3; // @[util.scala:466:20] reg [4:0] uops_15_ppred; // @[util.scala:466:20] reg uops_15_prs1_busy; // @[util.scala:466:20] reg uops_15_prs2_busy; // @[util.scala:466:20] reg uops_15_prs3_busy; // @[util.scala:466:20] reg uops_15_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_15_stale_pdst; // @[util.scala:466:20] reg uops_15_exception; // @[util.scala:466:20] reg [63:0] uops_15_exc_cause; // @[util.scala:466:20] reg uops_15_bypassable; // @[util.scala:466:20] reg [4:0] uops_15_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_15_mem_size; // @[util.scala:466:20] reg uops_15_mem_signed; // @[util.scala:466:20] reg uops_15_is_fence; // @[util.scala:466:20] reg uops_15_is_fencei; // @[util.scala:466:20] reg uops_15_is_amo; // @[util.scala:466:20] reg uops_15_uses_ldq; // @[util.scala:466:20] reg uops_15_uses_stq; // @[util.scala:466:20] reg uops_15_is_sys_pc2epc; // @[util.scala:466:20] reg uops_15_is_unique; // @[util.scala:466:20] reg uops_15_flush_on_commit; // @[util.scala:466:20] reg uops_15_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_15_ldst; // @[util.scala:466:20] reg [5:0] uops_15_lrs1; // @[util.scala:466:20] reg [5:0] uops_15_lrs2; // @[util.scala:466:20] reg [5:0] uops_15_lrs3; // @[util.scala:466:20] reg uops_15_ldst_val; // @[util.scala:466:20] reg [1:0] uops_15_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs2_rtype; // @[util.scala:466:20] reg uops_15_frs3_en; // @[util.scala:466:20] reg uops_15_fp_val; // @[util.scala:466:20] reg uops_15_fp_single; // @[util.scala:466:20] reg uops_15_xcpt_pf_if; // @[util.scala:466:20] reg uops_15_xcpt_ae_if; // @[util.scala:466:20] reg uops_15_xcpt_ma_if; // @[util.scala:466:20] reg uops_15_bp_debug_if; // @[util.scala:466:20] reg uops_15_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_15_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_15_debug_tsrc; // @[util.scala:466:20] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:470:27] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:448:7, :473:25] wire _GEN = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24] wire full; // @[util.scala:474:24] assign full = _GEN; // @[util.scala:474:24] wire _io_count_T; // @[util.scala:526:32] assign _io_count_T = _GEN; // @[util.scala:474:24, :526:32] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35] wire [15:0] _GEN_0 = {{valids_15}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42] wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_1; // @[util.scala:476:42] wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:448:7, :476:{39,42}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:448:7, :476:69] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}] wire do_deq = _do_deq_T_3; // @[util.scala:476:{24,66}] wire [15:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_0_T_1 = |_valids_0_T; // @[util.scala:118:{51,59}] wire _valids_0_T_2 = ~_valids_0_T_1; // @[util.scala:118:59, :481:32] wire _valids_0_T_3 = valids_0 & _valids_0_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_0_T_4 = io_flush_0 & uops_0_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_0_T_5 = ~_valids_0_T_4; // @[util.scala:481:{72,83}] wire _valids_0_T_6 = _valids_0_T_3 & _valids_0_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_1_T_1 = |_valids_1_T; // @[util.scala:118:{51,59}] wire _valids_1_T_2 = ~_valids_1_T_1; // @[util.scala:118:59, :481:32] wire _valids_1_T_3 = valids_1 & _valids_1_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_1_T_4 = io_flush_0 & uops_1_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_1_T_5 = ~_valids_1_T_4; // @[util.scala:481:{72,83}] wire _valids_1_T_6 = _valids_1_T_3 & _valids_1_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_2_T_1 = |_valids_2_T; // @[util.scala:118:{51,59}] wire _valids_2_T_2 = ~_valids_2_T_1; // @[util.scala:118:59, :481:32] wire _valids_2_T_3 = valids_2 & _valids_2_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_2_T_4 = io_flush_0 & uops_2_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_2_T_5 = ~_valids_2_T_4; // @[util.scala:481:{72,83}] wire _valids_2_T_6 = _valids_2_T_3 & _valids_2_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_3_T = io_brupdate_b1_mispredict_mask_0 & uops_3_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_3_T_1 = |_valids_3_T; // @[util.scala:118:{51,59}] wire _valids_3_T_2 = ~_valids_3_T_1; // @[util.scala:118:59, :481:32] wire _valids_3_T_3 = valids_3 & _valids_3_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_3_T_4 = io_flush_0 & uops_3_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_3_T_5 = ~_valids_3_T_4; // @[util.scala:481:{72,83}] wire _valids_3_T_6 = _valids_3_T_3 & _valids_3_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_3_br_mask_T_1 = uops_3_br_mask & _uops_3_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_4_T = io_brupdate_b1_mispredict_mask_0 & uops_4_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_4_T_1 = |_valids_4_T; // @[util.scala:118:{51,59}] wire _valids_4_T_2 = ~_valids_4_T_1; // @[util.scala:118:59, :481:32] wire _valids_4_T_3 = valids_4 & _valids_4_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_4_T_4 = io_flush_0 & uops_4_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_4_T_5 = ~_valids_4_T_4; // @[util.scala:481:{72,83}] wire _valids_4_T_6 = _valids_4_T_3 & _valids_4_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_4_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_4_br_mask_T_1 = uops_4_br_mask & _uops_4_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_5_T = io_brupdate_b1_mispredict_mask_0 & uops_5_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_5_T_1 = |_valids_5_T; // @[util.scala:118:{51,59}] wire _valids_5_T_2 = ~_valids_5_T_1; // @[util.scala:118:59, :481:32] wire _valids_5_T_3 = valids_5 & _valids_5_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_5_T_4 = io_flush_0 & uops_5_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_5_T_5 = ~_valids_5_T_4; // @[util.scala:481:{72,83}] wire _valids_5_T_6 = _valids_5_T_3 & _valids_5_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_5_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_5_br_mask_T_1 = uops_5_br_mask & _uops_5_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_6_T = io_brupdate_b1_mispredict_mask_0 & uops_6_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_6_T_1 = |_valids_6_T; // @[util.scala:118:{51,59}] wire _valids_6_T_2 = ~_valids_6_T_1; // @[util.scala:118:59, :481:32] wire _valids_6_T_3 = valids_6 & _valids_6_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_6_T_4 = io_flush_0 & uops_6_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_6_T_5 = ~_valids_6_T_4; // @[util.scala:481:{72,83}] wire _valids_6_T_6 = _valids_6_T_3 & _valids_6_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_6_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_6_br_mask_T_1 = uops_6_br_mask & _uops_6_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_7_T = io_brupdate_b1_mispredict_mask_0 & uops_7_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_7_T_1 = |_valids_7_T; // @[util.scala:118:{51,59}] wire _valids_7_T_2 = ~_valids_7_T_1; // @[util.scala:118:59, :481:32] wire _valids_7_T_3 = valids_7 & _valids_7_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_7_T_4 = io_flush_0 & uops_7_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_7_T_5 = ~_valids_7_T_4; // @[util.scala:481:{72,83}] wire _valids_7_T_6 = _valids_7_T_3 & _valids_7_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_7_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_7_br_mask_T_1 = uops_7_br_mask & _uops_7_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_8_T = io_brupdate_b1_mispredict_mask_0 & uops_8_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_8_T_1 = |_valids_8_T; // @[util.scala:118:{51,59}] wire _valids_8_T_2 = ~_valids_8_T_1; // @[util.scala:118:59, :481:32] wire _valids_8_T_3 = valids_8 & _valids_8_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_8_T_4 = io_flush_0 & uops_8_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_8_T_5 = ~_valids_8_T_4; // @[util.scala:481:{72,83}] wire _valids_8_T_6 = _valids_8_T_3 & _valids_8_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_8_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_8_br_mask_T_1 = uops_8_br_mask & _uops_8_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_9_T = io_brupdate_b1_mispredict_mask_0 & uops_9_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_9_T_1 = |_valids_9_T; // @[util.scala:118:{51,59}] wire _valids_9_T_2 = ~_valids_9_T_1; // @[util.scala:118:59, :481:32] wire _valids_9_T_3 = valids_9 & _valids_9_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_9_T_4 = io_flush_0 & uops_9_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_9_T_5 = ~_valids_9_T_4; // @[util.scala:481:{72,83}] wire _valids_9_T_6 = _valids_9_T_3 & _valids_9_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_9_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_9_br_mask_T_1 = uops_9_br_mask & _uops_9_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_10_T = io_brupdate_b1_mispredict_mask_0 & uops_10_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_10_T_1 = |_valids_10_T; // @[util.scala:118:{51,59}] wire _valids_10_T_2 = ~_valids_10_T_1; // @[util.scala:118:59, :481:32] wire _valids_10_T_3 = valids_10 & _valids_10_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_10_T_4 = io_flush_0 & uops_10_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_10_T_5 = ~_valids_10_T_4; // @[util.scala:481:{72,83}] wire _valids_10_T_6 = _valids_10_T_3 & _valids_10_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_10_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_10_br_mask_T_1 = uops_10_br_mask & _uops_10_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_11_T = io_brupdate_b1_mispredict_mask_0 & uops_11_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_11_T_1 = |_valids_11_T; // @[util.scala:118:{51,59}] wire _valids_11_T_2 = ~_valids_11_T_1; // @[util.scala:118:59, :481:32] wire _valids_11_T_3 = valids_11 & _valids_11_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_11_T_4 = io_flush_0 & uops_11_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_11_T_5 = ~_valids_11_T_4; // @[util.scala:481:{72,83}] wire _valids_11_T_6 = _valids_11_T_3 & _valids_11_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_11_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_11_br_mask_T_1 = uops_11_br_mask & _uops_11_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_12_T = io_brupdate_b1_mispredict_mask_0 & uops_12_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_12_T_1 = |_valids_12_T; // @[util.scala:118:{51,59}] wire _valids_12_T_2 = ~_valids_12_T_1; // @[util.scala:118:59, :481:32] wire _valids_12_T_3 = valids_12 & _valids_12_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_12_T_4 = io_flush_0 & uops_12_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_12_T_5 = ~_valids_12_T_4; // @[util.scala:481:{72,83}] wire _valids_12_T_6 = _valids_12_T_3 & _valids_12_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_12_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_12_br_mask_T_1 = uops_12_br_mask & _uops_12_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_13_T = io_brupdate_b1_mispredict_mask_0 & uops_13_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_13_T_1 = |_valids_13_T; // @[util.scala:118:{51,59}] wire _valids_13_T_2 = ~_valids_13_T_1; // @[util.scala:118:59, :481:32] wire _valids_13_T_3 = valids_13 & _valids_13_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_13_T_4 = io_flush_0 & uops_13_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_13_T_5 = ~_valids_13_T_4; // @[util.scala:481:{72,83}] wire _valids_13_T_6 = _valids_13_T_3 & _valids_13_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_13_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_13_br_mask_T_1 = uops_13_br_mask & _uops_13_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_14_T = io_brupdate_b1_mispredict_mask_0 & uops_14_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_14_T_1 = |_valids_14_T; // @[util.scala:118:{51,59}] wire _valids_14_T_2 = ~_valids_14_T_1; // @[util.scala:118:59, :481:32] wire _valids_14_T_3 = valids_14 & _valids_14_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_14_T_4 = io_flush_0 & uops_14_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_14_T_5 = ~_valids_14_T_4; // @[util.scala:481:{72,83}] wire _valids_14_T_6 = _valids_14_T_3 & _valids_14_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_14_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_14_br_mask_T_1 = uops_14_br_mask & _uops_14_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_15_T = io_brupdate_b1_mispredict_mask_0 & uops_15_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_15_T_1 = |_valids_15_T; // @[util.scala:118:{51,59}] wire _valids_15_T_2 = ~_valids_15_T_1; // @[util.scala:118:59, :481:32] wire _valids_15_T_3 = valids_15 & _valids_15_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_15_T_4 = io_flush_0 & uops_15_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_15_T_5 = ~_valids_15_T_4; // @[util.scala:481:{72,83}] wire _valids_15_T_6 = _valids_15_T_3 & _valids_15_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_15_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_15_br_mask_T_1 = uops_15_br_mask & _uops_15_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] wire [15:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:85:{25,27}, :448:7] wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_3 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19] assign io_deq_bits_uop_uopc_0 = out_uop_uopc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iq_type_0 = out_uop_iq_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fu_code_0 = out_uop_fu_code; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_br_type_0 = out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op1_sel_0 = out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op2_sel_0 = out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_imm_sel_0 = out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op_fcn_0 = out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_fcn_dw_0 = out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_csr_cmd_0 = out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_load_0 = out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_sta_0 = out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_std_0 = out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_state_0 = out_uop_iw_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p1_poisoned_0 = out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p2_poisoned_0 = out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_br_0 = out_uop_is_br; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jalr_0 = out_uop_is_jalr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jal_0 = out_uop_is_jal; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_csr_addr_0 = out_uop_csr_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bypassable_0 = out_uop_bypassable; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_val_0 = out_uop_ldst_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_single_0 = out_uop_fp_single; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_data_0 = out_data; // @[util.scala:448:7, :506:17] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:448:7, :506:17] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_way_en = out_way_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:448:7, :506:17] wire [15:0] out_uop_br_mask; // @[util.scala:506:17] wire [15:0][6:0] _GEN_4 = {{uops_15_uopc}, {uops_14_uopc}, {uops_13_uopc}, {uops_12_uopc}, {uops_11_uopc}, {uops_10_uopc}, {uops_9_uopc}, {uops_8_uopc}, {uops_7_uopc}, {uops_6_uopc}, {uops_5_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19] assign out_uop_uopc = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_5 = {{uops_15_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_6 = {{uops_15_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_inst = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_15_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_rvc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][39:0] _GEN_8 = {{uops_15_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_pc = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_9 = {{uops_15_iq_type}, {uops_14_iq_type}, {uops_13_iq_type}, {uops_12_iq_type}, {uops_11_iq_type}, {uops_10_iq_type}, {uops_9_iq_type}, {uops_8_iq_type}, {uops_7_iq_type}, {uops_6_iq_type}, {uops_5_iq_type}, {uops_4_iq_type}, {uops_3_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19] assign out_uop_iq_type = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][9:0] _GEN_10 = {{uops_15_fu_code}, {uops_14_fu_code}, {uops_13_fu_code}, {uops_12_fu_code}, {uops_11_fu_code}, {uops_10_fu_code}, {uops_9_fu_code}, {uops_8_fu_code}, {uops_7_fu_code}, {uops_6_fu_code}, {uops_5_fu_code}, {uops_4_fu_code}, {uops_3_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19] assign out_uop_fu_code = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_11 = {{uops_15_ctrl_br_type}, {uops_14_ctrl_br_type}, {uops_13_ctrl_br_type}, {uops_12_ctrl_br_type}, {uops_11_ctrl_br_type}, {uops_10_ctrl_br_type}, {uops_9_ctrl_br_type}, {uops_8_ctrl_br_type}, {uops_7_ctrl_br_type}, {uops_6_ctrl_br_type}, {uops_5_ctrl_br_type}, {uops_4_ctrl_br_type}, {uops_3_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_br_type = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_12 = {{uops_15_ctrl_op1_sel}, {uops_14_ctrl_op1_sel}, {uops_13_ctrl_op1_sel}, {uops_12_ctrl_op1_sel}, {uops_11_ctrl_op1_sel}, {uops_10_ctrl_op1_sel}, {uops_9_ctrl_op1_sel}, {uops_8_ctrl_op1_sel}, {uops_7_ctrl_op1_sel}, {uops_6_ctrl_op1_sel}, {uops_5_ctrl_op1_sel}, {uops_4_ctrl_op1_sel}, {uops_3_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op1_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_13 = {{uops_15_ctrl_op2_sel}, {uops_14_ctrl_op2_sel}, {uops_13_ctrl_op2_sel}, {uops_12_ctrl_op2_sel}, {uops_11_ctrl_op2_sel}, {uops_10_ctrl_op2_sel}, {uops_9_ctrl_op2_sel}, {uops_8_ctrl_op2_sel}, {uops_7_ctrl_op2_sel}, {uops_6_ctrl_op2_sel}, {uops_5_ctrl_op2_sel}, {uops_4_ctrl_op2_sel}, {uops_3_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op2_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_14 = {{uops_15_ctrl_imm_sel}, {uops_14_ctrl_imm_sel}, {uops_13_ctrl_imm_sel}, {uops_12_ctrl_imm_sel}, {uops_11_ctrl_imm_sel}, {uops_10_ctrl_imm_sel}, {uops_9_ctrl_imm_sel}, {uops_8_ctrl_imm_sel}, {uops_7_ctrl_imm_sel}, {uops_6_ctrl_imm_sel}, {uops_5_ctrl_imm_sel}, {uops_4_ctrl_imm_sel}, {uops_3_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_imm_sel = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_15 = {{uops_15_ctrl_op_fcn}, {uops_14_ctrl_op_fcn}, {uops_13_ctrl_op_fcn}, {uops_12_ctrl_op_fcn}, {uops_11_ctrl_op_fcn}, {uops_10_ctrl_op_fcn}, {uops_9_ctrl_op_fcn}, {uops_8_ctrl_op_fcn}, {uops_7_ctrl_op_fcn}, {uops_6_ctrl_op_fcn}, {uops_5_ctrl_op_fcn}, {uops_4_ctrl_op_fcn}, {uops_3_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op_fcn = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_15_ctrl_fcn_dw}, {uops_14_ctrl_fcn_dw}, {uops_13_ctrl_fcn_dw}, {uops_12_ctrl_fcn_dw}, {uops_11_ctrl_fcn_dw}, {uops_10_ctrl_fcn_dw}, {uops_9_ctrl_fcn_dw}, {uops_8_ctrl_fcn_dw}, {uops_7_ctrl_fcn_dw}, {uops_6_ctrl_fcn_dw}, {uops_5_ctrl_fcn_dw}, {uops_4_ctrl_fcn_dw}, {uops_3_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_fcn_dw = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_17 = {{uops_15_ctrl_csr_cmd}, {uops_14_ctrl_csr_cmd}, {uops_13_ctrl_csr_cmd}, {uops_12_ctrl_csr_cmd}, {uops_11_ctrl_csr_cmd}, {uops_10_ctrl_csr_cmd}, {uops_9_ctrl_csr_cmd}, {uops_8_ctrl_csr_cmd}, {uops_7_ctrl_csr_cmd}, {uops_6_ctrl_csr_cmd}, {uops_5_ctrl_csr_cmd}, {uops_4_ctrl_csr_cmd}, {uops_3_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_csr_cmd = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_15_ctrl_is_load}, {uops_14_ctrl_is_load}, {uops_13_ctrl_is_load}, {uops_12_ctrl_is_load}, {uops_11_ctrl_is_load}, {uops_10_ctrl_is_load}, {uops_9_ctrl_is_load}, {uops_8_ctrl_is_load}, {uops_7_ctrl_is_load}, {uops_6_ctrl_is_load}, {uops_5_ctrl_is_load}, {uops_4_ctrl_is_load}, {uops_3_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_load = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_15_ctrl_is_sta}, {uops_14_ctrl_is_sta}, {uops_13_ctrl_is_sta}, {uops_12_ctrl_is_sta}, {uops_11_ctrl_is_sta}, {uops_10_ctrl_is_sta}, {uops_9_ctrl_is_sta}, {uops_8_ctrl_is_sta}, {uops_7_ctrl_is_sta}, {uops_6_ctrl_is_sta}, {uops_5_ctrl_is_sta}, {uops_4_ctrl_is_sta}, {uops_3_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_sta = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_15_ctrl_is_std}, {uops_14_ctrl_is_std}, {uops_13_ctrl_is_std}, {uops_12_ctrl_is_std}, {uops_11_ctrl_is_std}, {uops_10_ctrl_is_std}, {uops_9_ctrl_is_std}, {uops_8_ctrl_is_std}, {uops_7_ctrl_is_std}, {uops_6_ctrl_is_std}, {uops_5_ctrl_is_std}, {uops_4_ctrl_is_std}, {uops_3_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_std = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_21 = {{uops_15_iw_state}, {uops_14_iw_state}, {uops_13_iw_state}, {uops_12_iw_state}, {uops_11_iw_state}, {uops_10_iw_state}, {uops_9_iw_state}, {uops_8_iw_state}, {uops_7_iw_state}, {uops_6_iw_state}, {uops_5_iw_state}, {uops_4_iw_state}, {uops_3_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_state = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_15_iw_p1_poisoned}, {uops_14_iw_p1_poisoned}, {uops_13_iw_p1_poisoned}, {uops_12_iw_p1_poisoned}, {uops_11_iw_p1_poisoned}, {uops_10_iw_p1_poisoned}, {uops_9_iw_p1_poisoned}, {uops_8_iw_p1_poisoned}, {uops_7_iw_p1_poisoned}, {uops_6_iw_p1_poisoned}, {uops_5_iw_p1_poisoned}, {uops_4_iw_p1_poisoned}, {uops_3_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p1_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_15_iw_p2_poisoned}, {uops_14_iw_p2_poisoned}, {uops_13_iw_p2_poisoned}, {uops_12_iw_p2_poisoned}, {uops_11_iw_p2_poisoned}, {uops_10_iw_p2_poisoned}, {uops_9_iw_p2_poisoned}, {uops_8_iw_p2_poisoned}, {uops_7_iw_p2_poisoned}, {uops_6_iw_p2_poisoned}, {uops_5_iw_p2_poisoned}, {uops_4_iw_p2_poisoned}, {uops_3_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p2_poisoned = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_24 = {{uops_15_is_br}, {uops_14_is_br}, {uops_13_is_br}, {uops_12_is_br}, {uops_11_is_br}, {uops_10_is_br}, {uops_9_is_br}, {uops_8_is_br}, {uops_7_is_br}, {uops_6_is_br}, {uops_5_is_br}, {uops_4_is_br}, {uops_3_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19] assign out_uop_is_br = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_25 = {{uops_15_is_jalr}, {uops_14_is_jalr}, {uops_13_is_jalr}, {uops_12_is_jalr}, {uops_11_is_jalr}, {uops_10_is_jalr}, {uops_9_is_jalr}, {uops_8_is_jalr}, {uops_7_is_jalr}, {uops_6_is_jalr}, {uops_5_is_jalr}, {uops_4_is_jalr}, {uops_3_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jalr = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_15_is_jal}, {uops_14_is_jal}, {uops_13_is_jal}, {uops_12_is_jal}, {uops_11_is_jal}, {uops_10_is_jal}, {uops_9_is_jal}, {uops_8_is_jal}, {uops_7_is_jal}, {uops_6_is_jal}, {uops_5_is_jal}, {uops_4_is_jal}, {uops_3_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jal = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_15_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sfb = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][15:0] _GEN_28 = {{uops_15_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19] assign out_uop_br_mask = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_29 = {{uops_15_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19] assign out_uop_br_tag = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_30 = {{uops_15_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ftq_idx = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_31 = {{uops_15_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_edge_inst = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_32 = {{uops_15_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19] assign out_uop_pc_lob = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_15_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19] assign out_uop_taken = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_34 = {{uops_15_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19] assign out_uop_imm_packed = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][11:0] _GEN_35 = {{uops_15_csr_addr}, {uops_14_csr_addr}, {uops_13_csr_addr}, {uops_12_csr_addr}, {uops_11_csr_addr}, {uops_10_csr_addr}, {uops_9_csr_addr}, {uops_8_csr_addr}, {uops_7_csr_addr}, {uops_6_csr_addr}, {uops_5_csr_addr}, {uops_4_csr_addr}, {uops_3_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19] assign out_uop_csr_addr = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_36 = {{uops_15_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rob_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_37 = {{uops_15_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ldq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_38 = {{uops_15_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_stq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_39 = {{uops_15_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rxq_idx = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_40 = {{uops_15_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_pdst = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_41 = {{uops_15_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_42 = {{uops_15_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_43 = {{uops_15_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3 = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_44 = {{uops_15_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_15_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_15_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_47 = {{uops_15_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_48 = {{uops_15_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred_busy = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_49 = {{uops_15_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_stale_pdst = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_50 = {{uops_15_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19] assign out_uop_exception = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_51 = {{uops_15_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19] assign out_uop_exc_cause = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_15_bypassable}, {uops_14_bypassable}, {uops_13_bypassable}, {uops_12_bypassable}, {uops_11_bypassable}, {uops_10_bypassable}, {uops_9_bypassable}, {uops_8_bypassable}, {uops_7_bypassable}, {uops_6_bypassable}, {uops_5_bypassable}, {uops_4_bypassable}, {uops_3_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19] assign out_uop_bypassable = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_53 = {{uops_15_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_cmd = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_54 = {{uops_15_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_size = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_15_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_signed = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_15_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fence = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_15_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fencei = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_15_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19] assign out_uop_is_amo = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_59 = {{uops_15_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_ldq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_60 = {{uops_15_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_stq = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_15_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sys_pc2epc = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_15_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19] assign out_uop_is_unique = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_15_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19] assign out_uop_flush_on_commit = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_15_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_is_rs1 = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_65 = {{uops_15_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_66 = {{uops_15_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_67 = {{uops_15_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_68 = {{uops_15_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs3 = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_69 = {{uops_15_ldst_val}, {uops_14_ldst_val}, {uops_13_ldst_val}, {uops_12_ldst_val}, {uops_11_ldst_val}, {uops_10_ldst_val}, {uops_9_ldst_val}, {uops_8_ldst_val}, {uops_7_ldst_val}, {uops_6_ldst_val}, {uops_5_ldst_val}, {uops_4_ldst_val}, {uops_3_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_val = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_70 = {{uops_15_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_dst_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_71 = {{uops_15_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_15_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2_rtype = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_73 = {{uops_15_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19] assign out_uop_frs3_en = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_74 = {{uops_15_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_val = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_75 = {{uops_15_fp_single}, {uops_14_fp_single}, {uops_13_fp_single}, {uops_12_fp_single}, {uops_11_fp_single}, {uops_10_fp_single}, {uops_9_fp_single}, {uops_8_fp_single}, {uops_7_fp_single}, {uops_6_fp_single}, {uops_5_fp_single}, {uops_4_fp_single}, {uops_3_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_single = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_76 = {{uops_15_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_pf_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_77 = {{uops_15_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ae_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_15_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ma_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_15_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_debug_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_15_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_xcpt_if = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_81 = {{uops_15_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_fsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_82 = {{uops_15_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_tsrc = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:448:7, :476:69, :509:30] wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:476:42, :509:{30,40}] wire [15:0] _io_deq_valid_T_2 = io_brupdate_b1_mispredict_mask_0 & out_uop_br_mask; // @[util.scala:118:51, :448:7, :506:17] wire _io_deq_valid_T_3 = |_io_deq_valid_T_2; // @[util.scala:118:{51,59}] wire _io_deq_valid_T_4 = ~_io_deq_valid_T_3; // @[util.scala:118:59, :509:68] wire _io_deq_valid_T_5 = _io_deq_valid_T_1 & _io_deq_valid_T_4; // @[util.scala:509:{40,65,68}] wire _io_deq_valid_T_6 = io_flush_0 & out_uop_uses_ldq; // @[util.scala:448:7, :506:17, :509:122] wire _io_deq_valid_T_7 = ~_io_deq_valid_T_6; // @[util.scala:509:{111,122}] assign _io_deq_valid_T_8 = _io_deq_valid_T_5 & _io_deq_valid_T_7; // @[util.scala:509:{65,108,111}] assign io_deq_valid_0 = _io_deq_valid_T_8; // @[util.scala:448:7, :509:108] wire [15:0] _io_deq_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] assign _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask & _io_deq_bits_uop_br_mask_T; // @[util.scala:85:{25,27}, :506:17] assign io_deq_bits_uop_br_mask_0 = _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7] wire [4:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:524:40] wire [4:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:524:40, :526:{20,32}] assign io_count = _io_count_T_1[3:0]; // @[util.scala:448:7, :526:{14,20}] wire _GEN_83 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_84 = do_enq & _GEN_83; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_85 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_86 = do_enq & _GEN_85; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_87 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_88 = do_enq & _GEN_87; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_89 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_90 = do_enq & _GEN_89; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_91 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_92 = do_enq & _GEN_91; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_93 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_94 = do_enq & _GEN_93; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_95 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_96 = do_enq & _GEN_95; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_97 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_98 = do_enq & _GEN_97; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_99 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_100 = do_enq & _GEN_99; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_101 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_102 = do_enq & _GEN_101; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_103 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_104 = do_enq & _GEN_103; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_105 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_106 = do_enq & _GEN_105; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_107 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_108 = do_enq & _GEN_107; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_109 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_110 = do_enq & _GEN_109; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_111 = enq_ptr_value == 4'hE; // @[Counter.scala:61:40] wire _GEN_112 = do_enq & _GEN_111; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_113 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40] always @(posedge clock) begin // @[util.scala:448:7] if (reset) begin // @[util.scala:448:7] valids_0 <= 1'h0; // @[util.scala:465:24] valids_1 <= 1'h0; // @[util.scala:465:24] valids_2 <= 1'h0; // @[util.scala:465:24] valids_3 <= 1'h0; // @[util.scala:465:24] valids_4 <= 1'h0; // @[util.scala:465:24] valids_5 <= 1'h0; // @[util.scala:465:24] valids_6 <= 1'h0; // @[util.scala:465:24] valids_7 <= 1'h0; // @[util.scala:465:24] valids_8 <= 1'h0; // @[util.scala:465:24] valids_9 <= 1'h0; // @[util.scala:465:24] valids_10 <= 1'h0; // @[util.scala:465:24] valids_11 <= 1'h0; // @[util.scala:465:24] valids_12 <= 1'h0; // @[util.scala:465:24] valids_13 <= 1'h0; // @[util.scala:465:24] valids_14 <= 1'h0; // @[util.scala:465:24] valids_15 <= 1'h0; // @[util.scala:465:24] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:470:27] end else begin // @[util.scala:448:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_84 | _valids_0_T_6); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_86 | _valids_1_T_6); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_88 | _valids_2_T_6); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_90 | _valids_3_T_6); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_92 | _valids_4_T_6); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_94 | _valids_5_T_6); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_96 | _valids_6_T_6); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_98 | _valids_7_T_6); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_100 | _valids_8_T_6); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_102 | _valids_9_T_6); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_104 | _valids_10_T_6); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_106 | _valids_11_T_6); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_108 | _valids_12_T_6); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_110 | _valids_13_T_6); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & deq_ptr_value == 4'hE) & (_GEN_112 | _valids_14_T_6); // @[Counter.scala:61:40] valids_15 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_113 | _valids_15_T_6); // @[Counter.scala:61:40] if (do_enq) // @[util.scala:475:24] enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24] if (do_deq) // @[util.scala:476:24] deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24] if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16] maybe_full <= do_enq; // @[util.scala:470:27, :475:24] end if (_GEN_84) begin // @[util.scala:481:16, :487:17, :489:33] uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_83) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_0) // @[util.scala:465:24] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33] uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_85) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_1) // @[util.scala:465:24] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_88) begin // @[util.scala:481:16, :487:17, :489:33] uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_87) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_2) // @[util.scala:465:24] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_90) begin // @[util.scala:481:16, :487:17, :489:33] uops_3_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_3_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_3_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_3_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_3_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_3_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_3_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_3_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_3_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_3_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_3_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_89) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_3) // @[util.scala:465:24] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_92) begin // @[util.scala:481:16, :487:17, :489:33] uops_4_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_4_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_4_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_4_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_4_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_4_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_4_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_4_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_4_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_4_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_4_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_91) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_4) // @[util.scala:465:24] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_94) begin // @[util.scala:481:16, :487:17, :489:33] uops_5_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_5_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_5_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_5_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_5_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_5_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_5_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_5_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_5_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_5_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_5_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_93) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_5) // @[util.scala:465:24] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_96) begin // @[util.scala:481:16, :487:17, :489:33] uops_6_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_6_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_6_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_6_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_6_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_6_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_6_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_6_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_6_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_6_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_6_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_95) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_6) // @[util.scala:465:24] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_98) begin // @[util.scala:481:16, :487:17, :489:33] uops_7_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_7_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_7_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_7_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_7_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_7_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_7_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_7_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_7_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_7_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_7_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_97) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_7) // @[util.scala:465:24] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_100) begin // @[util.scala:481:16, :487:17, :489:33] uops_8_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_8_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_8_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_8_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_8_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_8_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_8_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_8_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_8_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_8_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_8_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_99) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_8) // @[util.scala:465:24] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_102) begin // @[util.scala:481:16, :487:17, :489:33] uops_9_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_9_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_9_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_9_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_9_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_9_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_9_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_9_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_9_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_9_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_9_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_101) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_9) // @[util.scala:465:24] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_104) begin // @[util.scala:481:16, :487:17, :489:33] uops_10_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_10_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_10_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_10_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_10_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_10_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_10_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_10_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_10_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_10_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_10_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_103) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_10) // @[util.scala:465:24] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_106) begin // @[util.scala:481:16, :487:17, :489:33] uops_11_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_11_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_11_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_11_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_11_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_11_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_11_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_11_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_11_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_11_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_11_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_105) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_11) // @[util.scala:465:24] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_108) begin // @[util.scala:481:16, :487:17, :489:33] uops_12_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_12_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_12_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_12_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_12_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_12_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_12_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_12_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_12_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_12_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_12_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_107) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_12) // @[util.scala:465:24] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_110) begin // @[util.scala:481:16, :487:17, :489:33] uops_13_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_13_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_13_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_13_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_13_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_13_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_13_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_13_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_13_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_13_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_13_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_109) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_13) // @[util.scala:465:24] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_112) begin // @[util.scala:481:16, :487:17, :489:33] uops_14_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_14_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_14_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_14_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_14_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_14_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_14_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_14_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_14_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_14_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_14_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_111) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_14) // @[util.scala:465:24] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_113) begin // @[util.scala:481:16, :487:17, :489:33] uops_15_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_15_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_15_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_15_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_15_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_15_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_15_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_15_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_15_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_15_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_15_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_15_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_15_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_15_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_15_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_15_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_15_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_15_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_15_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_15_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_15_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_15_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_15_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_15_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_15_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_15_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_15_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_15_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_15_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_15_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_15_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_15_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_15_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_15_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_15_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_15_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_15_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_15_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_15_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_15_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_15_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_15_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_15_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_15_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_15_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_15_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_15_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_15_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_15_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_15_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_15_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_15_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_15_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_15_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_15_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_15_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_15_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40] uops_15_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_15) // @[util.scala:465:24] uops_15_br_mask <= _uops_15_br_mask_T_1; // @[util.scala:89:21, :466:20] always @(posedge) ram_16x141 ram_ext ( // @[util.scala:464:20] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:475:24] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:448:7, :464:20] ); // @[util.scala:464:20] assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7] assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:448:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:448:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:448:7] assign io_empty = io_empty_0; // @[util.scala:448:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module CSRFile : input clock : Clock input reset : Reset output io : { flip ungated_clock : Clock, flip interrupts : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt<2>, rw : { flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, decode : { flip inst : UInt<32>, fp_illegal : UInt<1>, vector_illegal : UInt<1>, fp_csr : UInt<1>, vector_csr : UInt<1>, rocc_illegal : UInt<1>, read_illegal : UInt<1>, write_illegal : UInt<1>, write_flush : UInt<1>, system_illegal : UInt<1>, virtual_access_illegal : UInt<1>, virtual_system_illegal : UInt<1>}[1], csr_stall : UInt<1>, rw_stall : UInt<1>, eret : UInt<1>, singleStep : UInt<1>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, flip cause : UInt<64>, flip pc : UInt<40>, flip tval : UInt<40>, flip htval : UInt<40>, flip mhtinst_read_pseudo : UInt<1>, flip gva : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip rocc_interrupt : UInt<1>, interrupt : UInt<1>, interrupt_cause : UInt<64>, bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[1], pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], counters : { eventSel : UInt<64>, flip inc : UInt<1>}[0], csrw_counter : UInt<32>, inhibit_cycle : UInt<1>, flip inst : UInt<32>[1], trace : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], mcontext : UInt<0>, scontext : UInt<0>, fiom : UInt<1>, customCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4], roccCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]} connect io.rw_stall, UInt<1>(0h0) wire _reset_mstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect _reset_mstatus_WIRE.uie, UInt<1>(0h0) connect _reset_mstatus_WIRE.sie, UInt<1>(0h0) connect _reset_mstatus_WIRE.hie, UInt<1>(0h0) connect _reset_mstatus_WIRE.mie, UInt<1>(0h0) connect _reset_mstatus_WIRE.upie, UInt<1>(0h0) connect _reset_mstatus_WIRE.spie, UInt<1>(0h0) connect _reset_mstatus_WIRE.ube, UInt<1>(0h0) connect _reset_mstatus_WIRE.mpie, UInt<1>(0h0) connect _reset_mstatus_WIRE.spp, UInt<1>(0h0) connect _reset_mstatus_WIRE.vs, UInt<2>(0h0) connect _reset_mstatus_WIRE.mpp, UInt<2>(0h0) connect _reset_mstatus_WIRE.fs, UInt<2>(0h0) connect _reset_mstatus_WIRE.xs, UInt<2>(0h0) connect _reset_mstatus_WIRE.mprv, UInt<1>(0h0) connect _reset_mstatus_WIRE.sum, UInt<1>(0h0) connect _reset_mstatus_WIRE.mxr, UInt<1>(0h0) connect _reset_mstatus_WIRE.tvm, UInt<1>(0h0) connect _reset_mstatus_WIRE.tw, UInt<1>(0h0) connect _reset_mstatus_WIRE.tsr, UInt<1>(0h0) connect _reset_mstatus_WIRE.zero1, UInt<8>(0h0) connect _reset_mstatus_WIRE.sd_rv32, UInt<1>(0h0) connect _reset_mstatus_WIRE.uxl, UInt<2>(0h0) connect _reset_mstatus_WIRE.sxl, UInt<2>(0h0) connect _reset_mstatus_WIRE.sbe, UInt<1>(0h0) connect _reset_mstatus_WIRE.mbe, UInt<1>(0h0) connect _reset_mstatus_WIRE.gva, UInt<1>(0h0) connect _reset_mstatus_WIRE.mpv, UInt<1>(0h0) connect _reset_mstatus_WIRE.zero2, UInt<23>(0h0) connect _reset_mstatus_WIRE.sd, UInt<1>(0h0) connect _reset_mstatus_WIRE.v, UInt<1>(0h0) connect _reset_mstatus_WIRE.prv, UInt<2>(0h0) connect _reset_mstatus_WIRE.dv, UInt<1>(0h0) connect _reset_mstatus_WIRE.dprv, UInt<2>(0h0) connect _reset_mstatus_WIRE.isa, UInt<32>(0h0) connect _reset_mstatus_WIRE.wfi, UInt<1>(0h0) connect _reset_mstatus_WIRE.cease, UInt<1>(0h0) connect _reset_mstatus_WIRE.debug, UInt<1>(0h0) wire reset_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect reset_mstatus, _reset_mstatus_WIRE connect reset_mstatus.mpp, UInt<2>(0h3) connect reset_mstatus.prv, UInt<2>(0h3) connect reset_mstatus.xs, UInt<1>(0h0) regreset reg_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock, reset, reset_mstatus wire new_prv : UInt connect new_prv, reg_mstatus.prv node _reg_mstatus_prv_T = eq(new_prv, UInt<2>(0h2)) node _reg_mstatus_prv_T_1 = mux(_reg_mstatus_prv_T, UInt<1>(0h0), new_prv) connect reg_mstatus.prv, _reg_mstatus_prv_T_1 wire _reset_dcsr_WIRE : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} connect _reset_dcsr_WIRE.prv, UInt<2>(0h0) connect _reset_dcsr_WIRE.step, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero1, UInt<2>(0h0) connect _reset_dcsr_WIRE.v, UInt<1>(0h0) connect _reset_dcsr_WIRE.cause, UInt<3>(0h0) connect _reset_dcsr_WIRE.stoptime, UInt<1>(0h0) connect _reset_dcsr_WIRE.stopcycle, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero2, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreaku, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreaks, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreakh, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreakm, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero3, UInt<12>(0h0) connect _reset_dcsr_WIRE.zero4, UInt<2>(0h0) connect _reset_dcsr_WIRE.xdebugver, UInt<2>(0h0) wire reset_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} connect reset_dcsr, _reset_dcsr_WIRE connect reset_dcsr.xdebugver, UInt<1>(0h1) connect reset_dcsr.prv, UInt<2>(0h3) regreset reg_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>}, clock, reset, reset_dcsr wire sup : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect sup.usip, UInt<1>(0h0) connect sup.ssip, UInt<1>(0h1) connect sup.vssip, UInt<1>(0h0) connect sup.msip, UInt<1>(0h1) connect sup.utip, UInt<1>(0h0) connect sup.stip, UInt<1>(0h1) connect sup.vstip, UInt<1>(0h0) connect sup.mtip, UInt<1>(0h1) connect sup.ueip, UInt<1>(0h0) connect sup.seip, UInt<1>(0h1) connect sup.vseip, UInt<1>(0h0) connect sup.meip, UInt<1>(0h1) connect sup.sgeip, UInt<1>(0h0) connect sup.rocc, UInt<1>(0h0) connect sup.debug, UInt<1>(0h0) connect sup.zero1, UInt<1>(0h0) wire del : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect del, sup connect del.msip, UInt<1>(0h0) connect del.mtip, UInt<1>(0h0) connect del.meip, UInt<1>(0h0) node lo_lo_lo = cat(sup.ssip, sup.usip) node lo_lo_hi = cat(sup.msip, sup.vssip) node lo_lo = cat(lo_lo_hi, lo_lo_lo) node lo_hi_lo = cat(sup.stip, sup.utip) node lo_hi_hi = cat(sup.mtip, sup.vstip) node lo_hi = cat(lo_hi_hi, lo_hi_lo) node lo = cat(lo_hi, lo_lo) node hi_lo_lo = cat(sup.seip, sup.ueip) node hi_lo_hi = cat(sup.meip, sup.vseip) node hi_lo = cat(hi_lo_hi, hi_lo_lo) node hi_hi_lo = cat(sup.rocc, sup.sgeip) node hi_hi_hi_hi = cat(UInt<0>(0h0), sup.zero1) node hi_hi_hi = cat(hi_hi_hi_hi, sup.debug) node hi_hi = cat(hi_hi_hi, hi_hi_lo) node hi = cat(hi_hi, hi_lo) node _T = cat(hi, lo) node supported_interrupts = or(_T, UInt<1>(0h0)) node lo_lo_lo_1 = cat(del.ssip, del.usip) node lo_lo_hi_1 = cat(del.msip, del.vssip) node lo_lo_1 = cat(lo_lo_hi_1, lo_lo_lo_1) node lo_hi_lo_1 = cat(del.stip, del.utip) node lo_hi_hi_1 = cat(del.mtip, del.vstip) node lo_hi_1 = cat(lo_hi_hi_1, lo_hi_lo_1) node lo_1 = cat(lo_hi_1, lo_lo_1) node hi_lo_lo_1 = cat(del.seip, del.ueip) node hi_lo_hi_1 = cat(del.meip, del.vseip) node hi_lo_1 = cat(hi_lo_hi_1, hi_lo_lo_1) node hi_hi_lo_1 = cat(del.rocc, del.sgeip) node hi_hi_hi_hi_1 = cat(UInt<0>(0h0), del.zero1) node hi_hi_hi_1 = cat(hi_hi_hi_hi_1, del.debug) node hi_hi_1 = cat(hi_hi_hi_1, hi_hi_lo_1) node hi_1 = cat(hi_hi_1, hi_lo_1) node delegable_interrupts = cat(hi_1, lo_1) wire _always_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect _always_WIRE.usip, UInt<1>(0h0) connect _always_WIRE.ssip, UInt<1>(0h0) connect _always_WIRE.vssip, UInt<1>(0h0) connect _always_WIRE.msip, UInt<1>(0h0) connect _always_WIRE.utip, UInt<1>(0h0) connect _always_WIRE.stip, UInt<1>(0h0) connect _always_WIRE.vstip, UInt<1>(0h0) connect _always_WIRE.mtip, UInt<1>(0h0) connect _always_WIRE.ueip, UInt<1>(0h0) connect _always_WIRE.seip, UInt<1>(0h0) connect _always_WIRE.vseip, UInt<1>(0h0) connect _always_WIRE.meip, UInt<1>(0h0) connect _always_WIRE.sgeip, UInt<1>(0h0) connect _always_WIRE.rocc, UInt<1>(0h0) connect _always_WIRE.debug, UInt<1>(0h0) connect _always_WIRE.zero1, UInt<1>(0h0) wire always : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect always, _always_WIRE connect always.vssip, UInt<1>(0h0) connect always.vstip, UInt<1>(0h0) connect always.vseip, UInt<1>(0h0) wire deleg : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect deleg, always node lo_lo_lo_2 = cat(deleg.ssip, deleg.usip) node lo_lo_hi_2 = cat(deleg.msip, deleg.vssip) node lo_lo_2 = cat(lo_lo_hi_2, lo_lo_lo_2) node lo_hi_lo_2 = cat(deleg.stip, deleg.utip) node lo_hi_hi_2 = cat(deleg.mtip, deleg.vstip) node lo_hi_2 = cat(lo_hi_hi_2, lo_hi_lo_2) node lo_2 = cat(lo_hi_2, lo_lo_2) node hi_lo_lo_2 = cat(deleg.seip, deleg.ueip) node hi_lo_hi_2 = cat(deleg.meip, deleg.vseip) node hi_lo_2 = cat(hi_lo_hi_2, hi_lo_lo_2) node hi_hi_lo_2 = cat(deleg.rocc, deleg.sgeip) node hi_hi_hi_hi_2 = cat(UInt<0>(0h0), deleg.zero1) node hi_hi_hi_2 = cat(hi_hi_hi_hi_2, deleg.debug) node hi_hi_2 = cat(hi_hi_hi_2, hi_hi_lo_2) node hi_2 = cat(hi_hi_2, hi_lo_2) node hs_delegable_interrupts = cat(hi_2, lo_2) node lo_lo_lo_3 = cat(always.ssip, always.usip) node lo_lo_hi_3 = cat(always.msip, always.vssip) node lo_lo_3 = cat(lo_lo_hi_3, lo_lo_lo_3) node lo_hi_lo_3 = cat(always.stip, always.utip) node lo_hi_hi_3 = cat(always.mtip, always.vstip) node lo_hi_3 = cat(lo_hi_hi_3, lo_hi_lo_3) node lo_3 = cat(lo_hi_3, lo_lo_3) node hi_lo_lo_3 = cat(always.seip, always.ueip) node hi_lo_hi_3 = cat(always.meip, always.vseip) node hi_lo_3 = cat(hi_lo_hi_3, hi_lo_lo_3) node hi_hi_lo_3 = cat(always.rocc, always.sgeip) node hi_hi_hi_hi_3 = cat(UInt<0>(0h0), always.zero1) node hi_hi_hi_3 = cat(hi_hi_hi_hi_3, always.debug) node hi_hi_3 = cat(hi_hi_hi_3, hi_hi_lo_3) node hi_3 = cat(hi_hi_3, hi_lo_3) node mideleg_always_hs = cat(hi_3, lo_3) regreset reg_debug : UInt<1>, clock, reset, UInt<1>(0h0) reg reg_dpc : UInt<40>, clock reg reg_dscratch0 : UInt<64>, clock reg reg_singleStepped : UInt<1>, clock reg reg_tselect : UInt<1>, clock reg reg_bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[2], clock reg reg_pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>}[8], clock reg reg_mie : UInt<64>, clock reg reg_mideleg : UInt<64>, clock node _T_1 = and(reg_mideleg, delegable_interrupts) node _T_2 = or(_T_1, mideleg_always_hs) node read_mideleg = mux(UInt<1>(0h1), _T_2, UInt<1>(0h0)) reg reg_medeleg : UInt<64>, clock node _T_3 = and(reg_medeleg, UInt<16>(0hb15d)) node read_medeleg = mux(UInt<1>(0h1), _T_3, UInt<1>(0h0)) reg reg_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock reg reg_mepc : UInt<40>, clock regreset reg_mcause : UInt<64>, clock, reset, UInt<64>(0h0) reg reg_mtval : UInt<40>, clock reg reg_mtval2 : UInt<40>, clock reg reg_mscratch : UInt<64>, clock regreset reg_mtvec : UInt<32>, clock, reset, UInt<32>(0h0) wire _reset_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect _reset_mnstatus_WIRE.zero1, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mie, UInt<1>(0h0) connect _reset_mnstatus_WIRE.zero2, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mpv, UInt<1>(0h0) connect _reset_mnstatus_WIRE.zero3, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mpp, UInt<2>(0h0) wire reset_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect reset_mnstatus, _reset_mnstatus_WIRE connect reset_mnstatus.mpp, UInt<2>(0h3) reg reg_mnscratch : UInt<64>, clock reg reg_mnepc : UInt<40>, clock regreset reg_mncause : UInt<64>, clock, reset, UInt<64>(0h0) regreset reg_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}, clock, reset, reset_mnstatus regreset reg_rnmie : UInt<1>, clock, reset, UInt<1>(0h1) wire _reg_menvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_menvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_menvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_menvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_menvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_menvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_menvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_menvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_menvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_menvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_menvcfg_WIRE wire _reg_senvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_senvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_senvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_senvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_senvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_senvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_senvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_senvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_senvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_senvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_senvcfg_WIRE wire _reg_henvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_henvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_henvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_henvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_henvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_henvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_henvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_henvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_henvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_henvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_henvcfg_WIRE reg reg_mcounteren : UInt<32>, clock node _T_4 = and(reg_mcounteren, UInt<3>(0h7)) node read_mcounteren = mux(UInt<1>(0h1), _T_4, UInt<1>(0h0)) reg reg_scounteren : UInt<32>, clock node _T_5 = and(reg_scounteren, UInt<3>(0h7)) node read_scounteren = mux(UInt<1>(0h1), _T_5, UInt<1>(0h0)) reg reg_hideleg : UInt<64>, clock node _T_6 = and(reg_hideleg, hs_delegable_interrupts) node read_hideleg = mux(UInt<1>(0h0), _T_6, UInt<1>(0h0)) reg reg_hedeleg : UInt<64>, clock node _T_7 = and(reg_hedeleg, UInt<16>(0hb1ff)) node read_hedeleg = mux(UInt<1>(0h0), _T_7, UInt<1>(0h0)) reg reg_hcounteren : UInt<32>, clock node _T_8 = and(reg_hcounteren, UInt<3>(0h7)) node read_hcounteren = mux(UInt<1>(0h0), _T_8, UInt<1>(0h0)) wire _reg_hstatus_WIRE : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>} connect _reg_hstatus_WIRE.zero1, UInt<5>(0h0) connect _reg_hstatus_WIRE.vsbe, UInt<1>(0h0) connect _reg_hstatus_WIRE.gva, UInt<1>(0h0) connect _reg_hstatus_WIRE.spv, UInt<1>(0h0) connect _reg_hstatus_WIRE.spvp, UInt<1>(0h0) connect _reg_hstatus_WIRE.hu, UInt<1>(0h0) connect _reg_hstatus_WIRE.zero2, UInt<2>(0h0) connect _reg_hstatus_WIRE.vgein, UInt<6>(0h0) connect _reg_hstatus_WIRE.zero3, UInt<2>(0h0) connect _reg_hstatus_WIRE.vtvm, UInt<1>(0h0) connect _reg_hstatus_WIRE.vtw, UInt<1>(0h0) connect _reg_hstatus_WIRE.vtsr, UInt<1>(0h0) connect _reg_hstatus_WIRE.zero5, UInt<9>(0h0) connect _reg_hstatus_WIRE.vsxl, UInt<2>(0h0) connect _reg_hstatus_WIRE.zero6, UInt<30>(0h0) regreset reg_hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, clock, reset, _reg_hstatus_WIRE reg reg_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg reg_htval : UInt<40>, clock node read_hvip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip) node read_hvip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip) node read_hvip_lo_lo = cat(read_hvip_lo_lo_hi, read_hvip_lo_lo_lo) node read_hvip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip) node read_hvip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip) node read_hvip_lo_hi = cat(read_hvip_lo_hi_hi, read_hvip_lo_hi_lo) node read_hvip_lo = cat(read_hvip_lo_hi, read_hvip_lo_lo) node read_hvip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip) node read_hvip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip) node read_hvip_hi_lo = cat(read_hvip_hi_lo_hi, read_hvip_hi_lo_lo) node read_hvip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip) node read_hvip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1) node read_hvip_hi_hi_hi = cat(read_hvip_hi_hi_hi_hi, reg_mip.debug) node read_hvip_hi_hi = cat(read_hvip_hi_hi_hi, read_hvip_hi_hi_lo) node read_hvip_hi = cat(read_hvip_hi_hi, read_hvip_hi_lo) node _read_hvip_T = cat(read_hvip_hi, read_hvip_lo) node read_hvip = and(_read_hvip_T, hs_delegable_interrupts) node read_hie = and(reg_mie, hs_delegable_interrupts) reg reg_vstvec : UInt<40>, clock node _T_9 = bits(reg_vstvec, 0, 0) node _T_10 = mux(_T_9, UInt<8>(0hfe), UInt<2>(0h2)) node _T_11 = and(reg_vstvec, UInt<1>(0h0)) node _T_12 = or(_T_10, _T_11) node _T_13 = not(_T_12) node _T_14 = and(reg_vstvec, _T_13) node _T_15 = bits(_T_14, 39, 39) node _T_16 = mux(_T_15, UInt<24>(0hffffff), UInt<24>(0h0)) node read_vstvec = cat(_T_16, _T_14) reg reg_vsstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock reg reg_vsscratch : UInt<64>, clock reg reg_vsepc : UInt<40>, clock reg reg_vscause : UInt<64>, clock reg reg_vstval : UInt<40>, clock reg reg_vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg reg_sepc : UInt<40>, clock reg reg_scause : UInt<64>, clock reg reg_stval : UInt<40>, clock reg reg_sscratch : UInt<64>, clock reg reg_stvec : UInt<39>, clock reg reg_satp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock regreset reg_wfi : UInt<1>, io.ungated_clock, reset, UInt<1>(0h0) reg reg_fflags : UInt<5>, clock reg reg_frm : UInt<3>, clock reg reg_mtinst_read_pseudo : UInt<1>, clock reg reg_htinst_read_pseudo : UInt<1>, clock node hi_4 = cat(reg_mtinst_read_pseudo, reg_mtinst_read_pseudo) node read_mtinst = cat(hi_4, UInt<12>(0h0)) node hi_5 = cat(reg_htinst_read_pseudo, reg_htinst_read_pseudo) node read_htinst = cat(hi_5, UInt<12>(0h0)) regreset reg_mcountinhibit : UInt<3>, clock, reset, UInt<3>(0h0) node _io_inhibit_cycle_T = bits(reg_mcountinhibit, 0, 0) connect io.inhibit_cycle, _io_inhibit_cycle_T node x3 = bits(reg_mcountinhibit, 2, 2) regreset small : UInt<6>, clock, reset, UInt<6>(0h0) node nextSmall = add(small, io.retire) node _T_17 = eq(x3, UInt<1>(0h0)) when _T_17 : connect small, nextSmall regreset large : UInt<58>, clock, reset, UInt<58>(0h0) node _large_T = bits(nextSmall, 6, 6) node _large_T_1 = eq(x3, UInt<1>(0h0)) node _large_T_2 = and(_large_T, _large_T_1) when _large_T_2 : node _large_r_T = add(large, UInt<1>(0h1)) node _large_r_T_1 = tail(_large_r_T, 1) connect large, _large_r_T_1 node value = cat(large, small) node x10 = eq(io.csr_stall, UInt<1>(0h0)) node x11 = bits(reg_mcountinhibit, 0, 0) regreset small_1 : UInt<6>, io.ungated_clock, reset, UInt<6>(0h0) node nextSmall_1 = add(small_1, x10) node _T_18 = eq(x11, UInt<1>(0h0)) when _T_18 : connect small_1, nextSmall_1 regreset large_1 : UInt<58>, io.ungated_clock, reset, UInt<58>(0h0) node _large_T_3 = bits(nextSmall_1, 6, 6) node _large_T_4 = eq(x11, UInt<1>(0h0)) node _large_T_5 = and(_large_T_3, _large_T_4) when _large_T_5 : node _large_r_T_2 = add(large_1, UInt<1>(0h1)) node _large_r_T_3 = tail(_large_r_T_2, 1) connect large_1, _large_r_T_3 node value_1 = cat(large_1, small_1) wire mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect mip, reg_mip connect mip.mtip, io.interrupts.mtip connect mip.msip, io.interrupts.msip connect mip.meip, io.interrupts.meip node _mip_seip_T = or(reg_mip.seip, io.interrupts.seip) connect mip.seip, _mip_seip_T connect mip.rocc, io.rocc_interrupt node read_mip_lo_lo_lo = cat(mip.ssip, mip.usip) node read_mip_lo_lo_hi = cat(mip.msip, mip.vssip) node read_mip_lo_lo = cat(read_mip_lo_lo_hi, read_mip_lo_lo_lo) node read_mip_lo_hi_lo = cat(mip.stip, mip.utip) node read_mip_lo_hi_hi = cat(mip.mtip, mip.vstip) node read_mip_lo_hi = cat(read_mip_lo_hi_hi, read_mip_lo_hi_lo) node read_mip_lo = cat(read_mip_lo_hi, read_mip_lo_lo) node read_mip_hi_lo_lo = cat(mip.seip, mip.ueip) node read_mip_hi_lo_hi = cat(mip.meip, mip.vseip) node read_mip_hi_lo = cat(read_mip_hi_lo_hi, read_mip_hi_lo_lo) node read_mip_hi_hi_lo = cat(mip.rocc, mip.sgeip) node read_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), mip.zero1) node read_mip_hi_hi_hi = cat(read_mip_hi_hi_hi_hi, mip.debug) node read_mip_hi_hi = cat(read_mip_hi_hi_hi, read_mip_hi_hi_lo) node read_mip_hi = cat(read_mip_hi_hi, read_mip_hi_lo) node _read_mip_T = cat(read_mip_hi, read_mip_lo) node read_mip = and(_read_mip_T, supported_interrupts) node read_hip = and(read_mip, hs_delegable_interrupts) node _pending_interrupts_T = and(read_mip, reg_mie) node pending_interrupts = or(UInt<1>(0h0), _pending_interrupts_T) node d_interrupts = shl(io.interrupts.debug, 14) node _m_interrupts_T = leq(reg_mstatus.prv, UInt<1>(0h1)) node _m_interrupts_T_1 = or(_m_interrupts_T, reg_mstatus.mie) node _m_interrupts_T_2 = and(reg_rnmie, _m_interrupts_T_1) node _m_interrupts_T_3 = not(pending_interrupts) node _m_interrupts_T_4 = or(_m_interrupts_T_3, read_mideleg) node _m_interrupts_T_5 = not(_m_interrupts_T_4) node m_interrupts = mux(_m_interrupts_T_2, _m_interrupts_T_5, UInt<1>(0h0)) node _s_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1)) node _s_interrupts_T_1 = or(reg_mstatus.v, _s_interrupts_T) node _s_interrupts_T_2 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _s_interrupts_T_3 = and(_s_interrupts_T_2, reg_mstatus.sie) node _s_interrupts_T_4 = or(_s_interrupts_T_1, _s_interrupts_T_3) node _s_interrupts_T_5 = and(reg_rnmie, _s_interrupts_T_4) node _s_interrupts_T_6 = and(pending_interrupts, read_mideleg) node _s_interrupts_T_7 = not(read_hideleg) node _s_interrupts_T_8 = and(_s_interrupts_T_6, _s_interrupts_T_7) node s_interrupts = mux(_s_interrupts_T_5, _s_interrupts_T_8, UInt<1>(0h0)) node _vs_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1)) node _vs_interrupts_T_1 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _vs_interrupts_T_2 = and(_vs_interrupts_T_1, reg_vsstatus.sie) node _vs_interrupts_T_3 = or(_vs_interrupts_T, _vs_interrupts_T_2) node _vs_interrupts_T_4 = and(reg_mstatus.v, _vs_interrupts_T_3) node _vs_interrupts_T_5 = and(reg_rnmie, _vs_interrupts_T_4) node _vs_interrupts_T_6 = and(pending_interrupts, read_hideleg) node vs_interrupts = mux(_vs_interrupts_T_5, _vs_interrupts_T_6, UInt<1>(0h0)) node _any_T = bits(d_interrupts, 14, 14) node _any_T_1 = bits(d_interrupts, 13, 13) node _any_T_2 = bits(d_interrupts, 12, 12) node _any_T_3 = bits(d_interrupts, 11, 11) node _any_T_4 = bits(d_interrupts, 3, 3) node _any_T_5 = bits(d_interrupts, 7, 7) node _any_T_6 = bits(d_interrupts, 9, 9) node _any_T_7 = bits(d_interrupts, 1, 1) node _any_T_8 = bits(d_interrupts, 5, 5) node _any_T_9 = bits(d_interrupts, 10, 10) node _any_T_10 = bits(d_interrupts, 2, 2) node _any_T_11 = bits(d_interrupts, 6, 6) node _any_T_12 = bits(d_interrupts, 8, 8) node _any_T_13 = bits(d_interrupts, 0, 0) node _any_T_14 = bits(d_interrupts, 4, 4) node _any_T_15 = bits(m_interrupts, 15, 15) node _any_T_16 = bits(m_interrupts, 14, 14) node _any_T_17 = bits(m_interrupts, 13, 13) node _any_T_18 = bits(m_interrupts, 12, 12) node _any_T_19 = bits(m_interrupts, 11, 11) node _any_T_20 = bits(m_interrupts, 3, 3) node _any_T_21 = bits(m_interrupts, 7, 7) node _any_T_22 = bits(m_interrupts, 9, 9) node _any_T_23 = bits(m_interrupts, 1, 1) node _any_T_24 = bits(m_interrupts, 5, 5) node _any_T_25 = bits(m_interrupts, 10, 10) node _any_T_26 = bits(m_interrupts, 2, 2) node _any_T_27 = bits(m_interrupts, 6, 6) node _any_T_28 = bits(m_interrupts, 8, 8) node _any_T_29 = bits(m_interrupts, 0, 0) node _any_T_30 = bits(m_interrupts, 4, 4) node _any_T_31 = bits(s_interrupts, 15, 15) node _any_T_32 = bits(s_interrupts, 14, 14) node _any_T_33 = bits(s_interrupts, 13, 13) node _any_T_34 = bits(s_interrupts, 12, 12) node _any_T_35 = bits(s_interrupts, 11, 11) node _any_T_36 = bits(s_interrupts, 3, 3) node _any_T_37 = bits(s_interrupts, 7, 7) node _any_T_38 = bits(s_interrupts, 9, 9) node _any_T_39 = bits(s_interrupts, 1, 1) node _any_T_40 = bits(s_interrupts, 5, 5) node _any_T_41 = bits(s_interrupts, 10, 10) node _any_T_42 = bits(s_interrupts, 2, 2) node _any_T_43 = bits(s_interrupts, 6, 6) node _any_T_44 = bits(s_interrupts, 8, 8) node _any_T_45 = bits(s_interrupts, 0, 0) node _any_T_46 = bits(s_interrupts, 4, 4) node _any_T_47 = bits(vs_interrupts, 15, 15) node _any_T_48 = bits(vs_interrupts, 14, 14) node _any_T_49 = bits(vs_interrupts, 13, 13) node _any_T_50 = bits(vs_interrupts, 12, 12) node _any_T_51 = bits(vs_interrupts, 11, 11) node _any_T_52 = bits(vs_interrupts, 3, 3) node _any_T_53 = bits(vs_interrupts, 7, 7) node _any_T_54 = bits(vs_interrupts, 9, 9) node _any_T_55 = bits(vs_interrupts, 1, 1) node _any_T_56 = bits(vs_interrupts, 5, 5) node _any_T_57 = bits(vs_interrupts, 10, 10) node _any_T_58 = bits(vs_interrupts, 2, 2) node _any_T_59 = bits(vs_interrupts, 6, 6) node _any_T_60 = bits(vs_interrupts, 8, 8) node _any_T_61 = bits(vs_interrupts, 0, 0) node _any_T_62 = bits(vs_interrupts, 4, 4) node _any_T_63 = or(_any_T, _any_T_1) node _any_T_64 = or(_any_T_63, _any_T_2) node _any_T_65 = or(_any_T_64, _any_T_3) node _any_T_66 = or(_any_T_65, _any_T_4) node _any_T_67 = or(_any_T_66, _any_T_5) node _any_T_68 = or(_any_T_67, _any_T_6) node _any_T_69 = or(_any_T_68, _any_T_7) node _any_T_70 = or(_any_T_69, _any_T_8) node _any_T_71 = or(_any_T_70, _any_T_9) node _any_T_72 = or(_any_T_71, _any_T_10) node _any_T_73 = or(_any_T_72, _any_T_11) node _any_T_74 = or(_any_T_73, _any_T_12) node _any_T_75 = or(_any_T_74, _any_T_13) node _any_T_76 = or(_any_T_75, _any_T_14) node _any_T_77 = or(_any_T_76, UInt<1>(0h0)) node _any_T_78 = or(_any_T_77, _any_T_15) node _any_T_79 = or(_any_T_78, _any_T_16) node _any_T_80 = or(_any_T_79, _any_T_17) node _any_T_81 = or(_any_T_80, _any_T_18) node _any_T_82 = or(_any_T_81, _any_T_19) node _any_T_83 = or(_any_T_82, _any_T_20) node _any_T_84 = or(_any_T_83, _any_T_21) node _any_T_85 = or(_any_T_84, _any_T_22) node _any_T_86 = or(_any_T_85, _any_T_23) node _any_T_87 = or(_any_T_86, _any_T_24) node _any_T_88 = or(_any_T_87, _any_T_25) node _any_T_89 = or(_any_T_88, _any_T_26) node _any_T_90 = or(_any_T_89, _any_T_27) node _any_T_91 = or(_any_T_90, _any_T_28) node _any_T_92 = or(_any_T_91, _any_T_29) node _any_T_93 = or(_any_T_92, _any_T_30) node _any_T_94 = or(_any_T_93, _any_T_31) node _any_T_95 = or(_any_T_94, _any_T_32) node _any_T_96 = or(_any_T_95, _any_T_33) node _any_T_97 = or(_any_T_96, _any_T_34) node _any_T_98 = or(_any_T_97, _any_T_35) node _any_T_99 = or(_any_T_98, _any_T_36) node _any_T_100 = or(_any_T_99, _any_T_37) node _any_T_101 = or(_any_T_100, _any_T_38) node _any_T_102 = or(_any_T_101, _any_T_39) node _any_T_103 = or(_any_T_102, _any_T_40) node _any_T_104 = or(_any_T_103, _any_T_41) node _any_T_105 = or(_any_T_104, _any_T_42) node _any_T_106 = or(_any_T_105, _any_T_43) node _any_T_107 = or(_any_T_106, _any_T_44) node _any_T_108 = or(_any_T_107, _any_T_45) node _any_T_109 = or(_any_T_108, _any_T_46) node _any_T_110 = or(_any_T_109, _any_T_47) node _any_T_111 = or(_any_T_110, _any_T_48) node _any_T_112 = or(_any_T_111, _any_T_49) node _any_T_113 = or(_any_T_112, _any_T_50) node _any_T_114 = or(_any_T_113, _any_T_51) node _any_T_115 = or(_any_T_114, _any_T_52) node _any_T_116 = or(_any_T_115, _any_T_53) node _any_T_117 = or(_any_T_116, _any_T_54) node _any_T_118 = or(_any_T_117, _any_T_55) node _any_T_119 = or(_any_T_118, _any_T_56) node _any_T_120 = or(_any_T_119, _any_T_57) node _any_T_121 = or(_any_T_120, _any_T_58) node _any_T_122 = or(_any_T_121, _any_T_59) node _any_T_123 = or(_any_T_122, _any_T_60) node _any_T_124 = or(_any_T_123, _any_T_61) node anyInterrupt = or(_any_T_124, _any_T_62) node _which_T = bits(d_interrupts, 14, 14) node _which_T_1 = bits(d_interrupts, 13, 13) node _which_T_2 = bits(d_interrupts, 12, 12) node _which_T_3 = bits(d_interrupts, 11, 11) node _which_T_4 = bits(d_interrupts, 3, 3) node _which_T_5 = bits(d_interrupts, 7, 7) node _which_T_6 = bits(d_interrupts, 9, 9) node _which_T_7 = bits(d_interrupts, 1, 1) node _which_T_8 = bits(d_interrupts, 5, 5) node _which_T_9 = bits(d_interrupts, 10, 10) node _which_T_10 = bits(d_interrupts, 2, 2) node _which_T_11 = bits(d_interrupts, 6, 6) node _which_T_12 = bits(d_interrupts, 8, 8) node _which_T_13 = bits(d_interrupts, 0, 0) node _which_T_14 = bits(d_interrupts, 4, 4) node _which_T_15 = bits(m_interrupts, 15, 15) node _which_T_16 = bits(m_interrupts, 14, 14) node _which_T_17 = bits(m_interrupts, 13, 13) node _which_T_18 = bits(m_interrupts, 12, 12) node _which_T_19 = bits(m_interrupts, 11, 11) node _which_T_20 = bits(m_interrupts, 3, 3) node _which_T_21 = bits(m_interrupts, 7, 7) node _which_T_22 = bits(m_interrupts, 9, 9) node _which_T_23 = bits(m_interrupts, 1, 1) node _which_T_24 = bits(m_interrupts, 5, 5) node _which_T_25 = bits(m_interrupts, 10, 10) node _which_T_26 = bits(m_interrupts, 2, 2) node _which_T_27 = bits(m_interrupts, 6, 6) node _which_T_28 = bits(m_interrupts, 8, 8) node _which_T_29 = bits(m_interrupts, 0, 0) node _which_T_30 = bits(m_interrupts, 4, 4) node _which_T_31 = bits(s_interrupts, 15, 15) node _which_T_32 = bits(s_interrupts, 14, 14) node _which_T_33 = bits(s_interrupts, 13, 13) node _which_T_34 = bits(s_interrupts, 12, 12) node _which_T_35 = bits(s_interrupts, 11, 11) node _which_T_36 = bits(s_interrupts, 3, 3) node _which_T_37 = bits(s_interrupts, 7, 7) node _which_T_38 = bits(s_interrupts, 9, 9) node _which_T_39 = bits(s_interrupts, 1, 1) node _which_T_40 = bits(s_interrupts, 5, 5) node _which_T_41 = bits(s_interrupts, 10, 10) node _which_T_42 = bits(s_interrupts, 2, 2) node _which_T_43 = bits(s_interrupts, 6, 6) node _which_T_44 = bits(s_interrupts, 8, 8) node _which_T_45 = bits(s_interrupts, 0, 0) node _which_T_46 = bits(s_interrupts, 4, 4) node _which_T_47 = bits(vs_interrupts, 15, 15) node _which_T_48 = bits(vs_interrupts, 14, 14) node _which_T_49 = bits(vs_interrupts, 13, 13) node _which_T_50 = bits(vs_interrupts, 12, 12) node _which_T_51 = bits(vs_interrupts, 11, 11) node _which_T_52 = bits(vs_interrupts, 3, 3) node _which_T_53 = bits(vs_interrupts, 7, 7) node _which_T_54 = bits(vs_interrupts, 9, 9) node _which_T_55 = bits(vs_interrupts, 1, 1) node _which_T_56 = bits(vs_interrupts, 5, 5) node _which_T_57 = bits(vs_interrupts, 10, 10) node _which_T_58 = bits(vs_interrupts, 2, 2) node _which_T_59 = bits(vs_interrupts, 6, 6) node _which_T_60 = bits(vs_interrupts, 8, 8) node _which_T_61 = bits(vs_interrupts, 0, 0) node _which_T_62 = bits(vs_interrupts, 4, 4) node _which_T_63 = mux(_which_T_61, UInt<1>(0h0), UInt<3>(0h4)) node _which_T_64 = mux(_which_T_60, UInt<4>(0h8), _which_T_63) node _which_T_65 = mux(_which_T_59, UInt<3>(0h6), _which_T_64) node _which_T_66 = mux(_which_T_58, UInt<2>(0h2), _which_T_65) node _which_T_67 = mux(_which_T_57, UInt<4>(0ha), _which_T_66) node _which_T_68 = mux(_which_T_56, UInt<3>(0h5), _which_T_67) node _which_T_69 = mux(_which_T_55, UInt<1>(0h1), _which_T_68) node _which_T_70 = mux(_which_T_54, UInt<4>(0h9), _which_T_69) node _which_T_71 = mux(_which_T_53, UInt<3>(0h7), _which_T_70) node _which_T_72 = mux(_which_T_52, UInt<2>(0h3), _which_T_71) node _which_T_73 = mux(_which_T_51, UInt<4>(0hb), _which_T_72) node _which_T_74 = mux(_which_T_50, UInt<4>(0hc), _which_T_73) node _which_T_75 = mux(_which_T_49, UInt<4>(0hd), _which_T_74) node _which_T_76 = mux(_which_T_48, UInt<4>(0he), _which_T_75) node _which_T_77 = mux(_which_T_47, UInt<4>(0hf), _which_T_76) node _which_T_78 = mux(_which_T_46, UInt<3>(0h4), _which_T_77) node _which_T_79 = mux(_which_T_45, UInt<1>(0h0), _which_T_78) node _which_T_80 = mux(_which_T_44, UInt<4>(0h8), _which_T_79) node _which_T_81 = mux(_which_T_43, UInt<3>(0h6), _which_T_80) node _which_T_82 = mux(_which_T_42, UInt<2>(0h2), _which_T_81) node _which_T_83 = mux(_which_T_41, UInt<4>(0ha), _which_T_82) node _which_T_84 = mux(_which_T_40, UInt<3>(0h5), _which_T_83) node _which_T_85 = mux(_which_T_39, UInt<1>(0h1), _which_T_84) node _which_T_86 = mux(_which_T_38, UInt<4>(0h9), _which_T_85) node _which_T_87 = mux(_which_T_37, UInt<3>(0h7), _which_T_86) node _which_T_88 = mux(_which_T_36, UInt<2>(0h3), _which_T_87) node _which_T_89 = mux(_which_T_35, UInt<4>(0hb), _which_T_88) node _which_T_90 = mux(_which_T_34, UInt<4>(0hc), _which_T_89) node _which_T_91 = mux(_which_T_33, UInt<4>(0hd), _which_T_90) node _which_T_92 = mux(_which_T_32, UInt<4>(0he), _which_T_91) node _which_T_93 = mux(_which_T_31, UInt<4>(0hf), _which_T_92) node _which_T_94 = mux(_which_T_30, UInt<3>(0h4), _which_T_93) node _which_T_95 = mux(_which_T_29, UInt<1>(0h0), _which_T_94) node _which_T_96 = mux(_which_T_28, UInt<4>(0h8), _which_T_95) node _which_T_97 = mux(_which_T_27, UInt<3>(0h6), _which_T_96) node _which_T_98 = mux(_which_T_26, UInt<2>(0h2), _which_T_97) node _which_T_99 = mux(_which_T_25, UInt<4>(0ha), _which_T_98) node _which_T_100 = mux(_which_T_24, UInt<3>(0h5), _which_T_99) node _which_T_101 = mux(_which_T_23, UInt<1>(0h1), _which_T_100) node _which_T_102 = mux(_which_T_22, UInt<4>(0h9), _which_T_101) node _which_T_103 = mux(_which_T_21, UInt<3>(0h7), _which_T_102) node _which_T_104 = mux(_which_T_20, UInt<2>(0h3), _which_T_103) node _which_T_105 = mux(_which_T_19, UInt<4>(0hb), _which_T_104) node _which_T_106 = mux(_which_T_18, UInt<4>(0hc), _which_T_105) node _which_T_107 = mux(_which_T_17, UInt<4>(0hd), _which_T_106) node _which_T_108 = mux(_which_T_16, UInt<4>(0he), _which_T_107) node _which_T_109 = mux(_which_T_15, UInt<4>(0hf), _which_T_108) node _which_T_110 = mux(UInt<1>(0h0), UInt<1>(0h0), _which_T_109) node _which_T_111 = mux(_which_T_14, UInt<3>(0h4), _which_T_110) node _which_T_112 = mux(_which_T_13, UInt<1>(0h0), _which_T_111) node _which_T_113 = mux(_which_T_12, UInt<4>(0h8), _which_T_112) node _which_T_114 = mux(_which_T_11, UInt<3>(0h6), _which_T_113) node _which_T_115 = mux(_which_T_10, UInt<2>(0h2), _which_T_114) node _which_T_116 = mux(_which_T_9, UInt<4>(0ha), _which_T_115) node _which_T_117 = mux(_which_T_8, UInt<3>(0h5), _which_T_116) node _which_T_118 = mux(_which_T_7, UInt<1>(0h1), _which_T_117) node _which_T_119 = mux(_which_T_6, UInt<4>(0h9), _which_T_118) node _which_T_120 = mux(_which_T_5, UInt<3>(0h7), _which_T_119) node _which_T_121 = mux(_which_T_4, UInt<2>(0h3), _which_T_120) node _which_T_122 = mux(_which_T_3, UInt<4>(0hb), _which_T_121) node _which_T_123 = mux(_which_T_2, UInt<4>(0hc), _which_T_122) node _which_T_124 = mux(_which_T_1, UInt<4>(0hd), _which_T_123) node whichInterrupt = mux(_which_T, UInt<4>(0he), _which_T_124) node _interruptCause_T = shl(UInt<1>(0h0), 62) node _interruptCause_T_1 = add(UInt<64>(0h8000000000000000), _interruptCause_T) node _interruptCause_T_2 = tail(_interruptCause_T_1, 1) node _interruptCause_T_3 = add(_interruptCause_T_2, whichInterrupt) node interruptCause = tail(_interruptCause_T_3, 1) node _io_interrupt_T = eq(io.singleStep, UInt<1>(0h0)) node _io_interrupt_T_1 = and(anyInterrupt, _io_interrupt_T) node _io_interrupt_T_2 = or(_io_interrupt_T_1, reg_singleStepped) node _io_interrupt_T_3 = or(reg_debug, io.status.cease) node _io_interrupt_T_4 = eq(_io_interrupt_T_3, UInt<1>(0h0)) node _io_interrupt_T_5 = and(_io_interrupt_T_2, _io_interrupt_T_4) connect io.interrupt, _io_interrupt_T_5 connect io.interrupt_cause, interruptCause connect io.bp[0], reg_bp[0] connect io.mcontext, UInt<1>(0h0) connect io.scontext, UInt<1>(0h0) node _io_fiom_T = lt(reg_mstatus.prv, UInt<2>(0h3)) node _io_fiom_T_1 = and(_io_fiom_T, reg_menvcfg.fiom) node _io_fiom_T_2 = lt(reg_mstatus.prv, UInt<1>(0h1)) node _io_fiom_T_3 = and(_io_fiom_T_2, reg_senvcfg.fiom) node _io_fiom_T_4 = or(_io_fiom_T_1, _io_fiom_T_3) node _io_fiom_T_5 = and(reg_mstatus.v, reg_henvcfg.fiom) node _io_fiom_T_6 = or(_io_fiom_T_4, _io_fiom_T_5) connect io.fiom, _io_fiom_T_6 wire pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp.cfg, reg_pmp[0].cfg connect pmp.addr, reg_pmp[0].addr node _pmp_mask_base_T = bits(pmp.cfg.a, 0, 0) node _pmp_mask_base_T_1 = cat(pmp.addr, _pmp_mask_base_T) node _pmp_mask_base_T_2 = shr(UInt<2>(0h3), 2) node pmp_mask_base = or(_pmp_mask_base_T_1, _pmp_mask_base_T_2) node _pmp_mask_T = add(pmp_mask_base, UInt<1>(0h1)) node _pmp_mask_T_1 = tail(_pmp_mask_T, 1) node _pmp_mask_T_2 = not(_pmp_mask_T_1) node _pmp_mask_T_3 = and(pmp_mask_base, _pmp_mask_T_2) node _pmp_mask_T_4 = cat(_pmp_mask_T_3, UInt<2>(0h3)) connect pmp.mask, _pmp_mask_T_4 wire pmp_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_1.cfg, reg_pmp[1].cfg connect pmp_1.addr, reg_pmp[1].addr node _pmp_mask_base_T_3 = bits(pmp_1.cfg.a, 0, 0) node _pmp_mask_base_T_4 = cat(pmp_1.addr, _pmp_mask_base_T_3) node _pmp_mask_base_T_5 = shr(UInt<2>(0h3), 2) node pmp_mask_base_1 = or(_pmp_mask_base_T_4, _pmp_mask_base_T_5) node _pmp_mask_T_5 = add(pmp_mask_base_1, UInt<1>(0h1)) node _pmp_mask_T_6 = tail(_pmp_mask_T_5, 1) node _pmp_mask_T_7 = not(_pmp_mask_T_6) node _pmp_mask_T_8 = and(pmp_mask_base_1, _pmp_mask_T_7) node _pmp_mask_T_9 = cat(_pmp_mask_T_8, UInt<2>(0h3)) connect pmp_1.mask, _pmp_mask_T_9 wire pmp_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_2.cfg, reg_pmp[2].cfg connect pmp_2.addr, reg_pmp[2].addr node _pmp_mask_base_T_6 = bits(pmp_2.cfg.a, 0, 0) node _pmp_mask_base_T_7 = cat(pmp_2.addr, _pmp_mask_base_T_6) node _pmp_mask_base_T_8 = shr(UInt<2>(0h3), 2) node pmp_mask_base_2 = or(_pmp_mask_base_T_7, _pmp_mask_base_T_8) node _pmp_mask_T_10 = add(pmp_mask_base_2, UInt<1>(0h1)) node _pmp_mask_T_11 = tail(_pmp_mask_T_10, 1) node _pmp_mask_T_12 = not(_pmp_mask_T_11) node _pmp_mask_T_13 = and(pmp_mask_base_2, _pmp_mask_T_12) node _pmp_mask_T_14 = cat(_pmp_mask_T_13, UInt<2>(0h3)) connect pmp_2.mask, _pmp_mask_T_14 wire pmp_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_3.cfg, reg_pmp[3].cfg connect pmp_3.addr, reg_pmp[3].addr node _pmp_mask_base_T_9 = bits(pmp_3.cfg.a, 0, 0) node _pmp_mask_base_T_10 = cat(pmp_3.addr, _pmp_mask_base_T_9) node _pmp_mask_base_T_11 = shr(UInt<2>(0h3), 2) node pmp_mask_base_3 = or(_pmp_mask_base_T_10, _pmp_mask_base_T_11) node _pmp_mask_T_15 = add(pmp_mask_base_3, UInt<1>(0h1)) node _pmp_mask_T_16 = tail(_pmp_mask_T_15, 1) node _pmp_mask_T_17 = not(_pmp_mask_T_16) node _pmp_mask_T_18 = and(pmp_mask_base_3, _pmp_mask_T_17) node _pmp_mask_T_19 = cat(_pmp_mask_T_18, UInt<2>(0h3)) connect pmp_3.mask, _pmp_mask_T_19 wire pmp_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_4.cfg, reg_pmp[4].cfg connect pmp_4.addr, reg_pmp[4].addr node _pmp_mask_base_T_12 = bits(pmp_4.cfg.a, 0, 0) node _pmp_mask_base_T_13 = cat(pmp_4.addr, _pmp_mask_base_T_12) node _pmp_mask_base_T_14 = shr(UInt<2>(0h3), 2) node pmp_mask_base_4 = or(_pmp_mask_base_T_13, _pmp_mask_base_T_14) node _pmp_mask_T_20 = add(pmp_mask_base_4, UInt<1>(0h1)) node _pmp_mask_T_21 = tail(_pmp_mask_T_20, 1) node _pmp_mask_T_22 = not(_pmp_mask_T_21) node _pmp_mask_T_23 = and(pmp_mask_base_4, _pmp_mask_T_22) node _pmp_mask_T_24 = cat(_pmp_mask_T_23, UInt<2>(0h3)) connect pmp_4.mask, _pmp_mask_T_24 wire pmp_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_5.cfg, reg_pmp[5].cfg connect pmp_5.addr, reg_pmp[5].addr node _pmp_mask_base_T_15 = bits(pmp_5.cfg.a, 0, 0) node _pmp_mask_base_T_16 = cat(pmp_5.addr, _pmp_mask_base_T_15) node _pmp_mask_base_T_17 = shr(UInt<2>(0h3), 2) node pmp_mask_base_5 = or(_pmp_mask_base_T_16, _pmp_mask_base_T_17) node _pmp_mask_T_25 = add(pmp_mask_base_5, UInt<1>(0h1)) node _pmp_mask_T_26 = tail(_pmp_mask_T_25, 1) node _pmp_mask_T_27 = not(_pmp_mask_T_26) node _pmp_mask_T_28 = and(pmp_mask_base_5, _pmp_mask_T_27) node _pmp_mask_T_29 = cat(_pmp_mask_T_28, UInt<2>(0h3)) connect pmp_5.mask, _pmp_mask_T_29 wire pmp_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_6.cfg, reg_pmp[6].cfg connect pmp_6.addr, reg_pmp[6].addr node _pmp_mask_base_T_18 = bits(pmp_6.cfg.a, 0, 0) node _pmp_mask_base_T_19 = cat(pmp_6.addr, _pmp_mask_base_T_18) node _pmp_mask_base_T_20 = shr(UInt<2>(0h3), 2) node pmp_mask_base_6 = or(_pmp_mask_base_T_19, _pmp_mask_base_T_20) node _pmp_mask_T_30 = add(pmp_mask_base_6, UInt<1>(0h1)) node _pmp_mask_T_31 = tail(_pmp_mask_T_30, 1) node _pmp_mask_T_32 = not(_pmp_mask_T_31) node _pmp_mask_T_33 = and(pmp_mask_base_6, _pmp_mask_T_32) node _pmp_mask_T_34 = cat(_pmp_mask_T_33, UInt<2>(0h3)) connect pmp_6.mask, _pmp_mask_T_34 wire pmp_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_7.cfg, reg_pmp[7].cfg connect pmp_7.addr, reg_pmp[7].addr node _pmp_mask_base_T_21 = bits(pmp_7.cfg.a, 0, 0) node _pmp_mask_base_T_22 = cat(pmp_7.addr, _pmp_mask_base_T_21) node _pmp_mask_base_T_23 = shr(UInt<2>(0h3), 2) node pmp_mask_base_7 = or(_pmp_mask_base_T_22, _pmp_mask_base_T_23) node _pmp_mask_T_35 = add(pmp_mask_base_7, UInt<1>(0h1)) node _pmp_mask_T_36 = tail(_pmp_mask_T_35, 1) node _pmp_mask_T_37 = not(_pmp_mask_T_36) node _pmp_mask_T_38 = and(pmp_mask_base_7, _pmp_mask_T_37) node _pmp_mask_T_39 = cat(_pmp_mask_T_38, UInt<2>(0h3)) connect pmp_7.mask, _pmp_mask_T_39 connect io.pmp[0], pmp connect io.pmp[1], pmp_1 connect io.pmp[2], pmp_2 connect io.pmp[3], pmp_3 connect io.pmp[4], pmp_4 connect io.pmp[5], pmp_5 connect io.pmp[6], pmp_6 connect io.pmp[7], pmp_7 regreset reg_misa : UInt, clock, reset, UInt<64>(0h800000000094112d) node read_mstatus_lo_lo_lo_lo = cat(io.status.sie, io.status.uie) node read_mstatus_lo_lo_lo_hi = cat(io.status.mie, io.status.hie) node read_mstatus_lo_lo_lo = cat(read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo) node read_mstatus_lo_lo_hi_lo = cat(io.status.spie, io.status.upie) node read_mstatus_lo_lo_hi_hi_hi = cat(io.status.spp, io.status.mpie) node read_mstatus_lo_lo_hi_hi = cat(read_mstatus_lo_lo_hi_hi_hi, io.status.ube) node read_mstatus_lo_lo_hi = cat(read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo) node read_mstatus_lo_lo = cat(read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo) node read_mstatus_lo_hi_lo_lo = cat(io.status.mpp, io.status.vs) node read_mstatus_lo_hi_lo_hi = cat(io.status.xs, io.status.fs) node read_mstatus_lo_hi_lo = cat(read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo) node read_mstatus_lo_hi_hi_lo = cat(io.status.sum, io.status.mprv) node read_mstatus_lo_hi_hi_hi_hi = cat(io.status.tw, io.status.tvm) node read_mstatus_lo_hi_hi_hi = cat(read_mstatus_lo_hi_hi_hi_hi, io.status.mxr) node read_mstatus_lo_hi_hi = cat(read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo) node read_mstatus_lo_hi = cat(read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo) node read_mstatus_lo = cat(read_mstatus_lo_hi, read_mstatus_lo_lo) node read_mstatus_hi_lo_lo_lo = cat(io.status.zero1, io.status.tsr) node read_mstatus_hi_lo_lo_hi = cat(io.status.uxl, io.status.sd_rv32) node read_mstatus_hi_lo_lo = cat(read_mstatus_hi_lo_lo_hi, read_mstatus_hi_lo_lo_lo) node read_mstatus_hi_lo_hi_lo = cat(io.status.sbe, io.status.sxl) node read_mstatus_hi_lo_hi_hi_hi = cat(io.status.mpv, io.status.gva) node read_mstatus_hi_lo_hi_hi = cat(read_mstatus_hi_lo_hi_hi_hi, io.status.mbe) node read_mstatus_hi_lo_hi = cat(read_mstatus_hi_lo_hi_hi, read_mstatus_hi_lo_hi_lo) node read_mstatus_hi_lo = cat(read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo) node read_mstatus_hi_hi_lo_lo = cat(io.status.sd, io.status.zero2) node read_mstatus_hi_hi_lo_hi_hi = cat(io.status.dv, io.status.prv) node read_mstatus_hi_hi_lo_hi = cat(read_mstatus_hi_hi_lo_hi_hi, io.status.v) node read_mstatus_hi_hi_lo = cat(read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo) node read_mstatus_hi_hi_hi_lo = cat(io.status.isa, io.status.dprv) node read_mstatus_hi_hi_hi_hi_hi = cat(io.status.debug, io.status.cease) node read_mstatus_hi_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi_hi, io.status.wfi) node read_mstatus_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo) node read_mstatus_hi_hi = cat(read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo) node read_mstatus_hi = cat(read_mstatus_hi_hi, read_mstatus_hi_lo) node _read_mstatus_T = cat(read_mstatus_hi, read_mstatus_lo) node read_mstatus = bits(_read_mstatus_T, 63, 0) node _read_mtvec_T = bits(reg_mtvec, 0, 0) node _read_mtvec_T_1 = mux(_read_mtvec_T, UInt<8>(0hfe), UInt<2>(0h2)) node _read_mtvec_T_2 = and(reg_mtvec, UInt<1>(0h0)) node _read_mtvec_T_3 = or(_read_mtvec_T_1, _read_mtvec_T_2) node _read_mtvec_T_4 = not(_read_mtvec_T_3) node _read_mtvec_T_5 = and(reg_mtvec, _read_mtvec_T_4) node read_mtvec = cat(UInt<32>(0h0), _read_mtvec_T_5) node _read_stvec_T = bits(reg_stvec, 0, 0) node _read_stvec_T_1 = mux(_read_stvec_T, UInt<8>(0hfe), UInt<2>(0h2)) node _read_stvec_T_2 = and(reg_stvec, UInt<1>(0h0)) node _read_stvec_T_3 = or(_read_stvec_T_1, _read_stvec_T_2) node _read_stvec_T_4 = not(_read_stvec_T_3) node _read_stvec_T_5 = and(reg_stvec, _read_stvec_T_4) node _read_stvec_T_6 = bits(_read_stvec_T_5, 38, 38) node _read_stvec_T_7 = mux(_read_stvec_T_6, UInt<25>(0h1ffffff), UInt<25>(0h0)) node read_stvec = cat(_read_stvec_T_7, _read_stvec_T_5) node read_mapping_lo_lo_hi = cat(reg_bp[reg_tselect].control.x, reg_bp[reg_tselect].control.w) node read_mapping_lo_lo = cat(read_mapping_lo_lo_hi, reg_bp[reg_tselect].control.r) node read_mapping_lo_hi_lo = cat(reg_bp[reg_tselect].control.s, reg_bp[reg_tselect].control.u) node read_mapping_lo_hi_hi = cat(reg_bp[reg_tselect].control.m, reg_bp[reg_tselect].control.h) node read_mapping_lo_hi = cat(read_mapping_lo_hi_hi, read_mapping_lo_hi_lo) node read_mapping_lo = cat(read_mapping_lo_hi, read_mapping_lo_lo) node read_mapping_hi_lo_lo = cat(reg_bp[reg_tselect].control.zero, reg_bp[reg_tselect].control.tmatch) node read_mapping_hi_lo_hi = cat(reg_bp[reg_tselect].control.action, reg_bp[reg_tselect].control.chain) node read_mapping_hi_lo = cat(read_mapping_hi_lo_hi, read_mapping_hi_lo_lo) node read_mapping_hi_hi_lo = cat(reg_bp[reg_tselect].control.maskmax, reg_bp[reg_tselect].control.reserved) node read_mapping_hi_hi_hi = cat(reg_bp[reg_tselect].control.ttype, reg_bp[reg_tselect].control.dmode) node read_mapping_hi_hi = cat(read_mapping_hi_hi_hi, read_mapping_hi_hi_lo) node read_mapping_hi = cat(read_mapping_hi_hi, read_mapping_hi_lo) node read_mapping_1_2 = cat(read_mapping_hi, read_mapping_lo) node _read_mapping_T = bits(reg_bp[reg_tselect].address, 38, 38) node _read_mapping_T_1 = mux(_read_mapping_T, UInt<25>(0h1ffffff), UInt<25>(0h0)) node read_mapping_2_2 = cat(_read_mapping_T_1, reg_bp[reg_tselect].address) node read_mapping_lo_hi_1 = cat(reg_bp[reg_tselect].textra.svalue, reg_bp[reg_tselect].textra.pad1) node read_mapping_lo_1 = cat(read_mapping_lo_hi_1, reg_bp[reg_tselect].textra.sselect) node read_mapping_hi_hi_1 = cat(reg_bp[reg_tselect].textra.mvalue, reg_bp[reg_tselect].textra.mselect) node read_mapping_hi_1 = cat(read_mapping_hi_hi_1, reg_bp[reg_tselect].textra.pad2) node read_mapping_3_2 = cat(read_mapping_hi_1, read_mapping_lo_1) node _read_mapping_T_2 = not(reg_mepc) node _read_mapping_T_3 = bits(reg_misa, 2, 2) node _read_mapping_T_4 = mux(_read_mapping_T_3, UInt<1>(0h1), UInt<2>(0h3)) node _read_mapping_T_5 = or(_read_mapping_T_2, _read_mapping_T_4) node _read_mapping_T_6 = not(_read_mapping_T_5) node _read_mapping_T_7 = bits(_read_mapping_T_6, 39, 39) node _read_mapping_T_8 = mux(_read_mapping_T_7, UInt<24>(0hffffff), UInt<24>(0h0)) node read_mapping_10_2 = cat(_read_mapping_T_8, _read_mapping_T_6) node _read_mapping_T_9 = bits(reg_mtval, 39, 39) node _read_mapping_T_10 = mux(_read_mapping_T_9, UInt<24>(0hffffff), UInt<24>(0h0)) node read_mapping_11_2 = cat(_read_mapping_T_10, reg_mtval) node debug_csrs_lo_lo_hi = cat(reg_dcsr.zero1, reg_dcsr.step) node debug_csrs_lo_lo = cat(debug_csrs_lo_lo_hi, reg_dcsr.prv) node debug_csrs_lo_hi_lo = cat(reg_dcsr.cause, reg_dcsr.v) node debug_csrs_lo_hi_hi = cat(reg_dcsr.stopcycle, reg_dcsr.stoptime) node debug_csrs_lo_hi = cat(debug_csrs_lo_hi_hi, debug_csrs_lo_hi_lo) node debug_csrs_lo = cat(debug_csrs_lo_hi, debug_csrs_lo_lo) node debug_csrs_hi_lo_lo = cat(reg_dcsr.ebreaku, reg_dcsr.zero2) node debug_csrs_hi_lo_hi = cat(reg_dcsr.ebreakh, reg_dcsr.ebreaks) node debug_csrs_hi_lo = cat(debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo) node debug_csrs_hi_hi_lo = cat(reg_dcsr.zero3, reg_dcsr.ebreakm) node debug_csrs_hi_hi_hi = cat(reg_dcsr.xdebugver, reg_dcsr.zero4) node debug_csrs_hi_hi = cat(debug_csrs_hi_hi_hi, debug_csrs_hi_hi_lo) node debug_csrs_hi = cat(debug_csrs_hi_hi, debug_csrs_hi_lo) node debug_csrs_0_2 = cat(debug_csrs_hi, debug_csrs_lo) node _debug_csrs_T = not(reg_dpc) node _debug_csrs_T_1 = bits(reg_misa, 2, 2) node _debug_csrs_T_2 = mux(_debug_csrs_T_1, UInt<1>(0h1), UInt<2>(0h3)) node _debug_csrs_T_3 = or(_debug_csrs_T, _debug_csrs_T_2) node _debug_csrs_T_4 = not(_debug_csrs_T_3) node _debug_csrs_T_5 = bits(_debug_csrs_T_4, 39, 39) node _debug_csrs_T_6 = mux(_debug_csrs_T_5, UInt<24>(0hffffff), UInt<24>(0h0)) node debug_csrs_1_2 = cat(_debug_csrs_T_6, _debug_csrs_T_4) wire _read_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect _read_mnstatus_WIRE.zero1, UInt<3>(0h0) connect _read_mnstatus_WIRE.mie, UInt<1>(0h0) connect _read_mnstatus_WIRE.zero2, UInt<3>(0h0) connect _read_mnstatus_WIRE.mpv, UInt<1>(0h0) connect _read_mnstatus_WIRE.zero3, UInt<3>(0h0) connect _read_mnstatus_WIRE.mpp, UInt<2>(0h0) wire read_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect read_mnstatus, _read_mnstatus_WIRE connect read_mnstatus.mpp, reg_mnstatus.mpp connect read_mnstatus.mpv, reg_mnstatus.mpv connect read_mnstatus.mie, reg_rnmie node read_fcsr = cat(reg_frm, reg_fflags) node read_vcsr = cat(UInt<1>(0h0), UInt<1>(0h0)) node lo_lo_4 = cat(reg_menvcfg.zero3, reg_menvcfg.fiom) node lo_hi_4 = cat(reg_menvcfg.cbcfe, reg_menvcfg.cbie) node lo_4 = cat(lo_hi_4, lo_lo_4) node hi_lo_4 = cat(reg_menvcfg.zero54, reg_menvcfg.cbze) node hi_hi_4 = cat(reg_menvcfg.stce, reg_menvcfg.pbmte) node hi_6 = cat(hi_hi_4, hi_lo_4) node _T_19 = cat(hi_6, lo_4) wire _sie_mask_sgeip_mask_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect _sie_mask_sgeip_mask_WIRE.usip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.ssip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vssip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.msip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.utip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.stip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vstip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.mtip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.ueip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.seip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vseip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.meip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.sgeip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.rocc, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.debug, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.zero1, UInt<1>(0h0) wire sie_mask_sgeip_mask : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect sie_mask_sgeip_mask, _sie_mask_sgeip_mask_WIRE connect sie_mask_sgeip_mask.sgeip, UInt<1>(0h1) node sie_mask_lo_lo_lo = cat(sie_mask_sgeip_mask.ssip, sie_mask_sgeip_mask.usip) node sie_mask_lo_lo_hi = cat(sie_mask_sgeip_mask.msip, sie_mask_sgeip_mask.vssip) node sie_mask_lo_lo = cat(sie_mask_lo_lo_hi, sie_mask_lo_lo_lo) node sie_mask_lo_hi_lo = cat(sie_mask_sgeip_mask.stip, sie_mask_sgeip_mask.utip) node sie_mask_lo_hi_hi = cat(sie_mask_sgeip_mask.mtip, sie_mask_sgeip_mask.vstip) node sie_mask_lo_hi = cat(sie_mask_lo_hi_hi, sie_mask_lo_hi_lo) node sie_mask_lo = cat(sie_mask_lo_hi, sie_mask_lo_lo) node sie_mask_hi_lo_lo = cat(sie_mask_sgeip_mask.seip, sie_mask_sgeip_mask.ueip) node sie_mask_hi_lo_hi = cat(sie_mask_sgeip_mask.meip, sie_mask_sgeip_mask.vseip) node sie_mask_hi_lo = cat(sie_mask_hi_lo_hi, sie_mask_hi_lo_lo) node sie_mask_hi_hi_lo = cat(sie_mask_sgeip_mask.rocc, sie_mask_sgeip_mask.sgeip) node sie_mask_hi_hi_hi_hi = cat(UInt<0>(0h0), sie_mask_sgeip_mask.zero1) node sie_mask_hi_hi_hi = cat(sie_mask_hi_hi_hi_hi, sie_mask_sgeip_mask.debug) node sie_mask_hi_hi = cat(sie_mask_hi_hi_hi, sie_mask_hi_hi_lo) node sie_mask_hi = cat(sie_mask_hi_hi, sie_mask_hi_lo) node _sie_mask_T = cat(sie_mask_hi, sie_mask_lo) node _sie_mask_T_1 = or(hs_delegable_interrupts, _sie_mask_T) node _sie_mask_T_2 = not(_sie_mask_T_1) node sie_mask = and(read_mideleg, _sie_mask_T_2) node read_sie = and(reg_mie, sie_mask) node read_sip = and(read_mip, sie_mask) wire _read_sstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect _read_sstatus_WIRE.uie, UInt<1>(0h0) connect _read_sstatus_WIRE.sie, UInt<1>(0h0) connect _read_sstatus_WIRE.hie, UInt<1>(0h0) connect _read_sstatus_WIRE.mie, UInt<1>(0h0) connect _read_sstatus_WIRE.upie, UInt<1>(0h0) connect _read_sstatus_WIRE.spie, UInt<1>(0h0) connect _read_sstatus_WIRE.ube, UInt<1>(0h0) connect _read_sstatus_WIRE.mpie, UInt<1>(0h0) connect _read_sstatus_WIRE.spp, UInt<1>(0h0) connect _read_sstatus_WIRE.vs, UInt<2>(0h0) connect _read_sstatus_WIRE.mpp, UInt<2>(0h0) connect _read_sstatus_WIRE.fs, UInt<2>(0h0) connect _read_sstatus_WIRE.xs, UInt<2>(0h0) connect _read_sstatus_WIRE.mprv, UInt<1>(0h0) connect _read_sstatus_WIRE.sum, UInt<1>(0h0) connect _read_sstatus_WIRE.mxr, UInt<1>(0h0) connect _read_sstatus_WIRE.tvm, UInt<1>(0h0) connect _read_sstatus_WIRE.tw, UInt<1>(0h0) connect _read_sstatus_WIRE.tsr, UInt<1>(0h0) connect _read_sstatus_WIRE.zero1, UInt<8>(0h0) connect _read_sstatus_WIRE.sd_rv32, UInt<1>(0h0) connect _read_sstatus_WIRE.uxl, UInt<2>(0h0) connect _read_sstatus_WIRE.sxl, UInt<2>(0h0) connect _read_sstatus_WIRE.sbe, UInt<1>(0h0) connect _read_sstatus_WIRE.mbe, UInt<1>(0h0) connect _read_sstatus_WIRE.gva, UInt<1>(0h0) connect _read_sstatus_WIRE.mpv, UInt<1>(0h0) connect _read_sstatus_WIRE.zero2, UInt<23>(0h0) connect _read_sstatus_WIRE.sd, UInt<1>(0h0) connect _read_sstatus_WIRE.v, UInt<1>(0h0) connect _read_sstatus_WIRE.prv, UInt<2>(0h0) connect _read_sstatus_WIRE.dv, UInt<1>(0h0) connect _read_sstatus_WIRE.dprv, UInt<2>(0h0) connect _read_sstatus_WIRE.isa, UInt<32>(0h0) connect _read_sstatus_WIRE.wfi, UInt<1>(0h0) connect _read_sstatus_WIRE.cease, UInt<1>(0h0) connect _read_sstatus_WIRE.debug, UInt<1>(0h0) wire read_sstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect read_sstatus, _read_sstatus_WIRE connect read_sstatus.sd, io.status.sd connect read_sstatus.uxl, io.status.uxl connect read_sstatus.sd_rv32, io.status.sd_rv32 connect read_sstatus.mxr, io.status.mxr connect read_sstatus.sum, io.status.sum connect read_sstatus.xs, io.status.xs connect read_sstatus.fs, io.status.fs connect read_sstatus.vs, io.status.vs connect read_sstatus.spp, io.status.spp connect read_sstatus.spie, io.status.spie connect read_sstatus.sie, io.status.sie node lo_lo_lo_lo = cat(read_sstatus.sie, read_sstatus.uie) node lo_lo_lo_hi = cat(read_sstatus.mie, read_sstatus.hie) node lo_lo_lo_4 = cat(lo_lo_lo_hi, lo_lo_lo_lo) node lo_lo_hi_lo = cat(read_sstatus.spie, read_sstatus.upie) node lo_lo_hi_hi_hi = cat(read_sstatus.spp, read_sstatus.mpie) node lo_lo_hi_hi = cat(lo_lo_hi_hi_hi, read_sstatus.ube) node lo_lo_hi_4 = cat(lo_lo_hi_hi, lo_lo_hi_lo) node lo_lo_5 = cat(lo_lo_hi_4, lo_lo_lo_4) node lo_hi_lo_lo = cat(read_sstatus.mpp, read_sstatus.vs) node lo_hi_lo_hi = cat(read_sstatus.xs, read_sstatus.fs) node lo_hi_lo_4 = cat(lo_hi_lo_hi, lo_hi_lo_lo) node lo_hi_hi_lo = cat(read_sstatus.sum, read_sstatus.mprv) node lo_hi_hi_hi_hi = cat(read_sstatus.tw, read_sstatus.tvm) node lo_hi_hi_hi = cat(lo_hi_hi_hi_hi, read_sstatus.mxr) node lo_hi_hi_4 = cat(lo_hi_hi_hi, lo_hi_hi_lo) node lo_hi_5 = cat(lo_hi_hi_4, lo_hi_lo_4) node lo_5 = cat(lo_hi_5, lo_lo_5) node hi_lo_lo_lo = cat(read_sstatus.zero1, read_sstatus.tsr) node hi_lo_lo_hi = cat(read_sstatus.uxl, read_sstatus.sd_rv32) node hi_lo_lo_4 = cat(hi_lo_lo_hi, hi_lo_lo_lo) node hi_lo_hi_lo = cat(read_sstatus.sbe, read_sstatus.sxl) node hi_lo_hi_hi_hi = cat(read_sstatus.mpv, read_sstatus.gva) node hi_lo_hi_hi = cat(hi_lo_hi_hi_hi, read_sstatus.mbe) node hi_lo_hi_4 = cat(hi_lo_hi_hi, hi_lo_hi_lo) node hi_lo_5 = cat(hi_lo_hi_4, hi_lo_lo_4) node hi_hi_lo_lo = cat(read_sstatus.sd, read_sstatus.zero2) node hi_hi_lo_hi_hi = cat(read_sstatus.dv, read_sstatus.prv) node hi_hi_lo_hi = cat(hi_hi_lo_hi_hi, read_sstatus.v) node hi_hi_lo_4 = cat(hi_hi_lo_hi, hi_hi_lo_lo) node hi_hi_hi_lo = cat(read_sstatus.isa, read_sstatus.dprv) node hi_hi_hi_hi_hi = cat(read_sstatus.debug, read_sstatus.cease) node hi_hi_hi_hi_4 = cat(hi_hi_hi_hi_hi, read_sstatus.wfi) node hi_hi_hi_4 = cat(hi_hi_hi_hi_4, hi_hi_hi_lo) node hi_hi_5 = cat(hi_hi_hi_4, hi_hi_lo_4) node hi_7 = cat(hi_hi_5, hi_lo_5) node _T_20 = cat(hi_7, lo_5) node _T_21 = bits(_T_20, 63, 0) node _T_22 = bits(reg_stval, 39, 39) node _T_23 = mux(_T_22, UInt<24>(0hffffff), UInt<24>(0h0)) node _T_24 = cat(_T_23, reg_stval) node hi_8 = cat(reg_satp.mode, reg_satp.asid) node _T_25 = cat(hi_8, reg_satp.ppn) node _T_26 = not(reg_sepc) node _T_27 = bits(reg_misa, 2, 2) node _T_28 = mux(_T_27, UInt<1>(0h1), UInt<2>(0h3)) node _T_29 = or(_T_26, _T_28) node _T_30 = not(_T_29) node _T_31 = bits(_T_30, 39, 39) node _T_32 = mux(_T_31, UInt<24>(0hffffff), UInt<24>(0h0)) node _T_33 = cat(_T_32, _T_30) node lo_lo_6 = cat(reg_senvcfg.zero3, reg_senvcfg.fiom) node lo_hi_6 = cat(reg_senvcfg.cbcfe, reg_senvcfg.cbie) node lo_6 = cat(lo_hi_6, lo_lo_6) node hi_lo_6 = cat(reg_senvcfg.zero54, reg_senvcfg.cbze) node hi_hi_6 = cat(reg_senvcfg.stce, reg_senvcfg.pbmte) node hi_9 = cat(hi_hi_6, hi_lo_6) node _T_34 = cat(hi_9, lo_6) wire read_pmp_15 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect read_pmp_15.mask, UInt<32>(0h0) connect read_pmp_15.addr, UInt<30>(0h0) connect read_pmp_15.cfg.r, UInt<1>(0h0) connect read_pmp_15.cfg.w, UInt<1>(0h0) connect read_pmp_15.cfg.x, UInt<1>(0h0) connect read_pmp_15.cfg.a, UInt<2>(0h0) connect read_pmp_15.cfg.res, UInt<2>(0h0) connect read_pmp_15.cfg.l, UInt<1>(0h0) node lo_hi_7 = cat(reg_pmp[0].cfg.x, reg_pmp[0].cfg.w) node lo_7 = cat(lo_hi_7, reg_pmp[0].cfg.r) node hi_hi_7 = cat(reg_pmp[0].cfg.l, reg_pmp[0].cfg.res) node hi_10 = cat(hi_hi_7, reg_pmp[0].cfg.a) node _T_35 = cat(hi_10, lo_7) node lo_hi_8 = cat(reg_pmp[1].cfg.x, reg_pmp[1].cfg.w) node lo_8 = cat(lo_hi_8, reg_pmp[1].cfg.r) node hi_hi_8 = cat(reg_pmp[1].cfg.l, reg_pmp[1].cfg.res) node hi_11 = cat(hi_hi_8, reg_pmp[1].cfg.a) node _T_36 = cat(hi_11, lo_8) node lo_hi_9 = cat(reg_pmp[2].cfg.x, reg_pmp[2].cfg.w) node lo_9 = cat(lo_hi_9, reg_pmp[2].cfg.r) node hi_hi_9 = cat(reg_pmp[2].cfg.l, reg_pmp[2].cfg.res) node hi_12 = cat(hi_hi_9, reg_pmp[2].cfg.a) node _T_37 = cat(hi_12, lo_9) node lo_hi_10 = cat(reg_pmp[3].cfg.x, reg_pmp[3].cfg.w) node lo_10 = cat(lo_hi_10, reg_pmp[3].cfg.r) node hi_hi_10 = cat(reg_pmp[3].cfg.l, reg_pmp[3].cfg.res) node hi_13 = cat(hi_hi_10, reg_pmp[3].cfg.a) node _T_38 = cat(hi_13, lo_10) node lo_hi_11 = cat(reg_pmp[4].cfg.x, reg_pmp[4].cfg.w) node lo_11 = cat(lo_hi_11, reg_pmp[4].cfg.r) node hi_hi_11 = cat(reg_pmp[4].cfg.l, reg_pmp[4].cfg.res) node hi_14 = cat(hi_hi_11, reg_pmp[4].cfg.a) node _T_39 = cat(hi_14, lo_11) node lo_hi_12 = cat(reg_pmp[5].cfg.x, reg_pmp[5].cfg.w) node lo_12 = cat(lo_hi_12, reg_pmp[5].cfg.r) node hi_hi_12 = cat(reg_pmp[5].cfg.l, reg_pmp[5].cfg.res) node hi_15 = cat(hi_hi_12, reg_pmp[5].cfg.a) node _T_40 = cat(hi_15, lo_12) node lo_hi_13 = cat(reg_pmp[6].cfg.x, reg_pmp[6].cfg.w) node lo_13 = cat(lo_hi_13, reg_pmp[6].cfg.r) node hi_hi_13 = cat(reg_pmp[6].cfg.l, reg_pmp[6].cfg.res) node hi_16 = cat(hi_hi_13, reg_pmp[6].cfg.a) node _T_41 = cat(hi_16, lo_13) node lo_hi_14 = cat(reg_pmp[7].cfg.x, reg_pmp[7].cfg.w) node lo_14 = cat(lo_hi_14, reg_pmp[7].cfg.r) node hi_hi_14 = cat(reg_pmp[7].cfg.l, reg_pmp[7].cfg.res) node hi_17 = cat(hi_hi_14, reg_pmp[7].cfg.a) node _T_42 = cat(hi_17, lo_14) node lo_lo_7 = cat(_T_36, _T_35) node lo_hi_15 = cat(_T_38, _T_37) node lo_15 = cat(lo_hi_15, lo_lo_7) node hi_lo_7 = cat(_T_40, _T_39) node hi_hi_15 = cat(_T_42, _T_41) node hi_18 = cat(hi_hi_15, hi_lo_7) node _T_43 = cat(hi_18, lo_15) node lo_hi_16 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_16 = cat(lo_hi_16, read_pmp_15.cfg.r) node hi_hi_16 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_19 = cat(hi_hi_16, read_pmp_15.cfg.a) node _T_44 = cat(hi_19, lo_16) node lo_hi_17 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_17 = cat(lo_hi_17, read_pmp_15.cfg.r) node hi_hi_17 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_20 = cat(hi_hi_17, read_pmp_15.cfg.a) node _T_45 = cat(hi_20, lo_17) node lo_hi_18 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_18 = cat(lo_hi_18, read_pmp_15.cfg.r) node hi_hi_18 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_21 = cat(hi_hi_18, read_pmp_15.cfg.a) node _T_46 = cat(hi_21, lo_18) node lo_hi_19 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_19 = cat(lo_hi_19, read_pmp_15.cfg.r) node hi_hi_19 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_22 = cat(hi_hi_19, read_pmp_15.cfg.a) node _T_47 = cat(hi_22, lo_19) node lo_hi_20 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_20 = cat(lo_hi_20, read_pmp_15.cfg.r) node hi_hi_20 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_23 = cat(hi_hi_20, read_pmp_15.cfg.a) node _T_48 = cat(hi_23, lo_20) node lo_hi_21 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_21 = cat(lo_hi_21, read_pmp_15.cfg.r) node hi_hi_21 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_24 = cat(hi_hi_21, read_pmp_15.cfg.a) node _T_49 = cat(hi_24, lo_21) node lo_hi_22 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_22 = cat(lo_hi_22, read_pmp_15.cfg.r) node hi_hi_22 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_25 = cat(hi_hi_22, read_pmp_15.cfg.a) node _T_50 = cat(hi_25, lo_22) node lo_hi_23 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_23 = cat(lo_hi_23, read_pmp_15.cfg.r) node hi_hi_23 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_26 = cat(hi_hi_23, read_pmp_15.cfg.a) node _T_51 = cat(hi_26, lo_23) node lo_lo_8 = cat(_T_45, _T_44) node lo_hi_24 = cat(_T_47, _T_46) node lo_24 = cat(lo_hi_24, lo_lo_8) node hi_lo_8 = cat(_T_49, _T_48) node hi_hi_24 = cat(_T_51, _T_50) node hi_27 = cat(hi_hi_24, hi_lo_8) node _T_52 = cat(hi_27, lo_24) regreset reg_custom_0 : UInt<64>, clock, reset, UInt<64>(0h208) node _reg_custom_read_T = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_1 = eq(io.rw.addr, UInt<11>(0h7c1)) node reg_custom_read = and(_reg_custom_read_T, _reg_custom_read_T_1) connect io.customCSRs[0].ren, reg_custom_read node _reg_custom_T = and(reg_custom_read, io.customCSRs[0].stall) when _reg_custom_T : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_1 : UInt<64>, clock, reset, UInt<64>(0h1) node _reg_custom_read_T_2 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_3 = eq(io.rw.addr, UInt<12>(0hf12)) node reg_custom_read_1 = and(_reg_custom_read_T_2, _reg_custom_read_T_3) connect io.customCSRs[1].ren, reg_custom_read_1 node _reg_custom_T_1 = and(reg_custom_read_1, io.customCSRs[1].stall) when _reg_custom_T_1 : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _reg_custom_read_T_4 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_5 = eq(io.rw.addr, UInt<12>(0hf11)) node reg_custom_read_2 = and(_reg_custom_read_T_4, _reg_custom_read_T_5) connect io.customCSRs[2].ren, reg_custom_read_2 node _reg_custom_T_2 = and(reg_custom_read_2, io.customCSRs[2].stall) when _reg_custom_T_2 : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_3 : UInt<64>, clock, reset, UInt<64>(0h20181004) node _reg_custom_read_T_6 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_7 = eq(io.rw.addr, UInt<12>(0hf13)) node reg_custom_read_3 = and(_reg_custom_read_T_6, _reg_custom_read_T_7) connect io.customCSRs[3].ren, reg_custom_read_3 node _reg_custom_T_3 = and(reg_custom_read_3, io.customCSRs[3].stall) when _reg_custom_T_3 : connect io.rw_stall, UInt<1>(0h1) node decoded_addr_addr = cat(io.status.v, io.rw.addr) wire decoded_addr_decoded_decoded_plaInput : UInt<12> node decoded_addr_decoded_decoded_invInputs = not(decoded_addr_decoded_decoded_plaInput) wire decoded_addr_decoded_decoded : UInt<150> node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo) node _decoded_addr_decoded_decoded_andMatrixOutputs_T = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo) node decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1) node decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2) node decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3) node decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4) node decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5) node decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6) node decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7) node decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8) node decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9) node decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10) node decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11) node decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_11) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12) node decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_12) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13) node decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_13) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14) node decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_14) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15) node decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_15) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16) node decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_16) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17) node decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_17) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18) node decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_18) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19) node decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_19) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20) node decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_20) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21) node decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_21) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22) node decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_22) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23) node decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_23) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24) node decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_24) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25) node decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_25) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26) node decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_26) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27) node decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_27) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28) node decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_28) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29) node decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_29) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30) node decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_30) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31) node decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_31) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32) node decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_32) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33) node decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_33) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34) node decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_34) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35) node decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_35) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36) node decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_36) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37) node decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_37) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38) node decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_38) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39) node decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_39) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40) node decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_40) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41) node decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_41) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42) node decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_42) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43) node decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_43) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44) node decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_44) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45) node decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_45) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46) node decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_46) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47) node decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_47) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48) node decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_48) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49) node decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_49) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50) node decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_50) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51) node decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_51) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52) node decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_52) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53) node decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_53) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54) node decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_54) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55) node decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_55) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56) node decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_56) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57) node decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_57) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58) node decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_58) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59) node decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_59) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60) node decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_60) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61) node decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_61) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62) node decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_62) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63) node decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_63) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64) node decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_64) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65) node decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_65) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66) node decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_66) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67) node decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_67) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68) node decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_68) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69) node decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_69) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70) node decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_70) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71) node decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_71) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72) node decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_72) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73) node decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_73) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74) node decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_74) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75) node decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_75) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76) node decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_76) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77) node decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_77) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78) node decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_78) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79) node decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_79) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80) node decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_80) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81) node decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_81) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82) node decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_82) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83) node decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_83) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84) node decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_84) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85) node decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_85) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86) node decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_86) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87) node decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_87) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88) node decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_88) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89) node decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_89) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90) node decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_90) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91) node decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_91) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92) node decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_92) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93) node decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_93) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94) node decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_94) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95) node decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_95) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96) node decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_96) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97) node decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_97) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98) node decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_98) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99) node decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_99) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100) node decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_100) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101) node decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_101) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102) node decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_102) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103) node decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_103) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104) node decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_104) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105) node decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_105) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106) node decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_106) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107) node decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_107) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108) node decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_108) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109) node decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_109) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110) node decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_110) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111) node decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_111) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112) node decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_112) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113) node decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_113) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114) node decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_114) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115) node decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_115) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116) node decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_116) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117) node decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_117) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118) node decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_118) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119) node decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_119) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120) node decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_120) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121) node decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_121) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122) node decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_122) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123) node decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_123) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124) node decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_124) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125) node decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_125) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126) node decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_126) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127) node decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_127) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128) node decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_128) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129) node decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_129) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130) node decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_130) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131) node decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_131) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132) node decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_132) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133) node decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_133) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134) node decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_134) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135) node decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_135) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136) node decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_136) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137) node decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_137) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138) node decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_138) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139) node decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_139) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140) node decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_140) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141) node decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_141) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142) node decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_142) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143) node decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_143) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144) node decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_144) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145) node decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_145) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146) node decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_146) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147) node decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_147) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148) node decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_148) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149) node decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_149) node _decoded_addr_decoded_decoded_orMatrixOutputs_T = orr(decoded_addr_decoded_decoded_andMatrixOutputs_75_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_13_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_101_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_38_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_12_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_149_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_113_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_98_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_145_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_42_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_72_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_137_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_93_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_111_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_100_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_85_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_57_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_88_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_18_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_45_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_10_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_48_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_67_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_0_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_82_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_28_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_27_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_123_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_59_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_74_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_116_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_24_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_92_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_89_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_121_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_1_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_40_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_52_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_49_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_84_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_110_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_126_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_144_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_78_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_54_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_32_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_70_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_96_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_39_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_43_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_60_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_63_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_51_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_97_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_33_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_15_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_90_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_36_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_46_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_14_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_65_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_117_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_131_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_94_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_125_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_143_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_22_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_99_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_16_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_142_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_103_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_29_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_133_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_69_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_4_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_87_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_148_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_102_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_17_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_108_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_130_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_129_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_112_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_71_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_83_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_19_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_5_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_61_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_64_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_115_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_8_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_25_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_9_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_86_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_37_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_132_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_139_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_135_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_58_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_120_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_53_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_62_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_118_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_73_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_31_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_11_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_35_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_44_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_141_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_127_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_140_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_47_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_30_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_77_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_7_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_21_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_147_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_109_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_6_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_124_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_105_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_107_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_26_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_55_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_20_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_95_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_136_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_79_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_76_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_34_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_41_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_134_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_138_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_23_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_50_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_3_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_81_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_80_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_122_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_106_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_66_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_91_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_119_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_68_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_114_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_104_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_56_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_128_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_146_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_2_2) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_12, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_31, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_45, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_50, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_71, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_72) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_92, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_120, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo) node _decoded_addr_decoded_decoded_invMatrixOutputs_T = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 0, 0) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 1, 1) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 2, 2) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 3, 3) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 4, 4) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 5, 5) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 6, 6) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 7, 7) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 8, 8) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 9, 9) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 10, 10) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 11, 11) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 12, 12) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 13, 13) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 14, 14) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 15, 15) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 16, 16) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 17, 17) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 18, 18) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 19, 19) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 20, 20) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 21, 21) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 22, 22) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 23, 23) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 24, 24) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 25, 25) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 26, 26) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 27, 27) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 28, 28) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 29, 29) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 30, 30) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 31, 31) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 32, 32) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 33, 33) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 34, 34) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 35, 35) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 36, 36) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 37, 37) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 38, 38) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 39, 39) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 40, 40) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 41, 41) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 42, 42) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 43, 43) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 44, 44) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 45, 45) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 46, 46) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 47, 47) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 48, 48) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 49, 49) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 50, 50) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 51, 51) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 52, 52) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 53, 53) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 54, 54) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 55, 55) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 56, 56) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 57, 57) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 58, 58) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 59, 59) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 60, 60) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 61, 61) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 62, 62) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 63, 63) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 64, 64) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 65, 65) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 66, 66) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 67, 67) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 68, 68) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 69, 69) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 70, 70) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 71, 71) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 72, 72) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 73, 73) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 74, 74) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 75, 75) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 76, 76) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 77, 77) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 78, 78) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 79, 79) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 80, 80) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 81, 81) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 82, 82) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 83, 83) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 84, 84) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 85, 85) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 86, 86) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 87, 87) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 88, 88) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 89, 89) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 90, 90) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 91, 91) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 92, 92) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 93, 93) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 94, 94) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 95, 95) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 96, 96) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 97, 97) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 98, 98) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 99, 99) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 100, 100) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 101, 101) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 102, 102) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 103, 103) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 104, 104) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 105, 105) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 106, 106) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 107, 107) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 108, 108) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 109, 109) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 110, 110) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 111, 111) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 112, 112) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 113, 113) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 114, 114) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 115, 115) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 116, 116) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 117, 117) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 118, 118) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 119, 119) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 120, 120) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 121, 121) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 122, 122) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 123, 123) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 124, 124) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 125, 125) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 126, 126) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 127, 127) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 128, 128) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 129, 129) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 130, 130) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 131, 131) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 132, 132) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 133, 133) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 134, 134) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 135, 135) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 136, 136) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 137, 137) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 138, 138) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 139, 139) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 140, 140) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 141, 141) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 142, 142) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 143, 143) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 144, 144) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 145, 145) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 146, 146) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 147, 147) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 148, 148) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 149, 149) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_12, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_31, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_45, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_50, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_71, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_72) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_92, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_120, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo) connect decoded_addr_decoded_decoded, decoded_addr_decoded_decoded_invMatrixOutputs connect decoded_addr_decoded_decoded_plaInput, decoded_addr_addr node decoded_addr_decoded_0 = bits(decoded_addr_decoded_decoded, 149, 149) node decoded_addr_decoded_1 = bits(decoded_addr_decoded_decoded, 148, 148) node decoded_addr_decoded_2 = bits(decoded_addr_decoded_decoded, 147, 147) node decoded_addr_decoded_3 = bits(decoded_addr_decoded_decoded, 146, 146) node decoded_addr_decoded_4 = bits(decoded_addr_decoded_decoded, 145, 145) node decoded_addr_decoded_5 = bits(decoded_addr_decoded_decoded, 144, 144) node decoded_addr_decoded_6 = bits(decoded_addr_decoded_decoded, 143, 143) node decoded_addr_decoded_7 = bits(decoded_addr_decoded_decoded, 142, 142) node decoded_addr_decoded_8 = bits(decoded_addr_decoded_decoded, 141, 141) node decoded_addr_decoded_9 = bits(decoded_addr_decoded_decoded, 140, 140) node decoded_addr_decoded_10 = bits(decoded_addr_decoded_decoded, 139, 139) node decoded_addr_decoded_11 = bits(decoded_addr_decoded_decoded, 138, 138) node decoded_addr_decoded_12 = bits(decoded_addr_decoded_decoded, 137, 137) node decoded_addr_decoded_13 = bits(decoded_addr_decoded_decoded, 136, 136) node decoded_addr_decoded_14 = bits(decoded_addr_decoded_decoded, 135, 135) node decoded_addr_decoded_15 = bits(decoded_addr_decoded_decoded, 134, 134) node decoded_addr_decoded_16 = bits(decoded_addr_decoded_decoded, 133, 133) node decoded_addr_decoded_17 = bits(decoded_addr_decoded_decoded, 132, 132) node decoded_addr_decoded_18 = bits(decoded_addr_decoded_decoded, 131, 131) node decoded_addr_decoded_19 = bits(decoded_addr_decoded_decoded, 130, 130) node decoded_addr_decoded_20 = bits(decoded_addr_decoded_decoded, 129, 129) node decoded_addr_decoded_21 = bits(decoded_addr_decoded_decoded, 128, 128) node decoded_addr_decoded_22 = bits(decoded_addr_decoded_decoded, 127, 127) node decoded_addr_decoded_23 = bits(decoded_addr_decoded_decoded, 126, 126) node decoded_addr_decoded_24 = bits(decoded_addr_decoded_decoded, 125, 125) node decoded_addr_decoded_25 = bits(decoded_addr_decoded_decoded, 124, 124) node decoded_addr_decoded_26 = bits(decoded_addr_decoded_decoded, 123, 123) node decoded_addr_decoded_27 = bits(decoded_addr_decoded_decoded, 122, 122) node decoded_addr_decoded_28 = bits(decoded_addr_decoded_decoded, 121, 121) node decoded_addr_decoded_29 = bits(decoded_addr_decoded_decoded, 120, 120) node decoded_addr_decoded_30 = bits(decoded_addr_decoded_decoded, 119, 119) node decoded_addr_decoded_31 = bits(decoded_addr_decoded_decoded, 118, 118) node decoded_addr_decoded_32 = bits(decoded_addr_decoded_decoded, 117, 117) node decoded_addr_decoded_33 = bits(decoded_addr_decoded_decoded, 116, 116) node decoded_addr_decoded_34 = bits(decoded_addr_decoded_decoded, 115, 115) node decoded_addr_decoded_35 = bits(decoded_addr_decoded_decoded, 114, 114) node decoded_addr_decoded_36 = bits(decoded_addr_decoded_decoded, 113, 113) node decoded_addr_decoded_37 = bits(decoded_addr_decoded_decoded, 112, 112) node decoded_addr_decoded_38 = bits(decoded_addr_decoded_decoded, 111, 111) node decoded_addr_decoded_39 = bits(decoded_addr_decoded_decoded, 110, 110) node decoded_addr_decoded_40 = bits(decoded_addr_decoded_decoded, 109, 109) node decoded_addr_decoded_41 = bits(decoded_addr_decoded_decoded, 108, 108) node decoded_addr_decoded_42 = bits(decoded_addr_decoded_decoded, 107, 107) node decoded_addr_decoded_43 = bits(decoded_addr_decoded_decoded, 106, 106) node decoded_addr_decoded_44 = bits(decoded_addr_decoded_decoded, 105, 105) node decoded_addr_decoded_45 = bits(decoded_addr_decoded_decoded, 104, 104) node decoded_addr_decoded_46 = bits(decoded_addr_decoded_decoded, 103, 103) node decoded_addr_decoded_47 = bits(decoded_addr_decoded_decoded, 102, 102) node decoded_addr_decoded_48 = bits(decoded_addr_decoded_decoded, 101, 101) node decoded_addr_decoded_49 = bits(decoded_addr_decoded_decoded, 100, 100) node decoded_addr_decoded_50 = bits(decoded_addr_decoded_decoded, 99, 99) node decoded_addr_decoded_51 = bits(decoded_addr_decoded_decoded, 98, 98) node decoded_addr_decoded_52 = bits(decoded_addr_decoded_decoded, 97, 97) node decoded_addr_decoded_53 = bits(decoded_addr_decoded_decoded, 96, 96) node decoded_addr_decoded_54 = bits(decoded_addr_decoded_decoded, 95, 95) node decoded_addr_decoded_55 = bits(decoded_addr_decoded_decoded, 94, 94) node decoded_addr_decoded_56 = bits(decoded_addr_decoded_decoded, 93, 93) node decoded_addr_decoded_57 = bits(decoded_addr_decoded_decoded, 92, 92) node decoded_addr_decoded_58 = bits(decoded_addr_decoded_decoded, 91, 91) node decoded_addr_decoded_59 = bits(decoded_addr_decoded_decoded, 90, 90) node decoded_addr_decoded_60 = bits(decoded_addr_decoded_decoded, 89, 89) node decoded_addr_decoded_61 = bits(decoded_addr_decoded_decoded, 88, 88) node decoded_addr_decoded_62 = bits(decoded_addr_decoded_decoded, 87, 87) node decoded_addr_decoded_63 = bits(decoded_addr_decoded_decoded, 86, 86) node decoded_addr_decoded_64 = bits(decoded_addr_decoded_decoded, 85, 85) node decoded_addr_decoded_65 = bits(decoded_addr_decoded_decoded, 84, 84) node decoded_addr_decoded_66 = bits(decoded_addr_decoded_decoded, 83, 83) node decoded_addr_decoded_67 = bits(decoded_addr_decoded_decoded, 82, 82) node decoded_addr_decoded_68 = bits(decoded_addr_decoded_decoded, 81, 81) node decoded_addr_decoded_69 = bits(decoded_addr_decoded_decoded, 80, 80) node decoded_addr_decoded_70 = bits(decoded_addr_decoded_decoded, 79, 79) node decoded_addr_decoded_71 = bits(decoded_addr_decoded_decoded, 78, 78) node decoded_addr_decoded_72 = bits(decoded_addr_decoded_decoded, 77, 77) node decoded_addr_decoded_73 = bits(decoded_addr_decoded_decoded, 76, 76) node decoded_addr_decoded_74 = bits(decoded_addr_decoded_decoded, 75, 75) node decoded_addr_decoded_75 = bits(decoded_addr_decoded_decoded, 74, 74) node decoded_addr_decoded_76 = bits(decoded_addr_decoded_decoded, 73, 73) node decoded_addr_decoded_77 = bits(decoded_addr_decoded_decoded, 72, 72) node decoded_addr_decoded_78 = bits(decoded_addr_decoded_decoded, 71, 71) node decoded_addr_decoded_79 = bits(decoded_addr_decoded_decoded, 70, 70) node decoded_addr_decoded_80 = bits(decoded_addr_decoded_decoded, 69, 69) node decoded_addr_decoded_81 = bits(decoded_addr_decoded_decoded, 68, 68) node decoded_addr_decoded_82 = bits(decoded_addr_decoded_decoded, 67, 67) node decoded_addr_decoded_83 = bits(decoded_addr_decoded_decoded, 66, 66) node decoded_addr_decoded_84 = bits(decoded_addr_decoded_decoded, 65, 65) node decoded_addr_decoded_85 = bits(decoded_addr_decoded_decoded, 64, 64) node decoded_addr_decoded_86 = bits(decoded_addr_decoded_decoded, 63, 63) node decoded_addr_decoded_87 = bits(decoded_addr_decoded_decoded, 62, 62) node decoded_addr_decoded_88 = bits(decoded_addr_decoded_decoded, 61, 61) node decoded_addr_decoded_89 = bits(decoded_addr_decoded_decoded, 60, 60) node decoded_addr_decoded_90 = bits(decoded_addr_decoded_decoded, 59, 59) node decoded_addr_decoded_91 = bits(decoded_addr_decoded_decoded, 58, 58) node decoded_addr_decoded_92 = bits(decoded_addr_decoded_decoded, 57, 57) node decoded_addr_decoded_93 = bits(decoded_addr_decoded_decoded, 56, 56) node decoded_addr_decoded_94 = bits(decoded_addr_decoded_decoded, 55, 55) node decoded_addr_decoded_95 = bits(decoded_addr_decoded_decoded, 54, 54) node decoded_addr_decoded_96 = bits(decoded_addr_decoded_decoded, 53, 53) node decoded_addr_decoded_97 = bits(decoded_addr_decoded_decoded, 52, 52) node decoded_addr_decoded_98 = bits(decoded_addr_decoded_decoded, 51, 51) node decoded_addr_decoded_99 = bits(decoded_addr_decoded_decoded, 50, 50) node decoded_addr_decoded_100 = bits(decoded_addr_decoded_decoded, 49, 49) node decoded_addr_decoded_101 = bits(decoded_addr_decoded_decoded, 48, 48) node decoded_addr_decoded_102 = bits(decoded_addr_decoded_decoded, 47, 47) node decoded_addr_decoded_103 = bits(decoded_addr_decoded_decoded, 46, 46) node decoded_addr_decoded_104 = bits(decoded_addr_decoded_decoded, 45, 45) node decoded_addr_decoded_105 = bits(decoded_addr_decoded_decoded, 44, 44) node decoded_addr_decoded_106 = bits(decoded_addr_decoded_decoded, 43, 43) node decoded_addr_decoded_107 = bits(decoded_addr_decoded_decoded, 42, 42) node decoded_addr_decoded_108 = bits(decoded_addr_decoded_decoded, 41, 41) node decoded_addr_decoded_109 = bits(decoded_addr_decoded_decoded, 40, 40) node decoded_addr_decoded_110 = bits(decoded_addr_decoded_decoded, 39, 39) node decoded_addr_decoded_111 = bits(decoded_addr_decoded_decoded, 38, 38) node decoded_addr_decoded_112 = bits(decoded_addr_decoded_decoded, 37, 37) node decoded_addr_decoded_113 = bits(decoded_addr_decoded_decoded, 36, 36) node decoded_addr_decoded_114 = bits(decoded_addr_decoded_decoded, 35, 35) node decoded_addr_decoded_115 = bits(decoded_addr_decoded_decoded, 34, 34) node decoded_addr_decoded_116 = bits(decoded_addr_decoded_decoded, 33, 33) node decoded_addr_decoded_117 = bits(decoded_addr_decoded_decoded, 32, 32) node decoded_addr_decoded_118 = bits(decoded_addr_decoded_decoded, 31, 31) node decoded_addr_decoded_119 = bits(decoded_addr_decoded_decoded, 30, 30) node decoded_addr_decoded_120 = bits(decoded_addr_decoded_decoded, 29, 29) node decoded_addr_decoded_121 = bits(decoded_addr_decoded_decoded, 28, 28) node decoded_addr_decoded_122 = bits(decoded_addr_decoded_decoded, 27, 27) node decoded_addr_decoded_123 = bits(decoded_addr_decoded_decoded, 26, 26) node decoded_addr_decoded_124 = bits(decoded_addr_decoded_decoded, 25, 25) node decoded_addr_decoded_125 = bits(decoded_addr_decoded_decoded, 24, 24) node decoded_addr_decoded_126 = bits(decoded_addr_decoded_decoded, 23, 23) node decoded_addr_decoded_127 = bits(decoded_addr_decoded_decoded, 22, 22) node decoded_addr_decoded_128 = bits(decoded_addr_decoded_decoded, 21, 21) node decoded_addr_decoded_129 = bits(decoded_addr_decoded_decoded, 20, 20) node decoded_addr_decoded_130 = bits(decoded_addr_decoded_decoded, 19, 19) node decoded_addr_decoded_131 = bits(decoded_addr_decoded_decoded, 18, 18) node decoded_addr_decoded_132 = bits(decoded_addr_decoded_decoded, 17, 17) node decoded_addr_decoded_133 = bits(decoded_addr_decoded_decoded, 16, 16) node decoded_addr_decoded_134 = bits(decoded_addr_decoded_decoded, 15, 15) node decoded_addr_decoded_135 = bits(decoded_addr_decoded_decoded, 14, 14) node decoded_addr_decoded_136 = bits(decoded_addr_decoded_decoded, 13, 13) node decoded_addr_decoded_137 = bits(decoded_addr_decoded_decoded, 12, 12) node decoded_addr_decoded_138 = bits(decoded_addr_decoded_decoded, 11, 11) node decoded_addr_decoded_139 = bits(decoded_addr_decoded_decoded, 10, 10) node decoded_addr_decoded_140 = bits(decoded_addr_decoded_decoded, 9, 9) node decoded_addr_decoded_141 = bits(decoded_addr_decoded_decoded, 8, 8) node decoded_addr_decoded_142 = bits(decoded_addr_decoded_decoded, 7, 7) node decoded_addr_decoded_143 = bits(decoded_addr_decoded_decoded, 6, 6) node decoded_addr_decoded_144 = bits(decoded_addr_decoded_decoded, 5, 5) node decoded_addr_decoded_145 = bits(decoded_addr_decoded_decoded, 4, 4) node decoded_addr_decoded_146 = bits(decoded_addr_decoded_decoded, 3, 3) node decoded_addr_decoded_147 = bits(decoded_addr_decoded_decoded, 2, 2) node decoded_addr_decoded_148 = bits(decoded_addr_decoded_decoded, 1, 1) node decoded_addr_decoded_149 = bits(decoded_addr_decoded_decoded, 0, 0) node decoded_addr_97_2 = bits(decoded_addr_decoded_0, 0, 0) node decoded_addr_55_2 = bits(decoded_addr_decoded_1, 0, 0) node decoded_addr_10_2 = bits(decoded_addr_decoded_2, 0, 0) node decoded_addr_118_2 = bits(decoded_addr_decoded_3, 0, 0) node decoded_addr_94_2 = bits(decoded_addr_decoded_4, 0, 0) node decoded_addr_100_2 = bits(decoded_addr_decoded_5, 0, 0) node decoded_addr_72_2 = bits(decoded_addr_decoded_6, 0, 0) node decoded_addr_108_2 = bits(decoded_addr_decoded_7, 0, 0) node decoded_addr_76_2 = bits(decoded_addr_decoded_8, 0, 0) node decoded_addr_129_2 = bits(decoded_addr_decoded_9, 0, 0) node decoded_addr_132_2 = bits(decoded_addr_decoded_10, 0, 0) node decoded_addr_136_2 = bits(decoded_addr_decoded_11, 0, 0) node decoded_addr_29_2 = bits(decoded_addr_decoded_12, 0, 0) node decoded_addr_131_2 = bits(decoded_addr_decoded_13, 0, 0) node decoded_addr_49_2 = bits(decoded_addr_decoded_14, 0, 0) node decoded_addr_89_2 = bits(decoded_addr_decoded_15, 0, 0) node decoded_addr_57_2 = bits(decoded_addr_decoded_16, 0, 0) node decoded_addr_36_2 = bits(decoded_addr_decoded_17, 0, 0) node decoded_addr_68_2 = bits(decoded_addr_decoded_18, 0, 0) node decoded_addr_99_2 = bits(decoded_addr_decoded_19, 0, 0) node decoded_addr_130_2 = bits(decoded_addr_decoded_20, 0, 0) node decoded_addr_103_2 = bits(decoded_addr_decoded_21, 0, 0) node decoded_addr_121_2 = bits(decoded_addr_decoded_22, 0, 0) node decoded_addr_146_2 = bits(decoded_addr_decoded_23, 0, 0) node decoded_addr_17_2 = bits(decoded_addr_decoded_24, 0, 0) node decoded_addr_27_2 = bits(decoded_addr_decoded_25, 0, 0) node decoded_addr_83_2 = bits(decoded_addr_decoded_26, 0, 0) node decoded_addr_52_2 = bits(decoded_addr_decoded_27, 0, 0) node decoded_addr_144_2 = bits(decoded_addr_decoded_28, 0, 0) node decoded_addr_70_2 = bits(decoded_addr_decoded_29, 0, 0) node decoded_addr_111_2 = bits(decoded_addr_decoded_30, 0, 0) node decoded_addr_82_2 = bits(decoded_addr_decoded_31, 0, 0) node decoded_addr_31_2 = bits(decoded_addr_decoded_32, 0, 0) node decoded_addr_0_2 = bits(decoded_addr_decoded_33, 0, 0) node decoded_addr_59_2 = bits(decoded_addr_decoded_34, 0, 0) node decoded_addr_138_2 = bits(decoded_addr_decoded_35, 0, 0) node decoded_addr_126_2 = bits(decoded_addr_decoded_36, 0, 0) node decoded_addr_74_2 = bits(decoded_addr_decoded_37, 0, 0) node decoded_addr_116_2 = bits(decoded_addr_decoded_38, 0, 0) node decoded_addr_90_2 = bits(decoded_addr_decoded_39, 0, 0) node decoded_addr_113_2 = bits(decoded_addr_decoded_40, 0, 0) node decoded_addr_1_2 = bits(decoded_addr_decoded_41, 0, 0) node decoded_addr_16_2 = bits(decoded_addr_decoded_42, 0, 0) node decoded_addr_78_2 = bits(decoded_addr_decoded_43, 0, 0) node decoded_addr_39_2 = bits(decoded_addr_decoded_44, 0, 0) node decoded_addr_51_2 = bits(decoded_addr_decoded_45, 0, 0) node decoded_addr_109_2 = bits(decoded_addr_decoded_46, 0, 0) node decoded_addr_91_2 = bits(decoded_addr_decoded_47, 0, 0) node decoded_addr_81_2 = bits(decoded_addr_decoded_48, 0, 0) node decoded_addr_67_2 = bits(decoded_addr_decoded_49, 0, 0) node decoded_addr_105_2 = bits(decoded_addr_decoded_50, 0, 0) node decoded_addr_122_2 = bits(decoded_addr_decoded_51, 0, 0) node decoded_addr_24_2 = bits(decoded_addr_decoded_52, 0, 0) node decoded_addr_124_2 = bits(decoded_addr_decoded_53, 0, 0) node decoded_addr_26_2 = bits(decoded_addr_decoded_54, 0, 0) node decoded_addr_128_2 = bits(decoded_addr_decoded_55, 0, 0) node decoded_addr_7_2 = bits(decoded_addr_decoded_56, 0, 0) node decoded_addr_62_2 = bits(decoded_addr_decoded_57, 0, 0) node decoded_addr_77_2 = bits(decoded_addr_decoded_58, 0, 0) node decoded_addr_46_2 = bits(decoded_addr_decoded_59, 0, 0) node decoded_addr_112_2 = bits(decoded_addr_decoded_60, 0, 0) node decoded_addr_60_2 = bits(decoded_addr_decoded_61, 0, 0) node decoded_addr_92_2 = bits(decoded_addr_decoded_62, 0, 0) node decoded_addr_148_2 = bits(decoded_addr_decoded_63, 0, 0) node decoded_addr_14_2 = bits(decoded_addr_decoded_64, 0, 0) node decoded_addr_21_2 = bits(decoded_addr_decoded_65, 0, 0) node decoded_addr_33_2 = bits(decoded_addr_decoded_66, 0, 0) node decoded_addr_19_2 = bits(decoded_addr_decoded_67, 0, 0) node decoded_addr_133_2 = bits(decoded_addr_decoded_68, 0, 0) node decoded_addr_149_2 = bits(decoded_addr_decoded_69, 0, 0) node decoded_addr_50_2 = bits(decoded_addr_decoded_70, 0, 0) node decoded_addr_75_2 = bits(decoded_addr_decoded_71, 0, 0) node decoded_addr_102_2 = bits(decoded_addr_decoded_72, 0, 0) node decoded_addr_84_2 = bits(decoded_addr_decoded_73, 0, 0) node decoded_addr_45_2 = bits(decoded_addr_decoded_74, 0, 0) node decoded_addr_64_2 = bits(decoded_addr_decoded_75, 0, 0) node decoded_addr_120_2 = bits(decoded_addr_decoded_76, 0, 0) node decoded_addr_30_2 = bits(decoded_addr_decoded_77, 0, 0) node decoded_addr_5_2 = bits(decoded_addr_decoded_78, 0, 0) node decoded_addr_32_2 = bits(decoded_addr_decoded_79, 0, 0) node decoded_addr_143_2 = bits(decoded_addr_decoded_80, 0, 0) node decoded_addr_117_2 = bits(decoded_addr_decoded_81, 0, 0) node decoded_addr_63_2 = bits(decoded_addr_decoded_82, 0, 0) node decoded_addr_107_2 = bits(decoded_addr_decoded_83, 0, 0) node decoded_addr_88_2 = bits(decoded_addr_decoded_84, 0, 0) node decoded_addr_114_2 = bits(decoded_addr_decoded_85, 0, 0) node decoded_addr_73_2 = bits(decoded_addr_decoded_86, 0, 0) node decoded_addr_53_2 = bits(decoded_addr_decoded_87, 0, 0) node decoded_addr_147_2 = bits(decoded_addr_decoded_88, 0, 0) node decoded_addr_41_2 = bits(decoded_addr_decoded_89, 0, 0) node decoded_addr_56_2 = bits(decoded_addr_decoded_90, 0, 0) node decoded_addr_37_2 = bits(decoded_addr_decoded_91, 0, 0) node decoded_addr_79_2 = bits(decoded_addr_decoded_92, 0, 0) node decoded_addr_96_2 = bits(decoded_addr_decoded_93, 0, 0) node decoded_addr_4_2 = bits(decoded_addr_decoded_94, 0, 0) node decoded_addr_101_2 = bits(decoded_addr_decoded_95, 0, 0) node decoded_addr_119_2 = bits(decoded_addr_decoded_96, 0, 0) node decoded_addr_22_2 = bits(decoded_addr_decoded_97, 0, 0) node decoded_addr_139_2 = bits(decoded_addr_decoded_98, 0, 0) node decoded_addr_11_2 = bits(decoded_addr_decoded_99, 0, 0) node decoded_addr_134_2 = bits(decoded_addr_decoded_100, 0, 0) node decoded_addr_12_2 = bits(decoded_addr_decoded_101, 0, 0) node decoded_addr_65_2 = bits(decoded_addr_decoded_102, 0, 0) node decoded_addr_86_2 = bits(decoded_addr_decoded_103, 0, 0) node decoded_addr_47_2 = bits(decoded_addr_decoded_104, 0, 0) node decoded_addr_106_2 = bits(decoded_addr_decoded_105, 0, 0) node decoded_addr_58_2 = bits(decoded_addr_decoded_106, 0, 0) node decoded_addr_87_2 = bits(decoded_addr_decoded_107, 0, 0) node decoded_addr_142_2 = bits(decoded_addr_decoded_108, 0, 0) node decoded_addr_13_2 = bits(decoded_addr_decoded_109, 0, 0) node decoded_addr_35_2 = bits(decoded_addr_decoded_110, 0, 0) node decoded_addr_2_2 = bits(decoded_addr_decoded_111, 0, 0) node decoded_addr_66_2 = bits(decoded_addr_decoded_112, 0, 0) node decoded_addr_42_2 = bits(decoded_addr_decoded_113, 0, 0) node decoded_addr_61_2 = bits(decoded_addr_decoded_114, 0, 0) node decoded_addr_48_2 = bits(decoded_addr_decoded_115, 0, 0) node decoded_addr_44_2 = bits(decoded_addr_decoded_116, 0, 0) node decoded_addr_15_2 = bits(decoded_addr_decoded_117, 0, 0) node decoded_addr_145_2 = bits(decoded_addr_decoded_118, 0, 0) node decoded_addr_93_2 = bits(decoded_addr_decoded_119, 0, 0) node decoded_addr_6_2 = bits(decoded_addr_decoded_120, 0, 0) node decoded_addr_28_2 = bits(decoded_addr_decoded_121, 0, 0) node decoded_addr_25_2 = bits(decoded_addr_decoded_122, 0, 0) node decoded_addr_137_2 = bits(decoded_addr_decoded_123, 0, 0) node decoded_addr_123_2 = bits(decoded_addr_decoded_124, 0, 0) node decoded_addr_23_2 = bits(decoded_addr_decoded_125, 0, 0) node decoded_addr_69_2 = bits(decoded_addr_decoded_126, 0, 0) node decoded_addr_141_2 = bits(decoded_addr_decoded_127, 0, 0) node decoded_addr_9_2 = bits(decoded_addr_decoded_128, 0, 0) node decoded_addr_104_2 = bits(decoded_addr_decoded_129, 0, 0) node decoded_addr_8_2 = bits(decoded_addr_decoded_130, 0, 0) node decoded_addr_125_2 = bits(decoded_addr_decoded_131, 0, 0) node decoded_addr_85_2 = bits(decoded_addr_decoded_132, 0, 0) node decoded_addr_54_2 = bits(decoded_addr_decoded_133, 0, 0) node decoded_addr_20_2 = bits(decoded_addr_decoded_134, 0, 0) node decoded_addr_135_2 = bits(decoded_addr_decoded_135, 0, 0) node decoded_addr_115_2 = bits(decoded_addr_decoded_136, 0, 0) node decoded_addr_43_2 = bits(decoded_addr_decoded_137, 0, 0) node decoded_addr_71_2 = bits(decoded_addr_decoded_138, 0, 0) node decoded_addr_110_2 = bits(decoded_addr_decoded_139, 0, 0) node decoded_addr_140_2 = bits(decoded_addr_decoded_140, 0, 0) node decoded_addr_34_2 = bits(decoded_addr_decoded_141, 0, 0) node decoded_addr_40_2 = bits(decoded_addr_decoded_142, 0, 0) node decoded_addr_80_2 = bits(decoded_addr_decoded_143, 0, 0) node decoded_addr_98_2 = bits(decoded_addr_decoded_144, 0, 0) node decoded_addr_18_2 = bits(decoded_addr_decoded_145, 0, 0) node decoded_addr_3_2 = bits(decoded_addr_decoded_146, 0, 0) node decoded_addr_38_2 = bits(decoded_addr_decoded_147, 0, 0) node decoded_addr_127_2 = bits(decoded_addr_decoded_148, 0, 0) node decoded_addr_95_2 = bits(decoded_addr_decoded_149, 0, 0) node _wdata_T = bits(io.rw.cmd, 1, 1) node _wdata_T_1 = mux(_wdata_T, io.rw.rdata, UInt<1>(0h0)) node _wdata_T_2 = or(_wdata_T_1, io.rw.wdata) node _wdata_T_3 = bits(io.rw.cmd, 1, 0) node _wdata_T_4 = andr(_wdata_T_3) node _wdata_T_5 = mux(_wdata_T_4, io.rw.wdata, UInt<1>(0h0)) node _wdata_T_6 = not(_wdata_T_5) node wdata = and(_wdata_T_2, _wdata_T_6) node system_insn = eq(io.rw.cmd, UInt<3>(0h4)) node _insn_T = shl(io.rw.addr, 20) node insn = or(UInt<7>(0h73), _insn_T) wire decoded_plaInput : UInt<32> node decoded_invInputs = not(decoded_plaInput) wire decoded : UInt<9> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_plaInput, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_plaInput, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_16 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo) node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_andMatrixOutputs_hi_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_plaInput, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs, 31, 31) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_6) node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_0_2) node _decoded_orMatrixOutputs_T_1 = orr(decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T_2 = orr(decoded_andMatrixOutputs_5_2) node _decoded_orMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_4 = orr(_decoded_orMatrixOutputs_T_3) node _decoded_orMatrixOutputs_T_5 = orr(decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_6_2) node decoded_orMatrixOutputs_lo_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi = cat(_decoded_orMatrixOutputs_T, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo = cat(_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5) node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4) node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) node decoded_invMatrixOutputs_lo_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded, decoded_invMatrixOutputs connect decoded_plaInput, insn node _T_53 = bits(decoded, 8, 8) node _T_54 = bits(decoded, 7, 7) node _T_55 = bits(decoded, 6, 6) node _T_56 = bits(decoded, 5, 5) node _T_57 = bits(decoded, 4, 4) node _T_58 = bits(decoded, 3, 3) node _T_59 = bits(decoded, 2, 2) node _T_60 = bits(decoded, 1, 1) node _T_61 = bits(decoded, 0, 0) node _T_62 = bits(_T_53, 0, 0) node insn_call = and(system_insn, _T_62) node _T_63 = bits(_T_54, 0, 0) node insn_break = and(system_insn, _T_63) node _T_64 = bits(_T_55, 0, 0) node insn_ret = and(system_insn, _T_64) node _T_65 = bits(_T_56, 0, 0) node insn_cease = and(system_insn, _T_65) node _T_66 = bits(_T_57, 0, 0) node insn_wfi = and(system_insn, _T_66) node _T_67 = bits(_T_58, 0, 0) node _T_68 = and(system_insn, _T_67) node _T_69 = bits(_T_59, 0, 0) node _T_70 = and(system_insn, _T_69) node _T_71 = bits(_T_60, 0, 0) node _T_72 = and(system_insn, _T_71) node _T_73 = bits(_T_61, 0, 0) node _T_74 = and(system_insn, _T_73) node addr = bits(io.decode[0].inst, 31, 20) wire decoded_plaInput_1 : UInt<32> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_1 : UInt<9> node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_invInputs_1, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_1, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_6_2_1 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput_1, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_1, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_4_2_1 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_plaInput_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_plaInput_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_plaInput_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1) node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11) node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_5_2_1 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_plaInput_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs_1, 31, 31) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_13) node _decoded_orMatrixOutputs_T_7 = orr(decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_8 = orr(decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_9 = orr(decoded_andMatrixOutputs_5_2_1) node _decoded_orMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node _decoded_orMatrixOutputs_T_12 = orr(decoded_andMatrixOutputs_4_2_1) node _decoded_orMatrixOutputs_T_13 = orr(decoded_andMatrixOutputs_6_2_1) node decoded_orMatrixOutputs_lo_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_7, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_1 = cat(_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8) node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11) node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_1, 7, 7) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_1, 8, 8) node decoded_invMatrixOutputs_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, io.decode[0].inst node _T_75 = bits(decoded_1, 8, 8) node _T_76 = bits(decoded_1, 7, 7) node _T_77 = bits(decoded_1, 6, 6) node _T_78 = bits(decoded_1, 5, 5) node _T_79 = bits(decoded_1, 4, 4) node _T_80 = bits(decoded_1, 3, 3) node _T_81 = bits(decoded_1, 2, 2) node _T_82 = bits(decoded_1, 1, 1) node _T_83 = bits(decoded_1, 0, 0) node _T_84 = bits(_T_75, 0, 0) node is_break = bits(_T_76, 0, 0) node is_ret = bits(_T_77, 0, 0) node _T_85 = bits(_T_78, 0, 0) node is_wfi = bits(_T_79, 0, 0) node is_sfence = bits(_T_80, 0, 0) node is_hfence_vvma = bits(_T_81, 0, 0) node is_hfence_gvma = bits(_T_82, 0, 0) node is_hlsv = bits(_T_83, 0, 0) node _is_counter_T = geq(addr, UInt<12>(0hc00)) node _is_counter_T_1 = lt(addr, UInt<12>(0hc20)) node _is_counter_T_2 = and(_is_counter_T, _is_counter_T_1) node _is_counter_T_3 = geq(addr, UInt<12>(0hc80)) node _is_counter_T_4 = lt(addr, UInt<12>(0hca0)) node _is_counter_T_5 = and(_is_counter_T_3, _is_counter_T_4) node is_counter = or(_is_counter_T_2, _is_counter_T_5) node _allow_wfi_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_wfi_T_1 = or(UInt<1>(0h0), _allow_wfi_T) node _allow_wfi_T_2 = eq(reg_mstatus.tw, UInt<1>(0h0)) node _allow_wfi_T_3 = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_wfi_T_4 = eq(reg_hstatus.vtw, UInt<1>(0h0)) node _allow_wfi_T_5 = or(_allow_wfi_T_3, _allow_wfi_T_4) node _allow_wfi_T_6 = and(_allow_wfi_T_2, _allow_wfi_T_5) node allow_wfi = or(_allow_wfi_T_1, _allow_wfi_T_6) node _allow_sfence_vma_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_sfence_vma_T_1 = or(UInt<1>(0h0), _allow_sfence_vma_T) node _allow_sfence_vma_T_2 = mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) node _allow_sfence_vma_T_3 = eq(_allow_sfence_vma_T_2, UInt<1>(0h0)) node allow_sfence_vma = or(_allow_sfence_vma_T_1, _allow_sfence_vma_T_3) node _allow_hfence_vvma_T = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_hfence_vvma_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_hfence_vvma_T_2 = and(_allow_hfence_vvma_T, _allow_hfence_vvma_T_1) node allow_hfence_vvma = or(UInt<1>(0h1), _allow_hfence_vvma_T_2) node _allow_hlsv_T = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_hlsv_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_hlsv_T_2 = or(_allow_hlsv_T_1, reg_hstatus.hu) node _allow_hlsv_T_3 = and(_allow_hlsv_T, _allow_hlsv_T_2) node allow_hlsv = or(UInt<1>(0h1), _allow_hlsv_T_3) node _allow_sret_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_sret_T_1 = or(UInt<1>(0h0), _allow_sret_T) node _allow_sret_T_2 = mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) node _allow_sret_T_3 = eq(_allow_sret_T_2, UInt<1>(0h0)) node allow_sret = or(_allow_sret_T_1, _allow_sret_T_3) node counter_addr = bits(addr, 4, 0) node _allow_counter_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_counter_T_1 = dshr(read_mcounteren, counter_addr) node _allow_counter_T_2 = bits(_allow_counter_T_1, 0, 0) node _allow_counter_T_3 = or(_allow_counter_T, _allow_counter_T_2) node _allow_counter_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _allow_counter_T_5 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_counter_T_6 = or(_allow_counter_T_4, _allow_counter_T_5) node _allow_counter_T_7 = dshr(read_scounteren, counter_addr) node _allow_counter_T_8 = bits(_allow_counter_T_7, 0, 0) node _allow_counter_T_9 = or(_allow_counter_T_6, _allow_counter_T_8) node _allow_counter_T_10 = and(_allow_counter_T_3, _allow_counter_T_9) node _allow_counter_T_11 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _allow_counter_T_12 = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_counter_T_13 = or(_allow_counter_T_11, _allow_counter_T_12) node _allow_counter_T_14 = dshr(read_hcounteren, counter_addr) node _allow_counter_T_15 = bits(_allow_counter_T_14, 0, 0) node _allow_counter_T_16 = or(_allow_counter_T_13, _allow_counter_T_15) node allow_counter = and(_allow_counter_T_10, _allow_counter_T_16) node _io_decode_0_fp_illegal_T = eq(io.status.fs, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_1 = eq(reg_vsstatus.fs, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_fp_illegal_T_1) node _io_decode_0_fp_illegal_T_3 = or(_io_decode_0_fp_illegal_T, _io_decode_0_fp_illegal_T_2) node _io_decode_0_fp_illegal_T_4 = bits(reg_misa, 5, 5) node _io_decode_0_fp_illegal_T_5 = eq(_io_decode_0_fp_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_6 = or(_io_decode_0_fp_illegal_T_3, _io_decode_0_fp_illegal_T_5) connect io.decode[0].fp_illegal, _io_decode_0_fp_illegal_T_6 node _io_decode_0_vector_illegal_T = eq(io.status.vs, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_1 = eq(reg_vsstatus.vs, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_vector_illegal_T_1) node _io_decode_0_vector_illegal_T_3 = or(_io_decode_0_vector_illegal_T, _io_decode_0_vector_illegal_T_2) node _io_decode_0_vector_illegal_T_4 = bits(reg_misa, 21, 21) node _io_decode_0_vector_illegal_T_5 = eq(_io_decode_0_vector_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_6 = or(_io_decode_0_vector_illegal_T_3, _io_decode_0_vector_illegal_T_5) connect io.decode[0].vector_illegal, _io_decode_0_vector_illegal_T_6 wire io_decode_0_fp_csr_plaInput : UInt<12> node io_decode_0_fp_csr_invInputs = not(io_decode_0_fp_csr_plaInput) wire io_decode_0_fp_csr_plaOutput : UInt<1> node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_fp_csr_invInputs, 8, 8) node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_fp_csr_invInputs, 9, 9) node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_fp_csr_invInputs, 10, 10) node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_fp_csr_invInputs, 11, 11) node io_decode_0_fp_csr_andMatrixOutputs_lo = cat(io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3) node io_decode_0_fp_csr_andMatrixOutputs_hi = cat(io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1) node _io_decode_0_fp_csr_andMatrixOutputs_T = cat(io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo) node io_decode_0_fp_csr_andMatrixOutputs_0_2 = andr(_io_decode_0_fp_csr_andMatrixOutputs_T) node io_decode_0_fp_csr_orMatrixOutputs = orr(io_decode_0_fp_csr_andMatrixOutputs_0_2) node io_decode_0_fp_csr_invMatrixOutputs = bits(io_decode_0_fp_csr_orMatrixOutputs, 0, 0) connect io_decode_0_fp_csr_plaOutput, io_decode_0_fp_csr_invMatrixOutputs connect io_decode_0_fp_csr_plaInput, addr node _io_decode_0_fp_csr_T = bits(io_decode_0_fp_csr_plaOutput, 0, 0) connect io.decode[0].fp_csr, _io_decode_0_fp_csr_T wire io_decode_0_vector_csr_plaInput : UInt<12> node io_decode_0_vector_csr_invInputs = not(io_decode_0_vector_csr_plaInput) wire io_decode_0_vector_csr_plaOutput : UInt<1> connect io_decode_0_vector_csr_plaOutput, UInt<1>(0h0) connect io_decode_0_vector_csr_plaInput, addr node _io_decode_0_vector_csr_T = bits(io_decode_0_vector_csr_plaOutput, 0, 0) connect io.decode[0].vector_csr, _io_decode_0_vector_csr_T node _io_decode_0_rocc_illegal_T = eq(io.status.xs, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_1 = eq(reg_vsstatus.xs, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_rocc_illegal_T_1) node _io_decode_0_rocc_illegal_T_3 = or(_io_decode_0_rocc_illegal_T, _io_decode_0_rocc_illegal_T_2) node _io_decode_0_rocc_illegal_T_4 = bits(reg_misa, 23, 23) node _io_decode_0_rocc_illegal_T_5 = eq(_io_decode_0_rocc_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_6 = or(_io_decode_0_rocc_illegal_T_3, _io_decode_0_rocc_illegal_T_5) connect io.decode[0].rocc_illegal, _io_decode_0_rocc_illegal_T_6 node _csr_addr_legal_T = bits(addr, 9, 8) node _csr_addr_legal_T_1 = geq(reg_mstatus.prv, _csr_addr_legal_T) node _csr_addr_legal_T_2 = eq(reg_mstatus.v, UInt<1>(0h0)) node _csr_addr_legal_T_3 = and(UInt<1>(0h0), _csr_addr_legal_T_2) node _csr_addr_legal_T_4 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _csr_addr_legal_T_5 = and(_csr_addr_legal_T_3, _csr_addr_legal_T_4) node _csr_addr_legal_T_6 = bits(addr, 9, 8) node _csr_addr_legal_T_7 = eq(_csr_addr_legal_T_6, UInt<2>(0h2)) node _csr_addr_legal_T_8 = and(_csr_addr_legal_T_5, _csr_addr_legal_T_7) node csr_addr_legal = or(_csr_addr_legal_T_1, _csr_addr_legal_T_8) node _csr_exists_T = eq(addr, UInt<11>(0h7a0)) node _csr_exists_T_1 = eq(addr, UInt<11>(0h7a1)) node _csr_exists_T_2 = eq(addr, UInt<11>(0h7a2)) node _csr_exists_T_3 = eq(addr, UInt<11>(0h7a3)) node _csr_exists_T_4 = eq(addr, UInt<10>(0h301)) node _csr_exists_T_5 = eq(addr, UInt<10>(0h300)) node _csr_exists_T_6 = eq(addr, UInt<10>(0h305)) node _csr_exists_T_7 = eq(addr, UInt<10>(0h344)) node _csr_exists_T_8 = eq(addr, UInt<10>(0h304)) node _csr_exists_T_9 = eq(addr, UInt<10>(0h340)) node _csr_exists_T_10 = eq(addr, UInt<10>(0h341)) node _csr_exists_T_11 = eq(addr, UInt<10>(0h343)) node _csr_exists_T_12 = eq(addr, UInt<10>(0h342)) node _csr_exists_T_13 = eq(addr, UInt<12>(0hf14)) node _csr_exists_T_14 = eq(addr, UInt<11>(0h7b0)) node _csr_exists_T_15 = eq(addr, UInt<11>(0h7b1)) node _csr_exists_T_16 = eq(addr, UInt<11>(0h7b2)) node _csr_exists_T_17 = eq(addr, UInt<1>(0h1)) node _csr_exists_T_18 = eq(addr, UInt<2>(0h2)) node _csr_exists_T_19 = eq(addr, UInt<2>(0h3)) node _csr_exists_T_20 = eq(addr, UInt<10>(0h320)) node _csr_exists_T_21 = eq(addr, UInt<12>(0hb00)) node _csr_exists_T_22 = eq(addr, UInt<12>(0hb02)) node _csr_exists_T_23 = eq(addr, UInt<10>(0h323)) node _csr_exists_T_24 = eq(addr, UInt<12>(0hb03)) node _csr_exists_T_25 = eq(addr, UInt<12>(0hc03)) node _csr_exists_T_26 = eq(addr, UInt<10>(0h324)) node _csr_exists_T_27 = eq(addr, UInt<12>(0hb04)) node _csr_exists_T_28 = eq(addr, UInt<12>(0hc04)) node _csr_exists_T_29 = eq(addr, UInt<10>(0h325)) node _csr_exists_T_30 = eq(addr, UInt<12>(0hb05)) node _csr_exists_T_31 = eq(addr, UInt<12>(0hc05)) node _csr_exists_T_32 = eq(addr, UInt<10>(0h326)) node _csr_exists_T_33 = eq(addr, UInt<12>(0hb06)) node _csr_exists_T_34 = eq(addr, UInt<12>(0hc06)) node _csr_exists_T_35 = eq(addr, UInt<10>(0h327)) node _csr_exists_T_36 = eq(addr, UInt<12>(0hb07)) node _csr_exists_T_37 = eq(addr, UInt<12>(0hc07)) node _csr_exists_T_38 = eq(addr, UInt<10>(0h328)) node _csr_exists_T_39 = eq(addr, UInt<12>(0hb08)) node _csr_exists_T_40 = eq(addr, UInt<12>(0hc08)) node _csr_exists_T_41 = eq(addr, UInt<10>(0h329)) node _csr_exists_T_42 = eq(addr, UInt<12>(0hb09)) node _csr_exists_T_43 = eq(addr, UInt<12>(0hc09)) node _csr_exists_T_44 = eq(addr, UInt<10>(0h32a)) node _csr_exists_T_45 = eq(addr, UInt<12>(0hb0a)) node _csr_exists_T_46 = eq(addr, UInt<12>(0hc0a)) node _csr_exists_T_47 = eq(addr, UInt<10>(0h32b)) node _csr_exists_T_48 = eq(addr, UInt<12>(0hb0b)) node _csr_exists_T_49 = eq(addr, UInt<12>(0hc0b)) node _csr_exists_T_50 = eq(addr, UInt<10>(0h32c)) node _csr_exists_T_51 = eq(addr, UInt<12>(0hb0c)) node _csr_exists_T_52 = eq(addr, UInt<12>(0hc0c)) node _csr_exists_T_53 = eq(addr, UInt<10>(0h32d)) node _csr_exists_T_54 = eq(addr, UInt<12>(0hb0d)) node _csr_exists_T_55 = eq(addr, UInt<12>(0hc0d)) node _csr_exists_T_56 = eq(addr, UInt<10>(0h32e)) node _csr_exists_T_57 = eq(addr, UInt<12>(0hb0e)) node _csr_exists_T_58 = eq(addr, UInt<12>(0hc0e)) node _csr_exists_T_59 = eq(addr, UInt<10>(0h32f)) node _csr_exists_T_60 = eq(addr, UInt<12>(0hb0f)) node _csr_exists_T_61 = eq(addr, UInt<12>(0hc0f)) node _csr_exists_T_62 = eq(addr, UInt<10>(0h330)) node _csr_exists_T_63 = eq(addr, UInt<12>(0hb10)) node _csr_exists_T_64 = eq(addr, UInt<12>(0hc10)) node _csr_exists_T_65 = eq(addr, UInt<10>(0h331)) node _csr_exists_T_66 = eq(addr, UInt<12>(0hb11)) node _csr_exists_T_67 = eq(addr, UInt<12>(0hc11)) node _csr_exists_T_68 = eq(addr, UInt<10>(0h332)) node _csr_exists_T_69 = eq(addr, UInt<12>(0hb12)) node _csr_exists_T_70 = eq(addr, UInt<12>(0hc12)) node _csr_exists_T_71 = eq(addr, UInt<10>(0h333)) node _csr_exists_T_72 = eq(addr, UInt<12>(0hb13)) node _csr_exists_T_73 = eq(addr, UInt<12>(0hc13)) node _csr_exists_T_74 = eq(addr, UInt<10>(0h334)) node _csr_exists_T_75 = eq(addr, UInt<12>(0hb14)) node _csr_exists_T_76 = eq(addr, UInt<12>(0hc14)) node _csr_exists_T_77 = eq(addr, UInt<10>(0h335)) node _csr_exists_T_78 = eq(addr, UInt<12>(0hb15)) node _csr_exists_T_79 = eq(addr, UInt<12>(0hc15)) node _csr_exists_T_80 = eq(addr, UInt<10>(0h336)) node _csr_exists_T_81 = eq(addr, UInt<12>(0hb16)) node _csr_exists_T_82 = eq(addr, UInt<12>(0hc16)) node _csr_exists_T_83 = eq(addr, UInt<10>(0h337)) node _csr_exists_T_84 = eq(addr, UInt<12>(0hb17)) node _csr_exists_T_85 = eq(addr, UInt<12>(0hc17)) node _csr_exists_T_86 = eq(addr, UInt<10>(0h338)) node _csr_exists_T_87 = eq(addr, UInt<12>(0hb18)) node _csr_exists_T_88 = eq(addr, UInt<12>(0hc18)) node _csr_exists_T_89 = eq(addr, UInt<10>(0h339)) node _csr_exists_T_90 = eq(addr, UInt<12>(0hb19)) node _csr_exists_T_91 = eq(addr, UInt<12>(0hc19)) node _csr_exists_T_92 = eq(addr, UInt<10>(0h33a)) node _csr_exists_T_93 = eq(addr, UInt<12>(0hb1a)) node _csr_exists_T_94 = eq(addr, UInt<12>(0hc1a)) node _csr_exists_T_95 = eq(addr, UInt<10>(0h33b)) node _csr_exists_T_96 = eq(addr, UInt<12>(0hb1b)) node _csr_exists_T_97 = eq(addr, UInt<12>(0hc1b)) node _csr_exists_T_98 = eq(addr, UInt<10>(0h33c)) node _csr_exists_T_99 = eq(addr, UInt<12>(0hb1c)) node _csr_exists_T_100 = eq(addr, UInt<12>(0hc1c)) node _csr_exists_T_101 = eq(addr, UInt<10>(0h33d)) node _csr_exists_T_102 = eq(addr, UInt<12>(0hb1d)) node _csr_exists_T_103 = eq(addr, UInt<12>(0hc1d)) node _csr_exists_T_104 = eq(addr, UInt<10>(0h33e)) node _csr_exists_T_105 = eq(addr, UInt<12>(0hb1e)) node _csr_exists_T_106 = eq(addr, UInt<12>(0hc1e)) node _csr_exists_T_107 = eq(addr, UInt<10>(0h33f)) node _csr_exists_T_108 = eq(addr, UInt<12>(0hb1f)) node _csr_exists_T_109 = eq(addr, UInt<12>(0hc1f)) node _csr_exists_T_110 = eq(addr, UInt<10>(0h306)) node _csr_exists_T_111 = eq(addr, UInt<12>(0hc00)) node _csr_exists_T_112 = eq(addr, UInt<12>(0hc02)) node _csr_exists_T_113 = eq(addr, UInt<10>(0h30a)) node _csr_exists_T_114 = eq(addr, UInt<9>(0h100)) node _csr_exists_T_115 = eq(addr, UInt<9>(0h144)) node _csr_exists_T_116 = eq(addr, UInt<9>(0h104)) node _csr_exists_T_117 = eq(addr, UInt<9>(0h140)) node _csr_exists_T_118 = eq(addr, UInt<9>(0h142)) node _csr_exists_T_119 = eq(addr, UInt<9>(0h143)) node _csr_exists_T_120 = eq(addr, UInt<9>(0h180)) node _csr_exists_T_121 = eq(addr, UInt<9>(0h141)) node _csr_exists_T_122 = eq(addr, UInt<9>(0h105)) node _csr_exists_T_123 = eq(addr, UInt<9>(0h106)) node _csr_exists_T_124 = eq(addr, UInt<10>(0h303)) node _csr_exists_T_125 = eq(addr, UInt<10>(0h302)) node _csr_exists_T_126 = eq(addr, UInt<9>(0h10a)) node _csr_exists_T_127 = eq(addr, UInt<10>(0h3a0)) node _csr_exists_T_128 = eq(addr, UInt<10>(0h3a2)) node _csr_exists_T_129 = eq(addr, UInt<10>(0h3b0)) node _csr_exists_T_130 = eq(addr, UInt<10>(0h3b1)) node _csr_exists_T_131 = eq(addr, UInt<10>(0h3b2)) node _csr_exists_T_132 = eq(addr, UInt<10>(0h3b3)) node _csr_exists_T_133 = eq(addr, UInt<10>(0h3b4)) node _csr_exists_T_134 = eq(addr, UInt<10>(0h3b5)) node _csr_exists_T_135 = eq(addr, UInt<10>(0h3b6)) node _csr_exists_T_136 = eq(addr, UInt<10>(0h3b7)) node _csr_exists_T_137 = eq(addr, UInt<10>(0h3b8)) node _csr_exists_T_138 = eq(addr, UInt<10>(0h3b9)) node _csr_exists_T_139 = eq(addr, UInt<10>(0h3ba)) node _csr_exists_T_140 = eq(addr, UInt<10>(0h3bb)) node _csr_exists_T_141 = eq(addr, UInt<10>(0h3bc)) node _csr_exists_T_142 = eq(addr, UInt<10>(0h3bd)) node _csr_exists_T_143 = eq(addr, UInt<10>(0h3be)) node _csr_exists_T_144 = eq(addr, UInt<10>(0h3bf)) node _csr_exists_T_145 = eq(addr, UInt<11>(0h7c1)) node _csr_exists_T_146 = eq(addr, UInt<12>(0hf12)) node _csr_exists_T_147 = eq(addr, UInt<12>(0hf11)) node _csr_exists_T_148 = eq(addr, UInt<12>(0hf13)) node _csr_exists_T_149 = eq(addr, UInt<12>(0hf15)) node _csr_exists_T_150 = or(_csr_exists_T, _csr_exists_T_1) node _csr_exists_T_151 = or(_csr_exists_T_150, _csr_exists_T_2) node _csr_exists_T_152 = or(_csr_exists_T_151, _csr_exists_T_3) node _csr_exists_T_153 = or(_csr_exists_T_152, _csr_exists_T_4) node _csr_exists_T_154 = or(_csr_exists_T_153, _csr_exists_T_5) node _csr_exists_T_155 = or(_csr_exists_T_154, _csr_exists_T_6) node _csr_exists_T_156 = or(_csr_exists_T_155, _csr_exists_T_7) node _csr_exists_T_157 = or(_csr_exists_T_156, _csr_exists_T_8) node _csr_exists_T_158 = or(_csr_exists_T_157, _csr_exists_T_9) node _csr_exists_T_159 = or(_csr_exists_T_158, _csr_exists_T_10) node _csr_exists_T_160 = or(_csr_exists_T_159, _csr_exists_T_11) node _csr_exists_T_161 = or(_csr_exists_T_160, _csr_exists_T_12) node _csr_exists_T_162 = or(_csr_exists_T_161, _csr_exists_T_13) node _csr_exists_T_163 = or(_csr_exists_T_162, _csr_exists_T_14) node _csr_exists_T_164 = or(_csr_exists_T_163, _csr_exists_T_15) node _csr_exists_T_165 = or(_csr_exists_T_164, _csr_exists_T_16) node _csr_exists_T_166 = or(_csr_exists_T_165, _csr_exists_T_17) node _csr_exists_T_167 = or(_csr_exists_T_166, _csr_exists_T_18) node _csr_exists_T_168 = or(_csr_exists_T_167, _csr_exists_T_19) node _csr_exists_T_169 = or(_csr_exists_T_168, _csr_exists_T_20) node _csr_exists_T_170 = or(_csr_exists_T_169, _csr_exists_T_21) node _csr_exists_T_171 = or(_csr_exists_T_170, _csr_exists_T_22) node _csr_exists_T_172 = or(_csr_exists_T_171, _csr_exists_T_23) node _csr_exists_T_173 = or(_csr_exists_T_172, _csr_exists_T_24) node _csr_exists_T_174 = or(_csr_exists_T_173, _csr_exists_T_25) node _csr_exists_T_175 = or(_csr_exists_T_174, _csr_exists_T_26) node _csr_exists_T_176 = or(_csr_exists_T_175, _csr_exists_T_27) node _csr_exists_T_177 = or(_csr_exists_T_176, _csr_exists_T_28) node _csr_exists_T_178 = or(_csr_exists_T_177, _csr_exists_T_29) node _csr_exists_T_179 = or(_csr_exists_T_178, _csr_exists_T_30) node _csr_exists_T_180 = or(_csr_exists_T_179, _csr_exists_T_31) node _csr_exists_T_181 = or(_csr_exists_T_180, _csr_exists_T_32) node _csr_exists_T_182 = or(_csr_exists_T_181, _csr_exists_T_33) node _csr_exists_T_183 = or(_csr_exists_T_182, _csr_exists_T_34) node _csr_exists_T_184 = or(_csr_exists_T_183, _csr_exists_T_35) node _csr_exists_T_185 = or(_csr_exists_T_184, _csr_exists_T_36) node _csr_exists_T_186 = or(_csr_exists_T_185, _csr_exists_T_37) node _csr_exists_T_187 = or(_csr_exists_T_186, _csr_exists_T_38) node _csr_exists_T_188 = or(_csr_exists_T_187, _csr_exists_T_39) node _csr_exists_T_189 = or(_csr_exists_T_188, _csr_exists_T_40) node _csr_exists_T_190 = or(_csr_exists_T_189, _csr_exists_T_41) node _csr_exists_T_191 = or(_csr_exists_T_190, _csr_exists_T_42) node _csr_exists_T_192 = or(_csr_exists_T_191, _csr_exists_T_43) node _csr_exists_T_193 = or(_csr_exists_T_192, _csr_exists_T_44) node _csr_exists_T_194 = or(_csr_exists_T_193, _csr_exists_T_45) node _csr_exists_T_195 = or(_csr_exists_T_194, _csr_exists_T_46) node _csr_exists_T_196 = or(_csr_exists_T_195, _csr_exists_T_47) node _csr_exists_T_197 = or(_csr_exists_T_196, _csr_exists_T_48) node _csr_exists_T_198 = or(_csr_exists_T_197, _csr_exists_T_49) node _csr_exists_T_199 = or(_csr_exists_T_198, _csr_exists_T_50) node _csr_exists_T_200 = or(_csr_exists_T_199, _csr_exists_T_51) node _csr_exists_T_201 = or(_csr_exists_T_200, _csr_exists_T_52) node _csr_exists_T_202 = or(_csr_exists_T_201, _csr_exists_T_53) node _csr_exists_T_203 = or(_csr_exists_T_202, _csr_exists_T_54) node _csr_exists_T_204 = or(_csr_exists_T_203, _csr_exists_T_55) node _csr_exists_T_205 = or(_csr_exists_T_204, _csr_exists_T_56) node _csr_exists_T_206 = or(_csr_exists_T_205, _csr_exists_T_57) node _csr_exists_T_207 = or(_csr_exists_T_206, _csr_exists_T_58) node _csr_exists_T_208 = or(_csr_exists_T_207, _csr_exists_T_59) node _csr_exists_T_209 = or(_csr_exists_T_208, _csr_exists_T_60) node _csr_exists_T_210 = or(_csr_exists_T_209, _csr_exists_T_61) node _csr_exists_T_211 = or(_csr_exists_T_210, _csr_exists_T_62) node _csr_exists_T_212 = or(_csr_exists_T_211, _csr_exists_T_63) node _csr_exists_T_213 = or(_csr_exists_T_212, _csr_exists_T_64) node _csr_exists_T_214 = or(_csr_exists_T_213, _csr_exists_T_65) node _csr_exists_T_215 = or(_csr_exists_T_214, _csr_exists_T_66) node _csr_exists_T_216 = or(_csr_exists_T_215, _csr_exists_T_67) node _csr_exists_T_217 = or(_csr_exists_T_216, _csr_exists_T_68) node _csr_exists_T_218 = or(_csr_exists_T_217, _csr_exists_T_69) node _csr_exists_T_219 = or(_csr_exists_T_218, _csr_exists_T_70) node _csr_exists_T_220 = or(_csr_exists_T_219, _csr_exists_T_71) node _csr_exists_T_221 = or(_csr_exists_T_220, _csr_exists_T_72) node _csr_exists_T_222 = or(_csr_exists_T_221, _csr_exists_T_73) node _csr_exists_T_223 = or(_csr_exists_T_222, _csr_exists_T_74) node _csr_exists_T_224 = or(_csr_exists_T_223, _csr_exists_T_75) node _csr_exists_T_225 = or(_csr_exists_T_224, _csr_exists_T_76) node _csr_exists_T_226 = or(_csr_exists_T_225, _csr_exists_T_77) node _csr_exists_T_227 = or(_csr_exists_T_226, _csr_exists_T_78) node _csr_exists_T_228 = or(_csr_exists_T_227, _csr_exists_T_79) node _csr_exists_T_229 = or(_csr_exists_T_228, _csr_exists_T_80) node _csr_exists_T_230 = or(_csr_exists_T_229, _csr_exists_T_81) node _csr_exists_T_231 = or(_csr_exists_T_230, _csr_exists_T_82) node _csr_exists_T_232 = or(_csr_exists_T_231, _csr_exists_T_83) node _csr_exists_T_233 = or(_csr_exists_T_232, _csr_exists_T_84) node _csr_exists_T_234 = or(_csr_exists_T_233, _csr_exists_T_85) node _csr_exists_T_235 = or(_csr_exists_T_234, _csr_exists_T_86) node _csr_exists_T_236 = or(_csr_exists_T_235, _csr_exists_T_87) node _csr_exists_T_237 = or(_csr_exists_T_236, _csr_exists_T_88) node _csr_exists_T_238 = or(_csr_exists_T_237, _csr_exists_T_89) node _csr_exists_T_239 = or(_csr_exists_T_238, _csr_exists_T_90) node _csr_exists_T_240 = or(_csr_exists_T_239, _csr_exists_T_91) node _csr_exists_T_241 = or(_csr_exists_T_240, _csr_exists_T_92) node _csr_exists_T_242 = or(_csr_exists_T_241, _csr_exists_T_93) node _csr_exists_T_243 = or(_csr_exists_T_242, _csr_exists_T_94) node _csr_exists_T_244 = or(_csr_exists_T_243, _csr_exists_T_95) node _csr_exists_T_245 = or(_csr_exists_T_244, _csr_exists_T_96) node _csr_exists_T_246 = or(_csr_exists_T_245, _csr_exists_T_97) node _csr_exists_T_247 = or(_csr_exists_T_246, _csr_exists_T_98) node _csr_exists_T_248 = or(_csr_exists_T_247, _csr_exists_T_99) node _csr_exists_T_249 = or(_csr_exists_T_248, _csr_exists_T_100) node _csr_exists_T_250 = or(_csr_exists_T_249, _csr_exists_T_101) node _csr_exists_T_251 = or(_csr_exists_T_250, _csr_exists_T_102) node _csr_exists_T_252 = or(_csr_exists_T_251, _csr_exists_T_103) node _csr_exists_T_253 = or(_csr_exists_T_252, _csr_exists_T_104) node _csr_exists_T_254 = or(_csr_exists_T_253, _csr_exists_T_105) node _csr_exists_T_255 = or(_csr_exists_T_254, _csr_exists_T_106) node _csr_exists_T_256 = or(_csr_exists_T_255, _csr_exists_T_107) node _csr_exists_T_257 = or(_csr_exists_T_256, _csr_exists_T_108) node _csr_exists_T_258 = or(_csr_exists_T_257, _csr_exists_T_109) node _csr_exists_T_259 = or(_csr_exists_T_258, _csr_exists_T_110) node _csr_exists_T_260 = or(_csr_exists_T_259, _csr_exists_T_111) node _csr_exists_T_261 = or(_csr_exists_T_260, _csr_exists_T_112) node _csr_exists_T_262 = or(_csr_exists_T_261, _csr_exists_T_113) node _csr_exists_T_263 = or(_csr_exists_T_262, _csr_exists_T_114) node _csr_exists_T_264 = or(_csr_exists_T_263, _csr_exists_T_115) node _csr_exists_T_265 = or(_csr_exists_T_264, _csr_exists_T_116) node _csr_exists_T_266 = or(_csr_exists_T_265, _csr_exists_T_117) node _csr_exists_T_267 = or(_csr_exists_T_266, _csr_exists_T_118) node _csr_exists_T_268 = or(_csr_exists_T_267, _csr_exists_T_119) node _csr_exists_T_269 = or(_csr_exists_T_268, _csr_exists_T_120) node _csr_exists_T_270 = or(_csr_exists_T_269, _csr_exists_T_121) node _csr_exists_T_271 = or(_csr_exists_T_270, _csr_exists_T_122) node _csr_exists_T_272 = or(_csr_exists_T_271, _csr_exists_T_123) node _csr_exists_T_273 = or(_csr_exists_T_272, _csr_exists_T_124) node _csr_exists_T_274 = or(_csr_exists_T_273, _csr_exists_T_125) node _csr_exists_T_275 = or(_csr_exists_T_274, _csr_exists_T_126) node _csr_exists_T_276 = or(_csr_exists_T_275, _csr_exists_T_127) node _csr_exists_T_277 = or(_csr_exists_T_276, _csr_exists_T_128) node _csr_exists_T_278 = or(_csr_exists_T_277, _csr_exists_T_129) node _csr_exists_T_279 = or(_csr_exists_T_278, _csr_exists_T_130) node _csr_exists_T_280 = or(_csr_exists_T_279, _csr_exists_T_131) node _csr_exists_T_281 = or(_csr_exists_T_280, _csr_exists_T_132) node _csr_exists_T_282 = or(_csr_exists_T_281, _csr_exists_T_133) node _csr_exists_T_283 = or(_csr_exists_T_282, _csr_exists_T_134) node _csr_exists_T_284 = or(_csr_exists_T_283, _csr_exists_T_135) node _csr_exists_T_285 = or(_csr_exists_T_284, _csr_exists_T_136) node _csr_exists_T_286 = or(_csr_exists_T_285, _csr_exists_T_137) node _csr_exists_T_287 = or(_csr_exists_T_286, _csr_exists_T_138) node _csr_exists_T_288 = or(_csr_exists_T_287, _csr_exists_T_139) node _csr_exists_T_289 = or(_csr_exists_T_288, _csr_exists_T_140) node _csr_exists_T_290 = or(_csr_exists_T_289, _csr_exists_T_141) node _csr_exists_T_291 = or(_csr_exists_T_290, _csr_exists_T_142) node _csr_exists_T_292 = or(_csr_exists_T_291, _csr_exists_T_143) node _csr_exists_T_293 = or(_csr_exists_T_292, _csr_exists_T_144) node _csr_exists_T_294 = or(_csr_exists_T_293, _csr_exists_T_145) node _csr_exists_T_295 = or(_csr_exists_T_294, _csr_exists_T_146) node _csr_exists_T_296 = or(_csr_exists_T_295, _csr_exists_T_147) node _csr_exists_T_297 = or(_csr_exists_T_296, _csr_exists_T_148) node csr_exists = or(_csr_exists_T_297, _csr_exists_T_149) node _io_decode_0_read_illegal_T = eq(csr_addr_legal, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_1 = eq(csr_exists, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_2 = or(_io_decode_0_read_illegal_T, _io_decode_0_read_illegal_T_1) node _io_decode_0_read_illegal_T_3 = eq(addr, UInt<9>(0h180)) node _io_decode_0_read_illegal_T_4 = eq(addr, UInt<11>(0h680)) node _io_decode_0_read_illegal_T_5 = or(_io_decode_0_read_illegal_T_3, _io_decode_0_read_illegal_T_4) node _io_decode_0_read_illegal_T_6 = eq(allow_sfence_vma, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_7 = and(_io_decode_0_read_illegal_T_5, _io_decode_0_read_illegal_T_6) node _io_decode_0_read_illegal_T_8 = or(_io_decode_0_read_illegal_T_2, _io_decode_0_read_illegal_T_7) node _io_decode_0_read_illegal_T_9 = eq(allow_counter, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_10 = and(is_counter, _io_decode_0_read_illegal_T_9) node _io_decode_0_read_illegal_T_11 = or(_io_decode_0_read_illegal_T_8, _io_decode_0_read_illegal_T_10) wire io_decode_0_read_illegal_plaInput : UInt<12> node io_decode_0_read_illegal_invInputs = not(io_decode_0_read_illegal_plaInput) wire io_decode_0_read_illegal_plaOutput : UInt<1> node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_read_illegal_plaInput, 4, 4) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_read_illegal_plaInput, 5, 5) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_read_illegal_invInputs, 6, 6) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_read_illegal_plaInput, 7, 7) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = bits(io_decode_0_read_illegal_plaInput, 8, 8) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = bits(io_decode_0_read_illegal_plaInput, 9, 9) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = bits(io_decode_0_read_illegal_plaInput, 10, 10) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = bits(io_decode_0_read_illegal_invInputs, 11, 11) node io_decode_0_read_illegal_andMatrixOutputs_lo_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7) node io_decode_0_read_illegal_andMatrixOutputs_lo_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5) node io_decode_0_read_illegal_andMatrixOutputs_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo) node io_decode_0_read_illegal_andMatrixOutputs_hi_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3) node io_decode_0_read_illegal_andMatrixOutputs_hi_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1) node io_decode_0_read_illegal_andMatrixOutputs_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo) node _io_decode_0_read_illegal_andMatrixOutputs_T = cat(io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo) node io_decode_0_read_illegal_andMatrixOutputs_0_2 = andr(_io_decode_0_read_illegal_andMatrixOutputs_T) node io_decode_0_read_illegal_orMatrixOutputs = orr(io_decode_0_read_illegal_andMatrixOutputs_0_2) node io_decode_0_read_illegal_invMatrixOutputs = bits(io_decode_0_read_illegal_orMatrixOutputs, 0, 0) connect io_decode_0_read_illegal_plaOutput, io_decode_0_read_illegal_invMatrixOutputs connect io_decode_0_read_illegal_plaInput, addr node _io_decode_0_read_illegal_T_12 = bits(io_decode_0_read_illegal_plaOutput, 0, 0) node _io_decode_0_read_illegal_T_13 = eq(reg_debug, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_14 = and(_io_decode_0_read_illegal_T_12, _io_decode_0_read_illegal_T_13) node _io_decode_0_read_illegal_T_15 = or(_io_decode_0_read_illegal_T_11, _io_decode_0_read_illegal_T_14) wire io_decode_0_read_illegal_plaInput_1 : UInt<12> node io_decode_0_read_illegal_invInputs_1 = not(io_decode_0_read_illegal_plaInput_1) wire io_decode_0_read_illegal_plaOutput_1 : UInt<1> connect io_decode_0_read_illegal_plaOutput_1, UInt<1>(0h0) connect io_decode_0_read_illegal_plaInput_1, addr node _io_decode_0_read_illegal_T_16 = bits(io_decode_0_read_illegal_plaOutput_1, 0, 0) node _io_decode_0_read_illegal_T_17 = and(_io_decode_0_read_illegal_T_16, io.decode[0].vector_illegal) node _io_decode_0_read_illegal_T_18 = or(_io_decode_0_read_illegal_T_15, _io_decode_0_read_illegal_T_17) node _io_decode_0_read_illegal_T_19 = and(io.decode[0].fp_csr, io.decode[0].fp_illegal) node _io_decode_0_read_illegal_T_20 = or(_io_decode_0_read_illegal_T_18, _io_decode_0_read_illegal_T_19) connect io.decode[0].read_illegal, _io_decode_0_read_illegal_T_20 node _io_decode_0_write_illegal_T = bits(addr, 11, 10) node _io_decode_0_write_illegal_T_1 = andr(_io_decode_0_write_illegal_T) connect io.decode[0].write_illegal, _io_decode_0_write_illegal_T_1 node _io_decode_0_write_flush_addr_m_T = shl(UInt<2>(0h3), 8) node io_decode_0_write_flush_addr_m = or(addr, _io_decode_0_write_flush_addr_m_T) node _io_decode_0_write_flush_T = geq(io_decode_0_write_flush_addr_m, UInt<10>(0h340)) node _io_decode_0_write_flush_T_1 = leq(io_decode_0_write_flush_addr_m, UInt<10>(0h343)) node _io_decode_0_write_flush_T_2 = and(_io_decode_0_write_flush_T, _io_decode_0_write_flush_T_1) node _io_decode_0_write_flush_T_3 = eq(_io_decode_0_write_flush_T_2, UInt<1>(0h0)) connect io.decode[0].write_flush, _io_decode_0_write_flush_T_3 node _io_decode_0_system_illegal_T = eq(csr_addr_legal, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_1 = eq(is_hlsv, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_2 = and(_io_decode_0_system_illegal_T, _io_decode_0_system_illegal_T_1) node _io_decode_0_system_illegal_T_3 = eq(allow_wfi, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_4 = and(is_wfi, _io_decode_0_system_illegal_T_3) node _io_decode_0_system_illegal_T_5 = or(_io_decode_0_system_illegal_T_2, _io_decode_0_system_illegal_T_4) node _io_decode_0_system_illegal_T_6 = eq(allow_sret, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_7 = and(is_ret, _io_decode_0_system_illegal_T_6) node _io_decode_0_system_illegal_T_8 = or(_io_decode_0_system_illegal_T_5, _io_decode_0_system_illegal_T_7) node _io_decode_0_system_illegal_T_9 = bits(addr, 10, 10) node _io_decode_0_system_illegal_T_10 = and(is_ret, _io_decode_0_system_illegal_T_9) node _io_decode_0_system_illegal_T_11 = bits(addr, 7, 7) node _io_decode_0_system_illegal_T_12 = and(_io_decode_0_system_illegal_T_10, _io_decode_0_system_illegal_T_11) node _io_decode_0_system_illegal_T_13 = eq(reg_debug, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_14 = and(_io_decode_0_system_illegal_T_12, _io_decode_0_system_illegal_T_13) node _io_decode_0_system_illegal_T_15 = or(_io_decode_0_system_illegal_T_8, _io_decode_0_system_illegal_T_14) node _io_decode_0_system_illegal_T_16 = or(is_sfence, is_hfence_gvma) node _io_decode_0_system_illegal_T_17 = eq(allow_sfence_vma, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_18 = and(_io_decode_0_system_illegal_T_16, _io_decode_0_system_illegal_T_17) node _io_decode_0_system_illegal_T_19 = or(_io_decode_0_system_illegal_T_15, _io_decode_0_system_illegal_T_18) node _io_decode_0_system_illegal_T_20 = eq(allow_hfence_vvma, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_21 = and(is_hfence_vvma, _io_decode_0_system_illegal_T_20) node _io_decode_0_system_illegal_T_22 = or(_io_decode_0_system_illegal_T_19, _io_decode_0_system_illegal_T_21) node _io_decode_0_system_illegal_T_23 = eq(allow_hlsv, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_24 = and(is_hlsv, _io_decode_0_system_illegal_T_23) node _io_decode_0_system_illegal_T_25 = or(_io_decode_0_system_illegal_T_22, _io_decode_0_system_illegal_T_24) connect io.decode[0].system_illegal, _io_decode_0_system_illegal_T_25 node _io_decode_0_virtual_access_illegal_T = and(reg_mstatus.v, csr_exists) node _io_decode_0_virtual_access_illegal_T_1 = bits(addr, 9, 8) node _io_decode_0_virtual_access_illegal_T_2 = eq(_io_decode_0_virtual_access_illegal_T_1, UInt<2>(0h2)) node _io_decode_0_virtual_access_illegal_T_3 = dshr(read_mcounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_4 = bits(_io_decode_0_virtual_access_illegal_T_3, 0, 0) node _io_decode_0_virtual_access_illegal_T_5 = and(is_counter, _io_decode_0_virtual_access_illegal_T_4) node _io_decode_0_virtual_access_illegal_T_6 = dshr(read_hcounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_7 = bits(_io_decode_0_virtual_access_illegal_T_6, 0, 0) node _io_decode_0_virtual_access_illegal_T_8 = eq(_io_decode_0_virtual_access_illegal_T_7, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_9 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_10 = eq(_io_decode_0_virtual_access_illegal_T_9, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_11 = dshr(read_scounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_12 = bits(_io_decode_0_virtual_access_illegal_T_11, 0, 0) node _io_decode_0_virtual_access_illegal_T_13 = eq(_io_decode_0_virtual_access_illegal_T_12, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_14 = and(_io_decode_0_virtual_access_illegal_T_10, _io_decode_0_virtual_access_illegal_T_13) node _io_decode_0_virtual_access_illegal_T_15 = or(_io_decode_0_virtual_access_illegal_T_8, _io_decode_0_virtual_access_illegal_T_14) node _io_decode_0_virtual_access_illegal_T_16 = and(_io_decode_0_virtual_access_illegal_T_5, _io_decode_0_virtual_access_illegal_T_15) node _io_decode_0_virtual_access_illegal_T_17 = or(_io_decode_0_virtual_access_illegal_T_2, _io_decode_0_virtual_access_illegal_T_16) node _io_decode_0_virtual_access_illegal_T_18 = bits(addr, 9, 8) node _io_decode_0_virtual_access_illegal_T_19 = eq(_io_decode_0_virtual_access_illegal_T_18, UInt<1>(0h1)) node _io_decode_0_virtual_access_illegal_T_20 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_21 = eq(_io_decode_0_virtual_access_illegal_T_20, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_22 = and(_io_decode_0_virtual_access_illegal_T_19, _io_decode_0_virtual_access_illegal_T_21) node _io_decode_0_virtual_access_illegal_T_23 = or(_io_decode_0_virtual_access_illegal_T_17, _io_decode_0_virtual_access_illegal_T_22) node _io_decode_0_virtual_access_illegal_T_24 = eq(addr, UInt<9>(0h180)) node _io_decode_0_virtual_access_illegal_T_25 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_26 = and(_io_decode_0_virtual_access_illegal_T_24, _io_decode_0_virtual_access_illegal_T_25) node _io_decode_0_virtual_access_illegal_T_27 = and(_io_decode_0_virtual_access_illegal_T_26, reg_hstatus.vtvm) node _io_decode_0_virtual_access_illegal_T_28 = or(_io_decode_0_virtual_access_illegal_T_23, _io_decode_0_virtual_access_illegal_T_27) node _io_decode_0_virtual_access_illegal_T_29 = and(_io_decode_0_virtual_access_illegal_T, _io_decode_0_virtual_access_illegal_T_28) connect io.decode[0].virtual_access_illegal, _io_decode_0_virtual_access_illegal_T_29 node _io_decode_0_virtual_system_illegal_T = or(is_hfence_vvma, is_hfence_gvma) node _io_decode_0_virtual_system_illegal_T_1 = or(_io_decode_0_virtual_system_illegal_T, is_hlsv) node _io_decode_0_virtual_system_illegal_T_2 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_3 = eq(_io_decode_0_virtual_system_illegal_T_2, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_4 = eq(reg_mstatus.tw, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_5 = and(_io_decode_0_virtual_system_illegal_T_4, reg_hstatus.vtw) node _io_decode_0_virtual_system_illegal_T_6 = or(_io_decode_0_virtual_system_illegal_T_3, _io_decode_0_virtual_system_illegal_T_5) node _io_decode_0_virtual_system_illegal_T_7 = and(is_wfi, _io_decode_0_virtual_system_illegal_T_6) node _io_decode_0_virtual_system_illegal_T_8 = or(_io_decode_0_virtual_system_illegal_T_1, _io_decode_0_virtual_system_illegal_T_7) node _io_decode_0_virtual_system_illegal_T_9 = bits(addr, 9, 8) node _io_decode_0_virtual_system_illegal_T_10 = eq(_io_decode_0_virtual_system_illegal_T_9, UInt<1>(0h1)) node _io_decode_0_virtual_system_illegal_T_11 = and(is_ret, _io_decode_0_virtual_system_illegal_T_10) node _io_decode_0_virtual_system_illegal_T_12 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_13 = eq(_io_decode_0_virtual_system_illegal_T_12, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_14 = or(_io_decode_0_virtual_system_illegal_T_13, reg_hstatus.vtsr) node _io_decode_0_virtual_system_illegal_T_15 = and(_io_decode_0_virtual_system_illegal_T_11, _io_decode_0_virtual_system_illegal_T_14) node _io_decode_0_virtual_system_illegal_T_16 = or(_io_decode_0_virtual_system_illegal_T_8, _io_decode_0_virtual_system_illegal_T_15) node _io_decode_0_virtual_system_illegal_T_17 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_18 = eq(_io_decode_0_virtual_system_illegal_T_17, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_19 = or(_io_decode_0_virtual_system_illegal_T_18, reg_hstatus.vtvm) node _io_decode_0_virtual_system_illegal_T_20 = and(is_sfence, _io_decode_0_virtual_system_illegal_T_19) node _io_decode_0_virtual_system_illegal_T_21 = or(_io_decode_0_virtual_system_illegal_T_16, _io_decode_0_virtual_system_illegal_T_20) node _io_decode_0_virtual_system_illegal_T_22 = and(reg_mstatus.v, _io_decode_0_virtual_system_illegal_T_21) connect io.decode[0].virtual_system_illegal, _io_decode_0_virtual_system_illegal_T_22 node _cause_T = bits(reg_mstatus.prv, 0, 0) node _cause_T_1 = and(_cause_T, reg_mstatus.v) node _cause_T_2 = mux(_cause_T_1, UInt<2>(0h2), reg_mstatus.prv) node _cause_T_3 = add(UInt<4>(0h8), _cause_T_2) node _cause_T_4 = tail(_cause_T_3, 1) node _cause_T_5 = mux(insn_break, UInt<2>(0h3), io.cause) node cause = mux(insn_call, _cause_T_4, _cause_T_5) node cause_lsbs = bits(cause, 7, 0) node cause_deleg_lsbs = bits(cause, 5, 0) node _causeIsDebugInt_T = bits(cause, 63, 63) node _causeIsDebugInt_T_1 = eq(cause_lsbs, UInt<4>(0he)) node causeIsDebugInt = and(_causeIsDebugInt_T, _causeIsDebugInt_T_1) node _causeIsDebugTrigger_T = bits(cause, 63, 63) node _causeIsDebugTrigger_T_1 = eq(_causeIsDebugTrigger_T, UInt<1>(0h0)) node _causeIsDebugTrigger_T_2 = eq(cause_lsbs, UInt<4>(0he)) node causeIsDebugTrigger = and(_causeIsDebugTrigger_T_1, _causeIsDebugTrigger_T_2) node _causeIsDebugBreak_T = bits(cause, 63, 63) node _causeIsDebugBreak_T_1 = eq(_causeIsDebugBreak_T, UInt<1>(0h0)) node _causeIsDebugBreak_T_2 = and(_causeIsDebugBreak_T_1, insn_break) node causeIsDebugBreak_lo = cat(reg_dcsr.ebreaks, reg_dcsr.ebreaku) node causeIsDebugBreak_hi = cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh) node _causeIsDebugBreak_T_3 = cat(causeIsDebugBreak_hi, causeIsDebugBreak_lo) node _causeIsDebugBreak_T_4 = dshr(_causeIsDebugBreak_T_3, reg_mstatus.prv) node _causeIsDebugBreak_T_5 = bits(_causeIsDebugBreak_T_4, 0, 0) node causeIsDebugBreak = and(_causeIsDebugBreak_T_2, _causeIsDebugBreak_T_5) node _trapToDebug_T = or(reg_singleStepped, causeIsDebugInt) node _trapToDebug_T_1 = or(_trapToDebug_T, causeIsDebugTrigger) node _trapToDebug_T_2 = or(_trapToDebug_T_1, causeIsDebugBreak) node _trapToDebug_T_3 = or(_trapToDebug_T_2, reg_debug) node trapToDebug = and(UInt<1>(0h1), _trapToDebug_T_3) node _debugTVec_T = mux(insn_break, UInt<12>(0h800), UInt<12>(0h808)) node debugTVec = mux(reg_debug, _debugTVec_T, UInt<12>(0h800)) node _delegate_T = leq(reg_mstatus.prv, UInt<1>(0h1)) node _delegate_T_1 = and(UInt<1>(0h1), _delegate_T) node _delegate_T_2 = bits(cause, 63, 63) node _delegate_T_3 = dshr(read_mideleg, cause_deleg_lsbs) node _delegate_T_4 = bits(_delegate_T_3, 0, 0) node _delegate_T_5 = dshr(read_medeleg, cause_deleg_lsbs) node _delegate_T_6 = bits(_delegate_T_5, 0, 0) node _delegate_T_7 = mux(_delegate_T_2, _delegate_T_4, _delegate_T_6) node delegate = and(_delegate_T_1, _delegate_T_7) node _delegateVS_T = and(reg_mstatus.v, delegate) node _delegateVS_T_1 = bits(cause, 63, 63) node _delegateVS_T_2 = dshr(read_hideleg, cause_deleg_lsbs) node _delegateVS_T_3 = bits(_delegateVS_T_2, 0, 0) node _delegateVS_T_4 = dshr(read_hedeleg, cause_deleg_lsbs) node _delegateVS_T_5 = bits(_delegateVS_T_4, 0, 0) node _delegateVS_T_6 = mux(_delegateVS_T_1, _delegateVS_T_3, _delegateVS_T_5) node delegateVS = and(_delegateVS_T, _delegateVS_T_6) node _notDebugTVec_base_T = mux(delegateVS, read_vstvec, read_stvec) node notDebugTVec_base = mux(delegate, _notDebugTVec_base_T, read_mtvec) node _notDebugTVec_interruptOffset_T = bits(cause, 5, 0) node notDebugTVec_interruptOffset = shl(_notDebugTVec_interruptOffset_T, 2) node _notDebugTVec_interruptVec_T = shr(notDebugTVec_base, 8) node notDebugTVec_interruptVec = cat(_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset) node _notDebugTVec_doVector_T = bits(notDebugTVec_base, 0, 0) node _notDebugTVec_doVector_T_1 = bits(cause, 63, 63) node _notDebugTVec_doVector_T_2 = and(_notDebugTVec_doVector_T, _notDebugTVec_doVector_T_1) node _notDebugTVec_doVector_T_3 = shr(cause_lsbs, 6) node _notDebugTVec_doVector_T_4 = eq(_notDebugTVec_doVector_T_3, UInt<1>(0h0)) node notDebugTVec_doVector = and(_notDebugTVec_doVector_T_2, _notDebugTVec_doVector_T_4) node _notDebugTVec_T = shr(notDebugTVec_base, 2) node _notDebugTVec_T_1 = shl(_notDebugTVec_T, 2) node notDebugTVec = mux(notDebugTVec_doVector, notDebugTVec_interruptVec, _notDebugTVec_T_1) node _causeIsRnmiInt_T = bits(cause, 63, 63) node _causeIsRnmiInt_T_1 = bits(cause, 62, 62) node _causeIsRnmiInt_T_2 = and(_causeIsRnmiInt_T, _causeIsRnmiInt_T_1) node _causeIsRnmiInt_T_3 = eq(cause_lsbs, UInt<4>(0hd)) node _causeIsRnmiInt_T_4 = eq(cause_lsbs, UInt<4>(0hc)) node _causeIsRnmiInt_T_5 = or(_causeIsRnmiInt_T_3, _causeIsRnmiInt_T_4) node causeIsRnmiInt = and(_causeIsRnmiInt_T_2, _causeIsRnmiInt_T_5) node _causeIsRnmiBEU_T = bits(cause, 63, 63) node _causeIsRnmiBEU_T_1 = bits(cause, 62, 62) node _causeIsRnmiBEU_T_2 = and(_causeIsRnmiBEU_T, _causeIsRnmiBEU_T_1) node _causeIsRnmiBEU_T_3 = eq(cause_lsbs, UInt<4>(0hc)) node causeIsRnmiBEU = and(_causeIsRnmiBEU_T_2, _causeIsRnmiBEU_T_3) node trapToNmiInt = and(UInt<1>(0h0), causeIsRnmiInt) node _trapToNmiXcpt_T = eq(reg_rnmie, UInt<1>(0h0)) node trapToNmiXcpt = and(UInt<1>(0h0), _trapToNmiXcpt_T) node trapToNmi = or(trapToNmiInt, trapToNmiXcpt) node _nmiTVec_T = mux(causeIsRnmiInt, UInt<1>(0h0), UInt<1>(0h0)) node _nmiTVec_T_1 = shr(_nmiTVec_T, 1) node nmiTVec = shl(_nmiTVec_T_1, 1) node _tvec_T = mux(trapToNmi, nmiTVec, notDebugTVec) node tvec = mux(trapToDebug, debugTVec, _tvec_T) connect io.evec, tvec connect io.ptbr, reg_satp connect io.hgatp, reg_hgatp connect io.vsatp, reg_vsatp node _io_eret_T = or(insn_call, insn_break) node _io_eret_T_1 = or(_io_eret_T, insn_ret) connect io.eret, _io_eret_T_1 node _io_singleStep_T = eq(reg_debug, UInt<1>(0h0)) node _io_singleStep_T_1 = and(reg_dcsr.step, _io_singleStep_T) connect io.singleStep, _io_singleStep_T_1 connect io.status, reg_mstatus node _io_status_sd_T = andr(io.status.fs) node _io_status_sd_T_1 = andr(io.status.xs) node _io_status_sd_T_2 = or(_io_status_sd_T, _io_status_sd_T_1) node _io_status_sd_T_3 = andr(io.status.vs) node _io_status_sd_T_4 = or(_io_status_sd_T_2, _io_status_sd_T_3) connect io.status.sd, _io_status_sd_T_4 connect io.status.debug, reg_debug connect io.status.isa, reg_misa connect io.status.uxl, UInt<2>(0h2) connect io.status.sxl, UInt<2>(0h2) node _io_status_dprv_T = eq(reg_debug, UInt<1>(0h0)) node _io_status_dprv_T_1 = and(reg_mstatus.mprv, _io_status_dprv_T) node _io_status_dprv_T_2 = mux(_io_status_dprv_T_1, reg_mstatus.mpp, reg_mstatus.prv) connect io.status.dprv, _io_status_dprv_T_2 node _io_status_dv_T = eq(reg_debug, UInt<1>(0h0)) node _io_status_dv_T_1 = and(reg_mstatus.mprv, _io_status_dv_T) node _io_status_dv_T_2 = mux(_io_status_dv_T_1, reg_mstatus.mpv, UInt<1>(0h0)) node _io_status_dv_T_3 = or(reg_mstatus.v, _io_status_dv_T_2) connect io.status.dv, _io_status_dv_T_3 node _io_status_sd_rv32_T = and(UInt<1>(0h0), io.status.sd) connect io.status.sd_rv32, _io_status_sd_rv32_T connect io.status.mpv, reg_mstatus.mpv connect io.status.gva, reg_mstatus.gva connect io.hstatus, reg_hstatus connect io.hstatus.vsxl, UInt<2>(0h2) connect io.gstatus, reg_vsstatus node _io_gstatus_sd_T = andr(io.gstatus.fs) node _io_gstatus_sd_T_1 = andr(io.gstatus.xs) node _io_gstatus_sd_T_2 = or(_io_gstatus_sd_T, _io_gstatus_sd_T_1) node _io_gstatus_sd_T_3 = andr(io.gstatus.vs) node _io_gstatus_sd_T_4 = or(_io_gstatus_sd_T_2, _io_gstatus_sd_T_3) connect io.gstatus.sd, _io_gstatus_sd_T_4 connect io.gstatus.uxl, UInt<2>(0h2) node _io_gstatus_sd_rv32_T = and(UInt<1>(0h0), io.gstatus.sd) connect io.gstatus.sd_rv32, _io_gstatus_sd_rv32_T node _exception_T = or(insn_call, insn_break) node exception = or(_exception_T, io.exception) node _T_86 = add(insn_ret, insn_call) node _T_87 = bits(_T_86, 1, 0) node _T_88 = add(insn_break, io.exception) node _T_89 = bits(_T_88, 1, 0) node _T_90 = add(_T_87, _T_89) node _T_91 = bits(_T_90, 2, 0) node _T_92 = leq(_T_91, UInt<1>(0h1)) node _T_93 = asUInt(reset) node _T_94 = eq(_T_93, UInt<1>(0h0)) when _T_94 : node _T_95 = eq(_T_92, UInt<1>(0h0)) when _T_95 : printf(clock, UInt<1>(0h1), "Assertion failed: these conditions must be mutually exclusive\n at CSR.scala:1021 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, \"these conditions must be mutually exclusive\")\n") : printf assert(clock, _T_92, UInt<1>(0h1), "") : assert node _T_96 = eq(io.singleStep, UInt<1>(0h0)) node _T_97 = and(insn_wfi, _T_96) node _T_98 = eq(reg_debug, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) when _T_99 : connect reg_wfi, UInt<1>(0h1) node _T_100 = orr(pending_interrupts) node _T_101 = or(_T_100, io.interrupts.debug) node _T_102 = or(_T_101, exception) when _T_102 : connect reg_wfi, UInt<1>(0h0) node _T_103 = bits(io.retire, 0, 0) node _T_104 = or(_T_103, exception) when _T_104 : connect reg_singleStepped, UInt<1>(0h1) node _T_105 = eq(io.singleStep, UInt<1>(0h0)) when _T_105 : connect reg_singleStepped, UInt<1>(0h0) node _T_106 = eq(io.singleStep, UInt<1>(0h0)) node _T_107 = leq(io.retire, UInt<1>(0h1)) node _T_108 = or(_T_106, _T_107) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1029 assert(!io.singleStep || io.retire <= 1.U)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(reg_singleStepped, UInt<1>(0h0)) node _T_113 = eq(io.retire, UInt<1>(0h0)) node _T_114 = or(_T_112, _T_113) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1030 assert(!reg_singleStepped || io.retire === 0.U)\n") : printf_2 assert(clock, _T_114, UInt<1>(0h1), "") : assert_2 node _epc_T = not(io.pc) node _epc_T_1 = or(_epc_T, UInt<1>(0h1)) node epc = not(_epc_T_1) node tval = mux(insn_break, epc, io.tval) when exception : when trapToDebug : node _T_118 = eq(reg_debug, UInt<1>(0h0)) when _T_118 : connect reg_mstatus.v, UInt<1>(0h0) connect reg_debug, UInt<1>(0h1) connect reg_dpc, epc node _reg_dcsr_cause_T = mux(causeIsDebugTrigger, UInt<2>(0h2), UInt<1>(0h1)) node _reg_dcsr_cause_T_1 = mux(causeIsDebugInt, UInt<2>(0h3), _reg_dcsr_cause_T) node _reg_dcsr_cause_T_2 = mux(reg_singleStepped, UInt<3>(0h4), _reg_dcsr_cause_T_1) connect reg_dcsr.cause, _reg_dcsr_cause_T_2 connect reg_dcsr.prv, reg_mstatus.prv connect reg_dcsr.v, reg_mstatus.v connect new_prv, UInt<2>(0h3) else : when trapToNmiInt : when reg_rnmie : connect reg_mstatus.v, UInt<1>(0h0) connect reg_mnstatus.mpv, reg_mstatus.v connect reg_rnmie, UInt<1>(0h0) connect reg_mnepc, epc node _reg_mncause_T = mux(causeIsRnmiBEU, UInt<2>(0h3), UInt<2>(0h2)) node _reg_mncause_T_1 = or(UInt<64>(0h8000000000000000), _reg_mncause_T) connect reg_mncause, _reg_mncause_T_1 connect reg_mnstatus.mpp, reg_mstatus.prv connect new_prv, UInt<2>(0h3) else : node _T_119 = and(delegateVS, reg_rnmie) when _T_119 : connect reg_mstatus.v, UInt<1>(0h1) connect reg_vsstatus.spp, reg_mstatus.prv connect reg_vsepc, epc node _reg_vscause_T = bits(cause, 63, 63) node _reg_vscause_T_1 = bits(cause, 63, 2) node _reg_vscause_T_2 = cat(_reg_vscause_T_1, UInt<2>(0h1)) node _reg_vscause_T_3 = mux(_reg_vscause_T, _reg_vscause_T_2, cause) connect reg_vscause, _reg_vscause_T_3 connect reg_vstval, tval connect reg_vsstatus.spie, reg_vsstatus.sie connect reg_vsstatus.sie, UInt<1>(0h0) connect new_prv, UInt<1>(0h1) else : node _T_120 = and(delegate, reg_rnmie) when _T_120 : connect reg_mstatus.v, UInt<1>(0h0) node _reg_hstatus_spvp_T = bits(reg_mstatus.prv, 0, 0) node _reg_hstatus_spvp_T_1 = mux(reg_mstatus.v, _reg_hstatus_spvp_T, reg_hstatus.spvp) connect reg_hstatus.spvp, _reg_hstatus_spvp_T_1 connect reg_hstatus.gva, io.gva connect reg_hstatus.spv, reg_mstatus.v connect reg_sepc, epc connect reg_scause, cause connect reg_stval, tval connect reg_htval, io.htval connect reg_htinst_read_pseudo, io.mhtinst_read_pseudo connect reg_mstatus.spie, reg_mstatus.sie connect reg_mstatus.spp, reg_mstatus.prv connect reg_mstatus.sie, UInt<1>(0h0) connect new_prv, UInt<1>(0h1) else : connect reg_mstatus.v, UInt<1>(0h0) connect reg_mstatus.mpv, reg_mstatus.v connect reg_mstatus.gva, io.gva connect reg_mepc, epc connect reg_mcause, cause connect reg_mtval, tval connect reg_mtval2, io.htval connect reg_mtinst_read_pseudo, io.mhtinst_read_pseudo connect reg_mstatus.mpie, reg_mstatus.mie connect reg_mstatus.mpp, reg_mstatus.prv connect reg_mstatus.mie, UInt<1>(0h0) connect new_prv, UInt<2>(0h3) node _en_T = and(supported_interrupts, UInt<1>(0h1)) node _en_T_1 = neq(_en_T, UInt<1>(0h0)) node _en_T_2 = and(exception, _en_T_1) node _en_T_3 = add(UInt<64>(0h8000000000000000), UInt<1>(0h0)) node _en_T_4 = tail(_en_T_3, 1) node _en_T_5 = eq(cause, _en_T_4) node en = and(_en_T_2, _en_T_5) node _delegable_T = and(delegable_interrupts, UInt<1>(0h1)) node delegable = neq(_delegable_T, UInt<1>(0h0)) node _T_121 = eq(delegate, UInt<1>(0h0)) node _T_122 = and(en, _T_121) node _T_123 = and(en, delegable) node _T_124 = and(_T_123, delegate) node _en_T_6 = and(supported_interrupts, UInt<2>(0h2)) node _en_T_7 = neq(_en_T_6, UInt<1>(0h0)) node _en_T_8 = and(exception, _en_T_7) node _en_T_9 = add(UInt<64>(0h8000000000000000), UInt<1>(0h1)) node _en_T_10 = tail(_en_T_9, 1) node _en_T_11 = eq(cause, _en_T_10) node en_1 = and(_en_T_8, _en_T_11) node _delegable_T_1 = and(delegable_interrupts, UInt<2>(0h2)) node delegable_1 = neq(_delegable_T_1, UInt<1>(0h0)) node _T_125 = eq(delegate, UInt<1>(0h0)) node _T_126 = and(en_1, _T_125) node _T_127 = and(en_1, delegable_1) node _T_128 = and(_T_127, delegate) node _en_T_12 = and(supported_interrupts, UInt<3>(0h4)) node _en_T_13 = neq(_en_T_12, UInt<1>(0h0)) node _en_T_14 = and(exception, _en_T_13) node _en_T_15 = add(UInt<64>(0h8000000000000000), UInt<2>(0h2)) node _en_T_16 = tail(_en_T_15, 1) node _en_T_17 = eq(cause, _en_T_16) node en_2 = and(_en_T_14, _en_T_17) node _delegable_T_2 = and(delegable_interrupts, UInt<3>(0h4)) node delegable_2 = neq(_delegable_T_2, UInt<1>(0h0)) node _T_129 = eq(delegate, UInt<1>(0h0)) node _T_130 = and(en_2, _T_129) node _T_131 = and(en_2, delegable_2) node _T_132 = and(_T_131, delegate) node _en_T_18 = and(supported_interrupts, UInt<4>(0h8)) node _en_T_19 = neq(_en_T_18, UInt<1>(0h0)) node _en_T_20 = and(exception, _en_T_19) node _en_T_21 = add(UInt<64>(0h8000000000000000), UInt<2>(0h3)) node _en_T_22 = tail(_en_T_21, 1) node _en_T_23 = eq(cause, _en_T_22) node en_3 = and(_en_T_20, _en_T_23) node _delegable_T_3 = and(delegable_interrupts, UInt<4>(0h8)) node delegable_3 = neq(_delegable_T_3, UInt<1>(0h0)) node _T_133 = eq(delegate, UInt<1>(0h0)) node _T_134 = and(en_3, _T_133) node _T_135 = and(en_3, delegable_3) node _T_136 = and(_T_135, delegate) node _en_T_24 = and(supported_interrupts, UInt<5>(0h10)) node _en_T_25 = neq(_en_T_24, UInt<1>(0h0)) node _en_T_26 = and(exception, _en_T_25) node _en_T_27 = add(UInt<64>(0h8000000000000000), UInt<3>(0h4)) node _en_T_28 = tail(_en_T_27, 1) node _en_T_29 = eq(cause, _en_T_28) node en_4 = and(_en_T_26, _en_T_29) node _delegable_T_4 = and(delegable_interrupts, UInt<5>(0h10)) node delegable_4 = neq(_delegable_T_4, UInt<1>(0h0)) node _T_137 = eq(delegate, UInt<1>(0h0)) node _T_138 = and(en_4, _T_137) node _T_139 = and(en_4, delegable_4) node _T_140 = and(_T_139, delegate) node _en_T_30 = and(supported_interrupts, UInt<6>(0h20)) node _en_T_31 = neq(_en_T_30, UInt<1>(0h0)) node _en_T_32 = and(exception, _en_T_31) node _en_T_33 = add(UInt<64>(0h8000000000000000), UInt<3>(0h5)) node _en_T_34 = tail(_en_T_33, 1) node _en_T_35 = eq(cause, _en_T_34) node en_5 = and(_en_T_32, _en_T_35) node _delegable_T_5 = and(delegable_interrupts, UInt<6>(0h20)) node delegable_5 = neq(_delegable_T_5, UInt<1>(0h0)) node _T_141 = eq(delegate, UInt<1>(0h0)) node _T_142 = and(en_5, _T_141) node _T_143 = and(en_5, delegable_5) node _T_144 = and(_T_143, delegate) node _en_T_36 = and(supported_interrupts, UInt<7>(0h40)) node _en_T_37 = neq(_en_T_36, UInt<1>(0h0)) node _en_T_38 = and(exception, _en_T_37) node _en_T_39 = add(UInt<64>(0h8000000000000000), UInt<3>(0h6)) node _en_T_40 = tail(_en_T_39, 1) node _en_T_41 = eq(cause, _en_T_40) node en_6 = and(_en_T_38, _en_T_41) node _delegable_T_6 = and(delegable_interrupts, UInt<7>(0h40)) node delegable_6 = neq(_delegable_T_6, UInt<1>(0h0)) node _T_145 = eq(delegate, UInt<1>(0h0)) node _T_146 = and(en_6, _T_145) node _T_147 = and(en_6, delegable_6) node _T_148 = and(_T_147, delegate) node _en_T_42 = and(supported_interrupts, UInt<8>(0h80)) node _en_T_43 = neq(_en_T_42, UInt<1>(0h0)) node _en_T_44 = and(exception, _en_T_43) node _en_T_45 = add(UInt<64>(0h8000000000000000), UInt<3>(0h7)) node _en_T_46 = tail(_en_T_45, 1) node _en_T_47 = eq(cause, _en_T_46) node en_7 = and(_en_T_44, _en_T_47) node _delegable_T_7 = and(delegable_interrupts, UInt<8>(0h80)) node delegable_7 = neq(_delegable_T_7, UInt<1>(0h0)) node _T_149 = eq(delegate, UInt<1>(0h0)) node _T_150 = and(en_7, _T_149) node _T_151 = and(en_7, delegable_7) node _T_152 = and(_T_151, delegate) node _en_T_48 = and(supported_interrupts, UInt<9>(0h100)) node _en_T_49 = neq(_en_T_48, UInt<1>(0h0)) node _en_T_50 = and(exception, _en_T_49) node _en_T_51 = add(UInt<64>(0h8000000000000000), UInt<4>(0h8)) node _en_T_52 = tail(_en_T_51, 1) node _en_T_53 = eq(cause, _en_T_52) node en_8 = and(_en_T_50, _en_T_53) node _delegable_T_8 = and(delegable_interrupts, UInt<9>(0h100)) node delegable_8 = neq(_delegable_T_8, UInt<1>(0h0)) node _T_153 = eq(delegate, UInt<1>(0h0)) node _T_154 = and(en_8, _T_153) node _T_155 = and(en_8, delegable_8) node _T_156 = and(_T_155, delegate) node _en_T_54 = and(supported_interrupts, UInt<10>(0h200)) node _en_T_55 = neq(_en_T_54, UInt<1>(0h0)) node _en_T_56 = and(exception, _en_T_55) node _en_T_57 = add(UInt<64>(0h8000000000000000), UInt<4>(0h9)) node _en_T_58 = tail(_en_T_57, 1) node _en_T_59 = eq(cause, _en_T_58) node en_9 = and(_en_T_56, _en_T_59) node _delegable_T_9 = and(delegable_interrupts, UInt<10>(0h200)) node delegable_9 = neq(_delegable_T_9, UInt<1>(0h0)) node _T_157 = eq(delegate, UInt<1>(0h0)) node _T_158 = and(en_9, _T_157) node _T_159 = and(en_9, delegable_9) node _T_160 = and(_T_159, delegate) node _en_T_60 = and(supported_interrupts, UInt<11>(0h400)) node _en_T_61 = neq(_en_T_60, UInt<1>(0h0)) node _en_T_62 = and(exception, _en_T_61) node _en_T_63 = add(UInt<64>(0h8000000000000000), UInt<4>(0ha)) node _en_T_64 = tail(_en_T_63, 1) node _en_T_65 = eq(cause, _en_T_64) node en_10 = and(_en_T_62, _en_T_65) node _delegable_T_10 = and(delegable_interrupts, UInt<11>(0h400)) node delegable_10 = neq(_delegable_T_10, UInt<1>(0h0)) node _T_161 = eq(delegate, UInt<1>(0h0)) node _T_162 = and(en_10, _T_161) node _T_163 = and(en_10, delegable_10) node _T_164 = and(_T_163, delegate) node _en_T_66 = and(supported_interrupts, UInt<12>(0h800)) node _en_T_67 = neq(_en_T_66, UInt<1>(0h0)) node _en_T_68 = and(exception, _en_T_67) node _en_T_69 = add(UInt<64>(0h8000000000000000), UInt<4>(0hb)) node _en_T_70 = tail(_en_T_69, 1) node _en_T_71 = eq(cause, _en_T_70) node en_11 = and(_en_T_68, _en_T_71) node _delegable_T_11 = and(delegable_interrupts, UInt<12>(0h800)) node delegable_11 = neq(_delegable_T_11, UInt<1>(0h0)) node _T_165 = eq(delegate, UInt<1>(0h0)) node _T_166 = and(en_11, _T_165) node _T_167 = and(en_11, delegable_11) node _T_168 = and(_T_167, delegate) node _en_T_72 = and(supported_interrupts, UInt<13>(0h1000)) node _en_T_73 = neq(_en_T_72, UInt<1>(0h0)) node _en_T_74 = and(exception, _en_T_73) node _en_T_75 = add(UInt<64>(0h8000000000000000), UInt<4>(0hc)) node _en_T_76 = tail(_en_T_75, 1) node _en_T_77 = eq(cause, _en_T_76) node en_12 = and(_en_T_74, _en_T_77) node _delegable_T_12 = and(delegable_interrupts, UInt<13>(0h1000)) node delegable_12 = neq(_delegable_T_12, UInt<1>(0h0)) node _T_169 = eq(delegate, UInt<1>(0h0)) node _T_170 = and(en_12, _T_169) node _T_171 = and(en_12, delegable_12) node _T_172 = and(_T_171, delegate) node _en_T_78 = and(supported_interrupts, UInt<14>(0h2000)) node _en_T_79 = neq(_en_T_78, UInt<1>(0h0)) node _en_T_80 = and(exception, _en_T_79) node _en_T_81 = add(UInt<64>(0h8000000000000000), UInt<4>(0hd)) node _en_T_82 = tail(_en_T_81, 1) node _en_T_83 = eq(cause, _en_T_82) node en_13 = and(_en_T_80, _en_T_83) node _delegable_T_13 = and(delegable_interrupts, UInt<14>(0h2000)) node delegable_13 = neq(_delegable_T_13, UInt<1>(0h0)) node _T_173 = eq(delegate, UInt<1>(0h0)) node _T_174 = and(en_13, _T_173) node _T_175 = and(en_13, delegable_13) node _T_176 = and(_T_175, delegate) node _en_T_84 = and(supported_interrupts, UInt<15>(0h4000)) node _en_T_85 = neq(_en_T_84, UInt<1>(0h0)) node _en_T_86 = and(exception, _en_T_85) node _en_T_87 = add(UInt<64>(0h8000000000000000), UInt<4>(0he)) node _en_T_88 = tail(_en_T_87, 1) node _en_T_89 = eq(cause, _en_T_88) node en_14 = and(_en_T_86, _en_T_89) node _delegable_T_14 = and(delegable_interrupts, UInt<15>(0h4000)) node delegable_14 = neq(_delegable_T_14, UInt<1>(0h0)) node _T_177 = eq(delegate, UInt<1>(0h0)) node _T_178 = and(en_14, _T_177) node _T_179 = and(en_14, delegable_14) node _T_180 = and(_T_179, delegate) node _en_T_90 = and(supported_interrupts, UInt<16>(0h8000)) node _en_T_91 = neq(_en_T_90, UInt<1>(0h0)) node _en_T_92 = and(exception, _en_T_91) node _en_T_93 = add(UInt<64>(0h8000000000000000), UInt<4>(0hf)) node _en_T_94 = tail(_en_T_93, 1) node _en_T_95 = eq(cause, _en_T_94) node en_15 = and(_en_T_92, _en_T_95) node _delegable_T_15 = and(delegable_interrupts, UInt<16>(0h8000)) node delegable_15 = neq(_delegable_T_15, UInt<1>(0h0)) node _T_181 = eq(delegate, UInt<1>(0h0)) node _T_182 = and(en_15, _T_181) node _T_183 = and(en_15, delegable_15) node _T_184 = and(_T_183, delegate) node _en_T_96 = eq(cause, UInt<1>(0h0)) node en_16 = and(exception, _en_T_96) node _delegable_T_16 = and(UInt<16>(0hb15d), UInt<1>(0h1)) node delegable_16 = neq(_delegable_T_16, UInt<1>(0h0)) node _T_185 = eq(delegate, UInt<1>(0h0)) node _T_186 = and(en_16, _T_185) node _T_187 = and(en_16, delegable_16) node _T_188 = and(_T_187, delegate) node _en_T_97 = eq(cause, UInt<1>(0h1)) node en_17 = and(exception, _en_T_97) node _delegable_T_17 = and(UInt<16>(0hb15d), UInt<2>(0h2)) node delegable_17 = neq(_delegable_T_17, UInt<1>(0h0)) node _T_189 = eq(delegate, UInt<1>(0h0)) node _T_190 = and(en_17, _T_189) node _T_191 = and(en_17, delegable_17) node _T_192 = and(_T_191, delegate) node _en_T_98 = eq(cause, UInt<2>(0h2)) node en_18 = and(exception, _en_T_98) node _delegable_T_18 = and(UInt<16>(0hb15d), UInt<3>(0h4)) node delegable_18 = neq(_delegable_T_18, UInt<1>(0h0)) node _T_193 = eq(delegate, UInt<1>(0h0)) node _T_194 = and(en_18, _T_193) node _T_195 = and(en_18, delegable_18) node _T_196 = and(_T_195, delegate) node _en_T_99 = eq(cause, UInt<2>(0h3)) node en_19 = and(exception, _en_T_99) node _delegable_T_19 = and(UInt<16>(0hb15d), UInt<4>(0h8)) node delegable_19 = neq(_delegable_T_19, UInt<1>(0h0)) node _T_197 = eq(delegate, UInt<1>(0h0)) node _T_198 = and(en_19, _T_197) node _T_199 = and(en_19, delegable_19) node _T_200 = and(_T_199, delegate) node _en_T_100 = eq(cause, UInt<3>(0h4)) node en_20 = and(exception, _en_T_100) node _delegable_T_20 = and(UInt<16>(0hb15d), UInt<5>(0h10)) node delegable_20 = neq(_delegable_T_20, UInt<1>(0h0)) node _T_201 = eq(delegate, UInt<1>(0h0)) node _T_202 = and(en_20, _T_201) node _T_203 = and(en_20, delegable_20) node _T_204 = and(_T_203, delegate) node _en_T_101 = eq(cause, UInt<3>(0h5)) node en_21 = and(exception, _en_T_101) node _delegable_T_21 = and(UInt<16>(0hb15d), UInt<6>(0h20)) node delegable_21 = neq(_delegable_T_21, UInt<1>(0h0)) node _T_205 = eq(delegate, UInt<1>(0h0)) node _T_206 = and(en_21, _T_205) node _T_207 = and(en_21, delegable_21) node _T_208 = and(_T_207, delegate) node _en_T_102 = eq(cause, UInt<3>(0h6)) node en_22 = and(exception, _en_T_102) node _delegable_T_22 = and(UInt<16>(0hb15d), UInt<7>(0h40)) node delegable_22 = neq(_delegable_T_22, UInt<1>(0h0)) node _T_209 = eq(delegate, UInt<1>(0h0)) node _T_210 = and(en_22, _T_209) node _T_211 = and(en_22, delegable_22) node _T_212 = and(_T_211, delegate) node _en_T_103 = eq(cause, UInt<3>(0h7)) node en_23 = and(exception, _en_T_103) node _delegable_T_23 = and(UInt<16>(0hb15d), UInt<8>(0h80)) node delegable_23 = neq(_delegable_T_23, UInt<1>(0h0)) node _T_213 = eq(delegate, UInt<1>(0h0)) node _T_214 = and(en_23, _T_213) node _T_215 = and(en_23, delegable_23) node _T_216 = and(_T_215, delegate) node _en_T_104 = eq(cause, UInt<4>(0h8)) node en_24 = and(exception, _en_T_104) node _delegable_T_24 = and(UInt<16>(0hb15d), UInt<9>(0h100)) node delegable_24 = neq(_delegable_T_24, UInt<1>(0h0)) node _T_217 = eq(delegate, UInt<1>(0h0)) node _T_218 = and(en_24, _T_217) node _T_219 = and(en_24, delegable_24) node _T_220 = and(_T_219, delegate) node _en_T_105 = eq(cause, UInt<4>(0h9)) node en_25 = and(exception, _en_T_105) node _delegable_T_25 = and(UInt<16>(0hb15d), UInt<10>(0h200)) node delegable_25 = neq(_delegable_T_25, UInt<1>(0h0)) node _T_221 = eq(delegate, UInt<1>(0h0)) node _T_222 = and(en_25, _T_221) node _T_223 = and(en_25, delegable_25) node _T_224 = and(_T_223, delegate) node _en_T_106 = eq(cause, UInt<4>(0hb)) node en_26 = and(exception, _en_T_106) node _delegable_T_26 = and(UInt<16>(0hb15d), UInt<12>(0h800)) node delegable_26 = neq(_delegable_T_26, UInt<1>(0h0)) node _T_225 = eq(delegate, UInt<1>(0h0)) node _T_226 = and(en_26, _T_225) node _T_227 = and(en_26, delegable_26) node _T_228 = and(_T_227, delegate) node _en_T_107 = eq(cause, UInt<4>(0hc)) node en_27 = and(exception, _en_T_107) node _delegable_T_27 = and(UInt<16>(0hb15d), UInt<13>(0h1000)) node delegable_27 = neq(_delegable_T_27, UInt<1>(0h0)) node _T_229 = eq(delegate, UInt<1>(0h0)) node _T_230 = and(en_27, _T_229) node _T_231 = and(en_27, delegable_27) node _T_232 = and(_T_231, delegate) node _en_T_108 = eq(cause, UInt<4>(0hd)) node en_28 = and(exception, _en_T_108) node _delegable_T_28 = and(UInt<16>(0hb15d), UInt<14>(0h2000)) node delegable_28 = neq(_delegable_T_28, UInt<1>(0h0)) node _T_233 = eq(delegate, UInt<1>(0h0)) node _T_234 = and(en_28, _T_233) node _T_235 = and(en_28, delegable_28) node _T_236 = and(_T_235, delegate) node _en_T_109 = eq(cause, UInt<4>(0hf)) node en_29 = and(exception, _en_T_109) node _delegable_T_29 = and(UInt<16>(0hb15d), UInt<16>(0h8000)) node delegable_29 = neq(_delegable_T_29, UInt<1>(0h0)) node _T_237 = eq(delegate, UInt<1>(0h0)) node _T_238 = and(en_29, _T_237) node _T_239 = and(en_29, delegable_29) node _T_240 = and(_T_239, delegate) when insn_ret : wire ret_prv : UInt invalidate ret_prv node _T_241 = bits(io.rw.addr, 9, 9) node _T_242 = eq(_T_241, UInt<1>(0h0)) node _T_243 = and(UInt<1>(0h1), _T_242) when _T_243 : node _T_244 = eq(reg_mstatus.v, UInt<1>(0h0)) when _T_244 : connect reg_mstatus.sie, reg_mstatus.spie connect reg_mstatus.spie, UInt<1>(0h1) connect reg_mstatus.spp, UInt<1>(0h0) connect ret_prv, reg_mstatus.spp node _reg_mstatus_v_T = and(UInt<1>(0h0), reg_hstatus.spv) connect reg_mstatus.v, _reg_mstatus_v_T node _io_evec_T = not(reg_sepc) node _io_evec_T_1 = bits(reg_misa, 2, 2) node _io_evec_T_2 = mux(_io_evec_T_1, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_3 = or(_io_evec_T, _io_evec_T_2) node _io_evec_T_4 = not(_io_evec_T_3) connect io.evec, _io_evec_T_4 connect reg_hstatus.spv, UInt<1>(0h0) else : connect reg_vsstatus.sie, reg_vsstatus.spie connect reg_vsstatus.spie, UInt<1>(0h1) connect reg_vsstatus.spp, UInt<1>(0h0) connect ret_prv, reg_vsstatus.spp connect reg_mstatus.v, UInt<1>(0h0) node _io_evec_T_5 = not(reg_vsepc) node _io_evec_T_6 = bits(reg_misa, 2, 2) node _io_evec_T_7 = mux(_io_evec_T_6, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_8 = or(_io_evec_T_5, _io_evec_T_7) node _io_evec_T_9 = not(_io_evec_T_8) connect io.evec, _io_evec_T_9 else : node _T_245 = bits(io.rw.addr, 10, 10) node _T_246 = and(UInt<1>(0h1), _T_245) node _T_247 = bits(io.rw.addr, 7, 7) node _T_248 = and(_T_246, _T_247) when _T_248 : connect ret_prv, reg_dcsr.prv node _reg_mstatus_v_T_1 = and(UInt<1>(0h0), reg_dcsr.v) node _reg_mstatus_v_T_2 = leq(reg_dcsr.prv, UInt<1>(0h1)) node _reg_mstatus_v_T_3 = and(_reg_mstatus_v_T_1, _reg_mstatus_v_T_2) connect reg_mstatus.v, _reg_mstatus_v_T_3 connect reg_debug, UInt<1>(0h0) node _io_evec_T_10 = not(reg_dpc) node _io_evec_T_11 = bits(reg_misa, 2, 2) node _io_evec_T_12 = mux(_io_evec_T_11, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_13 = or(_io_evec_T_10, _io_evec_T_12) node _io_evec_T_14 = not(_io_evec_T_13) connect io.evec, _io_evec_T_14 else : node _T_249 = bits(io.rw.addr, 10, 10) node _T_250 = and(UInt<1>(0h0), _T_249) node _T_251 = bits(io.rw.addr, 7, 7) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = and(_T_250, _T_252) when _T_253 : connect ret_prv, reg_mnstatus.mpp node _reg_mstatus_v_T_4 = and(UInt<1>(0h0), reg_mnstatus.mpv) node _reg_mstatus_v_T_5 = leq(reg_mnstatus.mpp, UInt<1>(0h1)) node _reg_mstatus_v_T_6 = and(_reg_mstatus_v_T_4, _reg_mstatus_v_T_5) connect reg_mstatus.v, _reg_mstatus_v_T_6 connect reg_rnmie, UInt<1>(0h1) node _io_evec_T_15 = not(reg_mnepc) node _io_evec_T_16 = bits(reg_misa, 2, 2) node _io_evec_T_17 = mux(_io_evec_T_16, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_18 = or(_io_evec_T_15, _io_evec_T_17) node _io_evec_T_19 = not(_io_evec_T_18) connect io.evec, _io_evec_T_19 else : connect reg_mstatus.mie, reg_mstatus.mpie connect reg_mstatus.mpie, UInt<1>(0h1) node _reg_mstatus_mpp_T = eq(UInt<1>(0h0), UInt<2>(0h2)) node _reg_mstatus_mpp_T_1 = mux(_reg_mstatus_mpp_T, UInt<1>(0h0), UInt<1>(0h0)) connect reg_mstatus.mpp, _reg_mstatus_mpp_T_1 connect reg_mstatus.mpv, UInt<1>(0h0) connect ret_prv, reg_mstatus.mpp node _reg_mstatus_v_T_7 = and(UInt<1>(0h0), reg_mstatus.mpv) node _reg_mstatus_v_T_8 = leq(reg_mstatus.mpp, UInt<1>(0h1)) node _reg_mstatus_v_T_9 = and(_reg_mstatus_v_T_7, _reg_mstatus_v_T_8) connect reg_mstatus.v, _reg_mstatus_v_T_9 node _io_evec_T_20 = not(reg_mepc) node _io_evec_T_21 = bits(reg_misa, 2, 2) node _io_evec_T_22 = mux(_io_evec_T_21, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_23 = or(_io_evec_T_20, _io_evec_T_22) node _io_evec_T_24 = not(_io_evec_T_23) connect io.evec, _io_evec_T_24 connect new_prv, ret_prv node _T_254 = leq(ret_prv, UInt<1>(0h1)) node _T_255 = and(UInt<1>(0h1), _T_254) when _T_255 : connect reg_mstatus.mprv, UInt<1>(0h0) connect io.time, value_1 node _io_csr_stall_T = or(reg_wfi, io.status.cease) connect io.csr_stall, _io_csr_stall_T regreset io_status_cease_r : UInt<1>, clock, reset, UInt<1>(0h0) when insn_cease : connect io_status_cease_r, UInt<1>(0h1) connect io.status.cease, io_status_cease_r connect io.status.wfi, reg_wfi connect io.customCSRs[0].wen, UInt<1>(0h0) connect io.customCSRs[0].wdata, wdata connect io.customCSRs[0].value, reg_custom_0 connect io.customCSRs[1].wen, UInt<1>(0h0) connect io.customCSRs[1].wdata, wdata connect io.customCSRs[1].value, reg_custom_1 connect io.customCSRs[2].wen, UInt<1>(0h0) connect io.customCSRs[2].wdata, wdata connect io.customCSRs[2].value, reg_custom_2 connect io.customCSRs[3].wen, UInt<1>(0h0) connect io.customCSRs[3].wdata, wdata connect io.customCSRs[3].value, reg_custom_3 node _io_rw_rdata_T = mux(decoded_addr_97_2, reg_tselect, UInt<1>(0h0)) node _io_rw_rdata_T_1 = mux(decoded_addr_55_2, read_mapping_1_2, UInt<1>(0h0)) node _io_rw_rdata_T_2 = mux(decoded_addr_10_2, read_mapping_2_2, UInt<1>(0h0)) node _io_rw_rdata_T_3 = mux(decoded_addr_118_2, read_mapping_3_2, UInt<1>(0h0)) node _io_rw_rdata_T_4 = mux(decoded_addr_94_2, reg_misa, UInt<1>(0h0)) node _io_rw_rdata_T_5 = mux(decoded_addr_100_2, read_mstatus, UInt<1>(0h0)) node _io_rw_rdata_T_6 = mux(decoded_addr_72_2, read_mtvec, UInt<1>(0h0)) node _io_rw_rdata_T_7 = mux(decoded_addr_108_2, read_mip, UInt<1>(0h0)) node _io_rw_rdata_T_8 = mux(decoded_addr_76_2, reg_mie, UInt<1>(0h0)) node _io_rw_rdata_T_9 = mux(decoded_addr_129_2, reg_mscratch, UInt<1>(0h0)) node _io_rw_rdata_T_10 = mux(decoded_addr_132_2, read_mapping_10_2, UInt<1>(0h0)) node _io_rw_rdata_T_11 = mux(decoded_addr_136_2, read_mapping_11_2, UInt<1>(0h0)) node _io_rw_rdata_T_12 = mux(decoded_addr_29_2, reg_mcause, UInt<1>(0h0)) node _io_rw_rdata_T_13 = mux(decoded_addr_131_2, io.hartid, UInt<1>(0h0)) node _io_rw_rdata_T_14 = mux(decoded_addr_49_2, debug_csrs_0_2, UInt<1>(0h0)) node _io_rw_rdata_T_15 = mux(decoded_addr_89_2, debug_csrs_1_2, UInt<1>(0h0)) node _io_rw_rdata_T_16 = mux(decoded_addr_57_2, reg_dscratch0, UInt<1>(0h0)) node _io_rw_rdata_T_17 = mux(decoded_addr_36_2, reg_fflags, UInt<1>(0h0)) node _io_rw_rdata_T_18 = mux(decoded_addr_68_2, reg_frm, UInt<1>(0h0)) node _io_rw_rdata_T_19 = mux(decoded_addr_99_2, read_fcsr, UInt<1>(0h0)) node _io_rw_rdata_T_20 = mux(decoded_addr_130_2, reg_mcountinhibit, UInt<1>(0h0)) node _io_rw_rdata_T_21 = mux(decoded_addr_103_2, value_1, UInt<1>(0h0)) node _io_rw_rdata_T_22 = mux(decoded_addr_121_2, value, UInt<1>(0h0)) node _io_rw_rdata_T_23 = mux(decoded_addr_146_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_24 = mux(decoded_addr_17_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_25 = mux(decoded_addr_27_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_26 = mux(decoded_addr_83_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_27 = mux(decoded_addr_52_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_28 = mux(decoded_addr_144_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_29 = mux(decoded_addr_70_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_30 = mux(decoded_addr_111_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_31 = mux(decoded_addr_82_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_32 = mux(decoded_addr_31_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_33 = mux(decoded_addr_0_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_34 = mux(decoded_addr_59_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_35 = mux(decoded_addr_138_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_36 = mux(decoded_addr_126_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_37 = mux(decoded_addr_74_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_38 = mux(decoded_addr_116_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_39 = mux(decoded_addr_90_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_40 = mux(decoded_addr_113_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_41 = mux(decoded_addr_1_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_42 = mux(decoded_addr_16_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_43 = mux(decoded_addr_78_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_44 = mux(decoded_addr_39_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_45 = mux(decoded_addr_51_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_46 = mux(decoded_addr_109_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_47 = mux(decoded_addr_91_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_48 = mux(decoded_addr_81_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_49 = mux(decoded_addr_67_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_50 = mux(decoded_addr_105_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_51 = mux(decoded_addr_122_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_52 = mux(decoded_addr_24_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_53 = mux(decoded_addr_124_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_54 = mux(decoded_addr_26_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_55 = mux(decoded_addr_128_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_56 = mux(decoded_addr_7_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_57 = mux(decoded_addr_62_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_58 = mux(decoded_addr_77_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_59 = mux(decoded_addr_46_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_60 = mux(decoded_addr_112_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_61 = mux(decoded_addr_60_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_62 = mux(decoded_addr_92_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_63 = mux(decoded_addr_148_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_64 = mux(decoded_addr_14_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_65 = mux(decoded_addr_21_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_66 = mux(decoded_addr_33_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_67 = mux(decoded_addr_19_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_68 = mux(decoded_addr_133_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_69 = mux(decoded_addr_149_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_70 = mux(decoded_addr_50_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_71 = mux(decoded_addr_75_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_72 = mux(decoded_addr_102_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_73 = mux(decoded_addr_84_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_74 = mux(decoded_addr_45_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_75 = mux(decoded_addr_64_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_76 = mux(decoded_addr_120_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_77 = mux(decoded_addr_30_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_78 = mux(decoded_addr_5_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_79 = mux(decoded_addr_32_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_80 = mux(decoded_addr_143_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_81 = mux(decoded_addr_117_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_82 = mux(decoded_addr_63_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_83 = mux(decoded_addr_107_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_84 = mux(decoded_addr_88_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_85 = mux(decoded_addr_114_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_86 = mux(decoded_addr_73_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_87 = mux(decoded_addr_53_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_88 = mux(decoded_addr_147_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_89 = mux(decoded_addr_41_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_90 = mux(decoded_addr_56_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_91 = mux(decoded_addr_37_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_92 = mux(decoded_addr_79_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_93 = mux(decoded_addr_96_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_94 = mux(decoded_addr_4_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_95 = mux(decoded_addr_101_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_96 = mux(decoded_addr_119_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_97 = mux(decoded_addr_22_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_98 = mux(decoded_addr_139_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_99 = mux(decoded_addr_11_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_100 = mux(decoded_addr_134_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_101 = mux(decoded_addr_12_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_102 = mux(decoded_addr_65_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_103 = mux(decoded_addr_86_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_104 = mux(decoded_addr_47_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_105 = mux(decoded_addr_106_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_106 = mux(decoded_addr_58_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_107 = mux(decoded_addr_87_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_108 = mux(decoded_addr_142_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_109 = mux(decoded_addr_13_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_110 = mux(decoded_addr_35_2, read_mcounteren, UInt<1>(0h0)) node _io_rw_rdata_T_111 = mux(decoded_addr_2_2, value_1, UInt<1>(0h0)) node _io_rw_rdata_T_112 = mux(decoded_addr_66_2, value, UInt<1>(0h0)) node _io_rw_rdata_T_113 = mux(decoded_addr_42_2, _T_19, UInt<1>(0h0)) node _io_rw_rdata_T_114 = mux(decoded_addr_61_2, _T_21, UInt<1>(0h0)) node _io_rw_rdata_T_115 = mux(decoded_addr_48_2, read_sip, UInt<1>(0h0)) node _io_rw_rdata_T_116 = mux(decoded_addr_44_2, read_sie, UInt<1>(0h0)) node _io_rw_rdata_T_117 = mux(decoded_addr_15_2, reg_sscratch, UInt<1>(0h0)) node _io_rw_rdata_T_118 = mux(decoded_addr_145_2, reg_scause, UInt<1>(0h0)) node _io_rw_rdata_T_119 = mux(decoded_addr_93_2, _T_24, UInt<1>(0h0)) node _io_rw_rdata_T_120 = mux(decoded_addr_6_2, _T_25, UInt<1>(0h0)) node _io_rw_rdata_T_121 = mux(decoded_addr_28_2, _T_33, UInt<1>(0h0)) node _io_rw_rdata_T_122 = mux(decoded_addr_25_2, read_stvec, UInt<1>(0h0)) node _io_rw_rdata_T_123 = mux(decoded_addr_137_2, read_scounteren, UInt<1>(0h0)) node _io_rw_rdata_T_124 = mux(decoded_addr_123_2, read_mideleg, UInt<1>(0h0)) node _io_rw_rdata_T_125 = mux(decoded_addr_23_2, read_medeleg, UInt<1>(0h0)) node _io_rw_rdata_T_126 = mux(decoded_addr_69_2, _T_34, UInt<1>(0h0)) node _io_rw_rdata_T_127 = mux(decoded_addr_141_2, _T_43, UInt<1>(0h0)) node _io_rw_rdata_T_128 = mux(decoded_addr_9_2, _T_52, UInt<1>(0h0)) node _io_rw_rdata_T_129 = mux(decoded_addr_104_2, reg_pmp[0].addr, UInt<1>(0h0)) node _io_rw_rdata_T_130 = mux(decoded_addr_8_2, reg_pmp[1].addr, UInt<1>(0h0)) node _io_rw_rdata_T_131 = mux(decoded_addr_125_2, reg_pmp[2].addr, UInt<1>(0h0)) node _io_rw_rdata_T_132 = mux(decoded_addr_85_2, reg_pmp[3].addr, UInt<1>(0h0)) node _io_rw_rdata_T_133 = mux(decoded_addr_54_2, reg_pmp[4].addr, UInt<1>(0h0)) node _io_rw_rdata_T_134 = mux(decoded_addr_20_2, reg_pmp[5].addr, UInt<1>(0h0)) node _io_rw_rdata_T_135 = mux(decoded_addr_135_2, reg_pmp[6].addr, UInt<1>(0h0)) node _io_rw_rdata_T_136 = mux(decoded_addr_115_2, reg_pmp[7].addr, UInt<1>(0h0)) node _io_rw_rdata_T_137 = mux(decoded_addr_43_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_138 = mux(decoded_addr_71_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_139 = mux(decoded_addr_110_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_140 = mux(decoded_addr_140_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_141 = mux(decoded_addr_34_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_142 = mux(decoded_addr_40_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_143 = mux(decoded_addr_80_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_144 = mux(decoded_addr_98_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_145 = mux(decoded_addr_18_2, reg_custom_0, UInt<1>(0h0)) node _io_rw_rdata_T_146 = mux(decoded_addr_3_2, reg_custom_1, UInt<1>(0h0)) node _io_rw_rdata_T_147 = mux(decoded_addr_38_2, reg_custom_2, UInt<1>(0h0)) node _io_rw_rdata_T_148 = mux(decoded_addr_127_2, reg_custom_3, UInt<1>(0h0)) node _io_rw_rdata_T_149 = mux(decoded_addr_95_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_150 = or(_io_rw_rdata_T, _io_rw_rdata_T_1) node _io_rw_rdata_T_151 = or(_io_rw_rdata_T_150, _io_rw_rdata_T_2) node _io_rw_rdata_T_152 = or(_io_rw_rdata_T_151, _io_rw_rdata_T_3) node _io_rw_rdata_T_153 = or(_io_rw_rdata_T_152, _io_rw_rdata_T_4) node _io_rw_rdata_T_154 = or(_io_rw_rdata_T_153, _io_rw_rdata_T_5) node _io_rw_rdata_T_155 = or(_io_rw_rdata_T_154, _io_rw_rdata_T_6) node _io_rw_rdata_T_156 = or(_io_rw_rdata_T_155, _io_rw_rdata_T_7) node _io_rw_rdata_T_157 = or(_io_rw_rdata_T_156, _io_rw_rdata_T_8) node _io_rw_rdata_T_158 = or(_io_rw_rdata_T_157, _io_rw_rdata_T_9) node _io_rw_rdata_T_159 = or(_io_rw_rdata_T_158, _io_rw_rdata_T_10) node _io_rw_rdata_T_160 = or(_io_rw_rdata_T_159, _io_rw_rdata_T_11) node _io_rw_rdata_T_161 = or(_io_rw_rdata_T_160, _io_rw_rdata_T_12) node _io_rw_rdata_T_162 = or(_io_rw_rdata_T_161, _io_rw_rdata_T_13) node _io_rw_rdata_T_163 = or(_io_rw_rdata_T_162, _io_rw_rdata_T_14) node _io_rw_rdata_T_164 = or(_io_rw_rdata_T_163, _io_rw_rdata_T_15) node _io_rw_rdata_T_165 = or(_io_rw_rdata_T_164, _io_rw_rdata_T_16) node _io_rw_rdata_T_166 = or(_io_rw_rdata_T_165, _io_rw_rdata_T_17) node _io_rw_rdata_T_167 = or(_io_rw_rdata_T_166, _io_rw_rdata_T_18) node _io_rw_rdata_T_168 = or(_io_rw_rdata_T_167, _io_rw_rdata_T_19) node _io_rw_rdata_T_169 = or(_io_rw_rdata_T_168, _io_rw_rdata_T_20) node _io_rw_rdata_T_170 = or(_io_rw_rdata_T_169, _io_rw_rdata_T_21) node _io_rw_rdata_T_171 = or(_io_rw_rdata_T_170, _io_rw_rdata_T_22) node _io_rw_rdata_T_172 = or(_io_rw_rdata_T_171, _io_rw_rdata_T_23) node _io_rw_rdata_T_173 = or(_io_rw_rdata_T_172, _io_rw_rdata_T_24) node _io_rw_rdata_T_174 = or(_io_rw_rdata_T_173, _io_rw_rdata_T_25) node _io_rw_rdata_T_175 = or(_io_rw_rdata_T_174, _io_rw_rdata_T_26) node _io_rw_rdata_T_176 = or(_io_rw_rdata_T_175, _io_rw_rdata_T_27) node _io_rw_rdata_T_177 = or(_io_rw_rdata_T_176, _io_rw_rdata_T_28) node _io_rw_rdata_T_178 = or(_io_rw_rdata_T_177, _io_rw_rdata_T_29) node _io_rw_rdata_T_179 = or(_io_rw_rdata_T_178, _io_rw_rdata_T_30) node _io_rw_rdata_T_180 = or(_io_rw_rdata_T_179, _io_rw_rdata_T_31) node _io_rw_rdata_T_181 = or(_io_rw_rdata_T_180, _io_rw_rdata_T_32) node _io_rw_rdata_T_182 = or(_io_rw_rdata_T_181, _io_rw_rdata_T_33) node _io_rw_rdata_T_183 = or(_io_rw_rdata_T_182, _io_rw_rdata_T_34) node _io_rw_rdata_T_184 = or(_io_rw_rdata_T_183, _io_rw_rdata_T_35) node _io_rw_rdata_T_185 = or(_io_rw_rdata_T_184, _io_rw_rdata_T_36) node _io_rw_rdata_T_186 = or(_io_rw_rdata_T_185, _io_rw_rdata_T_37) node _io_rw_rdata_T_187 = or(_io_rw_rdata_T_186, _io_rw_rdata_T_38) node _io_rw_rdata_T_188 = or(_io_rw_rdata_T_187, _io_rw_rdata_T_39) node _io_rw_rdata_T_189 = or(_io_rw_rdata_T_188, _io_rw_rdata_T_40) node _io_rw_rdata_T_190 = or(_io_rw_rdata_T_189, _io_rw_rdata_T_41) node _io_rw_rdata_T_191 = or(_io_rw_rdata_T_190, _io_rw_rdata_T_42) node _io_rw_rdata_T_192 = or(_io_rw_rdata_T_191, _io_rw_rdata_T_43) node _io_rw_rdata_T_193 = or(_io_rw_rdata_T_192, _io_rw_rdata_T_44) node _io_rw_rdata_T_194 = or(_io_rw_rdata_T_193, _io_rw_rdata_T_45) node _io_rw_rdata_T_195 = or(_io_rw_rdata_T_194, _io_rw_rdata_T_46) node _io_rw_rdata_T_196 = or(_io_rw_rdata_T_195, _io_rw_rdata_T_47) node _io_rw_rdata_T_197 = or(_io_rw_rdata_T_196, _io_rw_rdata_T_48) node _io_rw_rdata_T_198 = or(_io_rw_rdata_T_197, _io_rw_rdata_T_49) node _io_rw_rdata_T_199 = or(_io_rw_rdata_T_198, _io_rw_rdata_T_50) node _io_rw_rdata_T_200 = or(_io_rw_rdata_T_199, _io_rw_rdata_T_51) node _io_rw_rdata_T_201 = or(_io_rw_rdata_T_200, _io_rw_rdata_T_52) node _io_rw_rdata_T_202 = or(_io_rw_rdata_T_201, _io_rw_rdata_T_53) node _io_rw_rdata_T_203 = or(_io_rw_rdata_T_202, _io_rw_rdata_T_54) node _io_rw_rdata_T_204 = or(_io_rw_rdata_T_203, _io_rw_rdata_T_55) node _io_rw_rdata_T_205 = or(_io_rw_rdata_T_204, _io_rw_rdata_T_56) node _io_rw_rdata_T_206 = or(_io_rw_rdata_T_205, _io_rw_rdata_T_57) node _io_rw_rdata_T_207 = or(_io_rw_rdata_T_206, _io_rw_rdata_T_58) node _io_rw_rdata_T_208 = or(_io_rw_rdata_T_207, _io_rw_rdata_T_59) node _io_rw_rdata_T_209 = or(_io_rw_rdata_T_208, _io_rw_rdata_T_60) node _io_rw_rdata_T_210 = or(_io_rw_rdata_T_209, _io_rw_rdata_T_61) node _io_rw_rdata_T_211 = or(_io_rw_rdata_T_210, _io_rw_rdata_T_62) node _io_rw_rdata_T_212 = or(_io_rw_rdata_T_211, _io_rw_rdata_T_63) node _io_rw_rdata_T_213 = or(_io_rw_rdata_T_212, _io_rw_rdata_T_64) node _io_rw_rdata_T_214 = or(_io_rw_rdata_T_213, _io_rw_rdata_T_65) node _io_rw_rdata_T_215 = or(_io_rw_rdata_T_214, _io_rw_rdata_T_66) node _io_rw_rdata_T_216 = or(_io_rw_rdata_T_215, _io_rw_rdata_T_67) node _io_rw_rdata_T_217 = or(_io_rw_rdata_T_216, _io_rw_rdata_T_68) node _io_rw_rdata_T_218 = or(_io_rw_rdata_T_217, _io_rw_rdata_T_69) node _io_rw_rdata_T_219 = or(_io_rw_rdata_T_218, _io_rw_rdata_T_70) node _io_rw_rdata_T_220 = or(_io_rw_rdata_T_219, _io_rw_rdata_T_71) node _io_rw_rdata_T_221 = or(_io_rw_rdata_T_220, _io_rw_rdata_T_72) node _io_rw_rdata_T_222 = or(_io_rw_rdata_T_221, _io_rw_rdata_T_73) node _io_rw_rdata_T_223 = or(_io_rw_rdata_T_222, _io_rw_rdata_T_74) node _io_rw_rdata_T_224 = or(_io_rw_rdata_T_223, _io_rw_rdata_T_75) node _io_rw_rdata_T_225 = or(_io_rw_rdata_T_224, _io_rw_rdata_T_76) node _io_rw_rdata_T_226 = or(_io_rw_rdata_T_225, _io_rw_rdata_T_77) node _io_rw_rdata_T_227 = or(_io_rw_rdata_T_226, _io_rw_rdata_T_78) node _io_rw_rdata_T_228 = or(_io_rw_rdata_T_227, _io_rw_rdata_T_79) node _io_rw_rdata_T_229 = or(_io_rw_rdata_T_228, _io_rw_rdata_T_80) node _io_rw_rdata_T_230 = or(_io_rw_rdata_T_229, _io_rw_rdata_T_81) node _io_rw_rdata_T_231 = or(_io_rw_rdata_T_230, _io_rw_rdata_T_82) node _io_rw_rdata_T_232 = or(_io_rw_rdata_T_231, _io_rw_rdata_T_83) node _io_rw_rdata_T_233 = or(_io_rw_rdata_T_232, _io_rw_rdata_T_84) node _io_rw_rdata_T_234 = or(_io_rw_rdata_T_233, _io_rw_rdata_T_85) node _io_rw_rdata_T_235 = or(_io_rw_rdata_T_234, _io_rw_rdata_T_86) node _io_rw_rdata_T_236 = or(_io_rw_rdata_T_235, _io_rw_rdata_T_87) node _io_rw_rdata_T_237 = or(_io_rw_rdata_T_236, _io_rw_rdata_T_88) node _io_rw_rdata_T_238 = or(_io_rw_rdata_T_237, _io_rw_rdata_T_89) node _io_rw_rdata_T_239 = or(_io_rw_rdata_T_238, _io_rw_rdata_T_90) node _io_rw_rdata_T_240 = or(_io_rw_rdata_T_239, _io_rw_rdata_T_91) node _io_rw_rdata_T_241 = or(_io_rw_rdata_T_240, _io_rw_rdata_T_92) node _io_rw_rdata_T_242 = or(_io_rw_rdata_T_241, _io_rw_rdata_T_93) node _io_rw_rdata_T_243 = or(_io_rw_rdata_T_242, _io_rw_rdata_T_94) node _io_rw_rdata_T_244 = or(_io_rw_rdata_T_243, _io_rw_rdata_T_95) node _io_rw_rdata_T_245 = or(_io_rw_rdata_T_244, _io_rw_rdata_T_96) node _io_rw_rdata_T_246 = or(_io_rw_rdata_T_245, _io_rw_rdata_T_97) node _io_rw_rdata_T_247 = or(_io_rw_rdata_T_246, _io_rw_rdata_T_98) node _io_rw_rdata_T_248 = or(_io_rw_rdata_T_247, _io_rw_rdata_T_99) node _io_rw_rdata_T_249 = or(_io_rw_rdata_T_248, _io_rw_rdata_T_100) node _io_rw_rdata_T_250 = or(_io_rw_rdata_T_249, _io_rw_rdata_T_101) node _io_rw_rdata_T_251 = or(_io_rw_rdata_T_250, _io_rw_rdata_T_102) node _io_rw_rdata_T_252 = or(_io_rw_rdata_T_251, _io_rw_rdata_T_103) node _io_rw_rdata_T_253 = or(_io_rw_rdata_T_252, _io_rw_rdata_T_104) node _io_rw_rdata_T_254 = or(_io_rw_rdata_T_253, _io_rw_rdata_T_105) node _io_rw_rdata_T_255 = or(_io_rw_rdata_T_254, _io_rw_rdata_T_106) node _io_rw_rdata_T_256 = or(_io_rw_rdata_T_255, _io_rw_rdata_T_107) node _io_rw_rdata_T_257 = or(_io_rw_rdata_T_256, _io_rw_rdata_T_108) node _io_rw_rdata_T_258 = or(_io_rw_rdata_T_257, _io_rw_rdata_T_109) node _io_rw_rdata_T_259 = or(_io_rw_rdata_T_258, _io_rw_rdata_T_110) node _io_rw_rdata_T_260 = or(_io_rw_rdata_T_259, _io_rw_rdata_T_111) node _io_rw_rdata_T_261 = or(_io_rw_rdata_T_260, _io_rw_rdata_T_112) node _io_rw_rdata_T_262 = or(_io_rw_rdata_T_261, _io_rw_rdata_T_113) node _io_rw_rdata_T_263 = or(_io_rw_rdata_T_262, _io_rw_rdata_T_114) node _io_rw_rdata_T_264 = or(_io_rw_rdata_T_263, _io_rw_rdata_T_115) node _io_rw_rdata_T_265 = or(_io_rw_rdata_T_264, _io_rw_rdata_T_116) node _io_rw_rdata_T_266 = or(_io_rw_rdata_T_265, _io_rw_rdata_T_117) node _io_rw_rdata_T_267 = or(_io_rw_rdata_T_266, _io_rw_rdata_T_118) node _io_rw_rdata_T_268 = or(_io_rw_rdata_T_267, _io_rw_rdata_T_119) node _io_rw_rdata_T_269 = or(_io_rw_rdata_T_268, _io_rw_rdata_T_120) node _io_rw_rdata_T_270 = or(_io_rw_rdata_T_269, _io_rw_rdata_T_121) node _io_rw_rdata_T_271 = or(_io_rw_rdata_T_270, _io_rw_rdata_T_122) node _io_rw_rdata_T_272 = or(_io_rw_rdata_T_271, _io_rw_rdata_T_123) node _io_rw_rdata_T_273 = or(_io_rw_rdata_T_272, _io_rw_rdata_T_124) node _io_rw_rdata_T_274 = or(_io_rw_rdata_T_273, _io_rw_rdata_T_125) node _io_rw_rdata_T_275 = or(_io_rw_rdata_T_274, _io_rw_rdata_T_126) node _io_rw_rdata_T_276 = or(_io_rw_rdata_T_275, _io_rw_rdata_T_127) node _io_rw_rdata_T_277 = or(_io_rw_rdata_T_276, _io_rw_rdata_T_128) node _io_rw_rdata_T_278 = or(_io_rw_rdata_T_277, _io_rw_rdata_T_129) node _io_rw_rdata_T_279 = or(_io_rw_rdata_T_278, _io_rw_rdata_T_130) node _io_rw_rdata_T_280 = or(_io_rw_rdata_T_279, _io_rw_rdata_T_131) node _io_rw_rdata_T_281 = or(_io_rw_rdata_T_280, _io_rw_rdata_T_132) node _io_rw_rdata_T_282 = or(_io_rw_rdata_T_281, _io_rw_rdata_T_133) node _io_rw_rdata_T_283 = or(_io_rw_rdata_T_282, _io_rw_rdata_T_134) node _io_rw_rdata_T_284 = or(_io_rw_rdata_T_283, _io_rw_rdata_T_135) node _io_rw_rdata_T_285 = or(_io_rw_rdata_T_284, _io_rw_rdata_T_136) node _io_rw_rdata_T_286 = or(_io_rw_rdata_T_285, _io_rw_rdata_T_137) node _io_rw_rdata_T_287 = or(_io_rw_rdata_T_286, _io_rw_rdata_T_138) node _io_rw_rdata_T_288 = or(_io_rw_rdata_T_287, _io_rw_rdata_T_139) node _io_rw_rdata_T_289 = or(_io_rw_rdata_T_288, _io_rw_rdata_T_140) node _io_rw_rdata_T_290 = or(_io_rw_rdata_T_289, _io_rw_rdata_T_141) node _io_rw_rdata_T_291 = or(_io_rw_rdata_T_290, _io_rw_rdata_T_142) node _io_rw_rdata_T_292 = or(_io_rw_rdata_T_291, _io_rw_rdata_T_143) node _io_rw_rdata_T_293 = or(_io_rw_rdata_T_292, _io_rw_rdata_T_144) node _io_rw_rdata_T_294 = or(_io_rw_rdata_T_293, _io_rw_rdata_T_145) node _io_rw_rdata_T_295 = or(_io_rw_rdata_T_294, _io_rw_rdata_T_146) node _io_rw_rdata_T_296 = or(_io_rw_rdata_T_295, _io_rw_rdata_T_147) node _io_rw_rdata_T_297 = or(_io_rw_rdata_T_296, _io_rw_rdata_T_148) node _io_rw_rdata_T_298 = or(_io_rw_rdata_T_297, _io_rw_rdata_T_149) wire _io_rw_rdata_WIRE : UInt connect _io_rw_rdata_WIRE, _io_rw_rdata_T_298 connect io.rw.rdata, _io_rw_rdata_WIRE node _T_256 = andr(UInt<2>(0h1)) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_259 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_260 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_261 = or(_T_258, _T_259) node _T_262 = or(_T_261, _T_260) node _T_263 = eq(io.rw.addr, UInt<11>(0h7a0)) node _T_264 = and(_T_262, _T_263) else : node _T_265 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_266 = eq(io.rw.addr, UInt<11>(0h7a0)) node _T_267 = and(_T_265, _T_266) node _T_268 = andr(UInt<2>(0h1)) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_271 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_272 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_273 = or(_T_270, _T_271) node _T_274 = or(_T_273, _T_272) node _T_275 = eq(io.rw.addr, UInt<11>(0h7a1)) node _T_276 = and(_T_274, _T_275) else : node _T_277 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_278 = eq(io.rw.addr, UInt<11>(0h7a1)) node _T_279 = and(_T_277, _T_278) node _T_280 = andr(UInt<2>(0h1)) node _T_281 = eq(_T_280, UInt<1>(0h0)) when _T_281 : node _T_282 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_283 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_284 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_285 = or(_T_282, _T_283) node _T_286 = or(_T_285, _T_284) node _T_287 = eq(io.rw.addr, UInt<11>(0h7a2)) node _T_288 = and(_T_286, _T_287) else : node _T_289 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_290 = eq(io.rw.addr, UInt<11>(0h7a2)) node _T_291 = and(_T_289, _T_290) node _T_292 = andr(UInt<2>(0h1)) node _T_293 = eq(_T_292, UInt<1>(0h0)) when _T_293 : node _T_294 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_295 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_296 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_297 = or(_T_294, _T_295) node _T_298 = or(_T_297, _T_296) node _T_299 = eq(io.rw.addr, UInt<11>(0h7a3)) node _T_300 = and(_T_298, _T_299) else : node _T_301 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_302 = eq(io.rw.addr, UInt<11>(0h7a3)) node _T_303 = and(_T_301, _T_302) node _T_304 = andr(UInt<2>(0h0)) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_307 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_308 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_309 = or(_T_306, _T_307) node _T_310 = or(_T_309, _T_308) node _T_311 = eq(io.rw.addr, UInt<10>(0h301)) node _T_312 = and(_T_310, _T_311) else : node _T_313 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_314 = eq(io.rw.addr, UInt<10>(0h301)) node _T_315 = and(_T_313, _T_314) node _T_316 = andr(UInt<2>(0h0)) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_319 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_320 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_321 = or(_T_318, _T_319) node _T_322 = or(_T_321, _T_320) node _T_323 = eq(io.rw.addr, UInt<10>(0h300)) node _T_324 = and(_T_322, _T_323) else : node _T_325 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_326 = eq(io.rw.addr, UInt<10>(0h300)) node _T_327 = and(_T_325, _T_326) node _T_328 = andr(UInt<2>(0h0)) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_331 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_332 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_333 = or(_T_330, _T_331) node _T_334 = or(_T_333, _T_332) node _T_335 = eq(io.rw.addr, UInt<10>(0h305)) node _T_336 = and(_T_334, _T_335) else : node _T_337 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_338 = eq(io.rw.addr, UInt<10>(0h305)) node _T_339 = and(_T_337, _T_338) node _T_340 = andr(UInt<2>(0h0)) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_343 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_344 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_345 = or(_T_342, _T_343) node _T_346 = or(_T_345, _T_344) node _T_347 = eq(io.rw.addr, UInt<10>(0h344)) node _T_348 = and(_T_346, _T_347) else : node _T_349 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_350 = eq(io.rw.addr, UInt<10>(0h344)) node _T_351 = and(_T_349, _T_350) node _T_352 = andr(UInt<2>(0h0)) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_355 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_356 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_357 = or(_T_354, _T_355) node _T_358 = or(_T_357, _T_356) node _T_359 = eq(io.rw.addr, UInt<10>(0h304)) node _T_360 = and(_T_358, _T_359) else : node _T_361 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_362 = eq(io.rw.addr, UInt<10>(0h304)) node _T_363 = and(_T_361, _T_362) node _T_364 = andr(UInt<2>(0h0)) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_367 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_368 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_369 = or(_T_366, _T_367) node _T_370 = or(_T_369, _T_368) node _T_371 = eq(io.rw.addr, UInt<10>(0h340)) node _T_372 = and(_T_370, _T_371) else : node _T_373 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_374 = eq(io.rw.addr, UInt<10>(0h340)) node _T_375 = and(_T_373, _T_374) node _T_376 = andr(UInt<2>(0h0)) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_379 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_380 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_381 = or(_T_378, _T_379) node _T_382 = or(_T_381, _T_380) node _T_383 = eq(io.rw.addr, UInt<10>(0h341)) node _T_384 = and(_T_382, _T_383) else : node _T_385 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_386 = eq(io.rw.addr, UInt<10>(0h341)) node _T_387 = and(_T_385, _T_386) node _T_388 = andr(UInt<2>(0h0)) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_391 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_392 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_393 = or(_T_390, _T_391) node _T_394 = or(_T_393, _T_392) node _T_395 = eq(io.rw.addr, UInt<10>(0h343)) node _T_396 = and(_T_394, _T_395) else : node _T_397 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_398 = eq(io.rw.addr, UInt<10>(0h343)) node _T_399 = and(_T_397, _T_398) node _T_400 = andr(UInt<2>(0h0)) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_403 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_404 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_405 = or(_T_402, _T_403) node _T_406 = or(_T_405, _T_404) node _T_407 = eq(io.rw.addr, UInt<10>(0h342)) node _T_408 = and(_T_406, _T_407) else : node _T_409 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_410 = eq(io.rw.addr, UInt<10>(0h342)) node _T_411 = and(_T_409, _T_410) node _T_412 = andr(UInt<2>(0h3)) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_415 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_416 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_417 = or(_T_414, _T_415) node _T_418 = or(_T_417, _T_416) node _T_419 = eq(io.rw.addr, UInt<12>(0hf14)) node _T_420 = and(_T_418, _T_419) else : node _T_421 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_422 = eq(io.rw.addr, UInt<12>(0hf14)) node _T_423 = and(_T_421, _T_422) node _T_424 = andr(UInt<2>(0h1)) node _T_425 = eq(_T_424, UInt<1>(0h0)) when _T_425 : node _T_426 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_427 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_428 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_429 = or(_T_426, _T_427) node _T_430 = or(_T_429, _T_428) node _T_431 = eq(io.rw.addr, UInt<11>(0h7b0)) node _T_432 = and(_T_430, _T_431) else : node _T_433 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_434 = eq(io.rw.addr, UInt<11>(0h7b0)) node _T_435 = and(_T_433, _T_434) node _T_436 = andr(UInt<2>(0h1)) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_439 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_440 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_441 = or(_T_438, _T_439) node _T_442 = or(_T_441, _T_440) node _T_443 = eq(io.rw.addr, UInt<11>(0h7b1)) node _T_444 = and(_T_442, _T_443) else : node _T_445 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_446 = eq(io.rw.addr, UInt<11>(0h7b1)) node _T_447 = and(_T_445, _T_446) node _T_448 = andr(UInt<2>(0h1)) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_451 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_452 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_453 = or(_T_450, _T_451) node _T_454 = or(_T_453, _T_452) node _T_455 = eq(io.rw.addr, UInt<11>(0h7b2)) node _T_456 = and(_T_454, _T_455) else : node _T_457 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_458 = eq(io.rw.addr, UInt<11>(0h7b2)) node _T_459 = and(_T_457, _T_458) node _T_460 = andr(UInt<2>(0h0)) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_463 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_464 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_465 = or(_T_462, _T_463) node _T_466 = or(_T_465, _T_464) node _T_467 = eq(io.rw.addr, UInt<1>(0h1)) node _T_468 = and(_T_466, _T_467) else : node _T_469 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_470 = eq(io.rw.addr, UInt<1>(0h1)) node _T_471 = and(_T_469, _T_470) node _T_472 = andr(UInt<2>(0h0)) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_475 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_476 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_477 = or(_T_474, _T_475) node _T_478 = or(_T_477, _T_476) node _T_479 = eq(io.rw.addr, UInt<2>(0h2)) node _T_480 = and(_T_478, _T_479) else : node _T_481 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_482 = eq(io.rw.addr, UInt<2>(0h2)) node _T_483 = and(_T_481, _T_482) node _T_484 = andr(UInt<2>(0h0)) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_487 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_488 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_489 = or(_T_486, _T_487) node _T_490 = or(_T_489, _T_488) node _T_491 = eq(io.rw.addr, UInt<2>(0h3)) node _T_492 = and(_T_490, _T_491) else : node _T_493 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_494 = eq(io.rw.addr, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _T_496 = andr(UInt<2>(0h0)) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_499 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_500 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_501 = or(_T_498, _T_499) node _T_502 = or(_T_501, _T_500) node _T_503 = eq(io.rw.addr, UInt<10>(0h320)) node _T_504 = and(_T_502, _T_503) else : node _T_505 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_506 = eq(io.rw.addr, UInt<10>(0h320)) node _T_507 = and(_T_505, _T_506) node _T_508 = andr(UInt<2>(0h2)) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_511 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_512 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_513 = or(_T_510, _T_511) node _T_514 = or(_T_513, _T_512) node _T_515 = eq(io.rw.addr, UInt<12>(0hb00)) node _T_516 = and(_T_514, _T_515) else : node _T_517 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_518 = eq(io.rw.addr, UInt<12>(0hb00)) node _T_519 = and(_T_517, _T_518) node _T_520 = andr(UInt<2>(0h2)) node _T_521 = eq(_T_520, UInt<1>(0h0)) when _T_521 : node _T_522 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_523 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_524 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_525 = or(_T_522, _T_523) node _T_526 = or(_T_525, _T_524) node _T_527 = eq(io.rw.addr, UInt<12>(0hb02)) node _T_528 = and(_T_526, _T_527) else : node _T_529 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_530 = eq(io.rw.addr, UInt<12>(0hb02)) node _T_531 = and(_T_529, _T_530) node _T_532 = andr(UInt<2>(0h0)) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_535 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_536 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_537 = or(_T_534, _T_535) node _T_538 = or(_T_537, _T_536) node _T_539 = eq(io.rw.addr, UInt<10>(0h323)) node _T_540 = and(_T_538, _T_539) else : node _T_541 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_542 = eq(io.rw.addr, UInt<10>(0h323)) node _T_543 = and(_T_541, _T_542) node _T_544 = andr(UInt<2>(0h2)) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_547 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_548 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_549 = or(_T_546, _T_547) node _T_550 = or(_T_549, _T_548) node _T_551 = eq(io.rw.addr, UInt<12>(0hb03)) node _T_552 = and(_T_550, _T_551) else : node _T_553 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_554 = eq(io.rw.addr, UInt<12>(0hb03)) node _T_555 = and(_T_553, _T_554) node _T_556 = andr(UInt<2>(0h0)) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_559 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_560 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_561 = or(_T_558, _T_559) node _T_562 = or(_T_561, _T_560) node _T_563 = eq(io.rw.addr, UInt<10>(0h324)) node _T_564 = and(_T_562, _T_563) else : node _T_565 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_566 = eq(io.rw.addr, UInt<10>(0h324)) node _T_567 = and(_T_565, _T_566) node _T_568 = andr(UInt<2>(0h2)) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_571 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_572 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_573 = or(_T_570, _T_571) node _T_574 = or(_T_573, _T_572) node _T_575 = eq(io.rw.addr, UInt<12>(0hb04)) node _T_576 = and(_T_574, _T_575) else : node _T_577 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_578 = eq(io.rw.addr, UInt<12>(0hb04)) node _T_579 = and(_T_577, _T_578) node _T_580 = andr(UInt<2>(0h0)) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_583 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_584 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_585 = or(_T_582, _T_583) node _T_586 = or(_T_585, _T_584) node _T_587 = eq(io.rw.addr, UInt<10>(0h325)) node _T_588 = and(_T_586, _T_587) else : node _T_589 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_590 = eq(io.rw.addr, UInt<10>(0h325)) node _T_591 = and(_T_589, _T_590) node _T_592 = andr(UInt<2>(0h2)) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_595 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_596 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_597 = or(_T_594, _T_595) node _T_598 = or(_T_597, _T_596) node _T_599 = eq(io.rw.addr, UInt<12>(0hb05)) node _T_600 = and(_T_598, _T_599) else : node _T_601 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_602 = eq(io.rw.addr, UInt<12>(0hb05)) node _T_603 = and(_T_601, _T_602) node _T_604 = andr(UInt<2>(0h0)) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_607 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_608 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_609 = or(_T_606, _T_607) node _T_610 = or(_T_609, _T_608) node _T_611 = eq(io.rw.addr, UInt<10>(0h326)) node _T_612 = and(_T_610, _T_611) else : node _T_613 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_614 = eq(io.rw.addr, UInt<10>(0h326)) node _T_615 = and(_T_613, _T_614) node _T_616 = andr(UInt<2>(0h2)) node _T_617 = eq(_T_616, UInt<1>(0h0)) when _T_617 : node _T_618 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_619 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_620 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_621 = or(_T_618, _T_619) node _T_622 = or(_T_621, _T_620) node _T_623 = eq(io.rw.addr, UInt<12>(0hb06)) node _T_624 = and(_T_622, _T_623) else : node _T_625 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_626 = eq(io.rw.addr, UInt<12>(0hb06)) node _T_627 = and(_T_625, _T_626) node _T_628 = andr(UInt<2>(0h0)) node _T_629 = eq(_T_628, UInt<1>(0h0)) when _T_629 : node _T_630 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_631 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_632 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_633 = or(_T_630, _T_631) node _T_634 = or(_T_633, _T_632) node _T_635 = eq(io.rw.addr, UInt<10>(0h327)) node _T_636 = and(_T_634, _T_635) else : node _T_637 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_638 = eq(io.rw.addr, UInt<10>(0h327)) node _T_639 = and(_T_637, _T_638) node _T_640 = andr(UInt<2>(0h2)) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_643 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_644 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_645 = or(_T_642, _T_643) node _T_646 = or(_T_645, _T_644) node _T_647 = eq(io.rw.addr, UInt<12>(0hb07)) node _T_648 = and(_T_646, _T_647) else : node _T_649 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_650 = eq(io.rw.addr, UInt<12>(0hb07)) node _T_651 = and(_T_649, _T_650) node _T_652 = andr(UInt<2>(0h0)) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_655 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_656 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_657 = or(_T_654, _T_655) node _T_658 = or(_T_657, _T_656) node _T_659 = eq(io.rw.addr, UInt<10>(0h328)) node _T_660 = and(_T_658, _T_659) else : node _T_661 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_662 = eq(io.rw.addr, UInt<10>(0h328)) node _T_663 = and(_T_661, _T_662) node _T_664 = andr(UInt<2>(0h2)) node _T_665 = eq(_T_664, UInt<1>(0h0)) when _T_665 : node _T_666 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_667 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_668 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_669 = or(_T_666, _T_667) node _T_670 = or(_T_669, _T_668) node _T_671 = eq(io.rw.addr, UInt<12>(0hb08)) node _T_672 = and(_T_670, _T_671) else : node _T_673 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_674 = eq(io.rw.addr, UInt<12>(0hb08)) node _T_675 = and(_T_673, _T_674) node _T_676 = andr(UInt<2>(0h0)) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_679 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_680 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_681 = or(_T_678, _T_679) node _T_682 = or(_T_681, _T_680) node _T_683 = eq(io.rw.addr, UInt<10>(0h329)) node _T_684 = and(_T_682, _T_683) else : node _T_685 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_686 = eq(io.rw.addr, UInt<10>(0h329)) node _T_687 = and(_T_685, _T_686) node _T_688 = andr(UInt<2>(0h2)) node _T_689 = eq(_T_688, UInt<1>(0h0)) when _T_689 : node _T_690 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_691 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_692 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_693 = or(_T_690, _T_691) node _T_694 = or(_T_693, _T_692) node _T_695 = eq(io.rw.addr, UInt<12>(0hb09)) node _T_696 = and(_T_694, _T_695) else : node _T_697 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_698 = eq(io.rw.addr, UInt<12>(0hb09)) node _T_699 = and(_T_697, _T_698) node _T_700 = andr(UInt<2>(0h0)) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_703 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_704 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_705 = or(_T_702, _T_703) node _T_706 = or(_T_705, _T_704) node _T_707 = eq(io.rw.addr, UInt<10>(0h32a)) node _T_708 = and(_T_706, _T_707) else : node _T_709 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_710 = eq(io.rw.addr, UInt<10>(0h32a)) node _T_711 = and(_T_709, _T_710) node _T_712 = andr(UInt<2>(0h2)) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_715 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_716 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_717 = or(_T_714, _T_715) node _T_718 = or(_T_717, _T_716) node _T_719 = eq(io.rw.addr, UInt<12>(0hb0a)) node _T_720 = and(_T_718, _T_719) else : node _T_721 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_722 = eq(io.rw.addr, UInt<12>(0hb0a)) node _T_723 = and(_T_721, _T_722) node _T_724 = andr(UInt<2>(0h0)) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_727 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_728 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_729 = or(_T_726, _T_727) node _T_730 = or(_T_729, _T_728) node _T_731 = eq(io.rw.addr, UInt<10>(0h32b)) node _T_732 = and(_T_730, _T_731) else : node _T_733 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_734 = eq(io.rw.addr, UInt<10>(0h32b)) node _T_735 = and(_T_733, _T_734) node _T_736 = andr(UInt<2>(0h2)) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_739 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_740 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_741 = or(_T_738, _T_739) node _T_742 = or(_T_741, _T_740) node _T_743 = eq(io.rw.addr, UInt<12>(0hb0b)) node _T_744 = and(_T_742, _T_743) else : node _T_745 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_746 = eq(io.rw.addr, UInt<12>(0hb0b)) node _T_747 = and(_T_745, _T_746) node _T_748 = andr(UInt<2>(0h0)) node _T_749 = eq(_T_748, UInt<1>(0h0)) when _T_749 : node _T_750 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_751 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_752 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_753 = or(_T_750, _T_751) node _T_754 = or(_T_753, _T_752) node _T_755 = eq(io.rw.addr, UInt<10>(0h32c)) node _T_756 = and(_T_754, _T_755) else : node _T_757 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_758 = eq(io.rw.addr, UInt<10>(0h32c)) node _T_759 = and(_T_757, _T_758) node _T_760 = andr(UInt<2>(0h2)) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_763 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_764 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_765 = or(_T_762, _T_763) node _T_766 = or(_T_765, _T_764) node _T_767 = eq(io.rw.addr, UInt<12>(0hb0c)) node _T_768 = and(_T_766, _T_767) else : node _T_769 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_770 = eq(io.rw.addr, UInt<12>(0hb0c)) node _T_771 = and(_T_769, _T_770) node _T_772 = andr(UInt<2>(0h0)) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_775 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_776 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_777 = or(_T_774, _T_775) node _T_778 = or(_T_777, _T_776) node _T_779 = eq(io.rw.addr, UInt<10>(0h32d)) node _T_780 = and(_T_778, _T_779) else : node _T_781 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_782 = eq(io.rw.addr, UInt<10>(0h32d)) node _T_783 = and(_T_781, _T_782) node _T_784 = andr(UInt<2>(0h2)) node _T_785 = eq(_T_784, UInt<1>(0h0)) when _T_785 : node _T_786 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_787 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_788 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_789 = or(_T_786, _T_787) node _T_790 = or(_T_789, _T_788) node _T_791 = eq(io.rw.addr, UInt<12>(0hb0d)) node _T_792 = and(_T_790, _T_791) else : node _T_793 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_794 = eq(io.rw.addr, UInt<12>(0hb0d)) node _T_795 = and(_T_793, _T_794) node _T_796 = andr(UInt<2>(0h0)) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_799 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_800 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_801 = or(_T_798, _T_799) node _T_802 = or(_T_801, _T_800) node _T_803 = eq(io.rw.addr, UInt<10>(0h32e)) node _T_804 = and(_T_802, _T_803) else : node _T_805 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_806 = eq(io.rw.addr, UInt<10>(0h32e)) node _T_807 = and(_T_805, _T_806) node _T_808 = andr(UInt<2>(0h2)) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_811 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_812 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_813 = or(_T_810, _T_811) node _T_814 = or(_T_813, _T_812) node _T_815 = eq(io.rw.addr, UInt<12>(0hb0e)) node _T_816 = and(_T_814, _T_815) else : node _T_817 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_818 = eq(io.rw.addr, UInt<12>(0hb0e)) node _T_819 = and(_T_817, _T_818) node _T_820 = andr(UInt<2>(0h0)) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_823 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_824 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_825 = or(_T_822, _T_823) node _T_826 = or(_T_825, _T_824) node _T_827 = eq(io.rw.addr, UInt<10>(0h32f)) node _T_828 = and(_T_826, _T_827) else : node _T_829 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_830 = eq(io.rw.addr, UInt<10>(0h32f)) node _T_831 = and(_T_829, _T_830) node _T_832 = andr(UInt<2>(0h2)) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_835 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_836 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_837 = or(_T_834, _T_835) node _T_838 = or(_T_837, _T_836) node _T_839 = eq(io.rw.addr, UInt<12>(0hb0f)) node _T_840 = and(_T_838, _T_839) else : node _T_841 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_842 = eq(io.rw.addr, UInt<12>(0hb0f)) node _T_843 = and(_T_841, _T_842) node _T_844 = andr(UInt<2>(0h0)) node _T_845 = eq(_T_844, UInt<1>(0h0)) when _T_845 : node _T_846 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_847 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_848 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_849 = or(_T_846, _T_847) node _T_850 = or(_T_849, _T_848) node _T_851 = eq(io.rw.addr, UInt<10>(0h330)) node _T_852 = and(_T_850, _T_851) else : node _T_853 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_854 = eq(io.rw.addr, UInt<10>(0h330)) node _T_855 = and(_T_853, _T_854) node _T_856 = andr(UInt<2>(0h2)) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_859 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_860 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_861 = or(_T_858, _T_859) node _T_862 = or(_T_861, _T_860) node _T_863 = eq(io.rw.addr, UInt<12>(0hb10)) node _T_864 = and(_T_862, _T_863) else : node _T_865 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_866 = eq(io.rw.addr, UInt<12>(0hb10)) node _T_867 = and(_T_865, _T_866) node _T_868 = andr(UInt<2>(0h0)) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_871 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_872 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_873 = or(_T_870, _T_871) node _T_874 = or(_T_873, _T_872) node _T_875 = eq(io.rw.addr, UInt<10>(0h331)) node _T_876 = and(_T_874, _T_875) else : node _T_877 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_878 = eq(io.rw.addr, UInt<10>(0h331)) node _T_879 = and(_T_877, _T_878) node _T_880 = andr(UInt<2>(0h2)) node _T_881 = eq(_T_880, UInt<1>(0h0)) when _T_881 : node _T_882 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_883 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_884 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_885 = or(_T_882, _T_883) node _T_886 = or(_T_885, _T_884) node _T_887 = eq(io.rw.addr, UInt<12>(0hb11)) node _T_888 = and(_T_886, _T_887) else : node _T_889 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_890 = eq(io.rw.addr, UInt<12>(0hb11)) node _T_891 = and(_T_889, _T_890) node _T_892 = andr(UInt<2>(0h0)) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_895 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_896 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_897 = or(_T_894, _T_895) node _T_898 = or(_T_897, _T_896) node _T_899 = eq(io.rw.addr, UInt<10>(0h332)) node _T_900 = and(_T_898, _T_899) else : node _T_901 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_902 = eq(io.rw.addr, UInt<10>(0h332)) node _T_903 = and(_T_901, _T_902) node _T_904 = andr(UInt<2>(0h2)) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_907 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_908 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_909 = or(_T_906, _T_907) node _T_910 = or(_T_909, _T_908) node _T_911 = eq(io.rw.addr, UInt<12>(0hb12)) node _T_912 = and(_T_910, _T_911) else : node _T_913 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_914 = eq(io.rw.addr, UInt<12>(0hb12)) node _T_915 = and(_T_913, _T_914) node _T_916 = andr(UInt<2>(0h0)) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_919 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_920 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_921 = or(_T_918, _T_919) node _T_922 = or(_T_921, _T_920) node _T_923 = eq(io.rw.addr, UInt<10>(0h333)) node _T_924 = and(_T_922, _T_923) else : node _T_925 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_926 = eq(io.rw.addr, UInt<10>(0h333)) node _T_927 = and(_T_925, _T_926) node _T_928 = andr(UInt<2>(0h2)) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_931 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_932 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_933 = or(_T_930, _T_931) node _T_934 = or(_T_933, _T_932) node _T_935 = eq(io.rw.addr, UInt<12>(0hb13)) node _T_936 = and(_T_934, _T_935) else : node _T_937 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_938 = eq(io.rw.addr, UInt<12>(0hb13)) node _T_939 = and(_T_937, _T_938) node _T_940 = andr(UInt<2>(0h0)) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_943 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_944 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_945 = or(_T_942, _T_943) node _T_946 = or(_T_945, _T_944) node _T_947 = eq(io.rw.addr, UInt<10>(0h334)) node _T_948 = and(_T_946, _T_947) else : node _T_949 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_950 = eq(io.rw.addr, UInt<10>(0h334)) node _T_951 = and(_T_949, _T_950) node _T_952 = andr(UInt<2>(0h2)) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_955 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_956 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_957 = or(_T_954, _T_955) node _T_958 = or(_T_957, _T_956) node _T_959 = eq(io.rw.addr, UInt<12>(0hb14)) node _T_960 = and(_T_958, _T_959) else : node _T_961 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_962 = eq(io.rw.addr, UInt<12>(0hb14)) node _T_963 = and(_T_961, _T_962) node _T_964 = andr(UInt<2>(0h0)) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_967 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_968 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_969 = or(_T_966, _T_967) node _T_970 = or(_T_969, _T_968) node _T_971 = eq(io.rw.addr, UInt<10>(0h335)) node _T_972 = and(_T_970, _T_971) else : node _T_973 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_974 = eq(io.rw.addr, UInt<10>(0h335)) node _T_975 = and(_T_973, _T_974) node _T_976 = andr(UInt<2>(0h2)) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_979 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_980 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_981 = or(_T_978, _T_979) node _T_982 = or(_T_981, _T_980) node _T_983 = eq(io.rw.addr, UInt<12>(0hb15)) node _T_984 = and(_T_982, _T_983) else : node _T_985 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_986 = eq(io.rw.addr, UInt<12>(0hb15)) node _T_987 = and(_T_985, _T_986) node _T_988 = andr(UInt<2>(0h0)) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_991 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_992 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_993 = or(_T_990, _T_991) node _T_994 = or(_T_993, _T_992) node _T_995 = eq(io.rw.addr, UInt<10>(0h336)) node _T_996 = and(_T_994, _T_995) else : node _T_997 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_998 = eq(io.rw.addr, UInt<10>(0h336)) node _T_999 = and(_T_997, _T_998) node _T_1000 = andr(UInt<2>(0h2)) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1003 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1004 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1005 = or(_T_1002, _T_1003) node _T_1006 = or(_T_1005, _T_1004) node _T_1007 = eq(io.rw.addr, UInt<12>(0hb16)) node _T_1008 = and(_T_1006, _T_1007) else : node _T_1009 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1010 = eq(io.rw.addr, UInt<12>(0hb16)) node _T_1011 = and(_T_1009, _T_1010) node _T_1012 = andr(UInt<2>(0h0)) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1015 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1016 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1017 = or(_T_1014, _T_1015) node _T_1018 = or(_T_1017, _T_1016) node _T_1019 = eq(io.rw.addr, UInt<10>(0h337)) node _T_1020 = and(_T_1018, _T_1019) else : node _T_1021 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1022 = eq(io.rw.addr, UInt<10>(0h337)) node _T_1023 = and(_T_1021, _T_1022) node _T_1024 = andr(UInt<2>(0h2)) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1027 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1028 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1029 = or(_T_1026, _T_1027) node _T_1030 = or(_T_1029, _T_1028) node _T_1031 = eq(io.rw.addr, UInt<12>(0hb17)) node _T_1032 = and(_T_1030, _T_1031) else : node _T_1033 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1034 = eq(io.rw.addr, UInt<12>(0hb17)) node _T_1035 = and(_T_1033, _T_1034) node _T_1036 = andr(UInt<2>(0h0)) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1039 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1040 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1041 = or(_T_1038, _T_1039) node _T_1042 = or(_T_1041, _T_1040) node _T_1043 = eq(io.rw.addr, UInt<10>(0h338)) node _T_1044 = and(_T_1042, _T_1043) else : node _T_1045 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1046 = eq(io.rw.addr, UInt<10>(0h338)) node _T_1047 = and(_T_1045, _T_1046) node _T_1048 = andr(UInt<2>(0h2)) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1051 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1052 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1053 = or(_T_1050, _T_1051) node _T_1054 = or(_T_1053, _T_1052) node _T_1055 = eq(io.rw.addr, UInt<12>(0hb18)) node _T_1056 = and(_T_1054, _T_1055) else : node _T_1057 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1058 = eq(io.rw.addr, UInt<12>(0hb18)) node _T_1059 = and(_T_1057, _T_1058) node _T_1060 = andr(UInt<2>(0h0)) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1063 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1064 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1065 = or(_T_1062, _T_1063) node _T_1066 = or(_T_1065, _T_1064) node _T_1067 = eq(io.rw.addr, UInt<10>(0h339)) node _T_1068 = and(_T_1066, _T_1067) else : node _T_1069 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1070 = eq(io.rw.addr, UInt<10>(0h339)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = andr(UInt<2>(0h2)) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1075 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1076 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1077 = or(_T_1074, _T_1075) node _T_1078 = or(_T_1077, _T_1076) node _T_1079 = eq(io.rw.addr, UInt<12>(0hb19)) node _T_1080 = and(_T_1078, _T_1079) else : node _T_1081 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1082 = eq(io.rw.addr, UInt<12>(0hb19)) node _T_1083 = and(_T_1081, _T_1082) node _T_1084 = andr(UInt<2>(0h0)) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1087 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1088 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1089 = or(_T_1086, _T_1087) node _T_1090 = or(_T_1089, _T_1088) node _T_1091 = eq(io.rw.addr, UInt<10>(0h33a)) node _T_1092 = and(_T_1090, _T_1091) else : node _T_1093 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1094 = eq(io.rw.addr, UInt<10>(0h33a)) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = andr(UInt<2>(0h2)) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1099 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1100 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1101 = or(_T_1098, _T_1099) node _T_1102 = or(_T_1101, _T_1100) node _T_1103 = eq(io.rw.addr, UInt<12>(0hb1a)) node _T_1104 = and(_T_1102, _T_1103) else : node _T_1105 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1106 = eq(io.rw.addr, UInt<12>(0hb1a)) node _T_1107 = and(_T_1105, _T_1106) node _T_1108 = andr(UInt<2>(0h0)) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1111 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1112 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1113 = or(_T_1110, _T_1111) node _T_1114 = or(_T_1113, _T_1112) node _T_1115 = eq(io.rw.addr, UInt<10>(0h33b)) node _T_1116 = and(_T_1114, _T_1115) else : node _T_1117 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1118 = eq(io.rw.addr, UInt<10>(0h33b)) node _T_1119 = and(_T_1117, _T_1118) node _T_1120 = andr(UInt<2>(0h2)) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1123 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1124 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1125 = or(_T_1122, _T_1123) node _T_1126 = or(_T_1125, _T_1124) node _T_1127 = eq(io.rw.addr, UInt<12>(0hb1b)) node _T_1128 = and(_T_1126, _T_1127) else : node _T_1129 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1130 = eq(io.rw.addr, UInt<12>(0hb1b)) node _T_1131 = and(_T_1129, _T_1130) node _T_1132 = andr(UInt<2>(0h0)) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1135 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1136 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1137 = or(_T_1134, _T_1135) node _T_1138 = or(_T_1137, _T_1136) node _T_1139 = eq(io.rw.addr, UInt<10>(0h33c)) node _T_1140 = and(_T_1138, _T_1139) else : node _T_1141 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1142 = eq(io.rw.addr, UInt<10>(0h33c)) node _T_1143 = and(_T_1141, _T_1142) node _T_1144 = andr(UInt<2>(0h2)) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1147 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1148 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1149 = or(_T_1146, _T_1147) node _T_1150 = or(_T_1149, _T_1148) node _T_1151 = eq(io.rw.addr, UInt<12>(0hb1c)) node _T_1152 = and(_T_1150, _T_1151) else : node _T_1153 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1154 = eq(io.rw.addr, UInt<12>(0hb1c)) node _T_1155 = and(_T_1153, _T_1154) node _T_1156 = andr(UInt<2>(0h0)) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1159 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1160 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1161 = or(_T_1158, _T_1159) node _T_1162 = or(_T_1161, _T_1160) node _T_1163 = eq(io.rw.addr, UInt<10>(0h33d)) node _T_1164 = and(_T_1162, _T_1163) else : node _T_1165 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1166 = eq(io.rw.addr, UInt<10>(0h33d)) node _T_1167 = and(_T_1165, _T_1166) node _T_1168 = andr(UInt<2>(0h2)) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1171 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1172 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1173 = or(_T_1170, _T_1171) node _T_1174 = or(_T_1173, _T_1172) node _T_1175 = eq(io.rw.addr, UInt<12>(0hb1d)) node _T_1176 = and(_T_1174, _T_1175) else : node _T_1177 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1178 = eq(io.rw.addr, UInt<12>(0hb1d)) node _T_1179 = and(_T_1177, _T_1178) node _T_1180 = andr(UInt<2>(0h0)) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1183 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1184 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1185 = or(_T_1182, _T_1183) node _T_1186 = or(_T_1185, _T_1184) node _T_1187 = eq(io.rw.addr, UInt<10>(0h33e)) node _T_1188 = and(_T_1186, _T_1187) else : node _T_1189 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1190 = eq(io.rw.addr, UInt<10>(0h33e)) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = andr(UInt<2>(0h2)) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1195 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1196 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1197 = or(_T_1194, _T_1195) node _T_1198 = or(_T_1197, _T_1196) node _T_1199 = eq(io.rw.addr, UInt<12>(0hb1e)) node _T_1200 = and(_T_1198, _T_1199) else : node _T_1201 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1202 = eq(io.rw.addr, UInt<12>(0hb1e)) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = andr(UInt<2>(0h0)) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1207 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1208 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1209 = or(_T_1206, _T_1207) node _T_1210 = or(_T_1209, _T_1208) node _T_1211 = eq(io.rw.addr, UInt<10>(0h33f)) node _T_1212 = and(_T_1210, _T_1211) else : node _T_1213 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1214 = eq(io.rw.addr, UInt<10>(0h33f)) node _T_1215 = and(_T_1213, _T_1214) node _T_1216 = andr(UInt<2>(0h2)) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1219 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1220 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1221 = or(_T_1218, _T_1219) node _T_1222 = or(_T_1221, _T_1220) node _T_1223 = eq(io.rw.addr, UInt<12>(0hb1f)) node _T_1224 = and(_T_1222, _T_1223) else : node _T_1225 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1226 = eq(io.rw.addr, UInt<12>(0hb1f)) node _T_1227 = and(_T_1225, _T_1226) node _T_1228 = andr(UInt<2>(0h0)) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1231 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1232 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1233 = or(_T_1230, _T_1231) node _T_1234 = or(_T_1233, _T_1232) node _T_1235 = eq(io.rw.addr, UInt<10>(0h306)) node _T_1236 = and(_T_1234, _T_1235) else : node _T_1237 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1238 = eq(io.rw.addr, UInt<10>(0h306)) node _T_1239 = and(_T_1237, _T_1238) node _T_1240 = andr(UInt<2>(0h3)) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1243 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1244 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1245 = or(_T_1242, _T_1243) node _T_1246 = or(_T_1245, _T_1244) node _T_1247 = eq(io.rw.addr, UInt<12>(0hc00)) node _T_1248 = and(_T_1246, _T_1247) else : node _T_1249 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1250 = eq(io.rw.addr, UInt<12>(0hc00)) node _T_1251 = and(_T_1249, _T_1250) node _T_1252 = andr(UInt<2>(0h3)) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1255 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1256 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1257 = or(_T_1254, _T_1255) node _T_1258 = or(_T_1257, _T_1256) node _T_1259 = eq(io.rw.addr, UInt<12>(0hc02)) node _T_1260 = and(_T_1258, _T_1259) else : node _T_1261 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1262 = eq(io.rw.addr, UInt<12>(0hc02)) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = andr(UInt<2>(0h0)) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1267 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1268 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1269 = or(_T_1266, _T_1267) node _T_1270 = or(_T_1269, _T_1268) node _T_1271 = eq(io.rw.addr, UInt<10>(0h30a)) node _T_1272 = and(_T_1270, _T_1271) else : node _T_1273 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1274 = eq(io.rw.addr, UInt<10>(0h30a)) node _T_1275 = and(_T_1273, _T_1274) node _T_1276 = andr(UInt<2>(0h0)) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1279 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1280 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1281 = or(_T_1278, _T_1279) node _T_1282 = or(_T_1281, _T_1280) node _T_1283 = eq(io.rw.addr, UInt<9>(0h100)) node _T_1284 = and(_T_1282, _T_1283) else : node _T_1285 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1286 = eq(io.rw.addr, UInt<9>(0h100)) node _T_1287 = and(_T_1285, _T_1286) node _T_1288 = andr(UInt<2>(0h0)) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1291 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1292 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1293 = or(_T_1290, _T_1291) node _T_1294 = or(_T_1293, _T_1292) node _T_1295 = eq(io.rw.addr, UInt<9>(0h144)) node _T_1296 = and(_T_1294, _T_1295) else : node _T_1297 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1298 = eq(io.rw.addr, UInt<9>(0h144)) node _T_1299 = and(_T_1297, _T_1298) node _T_1300 = andr(UInt<2>(0h0)) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1303 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1304 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1305 = or(_T_1302, _T_1303) node _T_1306 = or(_T_1305, _T_1304) node _T_1307 = eq(io.rw.addr, UInt<9>(0h104)) node _T_1308 = and(_T_1306, _T_1307) else : node _T_1309 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1310 = eq(io.rw.addr, UInt<9>(0h104)) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = andr(UInt<2>(0h0)) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1315 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1316 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1317 = or(_T_1314, _T_1315) node _T_1318 = or(_T_1317, _T_1316) node _T_1319 = eq(io.rw.addr, UInt<9>(0h140)) node _T_1320 = and(_T_1318, _T_1319) else : node _T_1321 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1322 = eq(io.rw.addr, UInt<9>(0h140)) node _T_1323 = and(_T_1321, _T_1322) node _T_1324 = andr(UInt<2>(0h0)) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1327 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1328 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1329 = or(_T_1326, _T_1327) node _T_1330 = or(_T_1329, _T_1328) node _T_1331 = eq(io.rw.addr, UInt<9>(0h142)) node _T_1332 = and(_T_1330, _T_1331) else : node _T_1333 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1334 = eq(io.rw.addr, UInt<9>(0h142)) node _T_1335 = and(_T_1333, _T_1334) node _T_1336 = andr(UInt<2>(0h0)) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1339 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1340 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1341 = or(_T_1338, _T_1339) node _T_1342 = or(_T_1341, _T_1340) node _T_1343 = eq(io.rw.addr, UInt<9>(0h143)) node _T_1344 = and(_T_1342, _T_1343) else : node _T_1345 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1346 = eq(io.rw.addr, UInt<9>(0h143)) node _T_1347 = and(_T_1345, _T_1346) node _T_1348 = andr(UInt<2>(0h0)) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1351 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1352 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1353 = or(_T_1350, _T_1351) node _T_1354 = or(_T_1353, _T_1352) node _T_1355 = eq(io.rw.addr, UInt<9>(0h180)) node _T_1356 = and(_T_1354, _T_1355) else : node _T_1357 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1358 = eq(io.rw.addr, UInt<9>(0h180)) node _T_1359 = and(_T_1357, _T_1358) node _T_1360 = andr(UInt<2>(0h0)) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1363 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1364 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1365 = or(_T_1362, _T_1363) node _T_1366 = or(_T_1365, _T_1364) node _T_1367 = eq(io.rw.addr, UInt<9>(0h141)) node _T_1368 = and(_T_1366, _T_1367) else : node _T_1369 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1370 = eq(io.rw.addr, UInt<9>(0h141)) node _T_1371 = and(_T_1369, _T_1370) node _T_1372 = andr(UInt<2>(0h0)) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1375 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1376 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1377 = or(_T_1374, _T_1375) node _T_1378 = or(_T_1377, _T_1376) node _T_1379 = eq(io.rw.addr, UInt<9>(0h105)) node _T_1380 = and(_T_1378, _T_1379) else : node _T_1381 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1382 = eq(io.rw.addr, UInt<9>(0h105)) node _T_1383 = and(_T_1381, _T_1382) node _T_1384 = andr(UInt<2>(0h0)) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1387 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1388 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1389 = or(_T_1386, _T_1387) node _T_1390 = or(_T_1389, _T_1388) node _T_1391 = eq(io.rw.addr, UInt<9>(0h106)) node _T_1392 = and(_T_1390, _T_1391) else : node _T_1393 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1394 = eq(io.rw.addr, UInt<9>(0h106)) node _T_1395 = and(_T_1393, _T_1394) node _T_1396 = andr(UInt<2>(0h0)) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1399 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1400 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1401 = or(_T_1398, _T_1399) node _T_1402 = or(_T_1401, _T_1400) node _T_1403 = eq(io.rw.addr, UInt<10>(0h303)) node _T_1404 = and(_T_1402, _T_1403) else : node _T_1405 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1406 = eq(io.rw.addr, UInt<10>(0h303)) node _T_1407 = and(_T_1405, _T_1406) node _T_1408 = andr(UInt<2>(0h0)) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1411 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1412 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1413 = or(_T_1410, _T_1411) node _T_1414 = or(_T_1413, _T_1412) node _T_1415 = eq(io.rw.addr, UInt<10>(0h302)) node _T_1416 = and(_T_1414, _T_1415) else : node _T_1417 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1418 = eq(io.rw.addr, UInt<10>(0h302)) node _T_1419 = and(_T_1417, _T_1418) node _T_1420 = andr(UInt<2>(0h0)) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) when _T_1421 : node _T_1422 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1423 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1424 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1425 = or(_T_1422, _T_1423) node _T_1426 = or(_T_1425, _T_1424) node _T_1427 = eq(io.rw.addr, UInt<9>(0h10a)) node _T_1428 = and(_T_1426, _T_1427) else : node _T_1429 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1430 = eq(io.rw.addr, UInt<9>(0h10a)) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = andr(UInt<2>(0h0)) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1435 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1436 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1437 = or(_T_1434, _T_1435) node _T_1438 = or(_T_1437, _T_1436) node _T_1439 = eq(io.rw.addr, UInt<10>(0h3a0)) node _T_1440 = and(_T_1438, _T_1439) else : node _T_1441 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1442 = eq(io.rw.addr, UInt<10>(0h3a0)) node _T_1443 = and(_T_1441, _T_1442) node _T_1444 = andr(UInt<2>(0h0)) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) when _T_1445 : node _T_1446 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1447 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1448 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1449 = or(_T_1446, _T_1447) node _T_1450 = or(_T_1449, _T_1448) node _T_1451 = eq(io.rw.addr, UInt<10>(0h3a2)) node _T_1452 = and(_T_1450, _T_1451) else : node _T_1453 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1454 = eq(io.rw.addr, UInt<10>(0h3a2)) node _T_1455 = and(_T_1453, _T_1454) node _T_1456 = andr(UInt<2>(0h0)) node _T_1457 = eq(_T_1456, UInt<1>(0h0)) when _T_1457 : node _T_1458 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1459 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1460 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1461 = or(_T_1458, _T_1459) node _T_1462 = or(_T_1461, _T_1460) node _T_1463 = eq(io.rw.addr, UInt<10>(0h3b0)) node _T_1464 = and(_T_1462, _T_1463) else : node _T_1465 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1466 = eq(io.rw.addr, UInt<10>(0h3b0)) node _T_1467 = and(_T_1465, _T_1466) node _T_1468 = andr(UInt<2>(0h0)) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) when _T_1469 : node _T_1470 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1471 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1472 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1473 = or(_T_1470, _T_1471) node _T_1474 = or(_T_1473, _T_1472) node _T_1475 = eq(io.rw.addr, UInt<10>(0h3b1)) node _T_1476 = and(_T_1474, _T_1475) else : node _T_1477 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1478 = eq(io.rw.addr, UInt<10>(0h3b1)) node _T_1479 = and(_T_1477, _T_1478) node _T_1480 = andr(UInt<2>(0h0)) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) when _T_1481 : node _T_1482 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1483 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1484 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1485 = or(_T_1482, _T_1483) node _T_1486 = or(_T_1485, _T_1484) node _T_1487 = eq(io.rw.addr, UInt<10>(0h3b2)) node _T_1488 = and(_T_1486, _T_1487) else : node _T_1489 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1490 = eq(io.rw.addr, UInt<10>(0h3b2)) node _T_1491 = and(_T_1489, _T_1490) node _T_1492 = andr(UInt<2>(0h0)) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1495 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1496 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1497 = or(_T_1494, _T_1495) node _T_1498 = or(_T_1497, _T_1496) node _T_1499 = eq(io.rw.addr, UInt<10>(0h3b3)) node _T_1500 = and(_T_1498, _T_1499) else : node _T_1501 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1502 = eq(io.rw.addr, UInt<10>(0h3b3)) node _T_1503 = and(_T_1501, _T_1502) node _T_1504 = andr(UInt<2>(0h0)) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1507 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1508 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1509 = or(_T_1506, _T_1507) node _T_1510 = or(_T_1509, _T_1508) node _T_1511 = eq(io.rw.addr, UInt<10>(0h3b4)) node _T_1512 = and(_T_1510, _T_1511) else : node _T_1513 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1514 = eq(io.rw.addr, UInt<10>(0h3b4)) node _T_1515 = and(_T_1513, _T_1514) node _T_1516 = andr(UInt<2>(0h0)) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1519 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1520 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1521 = or(_T_1518, _T_1519) node _T_1522 = or(_T_1521, _T_1520) node _T_1523 = eq(io.rw.addr, UInt<10>(0h3b5)) node _T_1524 = and(_T_1522, _T_1523) else : node _T_1525 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1526 = eq(io.rw.addr, UInt<10>(0h3b5)) node _T_1527 = and(_T_1525, _T_1526) node _T_1528 = andr(UInt<2>(0h0)) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1531 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1532 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1533 = or(_T_1530, _T_1531) node _T_1534 = or(_T_1533, _T_1532) node _T_1535 = eq(io.rw.addr, UInt<10>(0h3b6)) node _T_1536 = and(_T_1534, _T_1535) else : node _T_1537 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1538 = eq(io.rw.addr, UInt<10>(0h3b6)) node _T_1539 = and(_T_1537, _T_1538) node _T_1540 = andr(UInt<2>(0h0)) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) when _T_1541 : node _T_1542 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1543 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1544 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1545 = or(_T_1542, _T_1543) node _T_1546 = or(_T_1545, _T_1544) node _T_1547 = eq(io.rw.addr, UInt<10>(0h3b7)) node _T_1548 = and(_T_1546, _T_1547) else : node _T_1549 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1550 = eq(io.rw.addr, UInt<10>(0h3b7)) node _T_1551 = and(_T_1549, _T_1550) node _T_1552 = andr(UInt<2>(0h0)) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1555 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1556 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1557 = or(_T_1554, _T_1555) node _T_1558 = or(_T_1557, _T_1556) node _T_1559 = eq(io.rw.addr, UInt<10>(0h3b8)) node _T_1560 = and(_T_1558, _T_1559) else : node _T_1561 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1562 = eq(io.rw.addr, UInt<10>(0h3b8)) node _T_1563 = and(_T_1561, _T_1562) node _T_1564 = andr(UInt<2>(0h0)) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1567 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1568 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1569 = or(_T_1566, _T_1567) node _T_1570 = or(_T_1569, _T_1568) node _T_1571 = eq(io.rw.addr, UInt<10>(0h3b9)) node _T_1572 = and(_T_1570, _T_1571) else : node _T_1573 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1574 = eq(io.rw.addr, UInt<10>(0h3b9)) node _T_1575 = and(_T_1573, _T_1574) node _T_1576 = andr(UInt<2>(0h0)) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1579 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1580 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1581 = or(_T_1578, _T_1579) node _T_1582 = or(_T_1581, _T_1580) node _T_1583 = eq(io.rw.addr, UInt<10>(0h3ba)) node _T_1584 = and(_T_1582, _T_1583) else : node _T_1585 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1586 = eq(io.rw.addr, UInt<10>(0h3ba)) node _T_1587 = and(_T_1585, _T_1586) node _T_1588 = andr(UInt<2>(0h0)) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1591 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1592 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1593 = or(_T_1590, _T_1591) node _T_1594 = or(_T_1593, _T_1592) node _T_1595 = eq(io.rw.addr, UInt<10>(0h3bb)) node _T_1596 = and(_T_1594, _T_1595) else : node _T_1597 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1598 = eq(io.rw.addr, UInt<10>(0h3bb)) node _T_1599 = and(_T_1597, _T_1598) node _T_1600 = andr(UInt<2>(0h0)) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1603 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1604 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1605 = or(_T_1602, _T_1603) node _T_1606 = or(_T_1605, _T_1604) node _T_1607 = eq(io.rw.addr, UInt<10>(0h3bc)) node _T_1608 = and(_T_1606, _T_1607) else : node _T_1609 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1610 = eq(io.rw.addr, UInt<10>(0h3bc)) node _T_1611 = and(_T_1609, _T_1610) node _T_1612 = andr(UInt<2>(0h0)) node _T_1613 = eq(_T_1612, UInt<1>(0h0)) when _T_1613 : node _T_1614 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1615 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1616 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1617 = or(_T_1614, _T_1615) node _T_1618 = or(_T_1617, _T_1616) node _T_1619 = eq(io.rw.addr, UInt<10>(0h3bd)) node _T_1620 = and(_T_1618, _T_1619) else : node _T_1621 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1622 = eq(io.rw.addr, UInt<10>(0h3bd)) node _T_1623 = and(_T_1621, _T_1622) node _T_1624 = andr(UInt<2>(0h0)) node _T_1625 = eq(_T_1624, UInt<1>(0h0)) when _T_1625 : node _T_1626 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1627 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1628 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1629 = or(_T_1626, _T_1627) node _T_1630 = or(_T_1629, _T_1628) node _T_1631 = eq(io.rw.addr, UInt<10>(0h3be)) node _T_1632 = and(_T_1630, _T_1631) else : node _T_1633 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1634 = eq(io.rw.addr, UInt<10>(0h3be)) node _T_1635 = and(_T_1633, _T_1634) node _T_1636 = andr(UInt<2>(0h0)) node _T_1637 = eq(_T_1636, UInt<1>(0h0)) when _T_1637 : node _T_1638 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1639 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1640 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1641 = or(_T_1638, _T_1639) node _T_1642 = or(_T_1641, _T_1640) node _T_1643 = eq(io.rw.addr, UInt<10>(0h3bf)) node _T_1644 = and(_T_1642, _T_1643) else : node _T_1645 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1646 = eq(io.rw.addr, UInt<10>(0h3bf)) node _T_1647 = and(_T_1645, _T_1646) node _T_1648 = andr(UInt<2>(0h1)) node _T_1649 = eq(_T_1648, UInt<1>(0h0)) when _T_1649 : node _T_1650 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1651 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1652 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1653 = or(_T_1650, _T_1651) node _T_1654 = or(_T_1653, _T_1652) node _T_1655 = eq(io.rw.addr, UInt<11>(0h7c1)) node _T_1656 = and(_T_1654, _T_1655) else : node _T_1657 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1658 = eq(io.rw.addr, UInt<11>(0h7c1)) node _T_1659 = and(_T_1657, _T_1658) node _T_1660 = andr(UInt<2>(0h3)) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) when _T_1661 : node _T_1662 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1663 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1664 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1665 = or(_T_1662, _T_1663) node _T_1666 = or(_T_1665, _T_1664) node _T_1667 = eq(io.rw.addr, UInt<12>(0hf12)) node _T_1668 = and(_T_1666, _T_1667) else : node _T_1669 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1670 = eq(io.rw.addr, UInt<12>(0hf12)) node _T_1671 = and(_T_1669, _T_1670) node _T_1672 = andr(UInt<2>(0h3)) node _T_1673 = eq(_T_1672, UInt<1>(0h0)) when _T_1673 : node _T_1674 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1675 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1676 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1677 = or(_T_1674, _T_1675) node _T_1678 = or(_T_1677, _T_1676) node _T_1679 = eq(io.rw.addr, UInt<12>(0hf11)) node _T_1680 = and(_T_1678, _T_1679) else : node _T_1681 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1682 = eq(io.rw.addr, UInt<12>(0hf11)) node _T_1683 = and(_T_1681, _T_1682) node _T_1684 = andr(UInt<2>(0h3)) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1687 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1688 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1689 = or(_T_1686, _T_1687) node _T_1690 = or(_T_1689, _T_1688) node _T_1691 = eq(io.rw.addr, UInt<12>(0hf13)) node _T_1692 = and(_T_1690, _T_1691) else : node _T_1693 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1694 = eq(io.rw.addr, UInt<12>(0hf13)) node _T_1695 = and(_T_1693, _T_1694) node _T_1696 = andr(UInt<2>(0h3)) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1699 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1700 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1701 = or(_T_1698, _T_1699) node _T_1702 = or(_T_1701, _T_1700) node _T_1703 = eq(io.rw.addr, UInt<12>(0hf15)) node _T_1704 = and(_T_1702, _T_1703) else : node _T_1705 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1706 = eq(io.rw.addr, UInt<12>(0hf15)) node _T_1707 = and(_T_1705, _T_1706) wire set_vs_dirty : UInt<1> connect set_vs_dirty, UInt<1>(0h0) wire set_fs_dirty : UInt<1> connect set_fs_dirty, UInt<1>(0h0) connect io.fcsr_rm, reg_frm when io.fcsr_flags.valid : node _reg_fflags_T = or(reg_fflags, io.fcsr_flags.bits) connect reg_fflags, _reg_fflags_T connect set_fs_dirty, UInt<1>(0h1) node _csr_wen_T = eq(io.rw.cmd, UInt<3>(0h6)) node _csr_wen_T_1 = eq(io.rw.cmd, UInt<3>(0h7)) node _csr_wen_T_2 = eq(io.rw.cmd, UInt<3>(0h5)) node _csr_wen_T_3 = or(_csr_wen_T, _csr_wen_T_1) node _csr_wen_T_4 = or(_csr_wen_T_3, _csr_wen_T_2) node _csr_wen_T_5 = eq(io.rw_stall, UInt<1>(0h0)) node csr_wen = and(_csr_wen_T_4, _csr_wen_T_5) node _io_csrw_counter_T = and(UInt<1>(0h1), csr_wen) node _io_csrw_counter_T_1 = geq(io.rw.addr, UInt<12>(0hb00)) node _io_csrw_counter_T_2 = lt(io.rw.addr, UInt<12>(0hb20)) node _io_csrw_counter_T_3 = and(_io_csrw_counter_T_1, _io_csrw_counter_T_2) node _io_csrw_counter_T_4 = geq(io.rw.addr, UInt<12>(0hb80)) node _io_csrw_counter_T_5 = lt(io.rw.addr, UInt<12>(0hba0)) node _io_csrw_counter_T_6 = and(_io_csrw_counter_T_4, _io_csrw_counter_T_5) node _io_csrw_counter_T_7 = or(_io_csrw_counter_T_3, _io_csrw_counter_T_6) node _io_csrw_counter_T_8 = and(_io_csrw_counter_T, _io_csrw_counter_T_7) node _io_csrw_counter_T_9 = bits(io.rw.addr, 4, 0) node _io_csrw_counter_T_10 = dshl(UInt<1>(0h1), _io_csrw_counter_T_9) node _io_csrw_counter_T_11 = mux(_io_csrw_counter_T_8, _io_csrw_counter_T_10, UInt<1>(0h0)) connect io.csrw_counter, _io_csrw_counter_T_11 when csr_wen : when decoded_addr_100_2 : wire new_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} wire _new_mstatus_WIRE : UInt<105> connect _new_mstatus_WIRE, wdata node _new_mstatus_T = bits(_new_mstatus_WIRE, 0, 0) connect new_mstatus.uie, _new_mstatus_T node _new_mstatus_T_1 = bits(_new_mstatus_WIRE, 1, 1) connect new_mstatus.sie, _new_mstatus_T_1 node _new_mstatus_T_2 = bits(_new_mstatus_WIRE, 2, 2) connect new_mstatus.hie, _new_mstatus_T_2 node _new_mstatus_T_3 = bits(_new_mstatus_WIRE, 3, 3) connect new_mstatus.mie, _new_mstatus_T_3 node _new_mstatus_T_4 = bits(_new_mstatus_WIRE, 4, 4) connect new_mstatus.upie, _new_mstatus_T_4 node _new_mstatus_T_5 = bits(_new_mstatus_WIRE, 5, 5) connect new_mstatus.spie, _new_mstatus_T_5 node _new_mstatus_T_6 = bits(_new_mstatus_WIRE, 6, 6) connect new_mstatus.ube, _new_mstatus_T_6 node _new_mstatus_T_7 = bits(_new_mstatus_WIRE, 7, 7) connect new_mstatus.mpie, _new_mstatus_T_7 node _new_mstatus_T_8 = bits(_new_mstatus_WIRE, 8, 8) connect new_mstatus.spp, _new_mstatus_T_8 node _new_mstatus_T_9 = bits(_new_mstatus_WIRE, 10, 9) connect new_mstatus.vs, _new_mstatus_T_9 node _new_mstatus_T_10 = bits(_new_mstatus_WIRE, 12, 11) connect new_mstatus.mpp, _new_mstatus_T_10 node _new_mstatus_T_11 = bits(_new_mstatus_WIRE, 14, 13) connect new_mstatus.fs, _new_mstatus_T_11 node _new_mstatus_T_12 = bits(_new_mstatus_WIRE, 16, 15) connect new_mstatus.xs, _new_mstatus_T_12 node _new_mstatus_T_13 = bits(_new_mstatus_WIRE, 17, 17) connect new_mstatus.mprv, _new_mstatus_T_13 node _new_mstatus_T_14 = bits(_new_mstatus_WIRE, 18, 18) connect new_mstatus.sum, _new_mstatus_T_14 node _new_mstatus_T_15 = bits(_new_mstatus_WIRE, 19, 19) connect new_mstatus.mxr, _new_mstatus_T_15 node _new_mstatus_T_16 = bits(_new_mstatus_WIRE, 20, 20) connect new_mstatus.tvm, _new_mstatus_T_16 node _new_mstatus_T_17 = bits(_new_mstatus_WIRE, 21, 21) connect new_mstatus.tw, _new_mstatus_T_17 node _new_mstatus_T_18 = bits(_new_mstatus_WIRE, 22, 22) connect new_mstatus.tsr, _new_mstatus_T_18 node _new_mstatus_T_19 = bits(_new_mstatus_WIRE, 30, 23) connect new_mstatus.zero1, _new_mstatus_T_19 node _new_mstatus_T_20 = bits(_new_mstatus_WIRE, 31, 31) connect new_mstatus.sd_rv32, _new_mstatus_T_20 node _new_mstatus_T_21 = bits(_new_mstatus_WIRE, 33, 32) connect new_mstatus.uxl, _new_mstatus_T_21 node _new_mstatus_T_22 = bits(_new_mstatus_WIRE, 35, 34) connect new_mstatus.sxl, _new_mstatus_T_22 node _new_mstatus_T_23 = bits(_new_mstatus_WIRE, 36, 36) connect new_mstatus.sbe, _new_mstatus_T_23 node _new_mstatus_T_24 = bits(_new_mstatus_WIRE, 37, 37) connect new_mstatus.mbe, _new_mstatus_T_24 node _new_mstatus_T_25 = bits(_new_mstatus_WIRE, 38, 38) connect new_mstatus.gva, _new_mstatus_T_25 node _new_mstatus_T_26 = bits(_new_mstatus_WIRE, 39, 39) connect new_mstatus.mpv, _new_mstatus_T_26 node _new_mstatus_T_27 = bits(_new_mstatus_WIRE, 62, 40) connect new_mstatus.zero2, _new_mstatus_T_27 node _new_mstatus_T_28 = bits(_new_mstatus_WIRE, 63, 63) connect new_mstatus.sd, _new_mstatus_T_28 node _new_mstatus_T_29 = bits(_new_mstatus_WIRE, 64, 64) connect new_mstatus.v, _new_mstatus_T_29 node _new_mstatus_T_30 = bits(_new_mstatus_WIRE, 66, 65) connect new_mstatus.prv, _new_mstatus_T_30 node _new_mstatus_T_31 = bits(_new_mstatus_WIRE, 67, 67) connect new_mstatus.dv, _new_mstatus_T_31 node _new_mstatus_T_32 = bits(_new_mstatus_WIRE, 69, 68) connect new_mstatus.dprv, _new_mstatus_T_32 node _new_mstatus_T_33 = bits(_new_mstatus_WIRE, 101, 70) connect new_mstatus.isa, _new_mstatus_T_33 node _new_mstatus_T_34 = bits(_new_mstatus_WIRE, 102, 102) connect new_mstatus.wfi, _new_mstatus_T_34 node _new_mstatus_T_35 = bits(_new_mstatus_WIRE, 103, 103) connect new_mstatus.cease, _new_mstatus_T_35 node _new_mstatus_T_36 = bits(_new_mstatus_WIRE, 104, 104) connect new_mstatus.debug, _new_mstatus_T_36 connect reg_mstatus.mie, new_mstatus.mie connect reg_mstatus.mpie, new_mstatus.mpie connect reg_mstatus.mprv, new_mstatus.mprv node _reg_mstatus_mpp_T_2 = eq(new_mstatus.mpp, UInt<2>(0h2)) node _reg_mstatus_mpp_T_3 = mux(_reg_mstatus_mpp_T_2, UInt<1>(0h0), new_mstatus.mpp) connect reg_mstatus.mpp, _reg_mstatus_mpp_T_3 connect reg_mstatus.spp, new_mstatus.spp connect reg_mstatus.spie, new_mstatus.spie connect reg_mstatus.sie, new_mstatus.sie connect reg_mstatus.tw, new_mstatus.tw connect reg_mstatus.tsr, new_mstatus.tsr connect reg_mstatus.mxr, new_mstatus.mxr connect reg_mstatus.sum, new_mstatus.sum connect reg_mstatus.tvm, new_mstatus.tvm node _reg_mstatus_fs_T = orr(new_mstatus.fs) node _reg_mstatus_fs_T_1 = mux(_reg_mstatus_fs_T, UInt<2>(0h3), UInt<2>(0h0)) connect reg_mstatus.fs, _reg_mstatus_fs_T_1 connect reg_mstatus.vs, UInt<1>(0h0) when decoded_addr_94_2 : node f = bits(wdata, 5, 5) node _T_1708 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_1709 = bits(io.pc, 1, 1) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) node _T_1711 = or(_T_1708, _T_1710) node _T_1712 = bits(wdata, 2, 2) node _T_1713 = or(_T_1711, _T_1712) when _T_1713 : node _reg_misa_T = not(wdata) node _reg_misa_T_1 = eq(f, UInt<1>(0h0)) node _reg_misa_T_2 = shl(_reg_misa_T_1, 3) node _reg_misa_T_3 = or(_reg_misa_T, _reg_misa_T_2) node _reg_misa_T_4 = not(_reg_misa_T_3) node _reg_misa_T_5 = and(_reg_misa_T_4, UInt<64>(0h102d)) node _reg_misa_T_6 = not(UInt<64>(0h102d)) node _reg_misa_T_7 = and(reg_misa, _reg_misa_T_6) node _reg_misa_T_8 = or(_reg_misa_T_5, _reg_misa_T_7) connect reg_misa, _reg_misa_T_8 when decoded_addr_108_2 : node new_mip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip) node new_mip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip) node new_mip_lo_lo = cat(new_mip_lo_lo_hi, new_mip_lo_lo_lo) node new_mip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip) node new_mip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip) node new_mip_lo_hi = cat(new_mip_lo_hi_hi, new_mip_lo_hi_lo) node new_mip_lo = cat(new_mip_lo_hi, new_mip_lo_lo) node new_mip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip) node new_mip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip) node new_mip_hi_lo = cat(new_mip_hi_lo_hi, new_mip_hi_lo_lo) node new_mip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip) node new_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1) node new_mip_hi_hi_hi = cat(new_mip_hi_hi_hi_hi, reg_mip.debug) node new_mip_hi_hi = cat(new_mip_hi_hi_hi, new_mip_hi_hi_lo) node new_mip_hi = cat(new_mip_hi_hi, new_mip_hi_lo) node _new_mip_T = cat(new_mip_hi, new_mip_lo) node _new_mip_T_1 = bits(io.rw.cmd, 1, 1) node _new_mip_T_2 = mux(_new_mip_T_1, _new_mip_T, UInt<1>(0h0)) node _new_mip_T_3 = or(_new_mip_T_2, io.rw.wdata) node _new_mip_T_4 = bits(io.rw.cmd, 1, 0) node _new_mip_T_5 = andr(_new_mip_T_4) node _new_mip_T_6 = mux(_new_mip_T_5, io.rw.wdata, UInt<1>(0h0)) node _new_mip_T_7 = not(_new_mip_T_6) node _new_mip_T_8 = and(_new_mip_T_3, _new_mip_T_7) wire new_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} wire _new_mip_WIRE : UInt<16> connect _new_mip_WIRE, _new_mip_T_8 node _new_mip_T_9 = bits(_new_mip_WIRE, 0, 0) connect new_mip.usip, _new_mip_T_9 node _new_mip_T_10 = bits(_new_mip_WIRE, 1, 1) connect new_mip.ssip, _new_mip_T_10 node _new_mip_T_11 = bits(_new_mip_WIRE, 2, 2) connect new_mip.vssip, _new_mip_T_11 node _new_mip_T_12 = bits(_new_mip_WIRE, 3, 3) connect new_mip.msip, _new_mip_T_12 node _new_mip_T_13 = bits(_new_mip_WIRE, 4, 4) connect new_mip.utip, _new_mip_T_13 node _new_mip_T_14 = bits(_new_mip_WIRE, 5, 5) connect new_mip.stip, _new_mip_T_14 node _new_mip_T_15 = bits(_new_mip_WIRE, 6, 6) connect new_mip.vstip, _new_mip_T_15 node _new_mip_T_16 = bits(_new_mip_WIRE, 7, 7) connect new_mip.mtip, _new_mip_T_16 node _new_mip_T_17 = bits(_new_mip_WIRE, 8, 8) connect new_mip.ueip, _new_mip_T_17 node _new_mip_T_18 = bits(_new_mip_WIRE, 9, 9) connect new_mip.seip, _new_mip_T_18 node _new_mip_T_19 = bits(_new_mip_WIRE, 10, 10) connect new_mip.vseip, _new_mip_T_19 node _new_mip_T_20 = bits(_new_mip_WIRE, 11, 11) connect new_mip.meip, _new_mip_T_20 node _new_mip_T_21 = bits(_new_mip_WIRE, 12, 12) connect new_mip.sgeip, _new_mip_T_21 node _new_mip_T_22 = bits(_new_mip_WIRE, 13, 13) connect new_mip.rocc, _new_mip_T_22 node _new_mip_T_23 = bits(_new_mip_WIRE, 14, 14) connect new_mip.debug, _new_mip_T_23 node _new_mip_T_24 = bits(_new_mip_WIRE, 15, 15) connect new_mip.zero1, _new_mip_T_24 connect reg_mip.ssip, new_mip.ssip connect reg_mip.stip, new_mip.stip connect reg_mip.seip, new_mip.seip when decoded_addr_76_2 : node _reg_mie_T = and(wdata, supported_interrupts) connect reg_mie, _reg_mie_T when decoded_addr_132_2 : node _reg_mepc_T = not(wdata) node _reg_mepc_T_1 = or(_reg_mepc_T, UInt<1>(0h1)) node _reg_mepc_T_2 = not(_reg_mepc_T_1) connect reg_mepc, _reg_mepc_T_2 when decoded_addr_129_2 : connect reg_mscratch, wdata when decoded_addr_72_2 : connect reg_mtvec, wdata when decoded_addr_29_2 : node _reg_mcause_T = and(wdata, UInt<64>(0h800000000000000f)) connect reg_mcause, _reg_mcause_T when decoded_addr_136_2 : connect reg_mtval, wdata when decoded_addr_130_2 : node _reg_mcountinhibit_T = not(UInt<64>(0h2)) node _reg_mcountinhibit_T_1 = and(wdata, _reg_mcountinhibit_T) connect reg_mcountinhibit, _reg_mcountinhibit_T_1 when decoded_addr_103_2 : node _T_1714 = bits(wdata, 63, 0) connect small_1, _T_1714 node _large_T_6 = shr(_T_1714, 6) connect large_1, _large_T_6 when decoded_addr_121_2 : node _T_1715 = bits(wdata, 63, 0) connect small, _T_1715 node _large_T_7 = shr(_T_1715, 6) connect large, _large_T_7 when decoded_addr_36_2 : connect set_fs_dirty, UInt<1>(0h1) connect reg_fflags, wdata when decoded_addr_68_2 : connect set_fs_dirty, UInt<1>(0h1) connect reg_frm, wdata when decoded_addr_99_2 : connect set_fs_dirty, UInt<1>(0h1) connect reg_fflags, wdata node _reg_frm_T = shr(wdata, 5) connect reg_frm, _reg_frm_T when decoded_addr_49_2 : wire new_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} wire _new_dcsr_WIRE : UInt<32> connect _new_dcsr_WIRE, wdata node _new_dcsr_T = bits(_new_dcsr_WIRE, 1, 0) connect new_dcsr.prv, _new_dcsr_T node _new_dcsr_T_1 = bits(_new_dcsr_WIRE, 2, 2) connect new_dcsr.step, _new_dcsr_T_1 node _new_dcsr_T_2 = bits(_new_dcsr_WIRE, 4, 3) connect new_dcsr.zero1, _new_dcsr_T_2 node _new_dcsr_T_3 = bits(_new_dcsr_WIRE, 5, 5) connect new_dcsr.v, _new_dcsr_T_3 node _new_dcsr_T_4 = bits(_new_dcsr_WIRE, 8, 6) connect new_dcsr.cause, _new_dcsr_T_4 node _new_dcsr_T_5 = bits(_new_dcsr_WIRE, 9, 9) connect new_dcsr.stoptime, _new_dcsr_T_5 node _new_dcsr_T_6 = bits(_new_dcsr_WIRE, 10, 10) connect new_dcsr.stopcycle, _new_dcsr_T_6 node _new_dcsr_T_7 = bits(_new_dcsr_WIRE, 11, 11) connect new_dcsr.zero2, _new_dcsr_T_7 node _new_dcsr_T_8 = bits(_new_dcsr_WIRE, 12, 12) connect new_dcsr.ebreaku, _new_dcsr_T_8 node _new_dcsr_T_9 = bits(_new_dcsr_WIRE, 13, 13) connect new_dcsr.ebreaks, _new_dcsr_T_9 node _new_dcsr_T_10 = bits(_new_dcsr_WIRE, 14, 14) connect new_dcsr.ebreakh, _new_dcsr_T_10 node _new_dcsr_T_11 = bits(_new_dcsr_WIRE, 15, 15) connect new_dcsr.ebreakm, _new_dcsr_T_11 node _new_dcsr_T_12 = bits(_new_dcsr_WIRE, 27, 16) connect new_dcsr.zero3, _new_dcsr_T_12 node _new_dcsr_T_13 = bits(_new_dcsr_WIRE, 29, 28) connect new_dcsr.zero4, _new_dcsr_T_13 node _new_dcsr_T_14 = bits(_new_dcsr_WIRE, 31, 30) connect new_dcsr.xdebugver, _new_dcsr_T_14 connect reg_dcsr.step, new_dcsr.step connect reg_dcsr.ebreakm, new_dcsr.ebreakm connect reg_dcsr.ebreaks, new_dcsr.ebreaks connect reg_dcsr.ebreaku, new_dcsr.ebreaku node _reg_dcsr_prv_T = eq(new_dcsr.prv, UInt<2>(0h2)) node _reg_dcsr_prv_T_1 = mux(_reg_dcsr_prv_T, UInt<1>(0h0), new_dcsr.prv) connect reg_dcsr.prv, _reg_dcsr_prv_T_1 when decoded_addr_89_2 : node _reg_dpc_T = not(wdata) node _reg_dpc_T_1 = or(_reg_dpc_T, UInt<1>(0h1)) node _reg_dpc_T_2 = not(_reg_dpc_T_1) connect reg_dpc, _reg_dpc_T_2 when decoded_addr_57_2 : connect reg_dscratch0, wdata when decoded_addr_61_2 : wire new_sstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} wire _new_sstatus_WIRE : UInt<105> connect _new_sstatus_WIRE, wdata node _new_sstatus_T = bits(_new_sstatus_WIRE, 0, 0) connect new_sstatus.uie, _new_sstatus_T node _new_sstatus_T_1 = bits(_new_sstatus_WIRE, 1, 1) connect new_sstatus.sie, _new_sstatus_T_1 node _new_sstatus_T_2 = bits(_new_sstatus_WIRE, 2, 2) connect new_sstatus.hie, _new_sstatus_T_2 node _new_sstatus_T_3 = bits(_new_sstatus_WIRE, 3, 3) connect new_sstatus.mie, _new_sstatus_T_3 node _new_sstatus_T_4 = bits(_new_sstatus_WIRE, 4, 4) connect new_sstatus.upie, _new_sstatus_T_4 node _new_sstatus_T_5 = bits(_new_sstatus_WIRE, 5, 5) connect new_sstatus.spie, _new_sstatus_T_5 node _new_sstatus_T_6 = bits(_new_sstatus_WIRE, 6, 6) connect new_sstatus.ube, _new_sstatus_T_6 node _new_sstatus_T_7 = bits(_new_sstatus_WIRE, 7, 7) connect new_sstatus.mpie, _new_sstatus_T_7 node _new_sstatus_T_8 = bits(_new_sstatus_WIRE, 8, 8) connect new_sstatus.spp, _new_sstatus_T_8 node _new_sstatus_T_9 = bits(_new_sstatus_WIRE, 10, 9) connect new_sstatus.vs, _new_sstatus_T_9 node _new_sstatus_T_10 = bits(_new_sstatus_WIRE, 12, 11) connect new_sstatus.mpp, _new_sstatus_T_10 node _new_sstatus_T_11 = bits(_new_sstatus_WIRE, 14, 13) connect new_sstatus.fs, _new_sstatus_T_11 node _new_sstatus_T_12 = bits(_new_sstatus_WIRE, 16, 15) connect new_sstatus.xs, _new_sstatus_T_12 node _new_sstatus_T_13 = bits(_new_sstatus_WIRE, 17, 17) connect new_sstatus.mprv, _new_sstatus_T_13 node _new_sstatus_T_14 = bits(_new_sstatus_WIRE, 18, 18) connect new_sstatus.sum, _new_sstatus_T_14 node _new_sstatus_T_15 = bits(_new_sstatus_WIRE, 19, 19) connect new_sstatus.mxr, _new_sstatus_T_15 node _new_sstatus_T_16 = bits(_new_sstatus_WIRE, 20, 20) connect new_sstatus.tvm, _new_sstatus_T_16 node _new_sstatus_T_17 = bits(_new_sstatus_WIRE, 21, 21) connect new_sstatus.tw, _new_sstatus_T_17 node _new_sstatus_T_18 = bits(_new_sstatus_WIRE, 22, 22) connect new_sstatus.tsr, _new_sstatus_T_18 node _new_sstatus_T_19 = bits(_new_sstatus_WIRE, 30, 23) connect new_sstatus.zero1, _new_sstatus_T_19 node _new_sstatus_T_20 = bits(_new_sstatus_WIRE, 31, 31) connect new_sstatus.sd_rv32, _new_sstatus_T_20 node _new_sstatus_T_21 = bits(_new_sstatus_WIRE, 33, 32) connect new_sstatus.uxl, _new_sstatus_T_21 node _new_sstatus_T_22 = bits(_new_sstatus_WIRE, 35, 34) connect new_sstatus.sxl, _new_sstatus_T_22 node _new_sstatus_T_23 = bits(_new_sstatus_WIRE, 36, 36) connect new_sstatus.sbe, _new_sstatus_T_23 node _new_sstatus_T_24 = bits(_new_sstatus_WIRE, 37, 37) connect new_sstatus.mbe, _new_sstatus_T_24 node _new_sstatus_T_25 = bits(_new_sstatus_WIRE, 38, 38) connect new_sstatus.gva, _new_sstatus_T_25 node _new_sstatus_T_26 = bits(_new_sstatus_WIRE, 39, 39) connect new_sstatus.mpv, _new_sstatus_T_26 node _new_sstatus_T_27 = bits(_new_sstatus_WIRE, 62, 40) connect new_sstatus.zero2, _new_sstatus_T_27 node _new_sstatus_T_28 = bits(_new_sstatus_WIRE, 63, 63) connect new_sstatus.sd, _new_sstatus_T_28 node _new_sstatus_T_29 = bits(_new_sstatus_WIRE, 64, 64) connect new_sstatus.v, _new_sstatus_T_29 node _new_sstatus_T_30 = bits(_new_sstatus_WIRE, 66, 65) connect new_sstatus.prv, _new_sstatus_T_30 node _new_sstatus_T_31 = bits(_new_sstatus_WIRE, 67, 67) connect new_sstatus.dv, _new_sstatus_T_31 node _new_sstatus_T_32 = bits(_new_sstatus_WIRE, 69, 68) connect new_sstatus.dprv, _new_sstatus_T_32 node _new_sstatus_T_33 = bits(_new_sstatus_WIRE, 101, 70) connect new_sstatus.isa, _new_sstatus_T_33 node _new_sstatus_T_34 = bits(_new_sstatus_WIRE, 102, 102) connect new_sstatus.wfi, _new_sstatus_T_34 node _new_sstatus_T_35 = bits(_new_sstatus_WIRE, 103, 103) connect new_sstatus.cease, _new_sstatus_T_35 node _new_sstatus_T_36 = bits(_new_sstatus_WIRE, 104, 104) connect new_sstatus.debug, _new_sstatus_T_36 connect reg_mstatus.sie, new_sstatus.sie connect reg_mstatus.spie, new_sstatus.spie connect reg_mstatus.spp, new_sstatus.spp node _reg_mstatus_fs_T_2 = orr(new_sstatus.fs) node _reg_mstatus_fs_T_3 = mux(_reg_mstatus_fs_T_2, UInt<2>(0h3), UInt<2>(0h0)) connect reg_mstatus.fs, _reg_mstatus_fs_T_3 connect reg_mstatus.vs, UInt<1>(0h0) connect reg_mstatus.mxr, new_sstatus.mxr connect reg_mstatus.sum, new_sstatus.sum when decoded_addr_48_2 : node _new_sip_T = not(read_mideleg) node _new_sip_T_1 = and(read_mip, _new_sip_T) node _new_sip_T_2 = and(wdata, read_mideleg) node _new_sip_T_3 = or(_new_sip_T_1, _new_sip_T_2) wire new_sip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} wire _new_sip_WIRE : UInt<16> connect _new_sip_WIRE, _new_sip_T_3 node _new_sip_T_4 = bits(_new_sip_WIRE, 0, 0) connect new_sip.usip, _new_sip_T_4 node _new_sip_T_5 = bits(_new_sip_WIRE, 1, 1) connect new_sip.ssip, _new_sip_T_5 node _new_sip_T_6 = bits(_new_sip_WIRE, 2, 2) connect new_sip.vssip, _new_sip_T_6 node _new_sip_T_7 = bits(_new_sip_WIRE, 3, 3) connect new_sip.msip, _new_sip_T_7 node _new_sip_T_8 = bits(_new_sip_WIRE, 4, 4) connect new_sip.utip, _new_sip_T_8 node _new_sip_T_9 = bits(_new_sip_WIRE, 5, 5) connect new_sip.stip, _new_sip_T_9 node _new_sip_T_10 = bits(_new_sip_WIRE, 6, 6) connect new_sip.vstip, _new_sip_T_10 node _new_sip_T_11 = bits(_new_sip_WIRE, 7, 7) connect new_sip.mtip, _new_sip_T_11 node _new_sip_T_12 = bits(_new_sip_WIRE, 8, 8) connect new_sip.ueip, _new_sip_T_12 node _new_sip_T_13 = bits(_new_sip_WIRE, 9, 9) connect new_sip.seip, _new_sip_T_13 node _new_sip_T_14 = bits(_new_sip_WIRE, 10, 10) connect new_sip.vseip, _new_sip_T_14 node _new_sip_T_15 = bits(_new_sip_WIRE, 11, 11) connect new_sip.meip, _new_sip_T_15 node _new_sip_T_16 = bits(_new_sip_WIRE, 12, 12) connect new_sip.sgeip, _new_sip_T_16 node _new_sip_T_17 = bits(_new_sip_WIRE, 13, 13) connect new_sip.rocc, _new_sip_T_17 node _new_sip_T_18 = bits(_new_sip_WIRE, 14, 14) connect new_sip.debug, _new_sip_T_18 node _new_sip_T_19 = bits(_new_sip_WIRE, 15, 15) connect new_sip.zero1, _new_sip_T_19 connect reg_mip.ssip, new_sip.ssip when decoded_addr_6_2 : wire new_satp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>} wire _new_satp_WIRE : UInt<64> connect _new_satp_WIRE, wdata node _new_satp_T = bits(_new_satp_WIRE, 43, 0) connect new_satp.ppn, _new_satp_T node _new_satp_T_1 = bits(_new_satp_WIRE, 59, 44) connect new_satp.asid, _new_satp_T_1 node _new_satp_T_2 = bits(_new_satp_WIRE, 63, 60) connect new_satp.mode, _new_satp_T_2 node _T_1716 = eq(new_satp.mode, UInt<1>(0h0)) node _T_1717 = eq(new_satp.mode, UInt<4>(0h8)) node _T_1718 = or(_T_1716, _T_1717) when _T_1718 : node _reg_satp_mode_T = and(new_satp.mode, UInt<4>(0h8)) connect reg_satp.mode, _reg_satp_mode_T node _reg_satp_ppn_T = bits(new_satp.ppn, 19, 0) connect reg_satp.ppn, _reg_satp_ppn_T when decoded_addr_44_2 : node _reg_mie_T_1 = not(sie_mask) node _reg_mie_T_2 = and(reg_mie, _reg_mie_T_1) node _reg_mie_T_3 = and(wdata, sie_mask) node _reg_mie_T_4 = or(_reg_mie_T_2, _reg_mie_T_3) connect reg_mie, _reg_mie_T_4 when decoded_addr_15_2 : connect reg_sscratch, wdata when decoded_addr_28_2 : node _reg_sepc_T = not(wdata) node _reg_sepc_T_1 = or(_reg_sepc_T, UInt<1>(0h1)) node _reg_sepc_T_2 = not(_reg_sepc_T_1) connect reg_sepc, _reg_sepc_T_2 when decoded_addr_25_2 : connect reg_stvec, wdata when decoded_addr_145_2 : node _reg_scause_T = and(wdata, UInt<64>(0h800000000000001f)) connect reg_scause, _reg_scause_T when decoded_addr_93_2 : connect reg_stval, wdata when decoded_addr_123_2 : connect reg_mideleg, wdata when decoded_addr_23_2 : connect reg_medeleg, wdata when decoded_addr_137_2 : connect reg_scounteren, wdata when decoded_addr_69_2 : wire new_envcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} wire _new_envcfg_WIRE : UInt<64> connect _new_envcfg_WIRE, wdata node _new_envcfg_T = bits(_new_envcfg_WIRE, 0, 0) connect new_envcfg.fiom, _new_envcfg_T node _new_envcfg_T_1 = bits(_new_envcfg_WIRE, 3, 1) connect new_envcfg.zero3, _new_envcfg_T_1 node _new_envcfg_T_2 = bits(_new_envcfg_WIRE, 5, 4) connect new_envcfg.cbie, _new_envcfg_T_2 node _new_envcfg_T_3 = bits(_new_envcfg_WIRE, 6, 6) connect new_envcfg.cbcfe, _new_envcfg_T_3 node _new_envcfg_T_4 = bits(_new_envcfg_WIRE, 7, 7) connect new_envcfg.cbze, _new_envcfg_T_4 node _new_envcfg_T_5 = bits(_new_envcfg_WIRE, 61, 8) connect new_envcfg.zero54, _new_envcfg_T_5 node _new_envcfg_T_6 = bits(_new_envcfg_WIRE, 62, 62) connect new_envcfg.pbmte, _new_envcfg_T_6 node _new_envcfg_T_7 = bits(_new_envcfg_WIRE, 63, 63) connect new_envcfg.stce, _new_envcfg_T_7 connect reg_senvcfg.fiom, new_envcfg.fiom when decoded_addr_35_2 : connect reg_mcounteren, wdata when decoded_addr_42_2 : wire new_envcfg_1 : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} wire _new_envcfg_WIRE_1 : UInt<64> connect _new_envcfg_WIRE_1, wdata node _new_envcfg_T_8 = bits(_new_envcfg_WIRE_1, 0, 0) connect new_envcfg_1.fiom, _new_envcfg_T_8 node _new_envcfg_T_9 = bits(_new_envcfg_WIRE_1, 3, 1) connect new_envcfg_1.zero3, _new_envcfg_T_9 node _new_envcfg_T_10 = bits(_new_envcfg_WIRE_1, 5, 4) connect new_envcfg_1.cbie, _new_envcfg_T_10 node _new_envcfg_T_11 = bits(_new_envcfg_WIRE_1, 6, 6) connect new_envcfg_1.cbcfe, _new_envcfg_T_11 node _new_envcfg_T_12 = bits(_new_envcfg_WIRE_1, 7, 7) connect new_envcfg_1.cbze, _new_envcfg_T_12 node _new_envcfg_T_13 = bits(_new_envcfg_WIRE_1, 61, 8) connect new_envcfg_1.zero54, _new_envcfg_T_13 node _new_envcfg_T_14 = bits(_new_envcfg_WIRE_1, 62, 62) connect new_envcfg_1.pbmte, _new_envcfg_T_14 node _new_envcfg_T_15 = bits(_new_envcfg_WIRE_1, 63, 63) connect new_envcfg_1.stce, _new_envcfg_T_15 connect reg_menvcfg.fiom, new_envcfg_1.fiom when decoded_addr_97_2 : connect reg_tselect, wdata node _T_1719 = eq(UInt<1>(0h0), reg_tselect) node _T_1720 = eq(reg_bp[0].control.dmode, UInt<1>(0h0)) node _T_1721 = or(_T_1720, reg_debug) node _T_1722 = and(_T_1719, _T_1721) when _T_1722 : when decoded_addr_10_2 : connect reg_bp[0].address, wdata when decoded_addr_118_2 : skip when decoded_addr_55_2 : wire _reg_bp_0_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _reg_bp_0_control_WIRE_1 : UInt<64> connect _reg_bp_0_control_WIRE_1, wdata node _reg_bp_0_control_T = bits(_reg_bp_0_control_WIRE_1, 0, 0) connect _reg_bp_0_control_WIRE.r, _reg_bp_0_control_T node _reg_bp_0_control_T_1 = bits(_reg_bp_0_control_WIRE_1, 1, 1) connect _reg_bp_0_control_WIRE.w, _reg_bp_0_control_T_1 node _reg_bp_0_control_T_2 = bits(_reg_bp_0_control_WIRE_1, 2, 2) connect _reg_bp_0_control_WIRE.x, _reg_bp_0_control_T_2 node _reg_bp_0_control_T_3 = bits(_reg_bp_0_control_WIRE_1, 3, 3) connect _reg_bp_0_control_WIRE.u, _reg_bp_0_control_T_3 node _reg_bp_0_control_T_4 = bits(_reg_bp_0_control_WIRE_1, 4, 4) connect _reg_bp_0_control_WIRE.s, _reg_bp_0_control_T_4 node _reg_bp_0_control_T_5 = bits(_reg_bp_0_control_WIRE_1, 5, 5) connect _reg_bp_0_control_WIRE.h, _reg_bp_0_control_T_5 node _reg_bp_0_control_T_6 = bits(_reg_bp_0_control_WIRE_1, 6, 6) connect _reg_bp_0_control_WIRE.m, _reg_bp_0_control_T_6 node _reg_bp_0_control_T_7 = bits(_reg_bp_0_control_WIRE_1, 8, 7) connect _reg_bp_0_control_WIRE.tmatch, _reg_bp_0_control_T_7 node _reg_bp_0_control_T_8 = bits(_reg_bp_0_control_WIRE_1, 10, 9) connect _reg_bp_0_control_WIRE.zero, _reg_bp_0_control_T_8 node _reg_bp_0_control_T_9 = bits(_reg_bp_0_control_WIRE_1, 11, 11) connect _reg_bp_0_control_WIRE.chain, _reg_bp_0_control_T_9 node _reg_bp_0_control_T_10 = bits(_reg_bp_0_control_WIRE_1, 12, 12) connect _reg_bp_0_control_WIRE.action, _reg_bp_0_control_T_10 node _reg_bp_0_control_T_11 = bits(_reg_bp_0_control_WIRE_1, 52, 13) connect _reg_bp_0_control_WIRE.reserved, _reg_bp_0_control_T_11 node _reg_bp_0_control_T_12 = bits(_reg_bp_0_control_WIRE_1, 58, 53) connect _reg_bp_0_control_WIRE.maskmax, _reg_bp_0_control_T_12 node _reg_bp_0_control_T_13 = bits(_reg_bp_0_control_WIRE_1, 59, 59) connect _reg_bp_0_control_WIRE.dmode, _reg_bp_0_control_T_13 node _reg_bp_0_control_T_14 = bits(_reg_bp_0_control_WIRE_1, 63, 60) connect _reg_bp_0_control_WIRE.ttype, _reg_bp_0_control_T_14 connect reg_bp[0].control, _reg_bp_0_control_WIRE node newBPC_lo_lo_hi = cat(reg_bp[0].control.x, reg_bp[0].control.w) node newBPC_lo_lo = cat(newBPC_lo_lo_hi, reg_bp[0].control.r) node newBPC_lo_hi_lo = cat(reg_bp[0].control.s, reg_bp[0].control.u) node newBPC_lo_hi_hi = cat(reg_bp[0].control.m, reg_bp[0].control.h) node newBPC_lo_hi = cat(newBPC_lo_hi_hi, newBPC_lo_hi_lo) node newBPC_lo = cat(newBPC_lo_hi, newBPC_lo_lo) node newBPC_hi_lo_lo = cat(reg_bp[0].control.zero, reg_bp[0].control.tmatch) node newBPC_hi_lo_hi = cat(reg_bp[0].control.action, reg_bp[0].control.chain) node newBPC_hi_lo = cat(newBPC_hi_lo_hi, newBPC_hi_lo_lo) node newBPC_hi_hi_lo = cat(reg_bp[0].control.maskmax, reg_bp[0].control.reserved) node newBPC_hi_hi_hi = cat(reg_bp[0].control.ttype, reg_bp[0].control.dmode) node newBPC_hi_hi = cat(newBPC_hi_hi_hi, newBPC_hi_hi_lo) node newBPC_hi = cat(newBPC_hi_hi, newBPC_hi_lo) node _newBPC_T = cat(newBPC_hi, newBPC_lo) node _newBPC_T_1 = bits(io.rw.cmd, 1, 1) node _newBPC_T_2 = mux(_newBPC_T_1, _newBPC_T, UInt<1>(0h0)) node _newBPC_T_3 = or(_newBPC_T_2, io.rw.wdata) node _newBPC_T_4 = bits(io.rw.cmd, 1, 0) node _newBPC_T_5 = andr(_newBPC_T_4) node _newBPC_T_6 = mux(_newBPC_T_5, io.rw.wdata, UInt<1>(0h0)) node _newBPC_T_7 = not(_newBPC_T_6) node _newBPC_T_8 = and(_newBPC_T_3, _newBPC_T_7) wire newBPC : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newBPC_WIRE : UInt<64> connect _newBPC_WIRE, _newBPC_T_8 node _newBPC_T_9 = bits(_newBPC_WIRE, 0, 0) connect newBPC.r, _newBPC_T_9 node _newBPC_T_10 = bits(_newBPC_WIRE, 1, 1) connect newBPC.w, _newBPC_T_10 node _newBPC_T_11 = bits(_newBPC_WIRE, 2, 2) connect newBPC.x, _newBPC_T_11 node _newBPC_T_12 = bits(_newBPC_WIRE, 3, 3) connect newBPC.u, _newBPC_T_12 node _newBPC_T_13 = bits(_newBPC_WIRE, 4, 4) connect newBPC.s, _newBPC_T_13 node _newBPC_T_14 = bits(_newBPC_WIRE, 5, 5) connect newBPC.h, _newBPC_T_14 node _newBPC_T_15 = bits(_newBPC_WIRE, 6, 6) connect newBPC.m, _newBPC_T_15 node _newBPC_T_16 = bits(_newBPC_WIRE, 8, 7) connect newBPC.tmatch, _newBPC_T_16 node _newBPC_T_17 = bits(_newBPC_WIRE, 10, 9) connect newBPC.zero, _newBPC_T_17 node _newBPC_T_18 = bits(_newBPC_WIRE, 11, 11) connect newBPC.chain, _newBPC_T_18 node _newBPC_T_19 = bits(_newBPC_WIRE, 12, 12) connect newBPC.action, _newBPC_T_19 node _newBPC_T_20 = bits(_newBPC_WIRE, 52, 13) connect newBPC.reserved, _newBPC_T_20 node _newBPC_T_21 = bits(_newBPC_WIRE, 58, 53) connect newBPC.maskmax, _newBPC_T_21 node _newBPC_T_22 = bits(_newBPC_WIRE, 59, 59) connect newBPC.dmode, _newBPC_T_22 node _newBPC_T_23 = bits(_newBPC_WIRE, 63, 60) connect newBPC.ttype, _newBPC_T_23 node _dMode_T = and(newBPC.dmode, reg_debug) node _dMode_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _dMode_T_2 = or(UInt<1>(0h0), _dMode_T_1) node dMode = and(_dMode_T, _dMode_T_2) connect reg_bp[0].control.dmode, dMode node _T_1723 = gt(newBPC.action, UInt<1>(0h1)) node _T_1724 = or(dMode, _T_1723) when _T_1724 : connect reg_bp[0].control.action, newBPC.action else : connect reg_bp[0].control.action, UInt<1>(0h0) node _reg_bp_0_control_chain_T = or(UInt<1>(0h0), UInt<1>(0h1)) node _reg_bp_0_control_chain_T_1 = eq(_reg_bp_0_control_chain_T, UInt<1>(0h0)) node _reg_bp_0_control_chain_T_2 = and(newBPC.chain, _reg_bp_0_control_chain_T_1) node _reg_bp_0_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _reg_bp_0_control_chain_T_4 = or(dMode, _reg_bp_0_control_chain_T_3) node _reg_bp_0_control_chain_T_5 = and(_reg_bp_0_control_chain_T_2, _reg_bp_0_control_chain_T_4) connect reg_bp[0].control.chain, _reg_bp_0_control_chain_T_5 node _T_1725 = eq(UInt<1>(0h1), reg_tselect) node _T_1726 = eq(reg_bp[1].control.dmode, UInt<1>(0h0)) node _T_1727 = or(_T_1726, reg_debug) node _T_1728 = and(_T_1725, _T_1727) when _T_1728 : when decoded_addr_10_2 : connect reg_bp[1].address, wdata when decoded_addr_118_2 : skip when decoded_addr_55_2 : wire _reg_bp_1_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _reg_bp_1_control_WIRE_1 : UInt<64> connect _reg_bp_1_control_WIRE_1, wdata node _reg_bp_1_control_T = bits(_reg_bp_1_control_WIRE_1, 0, 0) connect _reg_bp_1_control_WIRE.r, _reg_bp_1_control_T node _reg_bp_1_control_T_1 = bits(_reg_bp_1_control_WIRE_1, 1, 1) connect _reg_bp_1_control_WIRE.w, _reg_bp_1_control_T_1 node _reg_bp_1_control_T_2 = bits(_reg_bp_1_control_WIRE_1, 2, 2) connect _reg_bp_1_control_WIRE.x, _reg_bp_1_control_T_2 node _reg_bp_1_control_T_3 = bits(_reg_bp_1_control_WIRE_1, 3, 3) connect _reg_bp_1_control_WIRE.u, _reg_bp_1_control_T_3 node _reg_bp_1_control_T_4 = bits(_reg_bp_1_control_WIRE_1, 4, 4) connect _reg_bp_1_control_WIRE.s, _reg_bp_1_control_T_4 node _reg_bp_1_control_T_5 = bits(_reg_bp_1_control_WIRE_1, 5, 5) connect _reg_bp_1_control_WIRE.h, _reg_bp_1_control_T_5 node _reg_bp_1_control_T_6 = bits(_reg_bp_1_control_WIRE_1, 6, 6) connect _reg_bp_1_control_WIRE.m, _reg_bp_1_control_T_6 node _reg_bp_1_control_T_7 = bits(_reg_bp_1_control_WIRE_1, 8, 7) connect _reg_bp_1_control_WIRE.tmatch, _reg_bp_1_control_T_7 node _reg_bp_1_control_T_8 = bits(_reg_bp_1_control_WIRE_1, 10, 9) connect _reg_bp_1_control_WIRE.zero, _reg_bp_1_control_T_8 node _reg_bp_1_control_T_9 = bits(_reg_bp_1_control_WIRE_1, 11, 11) connect _reg_bp_1_control_WIRE.chain, _reg_bp_1_control_T_9 node _reg_bp_1_control_T_10 = bits(_reg_bp_1_control_WIRE_1, 12, 12) connect _reg_bp_1_control_WIRE.action, _reg_bp_1_control_T_10 node _reg_bp_1_control_T_11 = bits(_reg_bp_1_control_WIRE_1, 52, 13) connect _reg_bp_1_control_WIRE.reserved, _reg_bp_1_control_T_11 node _reg_bp_1_control_T_12 = bits(_reg_bp_1_control_WIRE_1, 58, 53) connect _reg_bp_1_control_WIRE.maskmax, _reg_bp_1_control_T_12 node _reg_bp_1_control_T_13 = bits(_reg_bp_1_control_WIRE_1, 59, 59) connect _reg_bp_1_control_WIRE.dmode, _reg_bp_1_control_T_13 node _reg_bp_1_control_T_14 = bits(_reg_bp_1_control_WIRE_1, 63, 60) connect _reg_bp_1_control_WIRE.ttype, _reg_bp_1_control_T_14 connect reg_bp[1].control, _reg_bp_1_control_WIRE node newBPC_lo_lo_hi_1 = cat(reg_bp[1].control.x, reg_bp[1].control.w) node newBPC_lo_lo_1 = cat(newBPC_lo_lo_hi_1, reg_bp[1].control.r) node newBPC_lo_hi_lo_1 = cat(reg_bp[1].control.s, reg_bp[1].control.u) node newBPC_lo_hi_hi_1 = cat(reg_bp[1].control.m, reg_bp[1].control.h) node newBPC_lo_hi_1 = cat(newBPC_lo_hi_hi_1, newBPC_lo_hi_lo_1) node newBPC_lo_1 = cat(newBPC_lo_hi_1, newBPC_lo_lo_1) node newBPC_hi_lo_lo_1 = cat(reg_bp[1].control.zero, reg_bp[1].control.tmatch) node newBPC_hi_lo_hi_1 = cat(reg_bp[1].control.action, reg_bp[1].control.chain) node newBPC_hi_lo_1 = cat(newBPC_hi_lo_hi_1, newBPC_hi_lo_lo_1) node newBPC_hi_hi_lo_1 = cat(reg_bp[1].control.maskmax, reg_bp[1].control.reserved) node newBPC_hi_hi_hi_1 = cat(reg_bp[1].control.ttype, reg_bp[1].control.dmode) node newBPC_hi_hi_1 = cat(newBPC_hi_hi_hi_1, newBPC_hi_hi_lo_1) node newBPC_hi_1 = cat(newBPC_hi_hi_1, newBPC_hi_lo_1) node _newBPC_T_24 = cat(newBPC_hi_1, newBPC_lo_1) node _newBPC_T_25 = bits(io.rw.cmd, 1, 1) node _newBPC_T_26 = mux(_newBPC_T_25, _newBPC_T_24, UInt<1>(0h0)) node _newBPC_T_27 = or(_newBPC_T_26, io.rw.wdata) node _newBPC_T_28 = bits(io.rw.cmd, 1, 0) node _newBPC_T_29 = andr(_newBPC_T_28) node _newBPC_T_30 = mux(_newBPC_T_29, io.rw.wdata, UInt<1>(0h0)) node _newBPC_T_31 = not(_newBPC_T_30) node _newBPC_T_32 = and(_newBPC_T_27, _newBPC_T_31) wire newBPC_1 : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newBPC_WIRE_1 : UInt<64> connect _newBPC_WIRE_1, _newBPC_T_32 node _newBPC_T_33 = bits(_newBPC_WIRE_1, 0, 0) connect newBPC_1.r, _newBPC_T_33 node _newBPC_T_34 = bits(_newBPC_WIRE_1, 1, 1) connect newBPC_1.w, _newBPC_T_34 node _newBPC_T_35 = bits(_newBPC_WIRE_1, 2, 2) connect newBPC_1.x, _newBPC_T_35 node _newBPC_T_36 = bits(_newBPC_WIRE_1, 3, 3) connect newBPC_1.u, _newBPC_T_36 node _newBPC_T_37 = bits(_newBPC_WIRE_1, 4, 4) connect newBPC_1.s, _newBPC_T_37 node _newBPC_T_38 = bits(_newBPC_WIRE_1, 5, 5) connect newBPC_1.h, _newBPC_T_38 node _newBPC_T_39 = bits(_newBPC_WIRE_1, 6, 6) connect newBPC_1.m, _newBPC_T_39 node _newBPC_T_40 = bits(_newBPC_WIRE_1, 8, 7) connect newBPC_1.tmatch, _newBPC_T_40 node _newBPC_T_41 = bits(_newBPC_WIRE_1, 10, 9) connect newBPC_1.zero, _newBPC_T_41 node _newBPC_T_42 = bits(_newBPC_WIRE_1, 11, 11) connect newBPC_1.chain, _newBPC_T_42 node _newBPC_T_43 = bits(_newBPC_WIRE_1, 12, 12) connect newBPC_1.action, _newBPC_T_43 node _newBPC_T_44 = bits(_newBPC_WIRE_1, 52, 13) connect newBPC_1.reserved, _newBPC_T_44 node _newBPC_T_45 = bits(_newBPC_WIRE_1, 58, 53) connect newBPC_1.maskmax, _newBPC_T_45 node _newBPC_T_46 = bits(_newBPC_WIRE_1, 59, 59) connect newBPC_1.dmode, _newBPC_T_46 node _newBPC_T_47 = bits(_newBPC_WIRE_1, 63, 60) connect newBPC_1.ttype, _newBPC_T_47 node _dMode_T_3 = and(newBPC_1.dmode, reg_debug) node _dMode_T_4 = eq(reg_bp[0].control.chain, UInt<1>(0h0)) node _dMode_T_5 = or(reg_bp[0].control.dmode, _dMode_T_4) node dMode_1 = and(_dMode_T_3, _dMode_T_5) connect reg_bp[1].control.dmode, dMode_1 node _T_1729 = gt(newBPC_1.action, UInt<1>(0h1)) node _T_1730 = or(dMode_1, _T_1729) when _T_1730 : connect reg_bp[1].control.action, newBPC_1.action else : connect reg_bp[1].control.action, UInt<1>(0h0) node _reg_bp_1_control_chain_T = or(reg_bp[0].control.chain, UInt<1>(0h1)) node _reg_bp_1_control_chain_T_1 = eq(_reg_bp_1_control_chain_T, UInt<1>(0h0)) node _reg_bp_1_control_chain_T_2 = and(newBPC_1.chain, _reg_bp_1_control_chain_T_1) node _reg_bp_1_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _reg_bp_1_control_chain_T_4 = or(dMode_1, _reg_bp_1_control_chain_T_3) node _reg_bp_1_control_chain_T_5 = and(_reg_bp_1_control_chain_T_2, _reg_bp_1_control_chain_T_4) connect reg_bp[1].control.chain, _reg_bp_1_control_chain_T_5 node _T_1731 = eq(reg_pmp[0].cfg.l, UInt<1>(0h0)) node _T_1732 = and(decoded_addr_141_2, _T_1731) when _T_1732 : node _newCfg_T = shr(wdata, 0) wire newCfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE : UInt<8> connect _newCfg_WIRE, _newCfg_T node _newCfg_T_1 = bits(_newCfg_WIRE, 0, 0) connect newCfg.r, _newCfg_T_1 node _newCfg_T_2 = bits(_newCfg_WIRE, 1, 1) connect newCfg.w, _newCfg_T_2 node _newCfg_T_3 = bits(_newCfg_WIRE, 2, 2) connect newCfg.x, _newCfg_T_3 node _newCfg_T_4 = bits(_newCfg_WIRE, 4, 3) connect newCfg.a, _newCfg_T_4 node _newCfg_T_5 = bits(_newCfg_WIRE, 6, 5) connect newCfg.res, _newCfg_T_5 node _newCfg_T_6 = bits(_newCfg_WIRE, 7, 7) connect newCfg.l, _newCfg_T_6 connect reg_pmp[0].cfg, newCfg node _reg_pmp_0_cfg_w_T = and(newCfg.w, newCfg.r) connect reg_pmp[0].cfg.w, _reg_pmp_0_cfg_w_T node _T_1733 = bits(reg_pmp[1].cfg.a, 1, 1) node _T_1734 = eq(_T_1733, UInt<1>(0h0)) node _T_1735 = bits(reg_pmp[1].cfg.a, 0, 0) node _T_1736 = and(_T_1734, _T_1735) node _T_1737 = and(reg_pmp[1].cfg.l, _T_1736) node _T_1738 = or(reg_pmp[0].cfg.l, _T_1737) node _T_1739 = eq(_T_1738, UInt<1>(0h0)) node _T_1740 = and(decoded_addr_104_2, _T_1739) when _T_1740 : connect reg_pmp[0].addr, wdata node _T_1741 = eq(reg_pmp[1].cfg.l, UInt<1>(0h0)) node _T_1742 = and(decoded_addr_141_2, _T_1741) when _T_1742 : node _newCfg_T_7 = shr(wdata, 8) wire newCfg_1 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_1 : UInt<8> connect _newCfg_WIRE_1, _newCfg_T_7 node _newCfg_T_8 = bits(_newCfg_WIRE_1, 0, 0) connect newCfg_1.r, _newCfg_T_8 node _newCfg_T_9 = bits(_newCfg_WIRE_1, 1, 1) connect newCfg_1.w, _newCfg_T_9 node _newCfg_T_10 = bits(_newCfg_WIRE_1, 2, 2) connect newCfg_1.x, _newCfg_T_10 node _newCfg_T_11 = bits(_newCfg_WIRE_1, 4, 3) connect newCfg_1.a, _newCfg_T_11 node _newCfg_T_12 = bits(_newCfg_WIRE_1, 6, 5) connect newCfg_1.res, _newCfg_T_12 node _newCfg_T_13 = bits(_newCfg_WIRE_1, 7, 7) connect newCfg_1.l, _newCfg_T_13 connect reg_pmp[1].cfg, newCfg_1 node _reg_pmp_1_cfg_w_T = and(newCfg_1.w, newCfg_1.r) connect reg_pmp[1].cfg.w, _reg_pmp_1_cfg_w_T node _T_1743 = bits(reg_pmp[2].cfg.a, 1, 1) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) node _T_1745 = bits(reg_pmp[2].cfg.a, 0, 0) node _T_1746 = and(_T_1744, _T_1745) node _T_1747 = and(reg_pmp[2].cfg.l, _T_1746) node _T_1748 = or(reg_pmp[1].cfg.l, _T_1747) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = and(decoded_addr_8_2, _T_1749) when _T_1750 : connect reg_pmp[1].addr, wdata node _T_1751 = eq(reg_pmp[2].cfg.l, UInt<1>(0h0)) node _T_1752 = and(decoded_addr_141_2, _T_1751) when _T_1752 : node _newCfg_T_14 = shr(wdata, 16) wire newCfg_2 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_2 : UInt<8> connect _newCfg_WIRE_2, _newCfg_T_14 node _newCfg_T_15 = bits(_newCfg_WIRE_2, 0, 0) connect newCfg_2.r, _newCfg_T_15 node _newCfg_T_16 = bits(_newCfg_WIRE_2, 1, 1) connect newCfg_2.w, _newCfg_T_16 node _newCfg_T_17 = bits(_newCfg_WIRE_2, 2, 2) connect newCfg_2.x, _newCfg_T_17 node _newCfg_T_18 = bits(_newCfg_WIRE_2, 4, 3) connect newCfg_2.a, _newCfg_T_18 node _newCfg_T_19 = bits(_newCfg_WIRE_2, 6, 5) connect newCfg_2.res, _newCfg_T_19 node _newCfg_T_20 = bits(_newCfg_WIRE_2, 7, 7) connect newCfg_2.l, _newCfg_T_20 connect reg_pmp[2].cfg, newCfg_2 node _reg_pmp_2_cfg_w_T = and(newCfg_2.w, newCfg_2.r) connect reg_pmp[2].cfg.w, _reg_pmp_2_cfg_w_T node _T_1753 = bits(reg_pmp[3].cfg.a, 1, 1) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) node _T_1755 = bits(reg_pmp[3].cfg.a, 0, 0) node _T_1756 = and(_T_1754, _T_1755) node _T_1757 = and(reg_pmp[3].cfg.l, _T_1756) node _T_1758 = or(reg_pmp[2].cfg.l, _T_1757) node _T_1759 = eq(_T_1758, UInt<1>(0h0)) node _T_1760 = and(decoded_addr_125_2, _T_1759) when _T_1760 : connect reg_pmp[2].addr, wdata node _T_1761 = eq(reg_pmp[3].cfg.l, UInt<1>(0h0)) node _T_1762 = and(decoded_addr_141_2, _T_1761) when _T_1762 : node _newCfg_T_21 = shr(wdata, 24) wire newCfg_3 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_3 : UInt<8> connect _newCfg_WIRE_3, _newCfg_T_21 node _newCfg_T_22 = bits(_newCfg_WIRE_3, 0, 0) connect newCfg_3.r, _newCfg_T_22 node _newCfg_T_23 = bits(_newCfg_WIRE_3, 1, 1) connect newCfg_3.w, _newCfg_T_23 node _newCfg_T_24 = bits(_newCfg_WIRE_3, 2, 2) connect newCfg_3.x, _newCfg_T_24 node _newCfg_T_25 = bits(_newCfg_WIRE_3, 4, 3) connect newCfg_3.a, _newCfg_T_25 node _newCfg_T_26 = bits(_newCfg_WIRE_3, 6, 5) connect newCfg_3.res, _newCfg_T_26 node _newCfg_T_27 = bits(_newCfg_WIRE_3, 7, 7) connect newCfg_3.l, _newCfg_T_27 connect reg_pmp[3].cfg, newCfg_3 node _reg_pmp_3_cfg_w_T = and(newCfg_3.w, newCfg_3.r) connect reg_pmp[3].cfg.w, _reg_pmp_3_cfg_w_T node _T_1763 = bits(reg_pmp[4].cfg.a, 1, 1) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) node _T_1765 = bits(reg_pmp[4].cfg.a, 0, 0) node _T_1766 = and(_T_1764, _T_1765) node _T_1767 = and(reg_pmp[4].cfg.l, _T_1766) node _T_1768 = or(reg_pmp[3].cfg.l, _T_1767) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = and(decoded_addr_85_2, _T_1769) when _T_1770 : connect reg_pmp[3].addr, wdata node _T_1771 = eq(reg_pmp[4].cfg.l, UInt<1>(0h0)) node _T_1772 = and(decoded_addr_141_2, _T_1771) when _T_1772 : node _newCfg_T_28 = shr(wdata, 32) wire newCfg_4 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_4 : UInt<8> connect _newCfg_WIRE_4, _newCfg_T_28 node _newCfg_T_29 = bits(_newCfg_WIRE_4, 0, 0) connect newCfg_4.r, _newCfg_T_29 node _newCfg_T_30 = bits(_newCfg_WIRE_4, 1, 1) connect newCfg_4.w, _newCfg_T_30 node _newCfg_T_31 = bits(_newCfg_WIRE_4, 2, 2) connect newCfg_4.x, _newCfg_T_31 node _newCfg_T_32 = bits(_newCfg_WIRE_4, 4, 3) connect newCfg_4.a, _newCfg_T_32 node _newCfg_T_33 = bits(_newCfg_WIRE_4, 6, 5) connect newCfg_4.res, _newCfg_T_33 node _newCfg_T_34 = bits(_newCfg_WIRE_4, 7, 7) connect newCfg_4.l, _newCfg_T_34 connect reg_pmp[4].cfg, newCfg_4 node _reg_pmp_4_cfg_w_T = and(newCfg_4.w, newCfg_4.r) connect reg_pmp[4].cfg.w, _reg_pmp_4_cfg_w_T node _T_1773 = bits(reg_pmp[5].cfg.a, 1, 1) node _T_1774 = eq(_T_1773, UInt<1>(0h0)) node _T_1775 = bits(reg_pmp[5].cfg.a, 0, 0) node _T_1776 = and(_T_1774, _T_1775) node _T_1777 = and(reg_pmp[5].cfg.l, _T_1776) node _T_1778 = or(reg_pmp[4].cfg.l, _T_1777) node _T_1779 = eq(_T_1778, UInt<1>(0h0)) node _T_1780 = and(decoded_addr_54_2, _T_1779) when _T_1780 : connect reg_pmp[4].addr, wdata node _T_1781 = eq(reg_pmp[5].cfg.l, UInt<1>(0h0)) node _T_1782 = and(decoded_addr_141_2, _T_1781) when _T_1782 : node _newCfg_T_35 = shr(wdata, 40) wire newCfg_5 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_5 : UInt<8> connect _newCfg_WIRE_5, _newCfg_T_35 node _newCfg_T_36 = bits(_newCfg_WIRE_5, 0, 0) connect newCfg_5.r, _newCfg_T_36 node _newCfg_T_37 = bits(_newCfg_WIRE_5, 1, 1) connect newCfg_5.w, _newCfg_T_37 node _newCfg_T_38 = bits(_newCfg_WIRE_5, 2, 2) connect newCfg_5.x, _newCfg_T_38 node _newCfg_T_39 = bits(_newCfg_WIRE_5, 4, 3) connect newCfg_5.a, _newCfg_T_39 node _newCfg_T_40 = bits(_newCfg_WIRE_5, 6, 5) connect newCfg_5.res, _newCfg_T_40 node _newCfg_T_41 = bits(_newCfg_WIRE_5, 7, 7) connect newCfg_5.l, _newCfg_T_41 connect reg_pmp[5].cfg, newCfg_5 node _reg_pmp_5_cfg_w_T = and(newCfg_5.w, newCfg_5.r) connect reg_pmp[5].cfg.w, _reg_pmp_5_cfg_w_T node _T_1783 = bits(reg_pmp[6].cfg.a, 1, 1) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) node _T_1785 = bits(reg_pmp[6].cfg.a, 0, 0) node _T_1786 = and(_T_1784, _T_1785) node _T_1787 = and(reg_pmp[6].cfg.l, _T_1786) node _T_1788 = or(reg_pmp[5].cfg.l, _T_1787) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) node _T_1790 = and(decoded_addr_20_2, _T_1789) when _T_1790 : connect reg_pmp[5].addr, wdata node _T_1791 = eq(reg_pmp[6].cfg.l, UInt<1>(0h0)) node _T_1792 = and(decoded_addr_141_2, _T_1791) when _T_1792 : node _newCfg_T_42 = shr(wdata, 48) wire newCfg_6 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_6 : UInt<8> connect _newCfg_WIRE_6, _newCfg_T_42 node _newCfg_T_43 = bits(_newCfg_WIRE_6, 0, 0) connect newCfg_6.r, _newCfg_T_43 node _newCfg_T_44 = bits(_newCfg_WIRE_6, 1, 1) connect newCfg_6.w, _newCfg_T_44 node _newCfg_T_45 = bits(_newCfg_WIRE_6, 2, 2) connect newCfg_6.x, _newCfg_T_45 node _newCfg_T_46 = bits(_newCfg_WIRE_6, 4, 3) connect newCfg_6.a, _newCfg_T_46 node _newCfg_T_47 = bits(_newCfg_WIRE_6, 6, 5) connect newCfg_6.res, _newCfg_T_47 node _newCfg_T_48 = bits(_newCfg_WIRE_6, 7, 7) connect newCfg_6.l, _newCfg_T_48 connect reg_pmp[6].cfg, newCfg_6 node _reg_pmp_6_cfg_w_T = and(newCfg_6.w, newCfg_6.r) connect reg_pmp[6].cfg.w, _reg_pmp_6_cfg_w_T node _T_1793 = bits(reg_pmp[7].cfg.a, 1, 1) node _T_1794 = eq(_T_1793, UInt<1>(0h0)) node _T_1795 = bits(reg_pmp[7].cfg.a, 0, 0) node _T_1796 = and(_T_1794, _T_1795) node _T_1797 = and(reg_pmp[7].cfg.l, _T_1796) node _T_1798 = or(reg_pmp[6].cfg.l, _T_1797) node _T_1799 = eq(_T_1798, UInt<1>(0h0)) node _T_1800 = and(decoded_addr_135_2, _T_1799) when _T_1800 : connect reg_pmp[6].addr, wdata node _T_1801 = eq(reg_pmp[7].cfg.l, UInt<1>(0h0)) node _T_1802 = and(decoded_addr_141_2, _T_1801) when _T_1802 : node _newCfg_T_49 = shr(wdata, 56) wire newCfg_7 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_7 : UInt<8> connect _newCfg_WIRE_7, _newCfg_T_49 node _newCfg_T_50 = bits(_newCfg_WIRE_7, 0, 0) connect newCfg_7.r, _newCfg_T_50 node _newCfg_T_51 = bits(_newCfg_WIRE_7, 1, 1) connect newCfg_7.w, _newCfg_T_51 node _newCfg_T_52 = bits(_newCfg_WIRE_7, 2, 2) connect newCfg_7.x, _newCfg_T_52 node _newCfg_T_53 = bits(_newCfg_WIRE_7, 4, 3) connect newCfg_7.a, _newCfg_T_53 node _newCfg_T_54 = bits(_newCfg_WIRE_7, 6, 5) connect newCfg_7.res, _newCfg_T_54 node _newCfg_T_55 = bits(_newCfg_WIRE_7, 7, 7) connect newCfg_7.l, _newCfg_T_55 connect reg_pmp[7].cfg, newCfg_7 node _reg_pmp_7_cfg_w_T = and(newCfg_7.w, newCfg_7.r) connect reg_pmp[7].cfg.w, _reg_pmp_7_cfg_w_T node _T_1803 = bits(reg_pmp[7].cfg.a, 1, 1) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) node _T_1805 = bits(reg_pmp[7].cfg.a, 0, 0) node _T_1806 = and(_T_1804, _T_1805) node _T_1807 = and(reg_pmp[7].cfg.l, _T_1806) node _T_1808 = or(reg_pmp[7].cfg.l, _T_1807) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) node _T_1810 = and(decoded_addr_115_2, _T_1809) when _T_1810 : connect reg_pmp[7].addr, wdata when decoded_addr_18_2 : node _reg_custom_0_T = and(wdata, UInt<64>(0h208)) node _reg_custom_0_T_1 = not(UInt<64>(0h208)) node _reg_custom_0_T_2 = and(reg_custom_0, _reg_custom_0_T_1) node _reg_custom_0_T_3 = or(_reg_custom_0_T, _reg_custom_0_T_2) connect reg_custom_0, _reg_custom_0_T_3 connect io.customCSRs[0].wen, UInt<1>(0h1) when decoded_addr_3_2 : node _reg_custom_1_T = and(wdata, UInt<64>(0h0)) node _reg_custom_1_T_1 = not(UInt<64>(0h0)) node _reg_custom_1_T_2 = and(reg_custom_1, _reg_custom_1_T_1) node _reg_custom_1_T_3 = or(_reg_custom_1_T, _reg_custom_1_T_2) connect reg_custom_1, _reg_custom_1_T_3 connect io.customCSRs[1].wen, UInt<1>(0h1) when decoded_addr_38_2 : node _reg_custom_2_T = and(wdata, UInt<64>(0h0)) node _reg_custom_2_T_1 = not(UInt<64>(0h0)) node _reg_custom_2_T_2 = and(reg_custom_2, _reg_custom_2_T_1) node _reg_custom_2_T_3 = or(_reg_custom_2_T, _reg_custom_2_T_2) connect reg_custom_2, _reg_custom_2_T_3 connect io.customCSRs[2].wen, UInt<1>(0h1) when decoded_addr_127_2 : node _reg_custom_3_T = and(wdata, UInt<64>(0h0)) node _reg_custom_3_T_1 = not(UInt<64>(0h0)) node _reg_custom_3_T_2 = and(reg_custom_3, _reg_custom_3_T_1) node _reg_custom_3_T_3 = or(_reg_custom_3_T, _reg_custom_3_T_2) connect reg_custom_3, _reg_custom_3_T_3 connect io.customCSRs[3].wen, UInt<1>(0h1) when io.customCSRs[0].set : node _reg_custom_0_T_4 = and(io.customCSRs[0].sdata, UInt<64>(0h208)) node _reg_custom_0_T_5 = not(UInt<64>(0h208)) node _reg_custom_0_T_6 = and(reg_custom_0, _reg_custom_0_T_5) node _reg_custom_0_T_7 = or(_reg_custom_0_T_4, _reg_custom_0_T_6) connect reg_custom_0, _reg_custom_0_T_7 when io.customCSRs[1].set : node _reg_custom_1_T_4 = and(io.customCSRs[1].sdata, UInt<64>(0h0)) node _reg_custom_1_T_5 = not(UInt<64>(0h0)) node _reg_custom_1_T_6 = and(reg_custom_1, _reg_custom_1_T_5) node _reg_custom_1_T_7 = or(_reg_custom_1_T_4, _reg_custom_1_T_6) connect reg_custom_1, _reg_custom_1_T_7 when io.customCSRs[2].set : node _reg_custom_2_T_4 = and(io.customCSRs[2].sdata, UInt<64>(0h0)) node _reg_custom_2_T_5 = not(UInt<64>(0h0)) node _reg_custom_2_T_6 = and(reg_custom_2, _reg_custom_2_T_5) node _reg_custom_2_T_7 = or(_reg_custom_2_T_4, _reg_custom_2_T_6) connect reg_custom_2, _reg_custom_2_T_7 when io.customCSRs[3].set : node _reg_custom_3_T_4 = and(io.customCSRs[3].sdata, UInt<64>(0h0)) node _reg_custom_3_T_5 = not(UInt<64>(0h0)) node _reg_custom_3_T_6 = and(reg_custom_3, _reg_custom_3_T_5) node _reg_custom_3_T_7 = or(_reg_custom_3_T_4, _reg_custom_3_T_6) connect reg_custom_3, _reg_custom_3_T_7 node _T_1811 = asUInt(reset) when _T_1811 : connect reg_satp.mode, UInt<1>(0h0) connect reg_vsatp.mode, UInt<1>(0h0) connect reg_hgatp.mode, UInt<1>(0h0) connect reg_vsatp.mode, UInt<1>(0h0) connect reg_vsatp.ppn, UInt<1>(0h0) connect reg_vsatp.asid, UInt<1>(0h0) connect reg_hgatp.mode, UInt<1>(0h0) connect reg_hgatp.ppn, UInt<1>(0h0) connect reg_hgatp.asid, UInt<1>(0h0) connect reg_satp.asid, UInt<1>(0h0) connect reg_vsatp.asid, UInt<1>(0h0) connect reg_hgatp.asid, UInt<1>(0h0) connect reg_vsstatus.xs, UInt<1>(0h0) connect reg_tselect, UInt<1>(0h0) connect reg_bp[0].control.ttype, UInt<2>(0h2) connect reg_bp[0].control.maskmax, UInt<3>(0h4) connect reg_bp[0].control.reserved, UInt<1>(0h0) connect reg_bp[0].control.zero, UInt<1>(0h0) connect reg_bp[0].control.h, UInt<1>(0h0) node _T_1812 = asUInt(reset) when _T_1812 : connect reg_bp[0].control.action, UInt<1>(0h0) connect reg_bp[0].control.dmode, UInt<1>(0h0) connect reg_bp[0].control.chain, UInt<1>(0h0) connect reg_bp[0].control.r, UInt<1>(0h0) connect reg_bp[0].control.w, UInt<1>(0h0) connect reg_bp[0].control.x, UInt<1>(0h0) connect reg_bp[1].control.ttype, UInt<2>(0h2) connect reg_bp[1].control.maskmax, UInt<3>(0h4) connect reg_bp[1].control.reserved, UInt<1>(0h0) connect reg_bp[1].control.zero, UInt<1>(0h0) connect reg_bp[1].control.h, UInt<1>(0h0) node _T_1813 = asUInt(reset) when _T_1813 : connect reg_bp[1].control.action, UInt<1>(0h0) connect reg_bp[1].control.dmode, UInt<1>(0h0) connect reg_bp[1].control.chain, UInt<1>(0h0) connect reg_bp[1].control.r, UInt<1>(0h0) connect reg_bp[1].control.w, UInt<1>(0h0) connect reg_bp[1].control.x, UInt<1>(0h0) connect reg_bp[0].textra.mselect, UInt<1>(0h0) connect reg_bp[0].textra.sselect, UInt<1>(0h0) connect reg_bp[1].textra.mselect, UInt<1>(0h0) connect reg_bp[1].textra.sselect, UInt<1>(0h0) wire _reg_bp_1_WIRE : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}} connect _reg_bp_1_WIRE.textra.sselect, UInt<1>(0h0) connect _reg_bp_1_WIRE.textra.pad1, UInt<1>(0h0) invalidate _reg_bp_1_WIRE.textra.svalue connect _reg_bp_1_WIRE.textra.pad2, UInt<48>(0h0) connect _reg_bp_1_WIRE.textra.mselect, UInt<1>(0h0) invalidate _reg_bp_1_WIRE.textra.mvalue connect _reg_bp_1_WIRE.address, UInt<39>(0h0) connect _reg_bp_1_WIRE.control.r, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.w, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.x, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.u, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.s, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.h, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.m, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.tmatch, UInt<2>(0h0) connect _reg_bp_1_WIRE.control.zero, UInt<2>(0h0) connect _reg_bp_1_WIRE.control.chain, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.action, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.reserved, UInt<40>(0h0) connect _reg_bp_1_WIRE.control.maskmax, UInt<6>(0h0) connect _reg_bp_1_WIRE.control.dmode, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.ttype, UInt<4>(0h0) connect reg_bp[1], _reg_bp_1_WIRE connect reg_pmp[0].cfg.res, UInt<1>(0h0) node _T_1814 = asUInt(reset) when _T_1814 : connect reg_pmp[0].cfg.a, UInt<1>(0h0) connect reg_pmp[0].cfg.l, UInt<1>(0h0) connect reg_pmp[1].cfg.res, UInt<1>(0h0) node _T_1815 = asUInt(reset) when _T_1815 : connect reg_pmp[1].cfg.a, UInt<1>(0h0) connect reg_pmp[1].cfg.l, UInt<1>(0h0) connect reg_pmp[2].cfg.res, UInt<1>(0h0) node _T_1816 = asUInt(reset) when _T_1816 : connect reg_pmp[2].cfg.a, UInt<1>(0h0) connect reg_pmp[2].cfg.l, UInt<1>(0h0) connect reg_pmp[3].cfg.res, UInt<1>(0h0) node _T_1817 = asUInt(reset) when _T_1817 : connect reg_pmp[3].cfg.a, UInt<1>(0h0) connect reg_pmp[3].cfg.l, UInt<1>(0h0) connect reg_pmp[4].cfg.res, UInt<1>(0h0) node _T_1818 = asUInt(reset) when _T_1818 : connect reg_pmp[4].cfg.a, UInt<1>(0h0) connect reg_pmp[4].cfg.l, UInt<1>(0h0) connect reg_pmp[5].cfg.res, UInt<1>(0h0) node _T_1819 = asUInt(reset) when _T_1819 : connect reg_pmp[5].cfg.a, UInt<1>(0h0) connect reg_pmp[5].cfg.l, UInt<1>(0h0) connect reg_pmp[6].cfg.res, UInt<1>(0h0) node _T_1820 = asUInt(reset) when _T_1820 : connect reg_pmp[6].cfg.a, UInt<1>(0h0) connect reg_pmp[6].cfg.l, UInt<1>(0h0) connect reg_pmp[7].cfg.res, UInt<1>(0h0) node _T_1821 = asUInt(reset) when _T_1821 : connect reg_pmp[7].cfg.a, UInt<1>(0h0) connect reg_pmp[7].cfg.l, UInt<1>(0h0) node _io_trace_0_exception_T = geq(io.retire, UInt<1>(0h0)) node _io_trace_0_exception_T_1 = and(_io_trace_0_exception_T, exception) connect io.trace[0].exception, _io_trace_0_exception_T_1 node _io_trace_0_valid_T = gt(io.retire, UInt<1>(0h0)) node _io_trace_0_valid_T_1 = or(_io_trace_0_valid_T, io.trace[0].exception) connect io.trace[0].valid, _io_trace_0_valid_T_1 connect io.trace[0].insn, io.inst[0] connect io.trace[0].iaddr, io.pc node _io_trace_0_priv_T = cat(reg_debug, reg_mstatus.prv) connect io.trace[0].priv, _io_trace_0_priv_T connect io.trace[0].cause, cause node _io_trace_0_interrupt_T = bits(cause, 63, 63) connect io.trace[0].interrupt, _io_trace_0_interrupt_T connect io.trace[0].tval, io.tval
module CSRFile( // @[CSR.scala:377:7] input clock, // @[CSR.scala:377:7] input reset, // @[CSR.scala:377:7] input io_ungated_clock, // @[CSR.scala:384:14] input io_interrupts_debug, // @[CSR.scala:384:14] input io_interrupts_mtip, // @[CSR.scala:384:14] input io_interrupts_msip, // @[CSR.scala:384:14] input io_interrupts_meip, // @[CSR.scala:384:14] input io_interrupts_seip, // @[CSR.scala:384:14] input [1:0] io_hartid, // @[CSR.scala:384:14] input [11:0] io_rw_addr, // @[CSR.scala:384:14] input [2:0] io_rw_cmd, // @[CSR.scala:384:14] output [63:0] io_rw_rdata, // @[CSR.scala:384:14] input [63:0] io_rw_wdata, // @[CSR.scala:384:14] input [31:0] io_decode_0_inst, // @[CSR.scala:384:14] output io_decode_0_fp_illegal, // @[CSR.scala:384:14] output io_decode_0_fp_csr, // @[CSR.scala:384:14] output io_decode_0_read_illegal, // @[CSR.scala:384:14] output io_decode_0_write_illegal, // @[CSR.scala:384:14] output io_decode_0_write_flush, // @[CSR.scala:384:14] output io_decode_0_system_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_access_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_system_illegal, // @[CSR.scala:384:14] output io_csr_stall, // @[CSR.scala:384:14] output io_eret, // @[CSR.scala:384:14] output io_singleStep, // @[CSR.scala:384:14] output io_status_debug, // @[CSR.scala:384:14] output io_status_wfi, // @[CSR.scala:384:14] output [31:0] io_status_isa, // @[CSR.scala:384:14] output [1:0] io_status_dprv, // @[CSR.scala:384:14] output io_status_dv, // @[CSR.scala:384:14] output [1:0] io_status_prv, // @[CSR.scala:384:14] output io_status_v, // @[CSR.scala:384:14] output io_status_mxr, // @[CSR.scala:384:14] output io_status_sum, // @[CSR.scala:384:14] output [3:0] io_ptbr_mode, // @[CSR.scala:384:14] output [43:0] io_ptbr_ppn, // @[CSR.scala:384:14] output [39:0] io_evec, // @[CSR.scala:384:14] input io_exception, // @[CSR.scala:384:14] input io_retire, // @[CSR.scala:384:14] input [63:0] io_cause, // @[CSR.scala:384:14] input [39:0] io_pc, // @[CSR.scala:384:14] input [39:0] io_tval, // @[CSR.scala:384:14] input io_gva, // @[CSR.scala:384:14] output [63:0] io_time, // @[CSR.scala:384:14] output [2:0] io_fcsr_rm, // @[CSR.scala:384:14] input io_fcsr_flags_valid, // @[CSR.scala:384:14] input [4:0] io_fcsr_flags_bits, // @[CSR.scala:384:14] output io_interrupt, // @[CSR.scala:384:14] output [63:0] io_interrupt_cause, // @[CSR.scala:384:14] output io_bp_0_control_action, // @[CSR.scala:384:14] output [1:0] io_bp_0_control_tmatch, // @[CSR.scala:384:14] output io_bp_0_control_m, // @[CSR.scala:384:14] output io_bp_0_control_s, // @[CSR.scala:384:14] output io_bp_0_control_u, // @[CSR.scala:384:14] output io_bp_0_control_x, // @[CSR.scala:384:14] output io_bp_0_control_w, // @[CSR.scala:384:14] output io_bp_0_control_r, // @[CSR.scala:384:14] output [38:0] io_bp_0_address, // @[CSR.scala:384:14] output io_pmp_0_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_0_cfg_a, // @[CSR.scala:384:14] output io_pmp_0_cfg_x, // @[CSR.scala:384:14] output io_pmp_0_cfg_w, // @[CSR.scala:384:14] output io_pmp_0_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_0_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_0_mask, // @[CSR.scala:384:14] output io_pmp_1_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_1_cfg_a, // @[CSR.scala:384:14] output io_pmp_1_cfg_x, // @[CSR.scala:384:14] output io_pmp_1_cfg_w, // @[CSR.scala:384:14] output io_pmp_1_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_1_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_1_mask, // @[CSR.scala:384:14] output io_pmp_2_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_2_cfg_a, // @[CSR.scala:384:14] output io_pmp_2_cfg_x, // @[CSR.scala:384:14] output io_pmp_2_cfg_w, // @[CSR.scala:384:14] output io_pmp_2_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_2_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_2_mask, // @[CSR.scala:384:14] output io_pmp_3_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_3_cfg_a, // @[CSR.scala:384:14] output io_pmp_3_cfg_x, // @[CSR.scala:384:14] output io_pmp_3_cfg_w, // @[CSR.scala:384:14] output io_pmp_3_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_3_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_3_mask, // @[CSR.scala:384:14] output io_pmp_4_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_4_cfg_a, // @[CSR.scala:384:14] output io_pmp_4_cfg_x, // @[CSR.scala:384:14] output io_pmp_4_cfg_w, // @[CSR.scala:384:14] output io_pmp_4_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_4_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_4_mask, // @[CSR.scala:384:14] output io_pmp_5_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_5_cfg_a, // @[CSR.scala:384:14] output io_pmp_5_cfg_x, // @[CSR.scala:384:14] output io_pmp_5_cfg_w, // @[CSR.scala:384:14] output io_pmp_5_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_5_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_5_mask, // @[CSR.scala:384:14] output io_pmp_6_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_6_cfg_a, // @[CSR.scala:384:14] output io_pmp_6_cfg_x, // @[CSR.scala:384:14] output io_pmp_6_cfg_w, // @[CSR.scala:384:14] output io_pmp_6_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_6_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_6_mask, // @[CSR.scala:384:14] output io_pmp_7_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_7_cfg_a, // @[CSR.scala:384:14] output io_pmp_7_cfg_x, // @[CSR.scala:384:14] output io_pmp_7_cfg_w, // @[CSR.scala:384:14] output io_pmp_7_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_7_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_7_mask, // @[CSR.scala:384:14] output io_inhibit_cycle, // @[CSR.scala:384:14] input [31:0] io_inst_0, // @[CSR.scala:384:14] output io_trace_0_valid, // @[CSR.scala:384:14] output [39:0] io_trace_0_iaddr, // @[CSR.scala:384:14] output [31:0] io_trace_0_insn, // @[CSR.scala:384:14] output io_trace_0_exception, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_value // @[CSR.scala:384:14] ); wire [63:0] _io_rw_rdata_T_298; // @[Mux.scala:30:73] reg io_status_cease_r; // @[CSR.scala:1162:31] wire io_singleStep_0; // @[CSR.scala:1001:34] reg [1:0] reg_mstatus_prv; // @[CSR.scala:395:28] reg reg_mstatus_v; // @[CSR.scala:395:28] reg reg_mstatus_mpv; // @[CSR.scala:395:28] reg reg_mstatus_gva; // @[CSR.scala:395:28] reg reg_mstatus_tsr; // @[CSR.scala:395:28] reg reg_mstatus_tw; // @[CSR.scala:395:28] reg reg_mstatus_tvm; // @[CSR.scala:395:28] reg reg_mstatus_mxr; // @[CSR.scala:395:28] reg reg_mstatus_sum; // @[CSR.scala:395:28] reg reg_mstatus_mprv; // @[CSR.scala:395:28] reg [1:0] reg_mstatus_fs; // @[CSR.scala:395:28] reg [1:0] reg_mstatus_mpp; // @[CSR.scala:395:28] reg reg_mstatus_spp; // @[CSR.scala:395:28] reg reg_mstatus_mpie; // @[CSR.scala:395:28] reg reg_mstatus_spie; // @[CSR.scala:395:28] reg reg_mstatus_mie; // @[CSR.scala:395:28] reg reg_mstatus_sie; // @[CSR.scala:395:28] reg reg_dcsr_ebreakm; // @[CSR.scala:403:25] reg reg_dcsr_ebreaks; // @[CSR.scala:403:25] reg reg_dcsr_ebreaku; // @[CSR.scala:403:25] reg [2:0] reg_dcsr_cause; // @[CSR.scala:403:25] reg reg_dcsr_v; // @[CSR.scala:403:25] reg reg_dcsr_step; // @[CSR.scala:403:25] reg [1:0] reg_dcsr_prv; // @[CSR.scala:403:25] reg reg_debug; // @[CSR.scala:482:26] reg [39:0] reg_dpc; // @[CSR.scala:483:20] reg [63:0] reg_dscratch0; // @[CSR.scala:484:26] reg reg_singleStepped; // @[CSR.scala:486:30] reg reg_bp_0_control_dmode; // @[CSR.scala:492:19] reg reg_bp_0_control_action; // @[CSR.scala:492:19] reg [1:0] reg_bp_0_control_tmatch; // @[CSR.scala:492:19] reg reg_bp_0_control_m; // @[CSR.scala:492:19] reg reg_bp_0_control_s; // @[CSR.scala:492:19] reg reg_bp_0_control_u; // @[CSR.scala:492:19] reg reg_bp_0_control_x; // @[CSR.scala:492:19] reg reg_bp_0_control_w; // @[CSR.scala:492:19] reg reg_bp_0_control_r; // @[CSR.scala:492:19] reg [38:0] reg_bp_0_address; // @[CSR.scala:492:19] reg reg_pmp_0_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_0_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_0_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_0_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_0_addr; // @[CSR.scala:493:20] reg reg_pmp_1_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_1_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_1_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_1_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_1_addr; // @[CSR.scala:493:20] reg reg_pmp_2_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_2_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_2_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_2_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_2_addr; // @[CSR.scala:493:20] reg reg_pmp_3_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_3_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_3_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_3_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_3_addr; // @[CSR.scala:493:20] reg reg_pmp_4_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_4_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_4_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_4_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_4_addr; // @[CSR.scala:493:20] reg reg_pmp_5_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_5_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_5_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_5_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_5_addr; // @[CSR.scala:493:20] reg reg_pmp_6_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_6_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_6_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_6_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_6_addr; // @[CSR.scala:493:20] reg reg_pmp_7_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_7_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_7_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_7_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_7_addr; // @[CSR.scala:493:20] reg [63:0] reg_mie; // @[CSR.scala:495:20] reg [63:0] reg_mideleg; // @[CSR.scala:497:18] wire [8:0] _GEN = reg_mideleg[9:1] & 9'h111; // @[CSR.scala:497:18, :498:38] wire [15:0] _GEN_0 = {6'h0, _GEN, 1'h0}; // @[CSR.scala:498:38] wire [63:0] _GEN_1 = {54'h0, _GEN, 1'h0}; // @[CSR.scala:498:38] reg [63:0] reg_medeleg; // @[CSR.scala:501:18] wire [63:0] _GEN_2 = {48'h0, reg_medeleg[15:0] & 16'hB15D}; // @[CSR.scala:501:18, :502:38] reg reg_mip_seip; // @[CSR.scala:504:20] reg reg_mip_stip; // @[CSR.scala:504:20] reg reg_mip_ssip; // @[CSR.scala:504:20] reg [39:0] reg_mepc; // @[CSR.scala:505:21] reg [63:0] reg_mcause; // @[CSR.scala:506:27] reg [39:0] reg_mtval; // @[CSR.scala:507:22] reg [63:0] reg_mscratch; // @[CSR.scala:509:25] reg [31:0] reg_mtvec; // @[CSR.scala:512:31] reg reg_menvcfg_fiom; // @[CSR.scala:525:28] reg reg_senvcfg_fiom; // @[CSR.scala:526:28] reg [31:0] reg_mcounteren; // @[CSR.scala:531:18] wire [31:0] _GEN_3 = {29'h0, reg_mcounteren[2:0]}; // @[CSR.scala:531:18, :532:32] reg [31:0] reg_scounteren; // @[CSR.scala:535:18] wire [31:0] _GEN_4 = {29'h0, reg_scounteren[2:0]}; // @[CSR.scala:535:18, :536:38] reg reg_vsstatus_spp; // @[CSR.scala:562:25] reg [39:0] reg_vsepc; // @[CSR.scala:564:22] reg [39:0] reg_sepc; // @[CSR.scala:569:21] reg [63:0] reg_scause; // @[CSR.scala:570:23] reg [39:0] reg_stval; // @[CSR.scala:571:22] reg [63:0] reg_sscratch; // @[CSR.scala:572:25] reg [38:0] reg_stvec; // @[CSR.scala:573:22] reg [3:0] reg_satp_mode; // @[CSR.scala:574:21] reg [43:0] reg_satp_ppn; // @[CSR.scala:574:21] reg reg_wfi; // @[CSR.scala:575:54] reg [4:0] reg_fflags; // @[CSR.scala:577:23] reg [2:0] reg_frm; // @[CSR.scala:578:20] reg [2:0] reg_mcountinhibit; // @[CSR.scala:590:34] reg [5:0] small_0; // @[Counters.scala:45:41] reg [57:0] large_0; // @[Counters.scala:50:31] wire [63:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30] reg [5:0] small_1; // @[Counters.scala:45:41] reg [57:0] large_1; // @[Counters.scala:50:31] wire [63:0] io_time_0 = {large_1, small_1}; // @[Counters.scala:45:41, :50:31, :55:30] wire [15:0] read_mip = {4'h0, io_interrupts_meip, 1'h0, reg_mip_seip | io_interrupts_seip, 1'h0, io_interrupts_mtip, 1'h0, reg_mip_stip, 1'h0, io_interrupts_msip, 1'h0, reg_mip_ssip, 1'h0}; // @[CSR.scala:504:20, :606:57, :610:22] wire [15:0] _GEN_5 = reg_mie[15:0] & read_mip; // @[CSR.scala:495:20, :610:22, :614:56] wire [15:0] m_interrupts = ~(reg_mstatus_prv[1]) | reg_mstatus_mie ? ~(~_GEN_5 | _GEN_0) : 16'h0; // @[CSR.scala:395:28, :498:38, :614:56, :620:{25,51,62,83,85,105}] wire [15:0] s_interrupts = reg_mstatus_v | reg_mstatus_prv == 2'h0 | reg_mstatus_prv == 2'h1 & reg_mstatus_sie ? _GEN_5 & _GEN_0 : 16'h0; // @[CSR.scala:395:28, :498:38, :614:56, :621:{25,49,68,78,98,110,151}] wire [29:0] _GEN_6 = {reg_pmp_0_addr[28:0], reg_pmp_0_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] wire [29:0] _GEN_7 = {reg_pmp_1_addr[28:0], reg_pmp_1_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] wire [29:0] _GEN_8 = {reg_pmp_2_addr[28:0], reg_pmp_2_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] wire [29:0] _GEN_9 = {reg_pmp_3_addr[28:0], reg_pmp_3_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] wire [29:0] _GEN_10 = {reg_pmp_4_addr[28:0], reg_pmp_4_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] wire [29:0] _GEN_11 = {reg_pmp_5_addr[28:0], reg_pmp_5_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] wire [29:0] _GEN_12 = {reg_pmp_6_addr[28:0], reg_pmp_6_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] wire [29:0] _GEN_13 = {reg_pmp_7_addr[28:0], reg_pmp_7_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] reg [63:0] reg_misa; // @[CSR.scala:648:25] wire [31:0] _read_mtvec_T_5 = reg_mtvec & {24'hFFFFFF, ~(reg_mtvec[0] ? 8'hFE : 8'h2)}; // @[package.scala:174:{35,37,41,46}] wire [38:0] _read_stvec_T_5 = reg_stvec & {31'h7FFFFFFF, ~(reg_stvec[0] ? 8'hFE : 8'h2)}; // @[package.scala:174:{35,37,41,46}] wire [39:0] _io_evec_T_20 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28] wire [39:0] _read_mapping_T_6 = ~{_io_evec_T_20[39:2], _io_evec_T_20[1:0] | {~(reg_misa[2]), 1'h1}}; // @[CSR.scala:648:25, :1665:{26,28,31,36,45}] wire [39:0] _io_evec_T_10 = ~reg_dpc; // @[CSR.scala:483:20, :1665:28] wire [39:0] _debug_csrs_T_4 = ~{_io_evec_T_10[39:2], _io_evec_T_10[1:0] | {~(reg_misa[2]), 1'h1}}; // @[CSR.scala:648:25, :1665:{26,28,31,36,45}] wire [39:0] _io_evec_T = ~reg_sepc; // @[CSR.scala:569:21, :1665:28] wire [39:0] _GEN_14 = ~{_io_evec_T[39:2], _io_evec_T[1:0] | {~(reg_misa[2]), 1'h1}}; // @[CSR.scala:648:25, :1665:{26,28,31,36,45}] reg [63:0] reg_custom_0; // @[CSR.scala:798:43] wire [11:0] decoded_addr_decoded_decoded_invInputs = ~io_rw_addr; // @[pla.scala:78:21] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T = {decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], decoded_addr_decoded_decoded_invInputs[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], decoded_addr_decoded_decoded_invInputs[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = {io_rw_addr[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], decoded_addr_decoded_decoded_invInputs[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = {decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = {io_rw_addr[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = {io_rw_addr[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = {io_rw_addr[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = {io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [4:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = {io_rw_addr[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = {io_rw_addr[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = {io_rw_addr[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = {io_rw_addr[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = {decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = {io_rw_addr[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = {io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = {decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = {io_rw_addr[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = {io_rw_addr[0], io_rw_addr[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = {io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [5:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = {io_rw_addr[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = {decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], io_rw_addr[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], io_rw_addr[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [63:0] _wdata_T_2 = (io_rw_cmd[1] ? _io_rw_rdata_T_298 : 64'h0) | io_rw_wdata; // @[Mux.scala:30:73] wire [63:0] _wdata_T_6 = ~((&(io_rw_cmd[1:0])) ? io_rw_wdata : 64'h0); // @[CSR.scala:1643:{41,45,49,55}] wire system_insn = io_rw_cmd == 3'h4; // @[CSR.scala:876:31] wire [11:0] _GEN_15 = ~io_rw_addr; // @[pla.scala:78:21] wire insn_call = system_insn & (&{_GEN_15[0], _GEN_15[1], _GEN_15[2], _GEN_15[3], _GEN_15[4], _GEN_15[5], _GEN_15[6], _GEN_15[7], _GEN_15[8], _GEN_15[9], _GEN_15[10], _GEN_15[11]}); // @[pla.scala:78:21, :91:29, :98:{53,70}] wire insn_break = system_insn & (&{io_rw_addr[0], _GEN_15[1], _GEN_15[2], _GEN_15[3], _GEN_15[4], _GEN_15[5], _GEN_15[6], _GEN_15[7], _GEN_15[8], _GEN_15[9], _GEN_15[10], _GEN_15[11]}); // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] wire insn_ret = system_insn & (|{&{_GEN_15[2], _GEN_15[3], _GEN_15[4], _GEN_15[5], _GEN_15[6], _GEN_15[7], io_rw_addr[8], _GEN_15[10], _GEN_15[11]}, &{io_rw_addr[10], _GEN_15[11]}}); // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] wire [29:0] decoded_invInputs_1 = ~(io_decode_0_inst[31:2]); // @[pla.scala:78:21] wire [9:0] _decoded_andMatrixOutputs_T_10 = {io_decode_0_inst[22], decoded_invInputs_1[21], decoded_invInputs_1[22], decoded_invInputs_1[23], decoded_invInputs_1[24], decoded_invInputs_1[25], io_decode_0_inst[28], decoded_invInputs_1[27], decoded_invInputs_1[28], decoded_invInputs_1[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_11 = {io_decode_0_inst[0], io_decode_0_inst[1], decoded_invInputs_1[0], decoded_invInputs_1[1], io_decode_0_inst[4], io_decode_0_inst[5], io_decode_0_inst[6], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_decode_0_inst[25], decoded_invInputs_1[24], decoded_invInputs_1[25], io_decode_0_inst[28], decoded_invInputs_1[27], decoded_invInputs_1[28], decoded_invInputs_1[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] _decoded_orMatrixOutputs_T_10 = {&{io_decode_0_inst[0], decoded_invInputs_1[20], decoded_invInputs_1[21], decoded_invInputs_1[22], decoded_invInputs_1[23], decoded_invInputs_1[24], decoded_invInputs_1[25], io_decode_0_inst[28], decoded_invInputs_1[28], decoded_invInputs_1[29]}, &{io_decode_0_inst[30], decoded_invInputs_1[29]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] wire is_counter = io_decode_0_inst[31:20] > 12'hBFF & io_decode_0_inst[31:20] < 12'hC20 | io_decode_0_inst[31:20] > 12'hC7F & io_decode_0_inst[31:20] < 12'hCA0; // @[package.scala:213:{47,55,60}] wire allow_sfence_vma = reg_mstatus_prv[1] | ~(~reg_mstatus_v & reg_mstatus_tvm); // @[CSR.scala:395:28, :906:61, :907:{70,73,77}] wire [31:0] _GEN_16 = {27'h0, io_decode_0_inst[24:20]}; // @[CSR.scala:897:27, :911:28, :912:70] wire [31:0] _io_decode_0_virtual_access_illegal_T_3 = _GEN_3 >> _GEN_16; // @[CSR.scala:532:32, :912:70] wire [31:0] _io_decode_0_virtual_access_illegal_T_11 = _GEN_4 >> _GEN_16; // @[CSR.scala:536:38, :912:70, :913:75] wire [31:0] _io_decode_0_virtual_access_illegal_T_6 = 32'h0 >> _GEN_16; // @[CSR.scala:912:70, :914:63] wire io_decode_0_fp_illegal_0 = reg_mstatus_fs == 2'h0 | reg_mstatus_v | ~(reg_misa[5]); // @[CSR.scala:395:28, :648:25, :915:{39,47,91,94,103}] wire [3:0] io_decode_0_fp_csr_invInputs = ~(io_decode_0_inst[31:28]); // @[pla.scala:78:21] wire [3:0] _io_decode_0_fp_csr_andMatrixOutputs_T = {io_decode_0_fp_csr_invInputs[0], io_decode_0_fp_csr_invInputs[1], io_decode_0_fp_csr_invInputs[2], io_decode_0_fp_csr_invInputs[3]}; // @[pla.scala:78:21, :91:29, :98:53] wire _io_decode_0_virtual_access_illegal_T_24 = io_decode_0_inst[31:20] == 12'h180; // @[CSR.scala:897:27, :899:93] wire csr_exists = io_decode_0_inst[31:20] == 12'h7A0 | io_decode_0_inst[31:20] == 12'h7A1 | io_decode_0_inst[31:20] == 12'h7A2 | io_decode_0_inst[31:20] == 12'h7A3 | io_decode_0_inst[31:20] == 12'h301 | io_decode_0_inst[31:20] == 12'h300 | io_decode_0_inst[31:20] == 12'h305 | io_decode_0_inst[31:20] == 12'h344 | io_decode_0_inst[31:20] == 12'h304 | io_decode_0_inst[31:20] == 12'h340 | io_decode_0_inst[31:20] == 12'h341 | io_decode_0_inst[31:20] == 12'h343 | io_decode_0_inst[31:20] == 12'h342 | io_decode_0_inst[31:20] == 12'hF14 | io_decode_0_inst[31:20] == 12'h7B0 | io_decode_0_inst[31:20] == 12'h7B1 | io_decode_0_inst[31:20] == 12'h7B2 | io_decode_0_inst[31:20] == 12'h1 | io_decode_0_inst[31:20] == 12'h2 | io_decode_0_inst[31:20] == 12'h3 | io_decode_0_inst[31:20] == 12'h320 | io_decode_0_inst[31:20] == 12'hB00 | io_decode_0_inst[31:20] == 12'hB02 | io_decode_0_inst[31:20] == 12'h323 | io_decode_0_inst[31:20] == 12'hB03 | io_decode_0_inst[31:20] == 12'hC03 | io_decode_0_inst[31:20] == 12'h324 | io_decode_0_inst[31:20] == 12'hB04 | io_decode_0_inst[31:20] == 12'hC04 | io_decode_0_inst[31:20] == 12'h325 | io_decode_0_inst[31:20] == 12'hB05 | io_decode_0_inst[31:20] == 12'hC05 | io_decode_0_inst[31:20] == 12'h326 | io_decode_0_inst[31:20] == 12'hB06 | io_decode_0_inst[31:20] == 12'hC06 | io_decode_0_inst[31:20] == 12'h327 | io_decode_0_inst[31:20] == 12'hB07 | io_decode_0_inst[31:20] == 12'hC07 | io_decode_0_inst[31:20] == 12'h328 | io_decode_0_inst[31:20] == 12'hB08 | io_decode_0_inst[31:20] == 12'hC08 | io_decode_0_inst[31:20] == 12'h329 | io_decode_0_inst[31:20] == 12'hB09 | io_decode_0_inst[31:20] == 12'hC09 | io_decode_0_inst[31:20] == 12'h32A | io_decode_0_inst[31:20] == 12'hB0A | io_decode_0_inst[31:20] == 12'hC0A | io_decode_0_inst[31:20] == 12'h32B | io_decode_0_inst[31:20] == 12'hB0B | io_decode_0_inst[31:20] == 12'hC0B | io_decode_0_inst[31:20] == 12'h32C | io_decode_0_inst[31:20] == 12'hB0C | io_decode_0_inst[31:20] == 12'hC0C | io_decode_0_inst[31:20] == 12'h32D | io_decode_0_inst[31:20] == 12'hB0D | io_decode_0_inst[31:20] == 12'hC0D | io_decode_0_inst[31:20] == 12'h32E | io_decode_0_inst[31:20] == 12'hB0E | io_decode_0_inst[31:20] == 12'hC0E | io_decode_0_inst[31:20] == 12'h32F | io_decode_0_inst[31:20] == 12'hB0F | io_decode_0_inst[31:20] == 12'hC0F | io_decode_0_inst[31:20] == 12'h330 | io_decode_0_inst[31:20] == 12'hB10 | io_decode_0_inst[31:20] == 12'hC10 | io_decode_0_inst[31:20] == 12'h331 | io_decode_0_inst[31:20] == 12'hB11 | io_decode_0_inst[31:20] == 12'hC11 | io_decode_0_inst[31:20] == 12'h332 | io_decode_0_inst[31:20] == 12'hB12 | io_decode_0_inst[31:20] == 12'hC12 | io_decode_0_inst[31:20] == 12'h333 | io_decode_0_inst[31:20] == 12'hB13 | io_decode_0_inst[31:20] == 12'hC13 | io_decode_0_inst[31:20] == 12'h334 | io_decode_0_inst[31:20] == 12'hB14 | io_decode_0_inst[31:20] == 12'hC14 | io_decode_0_inst[31:20] == 12'h335 | io_decode_0_inst[31:20] == 12'hB15 | io_decode_0_inst[31:20] == 12'hC15 | io_decode_0_inst[31:20] == 12'h336 | io_decode_0_inst[31:20] == 12'hB16 | io_decode_0_inst[31:20] == 12'hC16 | io_decode_0_inst[31:20] == 12'h337 | io_decode_0_inst[31:20] == 12'hB17 | io_decode_0_inst[31:20] == 12'hC17 | io_decode_0_inst[31:20] == 12'h338 | io_decode_0_inst[31:20] == 12'hB18 | io_decode_0_inst[31:20] == 12'hC18 | io_decode_0_inst[31:20] == 12'h339 | io_decode_0_inst[31:20] == 12'hB19 | io_decode_0_inst[31:20] == 12'hC19 | io_decode_0_inst[31:20] == 12'h33A | io_decode_0_inst[31:20] == 12'hB1A | io_decode_0_inst[31:20] == 12'hC1A | io_decode_0_inst[31:20] == 12'h33B | io_decode_0_inst[31:20] == 12'hB1B | io_decode_0_inst[31:20] == 12'hC1B | io_decode_0_inst[31:20] == 12'h33C | io_decode_0_inst[31:20] == 12'hB1C | io_decode_0_inst[31:20] == 12'hC1C | io_decode_0_inst[31:20] == 12'h33D | io_decode_0_inst[31:20] == 12'hB1D | io_decode_0_inst[31:20] == 12'hC1D | io_decode_0_inst[31:20] == 12'h33E | io_decode_0_inst[31:20] == 12'hB1E | io_decode_0_inst[31:20] == 12'hC1E | io_decode_0_inst[31:20] == 12'h33F | io_decode_0_inst[31:20] == 12'hB1F | io_decode_0_inst[31:20] == 12'hC1F | io_decode_0_inst[31:20] == 12'h306 | io_decode_0_inst[31:20] == 12'hC00 | io_decode_0_inst[31:20] == 12'hC02 | io_decode_0_inst[31:20] == 12'h30A | io_decode_0_inst[31:20] == 12'h100 | io_decode_0_inst[31:20] == 12'h144 | io_decode_0_inst[31:20] == 12'h104 | io_decode_0_inst[31:20] == 12'h140 | io_decode_0_inst[31:20] == 12'h142 | io_decode_0_inst[31:20] == 12'h143 | _io_decode_0_virtual_access_illegal_T_24 | io_decode_0_inst[31:20] == 12'h141 | io_decode_0_inst[31:20] == 12'h105 | io_decode_0_inst[31:20] == 12'h106 | io_decode_0_inst[31:20] == 12'h303 | io_decode_0_inst[31:20] == 12'h302 | io_decode_0_inst[31:20] == 12'h10A | io_decode_0_inst[31:20] == 12'h3A0 | io_decode_0_inst[31:20] == 12'h3A2 | io_decode_0_inst[31:20] == 12'h3B0 | io_decode_0_inst[31:20] == 12'h3B1 | io_decode_0_inst[31:20] == 12'h3B2 | io_decode_0_inst[31:20] == 12'h3B3 | io_decode_0_inst[31:20] == 12'h3B4 | io_decode_0_inst[31:20] == 12'h3B5 | io_decode_0_inst[31:20] == 12'h3B6 | io_decode_0_inst[31:20] == 12'h3B7 | io_decode_0_inst[31:20] == 12'h3B8 | io_decode_0_inst[31:20] == 12'h3B9 | io_decode_0_inst[31:20] == 12'h3BA | io_decode_0_inst[31:20] == 12'h3BB | io_decode_0_inst[31:20] == 12'h3BC | io_decode_0_inst[31:20] == 12'h3BD | io_decode_0_inst[31:20] == 12'h3BE | io_decode_0_inst[31:20] == 12'h3BF | io_decode_0_inst[31:20] == 12'h7C1 | io_decode_0_inst[31:20] == 12'hF12 | io_decode_0_inst[31:20] == 12'hF11 | io_decode_0_inst[31:20] == 12'hF13 | io_decode_0_inst[31:20] == 12'hF15; // @[CSR.scala:897:27, :899:{93,111}] wire _io_decode_0_system_illegal_T = reg_mstatus_prv < io_decode_0_inst[29:28]; // @[CSR.scala:190:36, :395:28, :897:27, :920:42, :923:28] wire [5:0] io_decode_0_read_illegal_invInputs = ~(io_decode_0_inst[31:26]); // @[pla.scala:78:21] wire [11:0] io_decode_0_write_flush_addr_m = {io_decode_0_inst[31:30], io_decode_0_inst[29:20] | 10'h300}; // @[CSR.scala:897:27, :932:25] wire [63:0] cause = insn_call ? {60'h0, {2'h0, reg_mstatus_prv[0] & reg_mstatus_v ? 2'h2 : reg_mstatus_prv} - 4'h8} : insn_break ? 64'h3 : io_cause; // @[CSR.scala:395:28, :893:83, :945:105, :959:{8,40,45,65}, :960:14] wire _causeIsDebugTrigger_T_2 = cause[7:0] == 8'hE; // @[CSR.scala:959:8, :961:25, :963:53] wire causeIsDebugInt = cause[63] & _causeIsDebugTrigger_T_2; // @[CSR.scala:959:8, :963:{30,39,53}] wire causeIsDebugTrigger = ~(cause[63]) & _causeIsDebugTrigger_T_2; // @[CSR.scala:959:8, :963:{30,53}, :964:{29,44}] wire [3:0] _causeIsDebugBreak_T_4 = {reg_dcsr_ebreakm, 1'h0, reg_dcsr_ebreaks, reg_dcsr_ebreaku} >> reg_mstatus_prv; // @[CSR.scala:395:28, :403:25, :965:{62,134}] wire trapToDebug = reg_singleStepped | causeIsDebugInt | causeIsDebugTrigger | ~(cause[63]) & insn_break & _causeIsDebugBreak_T_4[0] | reg_debug; // @[CSR.scala:482:26, :486:30, :893:83, :959:8, :963:{30,39}, :964:44, :965:{27,42,56,134}, :966:{56,75,98,119}] wire [63:0] _GEN_17 = {58'h0, cause[5:0]}; // @[CSR.scala:959:8, :962:31, :970:100] wire [63:0] _delegate_T_3 = _GEN_1 >> _GEN_17; // @[CSR.scala:498:38, :970:100] wire [63:0] _delegate_T_5 = _GEN_2 >> _GEN_17; // @[CSR.scala:502:38, :970:{100,132}] wire delegate = ~(reg_mstatus_prv[1]) & (cause[63] ? _delegate_T_3[0] : _delegate_T_5[0]); // @[CSR.scala:395:28, :620:51, :959:8, :963:30, :970:{66,72,100,132}] wire [63:0] _delegateVS_T_2 = 64'h0 >> _GEN_17; // @[CSR.scala:970:100, :971:80] wire [63:0] _delegateVS_T_4 = 64'h0 >> _GEN_17; // @[CSR.scala:970:100, :971:112] wire delegateVS = reg_mstatus_v & delegate & (cause[63] ? _delegateVS_T_2[0] : _delegateVS_T_4[0]); // @[CSR.scala:395:28, :959:8, :963:30, :970:66, :971:{34,46,52,80,112}] wire [39:0] notDebugTVec_base = delegate ? (delegateVS ? 40'h0 : {reg_stvec[38], _read_stvec_T_5}) : {8'h0, _read_mtvec_T_5}; // @[package.scala:132:{15,38}, :138:15, :174:35] wire _exception_T = insn_call | insn_break; // @[CSR.scala:893:83, :1000:24] assign io_singleStep_0 = reg_dcsr_step & ~reg_debug; // @[CSR.scala:403:25, :482:26, :927:45, :1001:34] wire exception = _exception_T | io_exception; // @[CSR.scala:1000:24, :1020:43]
Generate the Verilog code corresponding to this FIRRTL code module DTLB_8 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}}, flip kill : UInt<1>} node vpn = bits(io.req.bits.vaddr, 38, 12) reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[8][1], clock reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<2>, clock reg r_sectored_repl_addr : UInt<3>, clock reg r_sectored_hit : { valid : UInt<1>, bits : UInt<3>}, clock reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock reg r_vstage1_en : UInt<1>, clock reg r_stage2_en : UInt<1>, clock reg r_need_gpa : UInt<1>, clock reg r_gpa_valid : UInt<1>, clock reg r_gpa : UInt<39>, clock reg r_gpa_vpn : UInt<27>, clock reg r_gpa_is_pte : UInt<1>, clock node priv_v = and(UInt<1>(0h0), io.req.bits.v) node priv_s = bits(io.req.bits.prv, 0, 0) node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) node _stage1_en_T = bits(satp.mode, 3, 3) node stage1_en = and(UInt<1>(0h1), _stage1_en_T) node _vstage1_en_T = and(UInt<1>(0h0), priv_v) node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) node _stage2_en_T = and(UInt<1>(0h0), priv_v) node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) node stage2_en = and(_stage2_en_T, _stage2_en_T_1) node _vm_enabled_T = or(stage1_en, stage2_en) node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_WIRE_1 : UInt<42> connect _mpu_ppn_WIRE_1, special_entry.data[0] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_126 connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0)) node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9) node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0)) node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0) node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30) node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12) node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32) node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33) node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T) node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) inst pmp of PMPChecker_s3_8 connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr connect pmp.io.size, io.req.bits.size connect pmp.io.prv, mpu_priv inst pma of PMAChecker_9 connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr, UInt<18>(0h20000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<15>(0h4000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr, UInt<18>(0h24000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<13>(0h1000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr, UInt<21>(0h100000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr, UInt<26>(0h2000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr, UInt<26>(0h2010000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<13>(0h1000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<17>(0h10000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr, UInt<28>(0hc000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = xor(mpu_physaddr, UInt<29>(0h10020000)) node _homogeneous_T_51 = cvt(_homogeneous_T_50) node _homogeneous_T_52 = and(_homogeneous_T_51, asSInt(UInt<13>(0h1000))) node _homogeneous_T_53 = asSInt(_homogeneous_T_52) node _homogeneous_T_54 = eq(_homogeneous_T_53, asSInt(UInt<1>(0h0))) node _homogeneous_T_55 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_56 = cvt(_homogeneous_T_55) node _homogeneous_T_57 = and(_homogeneous_T_56, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_58 = asSInt(_homogeneous_T_57) node _homogeneous_T_59 = eq(_homogeneous_T_58, asSInt(UInt<1>(0h0))) node _homogeneous_T_60 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_61 = or(_homogeneous_T_60, _homogeneous_T_9) node _homogeneous_T_62 = or(_homogeneous_T_61, _homogeneous_T_14) node _homogeneous_T_63 = or(_homogeneous_T_62, _homogeneous_T_19) node _homogeneous_T_64 = or(_homogeneous_T_63, _homogeneous_T_24) node _homogeneous_T_65 = or(_homogeneous_T_64, _homogeneous_T_29) node _homogeneous_T_66 = or(_homogeneous_T_65, _homogeneous_T_34) node _homogeneous_T_67 = or(_homogeneous_T_66, _homogeneous_T_39) node _homogeneous_T_68 = or(_homogeneous_T_67, _homogeneous_T_44) node _homogeneous_T_69 = or(_homogeneous_T_68, _homogeneous_T_49) node _homogeneous_T_70 = or(_homogeneous_T_69, _homogeneous_T_54) node homogeneous = or(_homogeneous_T_70, _homogeneous_T_59) node _homogeneous_T_71 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_72 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_73 = cvt(_homogeneous_T_72) node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h8a130000))) node _homogeneous_T_75 = asSInt(_homogeneous_T_74) node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0))) node _homogeneous_T_77 = or(UInt<1>(0h0), _homogeneous_T_76) node _homogeneous_T_78 = eq(_homogeneous_T_77, UInt<1>(0h0)) node _homogeneous_T_79 = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_80 = cvt(_homogeneous_T_79) node _homogeneous_T_81 = and(_homogeneous_T_80, asSInt(UInt<33>(0hffff3000))) node _homogeneous_T_82 = asSInt(_homogeneous_T_81) node _homogeneous_T_83 = eq(_homogeneous_T_82, asSInt(UInt<1>(0h0))) node _homogeneous_T_84 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_85 = cvt(_homogeneous_T_84) node _homogeneous_T_86 = and(_homogeneous_T_85, asSInt(UInt<33>(0hffff3000))) node _homogeneous_T_87 = asSInt(_homogeneous_T_86) node _homogeneous_T_88 = eq(_homogeneous_T_87, asSInt(UInt<1>(0h0))) node _homogeneous_T_89 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_90 = cvt(_homogeneous_T_89) node _homogeneous_T_91 = and(_homogeneous_T_90, asSInt(UInt<33>(0hffff0000))) node _homogeneous_T_92 = asSInt(_homogeneous_T_91) node _homogeneous_T_93 = eq(_homogeneous_T_92, asSInt(UInt<1>(0h0))) node _homogeneous_T_94 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_95 = cvt(_homogeneous_T_94) node _homogeneous_T_96 = and(_homogeneous_T_95, asSInt(UInt<33>(0hffff0000))) node _homogeneous_T_97 = asSInt(_homogeneous_T_96) node _homogeneous_T_98 = eq(_homogeneous_T_97, asSInt(UInt<1>(0h0))) node _homogeneous_T_99 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_100 = cvt(_homogeneous_T_99) node _homogeneous_T_101 = and(_homogeneous_T_100, asSInt(UInt<33>(0hf0000000))) node _homogeneous_T_102 = asSInt(_homogeneous_T_101) node _homogeneous_T_103 = eq(_homogeneous_T_102, asSInt(UInt<1>(0h0))) node _homogeneous_T_104 = or(UInt<1>(0h0), _homogeneous_T_83) node _homogeneous_T_105 = or(_homogeneous_T_104, _homogeneous_T_88) node _homogeneous_T_106 = or(_homogeneous_T_105, _homogeneous_T_93) node _homogeneous_T_107 = or(_homogeneous_T_106, _homogeneous_T_98) node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_103) node _homogeneous_T_109 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_110 = cvt(_homogeneous_T_109) node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8e020000))) node _homogeneous_T_112 = asSInt(_homogeneous_T_111) node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0))) node _homogeneous_T_114 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_115 = cvt(_homogeneous_T_114) node _homogeneous_T_116 = and(_homogeneous_T_115, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_117 = asSInt(_homogeneous_T_116) node _homogeneous_T_118 = eq(_homogeneous_T_117, asSInt(UInt<1>(0h0))) node _homogeneous_T_119 = or(UInt<1>(0h0), _homogeneous_T_113) node _homogeneous_T_120 = or(_homogeneous_T_119, _homogeneous_T_118) node _homogeneous_T_121 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_122 = cvt(_homogeneous_T_121) node _homogeneous_T_123 = and(_homogeneous_T_122, asSInt(UInt<33>(0h8a130000))) node _homogeneous_T_124 = asSInt(_homogeneous_T_123) node _homogeneous_T_125 = eq(_homogeneous_T_124, asSInt(UInt<1>(0h0))) node _homogeneous_T_126 = or(UInt<1>(0h0), _homogeneous_T_125) node _homogeneous_T_127 = eq(_homogeneous_T_126, UInt<1>(0h0)) node _homogeneous_T_128 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_129 = cvt(_homogeneous_T_128) node _homogeneous_T_130 = and(_homogeneous_T_129, asSInt(UInt<33>(0h8a130000))) node _homogeneous_T_131 = asSInt(_homogeneous_T_130) node _homogeneous_T_132 = eq(_homogeneous_T_131, asSInt(UInt<1>(0h0))) node _homogeneous_T_133 = or(UInt<1>(0h0), _homogeneous_T_132) node _homogeneous_T_134 = eq(_homogeneous_T_133, UInt<1>(0h0)) node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) node prot_r = and(_prot_r_T_1, pmp.io.r) node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) node prot_w = and(_prot_w_T_1, pmp.io.w) node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) node prot_x = and(_prot_x_T_1, pmp.io.x) node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2]) node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3]) node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn) node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v) node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6) node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7) node _sector_hits_T_8 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[0][1].valid[2]) node _sector_hits_T_10 = or(_sector_hits_T_9, sectored_entries[0][1].valid[3]) node _sector_hits_T_11 = xor(sectored_entries[0][1].tag_vpn, vpn) node _sector_hits_T_12 = shr(_sector_hits_T_11, 2) node _sector_hits_T_13 = eq(_sector_hits_T_12, UInt<1>(0h0)) node _sector_hits_T_14 = eq(sectored_entries[0][1].tag_v, priv_v) node _sector_hits_T_15 = and(_sector_hits_T_13, _sector_hits_T_14) node sector_hits_1 = and(_sector_hits_T_10, _sector_hits_T_15) node _sector_hits_T_16 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _sector_hits_T_17 = or(_sector_hits_T_16, sectored_entries[0][2].valid[2]) node _sector_hits_T_18 = or(_sector_hits_T_17, sectored_entries[0][2].valid[3]) node _sector_hits_T_19 = xor(sectored_entries[0][2].tag_vpn, vpn) node _sector_hits_T_20 = shr(_sector_hits_T_19, 2) node _sector_hits_T_21 = eq(_sector_hits_T_20, UInt<1>(0h0)) node _sector_hits_T_22 = eq(sectored_entries[0][2].tag_v, priv_v) node _sector_hits_T_23 = and(_sector_hits_T_21, _sector_hits_T_22) node sector_hits_2 = and(_sector_hits_T_18, _sector_hits_T_23) node _sector_hits_T_24 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _sector_hits_T_25 = or(_sector_hits_T_24, sectored_entries[0][3].valid[2]) node _sector_hits_T_26 = or(_sector_hits_T_25, sectored_entries[0][3].valid[3]) node _sector_hits_T_27 = xor(sectored_entries[0][3].tag_vpn, vpn) node _sector_hits_T_28 = shr(_sector_hits_T_27, 2) node _sector_hits_T_29 = eq(_sector_hits_T_28, UInt<1>(0h0)) node _sector_hits_T_30 = eq(sectored_entries[0][3].tag_v, priv_v) node _sector_hits_T_31 = and(_sector_hits_T_29, _sector_hits_T_30) node sector_hits_3 = and(_sector_hits_T_26, _sector_hits_T_31) node _sector_hits_T_32 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _sector_hits_T_33 = or(_sector_hits_T_32, sectored_entries[0][4].valid[2]) node _sector_hits_T_34 = or(_sector_hits_T_33, sectored_entries[0][4].valid[3]) node _sector_hits_T_35 = xor(sectored_entries[0][4].tag_vpn, vpn) node _sector_hits_T_36 = shr(_sector_hits_T_35, 2) node _sector_hits_T_37 = eq(_sector_hits_T_36, UInt<1>(0h0)) node _sector_hits_T_38 = eq(sectored_entries[0][4].tag_v, priv_v) node _sector_hits_T_39 = and(_sector_hits_T_37, _sector_hits_T_38) node sector_hits_4 = and(_sector_hits_T_34, _sector_hits_T_39) node _sector_hits_T_40 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _sector_hits_T_41 = or(_sector_hits_T_40, sectored_entries[0][5].valid[2]) node _sector_hits_T_42 = or(_sector_hits_T_41, sectored_entries[0][5].valid[3]) node _sector_hits_T_43 = xor(sectored_entries[0][5].tag_vpn, vpn) node _sector_hits_T_44 = shr(_sector_hits_T_43, 2) node _sector_hits_T_45 = eq(_sector_hits_T_44, UInt<1>(0h0)) node _sector_hits_T_46 = eq(sectored_entries[0][5].tag_v, priv_v) node _sector_hits_T_47 = and(_sector_hits_T_45, _sector_hits_T_46) node sector_hits_5 = and(_sector_hits_T_42, _sector_hits_T_47) node _sector_hits_T_48 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _sector_hits_T_49 = or(_sector_hits_T_48, sectored_entries[0][6].valid[2]) node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[0][6].valid[3]) node _sector_hits_T_51 = xor(sectored_entries[0][6].tag_vpn, vpn) node _sector_hits_T_52 = shr(_sector_hits_T_51, 2) node _sector_hits_T_53 = eq(_sector_hits_T_52, UInt<1>(0h0)) node _sector_hits_T_54 = eq(sectored_entries[0][6].tag_v, priv_v) node _sector_hits_T_55 = and(_sector_hits_T_53, _sector_hits_T_54) node sector_hits_6 = and(_sector_hits_T_50, _sector_hits_T_55) node _sector_hits_T_56 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _sector_hits_T_57 = or(_sector_hits_T_56, sectored_entries[0][7].valid[2]) node _sector_hits_T_58 = or(_sector_hits_T_57, sectored_entries[0][7].valid[3]) node _sector_hits_T_59 = xor(sectored_entries[0][7].tag_vpn, vpn) node _sector_hits_T_60 = shr(_sector_hits_T_59, 2) node _sector_hits_T_61 = eq(_sector_hits_T_60, UInt<1>(0h0)) node _sector_hits_T_62 = eq(sectored_entries[0][7].tag_v, priv_v) node _sector_hits_T_63 = and(_sector_hits_T_61, _sector_hits_T_62) node sector_hits_7 = and(_sector_hits_T_58, _sector_hits_T_63) node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T) node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _superpage_hits_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node superpage_hits_tagMatch_1 = and(superpage_entries[1].valid[0], _superpage_hits_tagMatch_T_1) node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0)) node _superpage_hits_T_14 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_15 = bits(_superpage_hits_T_14, 26, 18) node _superpage_hits_T_16 = eq(_superpage_hits_T_15, UInt<1>(0h0)) node _superpage_hits_T_17 = or(superpage_hits_ignore_3, _superpage_hits_T_16) node _superpage_hits_T_18 = and(superpage_hits_tagMatch_1, _superpage_hits_T_17) node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0)) node _superpage_hits_T_19 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_20 = bits(_superpage_hits_T_19, 17, 9) node _superpage_hits_T_21 = eq(_superpage_hits_T_20, UInt<1>(0h0)) node _superpage_hits_T_22 = or(superpage_hits_ignore_4, _superpage_hits_T_21) node _superpage_hits_T_23 = and(_superpage_hits_T_18, _superpage_hits_T_22) node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1)) node _superpage_hits_T_24 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_25 = bits(_superpage_hits_T_24, 8, 0) node _superpage_hits_T_26 = eq(_superpage_hits_T_25, UInt<1>(0h0)) node _superpage_hits_T_27 = or(superpage_hits_ignore_5, _superpage_hits_T_26) node superpage_hits_1 = and(_superpage_hits_T_23, _superpage_hits_T_27) node _superpage_hits_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node superpage_hits_tagMatch_2 = and(superpage_entries[2].valid[0], _superpage_hits_tagMatch_T_2) node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0)) node _superpage_hits_T_28 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_29 = bits(_superpage_hits_T_28, 26, 18) node _superpage_hits_T_30 = eq(_superpage_hits_T_29, UInt<1>(0h0)) node _superpage_hits_T_31 = or(superpage_hits_ignore_6, _superpage_hits_T_30) node _superpage_hits_T_32 = and(superpage_hits_tagMatch_2, _superpage_hits_T_31) node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0)) node _superpage_hits_T_33 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_34 = bits(_superpage_hits_T_33, 17, 9) node _superpage_hits_T_35 = eq(_superpage_hits_T_34, UInt<1>(0h0)) node _superpage_hits_T_36 = or(superpage_hits_ignore_7, _superpage_hits_T_35) node _superpage_hits_T_37 = and(_superpage_hits_T_32, _superpage_hits_T_36) node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1)) node _superpage_hits_T_38 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_39 = bits(_superpage_hits_T_38, 8, 0) node _superpage_hits_T_40 = eq(_superpage_hits_T_39, UInt<1>(0h0)) node _superpage_hits_T_41 = or(superpage_hits_ignore_8, _superpage_hits_T_40) node superpage_hits_2 = and(_superpage_hits_T_37, _superpage_hits_T_41) node _superpage_hits_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node superpage_hits_tagMatch_3 = and(superpage_entries[3].valid[0], _superpage_hits_tagMatch_T_3) node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0)) node _superpage_hits_T_42 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_43 = bits(_superpage_hits_T_42, 26, 18) node _superpage_hits_T_44 = eq(_superpage_hits_T_43, UInt<1>(0h0)) node _superpage_hits_T_45 = or(superpage_hits_ignore_9, _superpage_hits_T_44) node _superpage_hits_T_46 = and(superpage_hits_tagMatch_3, _superpage_hits_T_45) node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0)) node _superpage_hits_T_47 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_48 = bits(_superpage_hits_T_47, 17, 9) node _superpage_hits_T_49 = eq(_superpage_hits_T_48, UInt<1>(0h0)) node _superpage_hits_T_50 = or(superpage_hits_ignore_10, _superpage_hits_T_49) node _superpage_hits_T_51 = and(_superpage_hits_T_46, _superpage_hits_T_50) node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1)) node _superpage_hits_T_52 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_53 = bits(_superpage_hits_T_52, 8, 0) node _superpage_hits_T_54 = eq(_superpage_hits_T_53, UInt<1>(0h0)) node _superpage_hits_T_55 = or(superpage_hits_ignore_11, _superpage_hits_T_54) node superpage_hits_3 = and(_superpage_hits_T_51, _superpage_hits_T_55) node hitsVec_idx = bits(vpn, 1, 0) node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn) node _hitsVec_T_1 = shr(_hitsVec_T, 2) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v) node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4) node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) node hitsVec_idx_1 = bits(vpn, 1, 0) node _hitsVec_T_6 = xor(sectored_entries[0][1].tag_vpn, vpn) node _hitsVec_T_7 = shr(_hitsVec_T_6, 2) node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) node _hitsVec_T_9 = eq(sectored_entries[0][1].tag_v, priv_v) node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) node _hitsVec_T_11 = and(sectored_entries[0][1].valid[hitsVec_idx_1], _hitsVec_T_10) node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) node hitsVec_idx_2 = bits(vpn, 1, 0) node _hitsVec_T_12 = xor(sectored_entries[0][2].tag_vpn, vpn) node _hitsVec_T_13 = shr(_hitsVec_T_12, 2) node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) node _hitsVec_T_15 = eq(sectored_entries[0][2].tag_v, priv_v) node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) node _hitsVec_T_17 = and(sectored_entries[0][2].valid[hitsVec_idx_2], _hitsVec_T_16) node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) node hitsVec_idx_3 = bits(vpn, 1, 0) node _hitsVec_T_18 = xor(sectored_entries[0][3].tag_vpn, vpn) node _hitsVec_T_19 = shr(_hitsVec_T_18, 2) node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) node _hitsVec_T_21 = eq(sectored_entries[0][3].tag_v, priv_v) node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = and(sectored_entries[0][3].valid[hitsVec_idx_3], _hitsVec_T_22) node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) node hitsVec_idx_4 = bits(vpn, 1, 0) node _hitsVec_T_24 = xor(sectored_entries[0][4].tag_vpn, vpn) node _hitsVec_T_25 = shr(_hitsVec_T_24, 2) node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) node _hitsVec_T_27 = eq(sectored_entries[0][4].tag_v, priv_v) node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27) node _hitsVec_T_29 = and(sectored_entries[0][4].valid[hitsVec_idx_4], _hitsVec_T_28) node hitsVec_4 = and(vm_enabled, _hitsVec_T_29) node hitsVec_idx_5 = bits(vpn, 1, 0) node _hitsVec_T_30 = xor(sectored_entries[0][5].tag_vpn, vpn) node _hitsVec_T_31 = shr(_hitsVec_T_30, 2) node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0)) node _hitsVec_T_33 = eq(sectored_entries[0][5].tag_v, priv_v) node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33) node _hitsVec_T_35 = and(sectored_entries[0][5].valid[hitsVec_idx_5], _hitsVec_T_34) node hitsVec_5 = and(vm_enabled, _hitsVec_T_35) node hitsVec_idx_6 = bits(vpn, 1, 0) node _hitsVec_T_36 = xor(sectored_entries[0][6].tag_vpn, vpn) node _hitsVec_T_37 = shr(_hitsVec_T_36, 2) node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0)) node _hitsVec_T_39 = eq(sectored_entries[0][6].tag_v, priv_v) node _hitsVec_T_40 = and(_hitsVec_T_38, _hitsVec_T_39) node _hitsVec_T_41 = and(sectored_entries[0][6].valid[hitsVec_idx_6], _hitsVec_T_40) node hitsVec_6 = and(vm_enabled, _hitsVec_T_41) node hitsVec_idx_7 = bits(vpn, 1, 0) node _hitsVec_T_42 = xor(sectored_entries[0][7].tag_vpn, vpn) node _hitsVec_T_43 = shr(_hitsVec_T_42, 2) node _hitsVec_T_44 = eq(_hitsVec_T_43, UInt<1>(0h0)) node _hitsVec_T_45 = eq(sectored_entries[0][7].tag_v, priv_v) node _hitsVec_T_46 = and(_hitsVec_T_44, _hitsVec_T_45) node _hitsVec_T_47 = and(sectored_entries[0][7].valid[hitsVec_idx_7], _hitsVec_T_46) node hitsVec_7 = and(vm_enabled, _hitsVec_T_47) node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_48 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_49 = bits(_hitsVec_T_48, 26, 18) node _hitsVec_T_50 = eq(_hitsVec_T_49, UInt<1>(0h0)) node _hitsVec_T_51 = or(hitsVec_ignore, _hitsVec_T_50) node _hitsVec_T_52 = and(hitsVec_tagMatch, _hitsVec_T_51) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_53 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_54 = bits(_hitsVec_T_53, 17, 9) node _hitsVec_T_55 = eq(_hitsVec_T_54, UInt<1>(0h0)) node _hitsVec_T_56 = or(hitsVec_ignore_1, _hitsVec_T_55) node _hitsVec_T_57 = and(_hitsVec_T_52, _hitsVec_T_56) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_58 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_59 = bits(_hitsVec_T_58, 8, 0) node _hitsVec_T_60 = eq(_hitsVec_T_59, UInt<1>(0h0)) node _hitsVec_T_61 = or(hitsVec_ignore_2, _hitsVec_T_60) node _hitsVec_T_62 = and(_hitsVec_T_57, _hitsVec_T_61) node hitsVec_8 = and(vm_enabled, _hitsVec_T_62) node _hitsVec_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node hitsVec_tagMatch_1 = and(superpage_entries[1].valid[0], _hitsVec_tagMatch_T_1) node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_63 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_64 = bits(_hitsVec_T_63, 26, 18) node _hitsVec_T_65 = eq(_hitsVec_T_64, UInt<1>(0h0)) node _hitsVec_T_66 = or(hitsVec_ignore_3, _hitsVec_T_65) node _hitsVec_T_67 = and(hitsVec_tagMatch_1, _hitsVec_T_66) node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_68 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_69 = bits(_hitsVec_T_68, 17, 9) node _hitsVec_T_70 = eq(_hitsVec_T_69, UInt<1>(0h0)) node _hitsVec_T_71 = or(hitsVec_ignore_4, _hitsVec_T_70) node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71) node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1)) node _hitsVec_T_73 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_74 = bits(_hitsVec_T_73, 8, 0) node _hitsVec_T_75 = eq(_hitsVec_T_74, UInt<1>(0h0)) node _hitsVec_T_76 = or(hitsVec_ignore_5, _hitsVec_T_75) node _hitsVec_T_77 = and(_hitsVec_T_72, _hitsVec_T_76) node hitsVec_9 = and(vm_enabled, _hitsVec_T_77) node _hitsVec_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node hitsVec_tagMatch_2 = and(superpage_entries[2].valid[0], _hitsVec_tagMatch_T_2) node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0)) node _hitsVec_T_78 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_79 = bits(_hitsVec_T_78, 26, 18) node _hitsVec_T_80 = eq(_hitsVec_T_79, UInt<1>(0h0)) node _hitsVec_T_81 = or(hitsVec_ignore_6, _hitsVec_T_80) node _hitsVec_T_82 = and(hitsVec_tagMatch_2, _hitsVec_T_81) node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0)) node _hitsVec_T_83 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_84 = bits(_hitsVec_T_83, 17, 9) node _hitsVec_T_85 = eq(_hitsVec_T_84, UInt<1>(0h0)) node _hitsVec_T_86 = or(hitsVec_ignore_7, _hitsVec_T_85) node _hitsVec_T_87 = and(_hitsVec_T_82, _hitsVec_T_86) node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1)) node _hitsVec_T_88 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_89 = bits(_hitsVec_T_88, 8, 0) node _hitsVec_T_90 = eq(_hitsVec_T_89, UInt<1>(0h0)) node _hitsVec_T_91 = or(hitsVec_ignore_8, _hitsVec_T_90) node _hitsVec_T_92 = and(_hitsVec_T_87, _hitsVec_T_91) node hitsVec_10 = and(vm_enabled, _hitsVec_T_92) node _hitsVec_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node hitsVec_tagMatch_3 = and(superpage_entries[3].valid[0], _hitsVec_tagMatch_T_3) node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0)) node _hitsVec_T_93 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_94 = bits(_hitsVec_T_93, 26, 18) node _hitsVec_T_95 = eq(_hitsVec_T_94, UInt<1>(0h0)) node _hitsVec_T_96 = or(hitsVec_ignore_9, _hitsVec_T_95) node _hitsVec_T_97 = and(hitsVec_tagMatch_3, _hitsVec_T_96) node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0)) node _hitsVec_T_98 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_99 = bits(_hitsVec_T_98, 17, 9) node _hitsVec_T_100 = eq(_hitsVec_T_99, UInt<1>(0h0)) node _hitsVec_T_101 = or(hitsVec_ignore_10, _hitsVec_T_100) node _hitsVec_T_102 = and(_hitsVec_T_97, _hitsVec_T_101) node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1)) node _hitsVec_T_103 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_104 = bits(_hitsVec_T_103, 8, 0) node _hitsVec_T_105 = eq(_hitsVec_T_104, UInt<1>(0h0)) node _hitsVec_T_106 = or(hitsVec_ignore_11, _hitsVec_T_105) node _hitsVec_T_107 = and(_hitsVec_T_102, _hitsVec_T_106) node hitsVec_11 = and(vm_enabled, _hitsVec_T_107) node _hitsVec_tagMatch_T_4 = eq(special_entry.tag_v, priv_v) node hitsVec_tagMatch_4 = and(special_entry.valid[0], _hitsVec_tagMatch_T_4) node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0)) node _hitsVec_T_108 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_109 = bits(_hitsVec_T_108, 26, 18) node _hitsVec_T_110 = eq(_hitsVec_T_109, UInt<1>(0h0)) node _hitsVec_T_111 = or(hitsVec_ignore_12, _hitsVec_T_110) node _hitsVec_T_112 = and(hitsVec_tagMatch_4, _hitsVec_T_111) node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0)) node _hitsVec_T_113 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_114 = bits(_hitsVec_T_113, 17, 9) node _hitsVec_T_115 = eq(_hitsVec_T_114, UInt<1>(0h0)) node _hitsVec_T_116 = or(hitsVec_ignore_13, _hitsVec_T_115) node _hitsVec_T_117 = and(_hitsVec_T_112, _hitsVec_T_116) node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0)) node _hitsVec_T_118 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_119 = bits(_hitsVec_T_118, 8, 0) node _hitsVec_T_120 = eq(_hitsVec_T_119, UInt<1>(0h0)) node _hitsVec_T_121 = or(hitsVec_ignore_14, _hitsVec_T_120) node _hitsVec_T_122 = and(_hitsVec_T_117, _hitsVec_T_121) node hitsVec_12 = and(vm_enabled, _hitsVec_T_122) node real_hits_lo_lo_hi = cat(hitsVec_2, hitsVec_1) node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec_0) node real_hits_lo_hi_hi = cat(hitsVec_5, hitsVec_4) node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec_3) node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo) node real_hits_hi_lo_hi = cat(hitsVec_8, hitsVec_7) node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec_6) node real_hits_hi_hi_lo = cat(hitsVec_10, hitsVec_9) node real_hits_hi_hi_hi = cat(hitsVec_12, hitsVec_11) node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo) node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo) node real_hits = cat(real_hits_hi, real_hits_lo) node _hits_T = eq(vm_enabled, UInt<1>(0h0)) node hits = cat(_hits_T, real_hits) when do_refill : node refill_v = or(r_vstage1_en, r_stage2_en) wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable connect newEntry.u, io.ptw.resp.bits.pte.u node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) connect newEntry.g, _newEntry_g_T connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw connect newEntry.ae_final, io.ptw.resp.bits.ae_final node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 connect newEntry.pf, io.ptw.resp.bits.pf connect newEntry.gf, io.ptw.resp.bits.gf connect newEntry.hr, io.ptw.resp.bits.hr connect newEntry.hw, io.ptw.resp.bits.hw connect newEntry.hx, io.ptw.resp.bits.hx node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r connect newEntry.pw, prot_w connect newEntry.px, prot_x connect newEntry.ppp, pma.io.resp.pp connect newEntry.pal, pma.io.resp.al connect newEntry.paa, pma.io.resp.aa connect newEntry.eff, pma.io.resp.eff connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag_vpn, r_refill_tag connect special_entry.tag_v, refill_v node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag_vpn, r_refill_tag connect superpage_entries[0].tag_v, refill_v node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T when invalidate_refill : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) when _T_4 : connect superpage_entries[1].tag_vpn, r_refill_tag connect superpage_entries[1].tag_v, refill_v node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[1].level, _superpage_entries_1_level_T connect superpage_entries[1].valid[0], UInt<1>(0h1) node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo) node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T when invalidate_refill : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) when _T_5 : connect superpage_entries[2].tag_vpn, r_refill_tag connect superpage_entries[2].tag_v, refill_v node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[2].level, _superpage_entries_2_level_T connect superpage_entries[2].valid[0], UInt<1>(0h1) node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo) node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T when invalidate_refill : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) when _T_6 : connect superpage_entries[3].tag_vpn, r_refill_tag connect superpage_entries[3].tag_v, refill_v node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[3].level, _superpage_entries_3_level_T connect superpage_entries[3].valid[0], UInt<1>(0h1) node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo) node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T when invalidate_refill : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) node _T_7 = eq(waddr_1, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_8 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][0].tag_vpn, r_refill_tag connect sectored_entries[0][0].tag_v, refill_v connect sectored_entries[0][0].level, UInt<2>(0h0) node idx = bits(r_refill_tag, 1, 0) connect sectored_entries[0][0].valid[idx], UInt<1>(0h1) node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo) node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo) node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo) node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo) node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo) node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo) node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo) connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T when invalidate_refill : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_9 = eq(waddr_1, UInt<1>(0h1)) when _T_9 : node _T_10 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_10 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].tag_vpn, r_refill_tag connect sectored_entries[0][1].tag_v, refill_v connect sectored_entries[0][1].level, UInt<2>(0h0) node idx_1 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][1].valid[idx_1], UInt<1>(0h1) node sectored_entries_0_1_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_1_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_1_data_lo_lo_hi = cat(sectored_entries_0_1_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_1_data_lo_lo = cat(sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo) node sectored_entries_0_1_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_1_data_lo_hi_lo = cat(sectored_entries_0_1_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_1_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_1_data_lo_hi_hi = cat(sectored_entries_0_1_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_1_data_lo_hi = cat(sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo) node sectored_entries_0_1_data_lo = cat(sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo) node sectored_entries_0_1_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_1_data_hi_lo_lo = cat(sectored_entries_0_1_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_1_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_1_data_hi_lo_hi = cat(sectored_entries_0_1_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_1_data_hi_lo = cat(sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo) node sectored_entries_0_1_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_1_data_hi_hi_lo = cat(sectored_entries_0_1_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_1_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_1_data_hi_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_1_data_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo) node sectored_entries_0_1_data_hi = cat(sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo) node _sectored_entries_0_1_data_T = cat(sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo) connect sectored_entries[0][1].data[idx_1], _sectored_entries_0_1_data_T when invalidate_refill : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_11 = eq(waddr_1, UInt<2>(0h2)) when _T_11 : node _T_12 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_12 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].tag_vpn, r_refill_tag connect sectored_entries[0][2].tag_v, refill_v connect sectored_entries[0][2].level, UInt<2>(0h0) node idx_2 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][2].valid[idx_2], UInt<1>(0h1) node sectored_entries_0_2_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_2_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_2_data_lo_lo_hi = cat(sectored_entries_0_2_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_2_data_lo_lo = cat(sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo) node sectored_entries_0_2_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_2_data_lo_hi_lo = cat(sectored_entries_0_2_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_2_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_2_data_lo_hi_hi = cat(sectored_entries_0_2_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_2_data_lo_hi = cat(sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo) node sectored_entries_0_2_data_lo = cat(sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo) node sectored_entries_0_2_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_2_data_hi_lo_lo = cat(sectored_entries_0_2_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_2_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_2_data_hi_lo_hi = cat(sectored_entries_0_2_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_2_data_hi_lo = cat(sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo) node sectored_entries_0_2_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_2_data_hi_hi_lo = cat(sectored_entries_0_2_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_2_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_2_data_hi_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_2_data_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo) node sectored_entries_0_2_data_hi = cat(sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo) node _sectored_entries_0_2_data_T = cat(sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo) connect sectored_entries[0][2].data[idx_2], _sectored_entries_0_2_data_T when invalidate_refill : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_13 = eq(waddr_1, UInt<2>(0h3)) when _T_13 : node _T_14 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_14 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].tag_vpn, r_refill_tag connect sectored_entries[0][3].tag_v, refill_v connect sectored_entries[0][3].level, UInt<2>(0h0) node idx_3 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][3].valid[idx_3], UInt<1>(0h1) node sectored_entries_0_3_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_3_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_3_data_lo_lo_hi = cat(sectored_entries_0_3_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_3_data_lo_lo = cat(sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo) node sectored_entries_0_3_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_3_data_lo_hi_lo = cat(sectored_entries_0_3_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_3_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_3_data_lo_hi_hi = cat(sectored_entries_0_3_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_3_data_lo_hi = cat(sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo) node sectored_entries_0_3_data_lo = cat(sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo) node sectored_entries_0_3_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_3_data_hi_lo_lo = cat(sectored_entries_0_3_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_3_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_3_data_hi_lo_hi = cat(sectored_entries_0_3_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_3_data_hi_lo = cat(sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo) node sectored_entries_0_3_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_3_data_hi_hi_lo = cat(sectored_entries_0_3_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_3_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_3_data_hi_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_3_data_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo) node sectored_entries_0_3_data_hi = cat(sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo) node _sectored_entries_0_3_data_T = cat(sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo) connect sectored_entries[0][3].data[idx_3], _sectored_entries_0_3_data_T when invalidate_refill : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_15 = eq(waddr_1, UInt<3>(0h4)) when _T_15 : node _T_16 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_16 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].tag_vpn, r_refill_tag connect sectored_entries[0][4].tag_v, refill_v connect sectored_entries[0][4].level, UInt<2>(0h0) node idx_4 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][4].valid[idx_4], UInt<1>(0h1) node sectored_entries_0_4_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_4_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_4_data_lo_lo_hi = cat(sectored_entries_0_4_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_4_data_lo_lo = cat(sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo) node sectored_entries_0_4_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_4_data_lo_hi_lo = cat(sectored_entries_0_4_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_4_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_4_data_lo_hi_hi = cat(sectored_entries_0_4_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_4_data_lo_hi = cat(sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo) node sectored_entries_0_4_data_lo = cat(sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo) node sectored_entries_0_4_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_4_data_hi_lo_lo = cat(sectored_entries_0_4_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_4_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_4_data_hi_lo_hi = cat(sectored_entries_0_4_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_4_data_hi_lo = cat(sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo) node sectored_entries_0_4_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_4_data_hi_hi_lo = cat(sectored_entries_0_4_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_4_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_4_data_hi_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_4_data_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo) node sectored_entries_0_4_data_hi = cat(sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo) node _sectored_entries_0_4_data_T = cat(sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo) connect sectored_entries[0][4].data[idx_4], _sectored_entries_0_4_data_T when invalidate_refill : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_17 = eq(waddr_1, UInt<3>(0h5)) when _T_17 : node _T_18 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_18 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].tag_vpn, r_refill_tag connect sectored_entries[0][5].tag_v, refill_v connect sectored_entries[0][5].level, UInt<2>(0h0) node idx_5 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][5].valid[idx_5], UInt<1>(0h1) node sectored_entries_0_5_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_5_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_5_data_lo_lo_hi = cat(sectored_entries_0_5_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_5_data_lo_lo = cat(sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo) node sectored_entries_0_5_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_5_data_lo_hi_lo = cat(sectored_entries_0_5_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_5_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_5_data_lo_hi_hi = cat(sectored_entries_0_5_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_5_data_lo_hi = cat(sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo) node sectored_entries_0_5_data_lo = cat(sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo) node sectored_entries_0_5_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_5_data_hi_lo_lo = cat(sectored_entries_0_5_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_5_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_5_data_hi_lo_hi = cat(sectored_entries_0_5_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_5_data_hi_lo = cat(sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo) node sectored_entries_0_5_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_5_data_hi_hi_lo = cat(sectored_entries_0_5_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_5_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_5_data_hi_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_5_data_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo) node sectored_entries_0_5_data_hi = cat(sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo) node _sectored_entries_0_5_data_T = cat(sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo) connect sectored_entries[0][5].data[idx_5], _sectored_entries_0_5_data_T when invalidate_refill : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_19 = eq(waddr_1, UInt<3>(0h6)) when _T_19 : node _T_20 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_20 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].tag_vpn, r_refill_tag connect sectored_entries[0][6].tag_v, refill_v connect sectored_entries[0][6].level, UInt<2>(0h0) node idx_6 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][6].valid[idx_6], UInt<1>(0h1) node sectored_entries_0_6_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_6_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_6_data_lo_lo_hi = cat(sectored_entries_0_6_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_6_data_lo_lo = cat(sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo) node sectored_entries_0_6_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_6_data_lo_hi_lo = cat(sectored_entries_0_6_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_6_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_6_data_lo_hi_hi = cat(sectored_entries_0_6_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_6_data_lo_hi = cat(sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo) node sectored_entries_0_6_data_lo = cat(sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo) node sectored_entries_0_6_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_6_data_hi_lo_lo = cat(sectored_entries_0_6_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_6_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_6_data_hi_lo_hi = cat(sectored_entries_0_6_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_6_data_hi_lo = cat(sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo) node sectored_entries_0_6_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_6_data_hi_hi_lo = cat(sectored_entries_0_6_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_6_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_6_data_hi_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_6_data_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo) node sectored_entries_0_6_data_hi = cat(sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo) node _sectored_entries_0_6_data_T = cat(sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo) connect sectored_entries[0][6].data[idx_6], _sectored_entries_0_6_data_T when invalidate_refill : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_21 = eq(waddr_1, UInt<3>(0h7)) when _T_21 : node _T_22 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_22 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].tag_vpn, r_refill_tag connect sectored_entries[0][7].tag_v, refill_v connect sectored_entries[0][7].level, UInt<2>(0h0) node idx_7 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][7].valid[idx_7], UInt<1>(0h1) node sectored_entries_0_7_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_7_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_7_data_lo_lo_hi = cat(sectored_entries_0_7_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_7_data_lo_lo = cat(sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo) node sectored_entries_0_7_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_7_data_lo_hi_lo = cat(sectored_entries_0_7_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_7_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_7_data_lo_hi_hi = cat(sectored_entries_0_7_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_7_data_lo_hi = cat(sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo) node sectored_entries_0_7_data_lo = cat(sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo) node sectored_entries_0_7_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_7_data_hi_lo_lo = cat(sectored_entries_0_7_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_7_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_7_data_hi_lo_hi = cat(sectored_entries_0_7_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_7_data_hi_lo = cat(sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo) node sectored_entries_0_7_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_7_data_hi_hi_lo = cat(sectored_entries_0_7_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_7_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_7_data_hi_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_7_data_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo) node sectored_entries_0_7_data_hi = cat(sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo) node _sectored_entries_0_7_data_T = cat(sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo) connect sectored_entries[0][7].data[idx_7], _sectored_entries_0_7_data_T when invalidate_refill : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect r_gpa_valid, io.ptw.resp.bits.gpa.valid connect r_gpa, io.ptw.resp.bits.gpa.bits connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte node _entries_T = bits(vpn, 1, 0) wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<42> connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.ppp, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.pr, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.px, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.pw, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.hr, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.hx, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.hw, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.sr, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.sx, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 14, 14) connect _entries_WIRE.sw, _entries_T_15 node _entries_T_16 = bits(_entries_WIRE_1, 15, 15) connect _entries_WIRE.gf, _entries_T_16 node _entries_T_17 = bits(_entries_WIRE_1, 16, 16) connect _entries_WIRE.pf, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_1, 17, 17) connect _entries_WIRE.ae_stage2, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_1, 18, 18) connect _entries_WIRE.ae_final, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_1, 19, 19) connect _entries_WIRE.ae_ptw, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_1, 20, 20) connect _entries_WIRE.g, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_1, 21, 21) connect _entries_WIRE.u, _entries_T_22 node _entries_T_23 = bits(_entries_WIRE_1, 41, 22) connect _entries_WIRE.ppn, _entries_T_23 inst entries_barrier of OptimizationBarrier_TLBEntryData_127 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.ppp, _entries_WIRE.ppp connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.hr, _entries_WIRE.hr connect entries_barrier.io.x.hx, _entries_WIRE.hx connect entries_barrier.io.x.hw, _entries_WIRE.hw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.gf, _entries_WIRE.gf connect entries_barrier.io.x.pf, _entries_WIRE.pf connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn node _entries_T_24 = bits(vpn, 1, 0) wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<42> connect _entries_WIRE_3, sectored_entries[0][1].data[_entries_T_24] node _entries_T_25 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.ppp, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.pr, _entries_T_31 node _entries_T_32 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.px, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.pw, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.hr, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.hx, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.hw, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.sr, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.sx, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_3, 14, 14) connect _entries_WIRE_2.sw, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_3, 15, 15) connect _entries_WIRE_2.gf, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_3, 16, 16) connect _entries_WIRE_2.pf, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_3, 17, 17) connect _entries_WIRE_2.ae_stage2, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_3, 18, 18) connect _entries_WIRE_2.ae_final, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_3, 19, 19) connect _entries_WIRE_2.ae_ptw, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_3, 20, 20) connect _entries_WIRE_2.g, _entries_T_45 node _entries_T_46 = bits(_entries_WIRE_3, 21, 21) connect _entries_WIRE_2.u, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_3, 41, 22) connect _entries_WIRE_2.ppn, _entries_T_47 inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_128 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn node _entries_T_48 = bits(vpn, 1, 0) wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<42> connect _entries_WIRE_5, sectored_entries[0][2].data[_entries_T_48] node _entries_T_49 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.ppp, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.pr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.px, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.pw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.hr, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.hx, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.hw, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.sr, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.sx, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_5, 14, 14) connect _entries_WIRE_4.sw, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_5, 15, 15) connect _entries_WIRE_4.gf, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_5, 16, 16) connect _entries_WIRE_4.pf, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_5, 17, 17) connect _entries_WIRE_4.ae_stage2, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_5, 18, 18) connect _entries_WIRE_4.ae_final, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_5, 19, 19) connect _entries_WIRE_4.ae_ptw, _entries_T_68 node _entries_T_69 = bits(_entries_WIRE_5, 20, 20) connect _entries_WIRE_4.g, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_5, 21, 21) connect _entries_WIRE_4.u, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_5, 41, 22) connect _entries_WIRE_4.ppn, _entries_T_71 inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_129 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn node _entries_T_72 = bits(vpn, 1, 0) wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<42> connect _entries_WIRE_7, sectored_entries[0][3].data[_entries_T_72] node _entries_T_73 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.ppp, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.pr, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.px, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.pw, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.hr, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.hx, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.hw, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.sr, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.sx, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_7, 14, 14) connect _entries_WIRE_6.sw, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_7, 15, 15) connect _entries_WIRE_6.gf, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_7, 16, 16) connect _entries_WIRE_6.pf, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_7, 17, 17) connect _entries_WIRE_6.ae_stage2, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_7, 18, 18) connect _entries_WIRE_6.ae_final, _entries_T_91 node _entries_T_92 = bits(_entries_WIRE_7, 19, 19) connect _entries_WIRE_6.ae_ptw, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_7, 20, 20) connect _entries_WIRE_6.g, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_7, 21, 21) connect _entries_WIRE_6.u, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_7, 41, 22) connect _entries_WIRE_6.ppn, _entries_T_95 inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_130 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn node _entries_T_96 = bits(vpn, 1, 0) wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<42> connect _entries_WIRE_9, sectored_entries[0][4].data[_entries_T_96] node _entries_T_97 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.ppp, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.pr, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.px, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.pw, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.hr, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.hx, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.hw, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.sr, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.sx, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_9, 14, 14) connect _entries_WIRE_8.sw, _entries_T_111 node _entries_T_112 = bits(_entries_WIRE_9, 15, 15) connect _entries_WIRE_8.gf, _entries_T_112 node _entries_T_113 = bits(_entries_WIRE_9, 16, 16) connect _entries_WIRE_8.pf, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_9, 17, 17) connect _entries_WIRE_8.ae_stage2, _entries_T_114 node _entries_T_115 = bits(_entries_WIRE_9, 18, 18) connect _entries_WIRE_8.ae_final, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_9, 19, 19) connect _entries_WIRE_8.ae_ptw, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_9, 20, 20) connect _entries_WIRE_8.g, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_9, 21, 21) connect _entries_WIRE_8.u, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_9, 41, 22) connect _entries_WIRE_8.ppn, _entries_T_119 inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_131 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn node _entries_T_120 = bits(vpn, 1, 0) wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<42> connect _entries_WIRE_11, sectored_entries[0][5].data[_entries_T_120] node _entries_T_121 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.ppp, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.pr, _entries_T_127 node _entries_T_128 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.px, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.pw, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.hr, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.hx, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.hw, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.sr, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.sx, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_11, 14, 14) connect _entries_WIRE_10.sw, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_11, 15, 15) connect _entries_WIRE_10.gf, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_11, 16, 16) connect _entries_WIRE_10.pf, _entries_T_137 node _entries_T_138 = bits(_entries_WIRE_11, 17, 17) connect _entries_WIRE_10.ae_stage2, _entries_T_138 node _entries_T_139 = bits(_entries_WIRE_11, 18, 18) connect _entries_WIRE_10.ae_final, _entries_T_139 node _entries_T_140 = bits(_entries_WIRE_11, 19, 19) connect _entries_WIRE_10.ae_ptw, _entries_T_140 node _entries_T_141 = bits(_entries_WIRE_11, 20, 20) connect _entries_WIRE_10.g, _entries_T_141 node _entries_T_142 = bits(_entries_WIRE_11, 21, 21) connect _entries_WIRE_10.u, _entries_T_142 node _entries_T_143 = bits(_entries_WIRE_11, 41, 22) connect _entries_WIRE_10.ppn, _entries_T_143 inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_132 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _entries_T_144 = bits(vpn, 1, 0) wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_13 : UInt<42> connect _entries_WIRE_13, sectored_entries[0][6].data[_entries_T_144] node _entries_T_145 = bits(_entries_WIRE_13, 0, 0) connect _entries_WIRE_12.fragmented_superpage, _entries_T_145 node _entries_T_146 = bits(_entries_WIRE_13, 1, 1) connect _entries_WIRE_12.c, _entries_T_146 node _entries_T_147 = bits(_entries_WIRE_13, 2, 2) connect _entries_WIRE_12.eff, _entries_T_147 node _entries_T_148 = bits(_entries_WIRE_13, 3, 3) connect _entries_WIRE_12.paa, _entries_T_148 node _entries_T_149 = bits(_entries_WIRE_13, 4, 4) connect _entries_WIRE_12.pal, _entries_T_149 node _entries_T_150 = bits(_entries_WIRE_13, 5, 5) connect _entries_WIRE_12.ppp, _entries_T_150 node _entries_T_151 = bits(_entries_WIRE_13, 6, 6) connect _entries_WIRE_12.pr, _entries_T_151 node _entries_T_152 = bits(_entries_WIRE_13, 7, 7) connect _entries_WIRE_12.px, _entries_T_152 node _entries_T_153 = bits(_entries_WIRE_13, 8, 8) connect _entries_WIRE_12.pw, _entries_T_153 node _entries_T_154 = bits(_entries_WIRE_13, 9, 9) connect _entries_WIRE_12.hr, _entries_T_154 node _entries_T_155 = bits(_entries_WIRE_13, 10, 10) connect _entries_WIRE_12.hx, _entries_T_155 node _entries_T_156 = bits(_entries_WIRE_13, 11, 11) connect _entries_WIRE_12.hw, _entries_T_156 node _entries_T_157 = bits(_entries_WIRE_13, 12, 12) connect _entries_WIRE_12.sr, _entries_T_157 node _entries_T_158 = bits(_entries_WIRE_13, 13, 13) connect _entries_WIRE_12.sx, _entries_T_158 node _entries_T_159 = bits(_entries_WIRE_13, 14, 14) connect _entries_WIRE_12.sw, _entries_T_159 node _entries_T_160 = bits(_entries_WIRE_13, 15, 15) connect _entries_WIRE_12.gf, _entries_T_160 node _entries_T_161 = bits(_entries_WIRE_13, 16, 16) connect _entries_WIRE_12.pf, _entries_T_161 node _entries_T_162 = bits(_entries_WIRE_13, 17, 17) connect _entries_WIRE_12.ae_stage2, _entries_T_162 node _entries_T_163 = bits(_entries_WIRE_13, 18, 18) connect _entries_WIRE_12.ae_final, _entries_T_163 node _entries_T_164 = bits(_entries_WIRE_13, 19, 19) connect _entries_WIRE_12.ae_ptw, _entries_T_164 node _entries_T_165 = bits(_entries_WIRE_13, 20, 20) connect _entries_WIRE_12.g, _entries_T_165 node _entries_T_166 = bits(_entries_WIRE_13, 21, 21) connect _entries_WIRE_12.u, _entries_T_166 node _entries_T_167 = bits(_entries_WIRE_13, 41, 22) connect _entries_WIRE_12.ppn, _entries_T_167 inst entries_barrier_6 of OptimizationBarrier_TLBEntryData_133 connect entries_barrier_6.clock, clock connect entries_barrier_6.reset, reset connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage connect entries_barrier_6.io.x.c, _entries_WIRE_12.c connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal connect entries_barrier_6.io.x.ppp, _entries_WIRE_12.ppp connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr connect entries_barrier_6.io.x.px, _entries_WIRE_12.px connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw connect entries_barrier_6.io.x.hr, _entries_WIRE_12.hr connect entries_barrier_6.io.x.hx, _entries_WIRE_12.hx connect entries_barrier_6.io.x.hw, _entries_WIRE_12.hw connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw connect entries_barrier_6.io.x.gf, _entries_WIRE_12.gf connect entries_barrier_6.io.x.pf, _entries_WIRE_12.pf connect entries_barrier_6.io.x.ae_stage2, _entries_WIRE_12.ae_stage2 connect entries_barrier_6.io.x.ae_final, _entries_WIRE_12.ae_final connect entries_barrier_6.io.x.ae_ptw, _entries_WIRE_12.ae_ptw connect entries_barrier_6.io.x.g, _entries_WIRE_12.g connect entries_barrier_6.io.x.u, _entries_WIRE_12.u connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn node _entries_T_168 = bits(vpn, 1, 0) wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_15 : UInt<42> connect _entries_WIRE_15, sectored_entries[0][7].data[_entries_T_168] node _entries_T_169 = bits(_entries_WIRE_15, 0, 0) connect _entries_WIRE_14.fragmented_superpage, _entries_T_169 node _entries_T_170 = bits(_entries_WIRE_15, 1, 1) connect _entries_WIRE_14.c, _entries_T_170 node _entries_T_171 = bits(_entries_WIRE_15, 2, 2) connect _entries_WIRE_14.eff, _entries_T_171 node _entries_T_172 = bits(_entries_WIRE_15, 3, 3) connect _entries_WIRE_14.paa, _entries_T_172 node _entries_T_173 = bits(_entries_WIRE_15, 4, 4) connect _entries_WIRE_14.pal, _entries_T_173 node _entries_T_174 = bits(_entries_WIRE_15, 5, 5) connect _entries_WIRE_14.ppp, _entries_T_174 node _entries_T_175 = bits(_entries_WIRE_15, 6, 6) connect _entries_WIRE_14.pr, _entries_T_175 node _entries_T_176 = bits(_entries_WIRE_15, 7, 7) connect _entries_WIRE_14.px, _entries_T_176 node _entries_T_177 = bits(_entries_WIRE_15, 8, 8) connect _entries_WIRE_14.pw, _entries_T_177 node _entries_T_178 = bits(_entries_WIRE_15, 9, 9) connect _entries_WIRE_14.hr, _entries_T_178 node _entries_T_179 = bits(_entries_WIRE_15, 10, 10) connect _entries_WIRE_14.hx, _entries_T_179 node _entries_T_180 = bits(_entries_WIRE_15, 11, 11) connect _entries_WIRE_14.hw, _entries_T_180 node _entries_T_181 = bits(_entries_WIRE_15, 12, 12) connect _entries_WIRE_14.sr, _entries_T_181 node _entries_T_182 = bits(_entries_WIRE_15, 13, 13) connect _entries_WIRE_14.sx, _entries_T_182 node _entries_T_183 = bits(_entries_WIRE_15, 14, 14) connect _entries_WIRE_14.sw, _entries_T_183 node _entries_T_184 = bits(_entries_WIRE_15, 15, 15) connect _entries_WIRE_14.gf, _entries_T_184 node _entries_T_185 = bits(_entries_WIRE_15, 16, 16) connect _entries_WIRE_14.pf, _entries_T_185 node _entries_T_186 = bits(_entries_WIRE_15, 17, 17) connect _entries_WIRE_14.ae_stage2, _entries_T_186 node _entries_T_187 = bits(_entries_WIRE_15, 18, 18) connect _entries_WIRE_14.ae_final, _entries_T_187 node _entries_T_188 = bits(_entries_WIRE_15, 19, 19) connect _entries_WIRE_14.ae_ptw, _entries_T_188 node _entries_T_189 = bits(_entries_WIRE_15, 20, 20) connect _entries_WIRE_14.g, _entries_T_189 node _entries_T_190 = bits(_entries_WIRE_15, 21, 21) connect _entries_WIRE_14.u, _entries_T_190 node _entries_T_191 = bits(_entries_WIRE_15, 41, 22) connect _entries_WIRE_14.ppn, _entries_T_191 inst entries_barrier_7 of OptimizationBarrier_TLBEntryData_134 connect entries_barrier_7.clock, clock connect entries_barrier_7.reset, reset connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage connect entries_barrier_7.io.x.c, _entries_WIRE_14.c connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal connect entries_barrier_7.io.x.ppp, _entries_WIRE_14.ppp connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr connect entries_barrier_7.io.x.px, _entries_WIRE_14.px connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw connect entries_barrier_7.io.x.hr, _entries_WIRE_14.hr connect entries_barrier_7.io.x.hx, _entries_WIRE_14.hx connect entries_barrier_7.io.x.hw, _entries_WIRE_14.hw connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw connect entries_barrier_7.io.x.gf, _entries_WIRE_14.gf connect entries_barrier_7.io.x.pf, _entries_WIRE_14.pf connect entries_barrier_7.io.x.ae_stage2, _entries_WIRE_14.ae_stage2 connect entries_barrier_7.io.x.ae_final, _entries_WIRE_14.ae_final connect entries_barrier_7.io.x.ae_ptw, _entries_WIRE_14.ae_ptw connect entries_barrier_7.io.x.g, _entries_WIRE_14.g connect entries_barrier_7.io.x.u, _entries_WIRE_14.u connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_17 : UInt<42> connect _entries_WIRE_17, superpage_entries[0].data[0] node _entries_T_192 = bits(_entries_WIRE_17, 0, 0) connect _entries_WIRE_16.fragmented_superpage, _entries_T_192 node _entries_T_193 = bits(_entries_WIRE_17, 1, 1) connect _entries_WIRE_16.c, _entries_T_193 node _entries_T_194 = bits(_entries_WIRE_17, 2, 2) connect _entries_WIRE_16.eff, _entries_T_194 node _entries_T_195 = bits(_entries_WIRE_17, 3, 3) connect _entries_WIRE_16.paa, _entries_T_195 node _entries_T_196 = bits(_entries_WIRE_17, 4, 4) connect _entries_WIRE_16.pal, _entries_T_196 node _entries_T_197 = bits(_entries_WIRE_17, 5, 5) connect _entries_WIRE_16.ppp, _entries_T_197 node _entries_T_198 = bits(_entries_WIRE_17, 6, 6) connect _entries_WIRE_16.pr, _entries_T_198 node _entries_T_199 = bits(_entries_WIRE_17, 7, 7) connect _entries_WIRE_16.px, _entries_T_199 node _entries_T_200 = bits(_entries_WIRE_17, 8, 8) connect _entries_WIRE_16.pw, _entries_T_200 node _entries_T_201 = bits(_entries_WIRE_17, 9, 9) connect _entries_WIRE_16.hr, _entries_T_201 node _entries_T_202 = bits(_entries_WIRE_17, 10, 10) connect _entries_WIRE_16.hx, _entries_T_202 node _entries_T_203 = bits(_entries_WIRE_17, 11, 11) connect _entries_WIRE_16.hw, _entries_T_203 node _entries_T_204 = bits(_entries_WIRE_17, 12, 12) connect _entries_WIRE_16.sr, _entries_T_204 node _entries_T_205 = bits(_entries_WIRE_17, 13, 13) connect _entries_WIRE_16.sx, _entries_T_205 node _entries_T_206 = bits(_entries_WIRE_17, 14, 14) connect _entries_WIRE_16.sw, _entries_T_206 node _entries_T_207 = bits(_entries_WIRE_17, 15, 15) connect _entries_WIRE_16.gf, _entries_T_207 node _entries_T_208 = bits(_entries_WIRE_17, 16, 16) connect _entries_WIRE_16.pf, _entries_T_208 node _entries_T_209 = bits(_entries_WIRE_17, 17, 17) connect _entries_WIRE_16.ae_stage2, _entries_T_209 node _entries_T_210 = bits(_entries_WIRE_17, 18, 18) connect _entries_WIRE_16.ae_final, _entries_T_210 node _entries_T_211 = bits(_entries_WIRE_17, 19, 19) connect _entries_WIRE_16.ae_ptw, _entries_T_211 node _entries_T_212 = bits(_entries_WIRE_17, 20, 20) connect _entries_WIRE_16.g, _entries_T_212 node _entries_T_213 = bits(_entries_WIRE_17, 21, 21) connect _entries_WIRE_16.u, _entries_T_213 node _entries_T_214 = bits(_entries_WIRE_17, 41, 22) connect _entries_WIRE_16.ppn, _entries_T_214 inst entries_barrier_8 of OptimizationBarrier_TLBEntryData_135 connect entries_barrier_8.clock, clock connect entries_barrier_8.reset, reset connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage connect entries_barrier_8.io.x.c, _entries_WIRE_16.c connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal connect entries_barrier_8.io.x.ppp, _entries_WIRE_16.ppp connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr connect entries_barrier_8.io.x.px, _entries_WIRE_16.px connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw connect entries_barrier_8.io.x.hr, _entries_WIRE_16.hr connect entries_barrier_8.io.x.hx, _entries_WIRE_16.hx connect entries_barrier_8.io.x.hw, _entries_WIRE_16.hw connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw connect entries_barrier_8.io.x.gf, _entries_WIRE_16.gf connect entries_barrier_8.io.x.pf, _entries_WIRE_16.pf connect entries_barrier_8.io.x.ae_stage2, _entries_WIRE_16.ae_stage2 connect entries_barrier_8.io.x.ae_final, _entries_WIRE_16.ae_final connect entries_barrier_8.io.x.ae_ptw, _entries_WIRE_16.ae_ptw connect entries_barrier_8.io.x.g, _entries_WIRE_16.g connect entries_barrier_8.io.x.u, _entries_WIRE_16.u connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_19 : UInt<42> connect _entries_WIRE_19, superpage_entries[1].data[0] node _entries_T_215 = bits(_entries_WIRE_19, 0, 0) connect _entries_WIRE_18.fragmented_superpage, _entries_T_215 node _entries_T_216 = bits(_entries_WIRE_19, 1, 1) connect _entries_WIRE_18.c, _entries_T_216 node _entries_T_217 = bits(_entries_WIRE_19, 2, 2) connect _entries_WIRE_18.eff, _entries_T_217 node _entries_T_218 = bits(_entries_WIRE_19, 3, 3) connect _entries_WIRE_18.paa, _entries_T_218 node _entries_T_219 = bits(_entries_WIRE_19, 4, 4) connect _entries_WIRE_18.pal, _entries_T_219 node _entries_T_220 = bits(_entries_WIRE_19, 5, 5) connect _entries_WIRE_18.ppp, _entries_T_220 node _entries_T_221 = bits(_entries_WIRE_19, 6, 6) connect _entries_WIRE_18.pr, _entries_T_221 node _entries_T_222 = bits(_entries_WIRE_19, 7, 7) connect _entries_WIRE_18.px, _entries_T_222 node _entries_T_223 = bits(_entries_WIRE_19, 8, 8) connect _entries_WIRE_18.pw, _entries_T_223 node _entries_T_224 = bits(_entries_WIRE_19, 9, 9) connect _entries_WIRE_18.hr, _entries_T_224 node _entries_T_225 = bits(_entries_WIRE_19, 10, 10) connect _entries_WIRE_18.hx, _entries_T_225 node _entries_T_226 = bits(_entries_WIRE_19, 11, 11) connect _entries_WIRE_18.hw, _entries_T_226 node _entries_T_227 = bits(_entries_WIRE_19, 12, 12) connect _entries_WIRE_18.sr, _entries_T_227 node _entries_T_228 = bits(_entries_WIRE_19, 13, 13) connect _entries_WIRE_18.sx, _entries_T_228 node _entries_T_229 = bits(_entries_WIRE_19, 14, 14) connect _entries_WIRE_18.sw, _entries_T_229 node _entries_T_230 = bits(_entries_WIRE_19, 15, 15) connect _entries_WIRE_18.gf, _entries_T_230 node _entries_T_231 = bits(_entries_WIRE_19, 16, 16) connect _entries_WIRE_18.pf, _entries_T_231 node _entries_T_232 = bits(_entries_WIRE_19, 17, 17) connect _entries_WIRE_18.ae_stage2, _entries_T_232 node _entries_T_233 = bits(_entries_WIRE_19, 18, 18) connect _entries_WIRE_18.ae_final, _entries_T_233 node _entries_T_234 = bits(_entries_WIRE_19, 19, 19) connect _entries_WIRE_18.ae_ptw, _entries_T_234 node _entries_T_235 = bits(_entries_WIRE_19, 20, 20) connect _entries_WIRE_18.g, _entries_T_235 node _entries_T_236 = bits(_entries_WIRE_19, 21, 21) connect _entries_WIRE_18.u, _entries_T_236 node _entries_T_237 = bits(_entries_WIRE_19, 41, 22) connect _entries_WIRE_18.ppn, _entries_T_237 inst entries_barrier_9 of OptimizationBarrier_TLBEntryData_136 connect entries_barrier_9.clock, clock connect entries_barrier_9.reset, reset connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage connect entries_barrier_9.io.x.c, _entries_WIRE_18.c connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal connect entries_barrier_9.io.x.ppp, _entries_WIRE_18.ppp connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr connect entries_barrier_9.io.x.px, _entries_WIRE_18.px connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw connect entries_barrier_9.io.x.hr, _entries_WIRE_18.hr connect entries_barrier_9.io.x.hx, _entries_WIRE_18.hx connect entries_barrier_9.io.x.hw, _entries_WIRE_18.hw connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw connect entries_barrier_9.io.x.gf, _entries_WIRE_18.gf connect entries_barrier_9.io.x.pf, _entries_WIRE_18.pf connect entries_barrier_9.io.x.ae_stage2, _entries_WIRE_18.ae_stage2 connect entries_barrier_9.io.x.ae_final, _entries_WIRE_18.ae_final connect entries_barrier_9.io.x.ae_ptw, _entries_WIRE_18.ae_ptw connect entries_barrier_9.io.x.g, _entries_WIRE_18.g connect entries_barrier_9.io.x.u, _entries_WIRE_18.u connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_21 : UInt<42> connect _entries_WIRE_21, superpage_entries[2].data[0] node _entries_T_238 = bits(_entries_WIRE_21, 0, 0) connect _entries_WIRE_20.fragmented_superpage, _entries_T_238 node _entries_T_239 = bits(_entries_WIRE_21, 1, 1) connect _entries_WIRE_20.c, _entries_T_239 node _entries_T_240 = bits(_entries_WIRE_21, 2, 2) connect _entries_WIRE_20.eff, _entries_T_240 node _entries_T_241 = bits(_entries_WIRE_21, 3, 3) connect _entries_WIRE_20.paa, _entries_T_241 node _entries_T_242 = bits(_entries_WIRE_21, 4, 4) connect _entries_WIRE_20.pal, _entries_T_242 node _entries_T_243 = bits(_entries_WIRE_21, 5, 5) connect _entries_WIRE_20.ppp, _entries_T_243 node _entries_T_244 = bits(_entries_WIRE_21, 6, 6) connect _entries_WIRE_20.pr, _entries_T_244 node _entries_T_245 = bits(_entries_WIRE_21, 7, 7) connect _entries_WIRE_20.px, _entries_T_245 node _entries_T_246 = bits(_entries_WIRE_21, 8, 8) connect _entries_WIRE_20.pw, _entries_T_246 node _entries_T_247 = bits(_entries_WIRE_21, 9, 9) connect _entries_WIRE_20.hr, _entries_T_247 node _entries_T_248 = bits(_entries_WIRE_21, 10, 10) connect _entries_WIRE_20.hx, _entries_T_248 node _entries_T_249 = bits(_entries_WIRE_21, 11, 11) connect _entries_WIRE_20.hw, _entries_T_249 node _entries_T_250 = bits(_entries_WIRE_21, 12, 12) connect _entries_WIRE_20.sr, _entries_T_250 node _entries_T_251 = bits(_entries_WIRE_21, 13, 13) connect _entries_WIRE_20.sx, _entries_T_251 node _entries_T_252 = bits(_entries_WIRE_21, 14, 14) connect _entries_WIRE_20.sw, _entries_T_252 node _entries_T_253 = bits(_entries_WIRE_21, 15, 15) connect _entries_WIRE_20.gf, _entries_T_253 node _entries_T_254 = bits(_entries_WIRE_21, 16, 16) connect _entries_WIRE_20.pf, _entries_T_254 node _entries_T_255 = bits(_entries_WIRE_21, 17, 17) connect _entries_WIRE_20.ae_stage2, _entries_T_255 node _entries_T_256 = bits(_entries_WIRE_21, 18, 18) connect _entries_WIRE_20.ae_final, _entries_T_256 node _entries_T_257 = bits(_entries_WIRE_21, 19, 19) connect _entries_WIRE_20.ae_ptw, _entries_T_257 node _entries_T_258 = bits(_entries_WIRE_21, 20, 20) connect _entries_WIRE_20.g, _entries_T_258 node _entries_T_259 = bits(_entries_WIRE_21, 21, 21) connect _entries_WIRE_20.u, _entries_T_259 node _entries_T_260 = bits(_entries_WIRE_21, 41, 22) connect _entries_WIRE_20.ppn, _entries_T_260 inst entries_barrier_10 of OptimizationBarrier_TLBEntryData_137 connect entries_barrier_10.clock, clock connect entries_barrier_10.reset, reset connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage connect entries_barrier_10.io.x.c, _entries_WIRE_20.c connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal connect entries_barrier_10.io.x.ppp, _entries_WIRE_20.ppp connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr connect entries_barrier_10.io.x.px, _entries_WIRE_20.px connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw connect entries_barrier_10.io.x.hr, _entries_WIRE_20.hr connect entries_barrier_10.io.x.hx, _entries_WIRE_20.hx connect entries_barrier_10.io.x.hw, _entries_WIRE_20.hw connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw connect entries_barrier_10.io.x.gf, _entries_WIRE_20.gf connect entries_barrier_10.io.x.pf, _entries_WIRE_20.pf connect entries_barrier_10.io.x.ae_stage2, _entries_WIRE_20.ae_stage2 connect entries_barrier_10.io.x.ae_final, _entries_WIRE_20.ae_final connect entries_barrier_10.io.x.ae_ptw, _entries_WIRE_20.ae_ptw connect entries_barrier_10.io.x.g, _entries_WIRE_20.g connect entries_barrier_10.io.x.u, _entries_WIRE_20.u connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_23 : UInt<42> connect _entries_WIRE_23, superpage_entries[3].data[0] node _entries_T_261 = bits(_entries_WIRE_23, 0, 0) connect _entries_WIRE_22.fragmented_superpage, _entries_T_261 node _entries_T_262 = bits(_entries_WIRE_23, 1, 1) connect _entries_WIRE_22.c, _entries_T_262 node _entries_T_263 = bits(_entries_WIRE_23, 2, 2) connect _entries_WIRE_22.eff, _entries_T_263 node _entries_T_264 = bits(_entries_WIRE_23, 3, 3) connect _entries_WIRE_22.paa, _entries_T_264 node _entries_T_265 = bits(_entries_WIRE_23, 4, 4) connect _entries_WIRE_22.pal, _entries_T_265 node _entries_T_266 = bits(_entries_WIRE_23, 5, 5) connect _entries_WIRE_22.ppp, _entries_T_266 node _entries_T_267 = bits(_entries_WIRE_23, 6, 6) connect _entries_WIRE_22.pr, _entries_T_267 node _entries_T_268 = bits(_entries_WIRE_23, 7, 7) connect _entries_WIRE_22.px, _entries_T_268 node _entries_T_269 = bits(_entries_WIRE_23, 8, 8) connect _entries_WIRE_22.pw, _entries_T_269 node _entries_T_270 = bits(_entries_WIRE_23, 9, 9) connect _entries_WIRE_22.hr, _entries_T_270 node _entries_T_271 = bits(_entries_WIRE_23, 10, 10) connect _entries_WIRE_22.hx, _entries_T_271 node _entries_T_272 = bits(_entries_WIRE_23, 11, 11) connect _entries_WIRE_22.hw, _entries_T_272 node _entries_T_273 = bits(_entries_WIRE_23, 12, 12) connect _entries_WIRE_22.sr, _entries_T_273 node _entries_T_274 = bits(_entries_WIRE_23, 13, 13) connect _entries_WIRE_22.sx, _entries_T_274 node _entries_T_275 = bits(_entries_WIRE_23, 14, 14) connect _entries_WIRE_22.sw, _entries_T_275 node _entries_T_276 = bits(_entries_WIRE_23, 15, 15) connect _entries_WIRE_22.gf, _entries_T_276 node _entries_T_277 = bits(_entries_WIRE_23, 16, 16) connect _entries_WIRE_22.pf, _entries_T_277 node _entries_T_278 = bits(_entries_WIRE_23, 17, 17) connect _entries_WIRE_22.ae_stage2, _entries_T_278 node _entries_T_279 = bits(_entries_WIRE_23, 18, 18) connect _entries_WIRE_22.ae_final, _entries_T_279 node _entries_T_280 = bits(_entries_WIRE_23, 19, 19) connect _entries_WIRE_22.ae_ptw, _entries_T_280 node _entries_T_281 = bits(_entries_WIRE_23, 20, 20) connect _entries_WIRE_22.g, _entries_T_281 node _entries_T_282 = bits(_entries_WIRE_23, 21, 21) connect _entries_WIRE_22.u, _entries_T_282 node _entries_T_283 = bits(_entries_WIRE_23, 41, 22) connect _entries_WIRE_22.ppn, _entries_T_283 inst entries_barrier_11 of OptimizationBarrier_TLBEntryData_138 connect entries_barrier_11.clock, clock connect entries_barrier_11.reset, reset connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage connect entries_barrier_11.io.x.c, _entries_WIRE_22.c connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal connect entries_barrier_11.io.x.ppp, _entries_WIRE_22.ppp connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr connect entries_barrier_11.io.x.px, _entries_WIRE_22.px connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw connect entries_barrier_11.io.x.hr, _entries_WIRE_22.hr connect entries_barrier_11.io.x.hx, _entries_WIRE_22.hx connect entries_barrier_11.io.x.hw, _entries_WIRE_22.hw connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw connect entries_barrier_11.io.x.gf, _entries_WIRE_22.gf connect entries_barrier_11.io.x.pf, _entries_WIRE_22.pf connect entries_barrier_11.io.x.ae_stage2, _entries_WIRE_22.ae_stage2 connect entries_barrier_11.io.x.ae_final, _entries_WIRE_22.ae_final connect entries_barrier_11.io.x.ae_ptw, _entries_WIRE_22.ae_ptw connect entries_barrier_11.io.x.g, _entries_WIRE_22.g connect entries_barrier_11.io.x.u, _entries_WIRE_22.u connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_25 : UInt<42> connect _entries_WIRE_25, special_entry.data[0] node _entries_T_284 = bits(_entries_WIRE_25, 0, 0) connect _entries_WIRE_24.fragmented_superpage, _entries_T_284 node _entries_T_285 = bits(_entries_WIRE_25, 1, 1) connect _entries_WIRE_24.c, _entries_T_285 node _entries_T_286 = bits(_entries_WIRE_25, 2, 2) connect _entries_WIRE_24.eff, _entries_T_286 node _entries_T_287 = bits(_entries_WIRE_25, 3, 3) connect _entries_WIRE_24.paa, _entries_T_287 node _entries_T_288 = bits(_entries_WIRE_25, 4, 4) connect _entries_WIRE_24.pal, _entries_T_288 node _entries_T_289 = bits(_entries_WIRE_25, 5, 5) connect _entries_WIRE_24.ppp, _entries_T_289 node _entries_T_290 = bits(_entries_WIRE_25, 6, 6) connect _entries_WIRE_24.pr, _entries_T_290 node _entries_T_291 = bits(_entries_WIRE_25, 7, 7) connect _entries_WIRE_24.px, _entries_T_291 node _entries_T_292 = bits(_entries_WIRE_25, 8, 8) connect _entries_WIRE_24.pw, _entries_T_292 node _entries_T_293 = bits(_entries_WIRE_25, 9, 9) connect _entries_WIRE_24.hr, _entries_T_293 node _entries_T_294 = bits(_entries_WIRE_25, 10, 10) connect _entries_WIRE_24.hx, _entries_T_294 node _entries_T_295 = bits(_entries_WIRE_25, 11, 11) connect _entries_WIRE_24.hw, _entries_T_295 node _entries_T_296 = bits(_entries_WIRE_25, 12, 12) connect _entries_WIRE_24.sr, _entries_T_296 node _entries_T_297 = bits(_entries_WIRE_25, 13, 13) connect _entries_WIRE_24.sx, _entries_T_297 node _entries_T_298 = bits(_entries_WIRE_25, 14, 14) connect _entries_WIRE_24.sw, _entries_T_298 node _entries_T_299 = bits(_entries_WIRE_25, 15, 15) connect _entries_WIRE_24.gf, _entries_T_299 node _entries_T_300 = bits(_entries_WIRE_25, 16, 16) connect _entries_WIRE_24.pf, _entries_T_300 node _entries_T_301 = bits(_entries_WIRE_25, 17, 17) connect _entries_WIRE_24.ae_stage2, _entries_T_301 node _entries_T_302 = bits(_entries_WIRE_25, 18, 18) connect _entries_WIRE_24.ae_final, _entries_T_302 node _entries_T_303 = bits(_entries_WIRE_25, 19, 19) connect _entries_WIRE_24.ae_ptw, _entries_T_303 node _entries_T_304 = bits(_entries_WIRE_25, 20, 20) connect _entries_WIRE_24.g, _entries_T_304 node _entries_T_305 = bits(_entries_WIRE_25, 21, 21) connect _entries_WIRE_24.u, _entries_T_305 node _entries_T_306 = bits(_entries_WIRE_25, 41, 22) connect _entries_WIRE_24.ppn, _entries_T_306 inst entries_barrier_12 of OptimizationBarrier_TLBEntryData_139 connect entries_barrier_12.clock, clock connect entries_barrier_12.reset, reset connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage connect entries_barrier_12.io.x.c, _entries_WIRE_24.c connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal connect entries_barrier_12.io.x.ppp, _entries_WIRE_24.ppp connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr connect entries_barrier_12.io.x.px, _entries_WIRE_24.px connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw connect entries_barrier_12.io.x.hr, _entries_WIRE_24.hr connect entries_barrier_12.io.x.hx, _entries_WIRE_24.hx connect entries_barrier_12.io.x.hw, _entries_WIRE_24.hw connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw connect entries_barrier_12.io.x.gf, _entries_WIRE_24.gf connect entries_barrier_12.io.x.pf, _entries_WIRE_24.pf connect entries_barrier_12.io.x.ae_stage2, _entries_WIRE_24.ae_stage2 connect entries_barrier_12.io.x.ae_final, _entries_WIRE_24.ae_final connect entries_barrier_12.io.x.ae_ptw, _entries_WIRE_24.ae_ptw connect entries_barrier_12.io.x.g, _entries_WIRE_24.g connect entries_barrier_12.io.x.u, _entries_WIRE_24.u connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) node ppn_res = shr(entries_barrier_8.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, entries_barrier_8.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, entries_barrier_8.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) node ppn_res_1 = shr(entries_barrier_9.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, entries_barrier_9.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1)) node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, entries_barrier_9.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) node ppn_res_2 = shr(entries_barrier_10.io.y.ppn, 18) node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0)) node _ppn_T_17 = mux(ppn_ignore_4, vpn, UInt<1>(0h0)) node _ppn_T_18 = or(_ppn_T_17, entries_barrier_10.io.y.ppn) node _ppn_T_19 = bits(_ppn_T_18, 17, 9) node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19) node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1)) node _ppn_T_21 = mux(ppn_ignore_5, vpn, UInt<1>(0h0)) node _ppn_T_22 = or(_ppn_T_21, entries_barrier_10.io.y.ppn) node _ppn_T_23 = bits(_ppn_T_22, 8, 0) node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23) node ppn_res_3 = shr(entries_barrier_11.io.y.ppn, 18) node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0)) node _ppn_T_25 = mux(ppn_ignore_6, vpn, UInt<1>(0h0)) node _ppn_T_26 = or(_ppn_T_25, entries_barrier_11.io.y.ppn) node _ppn_T_27 = bits(_ppn_T_26, 17, 9) node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27) node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1)) node _ppn_T_29 = mux(ppn_ignore_7, vpn, UInt<1>(0h0)) node _ppn_T_30 = or(_ppn_T_29, entries_barrier_11.io.y.ppn) node _ppn_T_31 = bits(_ppn_T_30, 8, 0) node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31) node ppn_res_4 = shr(entries_barrier_12.io.y.ppn, 18) node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0)) node _ppn_T_33 = mux(ppn_ignore_8, vpn, UInt<1>(0h0)) node _ppn_T_34 = or(_ppn_T_33, entries_barrier_12.io.y.ppn) node _ppn_T_35 = bits(_ppn_T_34, 17, 9) node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35) node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0)) node _ppn_T_37 = mux(ppn_ignore_9, vpn, UInt<1>(0h0)) node _ppn_T_38 = or(_ppn_T_37, entries_barrier_12.io.y.ppn) node _ppn_T_39 = bits(_ppn_T_38, 8, 0) node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39) node _ppn_T_41 = bits(vpn, 19, 0) node _ppn_T_42 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_43 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_44 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_45 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_46 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0)) node _ppn_T_47 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0)) node _ppn_T_48 = mux(hitsVec_6, entries_barrier_6.io.y.ppn, UInt<1>(0h0)) node _ppn_T_49 = mux(hitsVec_7, entries_barrier_7.io.y.ppn, UInt<1>(0h0)) node _ppn_T_50 = mux(hitsVec_8, _ppn_T_8, UInt<1>(0h0)) node _ppn_T_51 = mux(hitsVec_9, _ppn_T_16, UInt<1>(0h0)) node _ppn_T_52 = mux(hitsVec_10, _ppn_T_24, UInt<1>(0h0)) node _ppn_T_53 = mux(hitsVec_11, _ppn_T_32, UInt<1>(0h0)) node _ppn_T_54 = mux(hitsVec_12, _ppn_T_40, UInt<1>(0h0)) node _ppn_T_55 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0)) node _ppn_T_56 = or(_ppn_T_42, _ppn_T_43) node _ppn_T_57 = or(_ppn_T_56, _ppn_T_44) node _ppn_T_58 = or(_ppn_T_57, _ppn_T_45) node _ppn_T_59 = or(_ppn_T_58, _ppn_T_46) node _ppn_T_60 = or(_ppn_T_59, _ppn_T_47) node _ppn_T_61 = or(_ppn_T_60, _ppn_T_48) node _ppn_T_62 = or(_ppn_T_61, _ppn_T_49) node _ppn_T_63 = or(_ppn_T_62, _ppn_T_50) node _ppn_T_64 = or(_ppn_T_63, _ppn_T_51) node _ppn_T_65 = or(_ppn_T_64, _ppn_T_52) node _ppn_T_66 = or(_ppn_T_65, _ppn_T_53) node _ppn_T_67 = or(_ppn_T_66, _ppn_T_54) node _ppn_T_68 = or(_ppn_T_67, _ppn_T_55) wire ppn : UInt<20> connect ppn, _ppn_T_68 node ptw_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries_barrier.io.y.ae_ptw) node ptw_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_ptw) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo) node ptw_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_ptw, entries_barrier_7.io.y.ae_ptw) node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_ptw) node ptw_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_ptw, entries_barrier_9.io.y.ae_ptw) node ptw_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_ptw, entries_barrier_11.io.y.ae_ptw) node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) node final_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) node final_ae_array_lo_lo = cat(final_ae_array_lo_lo_hi, entries_barrier.io.y.ae_final) node final_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) node final_ae_array_lo_hi = cat(final_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_final) node final_ae_array_lo = cat(final_ae_array_lo_hi, final_ae_array_lo_lo) node final_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_final, entries_barrier_7.io.y.ae_final) node final_ae_array_hi_lo = cat(final_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_final) node final_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_final, entries_barrier_9.io.y.ae_final) node final_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_final, entries_barrier_11.io.y.ae_final) node final_ae_array_hi_hi = cat(final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo) node final_ae_array_hi = cat(final_ae_array_hi_hi, final_ae_array_hi_lo) node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) node ptw_pf_array_lo_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) node ptw_pf_array_lo_lo = cat(ptw_pf_array_lo_lo_hi, entries_barrier.io.y.pf) node ptw_pf_array_lo_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) node ptw_pf_array_lo_hi = cat(ptw_pf_array_lo_hi_hi, entries_barrier_3.io.y.pf) node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, ptw_pf_array_lo_lo) node ptw_pf_array_hi_lo_hi = cat(entries_barrier_8.io.y.pf, entries_barrier_7.io.y.pf) node ptw_pf_array_hi_lo = cat(ptw_pf_array_hi_lo_hi, entries_barrier_6.io.y.pf) node ptw_pf_array_hi_hi_lo = cat(entries_barrier_10.io.y.pf, entries_barrier_9.io.y.pf) node ptw_pf_array_hi_hi_hi = cat(entries_barrier_12.io.y.pf, entries_barrier_11.io.y.pf) node ptw_pf_array_hi_hi = cat(ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo) node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, ptw_pf_array_hi_lo) node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) node ptw_gf_array_lo_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) node ptw_gf_array_lo_lo = cat(ptw_gf_array_lo_lo_hi, entries_barrier.io.y.gf) node ptw_gf_array_lo_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) node ptw_gf_array_lo_hi = cat(ptw_gf_array_lo_hi_hi, entries_barrier_3.io.y.gf) node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, ptw_gf_array_lo_lo) node ptw_gf_array_hi_lo_hi = cat(entries_barrier_8.io.y.gf, entries_barrier_7.io.y.gf) node ptw_gf_array_hi_lo = cat(ptw_gf_array_hi_lo_hi, entries_barrier_6.io.y.gf) node ptw_gf_array_hi_hi_lo = cat(entries_barrier_10.io.y.gf, entries_barrier_9.io.y.gf) node ptw_gf_array_hi_hi_hi = cat(entries_barrier_12.io.y.gf, entries_barrier_11.io.y.gf) node ptw_gf_array_hi_hi = cat(ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo) node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, ptw_gf_array_hi_lo) node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) node priv_rw_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo) node priv_rw_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1) node priv_rw_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) node priv_x_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo) node priv_x_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1) node priv_x_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<13>(0h1fff), UInt<13>(0h0)) node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<13>(0h1fff), UInt<13>(0h0)) node stage1_bypass_lo_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) node stage1_bypass_lo_lo = cat(stage1_bypass_lo_lo_hi, entries_barrier.io.y.ae_stage2) node stage1_bypass_lo_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) node stage1_bypass_lo_hi = cat(stage1_bypass_lo_hi_hi, entries_barrier_3.io.y.ae_stage2) node stage1_bypass_lo = cat(stage1_bypass_lo_hi, stage1_bypass_lo_lo) node stage1_bypass_hi_lo_hi = cat(entries_barrier_8.io.y.ae_stage2, entries_barrier_7.io.y.ae_stage2) node stage1_bypass_hi_lo = cat(stage1_bypass_hi_lo_hi, entries_barrier_6.io.y.ae_stage2) node stage1_bypass_hi_hi_lo = cat(entries_barrier_10.io.y.ae_stage2, entries_barrier_9.io.y.ae_stage2) node stage1_bypass_hi_hi_hi = cat(entries_barrier_12.io.y.ae_stage2, entries_barrier_11.io.y.ae_stage2) node stage1_bypass_hi_hi = cat(stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo) node stage1_bypass_hi = cat(stage1_bypass_hi_hi, stage1_bypass_hi_lo) node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) node mxr = or(io.ptw.status.mxr, _mxr_T) node r_array_lo_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) node r_array_lo_lo = cat(r_array_lo_lo_hi, entries_barrier.io.y.sr) node r_array_lo_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) node r_array_lo_hi = cat(r_array_lo_hi_hi, entries_barrier_3.io.y.sr) node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo) node r_array_hi_lo_hi = cat(entries_barrier_8.io.y.sr, entries_barrier_7.io.y.sr) node r_array_hi_lo = cat(r_array_hi_lo_hi, entries_barrier_6.io.y.sr) node r_array_hi_hi_lo = cat(entries_barrier_10.io.y.sr, entries_barrier_9.io.y.sr) node r_array_hi_hi_hi = cat(entries_barrier_12.io.y.sr, entries_barrier_11.io.y.sr) node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo) node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries_barrier.io.y.sx) node r_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries_barrier_3.io.y.sx) node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1) node r_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries_barrier_6.io.y.sx) node r_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node r_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1) node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) node r_array = cat(UInt<1>(0h1), _r_array_T_5) node w_array_lo_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) node w_array_lo_lo = cat(w_array_lo_lo_hi, entries_barrier.io.y.sw) node w_array_lo_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) node w_array_lo_hi = cat(w_array_lo_hi_hi, entries_barrier_3.io.y.sw) node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo) node w_array_hi_lo_hi = cat(entries_barrier_8.io.y.sw, entries_barrier_7.io.y.sw) node w_array_hi_lo = cat(w_array_hi_lo_hi, entries_barrier_6.io.y.sw) node w_array_hi_hi_lo = cat(entries_barrier_10.io.y.sw, entries_barrier_9.io.y.sw) node w_array_hi_hi_hi = cat(entries_barrier_12.io.y.sw, entries_barrier_11.io.y.sw) node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo) node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok, _w_array_T) node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) node w_array = cat(UInt<1>(0h1), _w_array_T_2) node x_array_lo_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node x_array_lo_lo = cat(x_array_lo_lo_hi, entries_barrier.io.y.sx) node x_array_lo_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node x_array_lo_hi = cat(x_array_lo_hi_hi, entries_barrier_3.io.y.sx) node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo) node x_array_hi_lo_hi = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node x_array_hi_lo = cat(x_array_hi_lo_hi, entries_barrier_6.io.y.sx) node x_array_hi_hi_lo = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node x_array_hi_hi_hi = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo) node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok, _x_array_T) node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) node x_array = cat(UInt<1>(0h1), _x_array_T_2) node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) node stage2_bypass = mux(_stage2_bypass_T, UInt<13>(0h1fff), UInt<13>(0h0)) node hr_array_lo_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) node hr_array_lo_lo = cat(hr_array_lo_lo_hi, entries_barrier.io.y.hr) node hr_array_lo_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) node hr_array_lo_hi = cat(hr_array_lo_hi_hi, entries_barrier_3.io.y.hr) node hr_array_lo = cat(hr_array_lo_hi, hr_array_lo_lo) node hr_array_hi_lo_hi = cat(entries_barrier_8.io.y.hr, entries_barrier_7.io.y.hr) node hr_array_hi_lo = cat(hr_array_hi_lo_hi, entries_barrier_6.io.y.hr) node hr_array_hi_hi_lo = cat(entries_barrier_10.io.y.hr, entries_barrier_9.io.y.hr) node hr_array_hi_hi_hi = cat(entries_barrier_12.io.y.hr, entries_barrier_11.io.y.hr) node hr_array_hi_hi = cat(hr_array_hi_hi_hi, hr_array_hi_hi_lo) node hr_array_hi = cat(hr_array_hi_hi, hr_array_hi_lo) node _hr_array_T = cat(hr_array_hi, hr_array_lo) node hr_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hr_array_lo_lo_1 = cat(hr_array_lo_lo_hi_1, entries_barrier.io.y.hx) node hr_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hr_array_lo_hi_1 = cat(hr_array_lo_hi_hi_1, entries_barrier_3.io.y.hx) node hr_array_lo_1 = cat(hr_array_lo_hi_1, hr_array_lo_lo_1) node hr_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hr_array_hi_lo_1 = cat(hr_array_hi_lo_hi_1, entries_barrier_6.io.y.hx) node hr_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hr_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hr_array_hi_hi_1 = cat(hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1) node hr_array_hi_1 = cat(hr_array_hi_hi_1, hr_array_hi_lo_1) node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) node hw_array_lo_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) node hw_array_lo_lo = cat(hw_array_lo_lo_hi, entries_barrier.io.y.hw) node hw_array_lo_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) node hw_array_lo_hi = cat(hw_array_lo_hi_hi, entries_barrier_3.io.y.hw) node hw_array_lo = cat(hw_array_lo_hi, hw_array_lo_lo) node hw_array_hi_lo_hi = cat(entries_barrier_8.io.y.hw, entries_barrier_7.io.y.hw) node hw_array_hi_lo = cat(hw_array_hi_lo_hi, entries_barrier_6.io.y.hw) node hw_array_hi_hi_lo = cat(entries_barrier_10.io.y.hw, entries_barrier_9.io.y.hw) node hw_array_hi_hi_hi = cat(entries_barrier_12.io.y.hw, entries_barrier_11.io.y.hw) node hw_array_hi_hi = cat(hw_array_hi_hi_hi, hw_array_hi_hi_lo) node hw_array_hi = cat(hw_array_hi_hi, hw_array_hi_lo) node _hw_array_T = cat(hw_array_hi, hw_array_lo) node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) node hx_array_lo_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hx_array_lo_lo = cat(hx_array_lo_lo_hi, entries_barrier.io.y.hx) node hx_array_lo_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hx_array_lo_hi = cat(hx_array_lo_hi_hi, entries_barrier_3.io.y.hx) node hx_array_lo = cat(hx_array_lo_hi, hx_array_lo_lo) node hx_array_hi_lo_hi = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hx_array_hi_lo = cat(hx_array_hi_lo_hi, entries_barrier_6.io.y.hx) node hx_array_hi_hi_lo = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hx_array_hi_hi_hi = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hx_array_hi_hi = cat(hx_array_hi_hi_hi, hx_array_hi_hi_lo) node hx_array_hi = cat(hx_array_hi_hi, hx_array_hi_lo) node _hx_array_T = cat(hx_array_hi, hx_array_lo) node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo_lo_hi = cat(entries_barrier_2.io.y.pr, entries_barrier_1.io.y.pr) node pr_array_lo_lo = cat(pr_array_lo_lo_hi, entries_barrier.io.y.pr) node pr_array_lo_hi_hi = cat(entries_barrier_5.io.y.pr, entries_barrier_4.io.y.pr) node pr_array_lo_hi = cat(pr_array_lo_hi_hi, entries_barrier_3.io.y.pr) node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo) node pr_array_hi_lo_hi = cat(entries_barrier_8.io.y.pr, entries_barrier_7.io.y.pr) node pr_array_hi_lo = cat(pr_array_hi_lo_hi, entries_barrier_6.io.y.pr) node pr_array_hi_hi_hi = cat(entries_barrier_11.io.y.pr, entries_barrier_10.io.y.pr) node pr_array_hi_hi = cat(pr_array_hi_hi_hi, entries_barrier_9.io.y.pr) node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) node _pr_array_T_4 = not(_pr_array_T_3) node pr_array = and(_pr_array_T_2, _pr_array_T_4) node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo_lo_hi = cat(entries_barrier_2.io.y.pw, entries_barrier_1.io.y.pw) node pw_array_lo_lo = cat(pw_array_lo_lo_hi, entries_barrier.io.y.pw) node pw_array_lo_hi_hi = cat(entries_barrier_5.io.y.pw, entries_barrier_4.io.y.pw) node pw_array_lo_hi = cat(pw_array_lo_hi_hi, entries_barrier_3.io.y.pw) node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo) node pw_array_hi_lo_hi = cat(entries_barrier_8.io.y.pw, entries_barrier_7.io.y.pw) node pw_array_hi_lo = cat(pw_array_hi_lo_hi, entries_barrier_6.io.y.pw) node pw_array_hi_hi_hi = cat(entries_barrier_11.io.y.pw, entries_barrier_10.io.y.pw) node pw_array_hi_hi = cat(pw_array_hi_hi_hi, entries_barrier_9.io.y.pw) node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) node _pw_array_T_4 = not(_pw_array_T_3) node pw_array = and(_pw_array_T_2, _pw_array_T_4) node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo_lo_hi = cat(entries_barrier_2.io.y.px, entries_barrier_1.io.y.px) node px_array_lo_lo = cat(px_array_lo_lo_hi, entries_barrier.io.y.px) node px_array_lo_hi_hi = cat(entries_barrier_5.io.y.px, entries_barrier_4.io.y.px) node px_array_lo_hi = cat(px_array_lo_hi_hi, entries_barrier_3.io.y.px) node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo) node px_array_hi_lo_hi = cat(entries_barrier_8.io.y.px, entries_barrier_7.io.y.px) node px_array_hi_lo = cat(px_array_hi_lo_hi, entries_barrier_6.io.y.px) node px_array_hi_hi_hi = cat(entries_barrier_11.io.y.px, entries_barrier_10.io.y.px) node px_array_hi_hi = cat(px_array_hi_hi_hi, entries_barrier_9.io.y.px) node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = or(ptw_ae_array, final_ae_array) node _px_array_T_4 = not(_px_array_T_3) node px_array = and(_px_array_T_2, _px_array_T_4) node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo_lo_hi = cat(entries_barrier_2.io.y.eff, entries_barrier_1.io.y.eff) node eff_array_lo_lo = cat(eff_array_lo_lo_hi, entries_barrier.io.y.eff) node eff_array_lo_hi_hi = cat(entries_barrier_5.io.y.eff, entries_barrier_4.io.y.eff) node eff_array_lo_hi = cat(eff_array_lo_hi_hi, entries_barrier_3.io.y.eff) node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo) node eff_array_hi_lo_hi = cat(entries_barrier_8.io.y.eff, entries_barrier_7.io.y.eff) node eff_array_hi_lo = cat(eff_array_hi_lo_hi, entries_barrier_6.io.y.eff) node eff_array_hi_hi_hi = cat(entries_barrier_11.io.y.eff, entries_barrier_10.io.y.eff) node eff_array_hi_hi = cat(eff_array_hi_hi_hi, entries_barrier_9.io.y.eff) node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node eff_array = cat(_eff_array_T, _eff_array_T_1) node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node c_array_lo_lo = cat(c_array_lo_lo_hi, entries_barrier.io.y.c) node c_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node c_array_lo_hi = cat(c_array_lo_hi_hi, entries_barrier_3.io.y.c) node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo) node c_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node c_array_hi_lo = cat(c_array_hi_lo_hi, entries_barrier_6.io.y.c) node c_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node c_array_hi_hi = cat(c_array_hi_hi_hi, entries_barrier_9.io.y.c) node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node c_array = cat(_c_array_T, _c_array_T_1) node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) node ppp_array_lo_lo_hi = cat(entries_barrier_2.io.y.ppp, entries_barrier_1.io.y.ppp) node ppp_array_lo_lo = cat(ppp_array_lo_lo_hi, entries_barrier.io.y.ppp) node ppp_array_lo_hi_hi = cat(entries_barrier_5.io.y.ppp, entries_barrier_4.io.y.ppp) node ppp_array_lo_hi = cat(ppp_array_lo_hi_hi, entries_barrier_3.io.y.ppp) node ppp_array_lo = cat(ppp_array_lo_hi, ppp_array_lo_lo) node ppp_array_hi_lo_hi = cat(entries_barrier_8.io.y.ppp, entries_barrier_7.io.y.ppp) node ppp_array_hi_lo = cat(ppp_array_hi_lo_hi, entries_barrier_6.io.y.ppp) node ppp_array_hi_hi_hi = cat(entries_barrier_11.io.y.ppp, entries_barrier_10.io.y.ppp) node ppp_array_hi_hi = cat(ppp_array_hi_hi_hi, entries_barrier_9.io.y.ppp) node ppp_array_hi = cat(ppp_array_hi_hi, ppp_array_hi_lo) node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo_lo_hi = cat(entries_barrier_2.io.y.paa, entries_barrier_1.io.y.paa) node paa_array_lo_lo = cat(paa_array_lo_lo_hi, entries_barrier.io.y.paa) node paa_array_lo_hi_hi = cat(entries_barrier_5.io.y.paa, entries_barrier_4.io.y.paa) node paa_array_lo_hi = cat(paa_array_lo_hi_hi, entries_barrier_3.io.y.paa) node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo) node paa_array_hi_lo_hi = cat(entries_barrier_8.io.y.paa, entries_barrier_7.io.y.paa) node paa_array_hi_lo = cat(paa_array_hi_lo_hi, entries_barrier_6.io.y.paa) node paa_array_hi_hi_hi = cat(entries_barrier_11.io.y.paa, entries_barrier_10.io.y.paa) node paa_array_hi_hi = cat(paa_array_hi_hi_hi, entries_barrier_9.io.y.paa) node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node paa_array = cat(_paa_array_T, _paa_array_T_1) node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo_lo_hi = cat(entries_barrier_2.io.y.pal, entries_barrier_1.io.y.pal) node pal_array_lo_lo = cat(pal_array_lo_lo_hi, entries_barrier.io.y.pal) node pal_array_lo_hi_hi = cat(entries_barrier_5.io.y.pal, entries_barrier_4.io.y.pal) node pal_array_lo_hi = cat(pal_array_lo_hi_hi, entries_barrier_3.io.y.pal) node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo) node pal_array_hi_lo_hi = cat(entries_barrier_8.io.y.pal, entries_barrier_7.io.y.pal) node pal_array_hi_lo = cat(pal_array_hi_lo_hi, entries_barrier_6.io.y.pal) node pal_array_hi_hi_hi = cat(entries_barrier_11.io.y.pal, entries_barrier_10.io.y.pal) node pal_array_hi_hi = cat(pal_array_hi_hi_hi, entries_barrier_9.io.y.pal) node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node pal_array = cat(_pal_array_T, _pal_array_T_1) node ppp_array_if_cached = or(ppp_array, c_array) node paa_array_if_cached = or(paa_array, UInt<1>(0h0)) node pal_array_if_cached = or(pal_array, UInt<1>(0h0)) node _prefetchable_array_T = and(cacheable, homogeneous) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, entries_barrier.io.y.c) node prefetchable_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, entries_barrier_3.io.y.c) node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo) node prefetchable_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, entries_barrier_6.io.y.c) node prefetchable_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, entries_barrier_9.io.y.c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) node misaligned = orr(_misaligned_T_3) node _bad_va_T = and(vm_enabled, stage1_en) node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3) node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4) node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0)) node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6) node bad_va = and(_bad_va_T, _bad_va_T_7) node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node cmd_lrsc = and(UInt<1>(0h0), _cmd_lrsc_T_2) node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node cmd_amo_logical = and(UInt<1>(0h0), _cmd_amo_logical_T_6) node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node cmd_amo_arithmetic = and(UInt<1>(0h0), _cmd_amo_arithmetic_T_8) node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array) node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed) node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) node ae_array = or(_ae_array_T, _ae_array_T_2) node _ae_ld_array_T = not(pr_array) node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T) node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0)) node _ae_st_array_T = not(pw_array) node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(ppp_array_if_cached) node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(pal_array_if_cached) node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) node _ae_st_array_T_9 = not(paa_array_if_cached) node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) node _must_alloc_array_T = not(ppp_array) node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array) node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(paa_array) node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) node _must_alloc_array_T_8 = not(UInt<14>(0h0)) node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = not(ptw_ae_array) node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) node _pf_ld_array_T_5 = not(ptw_gf_array) node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) node _pf_st_array_T = not(w_array) node _pf_st_array_T_1 = not(ptw_ae_array) node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) node _pf_st_array_T_4 = not(ptw_gf_array) node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) node _pf_inst_array_T = not(x_array) node _pf_inst_array_T_1 = not(ptw_ae_array) node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) node _pf_inst_array_T_4 = not(ptw_gf_array) node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) node _gf_ld_array_T = and(priv_v, cmd_read) node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array) node _gf_ld_array_T_4 = not(ptw_ae_array) node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4) node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) node _gf_st_array_T = and(priv_v, cmd_write_perms) node _gf_st_array_T_1 = not(hw_array) node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array) node _gf_st_array_T_3 = not(ptw_ae_array) node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3) node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) node _gf_inst_array_T = not(hx_array) node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array) node _gf_inst_array_T_2 = not(ptw_ae_array) node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2) node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) node gpa_hits_need_gpa_mask = or(gf_ld_array, gf_st_array) node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<12>(0hfff), UInt<12>(0h0)) node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<13>(0h1fff), UInt<13>(0h0)) node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) node _gpa_hits_T = bits(gpa_hits_need_gpa_mask, 12, 0) node _gpa_hits_T_1 = not(_gpa_hits_T) node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) node tlb_hit_if_not_gpa_miss = orr(real_hits) node _tlb_hit_T = and(real_hits, gpa_hits) node tlb_hit = orr(_tlb_hit_T) node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0) wire _state_vec_WIRE : UInt<7>[1] connect _state_vec_WIRE[0], UInt<7>(0h0) regreset state_vec : UInt<7>[1], clock, reset, _state_vec_WIRE regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _T_23 = and(io.req.valid, vm_enabled) when _T_23 : node _T_24 = or(sector_hits_0, sector_hits_1) node _T_25 = or(_T_24, sector_hits_2) node _T_26 = or(_T_25, sector_hits_3) node _T_27 = or(_T_26, sector_hits_4) node _T_28 = or(_T_27, sector_hits_5) node _T_29 = or(_T_28, sector_hits_6) node _T_30 = or(_T_29, sector_hits_7) when _T_30 : node lo_lo = cat(sector_hits_1, sector_hits_0) node lo_hi = cat(sector_hits_3, sector_hits_2) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(sector_hits_5, sector_hits_4) node hi_hi = cat(sector_hits_7, sector_hits_6) node hi = cat(hi_hi, hi_lo) node _T_31 = cat(hi, lo) node hi_1 = bits(_T_31, 7, 4) node lo_1 = bits(_T_31, 3, 0) node _T_32 = orr(hi_1) node _T_33 = or(hi_1, lo_1) node hi_2 = bits(_T_33, 3, 2) node lo_2 = bits(_T_33, 1, 0) node _T_34 = orr(hi_2) node _T_35 = or(hi_2, lo_2) node _T_36 = bits(_T_35, 1, 1) node _T_37 = cat(_T_34, _T_36) node _T_38 = cat(_T_32, _T_37) node state_vec_0_touch_way_sized = bits(_T_38, 2, 0) node _state_vec_0_set_left_older_T = bits(state_vec_0_touch_way_sized, 2, 2) node state_vec_0_set_left_older = eq(_state_vec_0_set_left_older_T, UInt<1>(0h0)) node state_vec_0_left_subtree_state = bits(state_vec[0], 5, 3) node state_vec_0_right_subtree_state = bits(state_vec[0], 2, 0) node _state_vec_0_T = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_1 = bits(_state_vec_0_T, 1, 1) node state_vec_0_set_left_older_1 = eq(_state_vec_0_set_left_older_T_1, UInt<1>(0h0)) node state_vec_0_left_subtree_state_1 = bits(state_vec_0_left_subtree_state, 1, 1) node state_vec_0_right_subtree_state_1 = bits(state_vec_0_left_subtree_state, 0, 0) node _state_vec_0_T_1 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_2 = bits(_state_vec_0_T_1, 0, 0) node _state_vec_0_T_3 = eq(_state_vec_0_T_2, UInt<1>(0h0)) node _state_vec_0_T_4 = mux(state_vec_0_set_left_older_1, state_vec_0_left_subtree_state_1, _state_vec_0_T_3) node _state_vec_0_T_5 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_6 = bits(_state_vec_0_T_5, 0, 0) node _state_vec_0_T_7 = eq(_state_vec_0_T_6, UInt<1>(0h0)) node _state_vec_0_T_8 = mux(state_vec_0_set_left_older_1, _state_vec_0_T_7, state_vec_0_right_subtree_state_1) node state_vec_0_hi = cat(state_vec_0_set_left_older_1, _state_vec_0_T_4) node _state_vec_0_T_9 = cat(state_vec_0_hi, _state_vec_0_T_8) node _state_vec_0_T_10 = mux(state_vec_0_set_left_older, state_vec_0_left_subtree_state, _state_vec_0_T_9) node _state_vec_0_T_11 = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_2 = bits(_state_vec_0_T_11, 1, 1) node state_vec_0_set_left_older_2 = eq(_state_vec_0_set_left_older_T_2, UInt<1>(0h0)) node state_vec_0_left_subtree_state_2 = bits(state_vec_0_right_subtree_state, 1, 1) node state_vec_0_right_subtree_state_2 = bits(state_vec_0_right_subtree_state, 0, 0) node _state_vec_0_T_12 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_13 = bits(_state_vec_0_T_12, 0, 0) node _state_vec_0_T_14 = eq(_state_vec_0_T_13, UInt<1>(0h0)) node _state_vec_0_T_15 = mux(state_vec_0_set_left_older_2, state_vec_0_left_subtree_state_2, _state_vec_0_T_14) node _state_vec_0_T_16 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_17 = bits(_state_vec_0_T_16, 0, 0) node _state_vec_0_T_18 = eq(_state_vec_0_T_17, UInt<1>(0h0)) node _state_vec_0_T_19 = mux(state_vec_0_set_left_older_2, _state_vec_0_T_18, state_vec_0_right_subtree_state_2) node state_vec_0_hi_1 = cat(state_vec_0_set_left_older_2, _state_vec_0_T_15) node _state_vec_0_T_20 = cat(state_vec_0_hi_1, _state_vec_0_T_19) node _state_vec_0_T_21 = mux(state_vec_0_set_left_older, _state_vec_0_T_20, state_vec_0_right_subtree_state) node state_vec_0_hi_2 = cat(state_vec_0_set_left_older, _state_vec_0_T_10) node _state_vec_0_T_22 = cat(state_vec_0_hi_2, _state_vec_0_T_21) connect state_vec[0], _state_vec_0_T_22 node _T_39 = or(superpage_hits_0, superpage_hits_1) node _T_40 = or(_T_39, superpage_hits_2) node _T_41 = or(_T_40, superpage_hits_3) when _T_41 : node lo_3 = cat(superpage_hits_1, superpage_hits_0) node hi_3 = cat(superpage_hits_3, superpage_hits_2) node _T_42 = cat(hi_3, lo_3) node hi_4 = bits(_T_42, 3, 2) node lo_4 = bits(_T_42, 1, 0) node _T_43 = orr(hi_4) node _T_44 = or(hi_4, lo_4) node _T_45 = bits(_T_44, 1, 1) node _T_46 = cat(_T_43, _T_45) node state_reg_touch_way_sized = bits(_T_46, 1, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg_1, 1, 1) node state_reg_right_subtree_state = bits(state_reg_1, 0, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_1 = bits(_state_reg_T, 0, 0) node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0)) node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2) node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0) node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0)) node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state) node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3) node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7) connect state_reg_1, _state_reg_T_8 node _multipleHits_T = bits(real_hits, 5, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0) node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0) node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1) node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0) node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9) node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3) node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0) node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1) node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0) node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18) node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20) node _multipleHits_T_21 = bits(real_hits, 12, 6) node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0) node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0) node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0) node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1) node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0) node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0) node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1) node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0) node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5) node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5) node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28) node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6) node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3) node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6) node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30) node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3) node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0) node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0) node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0) node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1) node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0) node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7) node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7) node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36) node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2) node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0) node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0) node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1) node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0) node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8) node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8) node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41) node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9) node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4) node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9) node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43) node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10) node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5) node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10) node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45) node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11) node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6) node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11) node multipleHits = or(_multipleHits_T_47, _multipleHits_T_48) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_resp_pf_ld_T = and(bad_va, cmd_read) node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) connect io.resp.pf.ld, _io_resp_pf_ld_T_3 node _io_resp_pf_st_T = and(bad_va, cmd_write_perms) node _io_resp_pf_st_T_1 = and(pf_st_array, hits) node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) connect io.resp.pf.st, _io_resp_pf_st_T_3 node _io_resp_pf_inst_T = and(pf_inst_array, hits) node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1) connect io.resp.pf.inst, _io_resp_pf_inst_T_2 node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) connect io.resp.gf.ld, _io_resp_gf_ld_T_3 node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) node _io_resp_gf_st_T_1 = and(gf_st_array, hits) node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) connect io.resp.gf.st, _io_resp_gf_st_T_3 node _io_resp_gf_inst_T = and(gf_inst_array, hits) node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) connect io.resp.gf.inst, _io_resp_gf_inst_T_2 node _io_resp_ae_ld_T = and(ae_ld_array, hits) node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) connect io.resp.ae.ld, _io_resp_ae_ld_T_1 node _io_resp_ae_st_T = and(ae_st_array, hits) node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) connect io.resp.ae.st, _io_resp_ae_st_T_1 node _io_resp_ae_inst_T = not(px_array) node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) connect io.resp.ae.inst, _io_resp_ae_inst_T_2 node _io_resp_ma_ld_T = and(misaligned, cmd_read) connect io.resp.ma.ld, _io_resp_ma_ld_T node _io_resp_ma_st_T = and(misaligned, cmd_write) connect io.resp.ma.st, _io_resp_ma_st_T connect io.resp.ma.inst, UInt<1>(0h0) node _io_resp_cacheable_T = and(c_array, hits) node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) connect io.resp.cacheable, _io_resp_cacheable_T_1 node _io_resp_must_alloc_T = and(must_alloc_array, hits) node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) connect io.resp.must_alloc, _io_resp_must_alloc_T_1 node _io_resp_prefetchable_T = and(prefetchable_array, hits) node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) connect io.resp.prefetchable, _io_resp_prefetchable_T_2 node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) connect io.resp.miss, _io_resp_miss_T_2 node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) connect io.resp.paddr, _io_resp_paddr_T_1 connect io.resp.size, io.req.bits.size connect io.resp.cmd, io.req.bits.cmd node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) connect io.resp.gpa, _io_resp_gpa_T node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag connect io.ptw.req.bits.bits.vstage1, r_vstage1_en connect io.ptw.req.bits.bits.stage2, r_stage2_en connect io.ptw.req.bits.bits.need_gpa, r_need_gpa node _T_47 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_48 = and(_T_47, io.ptw.req.bits.valid) when _T_48 : connect r_gpa_valid, UInt<1>(0h0) connect r_gpa_vpn, r_refill_tag node _T_49 = and(io.req.ready, io.req.valid) node _T_50 = and(_T_49, tlb_miss) when _T_50 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn connect r_need_gpa, tlb_hit_if_not_gpa_miss connect r_vstage1_en, vstage1_en connect r_stage2_en, stage2_en node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2) node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1) node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0) node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0) node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0) node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1) node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2) node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0]) node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0]) node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo) node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0) node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1) node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2) node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3) node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10) node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11) node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13 node r_sectored_repl_addr_left_subtree_older = bits(state_vec[0], 6, 6) node r_sectored_repl_addr_left_subtree_state = bits(state_vec[0], 5, 3) node r_sectored_repl_addr_right_subtree_state = bits(state_vec[0], 2, 0) node r_sectored_repl_addr_left_subtree_older_1 = bits(r_sectored_repl_addr_left_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 0, 0) node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1) node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2) node r_sectored_repl_addr_left_subtree_older_2 = bits(r_sectored_repl_addr_right_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0) node _r_sectored_repl_addr_T_4 = bits(r_sectored_repl_addr_left_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_5 = bits(r_sectored_repl_addr_right_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_6 = mux(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_5) node _r_sectored_repl_addr_T_7 = cat(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6) node _r_sectored_repl_addr_T_8 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_7) node _r_sectored_repl_addr_T_9 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8) node _r_sectored_repl_addr_valids_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0][0].valid[2]) node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0][0].valid[3]) node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[0][1].valid[2]) node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[0][1].valid[3]) node _r_sectored_repl_addr_valids_T_6 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _r_sectored_repl_addr_valids_T_7 = or(_r_sectored_repl_addr_valids_T_6, sectored_entries[0][2].valid[2]) node _r_sectored_repl_addr_valids_T_8 = or(_r_sectored_repl_addr_valids_T_7, sectored_entries[0][2].valid[3]) node _r_sectored_repl_addr_valids_T_9 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _r_sectored_repl_addr_valids_T_10 = or(_r_sectored_repl_addr_valids_T_9, sectored_entries[0][3].valid[2]) node _r_sectored_repl_addr_valids_T_11 = or(_r_sectored_repl_addr_valids_T_10, sectored_entries[0][3].valid[3]) node _r_sectored_repl_addr_valids_T_12 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _r_sectored_repl_addr_valids_T_13 = or(_r_sectored_repl_addr_valids_T_12, sectored_entries[0][4].valid[2]) node _r_sectored_repl_addr_valids_T_14 = or(_r_sectored_repl_addr_valids_T_13, sectored_entries[0][4].valid[3]) node _r_sectored_repl_addr_valids_T_15 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _r_sectored_repl_addr_valids_T_16 = or(_r_sectored_repl_addr_valids_T_15, sectored_entries[0][5].valid[2]) node _r_sectored_repl_addr_valids_T_17 = or(_r_sectored_repl_addr_valids_T_16, sectored_entries[0][5].valid[3]) node _r_sectored_repl_addr_valids_T_18 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _r_sectored_repl_addr_valids_T_19 = or(_r_sectored_repl_addr_valids_T_18, sectored_entries[0][6].valid[2]) node _r_sectored_repl_addr_valids_T_20 = or(_r_sectored_repl_addr_valids_T_19, sectored_entries[0][6].valid[3]) node _r_sectored_repl_addr_valids_T_21 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _r_sectored_repl_addr_valids_T_22 = or(_r_sectored_repl_addr_valids_T_21, sectored_entries[0][7].valid[2]) node _r_sectored_repl_addr_valids_T_23 = or(_r_sectored_repl_addr_valids_T_22, sectored_entries[0][7].valid[3]) node r_sectored_repl_addr_valids_lo_lo = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2) node r_sectored_repl_addr_valids_lo_hi = cat(_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8) node r_sectored_repl_addr_valids_lo = cat(r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo) node r_sectored_repl_addr_valids_hi_lo = cat(_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14) node r_sectored_repl_addr_valids_hi_hi = cat(_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20) node r_sectored_repl_addr_valids_hi = cat(r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo) node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo) node _r_sectored_repl_addr_T_10 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_11 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_12 = bits(_r_sectored_repl_addr_T_11, 0, 0) node _r_sectored_repl_addr_T_13 = bits(_r_sectored_repl_addr_T_11, 1, 1) node _r_sectored_repl_addr_T_14 = bits(_r_sectored_repl_addr_T_11, 2, 2) node _r_sectored_repl_addr_T_15 = bits(_r_sectored_repl_addr_T_11, 3, 3) node _r_sectored_repl_addr_T_16 = bits(_r_sectored_repl_addr_T_11, 4, 4) node _r_sectored_repl_addr_T_17 = bits(_r_sectored_repl_addr_T_11, 5, 5) node _r_sectored_repl_addr_T_18 = bits(_r_sectored_repl_addr_T_11, 6, 6) node _r_sectored_repl_addr_T_19 = bits(_r_sectored_repl_addr_T_11, 7, 7) node _r_sectored_repl_addr_T_20 = mux(_r_sectored_repl_addr_T_18, UInt<3>(0h6), UInt<3>(0h7)) node _r_sectored_repl_addr_T_21 = mux(_r_sectored_repl_addr_T_17, UInt<3>(0h5), _r_sectored_repl_addr_T_20) node _r_sectored_repl_addr_T_22 = mux(_r_sectored_repl_addr_T_16, UInt<3>(0h4), _r_sectored_repl_addr_T_21) node _r_sectored_repl_addr_T_23 = mux(_r_sectored_repl_addr_T_15, UInt<2>(0h3), _r_sectored_repl_addr_T_22) node _r_sectored_repl_addr_T_24 = mux(_r_sectored_repl_addr_T_14, UInt<2>(0h2), _r_sectored_repl_addr_T_23) node _r_sectored_repl_addr_T_25 = mux(_r_sectored_repl_addr_T_13, UInt<1>(0h1), _r_sectored_repl_addr_T_24) node _r_sectored_repl_addr_T_26 = mux(_r_sectored_repl_addr_T_12, UInt<1>(0h0), _r_sectored_repl_addr_T_25) node _r_sectored_repl_addr_T_27 = mux(_r_sectored_repl_addr_T_10, _r_sectored_repl_addr_T_9, _r_sectored_repl_addr_T_26) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_27 node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1) node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2) node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3) node _r_sectored_hit_valid_T_3 = or(_r_sectored_hit_valid_T_2, sector_hits_4) node _r_sectored_hit_valid_T_4 = or(_r_sectored_hit_valid_T_3, sector_hits_5) node _r_sectored_hit_valid_T_5 = or(_r_sectored_hit_valid_T_4, sector_hits_6) node _r_sectored_hit_valid_T_6 = or(_r_sectored_hit_valid_T_5, sector_hits_7) connect r_sectored_hit.valid, _r_sectored_hit_valid_T_6 node r_sectored_hit_bits_lo_lo = cat(sector_hits_1, sector_hits_0) node r_sectored_hit_bits_lo_hi = cat(sector_hits_3, sector_hits_2) node r_sectored_hit_bits_lo = cat(r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo) node r_sectored_hit_bits_hi_lo = cat(sector_hits_5, sector_hits_4) node r_sectored_hit_bits_hi_hi = cat(sector_hits_7, sector_hits_6) node r_sectored_hit_bits_hi = cat(r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo) node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo) node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 7, 4) node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 3, 0) node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1) node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1) node r_sectored_hit_bits_hi_2 = bits(_r_sectored_hit_bits_T_2, 3, 2) node r_sectored_hit_bits_lo_2 = bits(_r_sectored_hit_bits_T_2, 1, 0) node _r_sectored_hit_bits_T_3 = orr(r_sectored_hit_bits_hi_2) node _r_sectored_hit_bits_T_4 = or(r_sectored_hit_bits_hi_2, r_sectored_hit_bits_lo_2) node _r_sectored_hit_bits_T_5 = bits(_r_sectored_hit_bits_T_4, 1, 1) node _r_sectored_hit_bits_T_6 = cat(_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5) node _r_sectored_hit_bits_T_7 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6) connect r_sectored_hit.bits, _r_sectored_hit_bits_T_7 node _r_superpage_hit_valid_T = or(superpage_hits_0, superpage_hits_1) node _r_superpage_hit_valid_T_1 = or(_r_superpage_hit_valid_T, superpage_hits_2) node _r_superpage_hit_valid_T_2 = or(_r_superpage_hit_valid_T_1, superpage_hits_3) connect r_superpage_hit.valid, _r_superpage_hit_valid_T_2 node r_superpage_hit_bits_lo = cat(superpage_hits_1, superpage_hits_0) node r_superpage_hit_bits_hi = cat(superpage_hits_3, superpage_hits_2) node _r_superpage_hit_bits_T = cat(r_superpage_hit_bits_hi, r_superpage_hit_bits_lo) node r_superpage_hit_bits_hi_1 = bits(_r_superpage_hit_bits_T, 3, 2) node r_superpage_hit_bits_lo_1 = bits(_r_superpage_hit_bits_T, 1, 0) node _r_superpage_hit_bits_T_1 = orr(r_superpage_hit_bits_hi_1) node _r_superpage_hit_bits_T_2 = or(r_superpage_hit_bits_hi_1, r_superpage_hit_bits_lo_1) node _r_superpage_hit_bits_T_3 = bits(_r_superpage_hit_bits_T_2, 1, 1) node _r_superpage_hit_bits_T_4 = cat(_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3) connect r_superpage_hit.bits, _r_superpage_hit_bits_T_4 node _T_51 = eq(state, UInt<2>(0h1)) when _T_51 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_52 = eq(state, UInt<2>(0h2)) node _T_53 = and(_T_52, io.sfence.valid) when _T_53 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_54 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_55 = shr(io.sfence.bits.addr, 12) node _T_56 = eq(_T_55, vpn) node _T_57 = or(_T_54, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf assert(clock, _T_57, UInt<1>(0h1), "") : assert node hv = and(UInt<1>(0h0), io.sfence.bits.hv) node hg = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_61 = eq(hg, UInt<1>(0h0)) node _T_62 = and(_T_61, io.sfence.bits.rs1) when _T_62 : node _T_63 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_64 = shr(_T_63, 2) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = eq(sectored_entries[0][0].tag_v, hv) node _T_67 = and(_T_65, _T_66) when _T_67 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<42> connect _WIRE_1, sectored_entries[0][0].data[0] node _T_68 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_68 node _T_69 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_69 node _T_70 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_70 node _T_71 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_71 node _T_72 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_72 node _T_73 = bits(_WIRE_1, 5, 5) connect _WIRE.ppp, _T_73 node _T_74 = bits(_WIRE_1, 6, 6) connect _WIRE.pr, _T_74 node _T_75 = bits(_WIRE_1, 7, 7) connect _WIRE.px, _T_75 node _T_76 = bits(_WIRE_1, 8, 8) connect _WIRE.pw, _T_76 node _T_77 = bits(_WIRE_1, 9, 9) connect _WIRE.hr, _T_77 node _T_78 = bits(_WIRE_1, 10, 10) connect _WIRE.hx, _T_78 node _T_79 = bits(_WIRE_1, 11, 11) connect _WIRE.hw, _T_79 node _T_80 = bits(_WIRE_1, 12, 12) connect _WIRE.sr, _T_80 node _T_81 = bits(_WIRE_1, 13, 13) connect _WIRE.sx, _T_81 node _T_82 = bits(_WIRE_1, 14, 14) connect _WIRE.sw, _T_82 node _T_83 = bits(_WIRE_1, 15, 15) connect _WIRE.gf, _T_83 node _T_84 = bits(_WIRE_1, 16, 16) connect _WIRE.pf, _T_84 node _T_85 = bits(_WIRE_1, 17, 17) connect _WIRE.ae_stage2, _T_85 node _T_86 = bits(_WIRE_1, 18, 18) connect _WIRE.ae_final, _T_86 node _T_87 = bits(_WIRE_1, 19, 19) connect _WIRE.ae_ptw, _T_87 node _T_88 = bits(_WIRE_1, 20, 20) connect _WIRE.g, _T_88 node _T_89 = bits(_WIRE_1, 21, 21) connect _WIRE.u, _T_89 node _T_90 = bits(_WIRE_1, 41, 22) connect _WIRE.ppn, _T_90 wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<42> connect _WIRE_3, sectored_entries[0][0].data[1] node _T_91 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_91 node _T_92 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_92 node _T_93 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_93 node _T_94 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_94 node _T_95 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_95 node _T_96 = bits(_WIRE_3, 5, 5) connect _WIRE_2.ppp, _T_96 node _T_97 = bits(_WIRE_3, 6, 6) connect _WIRE_2.pr, _T_97 node _T_98 = bits(_WIRE_3, 7, 7) connect _WIRE_2.px, _T_98 node _T_99 = bits(_WIRE_3, 8, 8) connect _WIRE_2.pw, _T_99 node _T_100 = bits(_WIRE_3, 9, 9) connect _WIRE_2.hr, _T_100 node _T_101 = bits(_WIRE_3, 10, 10) connect _WIRE_2.hx, _T_101 node _T_102 = bits(_WIRE_3, 11, 11) connect _WIRE_2.hw, _T_102 node _T_103 = bits(_WIRE_3, 12, 12) connect _WIRE_2.sr, _T_103 node _T_104 = bits(_WIRE_3, 13, 13) connect _WIRE_2.sx, _T_104 node _T_105 = bits(_WIRE_3, 14, 14) connect _WIRE_2.sw, _T_105 node _T_106 = bits(_WIRE_3, 15, 15) connect _WIRE_2.gf, _T_106 node _T_107 = bits(_WIRE_3, 16, 16) connect _WIRE_2.pf, _T_107 node _T_108 = bits(_WIRE_3, 17, 17) connect _WIRE_2.ae_stage2, _T_108 node _T_109 = bits(_WIRE_3, 18, 18) connect _WIRE_2.ae_final, _T_109 node _T_110 = bits(_WIRE_3, 19, 19) connect _WIRE_2.ae_ptw, _T_110 node _T_111 = bits(_WIRE_3, 20, 20) connect _WIRE_2.g, _T_111 node _T_112 = bits(_WIRE_3, 21, 21) connect _WIRE_2.u, _T_112 node _T_113 = bits(_WIRE_3, 41, 22) connect _WIRE_2.ppn, _T_113 wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<42> connect _WIRE_5, sectored_entries[0][0].data[2] node _T_114 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_114 node _T_115 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_115 node _T_116 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_116 node _T_117 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_117 node _T_118 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_118 node _T_119 = bits(_WIRE_5, 5, 5) connect _WIRE_4.ppp, _T_119 node _T_120 = bits(_WIRE_5, 6, 6) connect _WIRE_4.pr, _T_120 node _T_121 = bits(_WIRE_5, 7, 7) connect _WIRE_4.px, _T_121 node _T_122 = bits(_WIRE_5, 8, 8) connect _WIRE_4.pw, _T_122 node _T_123 = bits(_WIRE_5, 9, 9) connect _WIRE_4.hr, _T_123 node _T_124 = bits(_WIRE_5, 10, 10) connect _WIRE_4.hx, _T_124 node _T_125 = bits(_WIRE_5, 11, 11) connect _WIRE_4.hw, _T_125 node _T_126 = bits(_WIRE_5, 12, 12) connect _WIRE_4.sr, _T_126 node _T_127 = bits(_WIRE_5, 13, 13) connect _WIRE_4.sx, _T_127 node _T_128 = bits(_WIRE_5, 14, 14) connect _WIRE_4.sw, _T_128 node _T_129 = bits(_WIRE_5, 15, 15) connect _WIRE_4.gf, _T_129 node _T_130 = bits(_WIRE_5, 16, 16) connect _WIRE_4.pf, _T_130 node _T_131 = bits(_WIRE_5, 17, 17) connect _WIRE_4.ae_stage2, _T_131 node _T_132 = bits(_WIRE_5, 18, 18) connect _WIRE_4.ae_final, _T_132 node _T_133 = bits(_WIRE_5, 19, 19) connect _WIRE_4.ae_ptw, _T_133 node _T_134 = bits(_WIRE_5, 20, 20) connect _WIRE_4.g, _T_134 node _T_135 = bits(_WIRE_5, 21, 21) connect _WIRE_4.u, _T_135 node _T_136 = bits(_WIRE_5, 41, 22) connect _WIRE_4.ppn, _T_136 wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<42> connect _WIRE_7, sectored_entries[0][0].data[3] node _T_137 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_137 node _T_138 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_138 node _T_139 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_139 node _T_140 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_140 node _T_141 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_141 node _T_142 = bits(_WIRE_7, 5, 5) connect _WIRE_6.ppp, _T_142 node _T_143 = bits(_WIRE_7, 6, 6) connect _WIRE_6.pr, _T_143 node _T_144 = bits(_WIRE_7, 7, 7) connect _WIRE_6.px, _T_144 node _T_145 = bits(_WIRE_7, 8, 8) connect _WIRE_6.pw, _T_145 node _T_146 = bits(_WIRE_7, 9, 9) connect _WIRE_6.hr, _T_146 node _T_147 = bits(_WIRE_7, 10, 10) connect _WIRE_6.hx, _T_147 node _T_148 = bits(_WIRE_7, 11, 11) connect _WIRE_6.hw, _T_148 node _T_149 = bits(_WIRE_7, 12, 12) connect _WIRE_6.sr, _T_149 node _T_150 = bits(_WIRE_7, 13, 13) connect _WIRE_6.sx, _T_150 node _T_151 = bits(_WIRE_7, 14, 14) connect _WIRE_6.sw, _T_151 node _T_152 = bits(_WIRE_7, 15, 15) connect _WIRE_6.gf, _T_152 node _T_153 = bits(_WIRE_7, 16, 16) connect _WIRE_6.pf, _T_153 node _T_154 = bits(_WIRE_7, 17, 17) connect _WIRE_6.ae_stage2, _T_154 node _T_155 = bits(_WIRE_7, 18, 18) connect _WIRE_6.ae_final, _T_155 node _T_156 = bits(_WIRE_7, 19, 19) connect _WIRE_6.ae_ptw, _T_156 node _T_157 = bits(_WIRE_7, 20, 20) connect _WIRE_6.g, _T_157 node _T_158 = bits(_WIRE_7, 21, 21) connect _WIRE_6.u, _T_158 node _T_159 = bits(_WIRE_7, 41, 22) connect _WIRE_6.ppn, _T_159 node _T_160 = eq(sectored_entries[0][0].tag_v, hv) node _T_161 = bits(vpn, 1, 0) node _T_162 = eq(UInt<1>(0h0), _T_161) node _T_163 = and(_T_160, _T_162) when _T_163 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_164 = eq(sectored_entries[0][0].tag_v, hv) node _T_165 = bits(vpn, 1, 0) node _T_166 = eq(UInt<1>(0h1), _T_165) node _T_167 = and(_T_164, _T_166) when _T_167 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_168 = eq(sectored_entries[0][0].tag_v, hv) node _T_169 = bits(vpn, 1, 0) node _T_170 = eq(UInt<2>(0h2), _T_169) node _T_171 = and(_T_168, _T_170) when _T_171 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_172 = eq(sectored_entries[0][0].tag_v, hv) node _T_173 = bits(vpn, 1, 0) node _T_174 = eq(UInt<2>(0h3), _T_173) node _T_175 = and(_T_172, _T_174) when _T_175 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_176 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_177 = shr(_T_176, 18) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<42> connect _WIRE_9, sectored_entries[0][0].data[0] node _T_179 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_179 node _T_180 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_180 node _T_181 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_181 node _T_182 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_182 node _T_183 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_183 node _T_184 = bits(_WIRE_9, 5, 5) connect _WIRE_8.ppp, _T_184 node _T_185 = bits(_WIRE_9, 6, 6) connect _WIRE_8.pr, _T_185 node _T_186 = bits(_WIRE_9, 7, 7) connect _WIRE_8.px, _T_186 node _T_187 = bits(_WIRE_9, 8, 8) connect _WIRE_8.pw, _T_187 node _T_188 = bits(_WIRE_9, 9, 9) connect _WIRE_8.hr, _T_188 node _T_189 = bits(_WIRE_9, 10, 10) connect _WIRE_8.hx, _T_189 node _T_190 = bits(_WIRE_9, 11, 11) connect _WIRE_8.hw, _T_190 node _T_191 = bits(_WIRE_9, 12, 12) connect _WIRE_8.sr, _T_191 node _T_192 = bits(_WIRE_9, 13, 13) connect _WIRE_8.sx, _T_192 node _T_193 = bits(_WIRE_9, 14, 14) connect _WIRE_8.sw, _T_193 node _T_194 = bits(_WIRE_9, 15, 15) connect _WIRE_8.gf, _T_194 node _T_195 = bits(_WIRE_9, 16, 16) connect _WIRE_8.pf, _T_195 node _T_196 = bits(_WIRE_9, 17, 17) connect _WIRE_8.ae_stage2, _T_196 node _T_197 = bits(_WIRE_9, 18, 18) connect _WIRE_8.ae_final, _T_197 node _T_198 = bits(_WIRE_9, 19, 19) connect _WIRE_8.ae_ptw, _T_198 node _T_199 = bits(_WIRE_9, 20, 20) connect _WIRE_8.g, _T_199 node _T_200 = bits(_WIRE_9, 21, 21) connect _WIRE_8.u, _T_200 node _T_201 = bits(_WIRE_9, 41, 22) connect _WIRE_8.ppn, _T_201 wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<42> connect _WIRE_11, sectored_entries[0][0].data[1] node _T_202 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_202 node _T_203 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_203 node _T_204 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_204 node _T_205 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_205 node _T_206 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_206 node _T_207 = bits(_WIRE_11, 5, 5) connect _WIRE_10.ppp, _T_207 node _T_208 = bits(_WIRE_11, 6, 6) connect _WIRE_10.pr, _T_208 node _T_209 = bits(_WIRE_11, 7, 7) connect _WIRE_10.px, _T_209 node _T_210 = bits(_WIRE_11, 8, 8) connect _WIRE_10.pw, _T_210 node _T_211 = bits(_WIRE_11, 9, 9) connect _WIRE_10.hr, _T_211 node _T_212 = bits(_WIRE_11, 10, 10) connect _WIRE_10.hx, _T_212 node _T_213 = bits(_WIRE_11, 11, 11) connect _WIRE_10.hw, _T_213 node _T_214 = bits(_WIRE_11, 12, 12) connect _WIRE_10.sr, _T_214 node _T_215 = bits(_WIRE_11, 13, 13) connect _WIRE_10.sx, _T_215 node _T_216 = bits(_WIRE_11, 14, 14) connect _WIRE_10.sw, _T_216 node _T_217 = bits(_WIRE_11, 15, 15) connect _WIRE_10.gf, _T_217 node _T_218 = bits(_WIRE_11, 16, 16) connect _WIRE_10.pf, _T_218 node _T_219 = bits(_WIRE_11, 17, 17) connect _WIRE_10.ae_stage2, _T_219 node _T_220 = bits(_WIRE_11, 18, 18) connect _WIRE_10.ae_final, _T_220 node _T_221 = bits(_WIRE_11, 19, 19) connect _WIRE_10.ae_ptw, _T_221 node _T_222 = bits(_WIRE_11, 20, 20) connect _WIRE_10.g, _T_222 node _T_223 = bits(_WIRE_11, 21, 21) connect _WIRE_10.u, _T_223 node _T_224 = bits(_WIRE_11, 41, 22) connect _WIRE_10.ppn, _T_224 wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<42> connect _WIRE_13, sectored_entries[0][0].data[2] node _T_225 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_225 node _T_226 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_226 node _T_227 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_227 node _T_228 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_228 node _T_229 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_229 node _T_230 = bits(_WIRE_13, 5, 5) connect _WIRE_12.ppp, _T_230 node _T_231 = bits(_WIRE_13, 6, 6) connect _WIRE_12.pr, _T_231 node _T_232 = bits(_WIRE_13, 7, 7) connect _WIRE_12.px, _T_232 node _T_233 = bits(_WIRE_13, 8, 8) connect _WIRE_12.pw, _T_233 node _T_234 = bits(_WIRE_13, 9, 9) connect _WIRE_12.hr, _T_234 node _T_235 = bits(_WIRE_13, 10, 10) connect _WIRE_12.hx, _T_235 node _T_236 = bits(_WIRE_13, 11, 11) connect _WIRE_12.hw, _T_236 node _T_237 = bits(_WIRE_13, 12, 12) connect _WIRE_12.sr, _T_237 node _T_238 = bits(_WIRE_13, 13, 13) connect _WIRE_12.sx, _T_238 node _T_239 = bits(_WIRE_13, 14, 14) connect _WIRE_12.sw, _T_239 node _T_240 = bits(_WIRE_13, 15, 15) connect _WIRE_12.gf, _T_240 node _T_241 = bits(_WIRE_13, 16, 16) connect _WIRE_12.pf, _T_241 node _T_242 = bits(_WIRE_13, 17, 17) connect _WIRE_12.ae_stage2, _T_242 node _T_243 = bits(_WIRE_13, 18, 18) connect _WIRE_12.ae_final, _T_243 node _T_244 = bits(_WIRE_13, 19, 19) connect _WIRE_12.ae_ptw, _T_244 node _T_245 = bits(_WIRE_13, 20, 20) connect _WIRE_12.g, _T_245 node _T_246 = bits(_WIRE_13, 21, 21) connect _WIRE_12.u, _T_246 node _T_247 = bits(_WIRE_13, 41, 22) connect _WIRE_12.ppn, _T_247 wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<42> connect _WIRE_15, sectored_entries[0][0].data[3] node _T_248 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_248 node _T_249 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_249 node _T_250 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_250 node _T_251 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_251 node _T_252 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_252 node _T_253 = bits(_WIRE_15, 5, 5) connect _WIRE_14.ppp, _T_253 node _T_254 = bits(_WIRE_15, 6, 6) connect _WIRE_14.pr, _T_254 node _T_255 = bits(_WIRE_15, 7, 7) connect _WIRE_14.px, _T_255 node _T_256 = bits(_WIRE_15, 8, 8) connect _WIRE_14.pw, _T_256 node _T_257 = bits(_WIRE_15, 9, 9) connect _WIRE_14.hr, _T_257 node _T_258 = bits(_WIRE_15, 10, 10) connect _WIRE_14.hx, _T_258 node _T_259 = bits(_WIRE_15, 11, 11) connect _WIRE_14.hw, _T_259 node _T_260 = bits(_WIRE_15, 12, 12) connect _WIRE_14.sr, _T_260 node _T_261 = bits(_WIRE_15, 13, 13) connect _WIRE_14.sx, _T_261 node _T_262 = bits(_WIRE_15, 14, 14) connect _WIRE_14.sw, _T_262 node _T_263 = bits(_WIRE_15, 15, 15) connect _WIRE_14.gf, _T_263 node _T_264 = bits(_WIRE_15, 16, 16) connect _WIRE_14.pf, _T_264 node _T_265 = bits(_WIRE_15, 17, 17) connect _WIRE_14.ae_stage2, _T_265 node _T_266 = bits(_WIRE_15, 18, 18) connect _WIRE_14.ae_final, _T_266 node _T_267 = bits(_WIRE_15, 19, 19) connect _WIRE_14.ae_ptw, _T_267 node _T_268 = bits(_WIRE_15, 20, 20) connect _WIRE_14.g, _T_268 node _T_269 = bits(_WIRE_15, 21, 21) connect _WIRE_14.u, _T_269 node _T_270 = bits(_WIRE_15, 41, 22) connect _WIRE_14.ppn, _T_270 node _T_271 = eq(sectored_entries[0][0].tag_v, hv) node _T_272 = and(_T_271, _WIRE_8.fragmented_superpage) when _T_272 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_273 = eq(sectored_entries[0][0].tag_v, hv) node _T_274 = and(_T_273, _WIRE_10.fragmented_superpage) when _T_274 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_275 = eq(sectored_entries[0][0].tag_v, hv) node _T_276 = and(_T_275, _WIRE_12.fragmented_superpage) when _T_276 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_277 = eq(sectored_entries[0][0].tag_v, hv) node _T_278 = and(_T_277, _WIRE_14.fragmented_superpage) when _T_278 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_279 = eq(hg, UInt<1>(0h0)) node _T_280 = and(_T_279, io.sfence.bits.rs2) when _T_280 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<42> connect _WIRE_17, sectored_entries[0][0].data[0] node _T_281 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_281 node _T_282 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_282 node _T_283 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_283 node _T_284 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_284 node _T_285 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_285 node _T_286 = bits(_WIRE_17, 5, 5) connect _WIRE_16.ppp, _T_286 node _T_287 = bits(_WIRE_17, 6, 6) connect _WIRE_16.pr, _T_287 node _T_288 = bits(_WIRE_17, 7, 7) connect _WIRE_16.px, _T_288 node _T_289 = bits(_WIRE_17, 8, 8) connect _WIRE_16.pw, _T_289 node _T_290 = bits(_WIRE_17, 9, 9) connect _WIRE_16.hr, _T_290 node _T_291 = bits(_WIRE_17, 10, 10) connect _WIRE_16.hx, _T_291 node _T_292 = bits(_WIRE_17, 11, 11) connect _WIRE_16.hw, _T_292 node _T_293 = bits(_WIRE_17, 12, 12) connect _WIRE_16.sr, _T_293 node _T_294 = bits(_WIRE_17, 13, 13) connect _WIRE_16.sx, _T_294 node _T_295 = bits(_WIRE_17, 14, 14) connect _WIRE_16.sw, _T_295 node _T_296 = bits(_WIRE_17, 15, 15) connect _WIRE_16.gf, _T_296 node _T_297 = bits(_WIRE_17, 16, 16) connect _WIRE_16.pf, _T_297 node _T_298 = bits(_WIRE_17, 17, 17) connect _WIRE_16.ae_stage2, _T_298 node _T_299 = bits(_WIRE_17, 18, 18) connect _WIRE_16.ae_final, _T_299 node _T_300 = bits(_WIRE_17, 19, 19) connect _WIRE_16.ae_ptw, _T_300 node _T_301 = bits(_WIRE_17, 20, 20) connect _WIRE_16.g, _T_301 node _T_302 = bits(_WIRE_17, 21, 21) connect _WIRE_16.u, _T_302 node _T_303 = bits(_WIRE_17, 41, 22) connect _WIRE_16.ppn, _T_303 wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<42> connect _WIRE_19, sectored_entries[0][0].data[1] node _T_304 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_304 node _T_305 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_305 node _T_306 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_306 node _T_307 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_307 node _T_308 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_308 node _T_309 = bits(_WIRE_19, 5, 5) connect _WIRE_18.ppp, _T_309 node _T_310 = bits(_WIRE_19, 6, 6) connect _WIRE_18.pr, _T_310 node _T_311 = bits(_WIRE_19, 7, 7) connect _WIRE_18.px, _T_311 node _T_312 = bits(_WIRE_19, 8, 8) connect _WIRE_18.pw, _T_312 node _T_313 = bits(_WIRE_19, 9, 9) connect _WIRE_18.hr, _T_313 node _T_314 = bits(_WIRE_19, 10, 10) connect _WIRE_18.hx, _T_314 node _T_315 = bits(_WIRE_19, 11, 11) connect _WIRE_18.hw, _T_315 node _T_316 = bits(_WIRE_19, 12, 12) connect _WIRE_18.sr, _T_316 node _T_317 = bits(_WIRE_19, 13, 13) connect _WIRE_18.sx, _T_317 node _T_318 = bits(_WIRE_19, 14, 14) connect _WIRE_18.sw, _T_318 node _T_319 = bits(_WIRE_19, 15, 15) connect _WIRE_18.gf, _T_319 node _T_320 = bits(_WIRE_19, 16, 16) connect _WIRE_18.pf, _T_320 node _T_321 = bits(_WIRE_19, 17, 17) connect _WIRE_18.ae_stage2, _T_321 node _T_322 = bits(_WIRE_19, 18, 18) connect _WIRE_18.ae_final, _T_322 node _T_323 = bits(_WIRE_19, 19, 19) connect _WIRE_18.ae_ptw, _T_323 node _T_324 = bits(_WIRE_19, 20, 20) connect _WIRE_18.g, _T_324 node _T_325 = bits(_WIRE_19, 21, 21) connect _WIRE_18.u, _T_325 node _T_326 = bits(_WIRE_19, 41, 22) connect _WIRE_18.ppn, _T_326 wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<42> connect _WIRE_21, sectored_entries[0][0].data[2] node _T_327 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_327 node _T_328 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_328 node _T_329 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_329 node _T_330 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_330 node _T_331 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_331 node _T_332 = bits(_WIRE_21, 5, 5) connect _WIRE_20.ppp, _T_332 node _T_333 = bits(_WIRE_21, 6, 6) connect _WIRE_20.pr, _T_333 node _T_334 = bits(_WIRE_21, 7, 7) connect _WIRE_20.px, _T_334 node _T_335 = bits(_WIRE_21, 8, 8) connect _WIRE_20.pw, _T_335 node _T_336 = bits(_WIRE_21, 9, 9) connect _WIRE_20.hr, _T_336 node _T_337 = bits(_WIRE_21, 10, 10) connect _WIRE_20.hx, _T_337 node _T_338 = bits(_WIRE_21, 11, 11) connect _WIRE_20.hw, _T_338 node _T_339 = bits(_WIRE_21, 12, 12) connect _WIRE_20.sr, _T_339 node _T_340 = bits(_WIRE_21, 13, 13) connect _WIRE_20.sx, _T_340 node _T_341 = bits(_WIRE_21, 14, 14) connect _WIRE_20.sw, _T_341 node _T_342 = bits(_WIRE_21, 15, 15) connect _WIRE_20.gf, _T_342 node _T_343 = bits(_WIRE_21, 16, 16) connect _WIRE_20.pf, _T_343 node _T_344 = bits(_WIRE_21, 17, 17) connect _WIRE_20.ae_stage2, _T_344 node _T_345 = bits(_WIRE_21, 18, 18) connect _WIRE_20.ae_final, _T_345 node _T_346 = bits(_WIRE_21, 19, 19) connect _WIRE_20.ae_ptw, _T_346 node _T_347 = bits(_WIRE_21, 20, 20) connect _WIRE_20.g, _T_347 node _T_348 = bits(_WIRE_21, 21, 21) connect _WIRE_20.u, _T_348 node _T_349 = bits(_WIRE_21, 41, 22) connect _WIRE_20.ppn, _T_349 wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<42> connect _WIRE_23, sectored_entries[0][0].data[3] node _T_350 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_350 node _T_351 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_351 node _T_352 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_352 node _T_353 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_353 node _T_354 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_354 node _T_355 = bits(_WIRE_23, 5, 5) connect _WIRE_22.ppp, _T_355 node _T_356 = bits(_WIRE_23, 6, 6) connect _WIRE_22.pr, _T_356 node _T_357 = bits(_WIRE_23, 7, 7) connect _WIRE_22.px, _T_357 node _T_358 = bits(_WIRE_23, 8, 8) connect _WIRE_22.pw, _T_358 node _T_359 = bits(_WIRE_23, 9, 9) connect _WIRE_22.hr, _T_359 node _T_360 = bits(_WIRE_23, 10, 10) connect _WIRE_22.hx, _T_360 node _T_361 = bits(_WIRE_23, 11, 11) connect _WIRE_22.hw, _T_361 node _T_362 = bits(_WIRE_23, 12, 12) connect _WIRE_22.sr, _T_362 node _T_363 = bits(_WIRE_23, 13, 13) connect _WIRE_22.sx, _T_363 node _T_364 = bits(_WIRE_23, 14, 14) connect _WIRE_22.sw, _T_364 node _T_365 = bits(_WIRE_23, 15, 15) connect _WIRE_22.gf, _T_365 node _T_366 = bits(_WIRE_23, 16, 16) connect _WIRE_22.pf, _T_366 node _T_367 = bits(_WIRE_23, 17, 17) connect _WIRE_22.ae_stage2, _T_367 node _T_368 = bits(_WIRE_23, 18, 18) connect _WIRE_22.ae_final, _T_368 node _T_369 = bits(_WIRE_23, 19, 19) connect _WIRE_22.ae_ptw, _T_369 node _T_370 = bits(_WIRE_23, 20, 20) connect _WIRE_22.g, _T_370 node _T_371 = bits(_WIRE_23, 21, 21) connect _WIRE_22.u, _T_371 node _T_372 = bits(_WIRE_23, 41, 22) connect _WIRE_22.ppn, _T_372 node _T_373 = eq(sectored_entries[0][0].tag_v, hv) node _T_374 = eq(_WIRE_16.g, UInt<1>(0h0)) node _T_375 = and(_T_373, _T_374) when _T_375 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_376 = eq(sectored_entries[0][0].tag_v, hv) node _T_377 = eq(_WIRE_18.g, UInt<1>(0h0)) node _T_378 = and(_T_376, _T_377) when _T_378 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_379 = eq(sectored_entries[0][0].tag_v, hv) node _T_380 = eq(_WIRE_20.g, UInt<1>(0h0)) node _T_381 = and(_T_379, _T_380) when _T_381 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_382 = eq(sectored_entries[0][0].tag_v, hv) node _T_383 = eq(_WIRE_22.g, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) when _T_384 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_385 = or(hv, hg) wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<42> connect _WIRE_25, sectored_entries[0][0].data[0] node _T_386 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_386 node _T_387 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_387 node _T_388 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_388 node _T_389 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_389 node _T_390 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_390 node _T_391 = bits(_WIRE_25, 5, 5) connect _WIRE_24.ppp, _T_391 node _T_392 = bits(_WIRE_25, 6, 6) connect _WIRE_24.pr, _T_392 node _T_393 = bits(_WIRE_25, 7, 7) connect _WIRE_24.px, _T_393 node _T_394 = bits(_WIRE_25, 8, 8) connect _WIRE_24.pw, _T_394 node _T_395 = bits(_WIRE_25, 9, 9) connect _WIRE_24.hr, _T_395 node _T_396 = bits(_WIRE_25, 10, 10) connect _WIRE_24.hx, _T_396 node _T_397 = bits(_WIRE_25, 11, 11) connect _WIRE_24.hw, _T_397 node _T_398 = bits(_WIRE_25, 12, 12) connect _WIRE_24.sr, _T_398 node _T_399 = bits(_WIRE_25, 13, 13) connect _WIRE_24.sx, _T_399 node _T_400 = bits(_WIRE_25, 14, 14) connect _WIRE_24.sw, _T_400 node _T_401 = bits(_WIRE_25, 15, 15) connect _WIRE_24.gf, _T_401 node _T_402 = bits(_WIRE_25, 16, 16) connect _WIRE_24.pf, _T_402 node _T_403 = bits(_WIRE_25, 17, 17) connect _WIRE_24.ae_stage2, _T_403 node _T_404 = bits(_WIRE_25, 18, 18) connect _WIRE_24.ae_final, _T_404 node _T_405 = bits(_WIRE_25, 19, 19) connect _WIRE_24.ae_ptw, _T_405 node _T_406 = bits(_WIRE_25, 20, 20) connect _WIRE_24.g, _T_406 node _T_407 = bits(_WIRE_25, 21, 21) connect _WIRE_24.u, _T_407 node _T_408 = bits(_WIRE_25, 41, 22) connect _WIRE_24.ppn, _T_408 wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<42> connect _WIRE_27, sectored_entries[0][0].data[1] node _T_409 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_409 node _T_410 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_410 node _T_411 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_411 node _T_412 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_412 node _T_413 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_413 node _T_414 = bits(_WIRE_27, 5, 5) connect _WIRE_26.ppp, _T_414 node _T_415 = bits(_WIRE_27, 6, 6) connect _WIRE_26.pr, _T_415 node _T_416 = bits(_WIRE_27, 7, 7) connect _WIRE_26.px, _T_416 node _T_417 = bits(_WIRE_27, 8, 8) connect _WIRE_26.pw, _T_417 node _T_418 = bits(_WIRE_27, 9, 9) connect _WIRE_26.hr, _T_418 node _T_419 = bits(_WIRE_27, 10, 10) connect _WIRE_26.hx, _T_419 node _T_420 = bits(_WIRE_27, 11, 11) connect _WIRE_26.hw, _T_420 node _T_421 = bits(_WIRE_27, 12, 12) connect _WIRE_26.sr, _T_421 node _T_422 = bits(_WIRE_27, 13, 13) connect _WIRE_26.sx, _T_422 node _T_423 = bits(_WIRE_27, 14, 14) connect _WIRE_26.sw, _T_423 node _T_424 = bits(_WIRE_27, 15, 15) connect _WIRE_26.gf, _T_424 node _T_425 = bits(_WIRE_27, 16, 16) connect _WIRE_26.pf, _T_425 node _T_426 = bits(_WIRE_27, 17, 17) connect _WIRE_26.ae_stage2, _T_426 node _T_427 = bits(_WIRE_27, 18, 18) connect _WIRE_26.ae_final, _T_427 node _T_428 = bits(_WIRE_27, 19, 19) connect _WIRE_26.ae_ptw, _T_428 node _T_429 = bits(_WIRE_27, 20, 20) connect _WIRE_26.g, _T_429 node _T_430 = bits(_WIRE_27, 21, 21) connect _WIRE_26.u, _T_430 node _T_431 = bits(_WIRE_27, 41, 22) connect _WIRE_26.ppn, _T_431 wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<42> connect _WIRE_29, sectored_entries[0][0].data[2] node _T_432 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_432 node _T_433 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_433 node _T_434 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_434 node _T_435 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_435 node _T_436 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_436 node _T_437 = bits(_WIRE_29, 5, 5) connect _WIRE_28.ppp, _T_437 node _T_438 = bits(_WIRE_29, 6, 6) connect _WIRE_28.pr, _T_438 node _T_439 = bits(_WIRE_29, 7, 7) connect _WIRE_28.px, _T_439 node _T_440 = bits(_WIRE_29, 8, 8) connect _WIRE_28.pw, _T_440 node _T_441 = bits(_WIRE_29, 9, 9) connect _WIRE_28.hr, _T_441 node _T_442 = bits(_WIRE_29, 10, 10) connect _WIRE_28.hx, _T_442 node _T_443 = bits(_WIRE_29, 11, 11) connect _WIRE_28.hw, _T_443 node _T_444 = bits(_WIRE_29, 12, 12) connect _WIRE_28.sr, _T_444 node _T_445 = bits(_WIRE_29, 13, 13) connect _WIRE_28.sx, _T_445 node _T_446 = bits(_WIRE_29, 14, 14) connect _WIRE_28.sw, _T_446 node _T_447 = bits(_WIRE_29, 15, 15) connect _WIRE_28.gf, _T_447 node _T_448 = bits(_WIRE_29, 16, 16) connect _WIRE_28.pf, _T_448 node _T_449 = bits(_WIRE_29, 17, 17) connect _WIRE_28.ae_stage2, _T_449 node _T_450 = bits(_WIRE_29, 18, 18) connect _WIRE_28.ae_final, _T_450 node _T_451 = bits(_WIRE_29, 19, 19) connect _WIRE_28.ae_ptw, _T_451 node _T_452 = bits(_WIRE_29, 20, 20) connect _WIRE_28.g, _T_452 node _T_453 = bits(_WIRE_29, 21, 21) connect _WIRE_28.u, _T_453 node _T_454 = bits(_WIRE_29, 41, 22) connect _WIRE_28.ppn, _T_454 wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<42> connect _WIRE_31, sectored_entries[0][0].data[3] node _T_455 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_455 node _T_456 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_456 node _T_457 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_457 node _T_458 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_458 node _T_459 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_459 node _T_460 = bits(_WIRE_31, 5, 5) connect _WIRE_30.ppp, _T_460 node _T_461 = bits(_WIRE_31, 6, 6) connect _WIRE_30.pr, _T_461 node _T_462 = bits(_WIRE_31, 7, 7) connect _WIRE_30.px, _T_462 node _T_463 = bits(_WIRE_31, 8, 8) connect _WIRE_30.pw, _T_463 node _T_464 = bits(_WIRE_31, 9, 9) connect _WIRE_30.hr, _T_464 node _T_465 = bits(_WIRE_31, 10, 10) connect _WIRE_30.hx, _T_465 node _T_466 = bits(_WIRE_31, 11, 11) connect _WIRE_30.hw, _T_466 node _T_467 = bits(_WIRE_31, 12, 12) connect _WIRE_30.sr, _T_467 node _T_468 = bits(_WIRE_31, 13, 13) connect _WIRE_30.sx, _T_468 node _T_469 = bits(_WIRE_31, 14, 14) connect _WIRE_30.sw, _T_469 node _T_470 = bits(_WIRE_31, 15, 15) connect _WIRE_30.gf, _T_470 node _T_471 = bits(_WIRE_31, 16, 16) connect _WIRE_30.pf, _T_471 node _T_472 = bits(_WIRE_31, 17, 17) connect _WIRE_30.ae_stage2, _T_472 node _T_473 = bits(_WIRE_31, 18, 18) connect _WIRE_30.ae_final, _T_473 node _T_474 = bits(_WIRE_31, 19, 19) connect _WIRE_30.ae_ptw, _T_474 node _T_475 = bits(_WIRE_31, 20, 20) connect _WIRE_30.g, _T_475 node _T_476 = bits(_WIRE_31, 21, 21) connect _WIRE_30.u, _T_476 node _T_477 = bits(_WIRE_31, 41, 22) connect _WIRE_30.ppn, _T_477 node _T_478 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_478 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_479 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_479 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_480 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_480 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_481 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_481 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_482 = eq(hg_1, UInt<1>(0h0)) node _T_483 = and(_T_482, io.sfence.bits.rs1) when _T_483 : node _T_484 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_485 = shr(_T_484, 2) node _T_486 = eq(_T_485, UInt<1>(0h0)) node _T_487 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_488 = and(_T_486, _T_487) when _T_488 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<42> connect _WIRE_33, sectored_entries[0][1].data[0] node _T_489 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_489 node _T_490 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_490 node _T_491 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_491 node _T_492 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_492 node _T_493 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_493 node _T_494 = bits(_WIRE_33, 5, 5) connect _WIRE_32.ppp, _T_494 node _T_495 = bits(_WIRE_33, 6, 6) connect _WIRE_32.pr, _T_495 node _T_496 = bits(_WIRE_33, 7, 7) connect _WIRE_32.px, _T_496 node _T_497 = bits(_WIRE_33, 8, 8) connect _WIRE_32.pw, _T_497 node _T_498 = bits(_WIRE_33, 9, 9) connect _WIRE_32.hr, _T_498 node _T_499 = bits(_WIRE_33, 10, 10) connect _WIRE_32.hx, _T_499 node _T_500 = bits(_WIRE_33, 11, 11) connect _WIRE_32.hw, _T_500 node _T_501 = bits(_WIRE_33, 12, 12) connect _WIRE_32.sr, _T_501 node _T_502 = bits(_WIRE_33, 13, 13) connect _WIRE_32.sx, _T_502 node _T_503 = bits(_WIRE_33, 14, 14) connect _WIRE_32.sw, _T_503 node _T_504 = bits(_WIRE_33, 15, 15) connect _WIRE_32.gf, _T_504 node _T_505 = bits(_WIRE_33, 16, 16) connect _WIRE_32.pf, _T_505 node _T_506 = bits(_WIRE_33, 17, 17) connect _WIRE_32.ae_stage2, _T_506 node _T_507 = bits(_WIRE_33, 18, 18) connect _WIRE_32.ae_final, _T_507 node _T_508 = bits(_WIRE_33, 19, 19) connect _WIRE_32.ae_ptw, _T_508 node _T_509 = bits(_WIRE_33, 20, 20) connect _WIRE_32.g, _T_509 node _T_510 = bits(_WIRE_33, 21, 21) connect _WIRE_32.u, _T_510 node _T_511 = bits(_WIRE_33, 41, 22) connect _WIRE_32.ppn, _T_511 wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<42> connect _WIRE_35, sectored_entries[0][1].data[1] node _T_512 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_512 node _T_513 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_513 node _T_514 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_514 node _T_515 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_515 node _T_516 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_516 node _T_517 = bits(_WIRE_35, 5, 5) connect _WIRE_34.ppp, _T_517 node _T_518 = bits(_WIRE_35, 6, 6) connect _WIRE_34.pr, _T_518 node _T_519 = bits(_WIRE_35, 7, 7) connect _WIRE_34.px, _T_519 node _T_520 = bits(_WIRE_35, 8, 8) connect _WIRE_34.pw, _T_520 node _T_521 = bits(_WIRE_35, 9, 9) connect _WIRE_34.hr, _T_521 node _T_522 = bits(_WIRE_35, 10, 10) connect _WIRE_34.hx, _T_522 node _T_523 = bits(_WIRE_35, 11, 11) connect _WIRE_34.hw, _T_523 node _T_524 = bits(_WIRE_35, 12, 12) connect _WIRE_34.sr, _T_524 node _T_525 = bits(_WIRE_35, 13, 13) connect _WIRE_34.sx, _T_525 node _T_526 = bits(_WIRE_35, 14, 14) connect _WIRE_34.sw, _T_526 node _T_527 = bits(_WIRE_35, 15, 15) connect _WIRE_34.gf, _T_527 node _T_528 = bits(_WIRE_35, 16, 16) connect _WIRE_34.pf, _T_528 node _T_529 = bits(_WIRE_35, 17, 17) connect _WIRE_34.ae_stage2, _T_529 node _T_530 = bits(_WIRE_35, 18, 18) connect _WIRE_34.ae_final, _T_530 node _T_531 = bits(_WIRE_35, 19, 19) connect _WIRE_34.ae_ptw, _T_531 node _T_532 = bits(_WIRE_35, 20, 20) connect _WIRE_34.g, _T_532 node _T_533 = bits(_WIRE_35, 21, 21) connect _WIRE_34.u, _T_533 node _T_534 = bits(_WIRE_35, 41, 22) connect _WIRE_34.ppn, _T_534 wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<42> connect _WIRE_37, sectored_entries[0][1].data[2] node _T_535 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_535 node _T_536 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_536 node _T_537 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_537 node _T_538 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_538 node _T_539 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_539 node _T_540 = bits(_WIRE_37, 5, 5) connect _WIRE_36.ppp, _T_540 node _T_541 = bits(_WIRE_37, 6, 6) connect _WIRE_36.pr, _T_541 node _T_542 = bits(_WIRE_37, 7, 7) connect _WIRE_36.px, _T_542 node _T_543 = bits(_WIRE_37, 8, 8) connect _WIRE_36.pw, _T_543 node _T_544 = bits(_WIRE_37, 9, 9) connect _WIRE_36.hr, _T_544 node _T_545 = bits(_WIRE_37, 10, 10) connect _WIRE_36.hx, _T_545 node _T_546 = bits(_WIRE_37, 11, 11) connect _WIRE_36.hw, _T_546 node _T_547 = bits(_WIRE_37, 12, 12) connect _WIRE_36.sr, _T_547 node _T_548 = bits(_WIRE_37, 13, 13) connect _WIRE_36.sx, _T_548 node _T_549 = bits(_WIRE_37, 14, 14) connect _WIRE_36.sw, _T_549 node _T_550 = bits(_WIRE_37, 15, 15) connect _WIRE_36.gf, _T_550 node _T_551 = bits(_WIRE_37, 16, 16) connect _WIRE_36.pf, _T_551 node _T_552 = bits(_WIRE_37, 17, 17) connect _WIRE_36.ae_stage2, _T_552 node _T_553 = bits(_WIRE_37, 18, 18) connect _WIRE_36.ae_final, _T_553 node _T_554 = bits(_WIRE_37, 19, 19) connect _WIRE_36.ae_ptw, _T_554 node _T_555 = bits(_WIRE_37, 20, 20) connect _WIRE_36.g, _T_555 node _T_556 = bits(_WIRE_37, 21, 21) connect _WIRE_36.u, _T_556 node _T_557 = bits(_WIRE_37, 41, 22) connect _WIRE_36.ppn, _T_557 wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<42> connect _WIRE_39, sectored_entries[0][1].data[3] node _T_558 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_558 node _T_559 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_559 node _T_560 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_560 node _T_561 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_561 node _T_562 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_562 node _T_563 = bits(_WIRE_39, 5, 5) connect _WIRE_38.ppp, _T_563 node _T_564 = bits(_WIRE_39, 6, 6) connect _WIRE_38.pr, _T_564 node _T_565 = bits(_WIRE_39, 7, 7) connect _WIRE_38.px, _T_565 node _T_566 = bits(_WIRE_39, 8, 8) connect _WIRE_38.pw, _T_566 node _T_567 = bits(_WIRE_39, 9, 9) connect _WIRE_38.hr, _T_567 node _T_568 = bits(_WIRE_39, 10, 10) connect _WIRE_38.hx, _T_568 node _T_569 = bits(_WIRE_39, 11, 11) connect _WIRE_38.hw, _T_569 node _T_570 = bits(_WIRE_39, 12, 12) connect _WIRE_38.sr, _T_570 node _T_571 = bits(_WIRE_39, 13, 13) connect _WIRE_38.sx, _T_571 node _T_572 = bits(_WIRE_39, 14, 14) connect _WIRE_38.sw, _T_572 node _T_573 = bits(_WIRE_39, 15, 15) connect _WIRE_38.gf, _T_573 node _T_574 = bits(_WIRE_39, 16, 16) connect _WIRE_38.pf, _T_574 node _T_575 = bits(_WIRE_39, 17, 17) connect _WIRE_38.ae_stage2, _T_575 node _T_576 = bits(_WIRE_39, 18, 18) connect _WIRE_38.ae_final, _T_576 node _T_577 = bits(_WIRE_39, 19, 19) connect _WIRE_38.ae_ptw, _T_577 node _T_578 = bits(_WIRE_39, 20, 20) connect _WIRE_38.g, _T_578 node _T_579 = bits(_WIRE_39, 21, 21) connect _WIRE_38.u, _T_579 node _T_580 = bits(_WIRE_39, 41, 22) connect _WIRE_38.ppn, _T_580 node _T_581 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_582 = bits(vpn, 1, 0) node _T_583 = eq(UInt<1>(0h0), _T_582) node _T_584 = and(_T_581, _T_583) when _T_584 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_585 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_586 = bits(vpn, 1, 0) node _T_587 = eq(UInt<1>(0h1), _T_586) node _T_588 = and(_T_585, _T_587) when _T_588 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_589 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_590 = bits(vpn, 1, 0) node _T_591 = eq(UInt<2>(0h2), _T_590) node _T_592 = and(_T_589, _T_591) when _T_592 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_593 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_594 = bits(vpn, 1, 0) node _T_595 = eq(UInt<2>(0h3), _T_594) node _T_596 = and(_T_593, _T_595) when _T_596 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_597 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_598 = shr(_T_597, 18) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<42> connect _WIRE_41, sectored_entries[0][1].data[0] node _T_600 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_600 node _T_601 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_601 node _T_602 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_602 node _T_603 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_603 node _T_604 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_604 node _T_605 = bits(_WIRE_41, 5, 5) connect _WIRE_40.ppp, _T_605 node _T_606 = bits(_WIRE_41, 6, 6) connect _WIRE_40.pr, _T_606 node _T_607 = bits(_WIRE_41, 7, 7) connect _WIRE_40.px, _T_607 node _T_608 = bits(_WIRE_41, 8, 8) connect _WIRE_40.pw, _T_608 node _T_609 = bits(_WIRE_41, 9, 9) connect _WIRE_40.hr, _T_609 node _T_610 = bits(_WIRE_41, 10, 10) connect _WIRE_40.hx, _T_610 node _T_611 = bits(_WIRE_41, 11, 11) connect _WIRE_40.hw, _T_611 node _T_612 = bits(_WIRE_41, 12, 12) connect _WIRE_40.sr, _T_612 node _T_613 = bits(_WIRE_41, 13, 13) connect _WIRE_40.sx, _T_613 node _T_614 = bits(_WIRE_41, 14, 14) connect _WIRE_40.sw, _T_614 node _T_615 = bits(_WIRE_41, 15, 15) connect _WIRE_40.gf, _T_615 node _T_616 = bits(_WIRE_41, 16, 16) connect _WIRE_40.pf, _T_616 node _T_617 = bits(_WIRE_41, 17, 17) connect _WIRE_40.ae_stage2, _T_617 node _T_618 = bits(_WIRE_41, 18, 18) connect _WIRE_40.ae_final, _T_618 node _T_619 = bits(_WIRE_41, 19, 19) connect _WIRE_40.ae_ptw, _T_619 node _T_620 = bits(_WIRE_41, 20, 20) connect _WIRE_40.g, _T_620 node _T_621 = bits(_WIRE_41, 21, 21) connect _WIRE_40.u, _T_621 node _T_622 = bits(_WIRE_41, 41, 22) connect _WIRE_40.ppn, _T_622 wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_43 : UInt<42> connect _WIRE_43, sectored_entries[0][1].data[1] node _T_623 = bits(_WIRE_43, 0, 0) connect _WIRE_42.fragmented_superpage, _T_623 node _T_624 = bits(_WIRE_43, 1, 1) connect _WIRE_42.c, _T_624 node _T_625 = bits(_WIRE_43, 2, 2) connect _WIRE_42.eff, _T_625 node _T_626 = bits(_WIRE_43, 3, 3) connect _WIRE_42.paa, _T_626 node _T_627 = bits(_WIRE_43, 4, 4) connect _WIRE_42.pal, _T_627 node _T_628 = bits(_WIRE_43, 5, 5) connect _WIRE_42.ppp, _T_628 node _T_629 = bits(_WIRE_43, 6, 6) connect _WIRE_42.pr, _T_629 node _T_630 = bits(_WIRE_43, 7, 7) connect _WIRE_42.px, _T_630 node _T_631 = bits(_WIRE_43, 8, 8) connect _WIRE_42.pw, _T_631 node _T_632 = bits(_WIRE_43, 9, 9) connect _WIRE_42.hr, _T_632 node _T_633 = bits(_WIRE_43, 10, 10) connect _WIRE_42.hx, _T_633 node _T_634 = bits(_WIRE_43, 11, 11) connect _WIRE_42.hw, _T_634 node _T_635 = bits(_WIRE_43, 12, 12) connect _WIRE_42.sr, _T_635 node _T_636 = bits(_WIRE_43, 13, 13) connect _WIRE_42.sx, _T_636 node _T_637 = bits(_WIRE_43, 14, 14) connect _WIRE_42.sw, _T_637 node _T_638 = bits(_WIRE_43, 15, 15) connect _WIRE_42.gf, _T_638 node _T_639 = bits(_WIRE_43, 16, 16) connect _WIRE_42.pf, _T_639 node _T_640 = bits(_WIRE_43, 17, 17) connect _WIRE_42.ae_stage2, _T_640 node _T_641 = bits(_WIRE_43, 18, 18) connect _WIRE_42.ae_final, _T_641 node _T_642 = bits(_WIRE_43, 19, 19) connect _WIRE_42.ae_ptw, _T_642 node _T_643 = bits(_WIRE_43, 20, 20) connect _WIRE_42.g, _T_643 node _T_644 = bits(_WIRE_43, 21, 21) connect _WIRE_42.u, _T_644 node _T_645 = bits(_WIRE_43, 41, 22) connect _WIRE_42.ppn, _T_645 wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_45 : UInt<42> connect _WIRE_45, sectored_entries[0][1].data[2] node _T_646 = bits(_WIRE_45, 0, 0) connect _WIRE_44.fragmented_superpage, _T_646 node _T_647 = bits(_WIRE_45, 1, 1) connect _WIRE_44.c, _T_647 node _T_648 = bits(_WIRE_45, 2, 2) connect _WIRE_44.eff, _T_648 node _T_649 = bits(_WIRE_45, 3, 3) connect _WIRE_44.paa, _T_649 node _T_650 = bits(_WIRE_45, 4, 4) connect _WIRE_44.pal, _T_650 node _T_651 = bits(_WIRE_45, 5, 5) connect _WIRE_44.ppp, _T_651 node _T_652 = bits(_WIRE_45, 6, 6) connect _WIRE_44.pr, _T_652 node _T_653 = bits(_WIRE_45, 7, 7) connect _WIRE_44.px, _T_653 node _T_654 = bits(_WIRE_45, 8, 8) connect _WIRE_44.pw, _T_654 node _T_655 = bits(_WIRE_45, 9, 9) connect _WIRE_44.hr, _T_655 node _T_656 = bits(_WIRE_45, 10, 10) connect _WIRE_44.hx, _T_656 node _T_657 = bits(_WIRE_45, 11, 11) connect _WIRE_44.hw, _T_657 node _T_658 = bits(_WIRE_45, 12, 12) connect _WIRE_44.sr, _T_658 node _T_659 = bits(_WIRE_45, 13, 13) connect _WIRE_44.sx, _T_659 node _T_660 = bits(_WIRE_45, 14, 14) connect _WIRE_44.sw, _T_660 node _T_661 = bits(_WIRE_45, 15, 15) connect _WIRE_44.gf, _T_661 node _T_662 = bits(_WIRE_45, 16, 16) connect _WIRE_44.pf, _T_662 node _T_663 = bits(_WIRE_45, 17, 17) connect _WIRE_44.ae_stage2, _T_663 node _T_664 = bits(_WIRE_45, 18, 18) connect _WIRE_44.ae_final, _T_664 node _T_665 = bits(_WIRE_45, 19, 19) connect _WIRE_44.ae_ptw, _T_665 node _T_666 = bits(_WIRE_45, 20, 20) connect _WIRE_44.g, _T_666 node _T_667 = bits(_WIRE_45, 21, 21) connect _WIRE_44.u, _T_667 node _T_668 = bits(_WIRE_45, 41, 22) connect _WIRE_44.ppn, _T_668 wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_47 : UInt<42> connect _WIRE_47, sectored_entries[0][1].data[3] node _T_669 = bits(_WIRE_47, 0, 0) connect _WIRE_46.fragmented_superpage, _T_669 node _T_670 = bits(_WIRE_47, 1, 1) connect _WIRE_46.c, _T_670 node _T_671 = bits(_WIRE_47, 2, 2) connect _WIRE_46.eff, _T_671 node _T_672 = bits(_WIRE_47, 3, 3) connect _WIRE_46.paa, _T_672 node _T_673 = bits(_WIRE_47, 4, 4) connect _WIRE_46.pal, _T_673 node _T_674 = bits(_WIRE_47, 5, 5) connect _WIRE_46.ppp, _T_674 node _T_675 = bits(_WIRE_47, 6, 6) connect _WIRE_46.pr, _T_675 node _T_676 = bits(_WIRE_47, 7, 7) connect _WIRE_46.px, _T_676 node _T_677 = bits(_WIRE_47, 8, 8) connect _WIRE_46.pw, _T_677 node _T_678 = bits(_WIRE_47, 9, 9) connect _WIRE_46.hr, _T_678 node _T_679 = bits(_WIRE_47, 10, 10) connect _WIRE_46.hx, _T_679 node _T_680 = bits(_WIRE_47, 11, 11) connect _WIRE_46.hw, _T_680 node _T_681 = bits(_WIRE_47, 12, 12) connect _WIRE_46.sr, _T_681 node _T_682 = bits(_WIRE_47, 13, 13) connect _WIRE_46.sx, _T_682 node _T_683 = bits(_WIRE_47, 14, 14) connect _WIRE_46.sw, _T_683 node _T_684 = bits(_WIRE_47, 15, 15) connect _WIRE_46.gf, _T_684 node _T_685 = bits(_WIRE_47, 16, 16) connect _WIRE_46.pf, _T_685 node _T_686 = bits(_WIRE_47, 17, 17) connect _WIRE_46.ae_stage2, _T_686 node _T_687 = bits(_WIRE_47, 18, 18) connect _WIRE_46.ae_final, _T_687 node _T_688 = bits(_WIRE_47, 19, 19) connect _WIRE_46.ae_ptw, _T_688 node _T_689 = bits(_WIRE_47, 20, 20) connect _WIRE_46.g, _T_689 node _T_690 = bits(_WIRE_47, 21, 21) connect _WIRE_46.u, _T_690 node _T_691 = bits(_WIRE_47, 41, 22) connect _WIRE_46.ppn, _T_691 node _T_692 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_693 = and(_T_692, _WIRE_40.fragmented_superpage) when _T_693 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_694 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_695 = and(_T_694, _WIRE_42.fragmented_superpage) when _T_695 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_696 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_697 = and(_T_696, _WIRE_44.fragmented_superpage) when _T_697 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_698 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_699 = and(_T_698, _WIRE_46.fragmented_superpage) when _T_699 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_700 = eq(hg_1, UInt<1>(0h0)) node _T_701 = and(_T_700, io.sfence.bits.rs2) when _T_701 : wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_49 : UInt<42> connect _WIRE_49, sectored_entries[0][1].data[0] node _T_702 = bits(_WIRE_49, 0, 0) connect _WIRE_48.fragmented_superpage, _T_702 node _T_703 = bits(_WIRE_49, 1, 1) connect _WIRE_48.c, _T_703 node _T_704 = bits(_WIRE_49, 2, 2) connect _WIRE_48.eff, _T_704 node _T_705 = bits(_WIRE_49, 3, 3) connect _WIRE_48.paa, _T_705 node _T_706 = bits(_WIRE_49, 4, 4) connect _WIRE_48.pal, _T_706 node _T_707 = bits(_WIRE_49, 5, 5) connect _WIRE_48.ppp, _T_707 node _T_708 = bits(_WIRE_49, 6, 6) connect _WIRE_48.pr, _T_708 node _T_709 = bits(_WIRE_49, 7, 7) connect _WIRE_48.px, _T_709 node _T_710 = bits(_WIRE_49, 8, 8) connect _WIRE_48.pw, _T_710 node _T_711 = bits(_WIRE_49, 9, 9) connect _WIRE_48.hr, _T_711 node _T_712 = bits(_WIRE_49, 10, 10) connect _WIRE_48.hx, _T_712 node _T_713 = bits(_WIRE_49, 11, 11) connect _WIRE_48.hw, _T_713 node _T_714 = bits(_WIRE_49, 12, 12) connect _WIRE_48.sr, _T_714 node _T_715 = bits(_WIRE_49, 13, 13) connect _WIRE_48.sx, _T_715 node _T_716 = bits(_WIRE_49, 14, 14) connect _WIRE_48.sw, _T_716 node _T_717 = bits(_WIRE_49, 15, 15) connect _WIRE_48.gf, _T_717 node _T_718 = bits(_WIRE_49, 16, 16) connect _WIRE_48.pf, _T_718 node _T_719 = bits(_WIRE_49, 17, 17) connect _WIRE_48.ae_stage2, _T_719 node _T_720 = bits(_WIRE_49, 18, 18) connect _WIRE_48.ae_final, _T_720 node _T_721 = bits(_WIRE_49, 19, 19) connect _WIRE_48.ae_ptw, _T_721 node _T_722 = bits(_WIRE_49, 20, 20) connect _WIRE_48.g, _T_722 node _T_723 = bits(_WIRE_49, 21, 21) connect _WIRE_48.u, _T_723 node _T_724 = bits(_WIRE_49, 41, 22) connect _WIRE_48.ppn, _T_724 wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_51 : UInt<42> connect _WIRE_51, sectored_entries[0][1].data[1] node _T_725 = bits(_WIRE_51, 0, 0) connect _WIRE_50.fragmented_superpage, _T_725 node _T_726 = bits(_WIRE_51, 1, 1) connect _WIRE_50.c, _T_726 node _T_727 = bits(_WIRE_51, 2, 2) connect _WIRE_50.eff, _T_727 node _T_728 = bits(_WIRE_51, 3, 3) connect _WIRE_50.paa, _T_728 node _T_729 = bits(_WIRE_51, 4, 4) connect _WIRE_50.pal, _T_729 node _T_730 = bits(_WIRE_51, 5, 5) connect _WIRE_50.ppp, _T_730 node _T_731 = bits(_WIRE_51, 6, 6) connect _WIRE_50.pr, _T_731 node _T_732 = bits(_WIRE_51, 7, 7) connect _WIRE_50.px, _T_732 node _T_733 = bits(_WIRE_51, 8, 8) connect _WIRE_50.pw, _T_733 node _T_734 = bits(_WIRE_51, 9, 9) connect _WIRE_50.hr, _T_734 node _T_735 = bits(_WIRE_51, 10, 10) connect _WIRE_50.hx, _T_735 node _T_736 = bits(_WIRE_51, 11, 11) connect _WIRE_50.hw, _T_736 node _T_737 = bits(_WIRE_51, 12, 12) connect _WIRE_50.sr, _T_737 node _T_738 = bits(_WIRE_51, 13, 13) connect _WIRE_50.sx, _T_738 node _T_739 = bits(_WIRE_51, 14, 14) connect _WIRE_50.sw, _T_739 node _T_740 = bits(_WIRE_51, 15, 15) connect _WIRE_50.gf, _T_740 node _T_741 = bits(_WIRE_51, 16, 16) connect _WIRE_50.pf, _T_741 node _T_742 = bits(_WIRE_51, 17, 17) connect _WIRE_50.ae_stage2, _T_742 node _T_743 = bits(_WIRE_51, 18, 18) connect _WIRE_50.ae_final, _T_743 node _T_744 = bits(_WIRE_51, 19, 19) connect _WIRE_50.ae_ptw, _T_744 node _T_745 = bits(_WIRE_51, 20, 20) connect _WIRE_50.g, _T_745 node _T_746 = bits(_WIRE_51, 21, 21) connect _WIRE_50.u, _T_746 node _T_747 = bits(_WIRE_51, 41, 22) connect _WIRE_50.ppn, _T_747 wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_53 : UInt<42> connect _WIRE_53, sectored_entries[0][1].data[2] node _T_748 = bits(_WIRE_53, 0, 0) connect _WIRE_52.fragmented_superpage, _T_748 node _T_749 = bits(_WIRE_53, 1, 1) connect _WIRE_52.c, _T_749 node _T_750 = bits(_WIRE_53, 2, 2) connect _WIRE_52.eff, _T_750 node _T_751 = bits(_WIRE_53, 3, 3) connect _WIRE_52.paa, _T_751 node _T_752 = bits(_WIRE_53, 4, 4) connect _WIRE_52.pal, _T_752 node _T_753 = bits(_WIRE_53, 5, 5) connect _WIRE_52.ppp, _T_753 node _T_754 = bits(_WIRE_53, 6, 6) connect _WIRE_52.pr, _T_754 node _T_755 = bits(_WIRE_53, 7, 7) connect _WIRE_52.px, _T_755 node _T_756 = bits(_WIRE_53, 8, 8) connect _WIRE_52.pw, _T_756 node _T_757 = bits(_WIRE_53, 9, 9) connect _WIRE_52.hr, _T_757 node _T_758 = bits(_WIRE_53, 10, 10) connect _WIRE_52.hx, _T_758 node _T_759 = bits(_WIRE_53, 11, 11) connect _WIRE_52.hw, _T_759 node _T_760 = bits(_WIRE_53, 12, 12) connect _WIRE_52.sr, _T_760 node _T_761 = bits(_WIRE_53, 13, 13) connect _WIRE_52.sx, _T_761 node _T_762 = bits(_WIRE_53, 14, 14) connect _WIRE_52.sw, _T_762 node _T_763 = bits(_WIRE_53, 15, 15) connect _WIRE_52.gf, _T_763 node _T_764 = bits(_WIRE_53, 16, 16) connect _WIRE_52.pf, _T_764 node _T_765 = bits(_WIRE_53, 17, 17) connect _WIRE_52.ae_stage2, _T_765 node _T_766 = bits(_WIRE_53, 18, 18) connect _WIRE_52.ae_final, _T_766 node _T_767 = bits(_WIRE_53, 19, 19) connect _WIRE_52.ae_ptw, _T_767 node _T_768 = bits(_WIRE_53, 20, 20) connect _WIRE_52.g, _T_768 node _T_769 = bits(_WIRE_53, 21, 21) connect _WIRE_52.u, _T_769 node _T_770 = bits(_WIRE_53, 41, 22) connect _WIRE_52.ppn, _T_770 wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_55 : UInt<42> connect _WIRE_55, sectored_entries[0][1].data[3] node _T_771 = bits(_WIRE_55, 0, 0) connect _WIRE_54.fragmented_superpage, _T_771 node _T_772 = bits(_WIRE_55, 1, 1) connect _WIRE_54.c, _T_772 node _T_773 = bits(_WIRE_55, 2, 2) connect _WIRE_54.eff, _T_773 node _T_774 = bits(_WIRE_55, 3, 3) connect _WIRE_54.paa, _T_774 node _T_775 = bits(_WIRE_55, 4, 4) connect _WIRE_54.pal, _T_775 node _T_776 = bits(_WIRE_55, 5, 5) connect _WIRE_54.ppp, _T_776 node _T_777 = bits(_WIRE_55, 6, 6) connect _WIRE_54.pr, _T_777 node _T_778 = bits(_WIRE_55, 7, 7) connect _WIRE_54.px, _T_778 node _T_779 = bits(_WIRE_55, 8, 8) connect _WIRE_54.pw, _T_779 node _T_780 = bits(_WIRE_55, 9, 9) connect _WIRE_54.hr, _T_780 node _T_781 = bits(_WIRE_55, 10, 10) connect _WIRE_54.hx, _T_781 node _T_782 = bits(_WIRE_55, 11, 11) connect _WIRE_54.hw, _T_782 node _T_783 = bits(_WIRE_55, 12, 12) connect _WIRE_54.sr, _T_783 node _T_784 = bits(_WIRE_55, 13, 13) connect _WIRE_54.sx, _T_784 node _T_785 = bits(_WIRE_55, 14, 14) connect _WIRE_54.sw, _T_785 node _T_786 = bits(_WIRE_55, 15, 15) connect _WIRE_54.gf, _T_786 node _T_787 = bits(_WIRE_55, 16, 16) connect _WIRE_54.pf, _T_787 node _T_788 = bits(_WIRE_55, 17, 17) connect _WIRE_54.ae_stage2, _T_788 node _T_789 = bits(_WIRE_55, 18, 18) connect _WIRE_54.ae_final, _T_789 node _T_790 = bits(_WIRE_55, 19, 19) connect _WIRE_54.ae_ptw, _T_790 node _T_791 = bits(_WIRE_55, 20, 20) connect _WIRE_54.g, _T_791 node _T_792 = bits(_WIRE_55, 21, 21) connect _WIRE_54.u, _T_792 node _T_793 = bits(_WIRE_55, 41, 22) connect _WIRE_54.ppn, _T_793 node _T_794 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_795 = eq(_WIRE_48.g, UInt<1>(0h0)) node _T_796 = and(_T_794, _T_795) when _T_796 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_797 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_798 = eq(_WIRE_50.g, UInt<1>(0h0)) node _T_799 = and(_T_797, _T_798) when _T_799 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_800 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_801 = eq(_WIRE_52.g, UInt<1>(0h0)) node _T_802 = and(_T_800, _T_801) when _T_802 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_803 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_804 = eq(_WIRE_54.g, UInt<1>(0h0)) node _T_805 = and(_T_803, _T_804) when _T_805 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_806 = or(hv_1, hg_1) wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_57 : UInt<42> connect _WIRE_57, sectored_entries[0][1].data[0] node _T_807 = bits(_WIRE_57, 0, 0) connect _WIRE_56.fragmented_superpage, _T_807 node _T_808 = bits(_WIRE_57, 1, 1) connect _WIRE_56.c, _T_808 node _T_809 = bits(_WIRE_57, 2, 2) connect _WIRE_56.eff, _T_809 node _T_810 = bits(_WIRE_57, 3, 3) connect _WIRE_56.paa, _T_810 node _T_811 = bits(_WIRE_57, 4, 4) connect _WIRE_56.pal, _T_811 node _T_812 = bits(_WIRE_57, 5, 5) connect _WIRE_56.ppp, _T_812 node _T_813 = bits(_WIRE_57, 6, 6) connect _WIRE_56.pr, _T_813 node _T_814 = bits(_WIRE_57, 7, 7) connect _WIRE_56.px, _T_814 node _T_815 = bits(_WIRE_57, 8, 8) connect _WIRE_56.pw, _T_815 node _T_816 = bits(_WIRE_57, 9, 9) connect _WIRE_56.hr, _T_816 node _T_817 = bits(_WIRE_57, 10, 10) connect _WIRE_56.hx, _T_817 node _T_818 = bits(_WIRE_57, 11, 11) connect _WIRE_56.hw, _T_818 node _T_819 = bits(_WIRE_57, 12, 12) connect _WIRE_56.sr, _T_819 node _T_820 = bits(_WIRE_57, 13, 13) connect _WIRE_56.sx, _T_820 node _T_821 = bits(_WIRE_57, 14, 14) connect _WIRE_56.sw, _T_821 node _T_822 = bits(_WIRE_57, 15, 15) connect _WIRE_56.gf, _T_822 node _T_823 = bits(_WIRE_57, 16, 16) connect _WIRE_56.pf, _T_823 node _T_824 = bits(_WIRE_57, 17, 17) connect _WIRE_56.ae_stage2, _T_824 node _T_825 = bits(_WIRE_57, 18, 18) connect _WIRE_56.ae_final, _T_825 node _T_826 = bits(_WIRE_57, 19, 19) connect _WIRE_56.ae_ptw, _T_826 node _T_827 = bits(_WIRE_57, 20, 20) connect _WIRE_56.g, _T_827 node _T_828 = bits(_WIRE_57, 21, 21) connect _WIRE_56.u, _T_828 node _T_829 = bits(_WIRE_57, 41, 22) connect _WIRE_56.ppn, _T_829 wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_59 : UInt<42> connect _WIRE_59, sectored_entries[0][1].data[1] node _T_830 = bits(_WIRE_59, 0, 0) connect _WIRE_58.fragmented_superpage, _T_830 node _T_831 = bits(_WIRE_59, 1, 1) connect _WIRE_58.c, _T_831 node _T_832 = bits(_WIRE_59, 2, 2) connect _WIRE_58.eff, _T_832 node _T_833 = bits(_WIRE_59, 3, 3) connect _WIRE_58.paa, _T_833 node _T_834 = bits(_WIRE_59, 4, 4) connect _WIRE_58.pal, _T_834 node _T_835 = bits(_WIRE_59, 5, 5) connect _WIRE_58.ppp, _T_835 node _T_836 = bits(_WIRE_59, 6, 6) connect _WIRE_58.pr, _T_836 node _T_837 = bits(_WIRE_59, 7, 7) connect _WIRE_58.px, _T_837 node _T_838 = bits(_WIRE_59, 8, 8) connect _WIRE_58.pw, _T_838 node _T_839 = bits(_WIRE_59, 9, 9) connect _WIRE_58.hr, _T_839 node _T_840 = bits(_WIRE_59, 10, 10) connect _WIRE_58.hx, _T_840 node _T_841 = bits(_WIRE_59, 11, 11) connect _WIRE_58.hw, _T_841 node _T_842 = bits(_WIRE_59, 12, 12) connect _WIRE_58.sr, _T_842 node _T_843 = bits(_WIRE_59, 13, 13) connect _WIRE_58.sx, _T_843 node _T_844 = bits(_WIRE_59, 14, 14) connect _WIRE_58.sw, _T_844 node _T_845 = bits(_WIRE_59, 15, 15) connect _WIRE_58.gf, _T_845 node _T_846 = bits(_WIRE_59, 16, 16) connect _WIRE_58.pf, _T_846 node _T_847 = bits(_WIRE_59, 17, 17) connect _WIRE_58.ae_stage2, _T_847 node _T_848 = bits(_WIRE_59, 18, 18) connect _WIRE_58.ae_final, _T_848 node _T_849 = bits(_WIRE_59, 19, 19) connect _WIRE_58.ae_ptw, _T_849 node _T_850 = bits(_WIRE_59, 20, 20) connect _WIRE_58.g, _T_850 node _T_851 = bits(_WIRE_59, 21, 21) connect _WIRE_58.u, _T_851 node _T_852 = bits(_WIRE_59, 41, 22) connect _WIRE_58.ppn, _T_852 wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_61 : UInt<42> connect _WIRE_61, sectored_entries[0][1].data[2] node _T_853 = bits(_WIRE_61, 0, 0) connect _WIRE_60.fragmented_superpage, _T_853 node _T_854 = bits(_WIRE_61, 1, 1) connect _WIRE_60.c, _T_854 node _T_855 = bits(_WIRE_61, 2, 2) connect _WIRE_60.eff, _T_855 node _T_856 = bits(_WIRE_61, 3, 3) connect _WIRE_60.paa, _T_856 node _T_857 = bits(_WIRE_61, 4, 4) connect _WIRE_60.pal, _T_857 node _T_858 = bits(_WIRE_61, 5, 5) connect _WIRE_60.ppp, _T_858 node _T_859 = bits(_WIRE_61, 6, 6) connect _WIRE_60.pr, _T_859 node _T_860 = bits(_WIRE_61, 7, 7) connect _WIRE_60.px, _T_860 node _T_861 = bits(_WIRE_61, 8, 8) connect _WIRE_60.pw, _T_861 node _T_862 = bits(_WIRE_61, 9, 9) connect _WIRE_60.hr, _T_862 node _T_863 = bits(_WIRE_61, 10, 10) connect _WIRE_60.hx, _T_863 node _T_864 = bits(_WIRE_61, 11, 11) connect _WIRE_60.hw, _T_864 node _T_865 = bits(_WIRE_61, 12, 12) connect _WIRE_60.sr, _T_865 node _T_866 = bits(_WIRE_61, 13, 13) connect _WIRE_60.sx, _T_866 node _T_867 = bits(_WIRE_61, 14, 14) connect _WIRE_60.sw, _T_867 node _T_868 = bits(_WIRE_61, 15, 15) connect _WIRE_60.gf, _T_868 node _T_869 = bits(_WIRE_61, 16, 16) connect _WIRE_60.pf, _T_869 node _T_870 = bits(_WIRE_61, 17, 17) connect _WIRE_60.ae_stage2, _T_870 node _T_871 = bits(_WIRE_61, 18, 18) connect _WIRE_60.ae_final, _T_871 node _T_872 = bits(_WIRE_61, 19, 19) connect _WIRE_60.ae_ptw, _T_872 node _T_873 = bits(_WIRE_61, 20, 20) connect _WIRE_60.g, _T_873 node _T_874 = bits(_WIRE_61, 21, 21) connect _WIRE_60.u, _T_874 node _T_875 = bits(_WIRE_61, 41, 22) connect _WIRE_60.ppn, _T_875 wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_63 : UInt<42> connect _WIRE_63, sectored_entries[0][1].data[3] node _T_876 = bits(_WIRE_63, 0, 0) connect _WIRE_62.fragmented_superpage, _T_876 node _T_877 = bits(_WIRE_63, 1, 1) connect _WIRE_62.c, _T_877 node _T_878 = bits(_WIRE_63, 2, 2) connect _WIRE_62.eff, _T_878 node _T_879 = bits(_WIRE_63, 3, 3) connect _WIRE_62.paa, _T_879 node _T_880 = bits(_WIRE_63, 4, 4) connect _WIRE_62.pal, _T_880 node _T_881 = bits(_WIRE_63, 5, 5) connect _WIRE_62.ppp, _T_881 node _T_882 = bits(_WIRE_63, 6, 6) connect _WIRE_62.pr, _T_882 node _T_883 = bits(_WIRE_63, 7, 7) connect _WIRE_62.px, _T_883 node _T_884 = bits(_WIRE_63, 8, 8) connect _WIRE_62.pw, _T_884 node _T_885 = bits(_WIRE_63, 9, 9) connect _WIRE_62.hr, _T_885 node _T_886 = bits(_WIRE_63, 10, 10) connect _WIRE_62.hx, _T_886 node _T_887 = bits(_WIRE_63, 11, 11) connect _WIRE_62.hw, _T_887 node _T_888 = bits(_WIRE_63, 12, 12) connect _WIRE_62.sr, _T_888 node _T_889 = bits(_WIRE_63, 13, 13) connect _WIRE_62.sx, _T_889 node _T_890 = bits(_WIRE_63, 14, 14) connect _WIRE_62.sw, _T_890 node _T_891 = bits(_WIRE_63, 15, 15) connect _WIRE_62.gf, _T_891 node _T_892 = bits(_WIRE_63, 16, 16) connect _WIRE_62.pf, _T_892 node _T_893 = bits(_WIRE_63, 17, 17) connect _WIRE_62.ae_stage2, _T_893 node _T_894 = bits(_WIRE_63, 18, 18) connect _WIRE_62.ae_final, _T_894 node _T_895 = bits(_WIRE_63, 19, 19) connect _WIRE_62.ae_ptw, _T_895 node _T_896 = bits(_WIRE_63, 20, 20) connect _WIRE_62.g, _T_896 node _T_897 = bits(_WIRE_63, 21, 21) connect _WIRE_62.u, _T_897 node _T_898 = bits(_WIRE_63, 41, 22) connect _WIRE_62.ppn, _T_898 node _T_899 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_899 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_900 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_900 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_901 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_901 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_902 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_902 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_903 = eq(hg_2, UInt<1>(0h0)) node _T_904 = and(_T_903, io.sfence.bits.rs1) when _T_904 : node _T_905 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_906 = shr(_T_905, 2) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_909 = and(_T_907, _T_908) when _T_909 : wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_65 : UInt<42> connect _WIRE_65, sectored_entries[0][2].data[0] node _T_910 = bits(_WIRE_65, 0, 0) connect _WIRE_64.fragmented_superpage, _T_910 node _T_911 = bits(_WIRE_65, 1, 1) connect _WIRE_64.c, _T_911 node _T_912 = bits(_WIRE_65, 2, 2) connect _WIRE_64.eff, _T_912 node _T_913 = bits(_WIRE_65, 3, 3) connect _WIRE_64.paa, _T_913 node _T_914 = bits(_WIRE_65, 4, 4) connect _WIRE_64.pal, _T_914 node _T_915 = bits(_WIRE_65, 5, 5) connect _WIRE_64.ppp, _T_915 node _T_916 = bits(_WIRE_65, 6, 6) connect _WIRE_64.pr, _T_916 node _T_917 = bits(_WIRE_65, 7, 7) connect _WIRE_64.px, _T_917 node _T_918 = bits(_WIRE_65, 8, 8) connect _WIRE_64.pw, _T_918 node _T_919 = bits(_WIRE_65, 9, 9) connect _WIRE_64.hr, _T_919 node _T_920 = bits(_WIRE_65, 10, 10) connect _WIRE_64.hx, _T_920 node _T_921 = bits(_WIRE_65, 11, 11) connect _WIRE_64.hw, _T_921 node _T_922 = bits(_WIRE_65, 12, 12) connect _WIRE_64.sr, _T_922 node _T_923 = bits(_WIRE_65, 13, 13) connect _WIRE_64.sx, _T_923 node _T_924 = bits(_WIRE_65, 14, 14) connect _WIRE_64.sw, _T_924 node _T_925 = bits(_WIRE_65, 15, 15) connect _WIRE_64.gf, _T_925 node _T_926 = bits(_WIRE_65, 16, 16) connect _WIRE_64.pf, _T_926 node _T_927 = bits(_WIRE_65, 17, 17) connect _WIRE_64.ae_stage2, _T_927 node _T_928 = bits(_WIRE_65, 18, 18) connect _WIRE_64.ae_final, _T_928 node _T_929 = bits(_WIRE_65, 19, 19) connect _WIRE_64.ae_ptw, _T_929 node _T_930 = bits(_WIRE_65, 20, 20) connect _WIRE_64.g, _T_930 node _T_931 = bits(_WIRE_65, 21, 21) connect _WIRE_64.u, _T_931 node _T_932 = bits(_WIRE_65, 41, 22) connect _WIRE_64.ppn, _T_932 wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_67 : UInt<42> connect _WIRE_67, sectored_entries[0][2].data[1] node _T_933 = bits(_WIRE_67, 0, 0) connect _WIRE_66.fragmented_superpage, _T_933 node _T_934 = bits(_WIRE_67, 1, 1) connect _WIRE_66.c, _T_934 node _T_935 = bits(_WIRE_67, 2, 2) connect _WIRE_66.eff, _T_935 node _T_936 = bits(_WIRE_67, 3, 3) connect _WIRE_66.paa, _T_936 node _T_937 = bits(_WIRE_67, 4, 4) connect _WIRE_66.pal, _T_937 node _T_938 = bits(_WIRE_67, 5, 5) connect _WIRE_66.ppp, _T_938 node _T_939 = bits(_WIRE_67, 6, 6) connect _WIRE_66.pr, _T_939 node _T_940 = bits(_WIRE_67, 7, 7) connect _WIRE_66.px, _T_940 node _T_941 = bits(_WIRE_67, 8, 8) connect _WIRE_66.pw, _T_941 node _T_942 = bits(_WIRE_67, 9, 9) connect _WIRE_66.hr, _T_942 node _T_943 = bits(_WIRE_67, 10, 10) connect _WIRE_66.hx, _T_943 node _T_944 = bits(_WIRE_67, 11, 11) connect _WIRE_66.hw, _T_944 node _T_945 = bits(_WIRE_67, 12, 12) connect _WIRE_66.sr, _T_945 node _T_946 = bits(_WIRE_67, 13, 13) connect _WIRE_66.sx, _T_946 node _T_947 = bits(_WIRE_67, 14, 14) connect _WIRE_66.sw, _T_947 node _T_948 = bits(_WIRE_67, 15, 15) connect _WIRE_66.gf, _T_948 node _T_949 = bits(_WIRE_67, 16, 16) connect _WIRE_66.pf, _T_949 node _T_950 = bits(_WIRE_67, 17, 17) connect _WIRE_66.ae_stage2, _T_950 node _T_951 = bits(_WIRE_67, 18, 18) connect _WIRE_66.ae_final, _T_951 node _T_952 = bits(_WIRE_67, 19, 19) connect _WIRE_66.ae_ptw, _T_952 node _T_953 = bits(_WIRE_67, 20, 20) connect _WIRE_66.g, _T_953 node _T_954 = bits(_WIRE_67, 21, 21) connect _WIRE_66.u, _T_954 node _T_955 = bits(_WIRE_67, 41, 22) connect _WIRE_66.ppn, _T_955 wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_69 : UInt<42> connect _WIRE_69, sectored_entries[0][2].data[2] node _T_956 = bits(_WIRE_69, 0, 0) connect _WIRE_68.fragmented_superpage, _T_956 node _T_957 = bits(_WIRE_69, 1, 1) connect _WIRE_68.c, _T_957 node _T_958 = bits(_WIRE_69, 2, 2) connect _WIRE_68.eff, _T_958 node _T_959 = bits(_WIRE_69, 3, 3) connect _WIRE_68.paa, _T_959 node _T_960 = bits(_WIRE_69, 4, 4) connect _WIRE_68.pal, _T_960 node _T_961 = bits(_WIRE_69, 5, 5) connect _WIRE_68.ppp, _T_961 node _T_962 = bits(_WIRE_69, 6, 6) connect _WIRE_68.pr, _T_962 node _T_963 = bits(_WIRE_69, 7, 7) connect _WIRE_68.px, _T_963 node _T_964 = bits(_WIRE_69, 8, 8) connect _WIRE_68.pw, _T_964 node _T_965 = bits(_WIRE_69, 9, 9) connect _WIRE_68.hr, _T_965 node _T_966 = bits(_WIRE_69, 10, 10) connect _WIRE_68.hx, _T_966 node _T_967 = bits(_WIRE_69, 11, 11) connect _WIRE_68.hw, _T_967 node _T_968 = bits(_WIRE_69, 12, 12) connect _WIRE_68.sr, _T_968 node _T_969 = bits(_WIRE_69, 13, 13) connect _WIRE_68.sx, _T_969 node _T_970 = bits(_WIRE_69, 14, 14) connect _WIRE_68.sw, _T_970 node _T_971 = bits(_WIRE_69, 15, 15) connect _WIRE_68.gf, _T_971 node _T_972 = bits(_WIRE_69, 16, 16) connect _WIRE_68.pf, _T_972 node _T_973 = bits(_WIRE_69, 17, 17) connect _WIRE_68.ae_stage2, _T_973 node _T_974 = bits(_WIRE_69, 18, 18) connect _WIRE_68.ae_final, _T_974 node _T_975 = bits(_WIRE_69, 19, 19) connect _WIRE_68.ae_ptw, _T_975 node _T_976 = bits(_WIRE_69, 20, 20) connect _WIRE_68.g, _T_976 node _T_977 = bits(_WIRE_69, 21, 21) connect _WIRE_68.u, _T_977 node _T_978 = bits(_WIRE_69, 41, 22) connect _WIRE_68.ppn, _T_978 wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_71 : UInt<42> connect _WIRE_71, sectored_entries[0][2].data[3] node _T_979 = bits(_WIRE_71, 0, 0) connect _WIRE_70.fragmented_superpage, _T_979 node _T_980 = bits(_WIRE_71, 1, 1) connect _WIRE_70.c, _T_980 node _T_981 = bits(_WIRE_71, 2, 2) connect _WIRE_70.eff, _T_981 node _T_982 = bits(_WIRE_71, 3, 3) connect _WIRE_70.paa, _T_982 node _T_983 = bits(_WIRE_71, 4, 4) connect _WIRE_70.pal, _T_983 node _T_984 = bits(_WIRE_71, 5, 5) connect _WIRE_70.ppp, _T_984 node _T_985 = bits(_WIRE_71, 6, 6) connect _WIRE_70.pr, _T_985 node _T_986 = bits(_WIRE_71, 7, 7) connect _WIRE_70.px, _T_986 node _T_987 = bits(_WIRE_71, 8, 8) connect _WIRE_70.pw, _T_987 node _T_988 = bits(_WIRE_71, 9, 9) connect _WIRE_70.hr, _T_988 node _T_989 = bits(_WIRE_71, 10, 10) connect _WIRE_70.hx, _T_989 node _T_990 = bits(_WIRE_71, 11, 11) connect _WIRE_70.hw, _T_990 node _T_991 = bits(_WIRE_71, 12, 12) connect _WIRE_70.sr, _T_991 node _T_992 = bits(_WIRE_71, 13, 13) connect _WIRE_70.sx, _T_992 node _T_993 = bits(_WIRE_71, 14, 14) connect _WIRE_70.sw, _T_993 node _T_994 = bits(_WIRE_71, 15, 15) connect _WIRE_70.gf, _T_994 node _T_995 = bits(_WIRE_71, 16, 16) connect _WIRE_70.pf, _T_995 node _T_996 = bits(_WIRE_71, 17, 17) connect _WIRE_70.ae_stage2, _T_996 node _T_997 = bits(_WIRE_71, 18, 18) connect _WIRE_70.ae_final, _T_997 node _T_998 = bits(_WIRE_71, 19, 19) connect _WIRE_70.ae_ptw, _T_998 node _T_999 = bits(_WIRE_71, 20, 20) connect _WIRE_70.g, _T_999 node _T_1000 = bits(_WIRE_71, 21, 21) connect _WIRE_70.u, _T_1000 node _T_1001 = bits(_WIRE_71, 41, 22) connect _WIRE_70.ppn, _T_1001 node _T_1002 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1003 = bits(vpn, 1, 0) node _T_1004 = eq(UInt<1>(0h0), _T_1003) node _T_1005 = and(_T_1002, _T_1004) when _T_1005 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1006 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1007 = bits(vpn, 1, 0) node _T_1008 = eq(UInt<1>(0h1), _T_1007) node _T_1009 = and(_T_1006, _T_1008) when _T_1009 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1010 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1011 = bits(vpn, 1, 0) node _T_1012 = eq(UInt<2>(0h2), _T_1011) node _T_1013 = and(_T_1010, _T_1012) when _T_1013 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1014 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1015 = bits(vpn, 1, 0) node _T_1016 = eq(UInt<2>(0h3), _T_1015) node _T_1017 = and(_T_1014, _T_1016) when _T_1017 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_1018 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_1019 = shr(_T_1018, 18) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_73 : UInt<42> connect _WIRE_73, sectored_entries[0][2].data[0] node _T_1021 = bits(_WIRE_73, 0, 0) connect _WIRE_72.fragmented_superpage, _T_1021 node _T_1022 = bits(_WIRE_73, 1, 1) connect _WIRE_72.c, _T_1022 node _T_1023 = bits(_WIRE_73, 2, 2) connect _WIRE_72.eff, _T_1023 node _T_1024 = bits(_WIRE_73, 3, 3) connect _WIRE_72.paa, _T_1024 node _T_1025 = bits(_WIRE_73, 4, 4) connect _WIRE_72.pal, _T_1025 node _T_1026 = bits(_WIRE_73, 5, 5) connect _WIRE_72.ppp, _T_1026 node _T_1027 = bits(_WIRE_73, 6, 6) connect _WIRE_72.pr, _T_1027 node _T_1028 = bits(_WIRE_73, 7, 7) connect _WIRE_72.px, _T_1028 node _T_1029 = bits(_WIRE_73, 8, 8) connect _WIRE_72.pw, _T_1029 node _T_1030 = bits(_WIRE_73, 9, 9) connect _WIRE_72.hr, _T_1030 node _T_1031 = bits(_WIRE_73, 10, 10) connect _WIRE_72.hx, _T_1031 node _T_1032 = bits(_WIRE_73, 11, 11) connect _WIRE_72.hw, _T_1032 node _T_1033 = bits(_WIRE_73, 12, 12) connect _WIRE_72.sr, _T_1033 node _T_1034 = bits(_WIRE_73, 13, 13) connect _WIRE_72.sx, _T_1034 node _T_1035 = bits(_WIRE_73, 14, 14) connect _WIRE_72.sw, _T_1035 node _T_1036 = bits(_WIRE_73, 15, 15) connect _WIRE_72.gf, _T_1036 node _T_1037 = bits(_WIRE_73, 16, 16) connect _WIRE_72.pf, _T_1037 node _T_1038 = bits(_WIRE_73, 17, 17) connect _WIRE_72.ae_stage2, _T_1038 node _T_1039 = bits(_WIRE_73, 18, 18) connect _WIRE_72.ae_final, _T_1039 node _T_1040 = bits(_WIRE_73, 19, 19) connect _WIRE_72.ae_ptw, _T_1040 node _T_1041 = bits(_WIRE_73, 20, 20) connect _WIRE_72.g, _T_1041 node _T_1042 = bits(_WIRE_73, 21, 21) connect _WIRE_72.u, _T_1042 node _T_1043 = bits(_WIRE_73, 41, 22) connect _WIRE_72.ppn, _T_1043 wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_75 : UInt<42> connect _WIRE_75, sectored_entries[0][2].data[1] node _T_1044 = bits(_WIRE_75, 0, 0) connect _WIRE_74.fragmented_superpage, _T_1044 node _T_1045 = bits(_WIRE_75, 1, 1) connect _WIRE_74.c, _T_1045 node _T_1046 = bits(_WIRE_75, 2, 2) connect _WIRE_74.eff, _T_1046 node _T_1047 = bits(_WIRE_75, 3, 3) connect _WIRE_74.paa, _T_1047 node _T_1048 = bits(_WIRE_75, 4, 4) connect _WIRE_74.pal, _T_1048 node _T_1049 = bits(_WIRE_75, 5, 5) connect _WIRE_74.ppp, _T_1049 node _T_1050 = bits(_WIRE_75, 6, 6) connect _WIRE_74.pr, _T_1050 node _T_1051 = bits(_WIRE_75, 7, 7) connect _WIRE_74.px, _T_1051 node _T_1052 = bits(_WIRE_75, 8, 8) connect _WIRE_74.pw, _T_1052 node _T_1053 = bits(_WIRE_75, 9, 9) connect _WIRE_74.hr, _T_1053 node _T_1054 = bits(_WIRE_75, 10, 10) connect _WIRE_74.hx, _T_1054 node _T_1055 = bits(_WIRE_75, 11, 11) connect _WIRE_74.hw, _T_1055 node _T_1056 = bits(_WIRE_75, 12, 12) connect _WIRE_74.sr, _T_1056 node _T_1057 = bits(_WIRE_75, 13, 13) connect _WIRE_74.sx, _T_1057 node _T_1058 = bits(_WIRE_75, 14, 14) connect _WIRE_74.sw, _T_1058 node _T_1059 = bits(_WIRE_75, 15, 15) connect _WIRE_74.gf, _T_1059 node _T_1060 = bits(_WIRE_75, 16, 16) connect _WIRE_74.pf, _T_1060 node _T_1061 = bits(_WIRE_75, 17, 17) connect _WIRE_74.ae_stage2, _T_1061 node _T_1062 = bits(_WIRE_75, 18, 18) connect _WIRE_74.ae_final, _T_1062 node _T_1063 = bits(_WIRE_75, 19, 19) connect _WIRE_74.ae_ptw, _T_1063 node _T_1064 = bits(_WIRE_75, 20, 20) connect _WIRE_74.g, _T_1064 node _T_1065 = bits(_WIRE_75, 21, 21) connect _WIRE_74.u, _T_1065 node _T_1066 = bits(_WIRE_75, 41, 22) connect _WIRE_74.ppn, _T_1066 wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_77 : UInt<42> connect _WIRE_77, sectored_entries[0][2].data[2] node _T_1067 = bits(_WIRE_77, 0, 0) connect _WIRE_76.fragmented_superpage, _T_1067 node _T_1068 = bits(_WIRE_77, 1, 1) connect _WIRE_76.c, _T_1068 node _T_1069 = bits(_WIRE_77, 2, 2) connect _WIRE_76.eff, _T_1069 node _T_1070 = bits(_WIRE_77, 3, 3) connect _WIRE_76.paa, _T_1070 node _T_1071 = bits(_WIRE_77, 4, 4) connect _WIRE_76.pal, _T_1071 node _T_1072 = bits(_WIRE_77, 5, 5) connect _WIRE_76.ppp, _T_1072 node _T_1073 = bits(_WIRE_77, 6, 6) connect _WIRE_76.pr, _T_1073 node _T_1074 = bits(_WIRE_77, 7, 7) connect _WIRE_76.px, _T_1074 node _T_1075 = bits(_WIRE_77, 8, 8) connect _WIRE_76.pw, _T_1075 node _T_1076 = bits(_WIRE_77, 9, 9) connect _WIRE_76.hr, _T_1076 node _T_1077 = bits(_WIRE_77, 10, 10) connect _WIRE_76.hx, _T_1077 node _T_1078 = bits(_WIRE_77, 11, 11) connect _WIRE_76.hw, _T_1078 node _T_1079 = bits(_WIRE_77, 12, 12) connect _WIRE_76.sr, _T_1079 node _T_1080 = bits(_WIRE_77, 13, 13) connect _WIRE_76.sx, _T_1080 node _T_1081 = bits(_WIRE_77, 14, 14) connect _WIRE_76.sw, _T_1081 node _T_1082 = bits(_WIRE_77, 15, 15) connect _WIRE_76.gf, _T_1082 node _T_1083 = bits(_WIRE_77, 16, 16) connect _WIRE_76.pf, _T_1083 node _T_1084 = bits(_WIRE_77, 17, 17) connect _WIRE_76.ae_stage2, _T_1084 node _T_1085 = bits(_WIRE_77, 18, 18) connect _WIRE_76.ae_final, _T_1085 node _T_1086 = bits(_WIRE_77, 19, 19) connect _WIRE_76.ae_ptw, _T_1086 node _T_1087 = bits(_WIRE_77, 20, 20) connect _WIRE_76.g, _T_1087 node _T_1088 = bits(_WIRE_77, 21, 21) connect _WIRE_76.u, _T_1088 node _T_1089 = bits(_WIRE_77, 41, 22) connect _WIRE_76.ppn, _T_1089 wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_79 : UInt<42> connect _WIRE_79, sectored_entries[0][2].data[3] node _T_1090 = bits(_WIRE_79, 0, 0) connect _WIRE_78.fragmented_superpage, _T_1090 node _T_1091 = bits(_WIRE_79, 1, 1) connect _WIRE_78.c, _T_1091 node _T_1092 = bits(_WIRE_79, 2, 2) connect _WIRE_78.eff, _T_1092 node _T_1093 = bits(_WIRE_79, 3, 3) connect _WIRE_78.paa, _T_1093 node _T_1094 = bits(_WIRE_79, 4, 4) connect _WIRE_78.pal, _T_1094 node _T_1095 = bits(_WIRE_79, 5, 5) connect _WIRE_78.ppp, _T_1095 node _T_1096 = bits(_WIRE_79, 6, 6) connect _WIRE_78.pr, _T_1096 node _T_1097 = bits(_WIRE_79, 7, 7) connect _WIRE_78.px, _T_1097 node _T_1098 = bits(_WIRE_79, 8, 8) connect _WIRE_78.pw, _T_1098 node _T_1099 = bits(_WIRE_79, 9, 9) connect _WIRE_78.hr, _T_1099 node _T_1100 = bits(_WIRE_79, 10, 10) connect _WIRE_78.hx, _T_1100 node _T_1101 = bits(_WIRE_79, 11, 11) connect _WIRE_78.hw, _T_1101 node _T_1102 = bits(_WIRE_79, 12, 12) connect _WIRE_78.sr, _T_1102 node _T_1103 = bits(_WIRE_79, 13, 13) connect _WIRE_78.sx, _T_1103 node _T_1104 = bits(_WIRE_79, 14, 14) connect _WIRE_78.sw, _T_1104 node _T_1105 = bits(_WIRE_79, 15, 15) connect _WIRE_78.gf, _T_1105 node _T_1106 = bits(_WIRE_79, 16, 16) connect _WIRE_78.pf, _T_1106 node _T_1107 = bits(_WIRE_79, 17, 17) connect _WIRE_78.ae_stage2, _T_1107 node _T_1108 = bits(_WIRE_79, 18, 18) connect _WIRE_78.ae_final, _T_1108 node _T_1109 = bits(_WIRE_79, 19, 19) connect _WIRE_78.ae_ptw, _T_1109 node _T_1110 = bits(_WIRE_79, 20, 20) connect _WIRE_78.g, _T_1110 node _T_1111 = bits(_WIRE_79, 21, 21) connect _WIRE_78.u, _T_1111 node _T_1112 = bits(_WIRE_79, 41, 22) connect _WIRE_78.ppn, _T_1112 node _T_1113 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1114 = and(_T_1113, _WIRE_72.fragmented_superpage) when _T_1114 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1115 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1116 = and(_T_1115, _WIRE_74.fragmented_superpage) when _T_1116 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1117 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1118 = and(_T_1117, _WIRE_76.fragmented_superpage) when _T_1118 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1119 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1120 = and(_T_1119, _WIRE_78.fragmented_superpage) when _T_1120 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1121 = eq(hg_2, UInt<1>(0h0)) node _T_1122 = and(_T_1121, io.sfence.bits.rs2) when _T_1122 : wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_81 : UInt<42> connect _WIRE_81, sectored_entries[0][2].data[0] node _T_1123 = bits(_WIRE_81, 0, 0) connect _WIRE_80.fragmented_superpage, _T_1123 node _T_1124 = bits(_WIRE_81, 1, 1) connect _WIRE_80.c, _T_1124 node _T_1125 = bits(_WIRE_81, 2, 2) connect _WIRE_80.eff, _T_1125 node _T_1126 = bits(_WIRE_81, 3, 3) connect _WIRE_80.paa, _T_1126 node _T_1127 = bits(_WIRE_81, 4, 4) connect _WIRE_80.pal, _T_1127 node _T_1128 = bits(_WIRE_81, 5, 5) connect _WIRE_80.ppp, _T_1128 node _T_1129 = bits(_WIRE_81, 6, 6) connect _WIRE_80.pr, _T_1129 node _T_1130 = bits(_WIRE_81, 7, 7) connect _WIRE_80.px, _T_1130 node _T_1131 = bits(_WIRE_81, 8, 8) connect _WIRE_80.pw, _T_1131 node _T_1132 = bits(_WIRE_81, 9, 9) connect _WIRE_80.hr, _T_1132 node _T_1133 = bits(_WIRE_81, 10, 10) connect _WIRE_80.hx, _T_1133 node _T_1134 = bits(_WIRE_81, 11, 11) connect _WIRE_80.hw, _T_1134 node _T_1135 = bits(_WIRE_81, 12, 12) connect _WIRE_80.sr, _T_1135 node _T_1136 = bits(_WIRE_81, 13, 13) connect _WIRE_80.sx, _T_1136 node _T_1137 = bits(_WIRE_81, 14, 14) connect _WIRE_80.sw, _T_1137 node _T_1138 = bits(_WIRE_81, 15, 15) connect _WIRE_80.gf, _T_1138 node _T_1139 = bits(_WIRE_81, 16, 16) connect _WIRE_80.pf, _T_1139 node _T_1140 = bits(_WIRE_81, 17, 17) connect _WIRE_80.ae_stage2, _T_1140 node _T_1141 = bits(_WIRE_81, 18, 18) connect _WIRE_80.ae_final, _T_1141 node _T_1142 = bits(_WIRE_81, 19, 19) connect _WIRE_80.ae_ptw, _T_1142 node _T_1143 = bits(_WIRE_81, 20, 20) connect _WIRE_80.g, _T_1143 node _T_1144 = bits(_WIRE_81, 21, 21) connect _WIRE_80.u, _T_1144 node _T_1145 = bits(_WIRE_81, 41, 22) connect _WIRE_80.ppn, _T_1145 wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_83 : UInt<42> connect _WIRE_83, sectored_entries[0][2].data[1] node _T_1146 = bits(_WIRE_83, 0, 0) connect _WIRE_82.fragmented_superpage, _T_1146 node _T_1147 = bits(_WIRE_83, 1, 1) connect _WIRE_82.c, _T_1147 node _T_1148 = bits(_WIRE_83, 2, 2) connect _WIRE_82.eff, _T_1148 node _T_1149 = bits(_WIRE_83, 3, 3) connect _WIRE_82.paa, _T_1149 node _T_1150 = bits(_WIRE_83, 4, 4) connect _WIRE_82.pal, _T_1150 node _T_1151 = bits(_WIRE_83, 5, 5) connect _WIRE_82.ppp, _T_1151 node _T_1152 = bits(_WIRE_83, 6, 6) connect _WIRE_82.pr, _T_1152 node _T_1153 = bits(_WIRE_83, 7, 7) connect _WIRE_82.px, _T_1153 node _T_1154 = bits(_WIRE_83, 8, 8) connect _WIRE_82.pw, _T_1154 node _T_1155 = bits(_WIRE_83, 9, 9) connect _WIRE_82.hr, _T_1155 node _T_1156 = bits(_WIRE_83, 10, 10) connect _WIRE_82.hx, _T_1156 node _T_1157 = bits(_WIRE_83, 11, 11) connect _WIRE_82.hw, _T_1157 node _T_1158 = bits(_WIRE_83, 12, 12) connect _WIRE_82.sr, _T_1158 node _T_1159 = bits(_WIRE_83, 13, 13) connect _WIRE_82.sx, _T_1159 node _T_1160 = bits(_WIRE_83, 14, 14) connect _WIRE_82.sw, _T_1160 node _T_1161 = bits(_WIRE_83, 15, 15) connect _WIRE_82.gf, _T_1161 node _T_1162 = bits(_WIRE_83, 16, 16) connect _WIRE_82.pf, _T_1162 node _T_1163 = bits(_WIRE_83, 17, 17) connect _WIRE_82.ae_stage2, _T_1163 node _T_1164 = bits(_WIRE_83, 18, 18) connect _WIRE_82.ae_final, _T_1164 node _T_1165 = bits(_WIRE_83, 19, 19) connect _WIRE_82.ae_ptw, _T_1165 node _T_1166 = bits(_WIRE_83, 20, 20) connect _WIRE_82.g, _T_1166 node _T_1167 = bits(_WIRE_83, 21, 21) connect _WIRE_82.u, _T_1167 node _T_1168 = bits(_WIRE_83, 41, 22) connect _WIRE_82.ppn, _T_1168 wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_85 : UInt<42> connect _WIRE_85, sectored_entries[0][2].data[2] node _T_1169 = bits(_WIRE_85, 0, 0) connect _WIRE_84.fragmented_superpage, _T_1169 node _T_1170 = bits(_WIRE_85, 1, 1) connect _WIRE_84.c, _T_1170 node _T_1171 = bits(_WIRE_85, 2, 2) connect _WIRE_84.eff, _T_1171 node _T_1172 = bits(_WIRE_85, 3, 3) connect _WIRE_84.paa, _T_1172 node _T_1173 = bits(_WIRE_85, 4, 4) connect _WIRE_84.pal, _T_1173 node _T_1174 = bits(_WIRE_85, 5, 5) connect _WIRE_84.ppp, _T_1174 node _T_1175 = bits(_WIRE_85, 6, 6) connect _WIRE_84.pr, _T_1175 node _T_1176 = bits(_WIRE_85, 7, 7) connect _WIRE_84.px, _T_1176 node _T_1177 = bits(_WIRE_85, 8, 8) connect _WIRE_84.pw, _T_1177 node _T_1178 = bits(_WIRE_85, 9, 9) connect _WIRE_84.hr, _T_1178 node _T_1179 = bits(_WIRE_85, 10, 10) connect _WIRE_84.hx, _T_1179 node _T_1180 = bits(_WIRE_85, 11, 11) connect _WIRE_84.hw, _T_1180 node _T_1181 = bits(_WIRE_85, 12, 12) connect _WIRE_84.sr, _T_1181 node _T_1182 = bits(_WIRE_85, 13, 13) connect _WIRE_84.sx, _T_1182 node _T_1183 = bits(_WIRE_85, 14, 14) connect _WIRE_84.sw, _T_1183 node _T_1184 = bits(_WIRE_85, 15, 15) connect _WIRE_84.gf, _T_1184 node _T_1185 = bits(_WIRE_85, 16, 16) connect _WIRE_84.pf, _T_1185 node _T_1186 = bits(_WIRE_85, 17, 17) connect _WIRE_84.ae_stage2, _T_1186 node _T_1187 = bits(_WIRE_85, 18, 18) connect _WIRE_84.ae_final, _T_1187 node _T_1188 = bits(_WIRE_85, 19, 19) connect _WIRE_84.ae_ptw, _T_1188 node _T_1189 = bits(_WIRE_85, 20, 20) connect _WIRE_84.g, _T_1189 node _T_1190 = bits(_WIRE_85, 21, 21) connect _WIRE_84.u, _T_1190 node _T_1191 = bits(_WIRE_85, 41, 22) connect _WIRE_84.ppn, _T_1191 wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_87 : UInt<42> connect _WIRE_87, sectored_entries[0][2].data[3] node _T_1192 = bits(_WIRE_87, 0, 0) connect _WIRE_86.fragmented_superpage, _T_1192 node _T_1193 = bits(_WIRE_87, 1, 1) connect _WIRE_86.c, _T_1193 node _T_1194 = bits(_WIRE_87, 2, 2) connect _WIRE_86.eff, _T_1194 node _T_1195 = bits(_WIRE_87, 3, 3) connect _WIRE_86.paa, _T_1195 node _T_1196 = bits(_WIRE_87, 4, 4) connect _WIRE_86.pal, _T_1196 node _T_1197 = bits(_WIRE_87, 5, 5) connect _WIRE_86.ppp, _T_1197 node _T_1198 = bits(_WIRE_87, 6, 6) connect _WIRE_86.pr, _T_1198 node _T_1199 = bits(_WIRE_87, 7, 7) connect _WIRE_86.px, _T_1199 node _T_1200 = bits(_WIRE_87, 8, 8) connect _WIRE_86.pw, _T_1200 node _T_1201 = bits(_WIRE_87, 9, 9) connect _WIRE_86.hr, _T_1201 node _T_1202 = bits(_WIRE_87, 10, 10) connect _WIRE_86.hx, _T_1202 node _T_1203 = bits(_WIRE_87, 11, 11) connect _WIRE_86.hw, _T_1203 node _T_1204 = bits(_WIRE_87, 12, 12) connect _WIRE_86.sr, _T_1204 node _T_1205 = bits(_WIRE_87, 13, 13) connect _WIRE_86.sx, _T_1205 node _T_1206 = bits(_WIRE_87, 14, 14) connect _WIRE_86.sw, _T_1206 node _T_1207 = bits(_WIRE_87, 15, 15) connect _WIRE_86.gf, _T_1207 node _T_1208 = bits(_WIRE_87, 16, 16) connect _WIRE_86.pf, _T_1208 node _T_1209 = bits(_WIRE_87, 17, 17) connect _WIRE_86.ae_stage2, _T_1209 node _T_1210 = bits(_WIRE_87, 18, 18) connect _WIRE_86.ae_final, _T_1210 node _T_1211 = bits(_WIRE_87, 19, 19) connect _WIRE_86.ae_ptw, _T_1211 node _T_1212 = bits(_WIRE_87, 20, 20) connect _WIRE_86.g, _T_1212 node _T_1213 = bits(_WIRE_87, 21, 21) connect _WIRE_86.u, _T_1213 node _T_1214 = bits(_WIRE_87, 41, 22) connect _WIRE_86.ppn, _T_1214 node _T_1215 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1216 = eq(_WIRE_80.g, UInt<1>(0h0)) node _T_1217 = and(_T_1215, _T_1216) when _T_1217 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1218 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1219 = eq(_WIRE_82.g, UInt<1>(0h0)) node _T_1220 = and(_T_1218, _T_1219) when _T_1220 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1221 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1222 = eq(_WIRE_84.g, UInt<1>(0h0)) node _T_1223 = and(_T_1221, _T_1222) when _T_1223 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1224 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1225 = eq(_WIRE_86.g, UInt<1>(0h0)) node _T_1226 = and(_T_1224, _T_1225) when _T_1226 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1227 = or(hv_2, hg_2) wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_89 : UInt<42> connect _WIRE_89, sectored_entries[0][2].data[0] node _T_1228 = bits(_WIRE_89, 0, 0) connect _WIRE_88.fragmented_superpage, _T_1228 node _T_1229 = bits(_WIRE_89, 1, 1) connect _WIRE_88.c, _T_1229 node _T_1230 = bits(_WIRE_89, 2, 2) connect _WIRE_88.eff, _T_1230 node _T_1231 = bits(_WIRE_89, 3, 3) connect _WIRE_88.paa, _T_1231 node _T_1232 = bits(_WIRE_89, 4, 4) connect _WIRE_88.pal, _T_1232 node _T_1233 = bits(_WIRE_89, 5, 5) connect _WIRE_88.ppp, _T_1233 node _T_1234 = bits(_WIRE_89, 6, 6) connect _WIRE_88.pr, _T_1234 node _T_1235 = bits(_WIRE_89, 7, 7) connect _WIRE_88.px, _T_1235 node _T_1236 = bits(_WIRE_89, 8, 8) connect _WIRE_88.pw, _T_1236 node _T_1237 = bits(_WIRE_89, 9, 9) connect _WIRE_88.hr, _T_1237 node _T_1238 = bits(_WIRE_89, 10, 10) connect _WIRE_88.hx, _T_1238 node _T_1239 = bits(_WIRE_89, 11, 11) connect _WIRE_88.hw, _T_1239 node _T_1240 = bits(_WIRE_89, 12, 12) connect _WIRE_88.sr, _T_1240 node _T_1241 = bits(_WIRE_89, 13, 13) connect _WIRE_88.sx, _T_1241 node _T_1242 = bits(_WIRE_89, 14, 14) connect _WIRE_88.sw, _T_1242 node _T_1243 = bits(_WIRE_89, 15, 15) connect _WIRE_88.gf, _T_1243 node _T_1244 = bits(_WIRE_89, 16, 16) connect _WIRE_88.pf, _T_1244 node _T_1245 = bits(_WIRE_89, 17, 17) connect _WIRE_88.ae_stage2, _T_1245 node _T_1246 = bits(_WIRE_89, 18, 18) connect _WIRE_88.ae_final, _T_1246 node _T_1247 = bits(_WIRE_89, 19, 19) connect _WIRE_88.ae_ptw, _T_1247 node _T_1248 = bits(_WIRE_89, 20, 20) connect _WIRE_88.g, _T_1248 node _T_1249 = bits(_WIRE_89, 21, 21) connect _WIRE_88.u, _T_1249 node _T_1250 = bits(_WIRE_89, 41, 22) connect _WIRE_88.ppn, _T_1250 wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_91 : UInt<42> connect _WIRE_91, sectored_entries[0][2].data[1] node _T_1251 = bits(_WIRE_91, 0, 0) connect _WIRE_90.fragmented_superpage, _T_1251 node _T_1252 = bits(_WIRE_91, 1, 1) connect _WIRE_90.c, _T_1252 node _T_1253 = bits(_WIRE_91, 2, 2) connect _WIRE_90.eff, _T_1253 node _T_1254 = bits(_WIRE_91, 3, 3) connect _WIRE_90.paa, _T_1254 node _T_1255 = bits(_WIRE_91, 4, 4) connect _WIRE_90.pal, _T_1255 node _T_1256 = bits(_WIRE_91, 5, 5) connect _WIRE_90.ppp, _T_1256 node _T_1257 = bits(_WIRE_91, 6, 6) connect _WIRE_90.pr, _T_1257 node _T_1258 = bits(_WIRE_91, 7, 7) connect _WIRE_90.px, _T_1258 node _T_1259 = bits(_WIRE_91, 8, 8) connect _WIRE_90.pw, _T_1259 node _T_1260 = bits(_WIRE_91, 9, 9) connect _WIRE_90.hr, _T_1260 node _T_1261 = bits(_WIRE_91, 10, 10) connect _WIRE_90.hx, _T_1261 node _T_1262 = bits(_WIRE_91, 11, 11) connect _WIRE_90.hw, _T_1262 node _T_1263 = bits(_WIRE_91, 12, 12) connect _WIRE_90.sr, _T_1263 node _T_1264 = bits(_WIRE_91, 13, 13) connect _WIRE_90.sx, _T_1264 node _T_1265 = bits(_WIRE_91, 14, 14) connect _WIRE_90.sw, _T_1265 node _T_1266 = bits(_WIRE_91, 15, 15) connect _WIRE_90.gf, _T_1266 node _T_1267 = bits(_WIRE_91, 16, 16) connect _WIRE_90.pf, _T_1267 node _T_1268 = bits(_WIRE_91, 17, 17) connect _WIRE_90.ae_stage2, _T_1268 node _T_1269 = bits(_WIRE_91, 18, 18) connect _WIRE_90.ae_final, _T_1269 node _T_1270 = bits(_WIRE_91, 19, 19) connect _WIRE_90.ae_ptw, _T_1270 node _T_1271 = bits(_WIRE_91, 20, 20) connect _WIRE_90.g, _T_1271 node _T_1272 = bits(_WIRE_91, 21, 21) connect _WIRE_90.u, _T_1272 node _T_1273 = bits(_WIRE_91, 41, 22) connect _WIRE_90.ppn, _T_1273 wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_93 : UInt<42> connect _WIRE_93, sectored_entries[0][2].data[2] node _T_1274 = bits(_WIRE_93, 0, 0) connect _WIRE_92.fragmented_superpage, _T_1274 node _T_1275 = bits(_WIRE_93, 1, 1) connect _WIRE_92.c, _T_1275 node _T_1276 = bits(_WIRE_93, 2, 2) connect _WIRE_92.eff, _T_1276 node _T_1277 = bits(_WIRE_93, 3, 3) connect _WIRE_92.paa, _T_1277 node _T_1278 = bits(_WIRE_93, 4, 4) connect _WIRE_92.pal, _T_1278 node _T_1279 = bits(_WIRE_93, 5, 5) connect _WIRE_92.ppp, _T_1279 node _T_1280 = bits(_WIRE_93, 6, 6) connect _WIRE_92.pr, _T_1280 node _T_1281 = bits(_WIRE_93, 7, 7) connect _WIRE_92.px, _T_1281 node _T_1282 = bits(_WIRE_93, 8, 8) connect _WIRE_92.pw, _T_1282 node _T_1283 = bits(_WIRE_93, 9, 9) connect _WIRE_92.hr, _T_1283 node _T_1284 = bits(_WIRE_93, 10, 10) connect _WIRE_92.hx, _T_1284 node _T_1285 = bits(_WIRE_93, 11, 11) connect _WIRE_92.hw, _T_1285 node _T_1286 = bits(_WIRE_93, 12, 12) connect _WIRE_92.sr, _T_1286 node _T_1287 = bits(_WIRE_93, 13, 13) connect _WIRE_92.sx, _T_1287 node _T_1288 = bits(_WIRE_93, 14, 14) connect _WIRE_92.sw, _T_1288 node _T_1289 = bits(_WIRE_93, 15, 15) connect _WIRE_92.gf, _T_1289 node _T_1290 = bits(_WIRE_93, 16, 16) connect _WIRE_92.pf, _T_1290 node _T_1291 = bits(_WIRE_93, 17, 17) connect _WIRE_92.ae_stage2, _T_1291 node _T_1292 = bits(_WIRE_93, 18, 18) connect _WIRE_92.ae_final, _T_1292 node _T_1293 = bits(_WIRE_93, 19, 19) connect _WIRE_92.ae_ptw, _T_1293 node _T_1294 = bits(_WIRE_93, 20, 20) connect _WIRE_92.g, _T_1294 node _T_1295 = bits(_WIRE_93, 21, 21) connect _WIRE_92.u, _T_1295 node _T_1296 = bits(_WIRE_93, 41, 22) connect _WIRE_92.ppn, _T_1296 wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_95 : UInt<42> connect _WIRE_95, sectored_entries[0][2].data[3] node _T_1297 = bits(_WIRE_95, 0, 0) connect _WIRE_94.fragmented_superpage, _T_1297 node _T_1298 = bits(_WIRE_95, 1, 1) connect _WIRE_94.c, _T_1298 node _T_1299 = bits(_WIRE_95, 2, 2) connect _WIRE_94.eff, _T_1299 node _T_1300 = bits(_WIRE_95, 3, 3) connect _WIRE_94.paa, _T_1300 node _T_1301 = bits(_WIRE_95, 4, 4) connect _WIRE_94.pal, _T_1301 node _T_1302 = bits(_WIRE_95, 5, 5) connect _WIRE_94.ppp, _T_1302 node _T_1303 = bits(_WIRE_95, 6, 6) connect _WIRE_94.pr, _T_1303 node _T_1304 = bits(_WIRE_95, 7, 7) connect _WIRE_94.px, _T_1304 node _T_1305 = bits(_WIRE_95, 8, 8) connect _WIRE_94.pw, _T_1305 node _T_1306 = bits(_WIRE_95, 9, 9) connect _WIRE_94.hr, _T_1306 node _T_1307 = bits(_WIRE_95, 10, 10) connect _WIRE_94.hx, _T_1307 node _T_1308 = bits(_WIRE_95, 11, 11) connect _WIRE_94.hw, _T_1308 node _T_1309 = bits(_WIRE_95, 12, 12) connect _WIRE_94.sr, _T_1309 node _T_1310 = bits(_WIRE_95, 13, 13) connect _WIRE_94.sx, _T_1310 node _T_1311 = bits(_WIRE_95, 14, 14) connect _WIRE_94.sw, _T_1311 node _T_1312 = bits(_WIRE_95, 15, 15) connect _WIRE_94.gf, _T_1312 node _T_1313 = bits(_WIRE_95, 16, 16) connect _WIRE_94.pf, _T_1313 node _T_1314 = bits(_WIRE_95, 17, 17) connect _WIRE_94.ae_stage2, _T_1314 node _T_1315 = bits(_WIRE_95, 18, 18) connect _WIRE_94.ae_final, _T_1315 node _T_1316 = bits(_WIRE_95, 19, 19) connect _WIRE_94.ae_ptw, _T_1316 node _T_1317 = bits(_WIRE_95, 20, 20) connect _WIRE_94.g, _T_1317 node _T_1318 = bits(_WIRE_95, 21, 21) connect _WIRE_94.u, _T_1318 node _T_1319 = bits(_WIRE_95, 41, 22) connect _WIRE_94.ppn, _T_1319 node _T_1320 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1320 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1321 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1321 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1322 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1322 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1323 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1323 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1324 = eq(hg_3, UInt<1>(0h0)) node _T_1325 = and(_T_1324, io.sfence.bits.rs1) when _T_1325 : node _T_1326 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1327 = shr(_T_1326, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1330 = and(_T_1328, _T_1329) when _T_1330 : wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_97 : UInt<42> connect _WIRE_97, sectored_entries[0][3].data[0] node _T_1331 = bits(_WIRE_97, 0, 0) connect _WIRE_96.fragmented_superpage, _T_1331 node _T_1332 = bits(_WIRE_97, 1, 1) connect _WIRE_96.c, _T_1332 node _T_1333 = bits(_WIRE_97, 2, 2) connect _WIRE_96.eff, _T_1333 node _T_1334 = bits(_WIRE_97, 3, 3) connect _WIRE_96.paa, _T_1334 node _T_1335 = bits(_WIRE_97, 4, 4) connect _WIRE_96.pal, _T_1335 node _T_1336 = bits(_WIRE_97, 5, 5) connect _WIRE_96.ppp, _T_1336 node _T_1337 = bits(_WIRE_97, 6, 6) connect _WIRE_96.pr, _T_1337 node _T_1338 = bits(_WIRE_97, 7, 7) connect _WIRE_96.px, _T_1338 node _T_1339 = bits(_WIRE_97, 8, 8) connect _WIRE_96.pw, _T_1339 node _T_1340 = bits(_WIRE_97, 9, 9) connect _WIRE_96.hr, _T_1340 node _T_1341 = bits(_WIRE_97, 10, 10) connect _WIRE_96.hx, _T_1341 node _T_1342 = bits(_WIRE_97, 11, 11) connect _WIRE_96.hw, _T_1342 node _T_1343 = bits(_WIRE_97, 12, 12) connect _WIRE_96.sr, _T_1343 node _T_1344 = bits(_WIRE_97, 13, 13) connect _WIRE_96.sx, _T_1344 node _T_1345 = bits(_WIRE_97, 14, 14) connect _WIRE_96.sw, _T_1345 node _T_1346 = bits(_WIRE_97, 15, 15) connect _WIRE_96.gf, _T_1346 node _T_1347 = bits(_WIRE_97, 16, 16) connect _WIRE_96.pf, _T_1347 node _T_1348 = bits(_WIRE_97, 17, 17) connect _WIRE_96.ae_stage2, _T_1348 node _T_1349 = bits(_WIRE_97, 18, 18) connect _WIRE_96.ae_final, _T_1349 node _T_1350 = bits(_WIRE_97, 19, 19) connect _WIRE_96.ae_ptw, _T_1350 node _T_1351 = bits(_WIRE_97, 20, 20) connect _WIRE_96.g, _T_1351 node _T_1352 = bits(_WIRE_97, 21, 21) connect _WIRE_96.u, _T_1352 node _T_1353 = bits(_WIRE_97, 41, 22) connect _WIRE_96.ppn, _T_1353 wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_99 : UInt<42> connect _WIRE_99, sectored_entries[0][3].data[1] node _T_1354 = bits(_WIRE_99, 0, 0) connect _WIRE_98.fragmented_superpage, _T_1354 node _T_1355 = bits(_WIRE_99, 1, 1) connect _WIRE_98.c, _T_1355 node _T_1356 = bits(_WIRE_99, 2, 2) connect _WIRE_98.eff, _T_1356 node _T_1357 = bits(_WIRE_99, 3, 3) connect _WIRE_98.paa, _T_1357 node _T_1358 = bits(_WIRE_99, 4, 4) connect _WIRE_98.pal, _T_1358 node _T_1359 = bits(_WIRE_99, 5, 5) connect _WIRE_98.ppp, _T_1359 node _T_1360 = bits(_WIRE_99, 6, 6) connect _WIRE_98.pr, _T_1360 node _T_1361 = bits(_WIRE_99, 7, 7) connect _WIRE_98.px, _T_1361 node _T_1362 = bits(_WIRE_99, 8, 8) connect _WIRE_98.pw, _T_1362 node _T_1363 = bits(_WIRE_99, 9, 9) connect _WIRE_98.hr, _T_1363 node _T_1364 = bits(_WIRE_99, 10, 10) connect _WIRE_98.hx, _T_1364 node _T_1365 = bits(_WIRE_99, 11, 11) connect _WIRE_98.hw, _T_1365 node _T_1366 = bits(_WIRE_99, 12, 12) connect _WIRE_98.sr, _T_1366 node _T_1367 = bits(_WIRE_99, 13, 13) connect _WIRE_98.sx, _T_1367 node _T_1368 = bits(_WIRE_99, 14, 14) connect _WIRE_98.sw, _T_1368 node _T_1369 = bits(_WIRE_99, 15, 15) connect _WIRE_98.gf, _T_1369 node _T_1370 = bits(_WIRE_99, 16, 16) connect _WIRE_98.pf, _T_1370 node _T_1371 = bits(_WIRE_99, 17, 17) connect _WIRE_98.ae_stage2, _T_1371 node _T_1372 = bits(_WIRE_99, 18, 18) connect _WIRE_98.ae_final, _T_1372 node _T_1373 = bits(_WIRE_99, 19, 19) connect _WIRE_98.ae_ptw, _T_1373 node _T_1374 = bits(_WIRE_99, 20, 20) connect _WIRE_98.g, _T_1374 node _T_1375 = bits(_WIRE_99, 21, 21) connect _WIRE_98.u, _T_1375 node _T_1376 = bits(_WIRE_99, 41, 22) connect _WIRE_98.ppn, _T_1376 wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_101 : UInt<42> connect _WIRE_101, sectored_entries[0][3].data[2] node _T_1377 = bits(_WIRE_101, 0, 0) connect _WIRE_100.fragmented_superpage, _T_1377 node _T_1378 = bits(_WIRE_101, 1, 1) connect _WIRE_100.c, _T_1378 node _T_1379 = bits(_WIRE_101, 2, 2) connect _WIRE_100.eff, _T_1379 node _T_1380 = bits(_WIRE_101, 3, 3) connect _WIRE_100.paa, _T_1380 node _T_1381 = bits(_WIRE_101, 4, 4) connect _WIRE_100.pal, _T_1381 node _T_1382 = bits(_WIRE_101, 5, 5) connect _WIRE_100.ppp, _T_1382 node _T_1383 = bits(_WIRE_101, 6, 6) connect _WIRE_100.pr, _T_1383 node _T_1384 = bits(_WIRE_101, 7, 7) connect _WIRE_100.px, _T_1384 node _T_1385 = bits(_WIRE_101, 8, 8) connect _WIRE_100.pw, _T_1385 node _T_1386 = bits(_WIRE_101, 9, 9) connect _WIRE_100.hr, _T_1386 node _T_1387 = bits(_WIRE_101, 10, 10) connect _WIRE_100.hx, _T_1387 node _T_1388 = bits(_WIRE_101, 11, 11) connect _WIRE_100.hw, _T_1388 node _T_1389 = bits(_WIRE_101, 12, 12) connect _WIRE_100.sr, _T_1389 node _T_1390 = bits(_WIRE_101, 13, 13) connect _WIRE_100.sx, _T_1390 node _T_1391 = bits(_WIRE_101, 14, 14) connect _WIRE_100.sw, _T_1391 node _T_1392 = bits(_WIRE_101, 15, 15) connect _WIRE_100.gf, _T_1392 node _T_1393 = bits(_WIRE_101, 16, 16) connect _WIRE_100.pf, _T_1393 node _T_1394 = bits(_WIRE_101, 17, 17) connect _WIRE_100.ae_stage2, _T_1394 node _T_1395 = bits(_WIRE_101, 18, 18) connect _WIRE_100.ae_final, _T_1395 node _T_1396 = bits(_WIRE_101, 19, 19) connect _WIRE_100.ae_ptw, _T_1396 node _T_1397 = bits(_WIRE_101, 20, 20) connect _WIRE_100.g, _T_1397 node _T_1398 = bits(_WIRE_101, 21, 21) connect _WIRE_100.u, _T_1398 node _T_1399 = bits(_WIRE_101, 41, 22) connect _WIRE_100.ppn, _T_1399 wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_103 : UInt<42> connect _WIRE_103, sectored_entries[0][3].data[3] node _T_1400 = bits(_WIRE_103, 0, 0) connect _WIRE_102.fragmented_superpage, _T_1400 node _T_1401 = bits(_WIRE_103, 1, 1) connect _WIRE_102.c, _T_1401 node _T_1402 = bits(_WIRE_103, 2, 2) connect _WIRE_102.eff, _T_1402 node _T_1403 = bits(_WIRE_103, 3, 3) connect _WIRE_102.paa, _T_1403 node _T_1404 = bits(_WIRE_103, 4, 4) connect _WIRE_102.pal, _T_1404 node _T_1405 = bits(_WIRE_103, 5, 5) connect _WIRE_102.ppp, _T_1405 node _T_1406 = bits(_WIRE_103, 6, 6) connect _WIRE_102.pr, _T_1406 node _T_1407 = bits(_WIRE_103, 7, 7) connect _WIRE_102.px, _T_1407 node _T_1408 = bits(_WIRE_103, 8, 8) connect _WIRE_102.pw, _T_1408 node _T_1409 = bits(_WIRE_103, 9, 9) connect _WIRE_102.hr, _T_1409 node _T_1410 = bits(_WIRE_103, 10, 10) connect _WIRE_102.hx, _T_1410 node _T_1411 = bits(_WIRE_103, 11, 11) connect _WIRE_102.hw, _T_1411 node _T_1412 = bits(_WIRE_103, 12, 12) connect _WIRE_102.sr, _T_1412 node _T_1413 = bits(_WIRE_103, 13, 13) connect _WIRE_102.sx, _T_1413 node _T_1414 = bits(_WIRE_103, 14, 14) connect _WIRE_102.sw, _T_1414 node _T_1415 = bits(_WIRE_103, 15, 15) connect _WIRE_102.gf, _T_1415 node _T_1416 = bits(_WIRE_103, 16, 16) connect _WIRE_102.pf, _T_1416 node _T_1417 = bits(_WIRE_103, 17, 17) connect _WIRE_102.ae_stage2, _T_1417 node _T_1418 = bits(_WIRE_103, 18, 18) connect _WIRE_102.ae_final, _T_1418 node _T_1419 = bits(_WIRE_103, 19, 19) connect _WIRE_102.ae_ptw, _T_1419 node _T_1420 = bits(_WIRE_103, 20, 20) connect _WIRE_102.g, _T_1420 node _T_1421 = bits(_WIRE_103, 21, 21) connect _WIRE_102.u, _T_1421 node _T_1422 = bits(_WIRE_103, 41, 22) connect _WIRE_102.ppn, _T_1422 node _T_1423 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1424 = bits(vpn, 1, 0) node _T_1425 = eq(UInt<1>(0h0), _T_1424) node _T_1426 = and(_T_1423, _T_1425) when _T_1426 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1427 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1428 = bits(vpn, 1, 0) node _T_1429 = eq(UInt<1>(0h1), _T_1428) node _T_1430 = and(_T_1427, _T_1429) when _T_1430 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1431 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1432 = bits(vpn, 1, 0) node _T_1433 = eq(UInt<2>(0h2), _T_1432) node _T_1434 = and(_T_1431, _T_1433) when _T_1434 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1435 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1436 = bits(vpn, 1, 0) node _T_1437 = eq(UInt<2>(0h3), _T_1436) node _T_1438 = and(_T_1435, _T_1437) when _T_1438 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_1439 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1440 = shr(_T_1439, 18) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_105 : UInt<42> connect _WIRE_105, sectored_entries[0][3].data[0] node _T_1442 = bits(_WIRE_105, 0, 0) connect _WIRE_104.fragmented_superpage, _T_1442 node _T_1443 = bits(_WIRE_105, 1, 1) connect _WIRE_104.c, _T_1443 node _T_1444 = bits(_WIRE_105, 2, 2) connect _WIRE_104.eff, _T_1444 node _T_1445 = bits(_WIRE_105, 3, 3) connect _WIRE_104.paa, _T_1445 node _T_1446 = bits(_WIRE_105, 4, 4) connect _WIRE_104.pal, _T_1446 node _T_1447 = bits(_WIRE_105, 5, 5) connect _WIRE_104.ppp, _T_1447 node _T_1448 = bits(_WIRE_105, 6, 6) connect _WIRE_104.pr, _T_1448 node _T_1449 = bits(_WIRE_105, 7, 7) connect _WIRE_104.px, _T_1449 node _T_1450 = bits(_WIRE_105, 8, 8) connect _WIRE_104.pw, _T_1450 node _T_1451 = bits(_WIRE_105, 9, 9) connect _WIRE_104.hr, _T_1451 node _T_1452 = bits(_WIRE_105, 10, 10) connect _WIRE_104.hx, _T_1452 node _T_1453 = bits(_WIRE_105, 11, 11) connect _WIRE_104.hw, _T_1453 node _T_1454 = bits(_WIRE_105, 12, 12) connect _WIRE_104.sr, _T_1454 node _T_1455 = bits(_WIRE_105, 13, 13) connect _WIRE_104.sx, _T_1455 node _T_1456 = bits(_WIRE_105, 14, 14) connect _WIRE_104.sw, _T_1456 node _T_1457 = bits(_WIRE_105, 15, 15) connect _WIRE_104.gf, _T_1457 node _T_1458 = bits(_WIRE_105, 16, 16) connect _WIRE_104.pf, _T_1458 node _T_1459 = bits(_WIRE_105, 17, 17) connect _WIRE_104.ae_stage2, _T_1459 node _T_1460 = bits(_WIRE_105, 18, 18) connect _WIRE_104.ae_final, _T_1460 node _T_1461 = bits(_WIRE_105, 19, 19) connect _WIRE_104.ae_ptw, _T_1461 node _T_1462 = bits(_WIRE_105, 20, 20) connect _WIRE_104.g, _T_1462 node _T_1463 = bits(_WIRE_105, 21, 21) connect _WIRE_104.u, _T_1463 node _T_1464 = bits(_WIRE_105, 41, 22) connect _WIRE_104.ppn, _T_1464 wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_107 : UInt<42> connect _WIRE_107, sectored_entries[0][3].data[1] node _T_1465 = bits(_WIRE_107, 0, 0) connect _WIRE_106.fragmented_superpage, _T_1465 node _T_1466 = bits(_WIRE_107, 1, 1) connect _WIRE_106.c, _T_1466 node _T_1467 = bits(_WIRE_107, 2, 2) connect _WIRE_106.eff, _T_1467 node _T_1468 = bits(_WIRE_107, 3, 3) connect _WIRE_106.paa, _T_1468 node _T_1469 = bits(_WIRE_107, 4, 4) connect _WIRE_106.pal, _T_1469 node _T_1470 = bits(_WIRE_107, 5, 5) connect _WIRE_106.ppp, _T_1470 node _T_1471 = bits(_WIRE_107, 6, 6) connect _WIRE_106.pr, _T_1471 node _T_1472 = bits(_WIRE_107, 7, 7) connect _WIRE_106.px, _T_1472 node _T_1473 = bits(_WIRE_107, 8, 8) connect _WIRE_106.pw, _T_1473 node _T_1474 = bits(_WIRE_107, 9, 9) connect _WIRE_106.hr, _T_1474 node _T_1475 = bits(_WIRE_107, 10, 10) connect _WIRE_106.hx, _T_1475 node _T_1476 = bits(_WIRE_107, 11, 11) connect _WIRE_106.hw, _T_1476 node _T_1477 = bits(_WIRE_107, 12, 12) connect _WIRE_106.sr, _T_1477 node _T_1478 = bits(_WIRE_107, 13, 13) connect _WIRE_106.sx, _T_1478 node _T_1479 = bits(_WIRE_107, 14, 14) connect _WIRE_106.sw, _T_1479 node _T_1480 = bits(_WIRE_107, 15, 15) connect _WIRE_106.gf, _T_1480 node _T_1481 = bits(_WIRE_107, 16, 16) connect _WIRE_106.pf, _T_1481 node _T_1482 = bits(_WIRE_107, 17, 17) connect _WIRE_106.ae_stage2, _T_1482 node _T_1483 = bits(_WIRE_107, 18, 18) connect _WIRE_106.ae_final, _T_1483 node _T_1484 = bits(_WIRE_107, 19, 19) connect _WIRE_106.ae_ptw, _T_1484 node _T_1485 = bits(_WIRE_107, 20, 20) connect _WIRE_106.g, _T_1485 node _T_1486 = bits(_WIRE_107, 21, 21) connect _WIRE_106.u, _T_1486 node _T_1487 = bits(_WIRE_107, 41, 22) connect _WIRE_106.ppn, _T_1487 wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_109 : UInt<42> connect _WIRE_109, sectored_entries[0][3].data[2] node _T_1488 = bits(_WIRE_109, 0, 0) connect _WIRE_108.fragmented_superpage, _T_1488 node _T_1489 = bits(_WIRE_109, 1, 1) connect _WIRE_108.c, _T_1489 node _T_1490 = bits(_WIRE_109, 2, 2) connect _WIRE_108.eff, _T_1490 node _T_1491 = bits(_WIRE_109, 3, 3) connect _WIRE_108.paa, _T_1491 node _T_1492 = bits(_WIRE_109, 4, 4) connect _WIRE_108.pal, _T_1492 node _T_1493 = bits(_WIRE_109, 5, 5) connect _WIRE_108.ppp, _T_1493 node _T_1494 = bits(_WIRE_109, 6, 6) connect _WIRE_108.pr, _T_1494 node _T_1495 = bits(_WIRE_109, 7, 7) connect _WIRE_108.px, _T_1495 node _T_1496 = bits(_WIRE_109, 8, 8) connect _WIRE_108.pw, _T_1496 node _T_1497 = bits(_WIRE_109, 9, 9) connect _WIRE_108.hr, _T_1497 node _T_1498 = bits(_WIRE_109, 10, 10) connect _WIRE_108.hx, _T_1498 node _T_1499 = bits(_WIRE_109, 11, 11) connect _WIRE_108.hw, _T_1499 node _T_1500 = bits(_WIRE_109, 12, 12) connect _WIRE_108.sr, _T_1500 node _T_1501 = bits(_WIRE_109, 13, 13) connect _WIRE_108.sx, _T_1501 node _T_1502 = bits(_WIRE_109, 14, 14) connect _WIRE_108.sw, _T_1502 node _T_1503 = bits(_WIRE_109, 15, 15) connect _WIRE_108.gf, _T_1503 node _T_1504 = bits(_WIRE_109, 16, 16) connect _WIRE_108.pf, _T_1504 node _T_1505 = bits(_WIRE_109, 17, 17) connect _WIRE_108.ae_stage2, _T_1505 node _T_1506 = bits(_WIRE_109, 18, 18) connect _WIRE_108.ae_final, _T_1506 node _T_1507 = bits(_WIRE_109, 19, 19) connect _WIRE_108.ae_ptw, _T_1507 node _T_1508 = bits(_WIRE_109, 20, 20) connect _WIRE_108.g, _T_1508 node _T_1509 = bits(_WIRE_109, 21, 21) connect _WIRE_108.u, _T_1509 node _T_1510 = bits(_WIRE_109, 41, 22) connect _WIRE_108.ppn, _T_1510 wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_111 : UInt<42> connect _WIRE_111, sectored_entries[0][3].data[3] node _T_1511 = bits(_WIRE_111, 0, 0) connect _WIRE_110.fragmented_superpage, _T_1511 node _T_1512 = bits(_WIRE_111, 1, 1) connect _WIRE_110.c, _T_1512 node _T_1513 = bits(_WIRE_111, 2, 2) connect _WIRE_110.eff, _T_1513 node _T_1514 = bits(_WIRE_111, 3, 3) connect _WIRE_110.paa, _T_1514 node _T_1515 = bits(_WIRE_111, 4, 4) connect _WIRE_110.pal, _T_1515 node _T_1516 = bits(_WIRE_111, 5, 5) connect _WIRE_110.ppp, _T_1516 node _T_1517 = bits(_WIRE_111, 6, 6) connect _WIRE_110.pr, _T_1517 node _T_1518 = bits(_WIRE_111, 7, 7) connect _WIRE_110.px, _T_1518 node _T_1519 = bits(_WIRE_111, 8, 8) connect _WIRE_110.pw, _T_1519 node _T_1520 = bits(_WIRE_111, 9, 9) connect _WIRE_110.hr, _T_1520 node _T_1521 = bits(_WIRE_111, 10, 10) connect _WIRE_110.hx, _T_1521 node _T_1522 = bits(_WIRE_111, 11, 11) connect _WIRE_110.hw, _T_1522 node _T_1523 = bits(_WIRE_111, 12, 12) connect _WIRE_110.sr, _T_1523 node _T_1524 = bits(_WIRE_111, 13, 13) connect _WIRE_110.sx, _T_1524 node _T_1525 = bits(_WIRE_111, 14, 14) connect _WIRE_110.sw, _T_1525 node _T_1526 = bits(_WIRE_111, 15, 15) connect _WIRE_110.gf, _T_1526 node _T_1527 = bits(_WIRE_111, 16, 16) connect _WIRE_110.pf, _T_1527 node _T_1528 = bits(_WIRE_111, 17, 17) connect _WIRE_110.ae_stage2, _T_1528 node _T_1529 = bits(_WIRE_111, 18, 18) connect _WIRE_110.ae_final, _T_1529 node _T_1530 = bits(_WIRE_111, 19, 19) connect _WIRE_110.ae_ptw, _T_1530 node _T_1531 = bits(_WIRE_111, 20, 20) connect _WIRE_110.g, _T_1531 node _T_1532 = bits(_WIRE_111, 21, 21) connect _WIRE_110.u, _T_1532 node _T_1533 = bits(_WIRE_111, 41, 22) connect _WIRE_110.ppn, _T_1533 node _T_1534 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1535 = and(_T_1534, _WIRE_104.fragmented_superpage) when _T_1535 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1536 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1537 = and(_T_1536, _WIRE_106.fragmented_superpage) when _T_1537 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1538 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1539 = and(_T_1538, _WIRE_108.fragmented_superpage) when _T_1539 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1540 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1541 = and(_T_1540, _WIRE_110.fragmented_superpage) when _T_1541 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1542 = eq(hg_3, UInt<1>(0h0)) node _T_1543 = and(_T_1542, io.sfence.bits.rs2) when _T_1543 : wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_113 : UInt<42> connect _WIRE_113, sectored_entries[0][3].data[0] node _T_1544 = bits(_WIRE_113, 0, 0) connect _WIRE_112.fragmented_superpage, _T_1544 node _T_1545 = bits(_WIRE_113, 1, 1) connect _WIRE_112.c, _T_1545 node _T_1546 = bits(_WIRE_113, 2, 2) connect _WIRE_112.eff, _T_1546 node _T_1547 = bits(_WIRE_113, 3, 3) connect _WIRE_112.paa, _T_1547 node _T_1548 = bits(_WIRE_113, 4, 4) connect _WIRE_112.pal, _T_1548 node _T_1549 = bits(_WIRE_113, 5, 5) connect _WIRE_112.ppp, _T_1549 node _T_1550 = bits(_WIRE_113, 6, 6) connect _WIRE_112.pr, _T_1550 node _T_1551 = bits(_WIRE_113, 7, 7) connect _WIRE_112.px, _T_1551 node _T_1552 = bits(_WIRE_113, 8, 8) connect _WIRE_112.pw, _T_1552 node _T_1553 = bits(_WIRE_113, 9, 9) connect _WIRE_112.hr, _T_1553 node _T_1554 = bits(_WIRE_113, 10, 10) connect _WIRE_112.hx, _T_1554 node _T_1555 = bits(_WIRE_113, 11, 11) connect _WIRE_112.hw, _T_1555 node _T_1556 = bits(_WIRE_113, 12, 12) connect _WIRE_112.sr, _T_1556 node _T_1557 = bits(_WIRE_113, 13, 13) connect _WIRE_112.sx, _T_1557 node _T_1558 = bits(_WIRE_113, 14, 14) connect _WIRE_112.sw, _T_1558 node _T_1559 = bits(_WIRE_113, 15, 15) connect _WIRE_112.gf, _T_1559 node _T_1560 = bits(_WIRE_113, 16, 16) connect _WIRE_112.pf, _T_1560 node _T_1561 = bits(_WIRE_113, 17, 17) connect _WIRE_112.ae_stage2, _T_1561 node _T_1562 = bits(_WIRE_113, 18, 18) connect _WIRE_112.ae_final, _T_1562 node _T_1563 = bits(_WIRE_113, 19, 19) connect _WIRE_112.ae_ptw, _T_1563 node _T_1564 = bits(_WIRE_113, 20, 20) connect _WIRE_112.g, _T_1564 node _T_1565 = bits(_WIRE_113, 21, 21) connect _WIRE_112.u, _T_1565 node _T_1566 = bits(_WIRE_113, 41, 22) connect _WIRE_112.ppn, _T_1566 wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_115 : UInt<42> connect _WIRE_115, sectored_entries[0][3].data[1] node _T_1567 = bits(_WIRE_115, 0, 0) connect _WIRE_114.fragmented_superpage, _T_1567 node _T_1568 = bits(_WIRE_115, 1, 1) connect _WIRE_114.c, _T_1568 node _T_1569 = bits(_WIRE_115, 2, 2) connect _WIRE_114.eff, _T_1569 node _T_1570 = bits(_WIRE_115, 3, 3) connect _WIRE_114.paa, _T_1570 node _T_1571 = bits(_WIRE_115, 4, 4) connect _WIRE_114.pal, _T_1571 node _T_1572 = bits(_WIRE_115, 5, 5) connect _WIRE_114.ppp, _T_1572 node _T_1573 = bits(_WIRE_115, 6, 6) connect _WIRE_114.pr, _T_1573 node _T_1574 = bits(_WIRE_115, 7, 7) connect _WIRE_114.px, _T_1574 node _T_1575 = bits(_WIRE_115, 8, 8) connect _WIRE_114.pw, _T_1575 node _T_1576 = bits(_WIRE_115, 9, 9) connect _WIRE_114.hr, _T_1576 node _T_1577 = bits(_WIRE_115, 10, 10) connect _WIRE_114.hx, _T_1577 node _T_1578 = bits(_WIRE_115, 11, 11) connect _WIRE_114.hw, _T_1578 node _T_1579 = bits(_WIRE_115, 12, 12) connect _WIRE_114.sr, _T_1579 node _T_1580 = bits(_WIRE_115, 13, 13) connect _WIRE_114.sx, _T_1580 node _T_1581 = bits(_WIRE_115, 14, 14) connect _WIRE_114.sw, _T_1581 node _T_1582 = bits(_WIRE_115, 15, 15) connect _WIRE_114.gf, _T_1582 node _T_1583 = bits(_WIRE_115, 16, 16) connect _WIRE_114.pf, _T_1583 node _T_1584 = bits(_WIRE_115, 17, 17) connect _WIRE_114.ae_stage2, _T_1584 node _T_1585 = bits(_WIRE_115, 18, 18) connect _WIRE_114.ae_final, _T_1585 node _T_1586 = bits(_WIRE_115, 19, 19) connect _WIRE_114.ae_ptw, _T_1586 node _T_1587 = bits(_WIRE_115, 20, 20) connect _WIRE_114.g, _T_1587 node _T_1588 = bits(_WIRE_115, 21, 21) connect _WIRE_114.u, _T_1588 node _T_1589 = bits(_WIRE_115, 41, 22) connect _WIRE_114.ppn, _T_1589 wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_117 : UInt<42> connect _WIRE_117, sectored_entries[0][3].data[2] node _T_1590 = bits(_WIRE_117, 0, 0) connect _WIRE_116.fragmented_superpage, _T_1590 node _T_1591 = bits(_WIRE_117, 1, 1) connect _WIRE_116.c, _T_1591 node _T_1592 = bits(_WIRE_117, 2, 2) connect _WIRE_116.eff, _T_1592 node _T_1593 = bits(_WIRE_117, 3, 3) connect _WIRE_116.paa, _T_1593 node _T_1594 = bits(_WIRE_117, 4, 4) connect _WIRE_116.pal, _T_1594 node _T_1595 = bits(_WIRE_117, 5, 5) connect _WIRE_116.ppp, _T_1595 node _T_1596 = bits(_WIRE_117, 6, 6) connect _WIRE_116.pr, _T_1596 node _T_1597 = bits(_WIRE_117, 7, 7) connect _WIRE_116.px, _T_1597 node _T_1598 = bits(_WIRE_117, 8, 8) connect _WIRE_116.pw, _T_1598 node _T_1599 = bits(_WIRE_117, 9, 9) connect _WIRE_116.hr, _T_1599 node _T_1600 = bits(_WIRE_117, 10, 10) connect _WIRE_116.hx, _T_1600 node _T_1601 = bits(_WIRE_117, 11, 11) connect _WIRE_116.hw, _T_1601 node _T_1602 = bits(_WIRE_117, 12, 12) connect _WIRE_116.sr, _T_1602 node _T_1603 = bits(_WIRE_117, 13, 13) connect _WIRE_116.sx, _T_1603 node _T_1604 = bits(_WIRE_117, 14, 14) connect _WIRE_116.sw, _T_1604 node _T_1605 = bits(_WIRE_117, 15, 15) connect _WIRE_116.gf, _T_1605 node _T_1606 = bits(_WIRE_117, 16, 16) connect _WIRE_116.pf, _T_1606 node _T_1607 = bits(_WIRE_117, 17, 17) connect _WIRE_116.ae_stage2, _T_1607 node _T_1608 = bits(_WIRE_117, 18, 18) connect _WIRE_116.ae_final, _T_1608 node _T_1609 = bits(_WIRE_117, 19, 19) connect _WIRE_116.ae_ptw, _T_1609 node _T_1610 = bits(_WIRE_117, 20, 20) connect _WIRE_116.g, _T_1610 node _T_1611 = bits(_WIRE_117, 21, 21) connect _WIRE_116.u, _T_1611 node _T_1612 = bits(_WIRE_117, 41, 22) connect _WIRE_116.ppn, _T_1612 wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_119 : UInt<42> connect _WIRE_119, sectored_entries[0][3].data[3] node _T_1613 = bits(_WIRE_119, 0, 0) connect _WIRE_118.fragmented_superpage, _T_1613 node _T_1614 = bits(_WIRE_119, 1, 1) connect _WIRE_118.c, _T_1614 node _T_1615 = bits(_WIRE_119, 2, 2) connect _WIRE_118.eff, _T_1615 node _T_1616 = bits(_WIRE_119, 3, 3) connect _WIRE_118.paa, _T_1616 node _T_1617 = bits(_WIRE_119, 4, 4) connect _WIRE_118.pal, _T_1617 node _T_1618 = bits(_WIRE_119, 5, 5) connect _WIRE_118.ppp, _T_1618 node _T_1619 = bits(_WIRE_119, 6, 6) connect _WIRE_118.pr, _T_1619 node _T_1620 = bits(_WIRE_119, 7, 7) connect _WIRE_118.px, _T_1620 node _T_1621 = bits(_WIRE_119, 8, 8) connect _WIRE_118.pw, _T_1621 node _T_1622 = bits(_WIRE_119, 9, 9) connect _WIRE_118.hr, _T_1622 node _T_1623 = bits(_WIRE_119, 10, 10) connect _WIRE_118.hx, _T_1623 node _T_1624 = bits(_WIRE_119, 11, 11) connect _WIRE_118.hw, _T_1624 node _T_1625 = bits(_WIRE_119, 12, 12) connect _WIRE_118.sr, _T_1625 node _T_1626 = bits(_WIRE_119, 13, 13) connect _WIRE_118.sx, _T_1626 node _T_1627 = bits(_WIRE_119, 14, 14) connect _WIRE_118.sw, _T_1627 node _T_1628 = bits(_WIRE_119, 15, 15) connect _WIRE_118.gf, _T_1628 node _T_1629 = bits(_WIRE_119, 16, 16) connect _WIRE_118.pf, _T_1629 node _T_1630 = bits(_WIRE_119, 17, 17) connect _WIRE_118.ae_stage2, _T_1630 node _T_1631 = bits(_WIRE_119, 18, 18) connect _WIRE_118.ae_final, _T_1631 node _T_1632 = bits(_WIRE_119, 19, 19) connect _WIRE_118.ae_ptw, _T_1632 node _T_1633 = bits(_WIRE_119, 20, 20) connect _WIRE_118.g, _T_1633 node _T_1634 = bits(_WIRE_119, 21, 21) connect _WIRE_118.u, _T_1634 node _T_1635 = bits(_WIRE_119, 41, 22) connect _WIRE_118.ppn, _T_1635 node _T_1636 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1637 = eq(_WIRE_112.g, UInt<1>(0h0)) node _T_1638 = and(_T_1636, _T_1637) when _T_1638 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1639 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1640 = eq(_WIRE_114.g, UInt<1>(0h0)) node _T_1641 = and(_T_1639, _T_1640) when _T_1641 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1642 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1643 = eq(_WIRE_116.g, UInt<1>(0h0)) node _T_1644 = and(_T_1642, _T_1643) when _T_1644 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1645 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1646 = eq(_WIRE_118.g, UInt<1>(0h0)) node _T_1647 = and(_T_1645, _T_1646) when _T_1647 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1648 = or(hv_3, hg_3) wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_121 : UInt<42> connect _WIRE_121, sectored_entries[0][3].data[0] node _T_1649 = bits(_WIRE_121, 0, 0) connect _WIRE_120.fragmented_superpage, _T_1649 node _T_1650 = bits(_WIRE_121, 1, 1) connect _WIRE_120.c, _T_1650 node _T_1651 = bits(_WIRE_121, 2, 2) connect _WIRE_120.eff, _T_1651 node _T_1652 = bits(_WIRE_121, 3, 3) connect _WIRE_120.paa, _T_1652 node _T_1653 = bits(_WIRE_121, 4, 4) connect _WIRE_120.pal, _T_1653 node _T_1654 = bits(_WIRE_121, 5, 5) connect _WIRE_120.ppp, _T_1654 node _T_1655 = bits(_WIRE_121, 6, 6) connect _WIRE_120.pr, _T_1655 node _T_1656 = bits(_WIRE_121, 7, 7) connect _WIRE_120.px, _T_1656 node _T_1657 = bits(_WIRE_121, 8, 8) connect _WIRE_120.pw, _T_1657 node _T_1658 = bits(_WIRE_121, 9, 9) connect _WIRE_120.hr, _T_1658 node _T_1659 = bits(_WIRE_121, 10, 10) connect _WIRE_120.hx, _T_1659 node _T_1660 = bits(_WIRE_121, 11, 11) connect _WIRE_120.hw, _T_1660 node _T_1661 = bits(_WIRE_121, 12, 12) connect _WIRE_120.sr, _T_1661 node _T_1662 = bits(_WIRE_121, 13, 13) connect _WIRE_120.sx, _T_1662 node _T_1663 = bits(_WIRE_121, 14, 14) connect _WIRE_120.sw, _T_1663 node _T_1664 = bits(_WIRE_121, 15, 15) connect _WIRE_120.gf, _T_1664 node _T_1665 = bits(_WIRE_121, 16, 16) connect _WIRE_120.pf, _T_1665 node _T_1666 = bits(_WIRE_121, 17, 17) connect _WIRE_120.ae_stage2, _T_1666 node _T_1667 = bits(_WIRE_121, 18, 18) connect _WIRE_120.ae_final, _T_1667 node _T_1668 = bits(_WIRE_121, 19, 19) connect _WIRE_120.ae_ptw, _T_1668 node _T_1669 = bits(_WIRE_121, 20, 20) connect _WIRE_120.g, _T_1669 node _T_1670 = bits(_WIRE_121, 21, 21) connect _WIRE_120.u, _T_1670 node _T_1671 = bits(_WIRE_121, 41, 22) connect _WIRE_120.ppn, _T_1671 wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_123 : UInt<42> connect _WIRE_123, sectored_entries[0][3].data[1] node _T_1672 = bits(_WIRE_123, 0, 0) connect _WIRE_122.fragmented_superpage, _T_1672 node _T_1673 = bits(_WIRE_123, 1, 1) connect _WIRE_122.c, _T_1673 node _T_1674 = bits(_WIRE_123, 2, 2) connect _WIRE_122.eff, _T_1674 node _T_1675 = bits(_WIRE_123, 3, 3) connect _WIRE_122.paa, _T_1675 node _T_1676 = bits(_WIRE_123, 4, 4) connect _WIRE_122.pal, _T_1676 node _T_1677 = bits(_WIRE_123, 5, 5) connect _WIRE_122.ppp, _T_1677 node _T_1678 = bits(_WIRE_123, 6, 6) connect _WIRE_122.pr, _T_1678 node _T_1679 = bits(_WIRE_123, 7, 7) connect _WIRE_122.px, _T_1679 node _T_1680 = bits(_WIRE_123, 8, 8) connect _WIRE_122.pw, _T_1680 node _T_1681 = bits(_WIRE_123, 9, 9) connect _WIRE_122.hr, _T_1681 node _T_1682 = bits(_WIRE_123, 10, 10) connect _WIRE_122.hx, _T_1682 node _T_1683 = bits(_WIRE_123, 11, 11) connect _WIRE_122.hw, _T_1683 node _T_1684 = bits(_WIRE_123, 12, 12) connect _WIRE_122.sr, _T_1684 node _T_1685 = bits(_WIRE_123, 13, 13) connect _WIRE_122.sx, _T_1685 node _T_1686 = bits(_WIRE_123, 14, 14) connect _WIRE_122.sw, _T_1686 node _T_1687 = bits(_WIRE_123, 15, 15) connect _WIRE_122.gf, _T_1687 node _T_1688 = bits(_WIRE_123, 16, 16) connect _WIRE_122.pf, _T_1688 node _T_1689 = bits(_WIRE_123, 17, 17) connect _WIRE_122.ae_stage2, _T_1689 node _T_1690 = bits(_WIRE_123, 18, 18) connect _WIRE_122.ae_final, _T_1690 node _T_1691 = bits(_WIRE_123, 19, 19) connect _WIRE_122.ae_ptw, _T_1691 node _T_1692 = bits(_WIRE_123, 20, 20) connect _WIRE_122.g, _T_1692 node _T_1693 = bits(_WIRE_123, 21, 21) connect _WIRE_122.u, _T_1693 node _T_1694 = bits(_WIRE_123, 41, 22) connect _WIRE_122.ppn, _T_1694 wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_125 : UInt<42> connect _WIRE_125, sectored_entries[0][3].data[2] node _T_1695 = bits(_WIRE_125, 0, 0) connect _WIRE_124.fragmented_superpage, _T_1695 node _T_1696 = bits(_WIRE_125, 1, 1) connect _WIRE_124.c, _T_1696 node _T_1697 = bits(_WIRE_125, 2, 2) connect _WIRE_124.eff, _T_1697 node _T_1698 = bits(_WIRE_125, 3, 3) connect _WIRE_124.paa, _T_1698 node _T_1699 = bits(_WIRE_125, 4, 4) connect _WIRE_124.pal, _T_1699 node _T_1700 = bits(_WIRE_125, 5, 5) connect _WIRE_124.ppp, _T_1700 node _T_1701 = bits(_WIRE_125, 6, 6) connect _WIRE_124.pr, _T_1701 node _T_1702 = bits(_WIRE_125, 7, 7) connect _WIRE_124.px, _T_1702 node _T_1703 = bits(_WIRE_125, 8, 8) connect _WIRE_124.pw, _T_1703 node _T_1704 = bits(_WIRE_125, 9, 9) connect _WIRE_124.hr, _T_1704 node _T_1705 = bits(_WIRE_125, 10, 10) connect _WIRE_124.hx, _T_1705 node _T_1706 = bits(_WIRE_125, 11, 11) connect _WIRE_124.hw, _T_1706 node _T_1707 = bits(_WIRE_125, 12, 12) connect _WIRE_124.sr, _T_1707 node _T_1708 = bits(_WIRE_125, 13, 13) connect _WIRE_124.sx, _T_1708 node _T_1709 = bits(_WIRE_125, 14, 14) connect _WIRE_124.sw, _T_1709 node _T_1710 = bits(_WIRE_125, 15, 15) connect _WIRE_124.gf, _T_1710 node _T_1711 = bits(_WIRE_125, 16, 16) connect _WIRE_124.pf, _T_1711 node _T_1712 = bits(_WIRE_125, 17, 17) connect _WIRE_124.ae_stage2, _T_1712 node _T_1713 = bits(_WIRE_125, 18, 18) connect _WIRE_124.ae_final, _T_1713 node _T_1714 = bits(_WIRE_125, 19, 19) connect _WIRE_124.ae_ptw, _T_1714 node _T_1715 = bits(_WIRE_125, 20, 20) connect _WIRE_124.g, _T_1715 node _T_1716 = bits(_WIRE_125, 21, 21) connect _WIRE_124.u, _T_1716 node _T_1717 = bits(_WIRE_125, 41, 22) connect _WIRE_124.ppn, _T_1717 wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_127 : UInt<42> connect _WIRE_127, sectored_entries[0][3].data[3] node _T_1718 = bits(_WIRE_127, 0, 0) connect _WIRE_126.fragmented_superpage, _T_1718 node _T_1719 = bits(_WIRE_127, 1, 1) connect _WIRE_126.c, _T_1719 node _T_1720 = bits(_WIRE_127, 2, 2) connect _WIRE_126.eff, _T_1720 node _T_1721 = bits(_WIRE_127, 3, 3) connect _WIRE_126.paa, _T_1721 node _T_1722 = bits(_WIRE_127, 4, 4) connect _WIRE_126.pal, _T_1722 node _T_1723 = bits(_WIRE_127, 5, 5) connect _WIRE_126.ppp, _T_1723 node _T_1724 = bits(_WIRE_127, 6, 6) connect _WIRE_126.pr, _T_1724 node _T_1725 = bits(_WIRE_127, 7, 7) connect _WIRE_126.px, _T_1725 node _T_1726 = bits(_WIRE_127, 8, 8) connect _WIRE_126.pw, _T_1726 node _T_1727 = bits(_WIRE_127, 9, 9) connect _WIRE_126.hr, _T_1727 node _T_1728 = bits(_WIRE_127, 10, 10) connect _WIRE_126.hx, _T_1728 node _T_1729 = bits(_WIRE_127, 11, 11) connect _WIRE_126.hw, _T_1729 node _T_1730 = bits(_WIRE_127, 12, 12) connect _WIRE_126.sr, _T_1730 node _T_1731 = bits(_WIRE_127, 13, 13) connect _WIRE_126.sx, _T_1731 node _T_1732 = bits(_WIRE_127, 14, 14) connect _WIRE_126.sw, _T_1732 node _T_1733 = bits(_WIRE_127, 15, 15) connect _WIRE_126.gf, _T_1733 node _T_1734 = bits(_WIRE_127, 16, 16) connect _WIRE_126.pf, _T_1734 node _T_1735 = bits(_WIRE_127, 17, 17) connect _WIRE_126.ae_stage2, _T_1735 node _T_1736 = bits(_WIRE_127, 18, 18) connect _WIRE_126.ae_final, _T_1736 node _T_1737 = bits(_WIRE_127, 19, 19) connect _WIRE_126.ae_ptw, _T_1737 node _T_1738 = bits(_WIRE_127, 20, 20) connect _WIRE_126.g, _T_1738 node _T_1739 = bits(_WIRE_127, 21, 21) connect _WIRE_126.u, _T_1739 node _T_1740 = bits(_WIRE_127, 41, 22) connect _WIRE_126.ppn, _T_1740 node _T_1741 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1741 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1742 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1742 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1743 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1743 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1744 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1744 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1745 = eq(hg_4, UInt<1>(0h0)) node _T_1746 = and(_T_1745, io.sfence.bits.rs1) when _T_1746 : node _T_1747 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1748 = shr(_T_1747, 2) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1751 = and(_T_1749, _T_1750) when _T_1751 : wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_129 : UInt<42> connect _WIRE_129, sectored_entries[0][4].data[0] node _T_1752 = bits(_WIRE_129, 0, 0) connect _WIRE_128.fragmented_superpage, _T_1752 node _T_1753 = bits(_WIRE_129, 1, 1) connect _WIRE_128.c, _T_1753 node _T_1754 = bits(_WIRE_129, 2, 2) connect _WIRE_128.eff, _T_1754 node _T_1755 = bits(_WIRE_129, 3, 3) connect _WIRE_128.paa, _T_1755 node _T_1756 = bits(_WIRE_129, 4, 4) connect _WIRE_128.pal, _T_1756 node _T_1757 = bits(_WIRE_129, 5, 5) connect _WIRE_128.ppp, _T_1757 node _T_1758 = bits(_WIRE_129, 6, 6) connect _WIRE_128.pr, _T_1758 node _T_1759 = bits(_WIRE_129, 7, 7) connect _WIRE_128.px, _T_1759 node _T_1760 = bits(_WIRE_129, 8, 8) connect _WIRE_128.pw, _T_1760 node _T_1761 = bits(_WIRE_129, 9, 9) connect _WIRE_128.hr, _T_1761 node _T_1762 = bits(_WIRE_129, 10, 10) connect _WIRE_128.hx, _T_1762 node _T_1763 = bits(_WIRE_129, 11, 11) connect _WIRE_128.hw, _T_1763 node _T_1764 = bits(_WIRE_129, 12, 12) connect _WIRE_128.sr, _T_1764 node _T_1765 = bits(_WIRE_129, 13, 13) connect _WIRE_128.sx, _T_1765 node _T_1766 = bits(_WIRE_129, 14, 14) connect _WIRE_128.sw, _T_1766 node _T_1767 = bits(_WIRE_129, 15, 15) connect _WIRE_128.gf, _T_1767 node _T_1768 = bits(_WIRE_129, 16, 16) connect _WIRE_128.pf, _T_1768 node _T_1769 = bits(_WIRE_129, 17, 17) connect _WIRE_128.ae_stage2, _T_1769 node _T_1770 = bits(_WIRE_129, 18, 18) connect _WIRE_128.ae_final, _T_1770 node _T_1771 = bits(_WIRE_129, 19, 19) connect _WIRE_128.ae_ptw, _T_1771 node _T_1772 = bits(_WIRE_129, 20, 20) connect _WIRE_128.g, _T_1772 node _T_1773 = bits(_WIRE_129, 21, 21) connect _WIRE_128.u, _T_1773 node _T_1774 = bits(_WIRE_129, 41, 22) connect _WIRE_128.ppn, _T_1774 wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_131 : UInt<42> connect _WIRE_131, sectored_entries[0][4].data[1] node _T_1775 = bits(_WIRE_131, 0, 0) connect _WIRE_130.fragmented_superpage, _T_1775 node _T_1776 = bits(_WIRE_131, 1, 1) connect _WIRE_130.c, _T_1776 node _T_1777 = bits(_WIRE_131, 2, 2) connect _WIRE_130.eff, _T_1777 node _T_1778 = bits(_WIRE_131, 3, 3) connect _WIRE_130.paa, _T_1778 node _T_1779 = bits(_WIRE_131, 4, 4) connect _WIRE_130.pal, _T_1779 node _T_1780 = bits(_WIRE_131, 5, 5) connect _WIRE_130.ppp, _T_1780 node _T_1781 = bits(_WIRE_131, 6, 6) connect _WIRE_130.pr, _T_1781 node _T_1782 = bits(_WIRE_131, 7, 7) connect _WIRE_130.px, _T_1782 node _T_1783 = bits(_WIRE_131, 8, 8) connect _WIRE_130.pw, _T_1783 node _T_1784 = bits(_WIRE_131, 9, 9) connect _WIRE_130.hr, _T_1784 node _T_1785 = bits(_WIRE_131, 10, 10) connect _WIRE_130.hx, _T_1785 node _T_1786 = bits(_WIRE_131, 11, 11) connect _WIRE_130.hw, _T_1786 node _T_1787 = bits(_WIRE_131, 12, 12) connect _WIRE_130.sr, _T_1787 node _T_1788 = bits(_WIRE_131, 13, 13) connect _WIRE_130.sx, _T_1788 node _T_1789 = bits(_WIRE_131, 14, 14) connect _WIRE_130.sw, _T_1789 node _T_1790 = bits(_WIRE_131, 15, 15) connect _WIRE_130.gf, _T_1790 node _T_1791 = bits(_WIRE_131, 16, 16) connect _WIRE_130.pf, _T_1791 node _T_1792 = bits(_WIRE_131, 17, 17) connect _WIRE_130.ae_stage2, _T_1792 node _T_1793 = bits(_WIRE_131, 18, 18) connect _WIRE_130.ae_final, _T_1793 node _T_1794 = bits(_WIRE_131, 19, 19) connect _WIRE_130.ae_ptw, _T_1794 node _T_1795 = bits(_WIRE_131, 20, 20) connect _WIRE_130.g, _T_1795 node _T_1796 = bits(_WIRE_131, 21, 21) connect _WIRE_130.u, _T_1796 node _T_1797 = bits(_WIRE_131, 41, 22) connect _WIRE_130.ppn, _T_1797 wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_133 : UInt<42> connect _WIRE_133, sectored_entries[0][4].data[2] node _T_1798 = bits(_WIRE_133, 0, 0) connect _WIRE_132.fragmented_superpage, _T_1798 node _T_1799 = bits(_WIRE_133, 1, 1) connect _WIRE_132.c, _T_1799 node _T_1800 = bits(_WIRE_133, 2, 2) connect _WIRE_132.eff, _T_1800 node _T_1801 = bits(_WIRE_133, 3, 3) connect _WIRE_132.paa, _T_1801 node _T_1802 = bits(_WIRE_133, 4, 4) connect _WIRE_132.pal, _T_1802 node _T_1803 = bits(_WIRE_133, 5, 5) connect _WIRE_132.ppp, _T_1803 node _T_1804 = bits(_WIRE_133, 6, 6) connect _WIRE_132.pr, _T_1804 node _T_1805 = bits(_WIRE_133, 7, 7) connect _WIRE_132.px, _T_1805 node _T_1806 = bits(_WIRE_133, 8, 8) connect _WIRE_132.pw, _T_1806 node _T_1807 = bits(_WIRE_133, 9, 9) connect _WIRE_132.hr, _T_1807 node _T_1808 = bits(_WIRE_133, 10, 10) connect _WIRE_132.hx, _T_1808 node _T_1809 = bits(_WIRE_133, 11, 11) connect _WIRE_132.hw, _T_1809 node _T_1810 = bits(_WIRE_133, 12, 12) connect _WIRE_132.sr, _T_1810 node _T_1811 = bits(_WIRE_133, 13, 13) connect _WIRE_132.sx, _T_1811 node _T_1812 = bits(_WIRE_133, 14, 14) connect _WIRE_132.sw, _T_1812 node _T_1813 = bits(_WIRE_133, 15, 15) connect _WIRE_132.gf, _T_1813 node _T_1814 = bits(_WIRE_133, 16, 16) connect _WIRE_132.pf, _T_1814 node _T_1815 = bits(_WIRE_133, 17, 17) connect _WIRE_132.ae_stage2, _T_1815 node _T_1816 = bits(_WIRE_133, 18, 18) connect _WIRE_132.ae_final, _T_1816 node _T_1817 = bits(_WIRE_133, 19, 19) connect _WIRE_132.ae_ptw, _T_1817 node _T_1818 = bits(_WIRE_133, 20, 20) connect _WIRE_132.g, _T_1818 node _T_1819 = bits(_WIRE_133, 21, 21) connect _WIRE_132.u, _T_1819 node _T_1820 = bits(_WIRE_133, 41, 22) connect _WIRE_132.ppn, _T_1820 wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_135 : UInt<42> connect _WIRE_135, sectored_entries[0][4].data[3] node _T_1821 = bits(_WIRE_135, 0, 0) connect _WIRE_134.fragmented_superpage, _T_1821 node _T_1822 = bits(_WIRE_135, 1, 1) connect _WIRE_134.c, _T_1822 node _T_1823 = bits(_WIRE_135, 2, 2) connect _WIRE_134.eff, _T_1823 node _T_1824 = bits(_WIRE_135, 3, 3) connect _WIRE_134.paa, _T_1824 node _T_1825 = bits(_WIRE_135, 4, 4) connect _WIRE_134.pal, _T_1825 node _T_1826 = bits(_WIRE_135, 5, 5) connect _WIRE_134.ppp, _T_1826 node _T_1827 = bits(_WIRE_135, 6, 6) connect _WIRE_134.pr, _T_1827 node _T_1828 = bits(_WIRE_135, 7, 7) connect _WIRE_134.px, _T_1828 node _T_1829 = bits(_WIRE_135, 8, 8) connect _WIRE_134.pw, _T_1829 node _T_1830 = bits(_WIRE_135, 9, 9) connect _WIRE_134.hr, _T_1830 node _T_1831 = bits(_WIRE_135, 10, 10) connect _WIRE_134.hx, _T_1831 node _T_1832 = bits(_WIRE_135, 11, 11) connect _WIRE_134.hw, _T_1832 node _T_1833 = bits(_WIRE_135, 12, 12) connect _WIRE_134.sr, _T_1833 node _T_1834 = bits(_WIRE_135, 13, 13) connect _WIRE_134.sx, _T_1834 node _T_1835 = bits(_WIRE_135, 14, 14) connect _WIRE_134.sw, _T_1835 node _T_1836 = bits(_WIRE_135, 15, 15) connect _WIRE_134.gf, _T_1836 node _T_1837 = bits(_WIRE_135, 16, 16) connect _WIRE_134.pf, _T_1837 node _T_1838 = bits(_WIRE_135, 17, 17) connect _WIRE_134.ae_stage2, _T_1838 node _T_1839 = bits(_WIRE_135, 18, 18) connect _WIRE_134.ae_final, _T_1839 node _T_1840 = bits(_WIRE_135, 19, 19) connect _WIRE_134.ae_ptw, _T_1840 node _T_1841 = bits(_WIRE_135, 20, 20) connect _WIRE_134.g, _T_1841 node _T_1842 = bits(_WIRE_135, 21, 21) connect _WIRE_134.u, _T_1842 node _T_1843 = bits(_WIRE_135, 41, 22) connect _WIRE_134.ppn, _T_1843 node _T_1844 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1845 = bits(vpn, 1, 0) node _T_1846 = eq(UInt<1>(0h0), _T_1845) node _T_1847 = and(_T_1844, _T_1846) when _T_1847 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1848 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1849 = bits(vpn, 1, 0) node _T_1850 = eq(UInt<1>(0h1), _T_1849) node _T_1851 = and(_T_1848, _T_1850) when _T_1851 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1852 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1853 = bits(vpn, 1, 0) node _T_1854 = eq(UInt<2>(0h2), _T_1853) node _T_1855 = and(_T_1852, _T_1854) when _T_1855 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1856 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1857 = bits(vpn, 1, 0) node _T_1858 = eq(UInt<2>(0h3), _T_1857) node _T_1859 = and(_T_1856, _T_1858) when _T_1859 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_1860 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1861 = shr(_T_1860, 18) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_137 : UInt<42> connect _WIRE_137, sectored_entries[0][4].data[0] node _T_1863 = bits(_WIRE_137, 0, 0) connect _WIRE_136.fragmented_superpage, _T_1863 node _T_1864 = bits(_WIRE_137, 1, 1) connect _WIRE_136.c, _T_1864 node _T_1865 = bits(_WIRE_137, 2, 2) connect _WIRE_136.eff, _T_1865 node _T_1866 = bits(_WIRE_137, 3, 3) connect _WIRE_136.paa, _T_1866 node _T_1867 = bits(_WIRE_137, 4, 4) connect _WIRE_136.pal, _T_1867 node _T_1868 = bits(_WIRE_137, 5, 5) connect _WIRE_136.ppp, _T_1868 node _T_1869 = bits(_WIRE_137, 6, 6) connect _WIRE_136.pr, _T_1869 node _T_1870 = bits(_WIRE_137, 7, 7) connect _WIRE_136.px, _T_1870 node _T_1871 = bits(_WIRE_137, 8, 8) connect _WIRE_136.pw, _T_1871 node _T_1872 = bits(_WIRE_137, 9, 9) connect _WIRE_136.hr, _T_1872 node _T_1873 = bits(_WIRE_137, 10, 10) connect _WIRE_136.hx, _T_1873 node _T_1874 = bits(_WIRE_137, 11, 11) connect _WIRE_136.hw, _T_1874 node _T_1875 = bits(_WIRE_137, 12, 12) connect _WIRE_136.sr, _T_1875 node _T_1876 = bits(_WIRE_137, 13, 13) connect _WIRE_136.sx, _T_1876 node _T_1877 = bits(_WIRE_137, 14, 14) connect _WIRE_136.sw, _T_1877 node _T_1878 = bits(_WIRE_137, 15, 15) connect _WIRE_136.gf, _T_1878 node _T_1879 = bits(_WIRE_137, 16, 16) connect _WIRE_136.pf, _T_1879 node _T_1880 = bits(_WIRE_137, 17, 17) connect _WIRE_136.ae_stage2, _T_1880 node _T_1881 = bits(_WIRE_137, 18, 18) connect _WIRE_136.ae_final, _T_1881 node _T_1882 = bits(_WIRE_137, 19, 19) connect _WIRE_136.ae_ptw, _T_1882 node _T_1883 = bits(_WIRE_137, 20, 20) connect _WIRE_136.g, _T_1883 node _T_1884 = bits(_WIRE_137, 21, 21) connect _WIRE_136.u, _T_1884 node _T_1885 = bits(_WIRE_137, 41, 22) connect _WIRE_136.ppn, _T_1885 wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_139 : UInt<42> connect _WIRE_139, sectored_entries[0][4].data[1] node _T_1886 = bits(_WIRE_139, 0, 0) connect _WIRE_138.fragmented_superpage, _T_1886 node _T_1887 = bits(_WIRE_139, 1, 1) connect _WIRE_138.c, _T_1887 node _T_1888 = bits(_WIRE_139, 2, 2) connect _WIRE_138.eff, _T_1888 node _T_1889 = bits(_WIRE_139, 3, 3) connect _WIRE_138.paa, _T_1889 node _T_1890 = bits(_WIRE_139, 4, 4) connect _WIRE_138.pal, _T_1890 node _T_1891 = bits(_WIRE_139, 5, 5) connect _WIRE_138.ppp, _T_1891 node _T_1892 = bits(_WIRE_139, 6, 6) connect _WIRE_138.pr, _T_1892 node _T_1893 = bits(_WIRE_139, 7, 7) connect _WIRE_138.px, _T_1893 node _T_1894 = bits(_WIRE_139, 8, 8) connect _WIRE_138.pw, _T_1894 node _T_1895 = bits(_WIRE_139, 9, 9) connect _WIRE_138.hr, _T_1895 node _T_1896 = bits(_WIRE_139, 10, 10) connect _WIRE_138.hx, _T_1896 node _T_1897 = bits(_WIRE_139, 11, 11) connect _WIRE_138.hw, _T_1897 node _T_1898 = bits(_WIRE_139, 12, 12) connect _WIRE_138.sr, _T_1898 node _T_1899 = bits(_WIRE_139, 13, 13) connect _WIRE_138.sx, _T_1899 node _T_1900 = bits(_WIRE_139, 14, 14) connect _WIRE_138.sw, _T_1900 node _T_1901 = bits(_WIRE_139, 15, 15) connect _WIRE_138.gf, _T_1901 node _T_1902 = bits(_WIRE_139, 16, 16) connect _WIRE_138.pf, _T_1902 node _T_1903 = bits(_WIRE_139, 17, 17) connect _WIRE_138.ae_stage2, _T_1903 node _T_1904 = bits(_WIRE_139, 18, 18) connect _WIRE_138.ae_final, _T_1904 node _T_1905 = bits(_WIRE_139, 19, 19) connect _WIRE_138.ae_ptw, _T_1905 node _T_1906 = bits(_WIRE_139, 20, 20) connect _WIRE_138.g, _T_1906 node _T_1907 = bits(_WIRE_139, 21, 21) connect _WIRE_138.u, _T_1907 node _T_1908 = bits(_WIRE_139, 41, 22) connect _WIRE_138.ppn, _T_1908 wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_141 : UInt<42> connect _WIRE_141, sectored_entries[0][4].data[2] node _T_1909 = bits(_WIRE_141, 0, 0) connect _WIRE_140.fragmented_superpage, _T_1909 node _T_1910 = bits(_WIRE_141, 1, 1) connect _WIRE_140.c, _T_1910 node _T_1911 = bits(_WIRE_141, 2, 2) connect _WIRE_140.eff, _T_1911 node _T_1912 = bits(_WIRE_141, 3, 3) connect _WIRE_140.paa, _T_1912 node _T_1913 = bits(_WIRE_141, 4, 4) connect _WIRE_140.pal, _T_1913 node _T_1914 = bits(_WIRE_141, 5, 5) connect _WIRE_140.ppp, _T_1914 node _T_1915 = bits(_WIRE_141, 6, 6) connect _WIRE_140.pr, _T_1915 node _T_1916 = bits(_WIRE_141, 7, 7) connect _WIRE_140.px, _T_1916 node _T_1917 = bits(_WIRE_141, 8, 8) connect _WIRE_140.pw, _T_1917 node _T_1918 = bits(_WIRE_141, 9, 9) connect _WIRE_140.hr, _T_1918 node _T_1919 = bits(_WIRE_141, 10, 10) connect _WIRE_140.hx, _T_1919 node _T_1920 = bits(_WIRE_141, 11, 11) connect _WIRE_140.hw, _T_1920 node _T_1921 = bits(_WIRE_141, 12, 12) connect _WIRE_140.sr, _T_1921 node _T_1922 = bits(_WIRE_141, 13, 13) connect _WIRE_140.sx, _T_1922 node _T_1923 = bits(_WIRE_141, 14, 14) connect _WIRE_140.sw, _T_1923 node _T_1924 = bits(_WIRE_141, 15, 15) connect _WIRE_140.gf, _T_1924 node _T_1925 = bits(_WIRE_141, 16, 16) connect _WIRE_140.pf, _T_1925 node _T_1926 = bits(_WIRE_141, 17, 17) connect _WIRE_140.ae_stage2, _T_1926 node _T_1927 = bits(_WIRE_141, 18, 18) connect _WIRE_140.ae_final, _T_1927 node _T_1928 = bits(_WIRE_141, 19, 19) connect _WIRE_140.ae_ptw, _T_1928 node _T_1929 = bits(_WIRE_141, 20, 20) connect _WIRE_140.g, _T_1929 node _T_1930 = bits(_WIRE_141, 21, 21) connect _WIRE_140.u, _T_1930 node _T_1931 = bits(_WIRE_141, 41, 22) connect _WIRE_140.ppn, _T_1931 wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_143 : UInt<42> connect _WIRE_143, sectored_entries[0][4].data[3] node _T_1932 = bits(_WIRE_143, 0, 0) connect _WIRE_142.fragmented_superpage, _T_1932 node _T_1933 = bits(_WIRE_143, 1, 1) connect _WIRE_142.c, _T_1933 node _T_1934 = bits(_WIRE_143, 2, 2) connect _WIRE_142.eff, _T_1934 node _T_1935 = bits(_WIRE_143, 3, 3) connect _WIRE_142.paa, _T_1935 node _T_1936 = bits(_WIRE_143, 4, 4) connect _WIRE_142.pal, _T_1936 node _T_1937 = bits(_WIRE_143, 5, 5) connect _WIRE_142.ppp, _T_1937 node _T_1938 = bits(_WIRE_143, 6, 6) connect _WIRE_142.pr, _T_1938 node _T_1939 = bits(_WIRE_143, 7, 7) connect _WIRE_142.px, _T_1939 node _T_1940 = bits(_WIRE_143, 8, 8) connect _WIRE_142.pw, _T_1940 node _T_1941 = bits(_WIRE_143, 9, 9) connect _WIRE_142.hr, _T_1941 node _T_1942 = bits(_WIRE_143, 10, 10) connect _WIRE_142.hx, _T_1942 node _T_1943 = bits(_WIRE_143, 11, 11) connect _WIRE_142.hw, _T_1943 node _T_1944 = bits(_WIRE_143, 12, 12) connect _WIRE_142.sr, _T_1944 node _T_1945 = bits(_WIRE_143, 13, 13) connect _WIRE_142.sx, _T_1945 node _T_1946 = bits(_WIRE_143, 14, 14) connect _WIRE_142.sw, _T_1946 node _T_1947 = bits(_WIRE_143, 15, 15) connect _WIRE_142.gf, _T_1947 node _T_1948 = bits(_WIRE_143, 16, 16) connect _WIRE_142.pf, _T_1948 node _T_1949 = bits(_WIRE_143, 17, 17) connect _WIRE_142.ae_stage2, _T_1949 node _T_1950 = bits(_WIRE_143, 18, 18) connect _WIRE_142.ae_final, _T_1950 node _T_1951 = bits(_WIRE_143, 19, 19) connect _WIRE_142.ae_ptw, _T_1951 node _T_1952 = bits(_WIRE_143, 20, 20) connect _WIRE_142.g, _T_1952 node _T_1953 = bits(_WIRE_143, 21, 21) connect _WIRE_142.u, _T_1953 node _T_1954 = bits(_WIRE_143, 41, 22) connect _WIRE_142.ppn, _T_1954 node _T_1955 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1956 = and(_T_1955, _WIRE_136.fragmented_superpage) when _T_1956 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1957 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1958 = and(_T_1957, _WIRE_138.fragmented_superpage) when _T_1958 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1959 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1960 = and(_T_1959, _WIRE_140.fragmented_superpage) when _T_1960 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1961 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1962 = and(_T_1961, _WIRE_142.fragmented_superpage) when _T_1962 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_1963 = eq(hg_4, UInt<1>(0h0)) node _T_1964 = and(_T_1963, io.sfence.bits.rs2) when _T_1964 : wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_145 : UInt<42> connect _WIRE_145, sectored_entries[0][4].data[0] node _T_1965 = bits(_WIRE_145, 0, 0) connect _WIRE_144.fragmented_superpage, _T_1965 node _T_1966 = bits(_WIRE_145, 1, 1) connect _WIRE_144.c, _T_1966 node _T_1967 = bits(_WIRE_145, 2, 2) connect _WIRE_144.eff, _T_1967 node _T_1968 = bits(_WIRE_145, 3, 3) connect _WIRE_144.paa, _T_1968 node _T_1969 = bits(_WIRE_145, 4, 4) connect _WIRE_144.pal, _T_1969 node _T_1970 = bits(_WIRE_145, 5, 5) connect _WIRE_144.ppp, _T_1970 node _T_1971 = bits(_WIRE_145, 6, 6) connect _WIRE_144.pr, _T_1971 node _T_1972 = bits(_WIRE_145, 7, 7) connect _WIRE_144.px, _T_1972 node _T_1973 = bits(_WIRE_145, 8, 8) connect _WIRE_144.pw, _T_1973 node _T_1974 = bits(_WIRE_145, 9, 9) connect _WIRE_144.hr, _T_1974 node _T_1975 = bits(_WIRE_145, 10, 10) connect _WIRE_144.hx, _T_1975 node _T_1976 = bits(_WIRE_145, 11, 11) connect _WIRE_144.hw, _T_1976 node _T_1977 = bits(_WIRE_145, 12, 12) connect _WIRE_144.sr, _T_1977 node _T_1978 = bits(_WIRE_145, 13, 13) connect _WIRE_144.sx, _T_1978 node _T_1979 = bits(_WIRE_145, 14, 14) connect _WIRE_144.sw, _T_1979 node _T_1980 = bits(_WIRE_145, 15, 15) connect _WIRE_144.gf, _T_1980 node _T_1981 = bits(_WIRE_145, 16, 16) connect _WIRE_144.pf, _T_1981 node _T_1982 = bits(_WIRE_145, 17, 17) connect _WIRE_144.ae_stage2, _T_1982 node _T_1983 = bits(_WIRE_145, 18, 18) connect _WIRE_144.ae_final, _T_1983 node _T_1984 = bits(_WIRE_145, 19, 19) connect _WIRE_144.ae_ptw, _T_1984 node _T_1985 = bits(_WIRE_145, 20, 20) connect _WIRE_144.g, _T_1985 node _T_1986 = bits(_WIRE_145, 21, 21) connect _WIRE_144.u, _T_1986 node _T_1987 = bits(_WIRE_145, 41, 22) connect _WIRE_144.ppn, _T_1987 wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_147 : UInt<42> connect _WIRE_147, sectored_entries[0][4].data[1] node _T_1988 = bits(_WIRE_147, 0, 0) connect _WIRE_146.fragmented_superpage, _T_1988 node _T_1989 = bits(_WIRE_147, 1, 1) connect _WIRE_146.c, _T_1989 node _T_1990 = bits(_WIRE_147, 2, 2) connect _WIRE_146.eff, _T_1990 node _T_1991 = bits(_WIRE_147, 3, 3) connect _WIRE_146.paa, _T_1991 node _T_1992 = bits(_WIRE_147, 4, 4) connect _WIRE_146.pal, _T_1992 node _T_1993 = bits(_WIRE_147, 5, 5) connect _WIRE_146.ppp, _T_1993 node _T_1994 = bits(_WIRE_147, 6, 6) connect _WIRE_146.pr, _T_1994 node _T_1995 = bits(_WIRE_147, 7, 7) connect _WIRE_146.px, _T_1995 node _T_1996 = bits(_WIRE_147, 8, 8) connect _WIRE_146.pw, _T_1996 node _T_1997 = bits(_WIRE_147, 9, 9) connect _WIRE_146.hr, _T_1997 node _T_1998 = bits(_WIRE_147, 10, 10) connect _WIRE_146.hx, _T_1998 node _T_1999 = bits(_WIRE_147, 11, 11) connect _WIRE_146.hw, _T_1999 node _T_2000 = bits(_WIRE_147, 12, 12) connect _WIRE_146.sr, _T_2000 node _T_2001 = bits(_WIRE_147, 13, 13) connect _WIRE_146.sx, _T_2001 node _T_2002 = bits(_WIRE_147, 14, 14) connect _WIRE_146.sw, _T_2002 node _T_2003 = bits(_WIRE_147, 15, 15) connect _WIRE_146.gf, _T_2003 node _T_2004 = bits(_WIRE_147, 16, 16) connect _WIRE_146.pf, _T_2004 node _T_2005 = bits(_WIRE_147, 17, 17) connect _WIRE_146.ae_stage2, _T_2005 node _T_2006 = bits(_WIRE_147, 18, 18) connect _WIRE_146.ae_final, _T_2006 node _T_2007 = bits(_WIRE_147, 19, 19) connect _WIRE_146.ae_ptw, _T_2007 node _T_2008 = bits(_WIRE_147, 20, 20) connect _WIRE_146.g, _T_2008 node _T_2009 = bits(_WIRE_147, 21, 21) connect _WIRE_146.u, _T_2009 node _T_2010 = bits(_WIRE_147, 41, 22) connect _WIRE_146.ppn, _T_2010 wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_149 : UInt<42> connect _WIRE_149, sectored_entries[0][4].data[2] node _T_2011 = bits(_WIRE_149, 0, 0) connect _WIRE_148.fragmented_superpage, _T_2011 node _T_2012 = bits(_WIRE_149, 1, 1) connect _WIRE_148.c, _T_2012 node _T_2013 = bits(_WIRE_149, 2, 2) connect _WIRE_148.eff, _T_2013 node _T_2014 = bits(_WIRE_149, 3, 3) connect _WIRE_148.paa, _T_2014 node _T_2015 = bits(_WIRE_149, 4, 4) connect _WIRE_148.pal, _T_2015 node _T_2016 = bits(_WIRE_149, 5, 5) connect _WIRE_148.ppp, _T_2016 node _T_2017 = bits(_WIRE_149, 6, 6) connect _WIRE_148.pr, _T_2017 node _T_2018 = bits(_WIRE_149, 7, 7) connect _WIRE_148.px, _T_2018 node _T_2019 = bits(_WIRE_149, 8, 8) connect _WIRE_148.pw, _T_2019 node _T_2020 = bits(_WIRE_149, 9, 9) connect _WIRE_148.hr, _T_2020 node _T_2021 = bits(_WIRE_149, 10, 10) connect _WIRE_148.hx, _T_2021 node _T_2022 = bits(_WIRE_149, 11, 11) connect _WIRE_148.hw, _T_2022 node _T_2023 = bits(_WIRE_149, 12, 12) connect _WIRE_148.sr, _T_2023 node _T_2024 = bits(_WIRE_149, 13, 13) connect _WIRE_148.sx, _T_2024 node _T_2025 = bits(_WIRE_149, 14, 14) connect _WIRE_148.sw, _T_2025 node _T_2026 = bits(_WIRE_149, 15, 15) connect _WIRE_148.gf, _T_2026 node _T_2027 = bits(_WIRE_149, 16, 16) connect _WIRE_148.pf, _T_2027 node _T_2028 = bits(_WIRE_149, 17, 17) connect _WIRE_148.ae_stage2, _T_2028 node _T_2029 = bits(_WIRE_149, 18, 18) connect _WIRE_148.ae_final, _T_2029 node _T_2030 = bits(_WIRE_149, 19, 19) connect _WIRE_148.ae_ptw, _T_2030 node _T_2031 = bits(_WIRE_149, 20, 20) connect _WIRE_148.g, _T_2031 node _T_2032 = bits(_WIRE_149, 21, 21) connect _WIRE_148.u, _T_2032 node _T_2033 = bits(_WIRE_149, 41, 22) connect _WIRE_148.ppn, _T_2033 wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_151 : UInt<42> connect _WIRE_151, sectored_entries[0][4].data[3] node _T_2034 = bits(_WIRE_151, 0, 0) connect _WIRE_150.fragmented_superpage, _T_2034 node _T_2035 = bits(_WIRE_151, 1, 1) connect _WIRE_150.c, _T_2035 node _T_2036 = bits(_WIRE_151, 2, 2) connect _WIRE_150.eff, _T_2036 node _T_2037 = bits(_WIRE_151, 3, 3) connect _WIRE_150.paa, _T_2037 node _T_2038 = bits(_WIRE_151, 4, 4) connect _WIRE_150.pal, _T_2038 node _T_2039 = bits(_WIRE_151, 5, 5) connect _WIRE_150.ppp, _T_2039 node _T_2040 = bits(_WIRE_151, 6, 6) connect _WIRE_150.pr, _T_2040 node _T_2041 = bits(_WIRE_151, 7, 7) connect _WIRE_150.px, _T_2041 node _T_2042 = bits(_WIRE_151, 8, 8) connect _WIRE_150.pw, _T_2042 node _T_2043 = bits(_WIRE_151, 9, 9) connect _WIRE_150.hr, _T_2043 node _T_2044 = bits(_WIRE_151, 10, 10) connect _WIRE_150.hx, _T_2044 node _T_2045 = bits(_WIRE_151, 11, 11) connect _WIRE_150.hw, _T_2045 node _T_2046 = bits(_WIRE_151, 12, 12) connect _WIRE_150.sr, _T_2046 node _T_2047 = bits(_WIRE_151, 13, 13) connect _WIRE_150.sx, _T_2047 node _T_2048 = bits(_WIRE_151, 14, 14) connect _WIRE_150.sw, _T_2048 node _T_2049 = bits(_WIRE_151, 15, 15) connect _WIRE_150.gf, _T_2049 node _T_2050 = bits(_WIRE_151, 16, 16) connect _WIRE_150.pf, _T_2050 node _T_2051 = bits(_WIRE_151, 17, 17) connect _WIRE_150.ae_stage2, _T_2051 node _T_2052 = bits(_WIRE_151, 18, 18) connect _WIRE_150.ae_final, _T_2052 node _T_2053 = bits(_WIRE_151, 19, 19) connect _WIRE_150.ae_ptw, _T_2053 node _T_2054 = bits(_WIRE_151, 20, 20) connect _WIRE_150.g, _T_2054 node _T_2055 = bits(_WIRE_151, 21, 21) connect _WIRE_150.u, _T_2055 node _T_2056 = bits(_WIRE_151, 41, 22) connect _WIRE_150.ppn, _T_2056 node _T_2057 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2058 = eq(_WIRE_144.g, UInt<1>(0h0)) node _T_2059 = and(_T_2057, _T_2058) when _T_2059 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2060 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2061 = eq(_WIRE_146.g, UInt<1>(0h0)) node _T_2062 = and(_T_2060, _T_2061) when _T_2062 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2063 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2064 = eq(_WIRE_148.g, UInt<1>(0h0)) node _T_2065 = and(_T_2063, _T_2064) when _T_2065 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2066 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2067 = eq(_WIRE_150.g, UInt<1>(0h0)) node _T_2068 = and(_T_2066, _T_2067) when _T_2068 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_2069 = or(hv_4, hg_4) wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_153 : UInt<42> connect _WIRE_153, sectored_entries[0][4].data[0] node _T_2070 = bits(_WIRE_153, 0, 0) connect _WIRE_152.fragmented_superpage, _T_2070 node _T_2071 = bits(_WIRE_153, 1, 1) connect _WIRE_152.c, _T_2071 node _T_2072 = bits(_WIRE_153, 2, 2) connect _WIRE_152.eff, _T_2072 node _T_2073 = bits(_WIRE_153, 3, 3) connect _WIRE_152.paa, _T_2073 node _T_2074 = bits(_WIRE_153, 4, 4) connect _WIRE_152.pal, _T_2074 node _T_2075 = bits(_WIRE_153, 5, 5) connect _WIRE_152.ppp, _T_2075 node _T_2076 = bits(_WIRE_153, 6, 6) connect _WIRE_152.pr, _T_2076 node _T_2077 = bits(_WIRE_153, 7, 7) connect _WIRE_152.px, _T_2077 node _T_2078 = bits(_WIRE_153, 8, 8) connect _WIRE_152.pw, _T_2078 node _T_2079 = bits(_WIRE_153, 9, 9) connect _WIRE_152.hr, _T_2079 node _T_2080 = bits(_WIRE_153, 10, 10) connect _WIRE_152.hx, _T_2080 node _T_2081 = bits(_WIRE_153, 11, 11) connect _WIRE_152.hw, _T_2081 node _T_2082 = bits(_WIRE_153, 12, 12) connect _WIRE_152.sr, _T_2082 node _T_2083 = bits(_WIRE_153, 13, 13) connect _WIRE_152.sx, _T_2083 node _T_2084 = bits(_WIRE_153, 14, 14) connect _WIRE_152.sw, _T_2084 node _T_2085 = bits(_WIRE_153, 15, 15) connect _WIRE_152.gf, _T_2085 node _T_2086 = bits(_WIRE_153, 16, 16) connect _WIRE_152.pf, _T_2086 node _T_2087 = bits(_WIRE_153, 17, 17) connect _WIRE_152.ae_stage2, _T_2087 node _T_2088 = bits(_WIRE_153, 18, 18) connect _WIRE_152.ae_final, _T_2088 node _T_2089 = bits(_WIRE_153, 19, 19) connect _WIRE_152.ae_ptw, _T_2089 node _T_2090 = bits(_WIRE_153, 20, 20) connect _WIRE_152.g, _T_2090 node _T_2091 = bits(_WIRE_153, 21, 21) connect _WIRE_152.u, _T_2091 node _T_2092 = bits(_WIRE_153, 41, 22) connect _WIRE_152.ppn, _T_2092 wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_155 : UInt<42> connect _WIRE_155, sectored_entries[0][4].data[1] node _T_2093 = bits(_WIRE_155, 0, 0) connect _WIRE_154.fragmented_superpage, _T_2093 node _T_2094 = bits(_WIRE_155, 1, 1) connect _WIRE_154.c, _T_2094 node _T_2095 = bits(_WIRE_155, 2, 2) connect _WIRE_154.eff, _T_2095 node _T_2096 = bits(_WIRE_155, 3, 3) connect _WIRE_154.paa, _T_2096 node _T_2097 = bits(_WIRE_155, 4, 4) connect _WIRE_154.pal, _T_2097 node _T_2098 = bits(_WIRE_155, 5, 5) connect _WIRE_154.ppp, _T_2098 node _T_2099 = bits(_WIRE_155, 6, 6) connect _WIRE_154.pr, _T_2099 node _T_2100 = bits(_WIRE_155, 7, 7) connect _WIRE_154.px, _T_2100 node _T_2101 = bits(_WIRE_155, 8, 8) connect _WIRE_154.pw, _T_2101 node _T_2102 = bits(_WIRE_155, 9, 9) connect _WIRE_154.hr, _T_2102 node _T_2103 = bits(_WIRE_155, 10, 10) connect _WIRE_154.hx, _T_2103 node _T_2104 = bits(_WIRE_155, 11, 11) connect _WIRE_154.hw, _T_2104 node _T_2105 = bits(_WIRE_155, 12, 12) connect _WIRE_154.sr, _T_2105 node _T_2106 = bits(_WIRE_155, 13, 13) connect _WIRE_154.sx, _T_2106 node _T_2107 = bits(_WIRE_155, 14, 14) connect _WIRE_154.sw, _T_2107 node _T_2108 = bits(_WIRE_155, 15, 15) connect _WIRE_154.gf, _T_2108 node _T_2109 = bits(_WIRE_155, 16, 16) connect _WIRE_154.pf, _T_2109 node _T_2110 = bits(_WIRE_155, 17, 17) connect _WIRE_154.ae_stage2, _T_2110 node _T_2111 = bits(_WIRE_155, 18, 18) connect _WIRE_154.ae_final, _T_2111 node _T_2112 = bits(_WIRE_155, 19, 19) connect _WIRE_154.ae_ptw, _T_2112 node _T_2113 = bits(_WIRE_155, 20, 20) connect _WIRE_154.g, _T_2113 node _T_2114 = bits(_WIRE_155, 21, 21) connect _WIRE_154.u, _T_2114 node _T_2115 = bits(_WIRE_155, 41, 22) connect _WIRE_154.ppn, _T_2115 wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_157 : UInt<42> connect _WIRE_157, sectored_entries[0][4].data[2] node _T_2116 = bits(_WIRE_157, 0, 0) connect _WIRE_156.fragmented_superpage, _T_2116 node _T_2117 = bits(_WIRE_157, 1, 1) connect _WIRE_156.c, _T_2117 node _T_2118 = bits(_WIRE_157, 2, 2) connect _WIRE_156.eff, _T_2118 node _T_2119 = bits(_WIRE_157, 3, 3) connect _WIRE_156.paa, _T_2119 node _T_2120 = bits(_WIRE_157, 4, 4) connect _WIRE_156.pal, _T_2120 node _T_2121 = bits(_WIRE_157, 5, 5) connect _WIRE_156.ppp, _T_2121 node _T_2122 = bits(_WIRE_157, 6, 6) connect _WIRE_156.pr, _T_2122 node _T_2123 = bits(_WIRE_157, 7, 7) connect _WIRE_156.px, _T_2123 node _T_2124 = bits(_WIRE_157, 8, 8) connect _WIRE_156.pw, _T_2124 node _T_2125 = bits(_WIRE_157, 9, 9) connect _WIRE_156.hr, _T_2125 node _T_2126 = bits(_WIRE_157, 10, 10) connect _WIRE_156.hx, _T_2126 node _T_2127 = bits(_WIRE_157, 11, 11) connect _WIRE_156.hw, _T_2127 node _T_2128 = bits(_WIRE_157, 12, 12) connect _WIRE_156.sr, _T_2128 node _T_2129 = bits(_WIRE_157, 13, 13) connect _WIRE_156.sx, _T_2129 node _T_2130 = bits(_WIRE_157, 14, 14) connect _WIRE_156.sw, _T_2130 node _T_2131 = bits(_WIRE_157, 15, 15) connect _WIRE_156.gf, _T_2131 node _T_2132 = bits(_WIRE_157, 16, 16) connect _WIRE_156.pf, _T_2132 node _T_2133 = bits(_WIRE_157, 17, 17) connect _WIRE_156.ae_stage2, _T_2133 node _T_2134 = bits(_WIRE_157, 18, 18) connect _WIRE_156.ae_final, _T_2134 node _T_2135 = bits(_WIRE_157, 19, 19) connect _WIRE_156.ae_ptw, _T_2135 node _T_2136 = bits(_WIRE_157, 20, 20) connect _WIRE_156.g, _T_2136 node _T_2137 = bits(_WIRE_157, 21, 21) connect _WIRE_156.u, _T_2137 node _T_2138 = bits(_WIRE_157, 41, 22) connect _WIRE_156.ppn, _T_2138 wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_159 : UInt<42> connect _WIRE_159, sectored_entries[0][4].data[3] node _T_2139 = bits(_WIRE_159, 0, 0) connect _WIRE_158.fragmented_superpage, _T_2139 node _T_2140 = bits(_WIRE_159, 1, 1) connect _WIRE_158.c, _T_2140 node _T_2141 = bits(_WIRE_159, 2, 2) connect _WIRE_158.eff, _T_2141 node _T_2142 = bits(_WIRE_159, 3, 3) connect _WIRE_158.paa, _T_2142 node _T_2143 = bits(_WIRE_159, 4, 4) connect _WIRE_158.pal, _T_2143 node _T_2144 = bits(_WIRE_159, 5, 5) connect _WIRE_158.ppp, _T_2144 node _T_2145 = bits(_WIRE_159, 6, 6) connect _WIRE_158.pr, _T_2145 node _T_2146 = bits(_WIRE_159, 7, 7) connect _WIRE_158.px, _T_2146 node _T_2147 = bits(_WIRE_159, 8, 8) connect _WIRE_158.pw, _T_2147 node _T_2148 = bits(_WIRE_159, 9, 9) connect _WIRE_158.hr, _T_2148 node _T_2149 = bits(_WIRE_159, 10, 10) connect _WIRE_158.hx, _T_2149 node _T_2150 = bits(_WIRE_159, 11, 11) connect _WIRE_158.hw, _T_2150 node _T_2151 = bits(_WIRE_159, 12, 12) connect _WIRE_158.sr, _T_2151 node _T_2152 = bits(_WIRE_159, 13, 13) connect _WIRE_158.sx, _T_2152 node _T_2153 = bits(_WIRE_159, 14, 14) connect _WIRE_158.sw, _T_2153 node _T_2154 = bits(_WIRE_159, 15, 15) connect _WIRE_158.gf, _T_2154 node _T_2155 = bits(_WIRE_159, 16, 16) connect _WIRE_158.pf, _T_2155 node _T_2156 = bits(_WIRE_159, 17, 17) connect _WIRE_158.ae_stage2, _T_2156 node _T_2157 = bits(_WIRE_159, 18, 18) connect _WIRE_158.ae_final, _T_2157 node _T_2158 = bits(_WIRE_159, 19, 19) connect _WIRE_158.ae_ptw, _T_2158 node _T_2159 = bits(_WIRE_159, 20, 20) connect _WIRE_158.g, _T_2159 node _T_2160 = bits(_WIRE_159, 21, 21) connect _WIRE_158.u, _T_2160 node _T_2161 = bits(_WIRE_159, 41, 22) connect _WIRE_158.ppn, _T_2161 node _T_2162 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2162 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2163 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2163 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2164 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2164 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2165 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2165 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2166 = eq(hg_5, UInt<1>(0h0)) node _T_2167 = and(_T_2166, io.sfence.bits.rs1) when _T_2167 : node _T_2168 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2169 = shr(_T_2168, 2) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) node _T_2171 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2172 = and(_T_2170, _T_2171) when _T_2172 : wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_161 : UInt<42> connect _WIRE_161, sectored_entries[0][5].data[0] node _T_2173 = bits(_WIRE_161, 0, 0) connect _WIRE_160.fragmented_superpage, _T_2173 node _T_2174 = bits(_WIRE_161, 1, 1) connect _WIRE_160.c, _T_2174 node _T_2175 = bits(_WIRE_161, 2, 2) connect _WIRE_160.eff, _T_2175 node _T_2176 = bits(_WIRE_161, 3, 3) connect _WIRE_160.paa, _T_2176 node _T_2177 = bits(_WIRE_161, 4, 4) connect _WIRE_160.pal, _T_2177 node _T_2178 = bits(_WIRE_161, 5, 5) connect _WIRE_160.ppp, _T_2178 node _T_2179 = bits(_WIRE_161, 6, 6) connect _WIRE_160.pr, _T_2179 node _T_2180 = bits(_WIRE_161, 7, 7) connect _WIRE_160.px, _T_2180 node _T_2181 = bits(_WIRE_161, 8, 8) connect _WIRE_160.pw, _T_2181 node _T_2182 = bits(_WIRE_161, 9, 9) connect _WIRE_160.hr, _T_2182 node _T_2183 = bits(_WIRE_161, 10, 10) connect _WIRE_160.hx, _T_2183 node _T_2184 = bits(_WIRE_161, 11, 11) connect _WIRE_160.hw, _T_2184 node _T_2185 = bits(_WIRE_161, 12, 12) connect _WIRE_160.sr, _T_2185 node _T_2186 = bits(_WIRE_161, 13, 13) connect _WIRE_160.sx, _T_2186 node _T_2187 = bits(_WIRE_161, 14, 14) connect _WIRE_160.sw, _T_2187 node _T_2188 = bits(_WIRE_161, 15, 15) connect _WIRE_160.gf, _T_2188 node _T_2189 = bits(_WIRE_161, 16, 16) connect _WIRE_160.pf, _T_2189 node _T_2190 = bits(_WIRE_161, 17, 17) connect _WIRE_160.ae_stage2, _T_2190 node _T_2191 = bits(_WIRE_161, 18, 18) connect _WIRE_160.ae_final, _T_2191 node _T_2192 = bits(_WIRE_161, 19, 19) connect _WIRE_160.ae_ptw, _T_2192 node _T_2193 = bits(_WIRE_161, 20, 20) connect _WIRE_160.g, _T_2193 node _T_2194 = bits(_WIRE_161, 21, 21) connect _WIRE_160.u, _T_2194 node _T_2195 = bits(_WIRE_161, 41, 22) connect _WIRE_160.ppn, _T_2195 wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_163 : UInt<42> connect _WIRE_163, sectored_entries[0][5].data[1] node _T_2196 = bits(_WIRE_163, 0, 0) connect _WIRE_162.fragmented_superpage, _T_2196 node _T_2197 = bits(_WIRE_163, 1, 1) connect _WIRE_162.c, _T_2197 node _T_2198 = bits(_WIRE_163, 2, 2) connect _WIRE_162.eff, _T_2198 node _T_2199 = bits(_WIRE_163, 3, 3) connect _WIRE_162.paa, _T_2199 node _T_2200 = bits(_WIRE_163, 4, 4) connect _WIRE_162.pal, _T_2200 node _T_2201 = bits(_WIRE_163, 5, 5) connect _WIRE_162.ppp, _T_2201 node _T_2202 = bits(_WIRE_163, 6, 6) connect _WIRE_162.pr, _T_2202 node _T_2203 = bits(_WIRE_163, 7, 7) connect _WIRE_162.px, _T_2203 node _T_2204 = bits(_WIRE_163, 8, 8) connect _WIRE_162.pw, _T_2204 node _T_2205 = bits(_WIRE_163, 9, 9) connect _WIRE_162.hr, _T_2205 node _T_2206 = bits(_WIRE_163, 10, 10) connect _WIRE_162.hx, _T_2206 node _T_2207 = bits(_WIRE_163, 11, 11) connect _WIRE_162.hw, _T_2207 node _T_2208 = bits(_WIRE_163, 12, 12) connect _WIRE_162.sr, _T_2208 node _T_2209 = bits(_WIRE_163, 13, 13) connect _WIRE_162.sx, _T_2209 node _T_2210 = bits(_WIRE_163, 14, 14) connect _WIRE_162.sw, _T_2210 node _T_2211 = bits(_WIRE_163, 15, 15) connect _WIRE_162.gf, _T_2211 node _T_2212 = bits(_WIRE_163, 16, 16) connect _WIRE_162.pf, _T_2212 node _T_2213 = bits(_WIRE_163, 17, 17) connect _WIRE_162.ae_stage2, _T_2213 node _T_2214 = bits(_WIRE_163, 18, 18) connect _WIRE_162.ae_final, _T_2214 node _T_2215 = bits(_WIRE_163, 19, 19) connect _WIRE_162.ae_ptw, _T_2215 node _T_2216 = bits(_WIRE_163, 20, 20) connect _WIRE_162.g, _T_2216 node _T_2217 = bits(_WIRE_163, 21, 21) connect _WIRE_162.u, _T_2217 node _T_2218 = bits(_WIRE_163, 41, 22) connect _WIRE_162.ppn, _T_2218 wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_165 : UInt<42> connect _WIRE_165, sectored_entries[0][5].data[2] node _T_2219 = bits(_WIRE_165, 0, 0) connect _WIRE_164.fragmented_superpage, _T_2219 node _T_2220 = bits(_WIRE_165, 1, 1) connect _WIRE_164.c, _T_2220 node _T_2221 = bits(_WIRE_165, 2, 2) connect _WIRE_164.eff, _T_2221 node _T_2222 = bits(_WIRE_165, 3, 3) connect _WIRE_164.paa, _T_2222 node _T_2223 = bits(_WIRE_165, 4, 4) connect _WIRE_164.pal, _T_2223 node _T_2224 = bits(_WIRE_165, 5, 5) connect _WIRE_164.ppp, _T_2224 node _T_2225 = bits(_WIRE_165, 6, 6) connect _WIRE_164.pr, _T_2225 node _T_2226 = bits(_WIRE_165, 7, 7) connect _WIRE_164.px, _T_2226 node _T_2227 = bits(_WIRE_165, 8, 8) connect _WIRE_164.pw, _T_2227 node _T_2228 = bits(_WIRE_165, 9, 9) connect _WIRE_164.hr, _T_2228 node _T_2229 = bits(_WIRE_165, 10, 10) connect _WIRE_164.hx, _T_2229 node _T_2230 = bits(_WIRE_165, 11, 11) connect _WIRE_164.hw, _T_2230 node _T_2231 = bits(_WIRE_165, 12, 12) connect _WIRE_164.sr, _T_2231 node _T_2232 = bits(_WIRE_165, 13, 13) connect _WIRE_164.sx, _T_2232 node _T_2233 = bits(_WIRE_165, 14, 14) connect _WIRE_164.sw, _T_2233 node _T_2234 = bits(_WIRE_165, 15, 15) connect _WIRE_164.gf, _T_2234 node _T_2235 = bits(_WIRE_165, 16, 16) connect _WIRE_164.pf, _T_2235 node _T_2236 = bits(_WIRE_165, 17, 17) connect _WIRE_164.ae_stage2, _T_2236 node _T_2237 = bits(_WIRE_165, 18, 18) connect _WIRE_164.ae_final, _T_2237 node _T_2238 = bits(_WIRE_165, 19, 19) connect _WIRE_164.ae_ptw, _T_2238 node _T_2239 = bits(_WIRE_165, 20, 20) connect _WIRE_164.g, _T_2239 node _T_2240 = bits(_WIRE_165, 21, 21) connect _WIRE_164.u, _T_2240 node _T_2241 = bits(_WIRE_165, 41, 22) connect _WIRE_164.ppn, _T_2241 wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_167 : UInt<42> connect _WIRE_167, sectored_entries[0][5].data[3] node _T_2242 = bits(_WIRE_167, 0, 0) connect _WIRE_166.fragmented_superpage, _T_2242 node _T_2243 = bits(_WIRE_167, 1, 1) connect _WIRE_166.c, _T_2243 node _T_2244 = bits(_WIRE_167, 2, 2) connect _WIRE_166.eff, _T_2244 node _T_2245 = bits(_WIRE_167, 3, 3) connect _WIRE_166.paa, _T_2245 node _T_2246 = bits(_WIRE_167, 4, 4) connect _WIRE_166.pal, _T_2246 node _T_2247 = bits(_WIRE_167, 5, 5) connect _WIRE_166.ppp, _T_2247 node _T_2248 = bits(_WIRE_167, 6, 6) connect _WIRE_166.pr, _T_2248 node _T_2249 = bits(_WIRE_167, 7, 7) connect _WIRE_166.px, _T_2249 node _T_2250 = bits(_WIRE_167, 8, 8) connect _WIRE_166.pw, _T_2250 node _T_2251 = bits(_WIRE_167, 9, 9) connect _WIRE_166.hr, _T_2251 node _T_2252 = bits(_WIRE_167, 10, 10) connect _WIRE_166.hx, _T_2252 node _T_2253 = bits(_WIRE_167, 11, 11) connect _WIRE_166.hw, _T_2253 node _T_2254 = bits(_WIRE_167, 12, 12) connect _WIRE_166.sr, _T_2254 node _T_2255 = bits(_WIRE_167, 13, 13) connect _WIRE_166.sx, _T_2255 node _T_2256 = bits(_WIRE_167, 14, 14) connect _WIRE_166.sw, _T_2256 node _T_2257 = bits(_WIRE_167, 15, 15) connect _WIRE_166.gf, _T_2257 node _T_2258 = bits(_WIRE_167, 16, 16) connect _WIRE_166.pf, _T_2258 node _T_2259 = bits(_WIRE_167, 17, 17) connect _WIRE_166.ae_stage2, _T_2259 node _T_2260 = bits(_WIRE_167, 18, 18) connect _WIRE_166.ae_final, _T_2260 node _T_2261 = bits(_WIRE_167, 19, 19) connect _WIRE_166.ae_ptw, _T_2261 node _T_2262 = bits(_WIRE_167, 20, 20) connect _WIRE_166.g, _T_2262 node _T_2263 = bits(_WIRE_167, 21, 21) connect _WIRE_166.u, _T_2263 node _T_2264 = bits(_WIRE_167, 41, 22) connect _WIRE_166.ppn, _T_2264 node _T_2265 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2266 = bits(vpn, 1, 0) node _T_2267 = eq(UInt<1>(0h0), _T_2266) node _T_2268 = and(_T_2265, _T_2267) when _T_2268 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2269 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2270 = bits(vpn, 1, 0) node _T_2271 = eq(UInt<1>(0h1), _T_2270) node _T_2272 = and(_T_2269, _T_2271) when _T_2272 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2273 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2274 = bits(vpn, 1, 0) node _T_2275 = eq(UInt<2>(0h2), _T_2274) node _T_2276 = and(_T_2273, _T_2275) when _T_2276 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2277 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2278 = bits(vpn, 1, 0) node _T_2279 = eq(UInt<2>(0h3), _T_2278) node _T_2280 = and(_T_2277, _T_2279) when _T_2280 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_2281 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2282 = shr(_T_2281, 18) node _T_2283 = eq(_T_2282, UInt<1>(0h0)) when _T_2283 : wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_169 : UInt<42> connect _WIRE_169, sectored_entries[0][5].data[0] node _T_2284 = bits(_WIRE_169, 0, 0) connect _WIRE_168.fragmented_superpage, _T_2284 node _T_2285 = bits(_WIRE_169, 1, 1) connect _WIRE_168.c, _T_2285 node _T_2286 = bits(_WIRE_169, 2, 2) connect _WIRE_168.eff, _T_2286 node _T_2287 = bits(_WIRE_169, 3, 3) connect _WIRE_168.paa, _T_2287 node _T_2288 = bits(_WIRE_169, 4, 4) connect _WIRE_168.pal, _T_2288 node _T_2289 = bits(_WIRE_169, 5, 5) connect _WIRE_168.ppp, _T_2289 node _T_2290 = bits(_WIRE_169, 6, 6) connect _WIRE_168.pr, _T_2290 node _T_2291 = bits(_WIRE_169, 7, 7) connect _WIRE_168.px, _T_2291 node _T_2292 = bits(_WIRE_169, 8, 8) connect _WIRE_168.pw, _T_2292 node _T_2293 = bits(_WIRE_169, 9, 9) connect _WIRE_168.hr, _T_2293 node _T_2294 = bits(_WIRE_169, 10, 10) connect _WIRE_168.hx, _T_2294 node _T_2295 = bits(_WIRE_169, 11, 11) connect _WIRE_168.hw, _T_2295 node _T_2296 = bits(_WIRE_169, 12, 12) connect _WIRE_168.sr, _T_2296 node _T_2297 = bits(_WIRE_169, 13, 13) connect _WIRE_168.sx, _T_2297 node _T_2298 = bits(_WIRE_169, 14, 14) connect _WIRE_168.sw, _T_2298 node _T_2299 = bits(_WIRE_169, 15, 15) connect _WIRE_168.gf, _T_2299 node _T_2300 = bits(_WIRE_169, 16, 16) connect _WIRE_168.pf, _T_2300 node _T_2301 = bits(_WIRE_169, 17, 17) connect _WIRE_168.ae_stage2, _T_2301 node _T_2302 = bits(_WIRE_169, 18, 18) connect _WIRE_168.ae_final, _T_2302 node _T_2303 = bits(_WIRE_169, 19, 19) connect _WIRE_168.ae_ptw, _T_2303 node _T_2304 = bits(_WIRE_169, 20, 20) connect _WIRE_168.g, _T_2304 node _T_2305 = bits(_WIRE_169, 21, 21) connect _WIRE_168.u, _T_2305 node _T_2306 = bits(_WIRE_169, 41, 22) connect _WIRE_168.ppn, _T_2306 wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_171 : UInt<42> connect _WIRE_171, sectored_entries[0][5].data[1] node _T_2307 = bits(_WIRE_171, 0, 0) connect _WIRE_170.fragmented_superpage, _T_2307 node _T_2308 = bits(_WIRE_171, 1, 1) connect _WIRE_170.c, _T_2308 node _T_2309 = bits(_WIRE_171, 2, 2) connect _WIRE_170.eff, _T_2309 node _T_2310 = bits(_WIRE_171, 3, 3) connect _WIRE_170.paa, _T_2310 node _T_2311 = bits(_WIRE_171, 4, 4) connect _WIRE_170.pal, _T_2311 node _T_2312 = bits(_WIRE_171, 5, 5) connect _WIRE_170.ppp, _T_2312 node _T_2313 = bits(_WIRE_171, 6, 6) connect _WIRE_170.pr, _T_2313 node _T_2314 = bits(_WIRE_171, 7, 7) connect _WIRE_170.px, _T_2314 node _T_2315 = bits(_WIRE_171, 8, 8) connect _WIRE_170.pw, _T_2315 node _T_2316 = bits(_WIRE_171, 9, 9) connect _WIRE_170.hr, _T_2316 node _T_2317 = bits(_WIRE_171, 10, 10) connect _WIRE_170.hx, _T_2317 node _T_2318 = bits(_WIRE_171, 11, 11) connect _WIRE_170.hw, _T_2318 node _T_2319 = bits(_WIRE_171, 12, 12) connect _WIRE_170.sr, _T_2319 node _T_2320 = bits(_WIRE_171, 13, 13) connect _WIRE_170.sx, _T_2320 node _T_2321 = bits(_WIRE_171, 14, 14) connect _WIRE_170.sw, _T_2321 node _T_2322 = bits(_WIRE_171, 15, 15) connect _WIRE_170.gf, _T_2322 node _T_2323 = bits(_WIRE_171, 16, 16) connect _WIRE_170.pf, _T_2323 node _T_2324 = bits(_WIRE_171, 17, 17) connect _WIRE_170.ae_stage2, _T_2324 node _T_2325 = bits(_WIRE_171, 18, 18) connect _WIRE_170.ae_final, _T_2325 node _T_2326 = bits(_WIRE_171, 19, 19) connect _WIRE_170.ae_ptw, _T_2326 node _T_2327 = bits(_WIRE_171, 20, 20) connect _WIRE_170.g, _T_2327 node _T_2328 = bits(_WIRE_171, 21, 21) connect _WIRE_170.u, _T_2328 node _T_2329 = bits(_WIRE_171, 41, 22) connect _WIRE_170.ppn, _T_2329 wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_173 : UInt<42> connect _WIRE_173, sectored_entries[0][5].data[2] node _T_2330 = bits(_WIRE_173, 0, 0) connect _WIRE_172.fragmented_superpage, _T_2330 node _T_2331 = bits(_WIRE_173, 1, 1) connect _WIRE_172.c, _T_2331 node _T_2332 = bits(_WIRE_173, 2, 2) connect _WIRE_172.eff, _T_2332 node _T_2333 = bits(_WIRE_173, 3, 3) connect _WIRE_172.paa, _T_2333 node _T_2334 = bits(_WIRE_173, 4, 4) connect _WIRE_172.pal, _T_2334 node _T_2335 = bits(_WIRE_173, 5, 5) connect _WIRE_172.ppp, _T_2335 node _T_2336 = bits(_WIRE_173, 6, 6) connect _WIRE_172.pr, _T_2336 node _T_2337 = bits(_WIRE_173, 7, 7) connect _WIRE_172.px, _T_2337 node _T_2338 = bits(_WIRE_173, 8, 8) connect _WIRE_172.pw, _T_2338 node _T_2339 = bits(_WIRE_173, 9, 9) connect _WIRE_172.hr, _T_2339 node _T_2340 = bits(_WIRE_173, 10, 10) connect _WIRE_172.hx, _T_2340 node _T_2341 = bits(_WIRE_173, 11, 11) connect _WIRE_172.hw, _T_2341 node _T_2342 = bits(_WIRE_173, 12, 12) connect _WIRE_172.sr, _T_2342 node _T_2343 = bits(_WIRE_173, 13, 13) connect _WIRE_172.sx, _T_2343 node _T_2344 = bits(_WIRE_173, 14, 14) connect _WIRE_172.sw, _T_2344 node _T_2345 = bits(_WIRE_173, 15, 15) connect _WIRE_172.gf, _T_2345 node _T_2346 = bits(_WIRE_173, 16, 16) connect _WIRE_172.pf, _T_2346 node _T_2347 = bits(_WIRE_173, 17, 17) connect _WIRE_172.ae_stage2, _T_2347 node _T_2348 = bits(_WIRE_173, 18, 18) connect _WIRE_172.ae_final, _T_2348 node _T_2349 = bits(_WIRE_173, 19, 19) connect _WIRE_172.ae_ptw, _T_2349 node _T_2350 = bits(_WIRE_173, 20, 20) connect _WIRE_172.g, _T_2350 node _T_2351 = bits(_WIRE_173, 21, 21) connect _WIRE_172.u, _T_2351 node _T_2352 = bits(_WIRE_173, 41, 22) connect _WIRE_172.ppn, _T_2352 wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_175 : UInt<42> connect _WIRE_175, sectored_entries[0][5].data[3] node _T_2353 = bits(_WIRE_175, 0, 0) connect _WIRE_174.fragmented_superpage, _T_2353 node _T_2354 = bits(_WIRE_175, 1, 1) connect _WIRE_174.c, _T_2354 node _T_2355 = bits(_WIRE_175, 2, 2) connect _WIRE_174.eff, _T_2355 node _T_2356 = bits(_WIRE_175, 3, 3) connect _WIRE_174.paa, _T_2356 node _T_2357 = bits(_WIRE_175, 4, 4) connect _WIRE_174.pal, _T_2357 node _T_2358 = bits(_WIRE_175, 5, 5) connect _WIRE_174.ppp, _T_2358 node _T_2359 = bits(_WIRE_175, 6, 6) connect _WIRE_174.pr, _T_2359 node _T_2360 = bits(_WIRE_175, 7, 7) connect _WIRE_174.px, _T_2360 node _T_2361 = bits(_WIRE_175, 8, 8) connect _WIRE_174.pw, _T_2361 node _T_2362 = bits(_WIRE_175, 9, 9) connect _WIRE_174.hr, _T_2362 node _T_2363 = bits(_WIRE_175, 10, 10) connect _WIRE_174.hx, _T_2363 node _T_2364 = bits(_WIRE_175, 11, 11) connect _WIRE_174.hw, _T_2364 node _T_2365 = bits(_WIRE_175, 12, 12) connect _WIRE_174.sr, _T_2365 node _T_2366 = bits(_WIRE_175, 13, 13) connect _WIRE_174.sx, _T_2366 node _T_2367 = bits(_WIRE_175, 14, 14) connect _WIRE_174.sw, _T_2367 node _T_2368 = bits(_WIRE_175, 15, 15) connect _WIRE_174.gf, _T_2368 node _T_2369 = bits(_WIRE_175, 16, 16) connect _WIRE_174.pf, _T_2369 node _T_2370 = bits(_WIRE_175, 17, 17) connect _WIRE_174.ae_stage2, _T_2370 node _T_2371 = bits(_WIRE_175, 18, 18) connect _WIRE_174.ae_final, _T_2371 node _T_2372 = bits(_WIRE_175, 19, 19) connect _WIRE_174.ae_ptw, _T_2372 node _T_2373 = bits(_WIRE_175, 20, 20) connect _WIRE_174.g, _T_2373 node _T_2374 = bits(_WIRE_175, 21, 21) connect _WIRE_174.u, _T_2374 node _T_2375 = bits(_WIRE_175, 41, 22) connect _WIRE_174.ppn, _T_2375 node _T_2376 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2377 = and(_T_2376, _WIRE_168.fragmented_superpage) when _T_2377 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2378 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2379 = and(_T_2378, _WIRE_170.fragmented_superpage) when _T_2379 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2380 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2381 = and(_T_2380, _WIRE_172.fragmented_superpage) when _T_2381 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2382 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2383 = and(_T_2382, _WIRE_174.fragmented_superpage) when _T_2383 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2384 = eq(hg_5, UInt<1>(0h0)) node _T_2385 = and(_T_2384, io.sfence.bits.rs2) when _T_2385 : wire _WIRE_176 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_177 : UInt<42> connect _WIRE_177, sectored_entries[0][5].data[0] node _T_2386 = bits(_WIRE_177, 0, 0) connect _WIRE_176.fragmented_superpage, _T_2386 node _T_2387 = bits(_WIRE_177, 1, 1) connect _WIRE_176.c, _T_2387 node _T_2388 = bits(_WIRE_177, 2, 2) connect _WIRE_176.eff, _T_2388 node _T_2389 = bits(_WIRE_177, 3, 3) connect _WIRE_176.paa, _T_2389 node _T_2390 = bits(_WIRE_177, 4, 4) connect _WIRE_176.pal, _T_2390 node _T_2391 = bits(_WIRE_177, 5, 5) connect _WIRE_176.ppp, _T_2391 node _T_2392 = bits(_WIRE_177, 6, 6) connect _WIRE_176.pr, _T_2392 node _T_2393 = bits(_WIRE_177, 7, 7) connect _WIRE_176.px, _T_2393 node _T_2394 = bits(_WIRE_177, 8, 8) connect _WIRE_176.pw, _T_2394 node _T_2395 = bits(_WIRE_177, 9, 9) connect _WIRE_176.hr, _T_2395 node _T_2396 = bits(_WIRE_177, 10, 10) connect _WIRE_176.hx, _T_2396 node _T_2397 = bits(_WIRE_177, 11, 11) connect _WIRE_176.hw, _T_2397 node _T_2398 = bits(_WIRE_177, 12, 12) connect _WIRE_176.sr, _T_2398 node _T_2399 = bits(_WIRE_177, 13, 13) connect _WIRE_176.sx, _T_2399 node _T_2400 = bits(_WIRE_177, 14, 14) connect _WIRE_176.sw, _T_2400 node _T_2401 = bits(_WIRE_177, 15, 15) connect _WIRE_176.gf, _T_2401 node _T_2402 = bits(_WIRE_177, 16, 16) connect _WIRE_176.pf, _T_2402 node _T_2403 = bits(_WIRE_177, 17, 17) connect _WIRE_176.ae_stage2, _T_2403 node _T_2404 = bits(_WIRE_177, 18, 18) connect _WIRE_176.ae_final, _T_2404 node _T_2405 = bits(_WIRE_177, 19, 19) connect _WIRE_176.ae_ptw, _T_2405 node _T_2406 = bits(_WIRE_177, 20, 20) connect _WIRE_176.g, _T_2406 node _T_2407 = bits(_WIRE_177, 21, 21) connect _WIRE_176.u, _T_2407 node _T_2408 = bits(_WIRE_177, 41, 22) connect _WIRE_176.ppn, _T_2408 wire _WIRE_178 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_179 : UInt<42> connect _WIRE_179, sectored_entries[0][5].data[1] node _T_2409 = bits(_WIRE_179, 0, 0) connect _WIRE_178.fragmented_superpage, _T_2409 node _T_2410 = bits(_WIRE_179, 1, 1) connect _WIRE_178.c, _T_2410 node _T_2411 = bits(_WIRE_179, 2, 2) connect _WIRE_178.eff, _T_2411 node _T_2412 = bits(_WIRE_179, 3, 3) connect _WIRE_178.paa, _T_2412 node _T_2413 = bits(_WIRE_179, 4, 4) connect _WIRE_178.pal, _T_2413 node _T_2414 = bits(_WIRE_179, 5, 5) connect _WIRE_178.ppp, _T_2414 node _T_2415 = bits(_WIRE_179, 6, 6) connect _WIRE_178.pr, _T_2415 node _T_2416 = bits(_WIRE_179, 7, 7) connect _WIRE_178.px, _T_2416 node _T_2417 = bits(_WIRE_179, 8, 8) connect _WIRE_178.pw, _T_2417 node _T_2418 = bits(_WIRE_179, 9, 9) connect _WIRE_178.hr, _T_2418 node _T_2419 = bits(_WIRE_179, 10, 10) connect _WIRE_178.hx, _T_2419 node _T_2420 = bits(_WIRE_179, 11, 11) connect _WIRE_178.hw, _T_2420 node _T_2421 = bits(_WIRE_179, 12, 12) connect _WIRE_178.sr, _T_2421 node _T_2422 = bits(_WIRE_179, 13, 13) connect _WIRE_178.sx, _T_2422 node _T_2423 = bits(_WIRE_179, 14, 14) connect _WIRE_178.sw, _T_2423 node _T_2424 = bits(_WIRE_179, 15, 15) connect _WIRE_178.gf, _T_2424 node _T_2425 = bits(_WIRE_179, 16, 16) connect _WIRE_178.pf, _T_2425 node _T_2426 = bits(_WIRE_179, 17, 17) connect _WIRE_178.ae_stage2, _T_2426 node _T_2427 = bits(_WIRE_179, 18, 18) connect _WIRE_178.ae_final, _T_2427 node _T_2428 = bits(_WIRE_179, 19, 19) connect _WIRE_178.ae_ptw, _T_2428 node _T_2429 = bits(_WIRE_179, 20, 20) connect _WIRE_178.g, _T_2429 node _T_2430 = bits(_WIRE_179, 21, 21) connect _WIRE_178.u, _T_2430 node _T_2431 = bits(_WIRE_179, 41, 22) connect _WIRE_178.ppn, _T_2431 wire _WIRE_180 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_181 : UInt<42> connect _WIRE_181, sectored_entries[0][5].data[2] node _T_2432 = bits(_WIRE_181, 0, 0) connect _WIRE_180.fragmented_superpage, _T_2432 node _T_2433 = bits(_WIRE_181, 1, 1) connect _WIRE_180.c, _T_2433 node _T_2434 = bits(_WIRE_181, 2, 2) connect _WIRE_180.eff, _T_2434 node _T_2435 = bits(_WIRE_181, 3, 3) connect _WIRE_180.paa, _T_2435 node _T_2436 = bits(_WIRE_181, 4, 4) connect _WIRE_180.pal, _T_2436 node _T_2437 = bits(_WIRE_181, 5, 5) connect _WIRE_180.ppp, _T_2437 node _T_2438 = bits(_WIRE_181, 6, 6) connect _WIRE_180.pr, _T_2438 node _T_2439 = bits(_WIRE_181, 7, 7) connect _WIRE_180.px, _T_2439 node _T_2440 = bits(_WIRE_181, 8, 8) connect _WIRE_180.pw, _T_2440 node _T_2441 = bits(_WIRE_181, 9, 9) connect _WIRE_180.hr, _T_2441 node _T_2442 = bits(_WIRE_181, 10, 10) connect _WIRE_180.hx, _T_2442 node _T_2443 = bits(_WIRE_181, 11, 11) connect _WIRE_180.hw, _T_2443 node _T_2444 = bits(_WIRE_181, 12, 12) connect _WIRE_180.sr, _T_2444 node _T_2445 = bits(_WIRE_181, 13, 13) connect _WIRE_180.sx, _T_2445 node _T_2446 = bits(_WIRE_181, 14, 14) connect _WIRE_180.sw, _T_2446 node _T_2447 = bits(_WIRE_181, 15, 15) connect _WIRE_180.gf, _T_2447 node _T_2448 = bits(_WIRE_181, 16, 16) connect _WIRE_180.pf, _T_2448 node _T_2449 = bits(_WIRE_181, 17, 17) connect _WIRE_180.ae_stage2, _T_2449 node _T_2450 = bits(_WIRE_181, 18, 18) connect _WIRE_180.ae_final, _T_2450 node _T_2451 = bits(_WIRE_181, 19, 19) connect _WIRE_180.ae_ptw, _T_2451 node _T_2452 = bits(_WIRE_181, 20, 20) connect _WIRE_180.g, _T_2452 node _T_2453 = bits(_WIRE_181, 21, 21) connect _WIRE_180.u, _T_2453 node _T_2454 = bits(_WIRE_181, 41, 22) connect _WIRE_180.ppn, _T_2454 wire _WIRE_182 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_183 : UInt<42> connect _WIRE_183, sectored_entries[0][5].data[3] node _T_2455 = bits(_WIRE_183, 0, 0) connect _WIRE_182.fragmented_superpage, _T_2455 node _T_2456 = bits(_WIRE_183, 1, 1) connect _WIRE_182.c, _T_2456 node _T_2457 = bits(_WIRE_183, 2, 2) connect _WIRE_182.eff, _T_2457 node _T_2458 = bits(_WIRE_183, 3, 3) connect _WIRE_182.paa, _T_2458 node _T_2459 = bits(_WIRE_183, 4, 4) connect _WIRE_182.pal, _T_2459 node _T_2460 = bits(_WIRE_183, 5, 5) connect _WIRE_182.ppp, _T_2460 node _T_2461 = bits(_WIRE_183, 6, 6) connect _WIRE_182.pr, _T_2461 node _T_2462 = bits(_WIRE_183, 7, 7) connect _WIRE_182.px, _T_2462 node _T_2463 = bits(_WIRE_183, 8, 8) connect _WIRE_182.pw, _T_2463 node _T_2464 = bits(_WIRE_183, 9, 9) connect _WIRE_182.hr, _T_2464 node _T_2465 = bits(_WIRE_183, 10, 10) connect _WIRE_182.hx, _T_2465 node _T_2466 = bits(_WIRE_183, 11, 11) connect _WIRE_182.hw, _T_2466 node _T_2467 = bits(_WIRE_183, 12, 12) connect _WIRE_182.sr, _T_2467 node _T_2468 = bits(_WIRE_183, 13, 13) connect _WIRE_182.sx, _T_2468 node _T_2469 = bits(_WIRE_183, 14, 14) connect _WIRE_182.sw, _T_2469 node _T_2470 = bits(_WIRE_183, 15, 15) connect _WIRE_182.gf, _T_2470 node _T_2471 = bits(_WIRE_183, 16, 16) connect _WIRE_182.pf, _T_2471 node _T_2472 = bits(_WIRE_183, 17, 17) connect _WIRE_182.ae_stage2, _T_2472 node _T_2473 = bits(_WIRE_183, 18, 18) connect _WIRE_182.ae_final, _T_2473 node _T_2474 = bits(_WIRE_183, 19, 19) connect _WIRE_182.ae_ptw, _T_2474 node _T_2475 = bits(_WIRE_183, 20, 20) connect _WIRE_182.g, _T_2475 node _T_2476 = bits(_WIRE_183, 21, 21) connect _WIRE_182.u, _T_2476 node _T_2477 = bits(_WIRE_183, 41, 22) connect _WIRE_182.ppn, _T_2477 node _T_2478 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2479 = eq(_WIRE_176.g, UInt<1>(0h0)) node _T_2480 = and(_T_2478, _T_2479) when _T_2480 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2481 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2482 = eq(_WIRE_178.g, UInt<1>(0h0)) node _T_2483 = and(_T_2481, _T_2482) when _T_2483 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2484 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2485 = eq(_WIRE_180.g, UInt<1>(0h0)) node _T_2486 = and(_T_2484, _T_2485) when _T_2486 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2487 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2488 = eq(_WIRE_182.g, UInt<1>(0h0)) node _T_2489 = and(_T_2487, _T_2488) when _T_2489 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2490 = or(hv_5, hg_5) wire _WIRE_184 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_185 : UInt<42> connect _WIRE_185, sectored_entries[0][5].data[0] node _T_2491 = bits(_WIRE_185, 0, 0) connect _WIRE_184.fragmented_superpage, _T_2491 node _T_2492 = bits(_WIRE_185, 1, 1) connect _WIRE_184.c, _T_2492 node _T_2493 = bits(_WIRE_185, 2, 2) connect _WIRE_184.eff, _T_2493 node _T_2494 = bits(_WIRE_185, 3, 3) connect _WIRE_184.paa, _T_2494 node _T_2495 = bits(_WIRE_185, 4, 4) connect _WIRE_184.pal, _T_2495 node _T_2496 = bits(_WIRE_185, 5, 5) connect _WIRE_184.ppp, _T_2496 node _T_2497 = bits(_WIRE_185, 6, 6) connect _WIRE_184.pr, _T_2497 node _T_2498 = bits(_WIRE_185, 7, 7) connect _WIRE_184.px, _T_2498 node _T_2499 = bits(_WIRE_185, 8, 8) connect _WIRE_184.pw, _T_2499 node _T_2500 = bits(_WIRE_185, 9, 9) connect _WIRE_184.hr, _T_2500 node _T_2501 = bits(_WIRE_185, 10, 10) connect _WIRE_184.hx, _T_2501 node _T_2502 = bits(_WIRE_185, 11, 11) connect _WIRE_184.hw, _T_2502 node _T_2503 = bits(_WIRE_185, 12, 12) connect _WIRE_184.sr, _T_2503 node _T_2504 = bits(_WIRE_185, 13, 13) connect _WIRE_184.sx, _T_2504 node _T_2505 = bits(_WIRE_185, 14, 14) connect _WIRE_184.sw, _T_2505 node _T_2506 = bits(_WIRE_185, 15, 15) connect _WIRE_184.gf, _T_2506 node _T_2507 = bits(_WIRE_185, 16, 16) connect _WIRE_184.pf, _T_2507 node _T_2508 = bits(_WIRE_185, 17, 17) connect _WIRE_184.ae_stage2, _T_2508 node _T_2509 = bits(_WIRE_185, 18, 18) connect _WIRE_184.ae_final, _T_2509 node _T_2510 = bits(_WIRE_185, 19, 19) connect _WIRE_184.ae_ptw, _T_2510 node _T_2511 = bits(_WIRE_185, 20, 20) connect _WIRE_184.g, _T_2511 node _T_2512 = bits(_WIRE_185, 21, 21) connect _WIRE_184.u, _T_2512 node _T_2513 = bits(_WIRE_185, 41, 22) connect _WIRE_184.ppn, _T_2513 wire _WIRE_186 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_187 : UInt<42> connect _WIRE_187, sectored_entries[0][5].data[1] node _T_2514 = bits(_WIRE_187, 0, 0) connect _WIRE_186.fragmented_superpage, _T_2514 node _T_2515 = bits(_WIRE_187, 1, 1) connect _WIRE_186.c, _T_2515 node _T_2516 = bits(_WIRE_187, 2, 2) connect _WIRE_186.eff, _T_2516 node _T_2517 = bits(_WIRE_187, 3, 3) connect _WIRE_186.paa, _T_2517 node _T_2518 = bits(_WIRE_187, 4, 4) connect _WIRE_186.pal, _T_2518 node _T_2519 = bits(_WIRE_187, 5, 5) connect _WIRE_186.ppp, _T_2519 node _T_2520 = bits(_WIRE_187, 6, 6) connect _WIRE_186.pr, _T_2520 node _T_2521 = bits(_WIRE_187, 7, 7) connect _WIRE_186.px, _T_2521 node _T_2522 = bits(_WIRE_187, 8, 8) connect _WIRE_186.pw, _T_2522 node _T_2523 = bits(_WIRE_187, 9, 9) connect _WIRE_186.hr, _T_2523 node _T_2524 = bits(_WIRE_187, 10, 10) connect _WIRE_186.hx, _T_2524 node _T_2525 = bits(_WIRE_187, 11, 11) connect _WIRE_186.hw, _T_2525 node _T_2526 = bits(_WIRE_187, 12, 12) connect _WIRE_186.sr, _T_2526 node _T_2527 = bits(_WIRE_187, 13, 13) connect _WIRE_186.sx, _T_2527 node _T_2528 = bits(_WIRE_187, 14, 14) connect _WIRE_186.sw, _T_2528 node _T_2529 = bits(_WIRE_187, 15, 15) connect _WIRE_186.gf, _T_2529 node _T_2530 = bits(_WIRE_187, 16, 16) connect _WIRE_186.pf, _T_2530 node _T_2531 = bits(_WIRE_187, 17, 17) connect _WIRE_186.ae_stage2, _T_2531 node _T_2532 = bits(_WIRE_187, 18, 18) connect _WIRE_186.ae_final, _T_2532 node _T_2533 = bits(_WIRE_187, 19, 19) connect _WIRE_186.ae_ptw, _T_2533 node _T_2534 = bits(_WIRE_187, 20, 20) connect _WIRE_186.g, _T_2534 node _T_2535 = bits(_WIRE_187, 21, 21) connect _WIRE_186.u, _T_2535 node _T_2536 = bits(_WIRE_187, 41, 22) connect _WIRE_186.ppn, _T_2536 wire _WIRE_188 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_189 : UInt<42> connect _WIRE_189, sectored_entries[0][5].data[2] node _T_2537 = bits(_WIRE_189, 0, 0) connect _WIRE_188.fragmented_superpage, _T_2537 node _T_2538 = bits(_WIRE_189, 1, 1) connect _WIRE_188.c, _T_2538 node _T_2539 = bits(_WIRE_189, 2, 2) connect _WIRE_188.eff, _T_2539 node _T_2540 = bits(_WIRE_189, 3, 3) connect _WIRE_188.paa, _T_2540 node _T_2541 = bits(_WIRE_189, 4, 4) connect _WIRE_188.pal, _T_2541 node _T_2542 = bits(_WIRE_189, 5, 5) connect _WIRE_188.ppp, _T_2542 node _T_2543 = bits(_WIRE_189, 6, 6) connect _WIRE_188.pr, _T_2543 node _T_2544 = bits(_WIRE_189, 7, 7) connect _WIRE_188.px, _T_2544 node _T_2545 = bits(_WIRE_189, 8, 8) connect _WIRE_188.pw, _T_2545 node _T_2546 = bits(_WIRE_189, 9, 9) connect _WIRE_188.hr, _T_2546 node _T_2547 = bits(_WIRE_189, 10, 10) connect _WIRE_188.hx, _T_2547 node _T_2548 = bits(_WIRE_189, 11, 11) connect _WIRE_188.hw, _T_2548 node _T_2549 = bits(_WIRE_189, 12, 12) connect _WIRE_188.sr, _T_2549 node _T_2550 = bits(_WIRE_189, 13, 13) connect _WIRE_188.sx, _T_2550 node _T_2551 = bits(_WIRE_189, 14, 14) connect _WIRE_188.sw, _T_2551 node _T_2552 = bits(_WIRE_189, 15, 15) connect _WIRE_188.gf, _T_2552 node _T_2553 = bits(_WIRE_189, 16, 16) connect _WIRE_188.pf, _T_2553 node _T_2554 = bits(_WIRE_189, 17, 17) connect _WIRE_188.ae_stage2, _T_2554 node _T_2555 = bits(_WIRE_189, 18, 18) connect _WIRE_188.ae_final, _T_2555 node _T_2556 = bits(_WIRE_189, 19, 19) connect _WIRE_188.ae_ptw, _T_2556 node _T_2557 = bits(_WIRE_189, 20, 20) connect _WIRE_188.g, _T_2557 node _T_2558 = bits(_WIRE_189, 21, 21) connect _WIRE_188.u, _T_2558 node _T_2559 = bits(_WIRE_189, 41, 22) connect _WIRE_188.ppn, _T_2559 wire _WIRE_190 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_191 : UInt<42> connect _WIRE_191, sectored_entries[0][5].data[3] node _T_2560 = bits(_WIRE_191, 0, 0) connect _WIRE_190.fragmented_superpage, _T_2560 node _T_2561 = bits(_WIRE_191, 1, 1) connect _WIRE_190.c, _T_2561 node _T_2562 = bits(_WIRE_191, 2, 2) connect _WIRE_190.eff, _T_2562 node _T_2563 = bits(_WIRE_191, 3, 3) connect _WIRE_190.paa, _T_2563 node _T_2564 = bits(_WIRE_191, 4, 4) connect _WIRE_190.pal, _T_2564 node _T_2565 = bits(_WIRE_191, 5, 5) connect _WIRE_190.ppp, _T_2565 node _T_2566 = bits(_WIRE_191, 6, 6) connect _WIRE_190.pr, _T_2566 node _T_2567 = bits(_WIRE_191, 7, 7) connect _WIRE_190.px, _T_2567 node _T_2568 = bits(_WIRE_191, 8, 8) connect _WIRE_190.pw, _T_2568 node _T_2569 = bits(_WIRE_191, 9, 9) connect _WIRE_190.hr, _T_2569 node _T_2570 = bits(_WIRE_191, 10, 10) connect _WIRE_190.hx, _T_2570 node _T_2571 = bits(_WIRE_191, 11, 11) connect _WIRE_190.hw, _T_2571 node _T_2572 = bits(_WIRE_191, 12, 12) connect _WIRE_190.sr, _T_2572 node _T_2573 = bits(_WIRE_191, 13, 13) connect _WIRE_190.sx, _T_2573 node _T_2574 = bits(_WIRE_191, 14, 14) connect _WIRE_190.sw, _T_2574 node _T_2575 = bits(_WIRE_191, 15, 15) connect _WIRE_190.gf, _T_2575 node _T_2576 = bits(_WIRE_191, 16, 16) connect _WIRE_190.pf, _T_2576 node _T_2577 = bits(_WIRE_191, 17, 17) connect _WIRE_190.ae_stage2, _T_2577 node _T_2578 = bits(_WIRE_191, 18, 18) connect _WIRE_190.ae_final, _T_2578 node _T_2579 = bits(_WIRE_191, 19, 19) connect _WIRE_190.ae_ptw, _T_2579 node _T_2580 = bits(_WIRE_191, 20, 20) connect _WIRE_190.g, _T_2580 node _T_2581 = bits(_WIRE_191, 21, 21) connect _WIRE_190.u, _T_2581 node _T_2582 = bits(_WIRE_191, 41, 22) connect _WIRE_190.ppn, _T_2582 node _T_2583 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2583 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2584 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2584 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2585 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2585 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2586 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2586 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2587 = eq(hg_6, UInt<1>(0h0)) node _T_2588 = and(_T_2587, io.sfence.bits.rs1) when _T_2588 : node _T_2589 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2590 = shr(_T_2589, 2) node _T_2591 = eq(_T_2590, UInt<1>(0h0)) node _T_2592 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2593 = and(_T_2591, _T_2592) when _T_2593 : wire _WIRE_192 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_193 : UInt<42> connect _WIRE_193, sectored_entries[0][6].data[0] node _T_2594 = bits(_WIRE_193, 0, 0) connect _WIRE_192.fragmented_superpage, _T_2594 node _T_2595 = bits(_WIRE_193, 1, 1) connect _WIRE_192.c, _T_2595 node _T_2596 = bits(_WIRE_193, 2, 2) connect _WIRE_192.eff, _T_2596 node _T_2597 = bits(_WIRE_193, 3, 3) connect _WIRE_192.paa, _T_2597 node _T_2598 = bits(_WIRE_193, 4, 4) connect _WIRE_192.pal, _T_2598 node _T_2599 = bits(_WIRE_193, 5, 5) connect _WIRE_192.ppp, _T_2599 node _T_2600 = bits(_WIRE_193, 6, 6) connect _WIRE_192.pr, _T_2600 node _T_2601 = bits(_WIRE_193, 7, 7) connect _WIRE_192.px, _T_2601 node _T_2602 = bits(_WIRE_193, 8, 8) connect _WIRE_192.pw, _T_2602 node _T_2603 = bits(_WIRE_193, 9, 9) connect _WIRE_192.hr, _T_2603 node _T_2604 = bits(_WIRE_193, 10, 10) connect _WIRE_192.hx, _T_2604 node _T_2605 = bits(_WIRE_193, 11, 11) connect _WIRE_192.hw, _T_2605 node _T_2606 = bits(_WIRE_193, 12, 12) connect _WIRE_192.sr, _T_2606 node _T_2607 = bits(_WIRE_193, 13, 13) connect _WIRE_192.sx, _T_2607 node _T_2608 = bits(_WIRE_193, 14, 14) connect _WIRE_192.sw, _T_2608 node _T_2609 = bits(_WIRE_193, 15, 15) connect _WIRE_192.gf, _T_2609 node _T_2610 = bits(_WIRE_193, 16, 16) connect _WIRE_192.pf, _T_2610 node _T_2611 = bits(_WIRE_193, 17, 17) connect _WIRE_192.ae_stage2, _T_2611 node _T_2612 = bits(_WIRE_193, 18, 18) connect _WIRE_192.ae_final, _T_2612 node _T_2613 = bits(_WIRE_193, 19, 19) connect _WIRE_192.ae_ptw, _T_2613 node _T_2614 = bits(_WIRE_193, 20, 20) connect _WIRE_192.g, _T_2614 node _T_2615 = bits(_WIRE_193, 21, 21) connect _WIRE_192.u, _T_2615 node _T_2616 = bits(_WIRE_193, 41, 22) connect _WIRE_192.ppn, _T_2616 wire _WIRE_194 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_195 : UInt<42> connect _WIRE_195, sectored_entries[0][6].data[1] node _T_2617 = bits(_WIRE_195, 0, 0) connect _WIRE_194.fragmented_superpage, _T_2617 node _T_2618 = bits(_WIRE_195, 1, 1) connect _WIRE_194.c, _T_2618 node _T_2619 = bits(_WIRE_195, 2, 2) connect _WIRE_194.eff, _T_2619 node _T_2620 = bits(_WIRE_195, 3, 3) connect _WIRE_194.paa, _T_2620 node _T_2621 = bits(_WIRE_195, 4, 4) connect _WIRE_194.pal, _T_2621 node _T_2622 = bits(_WIRE_195, 5, 5) connect _WIRE_194.ppp, _T_2622 node _T_2623 = bits(_WIRE_195, 6, 6) connect _WIRE_194.pr, _T_2623 node _T_2624 = bits(_WIRE_195, 7, 7) connect _WIRE_194.px, _T_2624 node _T_2625 = bits(_WIRE_195, 8, 8) connect _WIRE_194.pw, _T_2625 node _T_2626 = bits(_WIRE_195, 9, 9) connect _WIRE_194.hr, _T_2626 node _T_2627 = bits(_WIRE_195, 10, 10) connect _WIRE_194.hx, _T_2627 node _T_2628 = bits(_WIRE_195, 11, 11) connect _WIRE_194.hw, _T_2628 node _T_2629 = bits(_WIRE_195, 12, 12) connect _WIRE_194.sr, _T_2629 node _T_2630 = bits(_WIRE_195, 13, 13) connect _WIRE_194.sx, _T_2630 node _T_2631 = bits(_WIRE_195, 14, 14) connect _WIRE_194.sw, _T_2631 node _T_2632 = bits(_WIRE_195, 15, 15) connect _WIRE_194.gf, _T_2632 node _T_2633 = bits(_WIRE_195, 16, 16) connect _WIRE_194.pf, _T_2633 node _T_2634 = bits(_WIRE_195, 17, 17) connect _WIRE_194.ae_stage2, _T_2634 node _T_2635 = bits(_WIRE_195, 18, 18) connect _WIRE_194.ae_final, _T_2635 node _T_2636 = bits(_WIRE_195, 19, 19) connect _WIRE_194.ae_ptw, _T_2636 node _T_2637 = bits(_WIRE_195, 20, 20) connect _WIRE_194.g, _T_2637 node _T_2638 = bits(_WIRE_195, 21, 21) connect _WIRE_194.u, _T_2638 node _T_2639 = bits(_WIRE_195, 41, 22) connect _WIRE_194.ppn, _T_2639 wire _WIRE_196 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_197 : UInt<42> connect _WIRE_197, sectored_entries[0][6].data[2] node _T_2640 = bits(_WIRE_197, 0, 0) connect _WIRE_196.fragmented_superpage, _T_2640 node _T_2641 = bits(_WIRE_197, 1, 1) connect _WIRE_196.c, _T_2641 node _T_2642 = bits(_WIRE_197, 2, 2) connect _WIRE_196.eff, _T_2642 node _T_2643 = bits(_WIRE_197, 3, 3) connect _WIRE_196.paa, _T_2643 node _T_2644 = bits(_WIRE_197, 4, 4) connect _WIRE_196.pal, _T_2644 node _T_2645 = bits(_WIRE_197, 5, 5) connect _WIRE_196.ppp, _T_2645 node _T_2646 = bits(_WIRE_197, 6, 6) connect _WIRE_196.pr, _T_2646 node _T_2647 = bits(_WIRE_197, 7, 7) connect _WIRE_196.px, _T_2647 node _T_2648 = bits(_WIRE_197, 8, 8) connect _WIRE_196.pw, _T_2648 node _T_2649 = bits(_WIRE_197, 9, 9) connect _WIRE_196.hr, _T_2649 node _T_2650 = bits(_WIRE_197, 10, 10) connect _WIRE_196.hx, _T_2650 node _T_2651 = bits(_WIRE_197, 11, 11) connect _WIRE_196.hw, _T_2651 node _T_2652 = bits(_WIRE_197, 12, 12) connect _WIRE_196.sr, _T_2652 node _T_2653 = bits(_WIRE_197, 13, 13) connect _WIRE_196.sx, _T_2653 node _T_2654 = bits(_WIRE_197, 14, 14) connect _WIRE_196.sw, _T_2654 node _T_2655 = bits(_WIRE_197, 15, 15) connect _WIRE_196.gf, _T_2655 node _T_2656 = bits(_WIRE_197, 16, 16) connect _WIRE_196.pf, _T_2656 node _T_2657 = bits(_WIRE_197, 17, 17) connect _WIRE_196.ae_stage2, _T_2657 node _T_2658 = bits(_WIRE_197, 18, 18) connect _WIRE_196.ae_final, _T_2658 node _T_2659 = bits(_WIRE_197, 19, 19) connect _WIRE_196.ae_ptw, _T_2659 node _T_2660 = bits(_WIRE_197, 20, 20) connect _WIRE_196.g, _T_2660 node _T_2661 = bits(_WIRE_197, 21, 21) connect _WIRE_196.u, _T_2661 node _T_2662 = bits(_WIRE_197, 41, 22) connect _WIRE_196.ppn, _T_2662 wire _WIRE_198 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_199 : UInt<42> connect _WIRE_199, sectored_entries[0][6].data[3] node _T_2663 = bits(_WIRE_199, 0, 0) connect _WIRE_198.fragmented_superpage, _T_2663 node _T_2664 = bits(_WIRE_199, 1, 1) connect _WIRE_198.c, _T_2664 node _T_2665 = bits(_WIRE_199, 2, 2) connect _WIRE_198.eff, _T_2665 node _T_2666 = bits(_WIRE_199, 3, 3) connect _WIRE_198.paa, _T_2666 node _T_2667 = bits(_WIRE_199, 4, 4) connect _WIRE_198.pal, _T_2667 node _T_2668 = bits(_WIRE_199, 5, 5) connect _WIRE_198.ppp, _T_2668 node _T_2669 = bits(_WIRE_199, 6, 6) connect _WIRE_198.pr, _T_2669 node _T_2670 = bits(_WIRE_199, 7, 7) connect _WIRE_198.px, _T_2670 node _T_2671 = bits(_WIRE_199, 8, 8) connect _WIRE_198.pw, _T_2671 node _T_2672 = bits(_WIRE_199, 9, 9) connect _WIRE_198.hr, _T_2672 node _T_2673 = bits(_WIRE_199, 10, 10) connect _WIRE_198.hx, _T_2673 node _T_2674 = bits(_WIRE_199, 11, 11) connect _WIRE_198.hw, _T_2674 node _T_2675 = bits(_WIRE_199, 12, 12) connect _WIRE_198.sr, _T_2675 node _T_2676 = bits(_WIRE_199, 13, 13) connect _WIRE_198.sx, _T_2676 node _T_2677 = bits(_WIRE_199, 14, 14) connect _WIRE_198.sw, _T_2677 node _T_2678 = bits(_WIRE_199, 15, 15) connect _WIRE_198.gf, _T_2678 node _T_2679 = bits(_WIRE_199, 16, 16) connect _WIRE_198.pf, _T_2679 node _T_2680 = bits(_WIRE_199, 17, 17) connect _WIRE_198.ae_stage2, _T_2680 node _T_2681 = bits(_WIRE_199, 18, 18) connect _WIRE_198.ae_final, _T_2681 node _T_2682 = bits(_WIRE_199, 19, 19) connect _WIRE_198.ae_ptw, _T_2682 node _T_2683 = bits(_WIRE_199, 20, 20) connect _WIRE_198.g, _T_2683 node _T_2684 = bits(_WIRE_199, 21, 21) connect _WIRE_198.u, _T_2684 node _T_2685 = bits(_WIRE_199, 41, 22) connect _WIRE_198.ppn, _T_2685 node _T_2686 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2687 = bits(vpn, 1, 0) node _T_2688 = eq(UInt<1>(0h0), _T_2687) node _T_2689 = and(_T_2686, _T_2688) when _T_2689 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2690 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2691 = bits(vpn, 1, 0) node _T_2692 = eq(UInt<1>(0h1), _T_2691) node _T_2693 = and(_T_2690, _T_2692) when _T_2693 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2694 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2695 = bits(vpn, 1, 0) node _T_2696 = eq(UInt<2>(0h2), _T_2695) node _T_2697 = and(_T_2694, _T_2696) when _T_2697 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2698 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2699 = bits(vpn, 1, 0) node _T_2700 = eq(UInt<2>(0h3), _T_2699) node _T_2701 = and(_T_2698, _T_2700) when _T_2701 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_2702 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2703 = shr(_T_2702, 18) node _T_2704 = eq(_T_2703, UInt<1>(0h0)) when _T_2704 : wire _WIRE_200 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_201 : UInt<42> connect _WIRE_201, sectored_entries[0][6].data[0] node _T_2705 = bits(_WIRE_201, 0, 0) connect _WIRE_200.fragmented_superpage, _T_2705 node _T_2706 = bits(_WIRE_201, 1, 1) connect _WIRE_200.c, _T_2706 node _T_2707 = bits(_WIRE_201, 2, 2) connect _WIRE_200.eff, _T_2707 node _T_2708 = bits(_WIRE_201, 3, 3) connect _WIRE_200.paa, _T_2708 node _T_2709 = bits(_WIRE_201, 4, 4) connect _WIRE_200.pal, _T_2709 node _T_2710 = bits(_WIRE_201, 5, 5) connect _WIRE_200.ppp, _T_2710 node _T_2711 = bits(_WIRE_201, 6, 6) connect _WIRE_200.pr, _T_2711 node _T_2712 = bits(_WIRE_201, 7, 7) connect _WIRE_200.px, _T_2712 node _T_2713 = bits(_WIRE_201, 8, 8) connect _WIRE_200.pw, _T_2713 node _T_2714 = bits(_WIRE_201, 9, 9) connect _WIRE_200.hr, _T_2714 node _T_2715 = bits(_WIRE_201, 10, 10) connect _WIRE_200.hx, _T_2715 node _T_2716 = bits(_WIRE_201, 11, 11) connect _WIRE_200.hw, _T_2716 node _T_2717 = bits(_WIRE_201, 12, 12) connect _WIRE_200.sr, _T_2717 node _T_2718 = bits(_WIRE_201, 13, 13) connect _WIRE_200.sx, _T_2718 node _T_2719 = bits(_WIRE_201, 14, 14) connect _WIRE_200.sw, _T_2719 node _T_2720 = bits(_WIRE_201, 15, 15) connect _WIRE_200.gf, _T_2720 node _T_2721 = bits(_WIRE_201, 16, 16) connect _WIRE_200.pf, _T_2721 node _T_2722 = bits(_WIRE_201, 17, 17) connect _WIRE_200.ae_stage2, _T_2722 node _T_2723 = bits(_WIRE_201, 18, 18) connect _WIRE_200.ae_final, _T_2723 node _T_2724 = bits(_WIRE_201, 19, 19) connect _WIRE_200.ae_ptw, _T_2724 node _T_2725 = bits(_WIRE_201, 20, 20) connect _WIRE_200.g, _T_2725 node _T_2726 = bits(_WIRE_201, 21, 21) connect _WIRE_200.u, _T_2726 node _T_2727 = bits(_WIRE_201, 41, 22) connect _WIRE_200.ppn, _T_2727 wire _WIRE_202 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_203 : UInt<42> connect _WIRE_203, sectored_entries[0][6].data[1] node _T_2728 = bits(_WIRE_203, 0, 0) connect _WIRE_202.fragmented_superpage, _T_2728 node _T_2729 = bits(_WIRE_203, 1, 1) connect _WIRE_202.c, _T_2729 node _T_2730 = bits(_WIRE_203, 2, 2) connect _WIRE_202.eff, _T_2730 node _T_2731 = bits(_WIRE_203, 3, 3) connect _WIRE_202.paa, _T_2731 node _T_2732 = bits(_WIRE_203, 4, 4) connect _WIRE_202.pal, _T_2732 node _T_2733 = bits(_WIRE_203, 5, 5) connect _WIRE_202.ppp, _T_2733 node _T_2734 = bits(_WIRE_203, 6, 6) connect _WIRE_202.pr, _T_2734 node _T_2735 = bits(_WIRE_203, 7, 7) connect _WIRE_202.px, _T_2735 node _T_2736 = bits(_WIRE_203, 8, 8) connect _WIRE_202.pw, _T_2736 node _T_2737 = bits(_WIRE_203, 9, 9) connect _WIRE_202.hr, _T_2737 node _T_2738 = bits(_WIRE_203, 10, 10) connect _WIRE_202.hx, _T_2738 node _T_2739 = bits(_WIRE_203, 11, 11) connect _WIRE_202.hw, _T_2739 node _T_2740 = bits(_WIRE_203, 12, 12) connect _WIRE_202.sr, _T_2740 node _T_2741 = bits(_WIRE_203, 13, 13) connect _WIRE_202.sx, _T_2741 node _T_2742 = bits(_WIRE_203, 14, 14) connect _WIRE_202.sw, _T_2742 node _T_2743 = bits(_WIRE_203, 15, 15) connect _WIRE_202.gf, _T_2743 node _T_2744 = bits(_WIRE_203, 16, 16) connect _WIRE_202.pf, _T_2744 node _T_2745 = bits(_WIRE_203, 17, 17) connect _WIRE_202.ae_stage2, _T_2745 node _T_2746 = bits(_WIRE_203, 18, 18) connect _WIRE_202.ae_final, _T_2746 node _T_2747 = bits(_WIRE_203, 19, 19) connect _WIRE_202.ae_ptw, _T_2747 node _T_2748 = bits(_WIRE_203, 20, 20) connect _WIRE_202.g, _T_2748 node _T_2749 = bits(_WIRE_203, 21, 21) connect _WIRE_202.u, _T_2749 node _T_2750 = bits(_WIRE_203, 41, 22) connect _WIRE_202.ppn, _T_2750 wire _WIRE_204 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_205 : UInt<42> connect _WIRE_205, sectored_entries[0][6].data[2] node _T_2751 = bits(_WIRE_205, 0, 0) connect _WIRE_204.fragmented_superpage, _T_2751 node _T_2752 = bits(_WIRE_205, 1, 1) connect _WIRE_204.c, _T_2752 node _T_2753 = bits(_WIRE_205, 2, 2) connect _WIRE_204.eff, _T_2753 node _T_2754 = bits(_WIRE_205, 3, 3) connect _WIRE_204.paa, _T_2754 node _T_2755 = bits(_WIRE_205, 4, 4) connect _WIRE_204.pal, _T_2755 node _T_2756 = bits(_WIRE_205, 5, 5) connect _WIRE_204.ppp, _T_2756 node _T_2757 = bits(_WIRE_205, 6, 6) connect _WIRE_204.pr, _T_2757 node _T_2758 = bits(_WIRE_205, 7, 7) connect _WIRE_204.px, _T_2758 node _T_2759 = bits(_WIRE_205, 8, 8) connect _WIRE_204.pw, _T_2759 node _T_2760 = bits(_WIRE_205, 9, 9) connect _WIRE_204.hr, _T_2760 node _T_2761 = bits(_WIRE_205, 10, 10) connect _WIRE_204.hx, _T_2761 node _T_2762 = bits(_WIRE_205, 11, 11) connect _WIRE_204.hw, _T_2762 node _T_2763 = bits(_WIRE_205, 12, 12) connect _WIRE_204.sr, _T_2763 node _T_2764 = bits(_WIRE_205, 13, 13) connect _WIRE_204.sx, _T_2764 node _T_2765 = bits(_WIRE_205, 14, 14) connect _WIRE_204.sw, _T_2765 node _T_2766 = bits(_WIRE_205, 15, 15) connect _WIRE_204.gf, _T_2766 node _T_2767 = bits(_WIRE_205, 16, 16) connect _WIRE_204.pf, _T_2767 node _T_2768 = bits(_WIRE_205, 17, 17) connect _WIRE_204.ae_stage2, _T_2768 node _T_2769 = bits(_WIRE_205, 18, 18) connect _WIRE_204.ae_final, _T_2769 node _T_2770 = bits(_WIRE_205, 19, 19) connect _WIRE_204.ae_ptw, _T_2770 node _T_2771 = bits(_WIRE_205, 20, 20) connect _WIRE_204.g, _T_2771 node _T_2772 = bits(_WIRE_205, 21, 21) connect _WIRE_204.u, _T_2772 node _T_2773 = bits(_WIRE_205, 41, 22) connect _WIRE_204.ppn, _T_2773 wire _WIRE_206 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_207 : UInt<42> connect _WIRE_207, sectored_entries[0][6].data[3] node _T_2774 = bits(_WIRE_207, 0, 0) connect _WIRE_206.fragmented_superpage, _T_2774 node _T_2775 = bits(_WIRE_207, 1, 1) connect _WIRE_206.c, _T_2775 node _T_2776 = bits(_WIRE_207, 2, 2) connect _WIRE_206.eff, _T_2776 node _T_2777 = bits(_WIRE_207, 3, 3) connect _WIRE_206.paa, _T_2777 node _T_2778 = bits(_WIRE_207, 4, 4) connect _WIRE_206.pal, _T_2778 node _T_2779 = bits(_WIRE_207, 5, 5) connect _WIRE_206.ppp, _T_2779 node _T_2780 = bits(_WIRE_207, 6, 6) connect _WIRE_206.pr, _T_2780 node _T_2781 = bits(_WIRE_207, 7, 7) connect _WIRE_206.px, _T_2781 node _T_2782 = bits(_WIRE_207, 8, 8) connect _WIRE_206.pw, _T_2782 node _T_2783 = bits(_WIRE_207, 9, 9) connect _WIRE_206.hr, _T_2783 node _T_2784 = bits(_WIRE_207, 10, 10) connect _WIRE_206.hx, _T_2784 node _T_2785 = bits(_WIRE_207, 11, 11) connect _WIRE_206.hw, _T_2785 node _T_2786 = bits(_WIRE_207, 12, 12) connect _WIRE_206.sr, _T_2786 node _T_2787 = bits(_WIRE_207, 13, 13) connect _WIRE_206.sx, _T_2787 node _T_2788 = bits(_WIRE_207, 14, 14) connect _WIRE_206.sw, _T_2788 node _T_2789 = bits(_WIRE_207, 15, 15) connect _WIRE_206.gf, _T_2789 node _T_2790 = bits(_WIRE_207, 16, 16) connect _WIRE_206.pf, _T_2790 node _T_2791 = bits(_WIRE_207, 17, 17) connect _WIRE_206.ae_stage2, _T_2791 node _T_2792 = bits(_WIRE_207, 18, 18) connect _WIRE_206.ae_final, _T_2792 node _T_2793 = bits(_WIRE_207, 19, 19) connect _WIRE_206.ae_ptw, _T_2793 node _T_2794 = bits(_WIRE_207, 20, 20) connect _WIRE_206.g, _T_2794 node _T_2795 = bits(_WIRE_207, 21, 21) connect _WIRE_206.u, _T_2795 node _T_2796 = bits(_WIRE_207, 41, 22) connect _WIRE_206.ppn, _T_2796 node _T_2797 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2798 = and(_T_2797, _WIRE_200.fragmented_superpage) when _T_2798 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2799 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2800 = and(_T_2799, _WIRE_202.fragmented_superpage) when _T_2800 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2801 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2802 = and(_T_2801, _WIRE_204.fragmented_superpage) when _T_2802 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2803 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2804 = and(_T_2803, _WIRE_206.fragmented_superpage) when _T_2804 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2805 = eq(hg_6, UInt<1>(0h0)) node _T_2806 = and(_T_2805, io.sfence.bits.rs2) when _T_2806 : wire _WIRE_208 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_209 : UInt<42> connect _WIRE_209, sectored_entries[0][6].data[0] node _T_2807 = bits(_WIRE_209, 0, 0) connect _WIRE_208.fragmented_superpage, _T_2807 node _T_2808 = bits(_WIRE_209, 1, 1) connect _WIRE_208.c, _T_2808 node _T_2809 = bits(_WIRE_209, 2, 2) connect _WIRE_208.eff, _T_2809 node _T_2810 = bits(_WIRE_209, 3, 3) connect _WIRE_208.paa, _T_2810 node _T_2811 = bits(_WIRE_209, 4, 4) connect _WIRE_208.pal, _T_2811 node _T_2812 = bits(_WIRE_209, 5, 5) connect _WIRE_208.ppp, _T_2812 node _T_2813 = bits(_WIRE_209, 6, 6) connect _WIRE_208.pr, _T_2813 node _T_2814 = bits(_WIRE_209, 7, 7) connect _WIRE_208.px, _T_2814 node _T_2815 = bits(_WIRE_209, 8, 8) connect _WIRE_208.pw, _T_2815 node _T_2816 = bits(_WIRE_209, 9, 9) connect _WIRE_208.hr, _T_2816 node _T_2817 = bits(_WIRE_209, 10, 10) connect _WIRE_208.hx, _T_2817 node _T_2818 = bits(_WIRE_209, 11, 11) connect _WIRE_208.hw, _T_2818 node _T_2819 = bits(_WIRE_209, 12, 12) connect _WIRE_208.sr, _T_2819 node _T_2820 = bits(_WIRE_209, 13, 13) connect _WIRE_208.sx, _T_2820 node _T_2821 = bits(_WIRE_209, 14, 14) connect _WIRE_208.sw, _T_2821 node _T_2822 = bits(_WIRE_209, 15, 15) connect _WIRE_208.gf, _T_2822 node _T_2823 = bits(_WIRE_209, 16, 16) connect _WIRE_208.pf, _T_2823 node _T_2824 = bits(_WIRE_209, 17, 17) connect _WIRE_208.ae_stage2, _T_2824 node _T_2825 = bits(_WIRE_209, 18, 18) connect _WIRE_208.ae_final, _T_2825 node _T_2826 = bits(_WIRE_209, 19, 19) connect _WIRE_208.ae_ptw, _T_2826 node _T_2827 = bits(_WIRE_209, 20, 20) connect _WIRE_208.g, _T_2827 node _T_2828 = bits(_WIRE_209, 21, 21) connect _WIRE_208.u, _T_2828 node _T_2829 = bits(_WIRE_209, 41, 22) connect _WIRE_208.ppn, _T_2829 wire _WIRE_210 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_211 : UInt<42> connect _WIRE_211, sectored_entries[0][6].data[1] node _T_2830 = bits(_WIRE_211, 0, 0) connect _WIRE_210.fragmented_superpage, _T_2830 node _T_2831 = bits(_WIRE_211, 1, 1) connect _WIRE_210.c, _T_2831 node _T_2832 = bits(_WIRE_211, 2, 2) connect _WIRE_210.eff, _T_2832 node _T_2833 = bits(_WIRE_211, 3, 3) connect _WIRE_210.paa, _T_2833 node _T_2834 = bits(_WIRE_211, 4, 4) connect _WIRE_210.pal, _T_2834 node _T_2835 = bits(_WIRE_211, 5, 5) connect _WIRE_210.ppp, _T_2835 node _T_2836 = bits(_WIRE_211, 6, 6) connect _WIRE_210.pr, _T_2836 node _T_2837 = bits(_WIRE_211, 7, 7) connect _WIRE_210.px, _T_2837 node _T_2838 = bits(_WIRE_211, 8, 8) connect _WIRE_210.pw, _T_2838 node _T_2839 = bits(_WIRE_211, 9, 9) connect _WIRE_210.hr, _T_2839 node _T_2840 = bits(_WIRE_211, 10, 10) connect _WIRE_210.hx, _T_2840 node _T_2841 = bits(_WIRE_211, 11, 11) connect _WIRE_210.hw, _T_2841 node _T_2842 = bits(_WIRE_211, 12, 12) connect _WIRE_210.sr, _T_2842 node _T_2843 = bits(_WIRE_211, 13, 13) connect _WIRE_210.sx, _T_2843 node _T_2844 = bits(_WIRE_211, 14, 14) connect _WIRE_210.sw, _T_2844 node _T_2845 = bits(_WIRE_211, 15, 15) connect _WIRE_210.gf, _T_2845 node _T_2846 = bits(_WIRE_211, 16, 16) connect _WIRE_210.pf, _T_2846 node _T_2847 = bits(_WIRE_211, 17, 17) connect _WIRE_210.ae_stage2, _T_2847 node _T_2848 = bits(_WIRE_211, 18, 18) connect _WIRE_210.ae_final, _T_2848 node _T_2849 = bits(_WIRE_211, 19, 19) connect _WIRE_210.ae_ptw, _T_2849 node _T_2850 = bits(_WIRE_211, 20, 20) connect _WIRE_210.g, _T_2850 node _T_2851 = bits(_WIRE_211, 21, 21) connect _WIRE_210.u, _T_2851 node _T_2852 = bits(_WIRE_211, 41, 22) connect _WIRE_210.ppn, _T_2852 wire _WIRE_212 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_213 : UInt<42> connect _WIRE_213, sectored_entries[0][6].data[2] node _T_2853 = bits(_WIRE_213, 0, 0) connect _WIRE_212.fragmented_superpage, _T_2853 node _T_2854 = bits(_WIRE_213, 1, 1) connect _WIRE_212.c, _T_2854 node _T_2855 = bits(_WIRE_213, 2, 2) connect _WIRE_212.eff, _T_2855 node _T_2856 = bits(_WIRE_213, 3, 3) connect _WIRE_212.paa, _T_2856 node _T_2857 = bits(_WIRE_213, 4, 4) connect _WIRE_212.pal, _T_2857 node _T_2858 = bits(_WIRE_213, 5, 5) connect _WIRE_212.ppp, _T_2858 node _T_2859 = bits(_WIRE_213, 6, 6) connect _WIRE_212.pr, _T_2859 node _T_2860 = bits(_WIRE_213, 7, 7) connect _WIRE_212.px, _T_2860 node _T_2861 = bits(_WIRE_213, 8, 8) connect _WIRE_212.pw, _T_2861 node _T_2862 = bits(_WIRE_213, 9, 9) connect _WIRE_212.hr, _T_2862 node _T_2863 = bits(_WIRE_213, 10, 10) connect _WIRE_212.hx, _T_2863 node _T_2864 = bits(_WIRE_213, 11, 11) connect _WIRE_212.hw, _T_2864 node _T_2865 = bits(_WIRE_213, 12, 12) connect _WIRE_212.sr, _T_2865 node _T_2866 = bits(_WIRE_213, 13, 13) connect _WIRE_212.sx, _T_2866 node _T_2867 = bits(_WIRE_213, 14, 14) connect _WIRE_212.sw, _T_2867 node _T_2868 = bits(_WIRE_213, 15, 15) connect _WIRE_212.gf, _T_2868 node _T_2869 = bits(_WIRE_213, 16, 16) connect _WIRE_212.pf, _T_2869 node _T_2870 = bits(_WIRE_213, 17, 17) connect _WIRE_212.ae_stage2, _T_2870 node _T_2871 = bits(_WIRE_213, 18, 18) connect _WIRE_212.ae_final, _T_2871 node _T_2872 = bits(_WIRE_213, 19, 19) connect _WIRE_212.ae_ptw, _T_2872 node _T_2873 = bits(_WIRE_213, 20, 20) connect _WIRE_212.g, _T_2873 node _T_2874 = bits(_WIRE_213, 21, 21) connect _WIRE_212.u, _T_2874 node _T_2875 = bits(_WIRE_213, 41, 22) connect _WIRE_212.ppn, _T_2875 wire _WIRE_214 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_215 : UInt<42> connect _WIRE_215, sectored_entries[0][6].data[3] node _T_2876 = bits(_WIRE_215, 0, 0) connect _WIRE_214.fragmented_superpage, _T_2876 node _T_2877 = bits(_WIRE_215, 1, 1) connect _WIRE_214.c, _T_2877 node _T_2878 = bits(_WIRE_215, 2, 2) connect _WIRE_214.eff, _T_2878 node _T_2879 = bits(_WIRE_215, 3, 3) connect _WIRE_214.paa, _T_2879 node _T_2880 = bits(_WIRE_215, 4, 4) connect _WIRE_214.pal, _T_2880 node _T_2881 = bits(_WIRE_215, 5, 5) connect _WIRE_214.ppp, _T_2881 node _T_2882 = bits(_WIRE_215, 6, 6) connect _WIRE_214.pr, _T_2882 node _T_2883 = bits(_WIRE_215, 7, 7) connect _WIRE_214.px, _T_2883 node _T_2884 = bits(_WIRE_215, 8, 8) connect _WIRE_214.pw, _T_2884 node _T_2885 = bits(_WIRE_215, 9, 9) connect _WIRE_214.hr, _T_2885 node _T_2886 = bits(_WIRE_215, 10, 10) connect _WIRE_214.hx, _T_2886 node _T_2887 = bits(_WIRE_215, 11, 11) connect _WIRE_214.hw, _T_2887 node _T_2888 = bits(_WIRE_215, 12, 12) connect _WIRE_214.sr, _T_2888 node _T_2889 = bits(_WIRE_215, 13, 13) connect _WIRE_214.sx, _T_2889 node _T_2890 = bits(_WIRE_215, 14, 14) connect _WIRE_214.sw, _T_2890 node _T_2891 = bits(_WIRE_215, 15, 15) connect _WIRE_214.gf, _T_2891 node _T_2892 = bits(_WIRE_215, 16, 16) connect _WIRE_214.pf, _T_2892 node _T_2893 = bits(_WIRE_215, 17, 17) connect _WIRE_214.ae_stage2, _T_2893 node _T_2894 = bits(_WIRE_215, 18, 18) connect _WIRE_214.ae_final, _T_2894 node _T_2895 = bits(_WIRE_215, 19, 19) connect _WIRE_214.ae_ptw, _T_2895 node _T_2896 = bits(_WIRE_215, 20, 20) connect _WIRE_214.g, _T_2896 node _T_2897 = bits(_WIRE_215, 21, 21) connect _WIRE_214.u, _T_2897 node _T_2898 = bits(_WIRE_215, 41, 22) connect _WIRE_214.ppn, _T_2898 node _T_2899 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2900 = eq(_WIRE_208.g, UInt<1>(0h0)) node _T_2901 = and(_T_2899, _T_2900) when _T_2901 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2902 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2903 = eq(_WIRE_210.g, UInt<1>(0h0)) node _T_2904 = and(_T_2902, _T_2903) when _T_2904 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2905 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2906 = eq(_WIRE_212.g, UInt<1>(0h0)) node _T_2907 = and(_T_2905, _T_2906) when _T_2907 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2908 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2909 = eq(_WIRE_214.g, UInt<1>(0h0)) node _T_2910 = and(_T_2908, _T_2909) when _T_2910 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2911 = or(hv_6, hg_6) wire _WIRE_216 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_217 : UInt<42> connect _WIRE_217, sectored_entries[0][6].data[0] node _T_2912 = bits(_WIRE_217, 0, 0) connect _WIRE_216.fragmented_superpage, _T_2912 node _T_2913 = bits(_WIRE_217, 1, 1) connect _WIRE_216.c, _T_2913 node _T_2914 = bits(_WIRE_217, 2, 2) connect _WIRE_216.eff, _T_2914 node _T_2915 = bits(_WIRE_217, 3, 3) connect _WIRE_216.paa, _T_2915 node _T_2916 = bits(_WIRE_217, 4, 4) connect _WIRE_216.pal, _T_2916 node _T_2917 = bits(_WIRE_217, 5, 5) connect _WIRE_216.ppp, _T_2917 node _T_2918 = bits(_WIRE_217, 6, 6) connect _WIRE_216.pr, _T_2918 node _T_2919 = bits(_WIRE_217, 7, 7) connect _WIRE_216.px, _T_2919 node _T_2920 = bits(_WIRE_217, 8, 8) connect _WIRE_216.pw, _T_2920 node _T_2921 = bits(_WIRE_217, 9, 9) connect _WIRE_216.hr, _T_2921 node _T_2922 = bits(_WIRE_217, 10, 10) connect _WIRE_216.hx, _T_2922 node _T_2923 = bits(_WIRE_217, 11, 11) connect _WIRE_216.hw, _T_2923 node _T_2924 = bits(_WIRE_217, 12, 12) connect _WIRE_216.sr, _T_2924 node _T_2925 = bits(_WIRE_217, 13, 13) connect _WIRE_216.sx, _T_2925 node _T_2926 = bits(_WIRE_217, 14, 14) connect _WIRE_216.sw, _T_2926 node _T_2927 = bits(_WIRE_217, 15, 15) connect _WIRE_216.gf, _T_2927 node _T_2928 = bits(_WIRE_217, 16, 16) connect _WIRE_216.pf, _T_2928 node _T_2929 = bits(_WIRE_217, 17, 17) connect _WIRE_216.ae_stage2, _T_2929 node _T_2930 = bits(_WIRE_217, 18, 18) connect _WIRE_216.ae_final, _T_2930 node _T_2931 = bits(_WIRE_217, 19, 19) connect _WIRE_216.ae_ptw, _T_2931 node _T_2932 = bits(_WIRE_217, 20, 20) connect _WIRE_216.g, _T_2932 node _T_2933 = bits(_WIRE_217, 21, 21) connect _WIRE_216.u, _T_2933 node _T_2934 = bits(_WIRE_217, 41, 22) connect _WIRE_216.ppn, _T_2934 wire _WIRE_218 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_219 : UInt<42> connect _WIRE_219, sectored_entries[0][6].data[1] node _T_2935 = bits(_WIRE_219, 0, 0) connect _WIRE_218.fragmented_superpage, _T_2935 node _T_2936 = bits(_WIRE_219, 1, 1) connect _WIRE_218.c, _T_2936 node _T_2937 = bits(_WIRE_219, 2, 2) connect _WIRE_218.eff, _T_2937 node _T_2938 = bits(_WIRE_219, 3, 3) connect _WIRE_218.paa, _T_2938 node _T_2939 = bits(_WIRE_219, 4, 4) connect _WIRE_218.pal, _T_2939 node _T_2940 = bits(_WIRE_219, 5, 5) connect _WIRE_218.ppp, _T_2940 node _T_2941 = bits(_WIRE_219, 6, 6) connect _WIRE_218.pr, _T_2941 node _T_2942 = bits(_WIRE_219, 7, 7) connect _WIRE_218.px, _T_2942 node _T_2943 = bits(_WIRE_219, 8, 8) connect _WIRE_218.pw, _T_2943 node _T_2944 = bits(_WIRE_219, 9, 9) connect _WIRE_218.hr, _T_2944 node _T_2945 = bits(_WIRE_219, 10, 10) connect _WIRE_218.hx, _T_2945 node _T_2946 = bits(_WIRE_219, 11, 11) connect _WIRE_218.hw, _T_2946 node _T_2947 = bits(_WIRE_219, 12, 12) connect _WIRE_218.sr, _T_2947 node _T_2948 = bits(_WIRE_219, 13, 13) connect _WIRE_218.sx, _T_2948 node _T_2949 = bits(_WIRE_219, 14, 14) connect _WIRE_218.sw, _T_2949 node _T_2950 = bits(_WIRE_219, 15, 15) connect _WIRE_218.gf, _T_2950 node _T_2951 = bits(_WIRE_219, 16, 16) connect _WIRE_218.pf, _T_2951 node _T_2952 = bits(_WIRE_219, 17, 17) connect _WIRE_218.ae_stage2, _T_2952 node _T_2953 = bits(_WIRE_219, 18, 18) connect _WIRE_218.ae_final, _T_2953 node _T_2954 = bits(_WIRE_219, 19, 19) connect _WIRE_218.ae_ptw, _T_2954 node _T_2955 = bits(_WIRE_219, 20, 20) connect _WIRE_218.g, _T_2955 node _T_2956 = bits(_WIRE_219, 21, 21) connect _WIRE_218.u, _T_2956 node _T_2957 = bits(_WIRE_219, 41, 22) connect _WIRE_218.ppn, _T_2957 wire _WIRE_220 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_221 : UInt<42> connect _WIRE_221, sectored_entries[0][6].data[2] node _T_2958 = bits(_WIRE_221, 0, 0) connect _WIRE_220.fragmented_superpage, _T_2958 node _T_2959 = bits(_WIRE_221, 1, 1) connect _WIRE_220.c, _T_2959 node _T_2960 = bits(_WIRE_221, 2, 2) connect _WIRE_220.eff, _T_2960 node _T_2961 = bits(_WIRE_221, 3, 3) connect _WIRE_220.paa, _T_2961 node _T_2962 = bits(_WIRE_221, 4, 4) connect _WIRE_220.pal, _T_2962 node _T_2963 = bits(_WIRE_221, 5, 5) connect _WIRE_220.ppp, _T_2963 node _T_2964 = bits(_WIRE_221, 6, 6) connect _WIRE_220.pr, _T_2964 node _T_2965 = bits(_WIRE_221, 7, 7) connect _WIRE_220.px, _T_2965 node _T_2966 = bits(_WIRE_221, 8, 8) connect _WIRE_220.pw, _T_2966 node _T_2967 = bits(_WIRE_221, 9, 9) connect _WIRE_220.hr, _T_2967 node _T_2968 = bits(_WIRE_221, 10, 10) connect _WIRE_220.hx, _T_2968 node _T_2969 = bits(_WIRE_221, 11, 11) connect _WIRE_220.hw, _T_2969 node _T_2970 = bits(_WIRE_221, 12, 12) connect _WIRE_220.sr, _T_2970 node _T_2971 = bits(_WIRE_221, 13, 13) connect _WIRE_220.sx, _T_2971 node _T_2972 = bits(_WIRE_221, 14, 14) connect _WIRE_220.sw, _T_2972 node _T_2973 = bits(_WIRE_221, 15, 15) connect _WIRE_220.gf, _T_2973 node _T_2974 = bits(_WIRE_221, 16, 16) connect _WIRE_220.pf, _T_2974 node _T_2975 = bits(_WIRE_221, 17, 17) connect _WIRE_220.ae_stage2, _T_2975 node _T_2976 = bits(_WIRE_221, 18, 18) connect _WIRE_220.ae_final, _T_2976 node _T_2977 = bits(_WIRE_221, 19, 19) connect _WIRE_220.ae_ptw, _T_2977 node _T_2978 = bits(_WIRE_221, 20, 20) connect _WIRE_220.g, _T_2978 node _T_2979 = bits(_WIRE_221, 21, 21) connect _WIRE_220.u, _T_2979 node _T_2980 = bits(_WIRE_221, 41, 22) connect _WIRE_220.ppn, _T_2980 wire _WIRE_222 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_223 : UInt<42> connect _WIRE_223, sectored_entries[0][6].data[3] node _T_2981 = bits(_WIRE_223, 0, 0) connect _WIRE_222.fragmented_superpage, _T_2981 node _T_2982 = bits(_WIRE_223, 1, 1) connect _WIRE_222.c, _T_2982 node _T_2983 = bits(_WIRE_223, 2, 2) connect _WIRE_222.eff, _T_2983 node _T_2984 = bits(_WIRE_223, 3, 3) connect _WIRE_222.paa, _T_2984 node _T_2985 = bits(_WIRE_223, 4, 4) connect _WIRE_222.pal, _T_2985 node _T_2986 = bits(_WIRE_223, 5, 5) connect _WIRE_222.ppp, _T_2986 node _T_2987 = bits(_WIRE_223, 6, 6) connect _WIRE_222.pr, _T_2987 node _T_2988 = bits(_WIRE_223, 7, 7) connect _WIRE_222.px, _T_2988 node _T_2989 = bits(_WIRE_223, 8, 8) connect _WIRE_222.pw, _T_2989 node _T_2990 = bits(_WIRE_223, 9, 9) connect _WIRE_222.hr, _T_2990 node _T_2991 = bits(_WIRE_223, 10, 10) connect _WIRE_222.hx, _T_2991 node _T_2992 = bits(_WIRE_223, 11, 11) connect _WIRE_222.hw, _T_2992 node _T_2993 = bits(_WIRE_223, 12, 12) connect _WIRE_222.sr, _T_2993 node _T_2994 = bits(_WIRE_223, 13, 13) connect _WIRE_222.sx, _T_2994 node _T_2995 = bits(_WIRE_223, 14, 14) connect _WIRE_222.sw, _T_2995 node _T_2996 = bits(_WIRE_223, 15, 15) connect _WIRE_222.gf, _T_2996 node _T_2997 = bits(_WIRE_223, 16, 16) connect _WIRE_222.pf, _T_2997 node _T_2998 = bits(_WIRE_223, 17, 17) connect _WIRE_222.ae_stage2, _T_2998 node _T_2999 = bits(_WIRE_223, 18, 18) connect _WIRE_222.ae_final, _T_2999 node _T_3000 = bits(_WIRE_223, 19, 19) connect _WIRE_222.ae_ptw, _T_3000 node _T_3001 = bits(_WIRE_223, 20, 20) connect _WIRE_222.g, _T_3001 node _T_3002 = bits(_WIRE_223, 21, 21) connect _WIRE_222.u, _T_3002 node _T_3003 = bits(_WIRE_223, 41, 22) connect _WIRE_222.ppn, _T_3003 node _T_3004 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3004 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_3005 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3005 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_3006 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3006 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_3007 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3007 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3008 = eq(hg_7, UInt<1>(0h0)) node _T_3009 = and(_T_3008, io.sfence.bits.rs1) when _T_3009 : node _T_3010 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3011 = shr(_T_3010, 2) node _T_3012 = eq(_T_3011, UInt<1>(0h0)) node _T_3013 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3014 = and(_T_3012, _T_3013) when _T_3014 : wire _WIRE_224 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_225 : UInt<42> connect _WIRE_225, sectored_entries[0][7].data[0] node _T_3015 = bits(_WIRE_225, 0, 0) connect _WIRE_224.fragmented_superpage, _T_3015 node _T_3016 = bits(_WIRE_225, 1, 1) connect _WIRE_224.c, _T_3016 node _T_3017 = bits(_WIRE_225, 2, 2) connect _WIRE_224.eff, _T_3017 node _T_3018 = bits(_WIRE_225, 3, 3) connect _WIRE_224.paa, _T_3018 node _T_3019 = bits(_WIRE_225, 4, 4) connect _WIRE_224.pal, _T_3019 node _T_3020 = bits(_WIRE_225, 5, 5) connect _WIRE_224.ppp, _T_3020 node _T_3021 = bits(_WIRE_225, 6, 6) connect _WIRE_224.pr, _T_3021 node _T_3022 = bits(_WIRE_225, 7, 7) connect _WIRE_224.px, _T_3022 node _T_3023 = bits(_WIRE_225, 8, 8) connect _WIRE_224.pw, _T_3023 node _T_3024 = bits(_WIRE_225, 9, 9) connect _WIRE_224.hr, _T_3024 node _T_3025 = bits(_WIRE_225, 10, 10) connect _WIRE_224.hx, _T_3025 node _T_3026 = bits(_WIRE_225, 11, 11) connect _WIRE_224.hw, _T_3026 node _T_3027 = bits(_WIRE_225, 12, 12) connect _WIRE_224.sr, _T_3027 node _T_3028 = bits(_WIRE_225, 13, 13) connect _WIRE_224.sx, _T_3028 node _T_3029 = bits(_WIRE_225, 14, 14) connect _WIRE_224.sw, _T_3029 node _T_3030 = bits(_WIRE_225, 15, 15) connect _WIRE_224.gf, _T_3030 node _T_3031 = bits(_WIRE_225, 16, 16) connect _WIRE_224.pf, _T_3031 node _T_3032 = bits(_WIRE_225, 17, 17) connect _WIRE_224.ae_stage2, _T_3032 node _T_3033 = bits(_WIRE_225, 18, 18) connect _WIRE_224.ae_final, _T_3033 node _T_3034 = bits(_WIRE_225, 19, 19) connect _WIRE_224.ae_ptw, _T_3034 node _T_3035 = bits(_WIRE_225, 20, 20) connect _WIRE_224.g, _T_3035 node _T_3036 = bits(_WIRE_225, 21, 21) connect _WIRE_224.u, _T_3036 node _T_3037 = bits(_WIRE_225, 41, 22) connect _WIRE_224.ppn, _T_3037 wire _WIRE_226 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_227 : UInt<42> connect _WIRE_227, sectored_entries[0][7].data[1] node _T_3038 = bits(_WIRE_227, 0, 0) connect _WIRE_226.fragmented_superpage, _T_3038 node _T_3039 = bits(_WIRE_227, 1, 1) connect _WIRE_226.c, _T_3039 node _T_3040 = bits(_WIRE_227, 2, 2) connect _WIRE_226.eff, _T_3040 node _T_3041 = bits(_WIRE_227, 3, 3) connect _WIRE_226.paa, _T_3041 node _T_3042 = bits(_WIRE_227, 4, 4) connect _WIRE_226.pal, _T_3042 node _T_3043 = bits(_WIRE_227, 5, 5) connect _WIRE_226.ppp, _T_3043 node _T_3044 = bits(_WIRE_227, 6, 6) connect _WIRE_226.pr, _T_3044 node _T_3045 = bits(_WIRE_227, 7, 7) connect _WIRE_226.px, _T_3045 node _T_3046 = bits(_WIRE_227, 8, 8) connect _WIRE_226.pw, _T_3046 node _T_3047 = bits(_WIRE_227, 9, 9) connect _WIRE_226.hr, _T_3047 node _T_3048 = bits(_WIRE_227, 10, 10) connect _WIRE_226.hx, _T_3048 node _T_3049 = bits(_WIRE_227, 11, 11) connect _WIRE_226.hw, _T_3049 node _T_3050 = bits(_WIRE_227, 12, 12) connect _WIRE_226.sr, _T_3050 node _T_3051 = bits(_WIRE_227, 13, 13) connect _WIRE_226.sx, _T_3051 node _T_3052 = bits(_WIRE_227, 14, 14) connect _WIRE_226.sw, _T_3052 node _T_3053 = bits(_WIRE_227, 15, 15) connect _WIRE_226.gf, _T_3053 node _T_3054 = bits(_WIRE_227, 16, 16) connect _WIRE_226.pf, _T_3054 node _T_3055 = bits(_WIRE_227, 17, 17) connect _WIRE_226.ae_stage2, _T_3055 node _T_3056 = bits(_WIRE_227, 18, 18) connect _WIRE_226.ae_final, _T_3056 node _T_3057 = bits(_WIRE_227, 19, 19) connect _WIRE_226.ae_ptw, _T_3057 node _T_3058 = bits(_WIRE_227, 20, 20) connect _WIRE_226.g, _T_3058 node _T_3059 = bits(_WIRE_227, 21, 21) connect _WIRE_226.u, _T_3059 node _T_3060 = bits(_WIRE_227, 41, 22) connect _WIRE_226.ppn, _T_3060 wire _WIRE_228 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_229 : UInt<42> connect _WIRE_229, sectored_entries[0][7].data[2] node _T_3061 = bits(_WIRE_229, 0, 0) connect _WIRE_228.fragmented_superpage, _T_3061 node _T_3062 = bits(_WIRE_229, 1, 1) connect _WIRE_228.c, _T_3062 node _T_3063 = bits(_WIRE_229, 2, 2) connect _WIRE_228.eff, _T_3063 node _T_3064 = bits(_WIRE_229, 3, 3) connect _WIRE_228.paa, _T_3064 node _T_3065 = bits(_WIRE_229, 4, 4) connect _WIRE_228.pal, _T_3065 node _T_3066 = bits(_WIRE_229, 5, 5) connect _WIRE_228.ppp, _T_3066 node _T_3067 = bits(_WIRE_229, 6, 6) connect _WIRE_228.pr, _T_3067 node _T_3068 = bits(_WIRE_229, 7, 7) connect _WIRE_228.px, _T_3068 node _T_3069 = bits(_WIRE_229, 8, 8) connect _WIRE_228.pw, _T_3069 node _T_3070 = bits(_WIRE_229, 9, 9) connect _WIRE_228.hr, _T_3070 node _T_3071 = bits(_WIRE_229, 10, 10) connect _WIRE_228.hx, _T_3071 node _T_3072 = bits(_WIRE_229, 11, 11) connect _WIRE_228.hw, _T_3072 node _T_3073 = bits(_WIRE_229, 12, 12) connect _WIRE_228.sr, _T_3073 node _T_3074 = bits(_WIRE_229, 13, 13) connect _WIRE_228.sx, _T_3074 node _T_3075 = bits(_WIRE_229, 14, 14) connect _WIRE_228.sw, _T_3075 node _T_3076 = bits(_WIRE_229, 15, 15) connect _WIRE_228.gf, _T_3076 node _T_3077 = bits(_WIRE_229, 16, 16) connect _WIRE_228.pf, _T_3077 node _T_3078 = bits(_WIRE_229, 17, 17) connect _WIRE_228.ae_stage2, _T_3078 node _T_3079 = bits(_WIRE_229, 18, 18) connect _WIRE_228.ae_final, _T_3079 node _T_3080 = bits(_WIRE_229, 19, 19) connect _WIRE_228.ae_ptw, _T_3080 node _T_3081 = bits(_WIRE_229, 20, 20) connect _WIRE_228.g, _T_3081 node _T_3082 = bits(_WIRE_229, 21, 21) connect _WIRE_228.u, _T_3082 node _T_3083 = bits(_WIRE_229, 41, 22) connect _WIRE_228.ppn, _T_3083 wire _WIRE_230 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_231 : UInt<42> connect _WIRE_231, sectored_entries[0][7].data[3] node _T_3084 = bits(_WIRE_231, 0, 0) connect _WIRE_230.fragmented_superpage, _T_3084 node _T_3085 = bits(_WIRE_231, 1, 1) connect _WIRE_230.c, _T_3085 node _T_3086 = bits(_WIRE_231, 2, 2) connect _WIRE_230.eff, _T_3086 node _T_3087 = bits(_WIRE_231, 3, 3) connect _WIRE_230.paa, _T_3087 node _T_3088 = bits(_WIRE_231, 4, 4) connect _WIRE_230.pal, _T_3088 node _T_3089 = bits(_WIRE_231, 5, 5) connect _WIRE_230.ppp, _T_3089 node _T_3090 = bits(_WIRE_231, 6, 6) connect _WIRE_230.pr, _T_3090 node _T_3091 = bits(_WIRE_231, 7, 7) connect _WIRE_230.px, _T_3091 node _T_3092 = bits(_WIRE_231, 8, 8) connect _WIRE_230.pw, _T_3092 node _T_3093 = bits(_WIRE_231, 9, 9) connect _WIRE_230.hr, _T_3093 node _T_3094 = bits(_WIRE_231, 10, 10) connect _WIRE_230.hx, _T_3094 node _T_3095 = bits(_WIRE_231, 11, 11) connect _WIRE_230.hw, _T_3095 node _T_3096 = bits(_WIRE_231, 12, 12) connect _WIRE_230.sr, _T_3096 node _T_3097 = bits(_WIRE_231, 13, 13) connect _WIRE_230.sx, _T_3097 node _T_3098 = bits(_WIRE_231, 14, 14) connect _WIRE_230.sw, _T_3098 node _T_3099 = bits(_WIRE_231, 15, 15) connect _WIRE_230.gf, _T_3099 node _T_3100 = bits(_WIRE_231, 16, 16) connect _WIRE_230.pf, _T_3100 node _T_3101 = bits(_WIRE_231, 17, 17) connect _WIRE_230.ae_stage2, _T_3101 node _T_3102 = bits(_WIRE_231, 18, 18) connect _WIRE_230.ae_final, _T_3102 node _T_3103 = bits(_WIRE_231, 19, 19) connect _WIRE_230.ae_ptw, _T_3103 node _T_3104 = bits(_WIRE_231, 20, 20) connect _WIRE_230.g, _T_3104 node _T_3105 = bits(_WIRE_231, 21, 21) connect _WIRE_230.u, _T_3105 node _T_3106 = bits(_WIRE_231, 41, 22) connect _WIRE_230.ppn, _T_3106 node _T_3107 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3108 = bits(vpn, 1, 0) node _T_3109 = eq(UInt<1>(0h0), _T_3108) node _T_3110 = and(_T_3107, _T_3109) when _T_3110 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3111 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3112 = bits(vpn, 1, 0) node _T_3113 = eq(UInt<1>(0h1), _T_3112) node _T_3114 = and(_T_3111, _T_3113) when _T_3114 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3115 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3116 = bits(vpn, 1, 0) node _T_3117 = eq(UInt<2>(0h2), _T_3116) node _T_3118 = and(_T_3115, _T_3117) when _T_3118 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3119 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3120 = bits(vpn, 1, 0) node _T_3121 = eq(UInt<2>(0h3), _T_3120) node _T_3122 = and(_T_3119, _T_3121) when _T_3122 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node _T_3123 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3124 = shr(_T_3123, 18) node _T_3125 = eq(_T_3124, UInt<1>(0h0)) when _T_3125 : wire _WIRE_232 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_233 : UInt<42> connect _WIRE_233, sectored_entries[0][7].data[0] node _T_3126 = bits(_WIRE_233, 0, 0) connect _WIRE_232.fragmented_superpage, _T_3126 node _T_3127 = bits(_WIRE_233, 1, 1) connect _WIRE_232.c, _T_3127 node _T_3128 = bits(_WIRE_233, 2, 2) connect _WIRE_232.eff, _T_3128 node _T_3129 = bits(_WIRE_233, 3, 3) connect _WIRE_232.paa, _T_3129 node _T_3130 = bits(_WIRE_233, 4, 4) connect _WIRE_232.pal, _T_3130 node _T_3131 = bits(_WIRE_233, 5, 5) connect _WIRE_232.ppp, _T_3131 node _T_3132 = bits(_WIRE_233, 6, 6) connect _WIRE_232.pr, _T_3132 node _T_3133 = bits(_WIRE_233, 7, 7) connect _WIRE_232.px, _T_3133 node _T_3134 = bits(_WIRE_233, 8, 8) connect _WIRE_232.pw, _T_3134 node _T_3135 = bits(_WIRE_233, 9, 9) connect _WIRE_232.hr, _T_3135 node _T_3136 = bits(_WIRE_233, 10, 10) connect _WIRE_232.hx, _T_3136 node _T_3137 = bits(_WIRE_233, 11, 11) connect _WIRE_232.hw, _T_3137 node _T_3138 = bits(_WIRE_233, 12, 12) connect _WIRE_232.sr, _T_3138 node _T_3139 = bits(_WIRE_233, 13, 13) connect _WIRE_232.sx, _T_3139 node _T_3140 = bits(_WIRE_233, 14, 14) connect _WIRE_232.sw, _T_3140 node _T_3141 = bits(_WIRE_233, 15, 15) connect _WIRE_232.gf, _T_3141 node _T_3142 = bits(_WIRE_233, 16, 16) connect _WIRE_232.pf, _T_3142 node _T_3143 = bits(_WIRE_233, 17, 17) connect _WIRE_232.ae_stage2, _T_3143 node _T_3144 = bits(_WIRE_233, 18, 18) connect _WIRE_232.ae_final, _T_3144 node _T_3145 = bits(_WIRE_233, 19, 19) connect _WIRE_232.ae_ptw, _T_3145 node _T_3146 = bits(_WIRE_233, 20, 20) connect _WIRE_232.g, _T_3146 node _T_3147 = bits(_WIRE_233, 21, 21) connect _WIRE_232.u, _T_3147 node _T_3148 = bits(_WIRE_233, 41, 22) connect _WIRE_232.ppn, _T_3148 wire _WIRE_234 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_235 : UInt<42> connect _WIRE_235, sectored_entries[0][7].data[1] node _T_3149 = bits(_WIRE_235, 0, 0) connect _WIRE_234.fragmented_superpage, _T_3149 node _T_3150 = bits(_WIRE_235, 1, 1) connect _WIRE_234.c, _T_3150 node _T_3151 = bits(_WIRE_235, 2, 2) connect _WIRE_234.eff, _T_3151 node _T_3152 = bits(_WIRE_235, 3, 3) connect _WIRE_234.paa, _T_3152 node _T_3153 = bits(_WIRE_235, 4, 4) connect _WIRE_234.pal, _T_3153 node _T_3154 = bits(_WIRE_235, 5, 5) connect _WIRE_234.ppp, _T_3154 node _T_3155 = bits(_WIRE_235, 6, 6) connect _WIRE_234.pr, _T_3155 node _T_3156 = bits(_WIRE_235, 7, 7) connect _WIRE_234.px, _T_3156 node _T_3157 = bits(_WIRE_235, 8, 8) connect _WIRE_234.pw, _T_3157 node _T_3158 = bits(_WIRE_235, 9, 9) connect _WIRE_234.hr, _T_3158 node _T_3159 = bits(_WIRE_235, 10, 10) connect _WIRE_234.hx, _T_3159 node _T_3160 = bits(_WIRE_235, 11, 11) connect _WIRE_234.hw, _T_3160 node _T_3161 = bits(_WIRE_235, 12, 12) connect _WIRE_234.sr, _T_3161 node _T_3162 = bits(_WIRE_235, 13, 13) connect _WIRE_234.sx, _T_3162 node _T_3163 = bits(_WIRE_235, 14, 14) connect _WIRE_234.sw, _T_3163 node _T_3164 = bits(_WIRE_235, 15, 15) connect _WIRE_234.gf, _T_3164 node _T_3165 = bits(_WIRE_235, 16, 16) connect _WIRE_234.pf, _T_3165 node _T_3166 = bits(_WIRE_235, 17, 17) connect _WIRE_234.ae_stage2, _T_3166 node _T_3167 = bits(_WIRE_235, 18, 18) connect _WIRE_234.ae_final, _T_3167 node _T_3168 = bits(_WIRE_235, 19, 19) connect _WIRE_234.ae_ptw, _T_3168 node _T_3169 = bits(_WIRE_235, 20, 20) connect _WIRE_234.g, _T_3169 node _T_3170 = bits(_WIRE_235, 21, 21) connect _WIRE_234.u, _T_3170 node _T_3171 = bits(_WIRE_235, 41, 22) connect _WIRE_234.ppn, _T_3171 wire _WIRE_236 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_237 : UInt<42> connect _WIRE_237, sectored_entries[0][7].data[2] node _T_3172 = bits(_WIRE_237, 0, 0) connect _WIRE_236.fragmented_superpage, _T_3172 node _T_3173 = bits(_WIRE_237, 1, 1) connect _WIRE_236.c, _T_3173 node _T_3174 = bits(_WIRE_237, 2, 2) connect _WIRE_236.eff, _T_3174 node _T_3175 = bits(_WIRE_237, 3, 3) connect _WIRE_236.paa, _T_3175 node _T_3176 = bits(_WIRE_237, 4, 4) connect _WIRE_236.pal, _T_3176 node _T_3177 = bits(_WIRE_237, 5, 5) connect _WIRE_236.ppp, _T_3177 node _T_3178 = bits(_WIRE_237, 6, 6) connect _WIRE_236.pr, _T_3178 node _T_3179 = bits(_WIRE_237, 7, 7) connect _WIRE_236.px, _T_3179 node _T_3180 = bits(_WIRE_237, 8, 8) connect _WIRE_236.pw, _T_3180 node _T_3181 = bits(_WIRE_237, 9, 9) connect _WIRE_236.hr, _T_3181 node _T_3182 = bits(_WIRE_237, 10, 10) connect _WIRE_236.hx, _T_3182 node _T_3183 = bits(_WIRE_237, 11, 11) connect _WIRE_236.hw, _T_3183 node _T_3184 = bits(_WIRE_237, 12, 12) connect _WIRE_236.sr, _T_3184 node _T_3185 = bits(_WIRE_237, 13, 13) connect _WIRE_236.sx, _T_3185 node _T_3186 = bits(_WIRE_237, 14, 14) connect _WIRE_236.sw, _T_3186 node _T_3187 = bits(_WIRE_237, 15, 15) connect _WIRE_236.gf, _T_3187 node _T_3188 = bits(_WIRE_237, 16, 16) connect _WIRE_236.pf, _T_3188 node _T_3189 = bits(_WIRE_237, 17, 17) connect _WIRE_236.ae_stage2, _T_3189 node _T_3190 = bits(_WIRE_237, 18, 18) connect _WIRE_236.ae_final, _T_3190 node _T_3191 = bits(_WIRE_237, 19, 19) connect _WIRE_236.ae_ptw, _T_3191 node _T_3192 = bits(_WIRE_237, 20, 20) connect _WIRE_236.g, _T_3192 node _T_3193 = bits(_WIRE_237, 21, 21) connect _WIRE_236.u, _T_3193 node _T_3194 = bits(_WIRE_237, 41, 22) connect _WIRE_236.ppn, _T_3194 wire _WIRE_238 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_239 : UInt<42> connect _WIRE_239, sectored_entries[0][7].data[3] node _T_3195 = bits(_WIRE_239, 0, 0) connect _WIRE_238.fragmented_superpage, _T_3195 node _T_3196 = bits(_WIRE_239, 1, 1) connect _WIRE_238.c, _T_3196 node _T_3197 = bits(_WIRE_239, 2, 2) connect _WIRE_238.eff, _T_3197 node _T_3198 = bits(_WIRE_239, 3, 3) connect _WIRE_238.paa, _T_3198 node _T_3199 = bits(_WIRE_239, 4, 4) connect _WIRE_238.pal, _T_3199 node _T_3200 = bits(_WIRE_239, 5, 5) connect _WIRE_238.ppp, _T_3200 node _T_3201 = bits(_WIRE_239, 6, 6) connect _WIRE_238.pr, _T_3201 node _T_3202 = bits(_WIRE_239, 7, 7) connect _WIRE_238.px, _T_3202 node _T_3203 = bits(_WIRE_239, 8, 8) connect _WIRE_238.pw, _T_3203 node _T_3204 = bits(_WIRE_239, 9, 9) connect _WIRE_238.hr, _T_3204 node _T_3205 = bits(_WIRE_239, 10, 10) connect _WIRE_238.hx, _T_3205 node _T_3206 = bits(_WIRE_239, 11, 11) connect _WIRE_238.hw, _T_3206 node _T_3207 = bits(_WIRE_239, 12, 12) connect _WIRE_238.sr, _T_3207 node _T_3208 = bits(_WIRE_239, 13, 13) connect _WIRE_238.sx, _T_3208 node _T_3209 = bits(_WIRE_239, 14, 14) connect _WIRE_238.sw, _T_3209 node _T_3210 = bits(_WIRE_239, 15, 15) connect _WIRE_238.gf, _T_3210 node _T_3211 = bits(_WIRE_239, 16, 16) connect _WIRE_238.pf, _T_3211 node _T_3212 = bits(_WIRE_239, 17, 17) connect _WIRE_238.ae_stage2, _T_3212 node _T_3213 = bits(_WIRE_239, 18, 18) connect _WIRE_238.ae_final, _T_3213 node _T_3214 = bits(_WIRE_239, 19, 19) connect _WIRE_238.ae_ptw, _T_3214 node _T_3215 = bits(_WIRE_239, 20, 20) connect _WIRE_238.g, _T_3215 node _T_3216 = bits(_WIRE_239, 21, 21) connect _WIRE_238.u, _T_3216 node _T_3217 = bits(_WIRE_239, 41, 22) connect _WIRE_238.ppn, _T_3217 node _T_3218 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3219 = and(_T_3218, _WIRE_232.fragmented_superpage) when _T_3219 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3220 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3221 = and(_T_3220, _WIRE_234.fragmented_superpage) when _T_3221 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3222 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3223 = and(_T_3222, _WIRE_236.fragmented_superpage) when _T_3223 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3224 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3225 = and(_T_3224, _WIRE_238.fragmented_superpage) when _T_3225 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3226 = eq(hg_7, UInt<1>(0h0)) node _T_3227 = and(_T_3226, io.sfence.bits.rs2) when _T_3227 : wire _WIRE_240 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_241 : UInt<42> connect _WIRE_241, sectored_entries[0][7].data[0] node _T_3228 = bits(_WIRE_241, 0, 0) connect _WIRE_240.fragmented_superpage, _T_3228 node _T_3229 = bits(_WIRE_241, 1, 1) connect _WIRE_240.c, _T_3229 node _T_3230 = bits(_WIRE_241, 2, 2) connect _WIRE_240.eff, _T_3230 node _T_3231 = bits(_WIRE_241, 3, 3) connect _WIRE_240.paa, _T_3231 node _T_3232 = bits(_WIRE_241, 4, 4) connect _WIRE_240.pal, _T_3232 node _T_3233 = bits(_WIRE_241, 5, 5) connect _WIRE_240.ppp, _T_3233 node _T_3234 = bits(_WIRE_241, 6, 6) connect _WIRE_240.pr, _T_3234 node _T_3235 = bits(_WIRE_241, 7, 7) connect _WIRE_240.px, _T_3235 node _T_3236 = bits(_WIRE_241, 8, 8) connect _WIRE_240.pw, _T_3236 node _T_3237 = bits(_WIRE_241, 9, 9) connect _WIRE_240.hr, _T_3237 node _T_3238 = bits(_WIRE_241, 10, 10) connect _WIRE_240.hx, _T_3238 node _T_3239 = bits(_WIRE_241, 11, 11) connect _WIRE_240.hw, _T_3239 node _T_3240 = bits(_WIRE_241, 12, 12) connect _WIRE_240.sr, _T_3240 node _T_3241 = bits(_WIRE_241, 13, 13) connect _WIRE_240.sx, _T_3241 node _T_3242 = bits(_WIRE_241, 14, 14) connect _WIRE_240.sw, _T_3242 node _T_3243 = bits(_WIRE_241, 15, 15) connect _WIRE_240.gf, _T_3243 node _T_3244 = bits(_WIRE_241, 16, 16) connect _WIRE_240.pf, _T_3244 node _T_3245 = bits(_WIRE_241, 17, 17) connect _WIRE_240.ae_stage2, _T_3245 node _T_3246 = bits(_WIRE_241, 18, 18) connect _WIRE_240.ae_final, _T_3246 node _T_3247 = bits(_WIRE_241, 19, 19) connect _WIRE_240.ae_ptw, _T_3247 node _T_3248 = bits(_WIRE_241, 20, 20) connect _WIRE_240.g, _T_3248 node _T_3249 = bits(_WIRE_241, 21, 21) connect _WIRE_240.u, _T_3249 node _T_3250 = bits(_WIRE_241, 41, 22) connect _WIRE_240.ppn, _T_3250 wire _WIRE_242 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_243 : UInt<42> connect _WIRE_243, sectored_entries[0][7].data[1] node _T_3251 = bits(_WIRE_243, 0, 0) connect _WIRE_242.fragmented_superpage, _T_3251 node _T_3252 = bits(_WIRE_243, 1, 1) connect _WIRE_242.c, _T_3252 node _T_3253 = bits(_WIRE_243, 2, 2) connect _WIRE_242.eff, _T_3253 node _T_3254 = bits(_WIRE_243, 3, 3) connect _WIRE_242.paa, _T_3254 node _T_3255 = bits(_WIRE_243, 4, 4) connect _WIRE_242.pal, _T_3255 node _T_3256 = bits(_WIRE_243, 5, 5) connect _WIRE_242.ppp, _T_3256 node _T_3257 = bits(_WIRE_243, 6, 6) connect _WIRE_242.pr, _T_3257 node _T_3258 = bits(_WIRE_243, 7, 7) connect _WIRE_242.px, _T_3258 node _T_3259 = bits(_WIRE_243, 8, 8) connect _WIRE_242.pw, _T_3259 node _T_3260 = bits(_WIRE_243, 9, 9) connect _WIRE_242.hr, _T_3260 node _T_3261 = bits(_WIRE_243, 10, 10) connect _WIRE_242.hx, _T_3261 node _T_3262 = bits(_WIRE_243, 11, 11) connect _WIRE_242.hw, _T_3262 node _T_3263 = bits(_WIRE_243, 12, 12) connect _WIRE_242.sr, _T_3263 node _T_3264 = bits(_WIRE_243, 13, 13) connect _WIRE_242.sx, _T_3264 node _T_3265 = bits(_WIRE_243, 14, 14) connect _WIRE_242.sw, _T_3265 node _T_3266 = bits(_WIRE_243, 15, 15) connect _WIRE_242.gf, _T_3266 node _T_3267 = bits(_WIRE_243, 16, 16) connect _WIRE_242.pf, _T_3267 node _T_3268 = bits(_WIRE_243, 17, 17) connect _WIRE_242.ae_stage2, _T_3268 node _T_3269 = bits(_WIRE_243, 18, 18) connect _WIRE_242.ae_final, _T_3269 node _T_3270 = bits(_WIRE_243, 19, 19) connect _WIRE_242.ae_ptw, _T_3270 node _T_3271 = bits(_WIRE_243, 20, 20) connect _WIRE_242.g, _T_3271 node _T_3272 = bits(_WIRE_243, 21, 21) connect _WIRE_242.u, _T_3272 node _T_3273 = bits(_WIRE_243, 41, 22) connect _WIRE_242.ppn, _T_3273 wire _WIRE_244 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_245 : UInt<42> connect _WIRE_245, sectored_entries[0][7].data[2] node _T_3274 = bits(_WIRE_245, 0, 0) connect _WIRE_244.fragmented_superpage, _T_3274 node _T_3275 = bits(_WIRE_245, 1, 1) connect _WIRE_244.c, _T_3275 node _T_3276 = bits(_WIRE_245, 2, 2) connect _WIRE_244.eff, _T_3276 node _T_3277 = bits(_WIRE_245, 3, 3) connect _WIRE_244.paa, _T_3277 node _T_3278 = bits(_WIRE_245, 4, 4) connect _WIRE_244.pal, _T_3278 node _T_3279 = bits(_WIRE_245, 5, 5) connect _WIRE_244.ppp, _T_3279 node _T_3280 = bits(_WIRE_245, 6, 6) connect _WIRE_244.pr, _T_3280 node _T_3281 = bits(_WIRE_245, 7, 7) connect _WIRE_244.px, _T_3281 node _T_3282 = bits(_WIRE_245, 8, 8) connect _WIRE_244.pw, _T_3282 node _T_3283 = bits(_WIRE_245, 9, 9) connect _WIRE_244.hr, _T_3283 node _T_3284 = bits(_WIRE_245, 10, 10) connect _WIRE_244.hx, _T_3284 node _T_3285 = bits(_WIRE_245, 11, 11) connect _WIRE_244.hw, _T_3285 node _T_3286 = bits(_WIRE_245, 12, 12) connect _WIRE_244.sr, _T_3286 node _T_3287 = bits(_WIRE_245, 13, 13) connect _WIRE_244.sx, _T_3287 node _T_3288 = bits(_WIRE_245, 14, 14) connect _WIRE_244.sw, _T_3288 node _T_3289 = bits(_WIRE_245, 15, 15) connect _WIRE_244.gf, _T_3289 node _T_3290 = bits(_WIRE_245, 16, 16) connect _WIRE_244.pf, _T_3290 node _T_3291 = bits(_WIRE_245, 17, 17) connect _WIRE_244.ae_stage2, _T_3291 node _T_3292 = bits(_WIRE_245, 18, 18) connect _WIRE_244.ae_final, _T_3292 node _T_3293 = bits(_WIRE_245, 19, 19) connect _WIRE_244.ae_ptw, _T_3293 node _T_3294 = bits(_WIRE_245, 20, 20) connect _WIRE_244.g, _T_3294 node _T_3295 = bits(_WIRE_245, 21, 21) connect _WIRE_244.u, _T_3295 node _T_3296 = bits(_WIRE_245, 41, 22) connect _WIRE_244.ppn, _T_3296 wire _WIRE_246 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_247 : UInt<42> connect _WIRE_247, sectored_entries[0][7].data[3] node _T_3297 = bits(_WIRE_247, 0, 0) connect _WIRE_246.fragmented_superpage, _T_3297 node _T_3298 = bits(_WIRE_247, 1, 1) connect _WIRE_246.c, _T_3298 node _T_3299 = bits(_WIRE_247, 2, 2) connect _WIRE_246.eff, _T_3299 node _T_3300 = bits(_WIRE_247, 3, 3) connect _WIRE_246.paa, _T_3300 node _T_3301 = bits(_WIRE_247, 4, 4) connect _WIRE_246.pal, _T_3301 node _T_3302 = bits(_WIRE_247, 5, 5) connect _WIRE_246.ppp, _T_3302 node _T_3303 = bits(_WIRE_247, 6, 6) connect _WIRE_246.pr, _T_3303 node _T_3304 = bits(_WIRE_247, 7, 7) connect _WIRE_246.px, _T_3304 node _T_3305 = bits(_WIRE_247, 8, 8) connect _WIRE_246.pw, _T_3305 node _T_3306 = bits(_WIRE_247, 9, 9) connect _WIRE_246.hr, _T_3306 node _T_3307 = bits(_WIRE_247, 10, 10) connect _WIRE_246.hx, _T_3307 node _T_3308 = bits(_WIRE_247, 11, 11) connect _WIRE_246.hw, _T_3308 node _T_3309 = bits(_WIRE_247, 12, 12) connect _WIRE_246.sr, _T_3309 node _T_3310 = bits(_WIRE_247, 13, 13) connect _WIRE_246.sx, _T_3310 node _T_3311 = bits(_WIRE_247, 14, 14) connect _WIRE_246.sw, _T_3311 node _T_3312 = bits(_WIRE_247, 15, 15) connect _WIRE_246.gf, _T_3312 node _T_3313 = bits(_WIRE_247, 16, 16) connect _WIRE_246.pf, _T_3313 node _T_3314 = bits(_WIRE_247, 17, 17) connect _WIRE_246.ae_stage2, _T_3314 node _T_3315 = bits(_WIRE_247, 18, 18) connect _WIRE_246.ae_final, _T_3315 node _T_3316 = bits(_WIRE_247, 19, 19) connect _WIRE_246.ae_ptw, _T_3316 node _T_3317 = bits(_WIRE_247, 20, 20) connect _WIRE_246.g, _T_3317 node _T_3318 = bits(_WIRE_247, 21, 21) connect _WIRE_246.u, _T_3318 node _T_3319 = bits(_WIRE_247, 41, 22) connect _WIRE_246.ppn, _T_3319 node _T_3320 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3321 = eq(_WIRE_240.g, UInt<1>(0h0)) node _T_3322 = and(_T_3320, _T_3321) when _T_3322 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3323 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3324 = eq(_WIRE_242.g, UInt<1>(0h0)) node _T_3325 = and(_T_3323, _T_3324) when _T_3325 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3326 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3327 = eq(_WIRE_244.g, UInt<1>(0h0)) node _T_3328 = and(_T_3326, _T_3327) when _T_3328 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3329 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3330 = eq(_WIRE_246.g, UInt<1>(0h0)) node _T_3331 = and(_T_3329, _T_3330) when _T_3331 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3332 = or(hv_7, hg_7) wire _WIRE_248 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_249 : UInt<42> connect _WIRE_249, sectored_entries[0][7].data[0] node _T_3333 = bits(_WIRE_249, 0, 0) connect _WIRE_248.fragmented_superpage, _T_3333 node _T_3334 = bits(_WIRE_249, 1, 1) connect _WIRE_248.c, _T_3334 node _T_3335 = bits(_WIRE_249, 2, 2) connect _WIRE_248.eff, _T_3335 node _T_3336 = bits(_WIRE_249, 3, 3) connect _WIRE_248.paa, _T_3336 node _T_3337 = bits(_WIRE_249, 4, 4) connect _WIRE_248.pal, _T_3337 node _T_3338 = bits(_WIRE_249, 5, 5) connect _WIRE_248.ppp, _T_3338 node _T_3339 = bits(_WIRE_249, 6, 6) connect _WIRE_248.pr, _T_3339 node _T_3340 = bits(_WIRE_249, 7, 7) connect _WIRE_248.px, _T_3340 node _T_3341 = bits(_WIRE_249, 8, 8) connect _WIRE_248.pw, _T_3341 node _T_3342 = bits(_WIRE_249, 9, 9) connect _WIRE_248.hr, _T_3342 node _T_3343 = bits(_WIRE_249, 10, 10) connect _WIRE_248.hx, _T_3343 node _T_3344 = bits(_WIRE_249, 11, 11) connect _WIRE_248.hw, _T_3344 node _T_3345 = bits(_WIRE_249, 12, 12) connect _WIRE_248.sr, _T_3345 node _T_3346 = bits(_WIRE_249, 13, 13) connect _WIRE_248.sx, _T_3346 node _T_3347 = bits(_WIRE_249, 14, 14) connect _WIRE_248.sw, _T_3347 node _T_3348 = bits(_WIRE_249, 15, 15) connect _WIRE_248.gf, _T_3348 node _T_3349 = bits(_WIRE_249, 16, 16) connect _WIRE_248.pf, _T_3349 node _T_3350 = bits(_WIRE_249, 17, 17) connect _WIRE_248.ae_stage2, _T_3350 node _T_3351 = bits(_WIRE_249, 18, 18) connect _WIRE_248.ae_final, _T_3351 node _T_3352 = bits(_WIRE_249, 19, 19) connect _WIRE_248.ae_ptw, _T_3352 node _T_3353 = bits(_WIRE_249, 20, 20) connect _WIRE_248.g, _T_3353 node _T_3354 = bits(_WIRE_249, 21, 21) connect _WIRE_248.u, _T_3354 node _T_3355 = bits(_WIRE_249, 41, 22) connect _WIRE_248.ppn, _T_3355 wire _WIRE_250 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_251 : UInt<42> connect _WIRE_251, sectored_entries[0][7].data[1] node _T_3356 = bits(_WIRE_251, 0, 0) connect _WIRE_250.fragmented_superpage, _T_3356 node _T_3357 = bits(_WIRE_251, 1, 1) connect _WIRE_250.c, _T_3357 node _T_3358 = bits(_WIRE_251, 2, 2) connect _WIRE_250.eff, _T_3358 node _T_3359 = bits(_WIRE_251, 3, 3) connect _WIRE_250.paa, _T_3359 node _T_3360 = bits(_WIRE_251, 4, 4) connect _WIRE_250.pal, _T_3360 node _T_3361 = bits(_WIRE_251, 5, 5) connect _WIRE_250.ppp, _T_3361 node _T_3362 = bits(_WIRE_251, 6, 6) connect _WIRE_250.pr, _T_3362 node _T_3363 = bits(_WIRE_251, 7, 7) connect _WIRE_250.px, _T_3363 node _T_3364 = bits(_WIRE_251, 8, 8) connect _WIRE_250.pw, _T_3364 node _T_3365 = bits(_WIRE_251, 9, 9) connect _WIRE_250.hr, _T_3365 node _T_3366 = bits(_WIRE_251, 10, 10) connect _WIRE_250.hx, _T_3366 node _T_3367 = bits(_WIRE_251, 11, 11) connect _WIRE_250.hw, _T_3367 node _T_3368 = bits(_WIRE_251, 12, 12) connect _WIRE_250.sr, _T_3368 node _T_3369 = bits(_WIRE_251, 13, 13) connect _WIRE_250.sx, _T_3369 node _T_3370 = bits(_WIRE_251, 14, 14) connect _WIRE_250.sw, _T_3370 node _T_3371 = bits(_WIRE_251, 15, 15) connect _WIRE_250.gf, _T_3371 node _T_3372 = bits(_WIRE_251, 16, 16) connect _WIRE_250.pf, _T_3372 node _T_3373 = bits(_WIRE_251, 17, 17) connect _WIRE_250.ae_stage2, _T_3373 node _T_3374 = bits(_WIRE_251, 18, 18) connect _WIRE_250.ae_final, _T_3374 node _T_3375 = bits(_WIRE_251, 19, 19) connect _WIRE_250.ae_ptw, _T_3375 node _T_3376 = bits(_WIRE_251, 20, 20) connect _WIRE_250.g, _T_3376 node _T_3377 = bits(_WIRE_251, 21, 21) connect _WIRE_250.u, _T_3377 node _T_3378 = bits(_WIRE_251, 41, 22) connect _WIRE_250.ppn, _T_3378 wire _WIRE_252 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_253 : UInt<42> connect _WIRE_253, sectored_entries[0][7].data[2] node _T_3379 = bits(_WIRE_253, 0, 0) connect _WIRE_252.fragmented_superpage, _T_3379 node _T_3380 = bits(_WIRE_253, 1, 1) connect _WIRE_252.c, _T_3380 node _T_3381 = bits(_WIRE_253, 2, 2) connect _WIRE_252.eff, _T_3381 node _T_3382 = bits(_WIRE_253, 3, 3) connect _WIRE_252.paa, _T_3382 node _T_3383 = bits(_WIRE_253, 4, 4) connect _WIRE_252.pal, _T_3383 node _T_3384 = bits(_WIRE_253, 5, 5) connect _WIRE_252.ppp, _T_3384 node _T_3385 = bits(_WIRE_253, 6, 6) connect _WIRE_252.pr, _T_3385 node _T_3386 = bits(_WIRE_253, 7, 7) connect _WIRE_252.px, _T_3386 node _T_3387 = bits(_WIRE_253, 8, 8) connect _WIRE_252.pw, _T_3387 node _T_3388 = bits(_WIRE_253, 9, 9) connect _WIRE_252.hr, _T_3388 node _T_3389 = bits(_WIRE_253, 10, 10) connect _WIRE_252.hx, _T_3389 node _T_3390 = bits(_WIRE_253, 11, 11) connect _WIRE_252.hw, _T_3390 node _T_3391 = bits(_WIRE_253, 12, 12) connect _WIRE_252.sr, _T_3391 node _T_3392 = bits(_WIRE_253, 13, 13) connect _WIRE_252.sx, _T_3392 node _T_3393 = bits(_WIRE_253, 14, 14) connect _WIRE_252.sw, _T_3393 node _T_3394 = bits(_WIRE_253, 15, 15) connect _WIRE_252.gf, _T_3394 node _T_3395 = bits(_WIRE_253, 16, 16) connect _WIRE_252.pf, _T_3395 node _T_3396 = bits(_WIRE_253, 17, 17) connect _WIRE_252.ae_stage2, _T_3396 node _T_3397 = bits(_WIRE_253, 18, 18) connect _WIRE_252.ae_final, _T_3397 node _T_3398 = bits(_WIRE_253, 19, 19) connect _WIRE_252.ae_ptw, _T_3398 node _T_3399 = bits(_WIRE_253, 20, 20) connect _WIRE_252.g, _T_3399 node _T_3400 = bits(_WIRE_253, 21, 21) connect _WIRE_252.u, _T_3400 node _T_3401 = bits(_WIRE_253, 41, 22) connect _WIRE_252.ppn, _T_3401 wire _WIRE_254 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_255 : UInt<42> connect _WIRE_255, sectored_entries[0][7].data[3] node _T_3402 = bits(_WIRE_255, 0, 0) connect _WIRE_254.fragmented_superpage, _T_3402 node _T_3403 = bits(_WIRE_255, 1, 1) connect _WIRE_254.c, _T_3403 node _T_3404 = bits(_WIRE_255, 2, 2) connect _WIRE_254.eff, _T_3404 node _T_3405 = bits(_WIRE_255, 3, 3) connect _WIRE_254.paa, _T_3405 node _T_3406 = bits(_WIRE_255, 4, 4) connect _WIRE_254.pal, _T_3406 node _T_3407 = bits(_WIRE_255, 5, 5) connect _WIRE_254.ppp, _T_3407 node _T_3408 = bits(_WIRE_255, 6, 6) connect _WIRE_254.pr, _T_3408 node _T_3409 = bits(_WIRE_255, 7, 7) connect _WIRE_254.px, _T_3409 node _T_3410 = bits(_WIRE_255, 8, 8) connect _WIRE_254.pw, _T_3410 node _T_3411 = bits(_WIRE_255, 9, 9) connect _WIRE_254.hr, _T_3411 node _T_3412 = bits(_WIRE_255, 10, 10) connect _WIRE_254.hx, _T_3412 node _T_3413 = bits(_WIRE_255, 11, 11) connect _WIRE_254.hw, _T_3413 node _T_3414 = bits(_WIRE_255, 12, 12) connect _WIRE_254.sr, _T_3414 node _T_3415 = bits(_WIRE_255, 13, 13) connect _WIRE_254.sx, _T_3415 node _T_3416 = bits(_WIRE_255, 14, 14) connect _WIRE_254.sw, _T_3416 node _T_3417 = bits(_WIRE_255, 15, 15) connect _WIRE_254.gf, _T_3417 node _T_3418 = bits(_WIRE_255, 16, 16) connect _WIRE_254.pf, _T_3418 node _T_3419 = bits(_WIRE_255, 17, 17) connect _WIRE_254.ae_stage2, _T_3419 node _T_3420 = bits(_WIRE_255, 18, 18) connect _WIRE_254.ae_final, _T_3420 node _T_3421 = bits(_WIRE_255, 19, 19) connect _WIRE_254.ae_ptw, _T_3421 node _T_3422 = bits(_WIRE_255, 20, 20) connect _WIRE_254.g, _T_3422 node _T_3423 = bits(_WIRE_255, 21, 21) connect _WIRE_254.u, _T_3423 node _T_3424 = bits(_WIRE_255, 41, 22) connect _WIRE_254.ppn, _T_3424 node _T_3425 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3425 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3426 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3426 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3427 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3427 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3428 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3428 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3429 = eq(hg_8, UInt<1>(0h0)) node _T_3430 = and(_T_3429, io.sfence.bits.rs1) when _T_3430 : node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_8) node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T) node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_3431 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3432 = bits(_T_3431, 26, 18) node _T_3433 = eq(_T_3432, UInt<1>(0h0)) node _T_3434 = or(ignore, _T_3433) node _T_3435 = and(tagMatch, _T_3434) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_3436 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3437 = bits(_T_3436, 17, 9) node _T_3438 = eq(_T_3437, UInt<1>(0h0)) node _T_3439 = or(ignore_1, _T_3438) node _T_3440 = and(_T_3435, _T_3439) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_3441 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3442 = bits(_T_3441, 8, 0) node _T_3443 = eq(_T_3442, UInt<1>(0h0)) node _T_3444 = or(ignore_2, _T_3443) node _T_3445 = and(_T_3440, _T_3444) when _T_3445 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_3446 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3447 = shr(_T_3446, 18) node _T_3448 = eq(_T_3447, UInt<1>(0h0)) when _T_3448 : wire _WIRE_256 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_257 : UInt<42> connect _WIRE_257, superpage_entries[0].data[0] node _T_3449 = bits(_WIRE_257, 0, 0) connect _WIRE_256.fragmented_superpage, _T_3449 node _T_3450 = bits(_WIRE_257, 1, 1) connect _WIRE_256.c, _T_3450 node _T_3451 = bits(_WIRE_257, 2, 2) connect _WIRE_256.eff, _T_3451 node _T_3452 = bits(_WIRE_257, 3, 3) connect _WIRE_256.paa, _T_3452 node _T_3453 = bits(_WIRE_257, 4, 4) connect _WIRE_256.pal, _T_3453 node _T_3454 = bits(_WIRE_257, 5, 5) connect _WIRE_256.ppp, _T_3454 node _T_3455 = bits(_WIRE_257, 6, 6) connect _WIRE_256.pr, _T_3455 node _T_3456 = bits(_WIRE_257, 7, 7) connect _WIRE_256.px, _T_3456 node _T_3457 = bits(_WIRE_257, 8, 8) connect _WIRE_256.pw, _T_3457 node _T_3458 = bits(_WIRE_257, 9, 9) connect _WIRE_256.hr, _T_3458 node _T_3459 = bits(_WIRE_257, 10, 10) connect _WIRE_256.hx, _T_3459 node _T_3460 = bits(_WIRE_257, 11, 11) connect _WIRE_256.hw, _T_3460 node _T_3461 = bits(_WIRE_257, 12, 12) connect _WIRE_256.sr, _T_3461 node _T_3462 = bits(_WIRE_257, 13, 13) connect _WIRE_256.sx, _T_3462 node _T_3463 = bits(_WIRE_257, 14, 14) connect _WIRE_256.sw, _T_3463 node _T_3464 = bits(_WIRE_257, 15, 15) connect _WIRE_256.gf, _T_3464 node _T_3465 = bits(_WIRE_257, 16, 16) connect _WIRE_256.pf, _T_3465 node _T_3466 = bits(_WIRE_257, 17, 17) connect _WIRE_256.ae_stage2, _T_3466 node _T_3467 = bits(_WIRE_257, 18, 18) connect _WIRE_256.ae_final, _T_3467 node _T_3468 = bits(_WIRE_257, 19, 19) connect _WIRE_256.ae_ptw, _T_3468 node _T_3469 = bits(_WIRE_257, 20, 20) connect _WIRE_256.g, _T_3469 node _T_3470 = bits(_WIRE_257, 21, 21) connect _WIRE_256.u, _T_3470 node _T_3471 = bits(_WIRE_257, 41, 22) connect _WIRE_256.ppn, _T_3471 node _T_3472 = eq(superpage_entries[0].tag_v, hv_8) node _T_3473 = and(_T_3472, _WIRE_256.fragmented_superpage) when _T_3473 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3474 = eq(hg_8, UInt<1>(0h0)) node _T_3475 = and(_T_3474, io.sfence.bits.rs2) when _T_3475 : wire _WIRE_258 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_259 : UInt<42> connect _WIRE_259, superpage_entries[0].data[0] node _T_3476 = bits(_WIRE_259, 0, 0) connect _WIRE_258.fragmented_superpage, _T_3476 node _T_3477 = bits(_WIRE_259, 1, 1) connect _WIRE_258.c, _T_3477 node _T_3478 = bits(_WIRE_259, 2, 2) connect _WIRE_258.eff, _T_3478 node _T_3479 = bits(_WIRE_259, 3, 3) connect _WIRE_258.paa, _T_3479 node _T_3480 = bits(_WIRE_259, 4, 4) connect _WIRE_258.pal, _T_3480 node _T_3481 = bits(_WIRE_259, 5, 5) connect _WIRE_258.ppp, _T_3481 node _T_3482 = bits(_WIRE_259, 6, 6) connect _WIRE_258.pr, _T_3482 node _T_3483 = bits(_WIRE_259, 7, 7) connect _WIRE_258.px, _T_3483 node _T_3484 = bits(_WIRE_259, 8, 8) connect _WIRE_258.pw, _T_3484 node _T_3485 = bits(_WIRE_259, 9, 9) connect _WIRE_258.hr, _T_3485 node _T_3486 = bits(_WIRE_259, 10, 10) connect _WIRE_258.hx, _T_3486 node _T_3487 = bits(_WIRE_259, 11, 11) connect _WIRE_258.hw, _T_3487 node _T_3488 = bits(_WIRE_259, 12, 12) connect _WIRE_258.sr, _T_3488 node _T_3489 = bits(_WIRE_259, 13, 13) connect _WIRE_258.sx, _T_3489 node _T_3490 = bits(_WIRE_259, 14, 14) connect _WIRE_258.sw, _T_3490 node _T_3491 = bits(_WIRE_259, 15, 15) connect _WIRE_258.gf, _T_3491 node _T_3492 = bits(_WIRE_259, 16, 16) connect _WIRE_258.pf, _T_3492 node _T_3493 = bits(_WIRE_259, 17, 17) connect _WIRE_258.ae_stage2, _T_3493 node _T_3494 = bits(_WIRE_259, 18, 18) connect _WIRE_258.ae_final, _T_3494 node _T_3495 = bits(_WIRE_259, 19, 19) connect _WIRE_258.ae_ptw, _T_3495 node _T_3496 = bits(_WIRE_259, 20, 20) connect _WIRE_258.g, _T_3496 node _T_3497 = bits(_WIRE_259, 21, 21) connect _WIRE_258.u, _T_3497 node _T_3498 = bits(_WIRE_259, 41, 22) connect _WIRE_258.ppn, _T_3498 node _T_3499 = eq(superpage_entries[0].tag_v, hv_8) node _T_3500 = eq(_WIRE_258.g, UInt<1>(0h0)) node _T_3501 = and(_T_3499, _T_3500) when _T_3501 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3502 = or(hv_8, hg_8) wire _WIRE_260 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_261 : UInt<42> connect _WIRE_261, superpage_entries[0].data[0] node _T_3503 = bits(_WIRE_261, 0, 0) connect _WIRE_260.fragmented_superpage, _T_3503 node _T_3504 = bits(_WIRE_261, 1, 1) connect _WIRE_260.c, _T_3504 node _T_3505 = bits(_WIRE_261, 2, 2) connect _WIRE_260.eff, _T_3505 node _T_3506 = bits(_WIRE_261, 3, 3) connect _WIRE_260.paa, _T_3506 node _T_3507 = bits(_WIRE_261, 4, 4) connect _WIRE_260.pal, _T_3507 node _T_3508 = bits(_WIRE_261, 5, 5) connect _WIRE_260.ppp, _T_3508 node _T_3509 = bits(_WIRE_261, 6, 6) connect _WIRE_260.pr, _T_3509 node _T_3510 = bits(_WIRE_261, 7, 7) connect _WIRE_260.px, _T_3510 node _T_3511 = bits(_WIRE_261, 8, 8) connect _WIRE_260.pw, _T_3511 node _T_3512 = bits(_WIRE_261, 9, 9) connect _WIRE_260.hr, _T_3512 node _T_3513 = bits(_WIRE_261, 10, 10) connect _WIRE_260.hx, _T_3513 node _T_3514 = bits(_WIRE_261, 11, 11) connect _WIRE_260.hw, _T_3514 node _T_3515 = bits(_WIRE_261, 12, 12) connect _WIRE_260.sr, _T_3515 node _T_3516 = bits(_WIRE_261, 13, 13) connect _WIRE_260.sx, _T_3516 node _T_3517 = bits(_WIRE_261, 14, 14) connect _WIRE_260.sw, _T_3517 node _T_3518 = bits(_WIRE_261, 15, 15) connect _WIRE_260.gf, _T_3518 node _T_3519 = bits(_WIRE_261, 16, 16) connect _WIRE_260.pf, _T_3519 node _T_3520 = bits(_WIRE_261, 17, 17) connect _WIRE_260.ae_stage2, _T_3520 node _T_3521 = bits(_WIRE_261, 18, 18) connect _WIRE_260.ae_final, _T_3521 node _T_3522 = bits(_WIRE_261, 19, 19) connect _WIRE_260.ae_ptw, _T_3522 node _T_3523 = bits(_WIRE_261, 20, 20) connect _WIRE_260.g, _T_3523 node _T_3524 = bits(_WIRE_261, 21, 21) connect _WIRE_260.u, _T_3524 node _T_3525 = bits(_WIRE_261, 41, 22) connect _WIRE_260.ppn, _T_3525 node _T_3526 = eq(superpage_entries[0].tag_v, _T_3502) when _T_3526 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3527 = eq(hg_9, UInt<1>(0h0)) node _T_3528 = and(_T_3527, io.sfence.bits.rs1) when _T_3528 : node _tagMatch_T_1 = eq(superpage_entries[1].tag_v, hv_9) node tagMatch_1 = and(superpage_entries[1].valid[0], _tagMatch_T_1) node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_3529 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3530 = bits(_T_3529, 26, 18) node _T_3531 = eq(_T_3530, UInt<1>(0h0)) node _T_3532 = or(ignore_3, _T_3531) node _T_3533 = and(tagMatch_1, _T_3532) node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_3534 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3535 = bits(_T_3534, 17, 9) node _T_3536 = eq(_T_3535, UInt<1>(0h0)) node _T_3537 = or(ignore_4, _T_3536) node _T_3538 = and(_T_3533, _T_3537) node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h1)) node _T_3539 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3540 = bits(_T_3539, 8, 0) node _T_3541 = eq(_T_3540, UInt<1>(0h0)) node _T_3542 = or(ignore_5, _T_3541) node _T_3543 = and(_T_3538, _T_3542) when _T_3543 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_3544 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3545 = shr(_T_3544, 18) node _T_3546 = eq(_T_3545, UInt<1>(0h0)) when _T_3546 : wire _WIRE_262 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_263 : UInt<42> connect _WIRE_263, superpage_entries[1].data[0] node _T_3547 = bits(_WIRE_263, 0, 0) connect _WIRE_262.fragmented_superpage, _T_3547 node _T_3548 = bits(_WIRE_263, 1, 1) connect _WIRE_262.c, _T_3548 node _T_3549 = bits(_WIRE_263, 2, 2) connect _WIRE_262.eff, _T_3549 node _T_3550 = bits(_WIRE_263, 3, 3) connect _WIRE_262.paa, _T_3550 node _T_3551 = bits(_WIRE_263, 4, 4) connect _WIRE_262.pal, _T_3551 node _T_3552 = bits(_WIRE_263, 5, 5) connect _WIRE_262.ppp, _T_3552 node _T_3553 = bits(_WIRE_263, 6, 6) connect _WIRE_262.pr, _T_3553 node _T_3554 = bits(_WIRE_263, 7, 7) connect _WIRE_262.px, _T_3554 node _T_3555 = bits(_WIRE_263, 8, 8) connect _WIRE_262.pw, _T_3555 node _T_3556 = bits(_WIRE_263, 9, 9) connect _WIRE_262.hr, _T_3556 node _T_3557 = bits(_WIRE_263, 10, 10) connect _WIRE_262.hx, _T_3557 node _T_3558 = bits(_WIRE_263, 11, 11) connect _WIRE_262.hw, _T_3558 node _T_3559 = bits(_WIRE_263, 12, 12) connect _WIRE_262.sr, _T_3559 node _T_3560 = bits(_WIRE_263, 13, 13) connect _WIRE_262.sx, _T_3560 node _T_3561 = bits(_WIRE_263, 14, 14) connect _WIRE_262.sw, _T_3561 node _T_3562 = bits(_WIRE_263, 15, 15) connect _WIRE_262.gf, _T_3562 node _T_3563 = bits(_WIRE_263, 16, 16) connect _WIRE_262.pf, _T_3563 node _T_3564 = bits(_WIRE_263, 17, 17) connect _WIRE_262.ae_stage2, _T_3564 node _T_3565 = bits(_WIRE_263, 18, 18) connect _WIRE_262.ae_final, _T_3565 node _T_3566 = bits(_WIRE_263, 19, 19) connect _WIRE_262.ae_ptw, _T_3566 node _T_3567 = bits(_WIRE_263, 20, 20) connect _WIRE_262.g, _T_3567 node _T_3568 = bits(_WIRE_263, 21, 21) connect _WIRE_262.u, _T_3568 node _T_3569 = bits(_WIRE_263, 41, 22) connect _WIRE_262.ppn, _T_3569 node _T_3570 = eq(superpage_entries[1].tag_v, hv_9) node _T_3571 = and(_T_3570, _WIRE_262.fragmented_superpage) when _T_3571 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3572 = eq(hg_9, UInt<1>(0h0)) node _T_3573 = and(_T_3572, io.sfence.bits.rs2) when _T_3573 : wire _WIRE_264 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_265 : UInt<42> connect _WIRE_265, superpage_entries[1].data[0] node _T_3574 = bits(_WIRE_265, 0, 0) connect _WIRE_264.fragmented_superpage, _T_3574 node _T_3575 = bits(_WIRE_265, 1, 1) connect _WIRE_264.c, _T_3575 node _T_3576 = bits(_WIRE_265, 2, 2) connect _WIRE_264.eff, _T_3576 node _T_3577 = bits(_WIRE_265, 3, 3) connect _WIRE_264.paa, _T_3577 node _T_3578 = bits(_WIRE_265, 4, 4) connect _WIRE_264.pal, _T_3578 node _T_3579 = bits(_WIRE_265, 5, 5) connect _WIRE_264.ppp, _T_3579 node _T_3580 = bits(_WIRE_265, 6, 6) connect _WIRE_264.pr, _T_3580 node _T_3581 = bits(_WIRE_265, 7, 7) connect _WIRE_264.px, _T_3581 node _T_3582 = bits(_WIRE_265, 8, 8) connect _WIRE_264.pw, _T_3582 node _T_3583 = bits(_WIRE_265, 9, 9) connect _WIRE_264.hr, _T_3583 node _T_3584 = bits(_WIRE_265, 10, 10) connect _WIRE_264.hx, _T_3584 node _T_3585 = bits(_WIRE_265, 11, 11) connect _WIRE_264.hw, _T_3585 node _T_3586 = bits(_WIRE_265, 12, 12) connect _WIRE_264.sr, _T_3586 node _T_3587 = bits(_WIRE_265, 13, 13) connect _WIRE_264.sx, _T_3587 node _T_3588 = bits(_WIRE_265, 14, 14) connect _WIRE_264.sw, _T_3588 node _T_3589 = bits(_WIRE_265, 15, 15) connect _WIRE_264.gf, _T_3589 node _T_3590 = bits(_WIRE_265, 16, 16) connect _WIRE_264.pf, _T_3590 node _T_3591 = bits(_WIRE_265, 17, 17) connect _WIRE_264.ae_stage2, _T_3591 node _T_3592 = bits(_WIRE_265, 18, 18) connect _WIRE_264.ae_final, _T_3592 node _T_3593 = bits(_WIRE_265, 19, 19) connect _WIRE_264.ae_ptw, _T_3593 node _T_3594 = bits(_WIRE_265, 20, 20) connect _WIRE_264.g, _T_3594 node _T_3595 = bits(_WIRE_265, 21, 21) connect _WIRE_264.u, _T_3595 node _T_3596 = bits(_WIRE_265, 41, 22) connect _WIRE_264.ppn, _T_3596 node _T_3597 = eq(superpage_entries[1].tag_v, hv_9) node _T_3598 = eq(_WIRE_264.g, UInt<1>(0h0)) node _T_3599 = and(_T_3597, _T_3598) when _T_3599 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3600 = or(hv_9, hg_9) wire _WIRE_266 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_267 : UInt<42> connect _WIRE_267, superpage_entries[1].data[0] node _T_3601 = bits(_WIRE_267, 0, 0) connect _WIRE_266.fragmented_superpage, _T_3601 node _T_3602 = bits(_WIRE_267, 1, 1) connect _WIRE_266.c, _T_3602 node _T_3603 = bits(_WIRE_267, 2, 2) connect _WIRE_266.eff, _T_3603 node _T_3604 = bits(_WIRE_267, 3, 3) connect _WIRE_266.paa, _T_3604 node _T_3605 = bits(_WIRE_267, 4, 4) connect _WIRE_266.pal, _T_3605 node _T_3606 = bits(_WIRE_267, 5, 5) connect _WIRE_266.ppp, _T_3606 node _T_3607 = bits(_WIRE_267, 6, 6) connect _WIRE_266.pr, _T_3607 node _T_3608 = bits(_WIRE_267, 7, 7) connect _WIRE_266.px, _T_3608 node _T_3609 = bits(_WIRE_267, 8, 8) connect _WIRE_266.pw, _T_3609 node _T_3610 = bits(_WIRE_267, 9, 9) connect _WIRE_266.hr, _T_3610 node _T_3611 = bits(_WIRE_267, 10, 10) connect _WIRE_266.hx, _T_3611 node _T_3612 = bits(_WIRE_267, 11, 11) connect _WIRE_266.hw, _T_3612 node _T_3613 = bits(_WIRE_267, 12, 12) connect _WIRE_266.sr, _T_3613 node _T_3614 = bits(_WIRE_267, 13, 13) connect _WIRE_266.sx, _T_3614 node _T_3615 = bits(_WIRE_267, 14, 14) connect _WIRE_266.sw, _T_3615 node _T_3616 = bits(_WIRE_267, 15, 15) connect _WIRE_266.gf, _T_3616 node _T_3617 = bits(_WIRE_267, 16, 16) connect _WIRE_266.pf, _T_3617 node _T_3618 = bits(_WIRE_267, 17, 17) connect _WIRE_266.ae_stage2, _T_3618 node _T_3619 = bits(_WIRE_267, 18, 18) connect _WIRE_266.ae_final, _T_3619 node _T_3620 = bits(_WIRE_267, 19, 19) connect _WIRE_266.ae_ptw, _T_3620 node _T_3621 = bits(_WIRE_267, 20, 20) connect _WIRE_266.g, _T_3621 node _T_3622 = bits(_WIRE_267, 21, 21) connect _WIRE_266.u, _T_3622 node _T_3623 = bits(_WIRE_267, 41, 22) connect _WIRE_266.ppn, _T_3623 node _T_3624 = eq(superpage_entries[1].tag_v, _T_3600) when _T_3624 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3625 = eq(hg_10, UInt<1>(0h0)) node _T_3626 = and(_T_3625, io.sfence.bits.rs1) when _T_3626 : node _tagMatch_T_2 = eq(superpage_entries[2].tag_v, hv_10) node tagMatch_2 = and(superpage_entries[2].valid[0], _tagMatch_T_2) node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node ignore_6 = or(_ignore_T_6, UInt<1>(0h0)) node _T_3627 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3628 = bits(_T_3627, 26, 18) node _T_3629 = eq(_T_3628, UInt<1>(0h0)) node _T_3630 = or(ignore_6, _T_3629) node _T_3631 = and(tagMatch_2, _T_3630) node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ignore_7 = or(_ignore_T_7, UInt<1>(0h0)) node _T_3632 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3633 = bits(_T_3632, 17, 9) node _T_3634 = eq(_T_3633, UInt<1>(0h0)) node _T_3635 = or(ignore_7, _T_3634) node _T_3636 = and(_T_3631, _T_3635) node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ignore_8 = or(_ignore_T_8, UInt<1>(0h1)) node _T_3637 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3638 = bits(_T_3637, 8, 0) node _T_3639 = eq(_T_3638, UInt<1>(0h0)) node _T_3640 = or(ignore_8, _T_3639) node _T_3641 = and(_T_3636, _T_3640) when _T_3641 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_3642 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3643 = shr(_T_3642, 18) node _T_3644 = eq(_T_3643, UInt<1>(0h0)) when _T_3644 : wire _WIRE_268 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_269 : UInt<42> connect _WIRE_269, superpage_entries[2].data[0] node _T_3645 = bits(_WIRE_269, 0, 0) connect _WIRE_268.fragmented_superpage, _T_3645 node _T_3646 = bits(_WIRE_269, 1, 1) connect _WIRE_268.c, _T_3646 node _T_3647 = bits(_WIRE_269, 2, 2) connect _WIRE_268.eff, _T_3647 node _T_3648 = bits(_WIRE_269, 3, 3) connect _WIRE_268.paa, _T_3648 node _T_3649 = bits(_WIRE_269, 4, 4) connect _WIRE_268.pal, _T_3649 node _T_3650 = bits(_WIRE_269, 5, 5) connect _WIRE_268.ppp, _T_3650 node _T_3651 = bits(_WIRE_269, 6, 6) connect _WIRE_268.pr, _T_3651 node _T_3652 = bits(_WIRE_269, 7, 7) connect _WIRE_268.px, _T_3652 node _T_3653 = bits(_WIRE_269, 8, 8) connect _WIRE_268.pw, _T_3653 node _T_3654 = bits(_WIRE_269, 9, 9) connect _WIRE_268.hr, _T_3654 node _T_3655 = bits(_WIRE_269, 10, 10) connect _WIRE_268.hx, _T_3655 node _T_3656 = bits(_WIRE_269, 11, 11) connect _WIRE_268.hw, _T_3656 node _T_3657 = bits(_WIRE_269, 12, 12) connect _WIRE_268.sr, _T_3657 node _T_3658 = bits(_WIRE_269, 13, 13) connect _WIRE_268.sx, _T_3658 node _T_3659 = bits(_WIRE_269, 14, 14) connect _WIRE_268.sw, _T_3659 node _T_3660 = bits(_WIRE_269, 15, 15) connect _WIRE_268.gf, _T_3660 node _T_3661 = bits(_WIRE_269, 16, 16) connect _WIRE_268.pf, _T_3661 node _T_3662 = bits(_WIRE_269, 17, 17) connect _WIRE_268.ae_stage2, _T_3662 node _T_3663 = bits(_WIRE_269, 18, 18) connect _WIRE_268.ae_final, _T_3663 node _T_3664 = bits(_WIRE_269, 19, 19) connect _WIRE_268.ae_ptw, _T_3664 node _T_3665 = bits(_WIRE_269, 20, 20) connect _WIRE_268.g, _T_3665 node _T_3666 = bits(_WIRE_269, 21, 21) connect _WIRE_268.u, _T_3666 node _T_3667 = bits(_WIRE_269, 41, 22) connect _WIRE_268.ppn, _T_3667 node _T_3668 = eq(superpage_entries[2].tag_v, hv_10) node _T_3669 = and(_T_3668, _WIRE_268.fragmented_superpage) when _T_3669 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3670 = eq(hg_10, UInt<1>(0h0)) node _T_3671 = and(_T_3670, io.sfence.bits.rs2) when _T_3671 : wire _WIRE_270 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_271 : UInt<42> connect _WIRE_271, superpage_entries[2].data[0] node _T_3672 = bits(_WIRE_271, 0, 0) connect _WIRE_270.fragmented_superpage, _T_3672 node _T_3673 = bits(_WIRE_271, 1, 1) connect _WIRE_270.c, _T_3673 node _T_3674 = bits(_WIRE_271, 2, 2) connect _WIRE_270.eff, _T_3674 node _T_3675 = bits(_WIRE_271, 3, 3) connect _WIRE_270.paa, _T_3675 node _T_3676 = bits(_WIRE_271, 4, 4) connect _WIRE_270.pal, _T_3676 node _T_3677 = bits(_WIRE_271, 5, 5) connect _WIRE_270.ppp, _T_3677 node _T_3678 = bits(_WIRE_271, 6, 6) connect _WIRE_270.pr, _T_3678 node _T_3679 = bits(_WIRE_271, 7, 7) connect _WIRE_270.px, _T_3679 node _T_3680 = bits(_WIRE_271, 8, 8) connect _WIRE_270.pw, _T_3680 node _T_3681 = bits(_WIRE_271, 9, 9) connect _WIRE_270.hr, _T_3681 node _T_3682 = bits(_WIRE_271, 10, 10) connect _WIRE_270.hx, _T_3682 node _T_3683 = bits(_WIRE_271, 11, 11) connect _WIRE_270.hw, _T_3683 node _T_3684 = bits(_WIRE_271, 12, 12) connect _WIRE_270.sr, _T_3684 node _T_3685 = bits(_WIRE_271, 13, 13) connect _WIRE_270.sx, _T_3685 node _T_3686 = bits(_WIRE_271, 14, 14) connect _WIRE_270.sw, _T_3686 node _T_3687 = bits(_WIRE_271, 15, 15) connect _WIRE_270.gf, _T_3687 node _T_3688 = bits(_WIRE_271, 16, 16) connect _WIRE_270.pf, _T_3688 node _T_3689 = bits(_WIRE_271, 17, 17) connect _WIRE_270.ae_stage2, _T_3689 node _T_3690 = bits(_WIRE_271, 18, 18) connect _WIRE_270.ae_final, _T_3690 node _T_3691 = bits(_WIRE_271, 19, 19) connect _WIRE_270.ae_ptw, _T_3691 node _T_3692 = bits(_WIRE_271, 20, 20) connect _WIRE_270.g, _T_3692 node _T_3693 = bits(_WIRE_271, 21, 21) connect _WIRE_270.u, _T_3693 node _T_3694 = bits(_WIRE_271, 41, 22) connect _WIRE_270.ppn, _T_3694 node _T_3695 = eq(superpage_entries[2].tag_v, hv_10) node _T_3696 = eq(_WIRE_270.g, UInt<1>(0h0)) node _T_3697 = and(_T_3695, _T_3696) when _T_3697 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3698 = or(hv_10, hg_10) wire _WIRE_272 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_273 : UInt<42> connect _WIRE_273, superpage_entries[2].data[0] node _T_3699 = bits(_WIRE_273, 0, 0) connect _WIRE_272.fragmented_superpage, _T_3699 node _T_3700 = bits(_WIRE_273, 1, 1) connect _WIRE_272.c, _T_3700 node _T_3701 = bits(_WIRE_273, 2, 2) connect _WIRE_272.eff, _T_3701 node _T_3702 = bits(_WIRE_273, 3, 3) connect _WIRE_272.paa, _T_3702 node _T_3703 = bits(_WIRE_273, 4, 4) connect _WIRE_272.pal, _T_3703 node _T_3704 = bits(_WIRE_273, 5, 5) connect _WIRE_272.ppp, _T_3704 node _T_3705 = bits(_WIRE_273, 6, 6) connect _WIRE_272.pr, _T_3705 node _T_3706 = bits(_WIRE_273, 7, 7) connect _WIRE_272.px, _T_3706 node _T_3707 = bits(_WIRE_273, 8, 8) connect _WIRE_272.pw, _T_3707 node _T_3708 = bits(_WIRE_273, 9, 9) connect _WIRE_272.hr, _T_3708 node _T_3709 = bits(_WIRE_273, 10, 10) connect _WIRE_272.hx, _T_3709 node _T_3710 = bits(_WIRE_273, 11, 11) connect _WIRE_272.hw, _T_3710 node _T_3711 = bits(_WIRE_273, 12, 12) connect _WIRE_272.sr, _T_3711 node _T_3712 = bits(_WIRE_273, 13, 13) connect _WIRE_272.sx, _T_3712 node _T_3713 = bits(_WIRE_273, 14, 14) connect _WIRE_272.sw, _T_3713 node _T_3714 = bits(_WIRE_273, 15, 15) connect _WIRE_272.gf, _T_3714 node _T_3715 = bits(_WIRE_273, 16, 16) connect _WIRE_272.pf, _T_3715 node _T_3716 = bits(_WIRE_273, 17, 17) connect _WIRE_272.ae_stage2, _T_3716 node _T_3717 = bits(_WIRE_273, 18, 18) connect _WIRE_272.ae_final, _T_3717 node _T_3718 = bits(_WIRE_273, 19, 19) connect _WIRE_272.ae_ptw, _T_3718 node _T_3719 = bits(_WIRE_273, 20, 20) connect _WIRE_272.g, _T_3719 node _T_3720 = bits(_WIRE_273, 21, 21) connect _WIRE_272.u, _T_3720 node _T_3721 = bits(_WIRE_273, 41, 22) connect _WIRE_272.ppn, _T_3721 node _T_3722 = eq(superpage_entries[2].tag_v, _T_3698) when _T_3722 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3723 = eq(hg_11, UInt<1>(0h0)) node _T_3724 = and(_T_3723, io.sfence.bits.rs1) when _T_3724 : node _tagMatch_T_3 = eq(superpage_entries[3].tag_v, hv_11) node tagMatch_3 = and(superpage_entries[3].valid[0], _tagMatch_T_3) node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node ignore_9 = or(_ignore_T_9, UInt<1>(0h0)) node _T_3725 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3726 = bits(_T_3725, 26, 18) node _T_3727 = eq(_T_3726, UInt<1>(0h0)) node _T_3728 = or(ignore_9, _T_3727) node _T_3729 = and(tagMatch_3, _T_3728) node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ignore_10 = or(_ignore_T_10, UInt<1>(0h0)) node _T_3730 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3731 = bits(_T_3730, 17, 9) node _T_3732 = eq(_T_3731, UInt<1>(0h0)) node _T_3733 = or(ignore_10, _T_3732) node _T_3734 = and(_T_3729, _T_3733) node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ignore_11 = or(_ignore_T_11, UInt<1>(0h1)) node _T_3735 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3736 = bits(_T_3735, 8, 0) node _T_3737 = eq(_T_3736, UInt<1>(0h0)) node _T_3738 = or(ignore_11, _T_3737) node _T_3739 = and(_T_3734, _T_3738) when _T_3739 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node _T_3740 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3741 = shr(_T_3740, 18) node _T_3742 = eq(_T_3741, UInt<1>(0h0)) when _T_3742 : wire _WIRE_274 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_275 : UInt<42> connect _WIRE_275, superpage_entries[3].data[0] node _T_3743 = bits(_WIRE_275, 0, 0) connect _WIRE_274.fragmented_superpage, _T_3743 node _T_3744 = bits(_WIRE_275, 1, 1) connect _WIRE_274.c, _T_3744 node _T_3745 = bits(_WIRE_275, 2, 2) connect _WIRE_274.eff, _T_3745 node _T_3746 = bits(_WIRE_275, 3, 3) connect _WIRE_274.paa, _T_3746 node _T_3747 = bits(_WIRE_275, 4, 4) connect _WIRE_274.pal, _T_3747 node _T_3748 = bits(_WIRE_275, 5, 5) connect _WIRE_274.ppp, _T_3748 node _T_3749 = bits(_WIRE_275, 6, 6) connect _WIRE_274.pr, _T_3749 node _T_3750 = bits(_WIRE_275, 7, 7) connect _WIRE_274.px, _T_3750 node _T_3751 = bits(_WIRE_275, 8, 8) connect _WIRE_274.pw, _T_3751 node _T_3752 = bits(_WIRE_275, 9, 9) connect _WIRE_274.hr, _T_3752 node _T_3753 = bits(_WIRE_275, 10, 10) connect _WIRE_274.hx, _T_3753 node _T_3754 = bits(_WIRE_275, 11, 11) connect _WIRE_274.hw, _T_3754 node _T_3755 = bits(_WIRE_275, 12, 12) connect _WIRE_274.sr, _T_3755 node _T_3756 = bits(_WIRE_275, 13, 13) connect _WIRE_274.sx, _T_3756 node _T_3757 = bits(_WIRE_275, 14, 14) connect _WIRE_274.sw, _T_3757 node _T_3758 = bits(_WIRE_275, 15, 15) connect _WIRE_274.gf, _T_3758 node _T_3759 = bits(_WIRE_275, 16, 16) connect _WIRE_274.pf, _T_3759 node _T_3760 = bits(_WIRE_275, 17, 17) connect _WIRE_274.ae_stage2, _T_3760 node _T_3761 = bits(_WIRE_275, 18, 18) connect _WIRE_274.ae_final, _T_3761 node _T_3762 = bits(_WIRE_275, 19, 19) connect _WIRE_274.ae_ptw, _T_3762 node _T_3763 = bits(_WIRE_275, 20, 20) connect _WIRE_274.g, _T_3763 node _T_3764 = bits(_WIRE_275, 21, 21) connect _WIRE_274.u, _T_3764 node _T_3765 = bits(_WIRE_275, 41, 22) connect _WIRE_274.ppn, _T_3765 node _T_3766 = eq(superpage_entries[3].tag_v, hv_11) node _T_3767 = and(_T_3766, _WIRE_274.fragmented_superpage) when _T_3767 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3768 = eq(hg_11, UInt<1>(0h0)) node _T_3769 = and(_T_3768, io.sfence.bits.rs2) when _T_3769 : wire _WIRE_276 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_277 : UInt<42> connect _WIRE_277, superpage_entries[3].data[0] node _T_3770 = bits(_WIRE_277, 0, 0) connect _WIRE_276.fragmented_superpage, _T_3770 node _T_3771 = bits(_WIRE_277, 1, 1) connect _WIRE_276.c, _T_3771 node _T_3772 = bits(_WIRE_277, 2, 2) connect _WIRE_276.eff, _T_3772 node _T_3773 = bits(_WIRE_277, 3, 3) connect _WIRE_276.paa, _T_3773 node _T_3774 = bits(_WIRE_277, 4, 4) connect _WIRE_276.pal, _T_3774 node _T_3775 = bits(_WIRE_277, 5, 5) connect _WIRE_276.ppp, _T_3775 node _T_3776 = bits(_WIRE_277, 6, 6) connect _WIRE_276.pr, _T_3776 node _T_3777 = bits(_WIRE_277, 7, 7) connect _WIRE_276.px, _T_3777 node _T_3778 = bits(_WIRE_277, 8, 8) connect _WIRE_276.pw, _T_3778 node _T_3779 = bits(_WIRE_277, 9, 9) connect _WIRE_276.hr, _T_3779 node _T_3780 = bits(_WIRE_277, 10, 10) connect _WIRE_276.hx, _T_3780 node _T_3781 = bits(_WIRE_277, 11, 11) connect _WIRE_276.hw, _T_3781 node _T_3782 = bits(_WIRE_277, 12, 12) connect _WIRE_276.sr, _T_3782 node _T_3783 = bits(_WIRE_277, 13, 13) connect _WIRE_276.sx, _T_3783 node _T_3784 = bits(_WIRE_277, 14, 14) connect _WIRE_276.sw, _T_3784 node _T_3785 = bits(_WIRE_277, 15, 15) connect _WIRE_276.gf, _T_3785 node _T_3786 = bits(_WIRE_277, 16, 16) connect _WIRE_276.pf, _T_3786 node _T_3787 = bits(_WIRE_277, 17, 17) connect _WIRE_276.ae_stage2, _T_3787 node _T_3788 = bits(_WIRE_277, 18, 18) connect _WIRE_276.ae_final, _T_3788 node _T_3789 = bits(_WIRE_277, 19, 19) connect _WIRE_276.ae_ptw, _T_3789 node _T_3790 = bits(_WIRE_277, 20, 20) connect _WIRE_276.g, _T_3790 node _T_3791 = bits(_WIRE_277, 21, 21) connect _WIRE_276.u, _T_3791 node _T_3792 = bits(_WIRE_277, 41, 22) connect _WIRE_276.ppn, _T_3792 node _T_3793 = eq(superpage_entries[3].tag_v, hv_11) node _T_3794 = eq(_WIRE_276.g, UInt<1>(0h0)) node _T_3795 = and(_T_3793, _T_3794) when _T_3795 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3796 = or(hv_11, hg_11) wire _WIRE_278 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_279 : UInt<42> connect _WIRE_279, superpage_entries[3].data[0] node _T_3797 = bits(_WIRE_279, 0, 0) connect _WIRE_278.fragmented_superpage, _T_3797 node _T_3798 = bits(_WIRE_279, 1, 1) connect _WIRE_278.c, _T_3798 node _T_3799 = bits(_WIRE_279, 2, 2) connect _WIRE_278.eff, _T_3799 node _T_3800 = bits(_WIRE_279, 3, 3) connect _WIRE_278.paa, _T_3800 node _T_3801 = bits(_WIRE_279, 4, 4) connect _WIRE_278.pal, _T_3801 node _T_3802 = bits(_WIRE_279, 5, 5) connect _WIRE_278.ppp, _T_3802 node _T_3803 = bits(_WIRE_279, 6, 6) connect _WIRE_278.pr, _T_3803 node _T_3804 = bits(_WIRE_279, 7, 7) connect _WIRE_278.px, _T_3804 node _T_3805 = bits(_WIRE_279, 8, 8) connect _WIRE_278.pw, _T_3805 node _T_3806 = bits(_WIRE_279, 9, 9) connect _WIRE_278.hr, _T_3806 node _T_3807 = bits(_WIRE_279, 10, 10) connect _WIRE_278.hx, _T_3807 node _T_3808 = bits(_WIRE_279, 11, 11) connect _WIRE_278.hw, _T_3808 node _T_3809 = bits(_WIRE_279, 12, 12) connect _WIRE_278.sr, _T_3809 node _T_3810 = bits(_WIRE_279, 13, 13) connect _WIRE_278.sx, _T_3810 node _T_3811 = bits(_WIRE_279, 14, 14) connect _WIRE_278.sw, _T_3811 node _T_3812 = bits(_WIRE_279, 15, 15) connect _WIRE_278.gf, _T_3812 node _T_3813 = bits(_WIRE_279, 16, 16) connect _WIRE_278.pf, _T_3813 node _T_3814 = bits(_WIRE_279, 17, 17) connect _WIRE_278.ae_stage2, _T_3814 node _T_3815 = bits(_WIRE_279, 18, 18) connect _WIRE_278.ae_final, _T_3815 node _T_3816 = bits(_WIRE_279, 19, 19) connect _WIRE_278.ae_ptw, _T_3816 node _T_3817 = bits(_WIRE_279, 20, 20) connect _WIRE_278.g, _T_3817 node _T_3818 = bits(_WIRE_279, 21, 21) connect _WIRE_278.u, _T_3818 node _T_3819 = bits(_WIRE_279, 41, 22) connect _WIRE_278.ppn, _T_3819 node _T_3820 = eq(superpage_entries[3].tag_v, _T_3796) when _T_3820 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3821 = eq(hg_12, UInt<1>(0h0)) node _T_3822 = and(_T_3821, io.sfence.bits.rs1) when _T_3822 : node _tagMatch_T_4 = eq(special_entry.tag_v, hv_12) node tagMatch_4 = and(special_entry.valid[0], _tagMatch_T_4) node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node ignore_12 = or(_ignore_T_12, UInt<1>(0h0)) node _T_3823 = xor(special_entry.tag_vpn, vpn) node _T_3824 = bits(_T_3823, 26, 18) node _T_3825 = eq(_T_3824, UInt<1>(0h0)) node _T_3826 = or(ignore_12, _T_3825) node _T_3827 = and(tagMatch_4, _T_3826) node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node ignore_13 = or(_ignore_T_13, UInt<1>(0h0)) node _T_3828 = xor(special_entry.tag_vpn, vpn) node _T_3829 = bits(_T_3828, 17, 9) node _T_3830 = eq(_T_3829, UInt<1>(0h0)) node _T_3831 = or(ignore_13, _T_3830) node _T_3832 = and(_T_3827, _T_3831) node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node ignore_14 = or(_ignore_T_14, UInt<1>(0h0)) node _T_3833 = xor(special_entry.tag_vpn, vpn) node _T_3834 = bits(_T_3833, 8, 0) node _T_3835 = eq(_T_3834, UInt<1>(0h0)) node _T_3836 = or(ignore_14, _T_3835) node _T_3837 = and(_T_3832, _T_3836) when _T_3837 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3838 = xor(special_entry.tag_vpn, vpn) node _T_3839 = shr(_T_3838, 18) node _T_3840 = eq(_T_3839, UInt<1>(0h0)) when _T_3840 : wire _WIRE_280 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_281 : UInt<42> connect _WIRE_281, special_entry.data[0] node _T_3841 = bits(_WIRE_281, 0, 0) connect _WIRE_280.fragmented_superpage, _T_3841 node _T_3842 = bits(_WIRE_281, 1, 1) connect _WIRE_280.c, _T_3842 node _T_3843 = bits(_WIRE_281, 2, 2) connect _WIRE_280.eff, _T_3843 node _T_3844 = bits(_WIRE_281, 3, 3) connect _WIRE_280.paa, _T_3844 node _T_3845 = bits(_WIRE_281, 4, 4) connect _WIRE_280.pal, _T_3845 node _T_3846 = bits(_WIRE_281, 5, 5) connect _WIRE_280.ppp, _T_3846 node _T_3847 = bits(_WIRE_281, 6, 6) connect _WIRE_280.pr, _T_3847 node _T_3848 = bits(_WIRE_281, 7, 7) connect _WIRE_280.px, _T_3848 node _T_3849 = bits(_WIRE_281, 8, 8) connect _WIRE_280.pw, _T_3849 node _T_3850 = bits(_WIRE_281, 9, 9) connect _WIRE_280.hr, _T_3850 node _T_3851 = bits(_WIRE_281, 10, 10) connect _WIRE_280.hx, _T_3851 node _T_3852 = bits(_WIRE_281, 11, 11) connect _WIRE_280.hw, _T_3852 node _T_3853 = bits(_WIRE_281, 12, 12) connect _WIRE_280.sr, _T_3853 node _T_3854 = bits(_WIRE_281, 13, 13) connect _WIRE_280.sx, _T_3854 node _T_3855 = bits(_WIRE_281, 14, 14) connect _WIRE_280.sw, _T_3855 node _T_3856 = bits(_WIRE_281, 15, 15) connect _WIRE_280.gf, _T_3856 node _T_3857 = bits(_WIRE_281, 16, 16) connect _WIRE_280.pf, _T_3857 node _T_3858 = bits(_WIRE_281, 17, 17) connect _WIRE_280.ae_stage2, _T_3858 node _T_3859 = bits(_WIRE_281, 18, 18) connect _WIRE_280.ae_final, _T_3859 node _T_3860 = bits(_WIRE_281, 19, 19) connect _WIRE_280.ae_ptw, _T_3860 node _T_3861 = bits(_WIRE_281, 20, 20) connect _WIRE_280.g, _T_3861 node _T_3862 = bits(_WIRE_281, 21, 21) connect _WIRE_280.u, _T_3862 node _T_3863 = bits(_WIRE_281, 41, 22) connect _WIRE_280.ppn, _T_3863 node _T_3864 = eq(special_entry.tag_v, hv_12) node _T_3865 = and(_T_3864, _WIRE_280.fragmented_superpage) when _T_3865 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3866 = eq(hg_12, UInt<1>(0h0)) node _T_3867 = and(_T_3866, io.sfence.bits.rs2) when _T_3867 : wire _WIRE_282 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_283 : UInt<42> connect _WIRE_283, special_entry.data[0] node _T_3868 = bits(_WIRE_283, 0, 0) connect _WIRE_282.fragmented_superpage, _T_3868 node _T_3869 = bits(_WIRE_283, 1, 1) connect _WIRE_282.c, _T_3869 node _T_3870 = bits(_WIRE_283, 2, 2) connect _WIRE_282.eff, _T_3870 node _T_3871 = bits(_WIRE_283, 3, 3) connect _WIRE_282.paa, _T_3871 node _T_3872 = bits(_WIRE_283, 4, 4) connect _WIRE_282.pal, _T_3872 node _T_3873 = bits(_WIRE_283, 5, 5) connect _WIRE_282.ppp, _T_3873 node _T_3874 = bits(_WIRE_283, 6, 6) connect _WIRE_282.pr, _T_3874 node _T_3875 = bits(_WIRE_283, 7, 7) connect _WIRE_282.px, _T_3875 node _T_3876 = bits(_WIRE_283, 8, 8) connect _WIRE_282.pw, _T_3876 node _T_3877 = bits(_WIRE_283, 9, 9) connect _WIRE_282.hr, _T_3877 node _T_3878 = bits(_WIRE_283, 10, 10) connect _WIRE_282.hx, _T_3878 node _T_3879 = bits(_WIRE_283, 11, 11) connect _WIRE_282.hw, _T_3879 node _T_3880 = bits(_WIRE_283, 12, 12) connect _WIRE_282.sr, _T_3880 node _T_3881 = bits(_WIRE_283, 13, 13) connect _WIRE_282.sx, _T_3881 node _T_3882 = bits(_WIRE_283, 14, 14) connect _WIRE_282.sw, _T_3882 node _T_3883 = bits(_WIRE_283, 15, 15) connect _WIRE_282.gf, _T_3883 node _T_3884 = bits(_WIRE_283, 16, 16) connect _WIRE_282.pf, _T_3884 node _T_3885 = bits(_WIRE_283, 17, 17) connect _WIRE_282.ae_stage2, _T_3885 node _T_3886 = bits(_WIRE_283, 18, 18) connect _WIRE_282.ae_final, _T_3886 node _T_3887 = bits(_WIRE_283, 19, 19) connect _WIRE_282.ae_ptw, _T_3887 node _T_3888 = bits(_WIRE_283, 20, 20) connect _WIRE_282.g, _T_3888 node _T_3889 = bits(_WIRE_283, 21, 21) connect _WIRE_282.u, _T_3889 node _T_3890 = bits(_WIRE_283, 41, 22) connect _WIRE_282.ppn, _T_3890 node _T_3891 = eq(special_entry.tag_v, hv_12) node _T_3892 = eq(_WIRE_282.g, UInt<1>(0h0)) node _T_3893 = and(_T_3891, _T_3892) when _T_3893 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3894 = or(hv_12, hg_12) wire _WIRE_284 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_285 : UInt<42> connect _WIRE_285, special_entry.data[0] node _T_3895 = bits(_WIRE_285, 0, 0) connect _WIRE_284.fragmented_superpage, _T_3895 node _T_3896 = bits(_WIRE_285, 1, 1) connect _WIRE_284.c, _T_3896 node _T_3897 = bits(_WIRE_285, 2, 2) connect _WIRE_284.eff, _T_3897 node _T_3898 = bits(_WIRE_285, 3, 3) connect _WIRE_284.paa, _T_3898 node _T_3899 = bits(_WIRE_285, 4, 4) connect _WIRE_284.pal, _T_3899 node _T_3900 = bits(_WIRE_285, 5, 5) connect _WIRE_284.ppp, _T_3900 node _T_3901 = bits(_WIRE_285, 6, 6) connect _WIRE_284.pr, _T_3901 node _T_3902 = bits(_WIRE_285, 7, 7) connect _WIRE_284.px, _T_3902 node _T_3903 = bits(_WIRE_285, 8, 8) connect _WIRE_284.pw, _T_3903 node _T_3904 = bits(_WIRE_285, 9, 9) connect _WIRE_284.hr, _T_3904 node _T_3905 = bits(_WIRE_285, 10, 10) connect _WIRE_284.hx, _T_3905 node _T_3906 = bits(_WIRE_285, 11, 11) connect _WIRE_284.hw, _T_3906 node _T_3907 = bits(_WIRE_285, 12, 12) connect _WIRE_284.sr, _T_3907 node _T_3908 = bits(_WIRE_285, 13, 13) connect _WIRE_284.sx, _T_3908 node _T_3909 = bits(_WIRE_285, 14, 14) connect _WIRE_284.sw, _T_3909 node _T_3910 = bits(_WIRE_285, 15, 15) connect _WIRE_284.gf, _T_3910 node _T_3911 = bits(_WIRE_285, 16, 16) connect _WIRE_284.pf, _T_3911 node _T_3912 = bits(_WIRE_285, 17, 17) connect _WIRE_284.ae_stage2, _T_3912 node _T_3913 = bits(_WIRE_285, 18, 18) connect _WIRE_284.ae_final, _T_3913 node _T_3914 = bits(_WIRE_285, 19, 19) connect _WIRE_284.ae_ptw, _T_3914 node _T_3915 = bits(_WIRE_285, 20, 20) connect _WIRE_284.g, _T_3915 node _T_3916 = bits(_WIRE_285, 21, 21) connect _WIRE_284.u, _T_3916 node _T_3917 = bits(_WIRE_285, 41, 22) connect _WIRE_284.ppn, _T_3917 node _T_3918 = eq(special_entry.tag_v, _T_3894) when _T_3918 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3919 = and(io.req.ready, io.req.valid) node _T_3920 = and(_T_3919, vsatp_mode_mismatch) when _T_3920 : wire _WIRE_286 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_287 : UInt<42> connect _WIRE_287, sectored_entries[0][0].data[0] node _T_3921 = bits(_WIRE_287, 0, 0) connect _WIRE_286.fragmented_superpage, _T_3921 node _T_3922 = bits(_WIRE_287, 1, 1) connect _WIRE_286.c, _T_3922 node _T_3923 = bits(_WIRE_287, 2, 2) connect _WIRE_286.eff, _T_3923 node _T_3924 = bits(_WIRE_287, 3, 3) connect _WIRE_286.paa, _T_3924 node _T_3925 = bits(_WIRE_287, 4, 4) connect _WIRE_286.pal, _T_3925 node _T_3926 = bits(_WIRE_287, 5, 5) connect _WIRE_286.ppp, _T_3926 node _T_3927 = bits(_WIRE_287, 6, 6) connect _WIRE_286.pr, _T_3927 node _T_3928 = bits(_WIRE_287, 7, 7) connect _WIRE_286.px, _T_3928 node _T_3929 = bits(_WIRE_287, 8, 8) connect _WIRE_286.pw, _T_3929 node _T_3930 = bits(_WIRE_287, 9, 9) connect _WIRE_286.hr, _T_3930 node _T_3931 = bits(_WIRE_287, 10, 10) connect _WIRE_286.hx, _T_3931 node _T_3932 = bits(_WIRE_287, 11, 11) connect _WIRE_286.hw, _T_3932 node _T_3933 = bits(_WIRE_287, 12, 12) connect _WIRE_286.sr, _T_3933 node _T_3934 = bits(_WIRE_287, 13, 13) connect _WIRE_286.sx, _T_3934 node _T_3935 = bits(_WIRE_287, 14, 14) connect _WIRE_286.sw, _T_3935 node _T_3936 = bits(_WIRE_287, 15, 15) connect _WIRE_286.gf, _T_3936 node _T_3937 = bits(_WIRE_287, 16, 16) connect _WIRE_286.pf, _T_3937 node _T_3938 = bits(_WIRE_287, 17, 17) connect _WIRE_286.ae_stage2, _T_3938 node _T_3939 = bits(_WIRE_287, 18, 18) connect _WIRE_286.ae_final, _T_3939 node _T_3940 = bits(_WIRE_287, 19, 19) connect _WIRE_286.ae_ptw, _T_3940 node _T_3941 = bits(_WIRE_287, 20, 20) connect _WIRE_286.g, _T_3941 node _T_3942 = bits(_WIRE_287, 21, 21) connect _WIRE_286.u, _T_3942 node _T_3943 = bits(_WIRE_287, 41, 22) connect _WIRE_286.ppn, _T_3943 wire _WIRE_288 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_289 : UInt<42> connect _WIRE_289, sectored_entries[0][0].data[1] node _T_3944 = bits(_WIRE_289, 0, 0) connect _WIRE_288.fragmented_superpage, _T_3944 node _T_3945 = bits(_WIRE_289, 1, 1) connect _WIRE_288.c, _T_3945 node _T_3946 = bits(_WIRE_289, 2, 2) connect _WIRE_288.eff, _T_3946 node _T_3947 = bits(_WIRE_289, 3, 3) connect _WIRE_288.paa, _T_3947 node _T_3948 = bits(_WIRE_289, 4, 4) connect _WIRE_288.pal, _T_3948 node _T_3949 = bits(_WIRE_289, 5, 5) connect _WIRE_288.ppp, _T_3949 node _T_3950 = bits(_WIRE_289, 6, 6) connect _WIRE_288.pr, _T_3950 node _T_3951 = bits(_WIRE_289, 7, 7) connect _WIRE_288.px, _T_3951 node _T_3952 = bits(_WIRE_289, 8, 8) connect _WIRE_288.pw, _T_3952 node _T_3953 = bits(_WIRE_289, 9, 9) connect _WIRE_288.hr, _T_3953 node _T_3954 = bits(_WIRE_289, 10, 10) connect _WIRE_288.hx, _T_3954 node _T_3955 = bits(_WIRE_289, 11, 11) connect _WIRE_288.hw, _T_3955 node _T_3956 = bits(_WIRE_289, 12, 12) connect _WIRE_288.sr, _T_3956 node _T_3957 = bits(_WIRE_289, 13, 13) connect _WIRE_288.sx, _T_3957 node _T_3958 = bits(_WIRE_289, 14, 14) connect _WIRE_288.sw, _T_3958 node _T_3959 = bits(_WIRE_289, 15, 15) connect _WIRE_288.gf, _T_3959 node _T_3960 = bits(_WIRE_289, 16, 16) connect _WIRE_288.pf, _T_3960 node _T_3961 = bits(_WIRE_289, 17, 17) connect _WIRE_288.ae_stage2, _T_3961 node _T_3962 = bits(_WIRE_289, 18, 18) connect _WIRE_288.ae_final, _T_3962 node _T_3963 = bits(_WIRE_289, 19, 19) connect _WIRE_288.ae_ptw, _T_3963 node _T_3964 = bits(_WIRE_289, 20, 20) connect _WIRE_288.g, _T_3964 node _T_3965 = bits(_WIRE_289, 21, 21) connect _WIRE_288.u, _T_3965 node _T_3966 = bits(_WIRE_289, 41, 22) connect _WIRE_288.ppn, _T_3966 wire _WIRE_290 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_291 : UInt<42> connect _WIRE_291, sectored_entries[0][0].data[2] node _T_3967 = bits(_WIRE_291, 0, 0) connect _WIRE_290.fragmented_superpage, _T_3967 node _T_3968 = bits(_WIRE_291, 1, 1) connect _WIRE_290.c, _T_3968 node _T_3969 = bits(_WIRE_291, 2, 2) connect _WIRE_290.eff, _T_3969 node _T_3970 = bits(_WIRE_291, 3, 3) connect _WIRE_290.paa, _T_3970 node _T_3971 = bits(_WIRE_291, 4, 4) connect _WIRE_290.pal, _T_3971 node _T_3972 = bits(_WIRE_291, 5, 5) connect _WIRE_290.ppp, _T_3972 node _T_3973 = bits(_WIRE_291, 6, 6) connect _WIRE_290.pr, _T_3973 node _T_3974 = bits(_WIRE_291, 7, 7) connect _WIRE_290.px, _T_3974 node _T_3975 = bits(_WIRE_291, 8, 8) connect _WIRE_290.pw, _T_3975 node _T_3976 = bits(_WIRE_291, 9, 9) connect _WIRE_290.hr, _T_3976 node _T_3977 = bits(_WIRE_291, 10, 10) connect _WIRE_290.hx, _T_3977 node _T_3978 = bits(_WIRE_291, 11, 11) connect _WIRE_290.hw, _T_3978 node _T_3979 = bits(_WIRE_291, 12, 12) connect _WIRE_290.sr, _T_3979 node _T_3980 = bits(_WIRE_291, 13, 13) connect _WIRE_290.sx, _T_3980 node _T_3981 = bits(_WIRE_291, 14, 14) connect _WIRE_290.sw, _T_3981 node _T_3982 = bits(_WIRE_291, 15, 15) connect _WIRE_290.gf, _T_3982 node _T_3983 = bits(_WIRE_291, 16, 16) connect _WIRE_290.pf, _T_3983 node _T_3984 = bits(_WIRE_291, 17, 17) connect _WIRE_290.ae_stage2, _T_3984 node _T_3985 = bits(_WIRE_291, 18, 18) connect _WIRE_290.ae_final, _T_3985 node _T_3986 = bits(_WIRE_291, 19, 19) connect _WIRE_290.ae_ptw, _T_3986 node _T_3987 = bits(_WIRE_291, 20, 20) connect _WIRE_290.g, _T_3987 node _T_3988 = bits(_WIRE_291, 21, 21) connect _WIRE_290.u, _T_3988 node _T_3989 = bits(_WIRE_291, 41, 22) connect _WIRE_290.ppn, _T_3989 wire _WIRE_292 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_293 : UInt<42> connect _WIRE_293, sectored_entries[0][0].data[3] node _T_3990 = bits(_WIRE_293, 0, 0) connect _WIRE_292.fragmented_superpage, _T_3990 node _T_3991 = bits(_WIRE_293, 1, 1) connect _WIRE_292.c, _T_3991 node _T_3992 = bits(_WIRE_293, 2, 2) connect _WIRE_292.eff, _T_3992 node _T_3993 = bits(_WIRE_293, 3, 3) connect _WIRE_292.paa, _T_3993 node _T_3994 = bits(_WIRE_293, 4, 4) connect _WIRE_292.pal, _T_3994 node _T_3995 = bits(_WIRE_293, 5, 5) connect _WIRE_292.ppp, _T_3995 node _T_3996 = bits(_WIRE_293, 6, 6) connect _WIRE_292.pr, _T_3996 node _T_3997 = bits(_WIRE_293, 7, 7) connect _WIRE_292.px, _T_3997 node _T_3998 = bits(_WIRE_293, 8, 8) connect _WIRE_292.pw, _T_3998 node _T_3999 = bits(_WIRE_293, 9, 9) connect _WIRE_292.hr, _T_3999 node _T_4000 = bits(_WIRE_293, 10, 10) connect _WIRE_292.hx, _T_4000 node _T_4001 = bits(_WIRE_293, 11, 11) connect _WIRE_292.hw, _T_4001 node _T_4002 = bits(_WIRE_293, 12, 12) connect _WIRE_292.sr, _T_4002 node _T_4003 = bits(_WIRE_293, 13, 13) connect _WIRE_292.sx, _T_4003 node _T_4004 = bits(_WIRE_293, 14, 14) connect _WIRE_292.sw, _T_4004 node _T_4005 = bits(_WIRE_293, 15, 15) connect _WIRE_292.gf, _T_4005 node _T_4006 = bits(_WIRE_293, 16, 16) connect _WIRE_292.pf, _T_4006 node _T_4007 = bits(_WIRE_293, 17, 17) connect _WIRE_292.ae_stage2, _T_4007 node _T_4008 = bits(_WIRE_293, 18, 18) connect _WIRE_292.ae_final, _T_4008 node _T_4009 = bits(_WIRE_293, 19, 19) connect _WIRE_292.ae_ptw, _T_4009 node _T_4010 = bits(_WIRE_293, 20, 20) connect _WIRE_292.g, _T_4010 node _T_4011 = bits(_WIRE_293, 21, 21) connect _WIRE_292.u, _T_4011 node _T_4012 = bits(_WIRE_293, 41, 22) connect _WIRE_292.ppn, _T_4012 node _T_4013 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4013 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_4014 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4014 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_4015 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4015 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_4016 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4016 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) wire _WIRE_294 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_295 : UInt<42> connect _WIRE_295, sectored_entries[0][1].data[0] node _T_4017 = bits(_WIRE_295, 0, 0) connect _WIRE_294.fragmented_superpage, _T_4017 node _T_4018 = bits(_WIRE_295, 1, 1) connect _WIRE_294.c, _T_4018 node _T_4019 = bits(_WIRE_295, 2, 2) connect _WIRE_294.eff, _T_4019 node _T_4020 = bits(_WIRE_295, 3, 3) connect _WIRE_294.paa, _T_4020 node _T_4021 = bits(_WIRE_295, 4, 4) connect _WIRE_294.pal, _T_4021 node _T_4022 = bits(_WIRE_295, 5, 5) connect _WIRE_294.ppp, _T_4022 node _T_4023 = bits(_WIRE_295, 6, 6) connect _WIRE_294.pr, _T_4023 node _T_4024 = bits(_WIRE_295, 7, 7) connect _WIRE_294.px, _T_4024 node _T_4025 = bits(_WIRE_295, 8, 8) connect _WIRE_294.pw, _T_4025 node _T_4026 = bits(_WIRE_295, 9, 9) connect _WIRE_294.hr, _T_4026 node _T_4027 = bits(_WIRE_295, 10, 10) connect _WIRE_294.hx, _T_4027 node _T_4028 = bits(_WIRE_295, 11, 11) connect _WIRE_294.hw, _T_4028 node _T_4029 = bits(_WIRE_295, 12, 12) connect _WIRE_294.sr, _T_4029 node _T_4030 = bits(_WIRE_295, 13, 13) connect _WIRE_294.sx, _T_4030 node _T_4031 = bits(_WIRE_295, 14, 14) connect _WIRE_294.sw, _T_4031 node _T_4032 = bits(_WIRE_295, 15, 15) connect _WIRE_294.gf, _T_4032 node _T_4033 = bits(_WIRE_295, 16, 16) connect _WIRE_294.pf, _T_4033 node _T_4034 = bits(_WIRE_295, 17, 17) connect _WIRE_294.ae_stage2, _T_4034 node _T_4035 = bits(_WIRE_295, 18, 18) connect _WIRE_294.ae_final, _T_4035 node _T_4036 = bits(_WIRE_295, 19, 19) connect _WIRE_294.ae_ptw, _T_4036 node _T_4037 = bits(_WIRE_295, 20, 20) connect _WIRE_294.g, _T_4037 node _T_4038 = bits(_WIRE_295, 21, 21) connect _WIRE_294.u, _T_4038 node _T_4039 = bits(_WIRE_295, 41, 22) connect _WIRE_294.ppn, _T_4039 wire _WIRE_296 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_297 : UInt<42> connect _WIRE_297, sectored_entries[0][1].data[1] node _T_4040 = bits(_WIRE_297, 0, 0) connect _WIRE_296.fragmented_superpage, _T_4040 node _T_4041 = bits(_WIRE_297, 1, 1) connect _WIRE_296.c, _T_4041 node _T_4042 = bits(_WIRE_297, 2, 2) connect _WIRE_296.eff, _T_4042 node _T_4043 = bits(_WIRE_297, 3, 3) connect _WIRE_296.paa, _T_4043 node _T_4044 = bits(_WIRE_297, 4, 4) connect _WIRE_296.pal, _T_4044 node _T_4045 = bits(_WIRE_297, 5, 5) connect _WIRE_296.ppp, _T_4045 node _T_4046 = bits(_WIRE_297, 6, 6) connect _WIRE_296.pr, _T_4046 node _T_4047 = bits(_WIRE_297, 7, 7) connect _WIRE_296.px, _T_4047 node _T_4048 = bits(_WIRE_297, 8, 8) connect _WIRE_296.pw, _T_4048 node _T_4049 = bits(_WIRE_297, 9, 9) connect _WIRE_296.hr, _T_4049 node _T_4050 = bits(_WIRE_297, 10, 10) connect _WIRE_296.hx, _T_4050 node _T_4051 = bits(_WIRE_297, 11, 11) connect _WIRE_296.hw, _T_4051 node _T_4052 = bits(_WIRE_297, 12, 12) connect _WIRE_296.sr, _T_4052 node _T_4053 = bits(_WIRE_297, 13, 13) connect _WIRE_296.sx, _T_4053 node _T_4054 = bits(_WIRE_297, 14, 14) connect _WIRE_296.sw, _T_4054 node _T_4055 = bits(_WIRE_297, 15, 15) connect _WIRE_296.gf, _T_4055 node _T_4056 = bits(_WIRE_297, 16, 16) connect _WIRE_296.pf, _T_4056 node _T_4057 = bits(_WIRE_297, 17, 17) connect _WIRE_296.ae_stage2, _T_4057 node _T_4058 = bits(_WIRE_297, 18, 18) connect _WIRE_296.ae_final, _T_4058 node _T_4059 = bits(_WIRE_297, 19, 19) connect _WIRE_296.ae_ptw, _T_4059 node _T_4060 = bits(_WIRE_297, 20, 20) connect _WIRE_296.g, _T_4060 node _T_4061 = bits(_WIRE_297, 21, 21) connect _WIRE_296.u, _T_4061 node _T_4062 = bits(_WIRE_297, 41, 22) connect _WIRE_296.ppn, _T_4062 wire _WIRE_298 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_299 : UInt<42> connect _WIRE_299, sectored_entries[0][1].data[2] node _T_4063 = bits(_WIRE_299, 0, 0) connect _WIRE_298.fragmented_superpage, _T_4063 node _T_4064 = bits(_WIRE_299, 1, 1) connect _WIRE_298.c, _T_4064 node _T_4065 = bits(_WIRE_299, 2, 2) connect _WIRE_298.eff, _T_4065 node _T_4066 = bits(_WIRE_299, 3, 3) connect _WIRE_298.paa, _T_4066 node _T_4067 = bits(_WIRE_299, 4, 4) connect _WIRE_298.pal, _T_4067 node _T_4068 = bits(_WIRE_299, 5, 5) connect _WIRE_298.ppp, _T_4068 node _T_4069 = bits(_WIRE_299, 6, 6) connect _WIRE_298.pr, _T_4069 node _T_4070 = bits(_WIRE_299, 7, 7) connect _WIRE_298.px, _T_4070 node _T_4071 = bits(_WIRE_299, 8, 8) connect _WIRE_298.pw, _T_4071 node _T_4072 = bits(_WIRE_299, 9, 9) connect _WIRE_298.hr, _T_4072 node _T_4073 = bits(_WIRE_299, 10, 10) connect _WIRE_298.hx, _T_4073 node _T_4074 = bits(_WIRE_299, 11, 11) connect _WIRE_298.hw, _T_4074 node _T_4075 = bits(_WIRE_299, 12, 12) connect _WIRE_298.sr, _T_4075 node _T_4076 = bits(_WIRE_299, 13, 13) connect _WIRE_298.sx, _T_4076 node _T_4077 = bits(_WIRE_299, 14, 14) connect _WIRE_298.sw, _T_4077 node _T_4078 = bits(_WIRE_299, 15, 15) connect _WIRE_298.gf, _T_4078 node _T_4079 = bits(_WIRE_299, 16, 16) connect _WIRE_298.pf, _T_4079 node _T_4080 = bits(_WIRE_299, 17, 17) connect _WIRE_298.ae_stage2, _T_4080 node _T_4081 = bits(_WIRE_299, 18, 18) connect _WIRE_298.ae_final, _T_4081 node _T_4082 = bits(_WIRE_299, 19, 19) connect _WIRE_298.ae_ptw, _T_4082 node _T_4083 = bits(_WIRE_299, 20, 20) connect _WIRE_298.g, _T_4083 node _T_4084 = bits(_WIRE_299, 21, 21) connect _WIRE_298.u, _T_4084 node _T_4085 = bits(_WIRE_299, 41, 22) connect _WIRE_298.ppn, _T_4085 wire _WIRE_300 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_301 : UInt<42> connect _WIRE_301, sectored_entries[0][1].data[3] node _T_4086 = bits(_WIRE_301, 0, 0) connect _WIRE_300.fragmented_superpage, _T_4086 node _T_4087 = bits(_WIRE_301, 1, 1) connect _WIRE_300.c, _T_4087 node _T_4088 = bits(_WIRE_301, 2, 2) connect _WIRE_300.eff, _T_4088 node _T_4089 = bits(_WIRE_301, 3, 3) connect _WIRE_300.paa, _T_4089 node _T_4090 = bits(_WIRE_301, 4, 4) connect _WIRE_300.pal, _T_4090 node _T_4091 = bits(_WIRE_301, 5, 5) connect _WIRE_300.ppp, _T_4091 node _T_4092 = bits(_WIRE_301, 6, 6) connect _WIRE_300.pr, _T_4092 node _T_4093 = bits(_WIRE_301, 7, 7) connect _WIRE_300.px, _T_4093 node _T_4094 = bits(_WIRE_301, 8, 8) connect _WIRE_300.pw, _T_4094 node _T_4095 = bits(_WIRE_301, 9, 9) connect _WIRE_300.hr, _T_4095 node _T_4096 = bits(_WIRE_301, 10, 10) connect _WIRE_300.hx, _T_4096 node _T_4097 = bits(_WIRE_301, 11, 11) connect _WIRE_300.hw, _T_4097 node _T_4098 = bits(_WIRE_301, 12, 12) connect _WIRE_300.sr, _T_4098 node _T_4099 = bits(_WIRE_301, 13, 13) connect _WIRE_300.sx, _T_4099 node _T_4100 = bits(_WIRE_301, 14, 14) connect _WIRE_300.sw, _T_4100 node _T_4101 = bits(_WIRE_301, 15, 15) connect _WIRE_300.gf, _T_4101 node _T_4102 = bits(_WIRE_301, 16, 16) connect _WIRE_300.pf, _T_4102 node _T_4103 = bits(_WIRE_301, 17, 17) connect _WIRE_300.ae_stage2, _T_4103 node _T_4104 = bits(_WIRE_301, 18, 18) connect _WIRE_300.ae_final, _T_4104 node _T_4105 = bits(_WIRE_301, 19, 19) connect _WIRE_300.ae_ptw, _T_4105 node _T_4106 = bits(_WIRE_301, 20, 20) connect _WIRE_300.g, _T_4106 node _T_4107 = bits(_WIRE_301, 21, 21) connect _WIRE_300.u, _T_4107 node _T_4108 = bits(_WIRE_301, 41, 22) connect _WIRE_300.ppn, _T_4108 node _T_4109 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4109 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_4110 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4110 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_4111 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4111 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_4112 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4112 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) wire _WIRE_302 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_303 : UInt<42> connect _WIRE_303, sectored_entries[0][2].data[0] node _T_4113 = bits(_WIRE_303, 0, 0) connect _WIRE_302.fragmented_superpage, _T_4113 node _T_4114 = bits(_WIRE_303, 1, 1) connect _WIRE_302.c, _T_4114 node _T_4115 = bits(_WIRE_303, 2, 2) connect _WIRE_302.eff, _T_4115 node _T_4116 = bits(_WIRE_303, 3, 3) connect _WIRE_302.paa, _T_4116 node _T_4117 = bits(_WIRE_303, 4, 4) connect _WIRE_302.pal, _T_4117 node _T_4118 = bits(_WIRE_303, 5, 5) connect _WIRE_302.ppp, _T_4118 node _T_4119 = bits(_WIRE_303, 6, 6) connect _WIRE_302.pr, _T_4119 node _T_4120 = bits(_WIRE_303, 7, 7) connect _WIRE_302.px, _T_4120 node _T_4121 = bits(_WIRE_303, 8, 8) connect _WIRE_302.pw, _T_4121 node _T_4122 = bits(_WIRE_303, 9, 9) connect _WIRE_302.hr, _T_4122 node _T_4123 = bits(_WIRE_303, 10, 10) connect _WIRE_302.hx, _T_4123 node _T_4124 = bits(_WIRE_303, 11, 11) connect _WIRE_302.hw, _T_4124 node _T_4125 = bits(_WIRE_303, 12, 12) connect _WIRE_302.sr, _T_4125 node _T_4126 = bits(_WIRE_303, 13, 13) connect _WIRE_302.sx, _T_4126 node _T_4127 = bits(_WIRE_303, 14, 14) connect _WIRE_302.sw, _T_4127 node _T_4128 = bits(_WIRE_303, 15, 15) connect _WIRE_302.gf, _T_4128 node _T_4129 = bits(_WIRE_303, 16, 16) connect _WIRE_302.pf, _T_4129 node _T_4130 = bits(_WIRE_303, 17, 17) connect _WIRE_302.ae_stage2, _T_4130 node _T_4131 = bits(_WIRE_303, 18, 18) connect _WIRE_302.ae_final, _T_4131 node _T_4132 = bits(_WIRE_303, 19, 19) connect _WIRE_302.ae_ptw, _T_4132 node _T_4133 = bits(_WIRE_303, 20, 20) connect _WIRE_302.g, _T_4133 node _T_4134 = bits(_WIRE_303, 21, 21) connect _WIRE_302.u, _T_4134 node _T_4135 = bits(_WIRE_303, 41, 22) connect _WIRE_302.ppn, _T_4135 wire _WIRE_304 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_305 : UInt<42> connect _WIRE_305, sectored_entries[0][2].data[1] node _T_4136 = bits(_WIRE_305, 0, 0) connect _WIRE_304.fragmented_superpage, _T_4136 node _T_4137 = bits(_WIRE_305, 1, 1) connect _WIRE_304.c, _T_4137 node _T_4138 = bits(_WIRE_305, 2, 2) connect _WIRE_304.eff, _T_4138 node _T_4139 = bits(_WIRE_305, 3, 3) connect _WIRE_304.paa, _T_4139 node _T_4140 = bits(_WIRE_305, 4, 4) connect _WIRE_304.pal, _T_4140 node _T_4141 = bits(_WIRE_305, 5, 5) connect _WIRE_304.ppp, _T_4141 node _T_4142 = bits(_WIRE_305, 6, 6) connect _WIRE_304.pr, _T_4142 node _T_4143 = bits(_WIRE_305, 7, 7) connect _WIRE_304.px, _T_4143 node _T_4144 = bits(_WIRE_305, 8, 8) connect _WIRE_304.pw, _T_4144 node _T_4145 = bits(_WIRE_305, 9, 9) connect _WIRE_304.hr, _T_4145 node _T_4146 = bits(_WIRE_305, 10, 10) connect _WIRE_304.hx, _T_4146 node _T_4147 = bits(_WIRE_305, 11, 11) connect _WIRE_304.hw, _T_4147 node _T_4148 = bits(_WIRE_305, 12, 12) connect _WIRE_304.sr, _T_4148 node _T_4149 = bits(_WIRE_305, 13, 13) connect _WIRE_304.sx, _T_4149 node _T_4150 = bits(_WIRE_305, 14, 14) connect _WIRE_304.sw, _T_4150 node _T_4151 = bits(_WIRE_305, 15, 15) connect _WIRE_304.gf, _T_4151 node _T_4152 = bits(_WIRE_305, 16, 16) connect _WIRE_304.pf, _T_4152 node _T_4153 = bits(_WIRE_305, 17, 17) connect _WIRE_304.ae_stage2, _T_4153 node _T_4154 = bits(_WIRE_305, 18, 18) connect _WIRE_304.ae_final, _T_4154 node _T_4155 = bits(_WIRE_305, 19, 19) connect _WIRE_304.ae_ptw, _T_4155 node _T_4156 = bits(_WIRE_305, 20, 20) connect _WIRE_304.g, _T_4156 node _T_4157 = bits(_WIRE_305, 21, 21) connect _WIRE_304.u, _T_4157 node _T_4158 = bits(_WIRE_305, 41, 22) connect _WIRE_304.ppn, _T_4158 wire _WIRE_306 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_307 : UInt<42> connect _WIRE_307, sectored_entries[0][2].data[2] node _T_4159 = bits(_WIRE_307, 0, 0) connect _WIRE_306.fragmented_superpage, _T_4159 node _T_4160 = bits(_WIRE_307, 1, 1) connect _WIRE_306.c, _T_4160 node _T_4161 = bits(_WIRE_307, 2, 2) connect _WIRE_306.eff, _T_4161 node _T_4162 = bits(_WIRE_307, 3, 3) connect _WIRE_306.paa, _T_4162 node _T_4163 = bits(_WIRE_307, 4, 4) connect _WIRE_306.pal, _T_4163 node _T_4164 = bits(_WIRE_307, 5, 5) connect _WIRE_306.ppp, _T_4164 node _T_4165 = bits(_WIRE_307, 6, 6) connect _WIRE_306.pr, _T_4165 node _T_4166 = bits(_WIRE_307, 7, 7) connect _WIRE_306.px, _T_4166 node _T_4167 = bits(_WIRE_307, 8, 8) connect _WIRE_306.pw, _T_4167 node _T_4168 = bits(_WIRE_307, 9, 9) connect _WIRE_306.hr, _T_4168 node _T_4169 = bits(_WIRE_307, 10, 10) connect _WIRE_306.hx, _T_4169 node _T_4170 = bits(_WIRE_307, 11, 11) connect _WIRE_306.hw, _T_4170 node _T_4171 = bits(_WIRE_307, 12, 12) connect _WIRE_306.sr, _T_4171 node _T_4172 = bits(_WIRE_307, 13, 13) connect _WIRE_306.sx, _T_4172 node _T_4173 = bits(_WIRE_307, 14, 14) connect _WIRE_306.sw, _T_4173 node _T_4174 = bits(_WIRE_307, 15, 15) connect _WIRE_306.gf, _T_4174 node _T_4175 = bits(_WIRE_307, 16, 16) connect _WIRE_306.pf, _T_4175 node _T_4176 = bits(_WIRE_307, 17, 17) connect _WIRE_306.ae_stage2, _T_4176 node _T_4177 = bits(_WIRE_307, 18, 18) connect _WIRE_306.ae_final, _T_4177 node _T_4178 = bits(_WIRE_307, 19, 19) connect _WIRE_306.ae_ptw, _T_4178 node _T_4179 = bits(_WIRE_307, 20, 20) connect _WIRE_306.g, _T_4179 node _T_4180 = bits(_WIRE_307, 21, 21) connect _WIRE_306.u, _T_4180 node _T_4181 = bits(_WIRE_307, 41, 22) connect _WIRE_306.ppn, _T_4181 wire _WIRE_308 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_309 : UInt<42> connect _WIRE_309, sectored_entries[0][2].data[3] node _T_4182 = bits(_WIRE_309, 0, 0) connect _WIRE_308.fragmented_superpage, _T_4182 node _T_4183 = bits(_WIRE_309, 1, 1) connect _WIRE_308.c, _T_4183 node _T_4184 = bits(_WIRE_309, 2, 2) connect _WIRE_308.eff, _T_4184 node _T_4185 = bits(_WIRE_309, 3, 3) connect _WIRE_308.paa, _T_4185 node _T_4186 = bits(_WIRE_309, 4, 4) connect _WIRE_308.pal, _T_4186 node _T_4187 = bits(_WIRE_309, 5, 5) connect _WIRE_308.ppp, _T_4187 node _T_4188 = bits(_WIRE_309, 6, 6) connect _WIRE_308.pr, _T_4188 node _T_4189 = bits(_WIRE_309, 7, 7) connect _WIRE_308.px, _T_4189 node _T_4190 = bits(_WIRE_309, 8, 8) connect _WIRE_308.pw, _T_4190 node _T_4191 = bits(_WIRE_309, 9, 9) connect _WIRE_308.hr, _T_4191 node _T_4192 = bits(_WIRE_309, 10, 10) connect _WIRE_308.hx, _T_4192 node _T_4193 = bits(_WIRE_309, 11, 11) connect _WIRE_308.hw, _T_4193 node _T_4194 = bits(_WIRE_309, 12, 12) connect _WIRE_308.sr, _T_4194 node _T_4195 = bits(_WIRE_309, 13, 13) connect _WIRE_308.sx, _T_4195 node _T_4196 = bits(_WIRE_309, 14, 14) connect _WIRE_308.sw, _T_4196 node _T_4197 = bits(_WIRE_309, 15, 15) connect _WIRE_308.gf, _T_4197 node _T_4198 = bits(_WIRE_309, 16, 16) connect _WIRE_308.pf, _T_4198 node _T_4199 = bits(_WIRE_309, 17, 17) connect _WIRE_308.ae_stage2, _T_4199 node _T_4200 = bits(_WIRE_309, 18, 18) connect _WIRE_308.ae_final, _T_4200 node _T_4201 = bits(_WIRE_309, 19, 19) connect _WIRE_308.ae_ptw, _T_4201 node _T_4202 = bits(_WIRE_309, 20, 20) connect _WIRE_308.g, _T_4202 node _T_4203 = bits(_WIRE_309, 21, 21) connect _WIRE_308.u, _T_4203 node _T_4204 = bits(_WIRE_309, 41, 22) connect _WIRE_308.ppn, _T_4204 node _T_4205 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4205 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_4206 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4206 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_4207 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4207 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_4208 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4208 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) wire _WIRE_310 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_311 : UInt<42> connect _WIRE_311, sectored_entries[0][3].data[0] node _T_4209 = bits(_WIRE_311, 0, 0) connect _WIRE_310.fragmented_superpage, _T_4209 node _T_4210 = bits(_WIRE_311, 1, 1) connect _WIRE_310.c, _T_4210 node _T_4211 = bits(_WIRE_311, 2, 2) connect _WIRE_310.eff, _T_4211 node _T_4212 = bits(_WIRE_311, 3, 3) connect _WIRE_310.paa, _T_4212 node _T_4213 = bits(_WIRE_311, 4, 4) connect _WIRE_310.pal, _T_4213 node _T_4214 = bits(_WIRE_311, 5, 5) connect _WIRE_310.ppp, _T_4214 node _T_4215 = bits(_WIRE_311, 6, 6) connect _WIRE_310.pr, _T_4215 node _T_4216 = bits(_WIRE_311, 7, 7) connect _WIRE_310.px, _T_4216 node _T_4217 = bits(_WIRE_311, 8, 8) connect _WIRE_310.pw, _T_4217 node _T_4218 = bits(_WIRE_311, 9, 9) connect _WIRE_310.hr, _T_4218 node _T_4219 = bits(_WIRE_311, 10, 10) connect _WIRE_310.hx, _T_4219 node _T_4220 = bits(_WIRE_311, 11, 11) connect _WIRE_310.hw, _T_4220 node _T_4221 = bits(_WIRE_311, 12, 12) connect _WIRE_310.sr, _T_4221 node _T_4222 = bits(_WIRE_311, 13, 13) connect _WIRE_310.sx, _T_4222 node _T_4223 = bits(_WIRE_311, 14, 14) connect _WIRE_310.sw, _T_4223 node _T_4224 = bits(_WIRE_311, 15, 15) connect _WIRE_310.gf, _T_4224 node _T_4225 = bits(_WIRE_311, 16, 16) connect _WIRE_310.pf, _T_4225 node _T_4226 = bits(_WIRE_311, 17, 17) connect _WIRE_310.ae_stage2, _T_4226 node _T_4227 = bits(_WIRE_311, 18, 18) connect _WIRE_310.ae_final, _T_4227 node _T_4228 = bits(_WIRE_311, 19, 19) connect _WIRE_310.ae_ptw, _T_4228 node _T_4229 = bits(_WIRE_311, 20, 20) connect _WIRE_310.g, _T_4229 node _T_4230 = bits(_WIRE_311, 21, 21) connect _WIRE_310.u, _T_4230 node _T_4231 = bits(_WIRE_311, 41, 22) connect _WIRE_310.ppn, _T_4231 wire _WIRE_312 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_313 : UInt<42> connect _WIRE_313, sectored_entries[0][3].data[1] node _T_4232 = bits(_WIRE_313, 0, 0) connect _WIRE_312.fragmented_superpage, _T_4232 node _T_4233 = bits(_WIRE_313, 1, 1) connect _WIRE_312.c, _T_4233 node _T_4234 = bits(_WIRE_313, 2, 2) connect _WIRE_312.eff, _T_4234 node _T_4235 = bits(_WIRE_313, 3, 3) connect _WIRE_312.paa, _T_4235 node _T_4236 = bits(_WIRE_313, 4, 4) connect _WIRE_312.pal, _T_4236 node _T_4237 = bits(_WIRE_313, 5, 5) connect _WIRE_312.ppp, _T_4237 node _T_4238 = bits(_WIRE_313, 6, 6) connect _WIRE_312.pr, _T_4238 node _T_4239 = bits(_WIRE_313, 7, 7) connect _WIRE_312.px, _T_4239 node _T_4240 = bits(_WIRE_313, 8, 8) connect _WIRE_312.pw, _T_4240 node _T_4241 = bits(_WIRE_313, 9, 9) connect _WIRE_312.hr, _T_4241 node _T_4242 = bits(_WIRE_313, 10, 10) connect _WIRE_312.hx, _T_4242 node _T_4243 = bits(_WIRE_313, 11, 11) connect _WIRE_312.hw, _T_4243 node _T_4244 = bits(_WIRE_313, 12, 12) connect _WIRE_312.sr, _T_4244 node _T_4245 = bits(_WIRE_313, 13, 13) connect _WIRE_312.sx, _T_4245 node _T_4246 = bits(_WIRE_313, 14, 14) connect _WIRE_312.sw, _T_4246 node _T_4247 = bits(_WIRE_313, 15, 15) connect _WIRE_312.gf, _T_4247 node _T_4248 = bits(_WIRE_313, 16, 16) connect _WIRE_312.pf, _T_4248 node _T_4249 = bits(_WIRE_313, 17, 17) connect _WIRE_312.ae_stage2, _T_4249 node _T_4250 = bits(_WIRE_313, 18, 18) connect _WIRE_312.ae_final, _T_4250 node _T_4251 = bits(_WIRE_313, 19, 19) connect _WIRE_312.ae_ptw, _T_4251 node _T_4252 = bits(_WIRE_313, 20, 20) connect _WIRE_312.g, _T_4252 node _T_4253 = bits(_WIRE_313, 21, 21) connect _WIRE_312.u, _T_4253 node _T_4254 = bits(_WIRE_313, 41, 22) connect _WIRE_312.ppn, _T_4254 wire _WIRE_314 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_315 : UInt<42> connect _WIRE_315, sectored_entries[0][3].data[2] node _T_4255 = bits(_WIRE_315, 0, 0) connect _WIRE_314.fragmented_superpage, _T_4255 node _T_4256 = bits(_WIRE_315, 1, 1) connect _WIRE_314.c, _T_4256 node _T_4257 = bits(_WIRE_315, 2, 2) connect _WIRE_314.eff, _T_4257 node _T_4258 = bits(_WIRE_315, 3, 3) connect _WIRE_314.paa, _T_4258 node _T_4259 = bits(_WIRE_315, 4, 4) connect _WIRE_314.pal, _T_4259 node _T_4260 = bits(_WIRE_315, 5, 5) connect _WIRE_314.ppp, _T_4260 node _T_4261 = bits(_WIRE_315, 6, 6) connect _WIRE_314.pr, _T_4261 node _T_4262 = bits(_WIRE_315, 7, 7) connect _WIRE_314.px, _T_4262 node _T_4263 = bits(_WIRE_315, 8, 8) connect _WIRE_314.pw, _T_4263 node _T_4264 = bits(_WIRE_315, 9, 9) connect _WIRE_314.hr, _T_4264 node _T_4265 = bits(_WIRE_315, 10, 10) connect _WIRE_314.hx, _T_4265 node _T_4266 = bits(_WIRE_315, 11, 11) connect _WIRE_314.hw, _T_4266 node _T_4267 = bits(_WIRE_315, 12, 12) connect _WIRE_314.sr, _T_4267 node _T_4268 = bits(_WIRE_315, 13, 13) connect _WIRE_314.sx, _T_4268 node _T_4269 = bits(_WIRE_315, 14, 14) connect _WIRE_314.sw, _T_4269 node _T_4270 = bits(_WIRE_315, 15, 15) connect _WIRE_314.gf, _T_4270 node _T_4271 = bits(_WIRE_315, 16, 16) connect _WIRE_314.pf, _T_4271 node _T_4272 = bits(_WIRE_315, 17, 17) connect _WIRE_314.ae_stage2, _T_4272 node _T_4273 = bits(_WIRE_315, 18, 18) connect _WIRE_314.ae_final, _T_4273 node _T_4274 = bits(_WIRE_315, 19, 19) connect _WIRE_314.ae_ptw, _T_4274 node _T_4275 = bits(_WIRE_315, 20, 20) connect _WIRE_314.g, _T_4275 node _T_4276 = bits(_WIRE_315, 21, 21) connect _WIRE_314.u, _T_4276 node _T_4277 = bits(_WIRE_315, 41, 22) connect _WIRE_314.ppn, _T_4277 wire _WIRE_316 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_317 : UInt<42> connect _WIRE_317, sectored_entries[0][3].data[3] node _T_4278 = bits(_WIRE_317, 0, 0) connect _WIRE_316.fragmented_superpage, _T_4278 node _T_4279 = bits(_WIRE_317, 1, 1) connect _WIRE_316.c, _T_4279 node _T_4280 = bits(_WIRE_317, 2, 2) connect _WIRE_316.eff, _T_4280 node _T_4281 = bits(_WIRE_317, 3, 3) connect _WIRE_316.paa, _T_4281 node _T_4282 = bits(_WIRE_317, 4, 4) connect _WIRE_316.pal, _T_4282 node _T_4283 = bits(_WIRE_317, 5, 5) connect _WIRE_316.ppp, _T_4283 node _T_4284 = bits(_WIRE_317, 6, 6) connect _WIRE_316.pr, _T_4284 node _T_4285 = bits(_WIRE_317, 7, 7) connect _WIRE_316.px, _T_4285 node _T_4286 = bits(_WIRE_317, 8, 8) connect _WIRE_316.pw, _T_4286 node _T_4287 = bits(_WIRE_317, 9, 9) connect _WIRE_316.hr, _T_4287 node _T_4288 = bits(_WIRE_317, 10, 10) connect _WIRE_316.hx, _T_4288 node _T_4289 = bits(_WIRE_317, 11, 11) connect _WIRE_316.hw, _T_4289 node _T_4290 = bits(_WIRE_317, 12, 12) connect _WIRE_316.sr, _T_4290 node _T_4291 = bits(_WIRE_317, 13, 13) connect _WIRE_316.sx, _T_4291 node _T_4292 = bits(_WIRE_317, 14, 14) connect _WIRE_316.sw, _T_4292 node _T_4293 = bits(_WIRE_317, 15, 15) connect _WIRE_316.gf, _T_4293 node _T_4294 = bits(_WIRE_317, 16, 16) connect _WIRE_316.pf, _T_4294 node _T_4295 = bits(_WIRE_317, 17, 17) connect _WIRE_316.ae_stage2, _T_4295 node _T_4296 = bits(_WIRE_317, 18, 18) connect _WIRE_316.ae_final, _T_4296 node _T_4297 = bits(_WIRE_317, 19, 19) connect _WIRE_316.ae_ptw, _T_4297 node _T_4298 = bits(_WIRE_317, 20, 20) connect _WIRE_316.g, _T_4298 node _T_4299 = bits(_WIRE_317, 21, 21) connect _WIRE_316.u, _T_4299 node _T_4300 = bits(_WIRE_317, 41, 22) connect _WIRE_316.ppn, _T_4300 node _T_4301 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4301 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_4302 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4302 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_4303 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4303 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_4304 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4304 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) wire _WIRE_318 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_319 : UInt<42> connect _WIRE_319, sectored_entries[0][4].data[0] node _T_4305 = bits(_WIRE_319, 0, 0) connect _WIRE_318.fragmented_superpage, _T_4305 node _T_4306 = bits(_WIRE_319, 1, 1) connect _WIRE_318.c, _T_4306 node _T_4307 = bits(_WIRE_319, 2, 2) connect _WIRE_318.eff, _T_4307 node _T_4308 = bits(_WIRE_319, 3, 3) connect _WIRE_318.paa, _T_4308 node _T_4309 = bits(_WIRE_319, 4, 4) connect _WIRE_318.pal, _T_4309 node _T_4310 = bits(_WIRE_319, 5, 5) connect _WIRE_318.ppp, _T_4310 node _T_4311 = bits(_WIRE_319, 6, 6) connect _WIRE_318.pr, _T_4311 node _T_4312 = bits(_WIRE_319, 7, 7) connect _WIRE_318.px, _T_4312 node _T_4313 = bits(_WIRE_319, 8, 8) connect _WIRE_318.pw, _T_4313 node _T_4314 = bits(_WIRE_319, 9, 9) connect _WIRE_318.hr, _T_4314 node _T_4315 = bits(_WIRE_319, 10, 10) connect _WIRE_318.hx, _T_4315 node _T_4316 = bits(_WIRE_319, 11, 11) connect _WIRE_318.hw, _T_4316 node _T_4317 = bits(_WIRE_319, 12, 12) connect _WIRE_318.sr, _T_4317 node _T_4318 = bits(_WIRE_319, 13, 13) connect _WIRE_318.sx, _T_4318 node _T_4319 = bits(_WIRE_319, 14, 14) connect _WIRE_318.sw, _T_4319 node _T_4320 = bits(_WIRE_319, 15, 15) connect _WIRE_318.gf, _T_4320 node _T_4321 = bits(_WIRE_319, 16, 16) connect _WIRE_318.pf, _T_4321 node _T_4322 = bits(_WIRE_319, 17, 17) connect _WIRE_318.ae_stage2, _T_4322 node _T_4323 = bits(_WIRE_319, 18, 18) connect _WIRE_318.ae_final, _T_4323 node _T_4324 = bits(_WIRE_319, 19, 19) connect _WIRE_318.ae_ptw, _T_4324 node _T_4325 = bits(_WIRE_319, 20, 20) connect _WIRE_318.g, _T_4325 node _T_4326 = bits(_WIRE_319, 21, 21) connect _WIRE_318.u, _T_4326 node _T_4327 = bits(_WIRE_319, 41, 22) connect _WIRE_318.ppn, _T_4327 wire _WIRE_320 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_321 : UInt<42> connect _WIRE_321, sectored_entries[0][4].data[1] node _T_4328 = bits(_WIRE_321, 0, 0) connect _WIRE_320.fragmented_superpage, _T_4328 node _T_4329 = bits(_WIRE_321, 1, 1) connect _WIRE_320.c, _T_4329 node _T_4330 = bits(_WIRE_321, 2, 2) connect _WIRE_320.eff, _T_4330 node _T_4331 = bits(_WIRE_321, 3, 3) connect _WIRE_320.paa, _T_4331 node _T_4332 = bits(_WIRE_321, 4, 4) connect _WIRE_320.pal, _T_4332 node _T_4333 = bits(_WIRE_321, 5, 5) connect _WIRE_320.ppp, _T_4333 node _T_4334 = bits(_WIRE_321, 6, 6) connect _WIRE_320.pr, _T_4334 node _T_4335 = bits(_WIRE_321, 7, 7) connect _WIRE_320.px, _T_4335 node _T_4336 = bits(_WIRE_321, 8, 8) connect _WIRE_320.pw, _T_4336 node _T_4337 = bits(_WIRE_321, 9, 9) connect _WIRE_320.hr, _T_4337 node _T_4338 = bits(_WIRE_321, 10, 10) connect _WIRE_320.hx, _T_4338 node _T_4339 = bits(_WIRE_321, 11, 11) connect _WIRE_320.hw, _T_4339 node _T_4340 = bits(_WIRE_321, 12, 12) connect _WIRE_320.sr, _T_4340 node _T_4341 = bits(_WIRE_321, 13, 13) connect _WIRE_320.sx, _T_4341 node _T_4342 = bits(_WIRE_321, 14, 14) connect _WIRE_320.sw, _T_4342 node _T_4343 = bits(_WIRE_321, 15, 15) connect _WIRE_320.gf, _T_4343 node _T_4344 = bits(_WIRE_321, 16, 16) connect _WIRE_320.pf, _T_4344 node _T_4345 = bits(_WIRE_321, 17, 17) connect _WIRE_320.ae_stage2, _T_4345 node _T_4346 = bits(_WIRE_321, 18, 18) connect _WIRE_320.ae_final, _T_4346 node _T_4347 = bits(_WIRE_321, 19, 19) connect _WIRE_320.ae_ptw, _T_4347 node _T_4348 = bits(_WIRE_321, 20, 20) connect _WIRE_320.g, _T_4348 node _T_4349 = bits(_WIRE_321, 21, 21) connect _WIRE_320.u, _T_4349 node _T_4350 = bits(_WIRE_321, 41, 22) connect _WIRE_320.ppn, _T_4350 wire _WIRE_322 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_323 : UInt<42> connect _WIRE_323, sectored_entries[0][4].data[2] node _T_4351 = bits(_WIRE_323, 0, 0) connect _WIRE_322.fragmented_superpage, _T_4351 node _T_4352 = bits(_WIRE_323, 1, 1) connect _WIRE_322.c, _T_4352 node _T_4353 = bits(_WIRE_323, 2, 2) connect _WIRE_322.eff, _T_4353 node _T_4354 = bits(_WIRE_323, 3, 3) connect _WIRE_322.paa, _T_4354 node _T_4355 = bits(_WIRE_323, 4, 4) connect _WIRE_322.pal, _T_4355 node _T_4356 = bits(_WIRE_323, 5, 5) connect _WIRE_322.ppp, _T_4356 node _T_4357 = bits(_WIRE_323, 6, 6) connect _WIRE_322.pr, _T_4357 node _T_4358 = bits(_WIRE_323, 7, 7) connect _WIRE_322.px, _T_4358 node _T_4359 = bits(_WIRE_323, 8, 8) connect _WIRE_322.pw, _T_4359 node _T_4360 = bits(_WIRE_323, 9, 9) connect _WIRE_322.hr, _T_4360 node _T_4361 = bits(_WIRE_323, 10, 10) connect _WIRE_322.hx, _T_4361 node _T_4362 = bits(_WIRE_323, 11, 11) connect _WIRE_322.hw, _T_4362 node _T_4363 = bits(_WIRE_323, 12, 12) connect _WIRE_322.sr, _T_4363 node _T_4364 = bits(_WIRE_323, 13, 13) connect _WIRE_322.sx, _T_4364 node _T_4365 = bits(_WIRE_323, 14, 14) connect _WIRE_322.sw, _T_4365 node _T_4366 = bits(_WIRE_323, 15, 15) connect _WIRE_322.gf, _T_4366 node _T_4367 = bits(_WIRE_323, 16, 16) connect _WIRE_322.pf, _T_4367 node _T_4368 = bits(_WIRE_323, 17, 17) connect _WIRE_322.ae_stage2, _T_4368 node _T_4369 = bits(_WIRE_323, 18, 18) connect _WIRE_322.ae_final, _T_4369 node _T_4370 = bits(_WIRE_323, 19, 19) connect _WIRE_322.ae_ptw, _T_4370 node _T_4371 = bits(_WIRE_323, 20, 20) connect _WIRE_322.g, _T_4371 node _T_4372 = bits(_WIRE_323, 21, 21) connect _WIRE_322.u, _T_4372 node _T_4373 = bits(_WIRE_323, 41, 22) connect _WIRE_322.ppn, _T_4373 wire _WIRE_324 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_325 : UInt<42> connect _WIRE_325, sectored_entries[0][4].data[3] node _T_4374 = bits(_WIRE_325, 0, 0) connect _WIRE_324.fragmented_superpage, _T_4374 node _T_4375 = bits(_WIRE_325, 1, 1) connect _WIRE_324.c, _T_4375 node _T_4376 = bits(_WIRE_325, 2, 2) connect _WIRE_324.eff, _T_4376 node _T_4377 = bits(_WIRE_325, 3, 3) connect _WIRE_324.paa, _T_4377 node _T_4378 = bits(_WIRE_325, 4, 4) connect _WIRE_324.pal, _T_4378 node _T_4379 = bits(_WIRE_325, 5, 5) connect _WIRE_324.ppp, _T_4379 node _T_4380 = bits(_WIRE_325, 6, 6) connect _WIRE_324.pr, _T_4380 node _T_4381 = bits(_WIRE_325, 7, 7) connect _WIRE_324.px, _T_4381 node _T_4382 = bits(_WIRE_325, 8, 8) connect _WIRE_324.pw, _T_4382 node _T_4383 = bits(_WIRE_325, 9, 9) connect _WIRE_324.hr, _T_4383 node _T_4384 = bits(_WIRE_325, 10, 10) connect _WIRE_324.hx, _T_4384 node _T_4385 = bits(_WIRE_325, 11, 11) connect _WIRE_324.hw, _T_4385 node _T_4386 = bits(_WIRE_325, 12, 12) connect _WIRE_324.sr, _T_4386 node _T_4387 = bits(_WIRE_325, 13, 13) connect _WIRE_324.sx, _T_4387 node _T_4388 = bits(_WIRE_325, 14, 14) connect _WIRE_324.sw, _T_4388 node _T_4389 = bits(_WIRE_325, 15, 15) connect _WIRE_324.gf, _T_4389 node _T_4390 = bits(_WIRE_325, 16, 16) connect _WIRE_324.pf, _T_4390 node _T_4391 = bits(_WIRE_325, 17, 17) connect _WIRE_324.ae_stage2, _T_4391 node _T_4392 = bits(_WIRE_325, 18, 18) connect _WIRE_324.ae_final, _T_4392 node _T_4393 = bits(_WIRE_325, 19, 19) connect _WIRE_324.ae_ptw, _T_4393 node _T_4394 = bits(_WIRE_325, 20, 20) connect _WIRE_324.g, _T_4394 node _T_4395 = bits(_WIRE_325, 21, 21) connect _WIRE_324.u, _T_4395 node _T_4396 = bits(_WIRE_325, 41, 22) connect _WIRE_324.ppn, _T_4396 node _T_4397 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4397 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_4398 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4398 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_4399 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4399 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_4400 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4400 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) wire _WIRE_326 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_327 : UInt<42> connect _WIRE_327, sectored_entries[0][5].data[0] node _T_4401 = bits(_WIRE_327, 0, 0) connect _WIRE_326.fragmented_superpage, _T_4401 node _T_4402 = bits(_WIRE_327, 1, 1) connect _WIRE_326.c, _T_4402 node _T_4403 = bits(_WIRE_327, 2, 2) connect _WIRE_326.eff, _T_4403 node _T_4404 = bits(_WIRE_327, 3, 3) connect _WIRE_326.paa, _T_4404 node _T_4405 = bits(_WIRE_327, 4, 4) connect _WIRE_326.pal, _T_4405 node _T_4406 = bits(_WIRE_327, 5, 5) connect _WIRE_326.ppp, _T_4406 node _T_4407 = bits(_WIRE_327, 6, 6) connect _WIRE_326.pr, _T_4407 node _T_4408 = bits(_WIRE_327, 7, 7) connect _WIRE_326.px, _T_4408 node _T_4409 = bits(_WIRE_327, 8, 8) connect _WIRE_326.pw, _T_4409 node _T_4410 = bits(_WIRE_327, 9, 9) connect _WIRE_326.hr, _T_4410 node _T_4411 = bits(_WIRE_327, 10, 10) connect _WIRE_326.hx, _T_4411 node _T_4412 = bits(_WIRE_327, 11, 11) connect _WIRE_326.hw, _T_4412 node _T_4413 = bits(_WIRE_327, 12, 12) connect _WIRE_326.sr, _T_4413 node _T_4414 = bits(_WIRE_327, 13, 13) connect _WIRE_326.sx, _T_4414 node _T_4415 = bits(_WIRE_327, 14, 14) connect _WIRE_326.sw, _T_4415 node _T_4416 = bits(_WIRE_327, 15, 15) connect _WIRE_326.gf, _T_4416 node _T_4417 = bits(_WIRE_327, 16, 16) connect _WIRE_326.pf, _T_4417 node _T_4418 = bits(_WIRE_327, 17, 17) connect _WIRE_326.ae_stage2, _T_4418 node _T_4419 = bits(_WIRE_327, 18, 18) connect _WIRE_326.ae_final, _T_4419 node _T_4420 = bits(_WIRE_327, 19, 19) connect _WIRE_326.ae_ptw, _T_4420 node _T_4421 = bits(_WIRE_327, 20, 20) connect _WIRE_326.g, _T_4421 node _T_4422 = bits(_WIRE_327, 21, 21) connect _WIRE_326.u, _T_4422 node _T_4423 = bits(_WIRE_327, 41, 22) connect _WIRE_326.ppn, _T_4423 wire _WIRE_328 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_329 : UInt<42> connect _WIRE_329, sectored_entries[0][5].data[1] node _T_4424 = bits(_WIRE_329, 0, 0) connect _WIRE_328.fragmented_superpage, _T_4424 node _T_4425 = bits(_WIRE_329, 1, 1) connect _WIRE_328.c, _T_4425 node _T_4426 = bits(_WIRE_329, 2, 2) connect _WIRE_328.eff, _T_4426 node _T_4427 = bits(_WIRE_329, 3, 3) connect _WIRE_328.paa, _T_4427 node _T_4428 = bits(_WIRE_329, 4, 4) connect _WIRE_328.pal, _T_4428 node _T_4429 = bits(_WIRE_329, 5, 5) connect _WIRE_328.ppp, _T_4429 node _T_4430 = bits(_WIRE_329, 6, 6) connect _WIRE_328.pr, _T_4430 node _T_4431 = bits(_WIRE_329, 7, 7) connect _WIRE_328.px, _T_4431 node _T_4432 = bits(_WIRE_329, 8, 8) connect _WIRE_328.pw, _T_4432 node _T_4433 = bits(_WIRE_329, 9, 9) connect _WIRE_328.hr, _T_4433 node _T_4434 = bits(_WIRE_329, 10, 10) connect _WIRE_328.hx, _T_4434 node _T_4435 = bits(_WIRE_329, 11, 11) connect _WIRE_328.hw, _T_4435 node _T_4436 = bits(_WIRE_329, 12, 12) connect _WIRE_328.sr, _T_4436 node _T_4437 = bits(_WIRE_329, 13, 13) connect _WIRE_328.sx, _T_4437 node _T_4438 = bits(_WIRE_329, 14, 14) connect _WIRE_328.sw, _T_4438 node _T_4439 = bits(_WIRE_329, 15, 15) connect _WIRE_328.gf, _T_4439 node _T_4440 = bits(_WIRE_329, 16, 16) connect _WIRE_328.pf, _T_4440 node _T_4441 = bits(_WIRE_329, 17, 17) connect _WIRE_328.ae_stage2, _T_4441 node _T_4442 = bits(_WIRE_329, 18, 18) connect _WIRE_328.ae_final, _T_4442 node _T_4443 = bits(_WIRE_329, 19, 19) connect _WIRE_328.ae_ptw, _T_4443 node _T_4444 = bits(_WIRE_329, 20, 20) connect _WIRE_328.g, _T_4444 node _T_4445 = bits(_WIRE_329, 21, 21) connect _WIRE_328.u, _T_4445 node _T_4446 = bits(_WIRE_329, 41, 22) connect _WIRE_328.ppn, _T_4446 wire _WIRE_330 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_331 : UInt<42> connect _WIRE_331, sectored_entries[0][5].data[2] node _T_4447 = bits(_WIRE_331, 0, 0) connect _WIRE_330.fragmented_superpage, _T_4447 node _T_4448 = bits(_WIRE_331, 1, 1) connect _WIRE_330.c, _T_4448 node _T_4449 = bits(_WIRE_331, 2, 2) connect _WIRE_330.eff, _T_4449 node _T_4450 = bits(_WIRE_331, 3, 3) connect _WIRE_330.paa, _T_4450 node _T_4451 = bits(_WIRE_331, 4, 4) connect _WIRE_330.pal, _T_4451 node _T_4452 = bits(_WIRE_331, 5, 5) connect _WIRE_330.ppp, _T_4452 node _T_4453 = bits(_WIRE_331, 6, 6) connect _WIRE_330.pr, _T_4453 node _T_4454 = bits(_WIRE_331, 7, 7) connect _WIRE_330.px, _T_4454 node _T_4455 = bits(_WIRE_331, 8, 8) connect _WIRE_330.pw, _T_4455 node _T_4456 = bits(_WIRE_331, 9, 9) connect _WIRE_330.hr, _T_4456 node _T_4457 = bits(_WIRE_331, 10, 10) connect _WIRE_330.hx, _T_4457 node _T_4458 = bits(_WIRE_331, 11, 11) connect _WIRE_330.hw, _T_4458 node _T_4459 = bits(_WIRE_331, 12, 12) connect _WIRE_330.sr, _T_4459 node _T_4460 = bits(_WIRE_331, 13, 13) connect _WIRE_330.sx, _T_4460 node _T_4461 = bits(_WIRE_331, 14, 14) connect _WIRE_330.sw, _T_4461 node _T_4462 = bits(_WIRE_331, 15, 15) connect _WIRE_330.gf, _T_4462 node _T_4463 = bits(_WIRE_331, 16, 16) connect _WIRE_330.pf, _T_4463 node _T_4464 = bits(_WIRE_331, 17, 17) connect _WIRE_330.ae_stage2, _T_4464 node _T_4465 = bits(_WIRE_331, 18, 18) connect _WIRE_330.ae_final, _T_4465 node _T_4466 = bits(_WIRE_331, 19, 19) connect _WIRE_330.ae_ptw, _T_4466 node _T_4467 = bits(_WIRE_331, 20, 20) connect _WIRE_330.g, _T_4467 node _T_4468 = bits(_WIRE_331, 21, 21) connect _WIRE_330.u, _T_4468 node _T_4469 = bits(_WIRE_331, 41, 22) connect _WIRE_330.ppn, _T_4469 wire _WIRE_332 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_333 : UInt<42> connect _WIRE_333, sectored_entries[0][5].data[3] node _T_4470 = bits(_WIRE_333, 0, 0) connect _WIRE_332.fragmented_superpage, _T_4470 node _T_4471 = bits(_WIRE_333, 1, 1) connect _WIRE_332.c, _T_4471 node _T_4472 = bits(_WIRE_333, 2, 2) connect _WIRE_332.eff, _T_4472 node _T_4473 = bits(_WIRE_333, 3, 3) connect _WIRE_332.paa, _T_4473 node _T_4474 = bits(_WIRE_333, 4, 4) connect _WIRE_332.pal, _T_4474 node _T_4475 = bits(_WIRE_333, 5, 5) connect _WIRE_332.ppp, _T_4475 node _T_4476 = bits(_WIRE_333, 6, 6) connect _WIRE_332.pr, _T_4476 node _T_4477 = bits(_WIRE_333, 7, 7) connect _WIRE_332.px, _T_4477 node _T_4478 = bits(_WIRE_333, 8, 8) connect _WIRE_332.pw, _T_4478 node _T_4479 = bits(_WIRE_333, 9, 9) connect _WIRE_332.hr, _T_4479 node _T_4480 = bits(_WIRE_333, 10, 10) connect _WIRE_332.hx, _T_4480 node _T_4481 = bits(_WIRE_333, 11, 11) connect _WIRE_332.hw, _T_4481 node _T_4482 = bits(_WIRE_333, 12, 12) connect _WIRE_332.sr, _T_4482 node _T_4483 = bits(_WIRE_333, 13, 13) connect _WIRE_332.sx, _T_4483 node _T_4484 = bits(_WIRE_333, 14, 14) connect _WIRE_332.sw, _T_4484 node _T_4485 = bits(_WIRE_333, 15, 15) connect _WIRE_332.gf, _T_4485 node _T_4486 = bits(_WIRE_333, 16, 16) connect _WIRE_332.pf, _T_4486 node _T_4487 = bits(_WIRE_333, 17, 17) connect _WIRE_332.ae_stage2, _T_4487 node _T_4488 = bits(_WIRE_333, 18, 18) connect _WIRE_332.ae_final, _T_4488 node _T_4489 = bits(_WIRE_333, 19, 19) connect _WIRE_332.ae_ptw, _T_4489 node _T_4490 = bits(_WIRE_333, 20, 20) connect _WIRE_332.g, _T_4490 node _T_4491 = bits(_WIRE_333, 21, 21) connect _WIRE_332.u, _T_4491 node _T_4492 = bits(_WIRE_333, 41, 22) connect _WIRE_332.ppn, _T_4492 node _T_4493 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4493 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_4494 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4494 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_4495 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4495 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_4496 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4496 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) wire _WIRE_334 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_335 : UInt<42> connect _WIRE_335, sectored_entries[0][6].data[0] node _T_4497 = bits(_WIRE_335, 0, 0) connect _WIRE_334.fragmented_superpage, _T_4497 node _T_4498 = bits(_WIRE_335, 1, 1) connect _WIRE_334.c, _T_4498 node _T_4499 = bits(_WIRE_335, 2, 2) connect _WIRE_334.eff, _T_4499 node _T_4500 = bits(_WIRE_335, 3, 3) connect _WIRE_334.paa, _T_4500 node _T_4501 = bits(_WIRE_335, 4, 4) connect _WIRE_334.pal, _T_4501 node _T_4502 = bits(_WIRE_335, 5, 5) connect _WIRE_334.ppp, _T_4502 node _T_4503 = bits(_WIRE_335, 6, 6) connect _WIRE_334.pr, _T_4503 node _T_4504 = bits(_WIRE_335, 7, 7) connect _WIRE_334.px, _T_4504 node _T_4505 = bits(_WIRE_335, 8, 8) connect _WIRE_334.pw, _T_4505 node _T_4506 = bits(_WIRE_335, 9, 9) connect _WIRE_334.hr, _T_4506 node _T_4507 = bits(_WIRE_335, 10, 10) connect _WIRE_334.hx, _T_4507 node _T_4508 = bits(_WIRE_335, 11, 11) connect _WIRE_334.hw, _T_4508 node _T_4509 = bits(_WIRE_335, 12, 12) connect _WIRE_334.sr, _T_4509 node _T_4510 = bits(_WIRE_335, 13, 13) connect _WIRE_334.sx, _T_4510 node _T_4511 = bits(_WIRE_335, 14, 14) connect _WIRE_334.sw, _T_4511 node _T_4512 = bits(_WIRE_335, 15, 15) connect _WIRE_334.gf, _T_4512 node _T_4513 = bits(_WIRE_335, 16, 16) connect _WIRE_334.pf, _T_4513 node _T_4514 = bits(_WIRE_335, 17, 17) connect _WIRE_334.ae_stage2, _T_4514 node _T_4515 = bits(_WIRE_335, 18, 18) connect _WIRE_334.ae_final, _T_4515 node _T_4516 = bits(_WIRE_335, 19, 19) connect _WIRE_334.ae_ptw, _T_4516 node _T_4517 = bits(_WIRE_335, 20, 20) connect _WIRE_334.g, _T_4517 node _T_4518 = bits(_WIRE_335, 21, 21) connect _WIRE_334.u, _T_4518 node _T_4519 = bits(_WIRE_335, 41, 22) connect _WIRE_334.ppn, _T_4519 wire _WIRE_336 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_337 : UInt<42> connect _WIRE_337, sectored_entries[0][6].data[1] node _T_4520 = bits(_WIRE_337, 0, 0) connect _WIRE_336.fragmented_superpage, _T_4520 node _T_4521 = bits(_WIRE_337, 1, 1) connect _WIRE_336.c, _T_4521 node _T_4522 = bits(_WIRE_337, 2, 2) connect _WIRE_336.eff, _T_4522 node _T_4523 = bits(_WIRE_337, 3, 3) connect _WIRE_336.paa, _T_4523 node _T_4524 = bits(_WIRE_337, 4, 4) connect _WIRE_336.pal, _T_4524 node _T_4525 = bits(_WIRE_337, 5, 5) connect _WIRE_336.ppp, _T_4525 node _T_4526 = bits(_WIRE_337, 6, 6) connect _WIRE_336.pr, _T_4526 node _T_4527 = bits(_WIRE_337, 7, 7) connect _WIRE_336.px, _T_4527 node _T_4528 = bits(_WIRE_337, 8, 8) connect _WIRE_336.pw, _T_4528 node _T_4529 = bits(_WIRE_337, 9, 9) connect _WIRE_336.hr, _T_4529 node _T_4530 = bits(_WIRE_337, 10, 10) connect _WIRE_336.hx, _T_4530 node _T_4531 = bits(_WIRE_337, 11, 11) connect _WIRE_336.hw, _T_4531 node _T_4532 = bits(_WIRE_337, 12, 12) connect _WIRE_336.sr, _T_4532 node _T_4533 = bits(_WIRE_337, 13, 13) connect _WIRE_336.sx, _T_4533 node _T_4534 = bits(_WIRE_337, 14, 14) connect _WIRE_336.sw, _T_4534 node _T_4535 = bits(_WIRE_337, 15, 15) connect _WIRE_336.gf, _T_4535 node _T_4536 = bits(_WIRE_337, 16, 16) connect _WIRE_336.pf, _T_4536 node _T_4537 = bits(_WIRE_337, 17, 17) connect _WIRE_336.ae_stage2, _T_4537 node _T_4538 = bits(_WIRE_337, 18, 18) connect _WIRE_336.ae_final, _T_4538 node _T_4539 = bits(_WIRE_337, 19, 19) connect _WIRE_336.ae_ptw, _T_4539 node _T_4540 = bits(_WIRE_337, 20, 20) connect _WIRE_336.g, _T_4540 node _T_4541 = bits(_WIRE_337, 21, 21) connect _WIRE_336.u, _T_4541 node _T_4542 = bits(_WIRE_337, 41, 22) connect _WIRE_336.ppn, _T_4542 wire _WIRE_338 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_339 : UInt<42> connect _WIRE_339, sectored_entries[0][6].data[2] node _T_4543 = bits(_WIRE_339, 0, 0) connect _WIRE_338.fragmented_superpage, _T_4543 node _T_4544 = bits(_WIRE_339, 1, 1) connect _WIRE_338.c, _T_4544 node _T_4545 = bits(_WIRE_339, 2, 2) connect _WIRE_338.eff, _T_4545 node _T_4546 = bits(_WIRE_339, 3, 3) connect _WIRE_338.paa, _T_4546 node _T_4547 = bits(_WIRE_339, 4, 4) connect _WIRE_338.pal, _T_4547 node _T_4548 = bits(_WIRE_339, 5, 5) connect _WIRE_338.ppp, _T_4548 node _T_4549 = bits(_WIRE_339, 6, 6) connect _WIRE_338.pr, _T_4549 node _T_4550 = bits(_WIRE_339, 7, 7) connect _WIRE_338.px, _T_4550 node _T_4551 = bits(_WIRE_339, 8, 8) connect _WIRE_338.pw, _T_4551 node _T_4552 = bits(_WIRE_339, 9, 9) connect _WIRE_338.hr, _T_4552 node _T_4553 = bits(_WIRE_339, 10, 10) connect _WIRE_338.hx, _T_4553 node _T_4554 = bits(_WIRE_339, 11, 11) connect _WIRE_338.hw, _T_4554 node _T_4555 = bits(_WIRE_339, 12, 12) connect _WIRE_338.sr, _T_4555 node _T_4556 = bits(_WIRE_339, 13, 13) connect _WIRE_338.sx, _T_4556 node _T_4557 = bits(_WIRE_339, 14, 14) connect _WIRE_338.sw, _T_4557 node _T_4558 = bits(_WIRE_339, 15, 15) connect _WIRE_338.gf, _T_4558 node _T_4559 = bits(_WIRE_339, 16, 16) connect _WIRE_338.pf, _T_4559 node _T_4560 = bits(_WIRE_339, 17, 17) connect _WIRE_338.ae_stage2, _T_4560 node _T_4561 = bits(_WIRE_339, 18, 18) connect _WIRE_338.ae_final, _T_4561 node _T_4562 = bits(_WIRE_339, 19, 19) connect _WIRE_338.ae_ptw, _T_4562 node _T_4563 = bits(_WIRE_339, 20, 20) connect _WIRE_338.g, _T_4563 node _T_4564 = bits(_WIRE_339, 21, 21) connect _WIRE_338.u, _T_4564 node _T_4565 = bits(_WIRE_339, 41, 22) connect _WIRE_338.ppn, _T_4565 wire _WIRE_340 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_341 : UInt<42> connect _WIRE_341, sectored_entries[0][6].data[3] node _T_4566 = bits(_WIRE_341, 0, 0) connect _WIRE_340.fragmented_superpage, _T_4566 node _T_4567 = bits(_WIRE_341, 1, 1) connect _WIRE_340.c, _T_4567 node _T_4568 = bits(_WIRE_341, 2, 2) connect _WIRE_340.eff, _T_4568 node _T_4569 = bits(_WIRE_341, 3, 3) connect _WIRE_340.paa, _T_4569 node _T_4570 = bits(_WIRE_341, 4, 4) connect _WIRE_340.pal, _T_4570 node _T_4571 = bits(_WIRE_341, 5, 5) connect _WIRE_340.ppp, _T_4571 node _T_4572 = bits(_WIRE_341, 6, 6) connect _WIRE_340.pr, _T_4572 node _T_4573 = bits(_WIRE_341, 7, 7) connect _WIRE_340.px, _T_4573 node _T_4574 = bits(_WIRE_341, 8, 8) connect _WIRE_340.pw, _T_4574 node _T_4575 = bits(_WIRE_341, 9, 9) connect _WIRE_340.hr, _T_4575 node _T_4576 = bits(_WIRE_341, 10, 10) connect _WIRE_340.hx, _T_4576 node _T_4577 = bits(_WIRE_341, 11, 11) connect _WIRE_340.hw, _T_4577 node _T_4578 = bits(_WIRE_341, 12, 12) connect _WIRE_340.sr, _T_4578 node _T_4579 = bits(_WIRE_341, 13, 13) connect _WIRE_340.sx, _T_4579 node _T_4580 = bits(_WIRE_341, 14, 14) connect _WIRE_340.sw, _T_4580 node _T_4581 = bits(_WIRE_341, 15, 15) connect _WIRE_340.gf, _T_4581 node _T_4582 = bits(_WIRE_341, 16, 16) connect _WIRE_340.pf, _T_4582 node _T_4583 = bits(_WIRE_341, 17, 17) connect _WIRE_340.ae_stage2, _T_4583 node _T_4584 = bits(_WIRE_341, 18, 18) connect _WIRE_340.ae_final, _T_4584 node _T_4585 = bits(_WIRE_341, 19, 19) connect _WIRE_340.ae_ptw, _T_4585 node _T_4586 = bits(_WIRE_341, 20, 20) connect _WIRE_340.g, _T_4586 node _T_4587 = bits(_WIRE_341, 21, 21) connect _WIRE_340.u, _T_4587 node _T_4588 = bits(_WIRE_341, 41, 22) connect _WIRE_340.ppn, _T_4588 node _T_4589 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4589 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_4590 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4590 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_4591 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4591 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_4592 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4592 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) wire _WIRE_342 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_343 : UInt<42> connect _WIRE_343, sectored_entries[0][7].data[0] node _T_4593 = bits(_WIRE_343, 0, 0) connect _WIRE_342.fragmented_superpage, _T_4593 node _T_4594 = bits(_WIRE_343, 1, 1) connect _WIRE_342.c, _T_4594 node _T_4595 = bits(_WIRE_343, 2, 2) connect _WIRE_342.eff, _T_4595 node _T_4596 = bits(_WIRE_343, 3, 3) connect _WIRE_342.paa, _T_4596 node _T_4597 = bits(_WIRE_343, 4, 4) connect _WIRE_342.pal, _T_4597 node _T_4598 = bits(_WIRE_343, 5, 5) connect _WIRE_342.ppp, _T_4598 node _T_4599 = bits(_WIRE_343, 6, 6) connect _WIRE_342.pr, _T_4599 node _T_4600 = bits(_WIRE_343, 7, 7) connect _WIRE_342.px, _T_4600 node _T_4601 = bits(_WIRE_343, 8, 8) connect _WIRE_342.pw, _T_4601 node _T_4602 = bits(_WIRE_343, 9, 9) connect _WIRE_342.hr, _T_4602 node _T_4603 = bits(_WIRE_343, 10, 10) connect _WIRE_342.hx, _T_4603 node _T_4604 = bits(_WIRE_343, 11, 11) connect _WIRE_342.hw, _T_4604 node _T_4605 = bits(_WIRE_343, 12, 12) connect _WIRE_342.sr, _T_4605 node _T_4606 = bits(_WIRE_343, 13, 13) connect _WIRE_342.sx, _T_4606 node _T_4607 = bits(_WIRE_343, 14, 14) connect _WIRE_342.sw, _T_4607 node _T_4608 = bits(_WIRE_343, 15, 15) connect _WIRE_342.gf, _T_4608 node _T_4609 = bits(_WIRE_343, 16, 16) connect _WIRE_342.pf, _T_4609 node _T_4610 = bits(_WIRE_343, 17, 17) connect _WIRE_342.ae_stage2, _T_4610 node _T_4611 = bits(_WIRE_343, 18, 18) connect _WIRE_342.ae_final, _T_4611 node _T_4612 = bits(_WIRE_343, 19, 19) connect _WIRE_342.ae_ptw, _T_4612 node _T_4613 = bits(_WIRE_343, 20, 20) connect _WIRE_342.g, _T_4613 node _T_4614 = bits(_WIRE_343, 21, 21) connect _WIRE_342.u, _T_4614 node _T_4615 = bits(_WIRE_343, 41, 22) connect _WIRE_342.ppn, _T_4615 wire _WIRE_344 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_345 : UInt<42> connect _WIRE_345, sectored_entries[0][7].data[1] node _T_4616 = bits(_WIRE_345, 0, 0) connect _WIRE_344.fragmented_superpage, _T_4616 node _T_4617 = bits(_WIRE_345, 1, 1) connect _WIRE_344.c, _T_4617 node _T_4618 = bits(_WIRE_345, 2, 2) connect _WIRE_344.eff, _T_4618 node _T_4619 = bits(_WIRE_345, 3, 3) connect _WIRE_344.paa, _T_4619 node _T_4620 = bits(_WIRE_345, 4, 4) connect _WIRE_344.pal, _T_4620 node _T_4621 = bits(_WIRE_345, 5, 5) connect _WIRE_344.ppp, _T_4621 node _T_4622 = bits(_WIRE_345, 6, 6) connect _WIRE_344.pr, _T_4622 node _T_4623 = bits(_WIRE_345, 7, 7) connect _WIRE_344.px, _T_4623 node _T_4624 = bits(_WIRE_345, 8, 8) connect _WIRE_344.pw, _T_4624 node _T_4625 = bits(_WIRE_345, 9, 9) connect _WIRE_344.hr, _T_4625 node _T_4626 = bits(_WIRE_345, 10, 10) connect _WIRE_344.hx, _T_4626 node _T_4627 = bits(_WIRE_345, 11, 11) connect _WIRE_344.hw, _T_4627 node _T_4628 = bits(_WIRE_345, 12, 12) connect _WIRE_344.sr, _T_4628 node _T_4629 = bits(_WIRE_345, 13, 13) connect _WIRE_344.sx, _T_4629 node _T_4630 = bits(_WIRE_345, 14, 14) connect _WIRE_344.sw, _T_4630 node _T_4631 = bits(_WIRE_345, 15, 15) connect _WIRE_344.gf, _T_4631 node _T_4632 = bits(_WIRE_345, 16, 16) connect _WIRE_344.pf, _T_4632 node _T_4633 = bits(_WIRE_345, 17, 17) connect _WIRE_344.ae_stage2, _T_4633 node _T_4634 = bits(_WIRE_345, 18, 18) connect _WIRE_344.ae_final, _T_4634 node _T_4635 = bits(_WIRE_345, 19, 19) connect _WIRE_344.ae_ptw, _T_4635 node _T_4636 = bits(_WIRE_345, 20, 20) connect _WIRE_344.g, _T_4636 node _T_4637 = bits(_WIRE_345, 21, 21) connect _WIRE_344.u, _T_4637 node _T_4638 = bits(_WIRE_345, 41, 22) connect _WIRE_344.ppn, _T_4638 wire _WIRE_346 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_347 : UInt<42> connect _WIRE_347, sectored_entries[0][7].data[2] node _T_4639 = bits(_WIRE_347, 0, 0) connect _WIRE_346.fragmented_superpage, _T_4639 node _T_4640 = bits(_WIRE_347, 1, 1) connect _WIRE_346.c, _T_4640 node _T_4641 = bits(_WIRE_347, 2, 2) connect _WIRE_346.eff, _T_4641 node _T_4642 = bits(_WIRE_347, 3, 3) connect _WIRE_346.paa, _T_4642 node _T_4643 = bits(_WIRE_347, 4, 4) connect _WIRE_346.pal, _T_4643 node _T_4644 = bits(_WIRE_347, 5, 5) connect _WIRE_346.ppp, _T_4644 node _T_4645 = bits(_WIRE_347, 6, 6) connect _WIRE_346.pr, _T_4645 node _T_4646 = bits(_WIRE_347, 7, 7) connect _WIRE_346.px, _T_4646 node _T_4647 = bits(_WIRE_347, 8, 8) connect _WIRE_346.pw, _T_4647 node _T_4648 = bits(_WIRE_347, 9, 9) connect _WIRE_346.hr, _T_4648 node _T_4649 = bits(_WIRE_347, 10, 10) connect _WIRE_346.hx, _T_4649 node _T_4650 = bits(_WIRE_347, 11, 11) connect _WIRE_346.hw, _T_4650 node _T_4651 = bits(_WIRE_347, 12, 12) connect _WIRE_346.sr, _T_4651 node _T_4652 = bits(_WIRE_347, 13, 13) connect _WIRE_346.sx, _T_4652 node _T_4653 = bits(_WIRE_347, 14, 14) connect _WIRE_346.sw, _T_4653 node _T_4654 = bits(_WIRE_347, 15, 15) connect _WIRE_346.gf, _T_4654 node _T_4655 = bits(_WIRE_347, 16, 16) connect _WIRE_346.pf, _T_4655 node _T_4656 = bits(_WIRE_347, 17, 17) connect _WIRE_346.ae_stage2, _T_4656 node _T_4657 = bits(_WIRE_347, 18, 18) connect _WIRE_346.ae_final, _T_4657 node _T_4658 = bits(_WIRE_347, 19, 19) connect _WIRE_346.ae_ptw, _T_4658 node _T_4659 = bits(_WIRE_347, 20, 20) connect _WIRE_346.g, _T_4659 node _T_4660 = bits(_WIRE_347, 21, 21) connect _WIRE_346.u, _T_4660 node _T_4661 = bits(_WIRE_347, 41, 22) connect _WIRE_346.ppn, _T_4661 wire _WIRE_348 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_349 : UInt<42> connect _WIRE_349, sectored_entries[0][7].data[3] node _T_4662 = bits(_WIRE_349, 0, 0) connect _WIRE_348.fragmented_superpage, _T_4662 node _T_4663 = bits(_WIRE_349, 1, 1) connect _WIRE_348.c, _T_4663 node _T_4664 = bits(_WIRE_349, 2, 2) connect _WIRE_348.eff, _T_4664 node _T_4665 = bits(_WIRE_349, 3, 3) connect _WIRE_348.paa, _T_4665 node _T_4666 = bits(_WIRE_349, 4, 4) connect _WIRE_348.pal, _T_4666 node _T_4667 = bits(_WIRE_349, 5, 5) connect _WIRE_348.ppp, _T_4667 node _T_4668 = bits(_WIRE_349, 6, 6) connect _WIRE_348.pr, _T_4668 node _T_4669 = bits(_WIRE_349, 7, 7) connect _WIRE_348.px, _T_4669 node _T_4670 = bits(_WIRE_349, 8, 8) connect _WIRE_348.pw, _T_4670 node _T_4671 = bits(_WIRE_349, 9, 9) connect _WIRE_348.hr, _T_4671 node _T_4672 = bits(_WIRE_349, 10, 10) connect _WIRE_348.hx, _T_4672 node _T_4673 = bits(_WIRE_349, 11, 11) connect _WIRE_348.hw, _T_4673 node _T_4674 = bits(_WIRE_349, 12, 12) connect _WIRE_348.sr, _T_4674 node _T_4675 = bits(_WIRE_349, 13, 13) connect _WIRE_348.sx, _T_4675 node _T_4676 = bits(_WIRE_349, 14, 14) connect _WIRE_348.sw, _T_4676 node _T_4677 = bits(_WIRE_349, 15, 15) connect _WIRE_348.gf, _T_4677 node _T_4678 = bits(_WIRE_349, 16, 16) connect _WIRE_348.pf, _T_4678 node _T_4679 = bits(_WIRE_349, 17, 17) connect _WIRE_348.ae_stage2, _T_4679 node _T_4680 = bits(_WIRE_349, 18, 18) connect _WIRE_348.ae_final, _T_4680 node _T_4681 = bits(_WIRE_349, 19, 19) connect _WIRE_348.ae_ptw, _T_4681 node _T_4682 = bits(_WIRE_349, 20, 20) connect _WIRE_348.g, _T_4682 node _T_4683 = bits(_WIRE_349, 21, 21) connect _WIRE_348.u, _T_4683 node _T_4684 = bits(_WIRE_349, 41, 22) connect _WIRE_348.ppn, _T_4684 node _T_4685 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4685 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_4686 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4686 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_4687 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4687 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_4688 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4688 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) wire _WIRE_350 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_351 : UInt<42> connect _WIRE_351, superpage_entries[0].data[0] node _T_4689 = bits(_WIRE_351, 0, 0) connect _WIRE_350.fragmented_superpage, _T_4689 node _T_4690 = bits(_WIRE_351, 1, 1) connect _WIRE_350.c, _T_4690 node _T_4691 = bits(_WIRE_351, 2, 2) connect _WIRE_350.eff, _T_4691 node _T_4692 = bits(_WIRE_351, 3, 3) connect _WIRE_350.paa, _T_4692 node _T_4693 = bits(_WIRE_351, 4, 4) connect _WIRE_350.pal, _T_4693 node _T_4694 = bits(_WIRE_351, 5, 5) connect _WIRE_350.ppp, _T_4694 node _T_4695 = bits(_WIRE_351, 6, 6) connect _WIRE_350.pr, _T_4695 node _T_4696 = bits(_WIRE_351, 7, 7) connect _WIRE_350.px, _T_4696 node _T_4697 = bits(_WIRE_351, 8, 8) connect _WIRE_350.pw, _T_4697 node _T_4698 = bits(_WIRE_351, 9, 9) connect _WIRE_350.hr, _T_4698 node _T_4699 = bits(_WIRE_351, 10, 10) connect _WIRE_350.hx, _T_4699 node _T_4700 = bits(_WIRE_351, 11, 11) connect _WIRE_350.hw, _T_4700 node _T_4701 = bits(_WIRE_351, 12, 12) connect _WIRE_350.sr, _T_4701 node _T_4702 = bits(_WIRE_351, 13, 13) connect _WIRE_350.sx, _T_4702 node _T_4703 = bits(_WIRE_351, 14, 14) connect _WIRE_350.sw, _T_4703 node _T_4704 = bits(_WIRE_351, 15, 15) connect _WIRE_350.gf, _T_4704 node _T_4705 = bits(_WIRE_351, 16, 16) connect _WIRE_350.pf, _T_4705 node _T_4706 = bits(_WIRE_351, 17, 17) connect _WIRE_350.ae_stage2, _T_4706 node _T_4707 = bits(_WIRE_351, 18, 18) connect _WIRE_350.ae_final, _T_4707 node _T_4708 = bits(_WIRE_351, 19, 19) connect _WIRE_350.ae_ptw, _T_4708 node _T_4709 = bits(_WIRE_351, 20, 20) connect _WIRE_350.g, _T_4709 node _T_4710 = bits(_WIRE_351, 21, 21) connect _WIRE_350.u, _T_4710 node _T_4711 = bits(_WIRE_351, 41, 22) connect _WIRE_350.ppn, _T_4711 node _T_4712 = eq(superpage_entries[0].tag_v, UInt<1>(0h1)) when _T_4712 : connect superpage_entries[0].valid[0], UInt<1>(0h0) wire _WIRE_352 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_353 : UInt<42> connect _WIRE_353, superpage_entries[1].data[0] node _T_4713 = bits(_WIRE_353, 0, 0) connect _WIRE_352.fragmented_superpage, _T_4713 node _T_4714 = bits(_WIRE_353, 1, 1) connect _WIRE_352.c, _T_4714 node _T_4715 = bits(_WIRE_353, 2, 2) connect _WIRE_352.eff, _T_4715 node _T_4716 = bits(_WIRE_353, 3, 3) connect _WIRE_352.paa, _T_4716 node _T_4717 = bits(_WIRE_353, 4, 4) connect _WIRE_352.pal, _T_4717 node _T_4718 = bits(_WIRE_353, 5, 5) connect _WIRE_352.ppp, _T_4718 node _T_4719 = bits(_WIRE_353, 6, 6) connect _WIRE_352.pr, _T_4719 node _T_4720 = bits(_WIRE_353, 7, 7) connect _WIRE_352.px, _T_4720 node _T_4721 = bits(_WIRE_353, 8, 8) connect _WIRE_352.pw, _T_4721 node _T_4722 = bits(_WIRE_353, 9, 9) connect _WIRE_352.hr, _T_4722 node _T_4723 = bits(_WIRE_353, 10, 10) connect _WIRE_352.hx, _T_4723 node _T_4724 = bits(_WIRE_353, 11, 11) connect _WIRE_352.hw, _T_4724 node _T_4725 = bits(_WIRE_353, 12, 12) connect _WIRE_352.sr, _T_4725 node _T_4726 = bits(_WIRE_353, 13, 13) connect _WIRE_352.sx, _T_4726 node _T_4727 = bits(_WIRE_353, 14, 14) connect _WIRE_352.sw, _T_4727 node _T_4728 = bits(_WIRE_353, 15, 15) connect _WIRE_352.gf, _T_4728 node _T_4729 = bits(_WIRE_353, 16, 16) connect _WIRE_352.pf, _T_4729 node _T_4730 = bits(_WIRE_353, 17, 17) connect _WIRE_352.ae_stage2, _T_4730 node _T_4731 = bits(_WIRE_353, 18, 18) connect _WIRE_352.ae_final, _T_4731 node _T_4732 = bits(_WIRE_353, 19, 19) connect _WIRE_352.ae_ptw, _T_4732 node _T_4733 = bits(_WIRE_353, 20, 20) connect _WIRE_352.g, _T_4733 node _T_4734 = bits(_WIRE_353, 21, 21) connect _WIRE_352.u, _T_4734 node _T_4735 = bits(_WIRE_353, 41, 22) connect _WIRE_352.ppn, _T_4735 node _T_4736 = eq(superpage_entries[1].tag_v, UInt<1>(0h1)) when _T_4736 : connect superpage_entries[1].valid[0], UInt<1>(0h0) wire _WIRE_354 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_355 : UInt<42> connect _WIRE_355, superpage_entries[2].data[0] node _T_4737 = bits(_WIRE_355, 0, 0) connect _WIRE_354.fragmented_superpage, _T_4737 node _T_4738 = bits(_WIRE_355, 1, 1) connect _WIRE_354.c, _T_4738 node _T_4739 = bits(_WIRE_355, 2, 2) connect _WIRE_354.eff, _T_4739 node _T_4740 = bits(_WIRE_355, 3, 3) connect _WIRE_354.paa, _T_4740 node _T_4741 = bits(_WIRE_355, 4, 4) connect _WIRE_354.pal, _T_4741 node _T_4742 = bits(_WIRE_355, 5, 5) connect _WIRE_354.ppp, _T_4742 node _T_4743 = bits(_WIRE_355, 6, 6) connect _WIRE_354.pr, _T_4743 node _T_4744 = bits(_WIRE_355, 7, 7) connect _WIRE_354.px, _T_4744 node _T_4745 = bits(_WIRE_355, 8, 8) connect _WIRE_354.pw, _T_4745 node _T_4746 = bits(_WIRE_355, 9, 9) connect _WIRE_354.hr, _T_4746 node _T_4747 = bits(_WIRE_355, 10, 10) connect _WIRE_354.hx, _T_4747 node _T_4748 = bits(_WIRE_355, 11, 11) connect _WIRE_354.hw, _T_4748 node _T_4749 = bits(_WIRE_355, 12, 12) connect _WIRE_354.sr, _T_4749 node _T_4750 = bits(_WIRE_355, 13, 13) connect _WIRE_354.sx, _T_4750 node _T_4751 = bits(_WIRE_355, 14, 14) connect _WIRE_354.sw, _T_4751 node _T_4752 = bits(_WIRE_355, 15, 15) connect _WIRE_354.gf, _T_4752 node _T_4753 = bits(_WIRE_355, 16, 16) connect _WIRE_354.pf, _T_4753 node _T_4754 = bits(_WIRE_355, 17, 17) connect _WIRE_354.ae_stage2, _T_4754 node _T_4755 = bits(_WIRE_355, 18, 18) connect _WIRE_354.ae_final, _T_4755 node _T_4756 = bits(_WIRE_355, 19, 19) connect _WIRE_354.ae_ptw, _T_4756 node _T_4757 = bits(_WIRE_355, 20, 20) connect _WIRE_354.g, _T_4757 node _T_4758 = bits(_WIRE_355, 21, 21) connect _WIRE_354.u, _T_4758 node _T_4759 = bits(_WIRE_355, 41, 22) connect _WIRE_354.ppn, _T_4759 node _T_4760 = eq(superpage_entries[2].tag_v, UInt<1>(0h1)) when _T_4760 : connect superpage_entries[2].valid[0], UInt<1>(0h0) wire _WIRE_356 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_357 : UInt<42> connect _WIRE_357, superpage_entries[3].data[0] node _T_4761 = bits(_WIRE_357, 0, 0) connect _WIRE_356.fragmented_superpage, _T_4761 node _T_4762 = bits(_WIRE_357, 1, 1) connect _WIRE_356.c, _T_4762 node _T_4763 = bits(_WIRE_357, 2, 2) connect _WIRE_356.eff, _T_4763 node _T_4764 = bits(_WIRE_357, 3, 3) connect _WIRE_356.paa, _T_4764 node _T_4765 = bits(_WIRE_357, 4, 4) connect _WIRE_356.pal, _T_4765 node _T_4766 = bits(_WIRE_357, 5, 5) connect _WIRE_356.ppp, _T_4766 node _T_4767 = bits(_WIRE_357, 6, 6) connect _WIRE_356.pr, _T_4767 node _T_4768 = bits(_WIRE_357, 7, 7) connect _WIRE_356.px, _T_4768 node _T_4769 = bits(_WIRE_357, 8, 8) connect _WIRE_356.pw, _T_4769 node _T_4770 = bits(_WIRE_357, 9, 9) connect _WIRE_356.hr, _T_4770 node _T_4771 = bits(_WIRE_357, 10, 10) connect _WIRE_356.hx, _T_4771 node _T_4772 = bits(_WIRE_357, 11, 11) connect _WIRE_356.hw, _T_4772 node _T_4773 = bits(_WIRE_357, 12, 12) connect _WIRE_356.sr, _T_4773 node _T_4774 = bits(_WIRE_357, 13, 13) connect _WIRE_356.sx, _T_4774 node _T_4775 = bits(_WIRE_357, 14, 14) connect _WIRE_356.sw, _T_4775 node _T_4776 = bits(_WIRE_357, 15, 15) connect _WIRE_356.gf, _T_4776 node _T_4777 = bits(_WIRE_357, 16, 16) connect _WIRE_356.pf, _T_4777 node _T_4778 = bits(_WIRE_357, 17, 17) connect _WIRE_356.ae_stage2, _T_4778 node _T_4779 = bits(_WIRE_357, 18, 18) connect _WIRE_356.ae_final, _T_4779 node _T_4780 = bits(_WIRE_357, 19, 19) connect _WIRE_356.ae_ptw, _T_4780 node _T_4781 = bits(_WIRE_357, 20, 20) connect _WIRE_356.g, _T_4781 node _T_4782 = bits(_WIRE_357, 21, 21) connect _WIRE_356.u, _T_4782 node _T_4783 = bits(_WIRE_357, 41, 22) connect _WIRE_356.ppn, _T_4783 node _T_4784 = eq(superpage_entries[3].tag_v, UInt<1>(0h1)) when _T_4784 : connect superpage_entries[3].valid[0], UInt<1>(0h0) wire _WIRE_358 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_359 : UInt<42> connect _WIRE_359, special_entry.data[0] node _T_4785 = bits(_WIRE_359, 0, 0) connect _WIRE_358.fragmented_superpage, _T_4785 node _T_4786 = bits(_WIRE_359, 1, 1) connect _WIRE_358.c, _T_4786 node _T_4787 = bits(_WIRE_359, 2, 2) connect _WIRE_358.eff, _T_4787 node _T_4788 = bits(_WIRE_359, 3, 3) connect _WIRE_358.paa, _T_4788 node _T_4789 = bits(_WIRE_359, 4, 4) connect _WIRE_358.pal, _T_4789 node _T_4790 = bits(_WIRE_359, 5, 5) connect _WIRE_358.ppp, _T_4790 node _T_4791 = bits(_WIRE_359, 6, 6) connect _WIRE_358.pr, _T_4791 node _T_4792 = bits(_WIRE_359, 7, 7) connect _WIRE_358.px, _T_4792 node _T_4793 = bits(_WIRE_359, 8, 8) connect _WIRE_358.pw, _T_4793 node _T_4794 = bits(_WIRE_359, 9, 9) connect _WIRE_358.hr, _T_4794 node _T_4795 = bits(_WIRE_359, 10, 10) connect _WIRE_358.hx, _T_4795 node _T_4796 = bits(_WIRE_359, 11, 11) connect _WIRE_358.hw, _T_4796 node _T_4797 = bits(_WIRE_359, 12, 12) connect _WIRE_358.sr, _T_4797 node _T_4798 = bits(_WIRE_359, 13, 13) connect _WIRE_358.sx, _T_4798 node _T_4799 = bits(_WIRE_359, 14, 14) connect _WIRE_358.sw, _T_4799 node _T_4800 = bits(_WIRE_359, 15, 15) connect _WIRE_358.gf, _T_4800 node _T_4801 = bits(_WIRE_359, 16, 16) connect _WIRE_358.pf, _T_4801 node _T_4802 = bits(_WIRE_359, 17, 17) connect _WIRE_358.ae_stage2, _T_4802 node _T_4803 = bits(_WIRE_359, 18, 18) connect _WIRE_358.ae_final, _T_4803 node _T_4804 = bits(_WIRE_359, 19, 19) connect _WIRE_358.ae_ptw, _T_4804 node _T_4805 = bits(_WIRE_359, 20, 20) connect _WIRE_358.g, _T_4805 node _T_4806 = bits(_WIRE_359, 21, 21) connect _WIRE_358.u, _T_4806 node _T_4807 = bits(_WIRE_359, 41, 22) connect _WIRE_358.ppn, _T_4807 node _T_4808 = eq(special_entry.tag_v, UInt<1>(0h1)) when _T_4808 : connect special_entry.valid[0], UInt<1>(0h0) connect v_entries_use_stage1, vstage1_en node _T_4809 = asUInt(reset) node _T_4810 = or(multipleHits, _T_4809) when _T_4810 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect superpage_entries[1].valid[0], UInt<1>(0h0) connect superpage_entries[2].valid[0], UInt<1>(0h0) connect superpage_entries[3].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0) node _T_4811 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_4812 = eq(io.ptw.req.ready, UInt<1>(0h0)) node _T_4813 = and(io.ptw.req.valid, _T_4812) node _T_4814 = eq(state, UInt<2>(0h3)) node _T_4815 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4816 = and(io.sfence.valid, _T_4815) node _T_4817 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4818 = and(_T_4816, _T_4817) node _T_4819 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4820 = and(io.sfence.valid, _T_4819) node _T_4821 = and(_T_4820, io.sfence.bits.rs2) node _T_4822 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4823 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4824 = and(_T_4822, _T_4823) node _T_4825 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4826 = and(_T_4825, io.sfence.bits.rs2)
module DTLB_8( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input io_req_bits_passthrough, // @[TLB.scala:320:14] input [1:0] io_req_bits_size, // @[TLB.scala:320:14] input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14] input [1:0] io_req_bits_prv, // @[TLB.scala:320:14] input io_req_bits_v, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] output [39:0] io_resp_gpa, // @[TLB.scala:320:14] output io_resp_pf_ld, // @[TLB.scala:320:14] output io_resp_pf_st, // @[TLB.scala:320:14] output io_resp_pf_inst, // @[TLB.scala:320:14] output io_resp_ae_ld, // @[TLB.scala:320:14] output io_resp_ae_st, // @[TLB.scala:320:14] output io_resp_ae_inst, // @[TLB.scala:320:14] output io_resp_ma_ld, // @[TLB.scala:320:14] output io_resp_ma_st, // @[TLB.scala:320:14] output io_resp_cacheable, // @[TLB.scala:320:14] output io_resp_must_alloc, // @[TLB.scala:320:14] output io_resp_prefetchable, // @[TLB.scala:320:14] output [1:0] io_resp_size, // @[TLB.scala:320:14] output [4:0] io_resp_cmd, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_sfence_bits_rs1, // @[TLB.scala:320:14] input io_sfence_bits_rs2, // @[TLB.scala:320:14] input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14] input io_sfence_bits_asid, // @[TLB.scala:320:14] input io_sfence_bits_hv, // @[TLB.scala:320:14] input io_sfence_bits_hg, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [15:0] io_ptw_ptbr_asid, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_status_zero2, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_mbe, // @[TLB.scala:320:14] input io_ptw_status_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_status_sxl, // @[TLB.scala:320:14] input [1:0] io_ptw_status_uxl, // @[TLB.scala:320:14] input io_ptw_status_sd_rv32, // @[TLB.scala:320:14] input [7:0] io_ptw_status_zero1, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_xs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_status_vs, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_ube, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_upie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_hie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_status_uie // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_8_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_7_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_6_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_5_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire io_req_bits_passthrough_0 = io_req_bits_passthrough; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7] wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7] wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7] wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7] wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7] wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7] wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [15:0] io_ptw_ptbr_asid_0 = io_ptw_ptbr_asid; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[TLB.scala:318:7] wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_v = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire cmd_lrsc = 1'h0; // @[TLB.scala:570:33] wire cmd_amo_logical = 1'h0; // @[TLB.scala:571:40] wire cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire ignore_6 = 1'h0; // @[TLB.scala:182:34] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire ignore_9 = 1'h0; // @[TLB.scala:182:34] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire ignore_12 = 1'h0; // @[TLB.scala:182:34] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire _homogeneous_T_71 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire ignore_5 = 1'h1; // @[TLB.scala:182:34] wire ignore_8 = 1'h1; // @[TLB.scala:182:34] wire ignore_11 = 1'h1; // @[TLB.scala:182:34] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[TLB.scala:318:7] wire [13:0] _ae_array_T_2 = 14'h0; // @[TLB.scala:583:8] wire [13:0] _ae_st_array_T_7 = 14'h0; // @[TLB.scala:590:8] wire [13:0] _ae_st_array_T_10 = 14'h0; // @[TLB.scala:591:8] wire [13:0] _must_alloc_array_T_3 = 14'h0; // @[TLB.scala:594:8] wire [13:0] _must_alloc_array_T_6 = 14'h0; // @[TLB.scala:595:8] wire [13:0] _must_alloc_array_T_9 = 14'h0; // @[TLB.scala:596:8] wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73] wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire _io_req_ready_T; // @[TLB.scala:631:25] wire [1:0] io_resp_size_0 = io_req_bits_size_0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd_0 = io_req_bits_cmd_0; // @[TLB.scala:318:7] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_ma_st_T; // @[TLB.scala:646:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [15:0] satp_asid = io_ptw_ptbr_asid_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld_0; // @[TLB.scala:318:7] wire io_resp_pf_st_0; // @[TLB.scala:318:7] wire io_resp_pf_inst_0; // @[TLB.scala:318:7] wire io_resp_ae_ld_0; // @[TLB.scala:318:7] wire io_resp_ae_st_0; // @[TLB.scala:318:7] wire io_resp_ae_inst_0; // @[TLB.scala:318:7] wire io_resp_ma_ld_0; // @[TLB.scala:318:7] wire io_resp_ma_st_0; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7] wire io_resp_cacheable_0; // @[TLB.scala:318:7] wire io_resp_must_alloc_0; // @[TLB.scala:318:7] wire io_resp_prefetchable_0; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_1_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_1_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_2_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_2_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_3_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_3_valid_0; // @[TLB.scala:341:30] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34] wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22] reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20] wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}] wire _vm_enabled_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64] wire vm_enabled = _vm_enabled_T_1 & _vm_enabled_T_2; // @[TLB.scala:399:{45,61,64}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire _vsatp_mode_mismatch_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64, :403:81] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_51 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_51; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_8; // @[TLB.scala:197:28] assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_13; // @[TLB.scala:182:28] assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_79 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T = do_refill | io_req_bits_passthrough_0; // @[TLB.scala:318:7, :408:29, :415:52] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_60 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_84; // @[Parameters.scala:137:31] assign _homogeneous_T_84 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_89; // @[Parameters.scala:137:31] assign _homogeneous_T_89 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_121; // @[Parameters.scala:137:31] assign _homogeneous_T_121 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_128; // @[Parameters.scala:137:31] assign _homogeneous_T_128 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:18], mpu_physaddr[17:0] ^ 18'h20000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFFC000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:18], mpu_physaddr[17:0] ^ 18'h24000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_30 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_40; // @[Parameters.scala:137:31] assign _homogeneous_T_40 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_94; // @[Parameters.scala:137:31] assign _homogeneous_T_94 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_45 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_50 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_51 = {1'h0, _homogeneous_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_52 = _homogeneous_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_53 = _homogeneous_T_52; // @[Parameters.scala:137:46] wire _homogeneous_T_54 = _homogeneous_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_55; // @[Parameters.scala:137:31] assign _homogeneous_T_55 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_99; // @[Parameters.scala:137:31] assign _homogeneous_T_99 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_114; // @[Parameters.scala:137:31] assign _homogeneous_T_114 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_56 = {1'h0, _homogeneous_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_57 = _homogeneous_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_58 = _homogeneous_T_57; // @[Parameters.scala:137:46] wire _homogeneous_T_59 = _homogeneous_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_61 = _homogeneous_T_60 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_62 = _homogeneous_T_61 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_63 = _homogeneous_T_62 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_64 = _homogeneous_T_63 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_65 = _homogeneous_T_64 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_66 = _homogeneous_T_65 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_67 = _homogeneous_T_66 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_68 = _homogeneous_T_67 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_69 = _homogeneous_T_68 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_70 = _homogeneous_T_69 | _homogeneous_T_54; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_70 | _homogeneous_T_59; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h8A130000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_77 = _homogeneous_T_76; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_78 = ~_homogeneous_T_77; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_80 = {1'h0, _homogeneous_T_79}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_81 = _homogeneous_T_80 & 41'hFFFF3000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_82 = _homogeneous_T_81; // @[Parameters.scala:137:46] wire _homogeneous_T_83 = _homogeneous_T_82 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_104 = _homogeneous_T_83; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_85 = {1'h0, _homogeneous_T_84}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_86 = _homogeneous_T_85 & 41'hFFFF3000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_87 = _homogeneous_T_86; // @[Parameters.scala:137:46] wire _homogeneous_T_88 = _homogeneous_T_87 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_90 = {1'h0, _homogeneous_T_89}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_91 = _homogeneous_T_90 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_92 = _homogeneous_T_91; // @[Parameters.scala:137:46] wire _homogeneous_T_93 = _homogeneous_T_92 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_95 = {1'h0, _homogeneous_T_94}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_96 = _homogeneous_T_95 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_97 = _homogeneous_T_96; // @[Parameters.scala:137:46] wire _homogeneous_T_98 = _homogeneous_T_97 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_100 = {1'h0, _homogeneous_T_99}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_101 = _homogeneous_T_100 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_102 = _homogeneous_T_101; // @[Parameters.scala:137:46] wire _homogeneous_T_103 = _homogeneous_T_102 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_105 = _homogeneous_T_104 | _homogeneous_T_88; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_106 = _homogeneous_T_105 | _homogeneous_T_93; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_107 = _homogeneous_T_106 | _homogeneous_T_98; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_103; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8E020000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_119 = _homogeneous_T_113; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_115 = {1'h0, _homogeneous_T_114}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_116 = _homogeneous_T_115 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_117 = _homogeneous_T_116; // @[Parameters.scala:137:46] wire _homogeneous_T_118 = _homogeneous_T_117 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_120 = _homogeneous_T_119 | _homogeneous_T_118; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_122 = {1'h0, _homogeneous_T_121}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_123 = _homogeneous_T_122 & 41'h8A130000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_124 = _homogeneous_T_123; // @[Parameters.scala:137:46] wire _homogeneous_T_125 = _homogeneous_T_124 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_126 = _homogeneous_T_125; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_127 = ~_homogeneous_T_126; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_129 = {1'h0, _homogeneous_T_128}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_130 = _homogeneous_T_129 & 41'h8A130000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_131 = _homogeneous_T_130; // @[Parameters.scala:137:46] wire _homogeneous_T_132 = _homogeneous_T_131 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_133 = _homogeneous_T_132; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_134 = ~_homogeneous_T_133; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1; // @[TLB.scala:429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1; // @[TLB.scala:430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1; // @[TLB.scala:434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire _GEN_4 = sectored_entries_0_0_valid_0 | sectored_entries_0_0_valid_1; // @[package.scala:81:59] wire _sector_hits_T; // @[package.scala:81:59] assign _sector_hits_T = _GEN_4; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59] wire _sector_hits_T_1 = _sector_hits_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _sector_hits_T_2 = _sector_hits_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61] assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _T_176; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59] wire _GEN_5 = sectored_entries_0_1_valid_0 | sectored_entries_0_1_valid_1; // @[package.scala:81:59] wire _sector_hits_T_8; // @[package.scala:81:59] assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59] wire _sector_hits_T_9 = _sector_hits_T_8 | sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _sector_hits_T_10 = _sector_hits_T_9 | sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61] assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59] wire _GEN_6 = sectored_entries_0_2_valid_0 | sectored_entries_0_2_valid_1; // @[package.scala:81:59] wire _sector_hits_T_16; // @[package.scala:81:59] assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59] wire _sector_hits_T_17 = _sector_hits_T_16 | sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _sector_hits_T_18 = _sector_hits_T_17 | sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61] assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59] wire _GEN_7 = sectored_entries_0_3_valid_0 | sectored_entries_0_3_valid_1; // @[package.scala:81:59] wire _sector_hits_T_24; // @[package.scala:81:59] assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59] wire _sector_hits_T_25 = _sector_hits_T_24 | sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _sector_hits_T_26 = _sector_hits_T_25 | sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61] assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59] wire _GEN_8 = sectored_entries_0_4_valid_0 | sectored_entries_0_4_valid_1; // @[package.scala:81:59] wire _sector_hits_T_32; // @[package.scala:81:59] assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59] wire _sector_hits_T_33 = _sector_hits_T_32 | sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _sector_hits_T_34 = _sector_hits_T_33 | sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61] assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61] assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59] wire _GEN_9 = sectored_entries_0_5_valid_0 | sectored_entries_0_5_valid_1; // @[package.scala:81:59] wire _sector_hits_T_40; // @[package.scala:81:59] assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59] wire _sector_hits_T_41 = _sector_hits_T_40 | sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _sector_hits_T_42 = _sector_hits_T_41 | sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61] assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61] assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59] wire _GEN_10 = sectored_entries_0_6_valid_0 | sectored_entries_0_6_valid_1; // @[package.scala:81:59] wire _sector_hits_T_48; // @[package.scala:81:59] assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59] wire _sector_hits_T_49 = _sector_hits_T_48 | sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _sector_hits_T_50 = _sector_hits_T_49 | sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61] assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61] assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59] wire _GEN_11 = sectored_entries_0_7_valid_0 | sectored_entries_0_7_valid_1; // @[package.scala:81:59] wire _sector_hits_T_56; // @[package.scala:81:59] assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59] wire _sector_hits_T_57 = _sector_hits_T_56 | sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _sector_hits_T_58 = _sector_hits_T_57 | sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61] assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61] assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52] assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52] assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52] assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52] assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52] assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52] assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52] assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52] assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52] assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_22 = superpage_hits_ignore_4 | _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}] wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52] assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52] assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52] assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52] assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52] assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52] assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _ppn_ignore_T_4; // @[TLB.scala:197:28] assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28] wire _ignore_T_7; // @[TLB.scala:182:28] assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_36 = superpage_hits_ignore_7 | _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}] wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52] assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52] assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52] assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52] assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52] assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52] assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _ppn_ignore_T_6; // @[TLB.scala:197:28] assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28] wire _ignore_T_10; // @[TLB.scala:182:28] assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_50 = superpage_hits_ignore_10 | _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}] wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}] wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13] wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13] wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13] wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13] wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13] wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_56 = hitsVec_ignore_1 | _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_71 = hitsVec_ignore_4 | _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_86 = hitsVec_ignore_7 | _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_101 = hitsVec_ignore_10 | _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52] assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52] assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52] assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_116 = hitsVec_ignore_13 | _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_121 = hitsVec_ignore_14 | _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}] wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27] wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27] wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27] wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27] wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_23; // @[TLB.scala:170:77] wire _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13] assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77] wire [19:0] _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] wire _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13] assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77] wire [19:0] _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] wire _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13] assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77] wire [19:0] _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] wire _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13] assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77] wire [19:0] _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] wire _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13] assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77] wire [19:0] _entries_T_143; // @[TLB.scala:170:77] wire _entries_T_142; // @[TLB.scala:170:77] wire _entries_T_141; // @[TLB.scala:170:77] wire _entries_T_140; // @[TLB.scala:170:77] wire _entries_T_139; // @[TLB.scala:170:77] wire _entries_T_138; // @[TLB.scala:170:77] wire _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13] assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77] assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77] assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77] assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77] assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77] assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77] assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77] wire [19:0] _entries_T_167; // @[TLB.scala:170:77] wire _entries_T_166; // @[TLB.scala:170:77] wire _entries_T_165; // @[TLB.scala:170:77] wire _entries_T_164; // @[TLB.scala:170:77] wire _entries_T_163; // @[TLB.scala:170:77] wire _entries_T_162; // @[TLB.scala:170:77] wire _entries_T_161; // @[TLB.scala:170:77] wire _entries_T_160; // @[TLB.scala:170:77] wire _entries_T_159; // @[TLB.scala:170:77] wire _entries_T_158; // @[TLB.scala:170:77] wire _entries_T_157; // @[TLB.scala:170:77] wire _entries_T_156; // @[TLB.scala:170:77] wire _entries_T_155; // @[TLB.scala:170:77] wire _entries_T_154; // @[TLB.scala:170:77] wire _entries_T_153; // @[TLB.scala:170:77] wire _entries_T_152; // @[TLB.scala:170:77] wire _entries_T_151; // @[TLB.scala:170:77] wire _entries_T_150; // @[TLB.scala:170:77] wire _entries_T_149; // @[TLB.scala:170:77] wire _entries_T_148; // @[TLB.scala:170:77] wire _entries_T_147; // @[TLB.scala:170:77] wire _entries_T_146; // @[TLB.scala:170:77] wire _entries_T_145; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13] assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77] wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77] assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77] wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77] assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77] wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77] assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77] wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77] assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77] assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77] assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77] assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77] wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77] assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77] assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77] assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77] assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77] assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77] assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77] assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77] assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77] wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77] assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77] assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77] assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77] assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77] assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77] wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77] assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77] wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77] assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77] wire [19:0] _entries_T_191; // @[TLB.scala:170:77] wire _entries_T_190; // @[TLB.scala:170:77] wire _entries_T_189; // @[TLB.scala:170:77] wire _entries_T_188; // @[TLB.scala:170:77] wire _entries_T_187; // @[TLB.scala:170:77] wire _entries_T_186; // @[TLB.scala:170:77] wire _entries_T_185; // @[TLB.scala:170:77] wire _entries_T_184; // @[TLB.scala:170:77] wire _entries_T_183; // @[TLB.scala:170:77] wire _entries_T_182; // @[TLB.scala:170:77] wire _entries_T_181; // @[TLB.scala:170:77] wire _entries_T_180; // @[TLB.scala:170:77] wire _entries_T_179; // @[TLB.scala:170:77] wire _entries_T_178; // @[TLB.scala:170:77] wire _entries_T_177; // @[TLB.scala:170:77] wire _entries_T_176; // @[TLB.scala:170:77] wire _entries_T_175; // @[TLB.scala:170:77] wire _entries_T_174; // @[TLB.scala:170:77] wire _entries_T_173; // @[TLB.scala:170:77] wire _entries_T_172; // @[TLB.scala:170:77] wire _entries_T_171; // @[TLB.scala:170:77] wire _entries_T_170; // @[TLB.scala:170:77] wire _entries_T_169; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13] assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77] wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77] assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77] wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77] assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77] wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77] assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77] wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77] assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77] assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77] assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77] assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77] wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77] assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77] assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77] assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77] assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77] assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77] assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77] assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77] assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77] wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77] assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77] assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77] assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77] assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77] assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77] wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77] assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77] wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77] assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77] wire [19:0] _entries_T_214; // @[TLB.scala:170:77] wire _entries_T_213; // @[TLB.scala:170:77] wire _entries_T_212; // @[TLB.scala:170:77] wire _entries_T_211; // @[TLB.scala:170:77] wire _entries_T_210; // @[TLB.scala:170:77] wire _entries_T_209; // @[TLB.scala:170:77] wire _entries_T_208; // @[TLB.scala:170:77] wire _entries_T_207; // @[TLB.scala:170:77] wire _entries_T_206; // @[TLB.scala:170:77] wire _entries_T_205; // @[TLB.scala:170:77] wire _entries_T_204; // @[TLB.scala:170:77] wire _entries_T_203; // @[TLB.scala:170:77] wire _entries_T_202; // @[TLB.scala:170:77] wire _entries_T_201; // @[TLB.scala:170:77] wire _entries_T_200; // @[TLB.scala:170:77] wire _entries_T_199; // @[TLB.scala:170:77] wire _entries_T_198; // @[TLB.scala:170:77] wire _entries_T_197; // @[TLB.scala:170:77] wire _entries_T_196; // @[TLB.scala:170:77] wire _entries_T_195; // @[TLB.scala:170:77] wire _entries_T_194; // @[TLB.scala:170:77] wire _entries_T_193; // @[TLB.scala:170:77] wire _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77] wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77] wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77] assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77] wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77] assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77] wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77] assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77] assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77] assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77] assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77] wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77] assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77] assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77] assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77] assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77] assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77] assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77] assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77] assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77] wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77] assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77] assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77] assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77] assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77] assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77] wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77] assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77] wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77] assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77] wire [19:0] _entries_T_237; // @[TLB.scala:170:77] wire _entries_T_236; // @[TLB.scala:170:77] wire _entries_T_235; // @[TLB.scala:170:77] wire _entries_T_234; // @[TLB.scala:170:77] wire _entries_T_233; // @[TLB.scala:170:77] wire _entries_T_232; // @[TLB.scala:170:77] wire _entries_T_231; // @[TLB.scala:170:77] wire _entries_T_230; // @[TLB.scala:170:77] wire _entries_T_229; // @[TLB.scala:170:77] wire _entries_T_228; // @[TLB.scala:170:77] wire _entries_T_227; // @[TLB.scala:170:77] wire _entries_T_226; // @[TLB.scala:170:77] wire _entries_T_225; // @[TLB.scala:170:77] wire _entries_T_224; // @[TLB.scala:170:77] wire _entries_T_223; // @[TLB.scala:170:77] wire _entries_T_222; // @[TLB.scala:170:77] wire _entries_T_221; // @[TLB.scala:170:77] wire _entries_T_220; // @[TLB.scala:170:77] wire _entries_T_219; // @[TLB.scala:170:77] wire _entries_T_218; // @[TLB.scala:170:77] wire _entries_T_217; // @[TLB.scala:170:77] wire _entries_T_216; // @[TLB.scala:170:77] wire _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77] wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77] wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77] assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77] wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77] assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77] wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77] assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77] assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77] assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77] assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77] wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77] assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77] assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77] assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77] assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77] assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77] assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77] assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77] assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77] wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77] assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77] assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77] assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77] assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77] assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77] wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77] assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77] wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77] assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77] wire [19:0] _entries_T_260; // @[TLB.scala:170:77] wire _entries_T_259; // @[TLB.scala:170:77] wire _entries_T_258; // @[TLB.scala:170:77] wire _entries_T_257; // @[TLB.scala:170:77] wire _entries_T_256; // @[TLB.scala:170:77] wire _entries_T_255; // @[TLB.scala:170:77] wire _entries_T_254; // @[TLB.scala:170:77] wire _entries_T_253; // @[TLB.scala:170:77] wire _entries_T_252; // @[TLB.scala:170:77] wire _entries_T_251; // @[TLB.scala:170:77] wire _entries_T_250; // @[TLB.scala:170:77] wire _entries_T_249; // @[TLB.scala:170:77] wire _entries_T_248; // @[TLB.scala:170:77] wire _entries_T_247; // @[TLB.scala:170:77] wire _entries_T_246; // @[TLB.scala:170:77] wire _entries_T_245; // @[TLB.scala:170:77] wire _entries_T_244; // @[TLB.scala:170:77] wire _entries_T_243; // @[TLB.scala:170:77] wire _entries_T_242; // @[TLB.scala:170:77] wire _entries_T_241; // @[TLB.scala:170:77] wire _entries_T_240; // @[TLB.scala:170:77] wire _entries_T_239; // @[TLB.scala:170:77] wire _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77] wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77] wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77] assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77] wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77] assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77] wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77] assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77] assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77] assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77] assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77] wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77] assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77] assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77] assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77] assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77] assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77] assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77] assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77] assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77] wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77] assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77] assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77] assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77] assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77] assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77] wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77] assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77] wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77] assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77] wire [19:0] _entries_T_283; // @[TLB.scala:170:77] wire _entries_T_282; // @[TLB.scala:170:77] wire _entries_T_281; // @[TLB.scala:170:77] wire _entries_T_280; // @[TLB.scala:170:77] wire _entries_T_279; // @[TLB.scala:170:77] wire _entries_T_278; // @[TLB.scala:170:77] wire _entries_T_277; // @[TLB.scala:170:77] wire _entries_T_276; // @[TLB.scala:170:77] wire _entries_T_275; // @[TLB.scala:170:77] wire _entries_T_274; // @[TLB.scala:170:77] wire _entries_T_273; // @[TLB.scala:170:77] wire _entries_T_272; // @[TLB.scala:170:77] wire _entries_T_271; // @[TLB.scala:170:77] wire _entries_T_270; // @[TLB.scala:170:77] wire _entries_T_269; // @[TLB.scala:170:77] wire _entries_T_268; // @[TLB.scala:170:77] wire _entries_T_267; // @[TLB.scala:170:77] wire _entries_T_266; // @[TLB.scala:170:77] wire _entries_T_265; // @[TLB.scala:170:77] wire _entries_T_264; // @[TLB.scala:170:77] wire _entries_T_263; // @[TLB.scala:170:77] wire _entries_T_262; // @[TLB.scala:170:77] wire _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77] wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77] wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77] assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77] wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77] assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77] wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77] assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77] assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77] assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77] assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77] wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77] assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77] assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77] assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77] assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77] assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77] assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77] assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77] assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77] wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77] assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77] assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77] assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77] assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77] assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77] wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77] assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77] wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77] assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77] wire [19:0] _entries_T_306; // @[TLB.scala:170:77] wire _entries_T_305; // @[TLB.scala:170:77] wire _entries_T_304; // @[TLB.scala:170:77] wire _entries_T_303; // @[TLB.scala:170:77] wire _entries_T_302; // @[TLB.scala:170:77] wire _entries_T_301; // @[TLB.scala:170:77] wire _entries_T_300; // @[TLB.scala:170:77] wire _entries_T_299; // @[TLB.scala:170:77] wire _entries_T_298; // @[TLB.scala:170:77] wire _entries_T_297; // @[TLB.scala:170:77] wire _entries_T_296; // @[TLB.scala:170:77] wire _entries_T_295; // @[TLB.scala:170:77] wire _entries_T_294; // @[TLB.scala:170:77] wire _entries_T_293; // @[TLB.scala:170:77] wire _entries_T_292; // @[TLB.scala:170:77] wire _entries_T_291; // @[TLB.scala:170:77] wire _entries_T_290; // @[TLB.scala:170:77] wire _entries_T_289; // @[TLB.scala:170:77] wire _entries_T_288; // @[TLB.scala:170:77] wire _entries_T_287; // @[TLB.scala:170:77] wire _entries_T_286; // @[TLB.scala:170:77] wire _entries_T_285; // @[TLB.scala:170:77] wire _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77] wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77] wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77] assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77] wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77] assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77] wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77] assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77] assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77] assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77] assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77] wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77] assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77] assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77] assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77] assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77] assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77] assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77] assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77] assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77] wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77] assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77] assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77] assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77] assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77] assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77] wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77] assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77] wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77] assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_56 = _ppn_T_42 | _ppn_T_43; // @[Mux.scala:30:73] wire [19:0] _ppn_T_57 = _ppn_T_56 | _ppn_T_44; // @[Mux.scala:30:73] wire [19:0] _ppn_T_58 = _ppn_T_57 | _ppn_T_45; // @[Mux.scala:30:73] wire [19:0] _ppn_T_59 = _ppn_T_58 | _ppn_T_46; // @[Mux.scala:30:73] wire [19:0] _ppn_T_60 = _ppn_T_59 | _ppn_T_47; // @[Mux.scala:30:73] wire [19:0] _ppn_T_61 = _ppn_T_60 | _ppn_T_48; // @[Mux.scala:30:73] wire [19:0] _ppn_T_62 = _ppn_T_61 | _ppn_T_49; // @[Mux.scala:30:73] wire [19:0] _ppn_T_63 = _ppn_T_62 | _ppn_T_50; // @[Mux.scala:30:73] wire [19:0] _ppn_T_64 = _ppn_T_63 | _ppn_T_51; // @[Mux.scala:30:73] wire [19:0] _ppn_T_65 = _ppn_T_64 | _ppn_T_52; // @[Mux.scala:30:73] wire [19:0] _ppn_T_66 = _ppn_T_65 | _ppn_T_53; // @[Mux.scala:30:73] wire [19:0] _ppn_T_67 = _ppn_T_66 | _ppn_T_54; // @[Mux.scala:30:73] wire [19:0] _ppn_T_68 = _ppn_T_67 | _ppn_T_55; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24] wire _priv_rw_ok_T_1 = _priv_rw_ok_T | sum; // @[TLB.scala:510:16, :513:{24,32}] wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 | _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27] wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27] assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27] wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27] wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27] assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27] wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27] assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27] wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27] assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27] wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27] assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27] assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27] wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27] wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27] wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27] wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27] assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27] wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27] assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27] wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27] wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27] assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27] wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27] assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27] wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27] wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_55 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104] wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104] wire [13:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104] wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27] assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27] assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27] assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [13:0] paa_array_if_cached = paa_array; // @[TLB.scala:541:22, :545:39] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [13:0] pal_array_if_cached = pal_array; // @[TLB.scala:543:22, :546:39] wire [13:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}] wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _GEN_60 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_60; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_60; // @[package.scala:16:47] wire _GEN_61 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_61; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_61; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_61; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire _GEN_62 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_62; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_62; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_62; // @[package.scala:16:47] wire _GEN_63 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_63; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_63; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_63; // @[package.scala:16:47] wire _GEN_64 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_64; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_64; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_64; // @[package.scala:16:47] wire _GEN_65 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_65; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_65; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_65; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T | _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 | _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 | _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire _GEN_66 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_66; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_66; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_66; // @[package.scala:16:47] wire _GEN_67 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_67; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_67; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_67; // @[package.scala:16:47] wire _GEN_68 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_68; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_68; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_68; // @[package.scala:16:47] wire _GEN_69 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_69; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_69; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_69; // @[package.scala:16:47] wire _GEN_70 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_70; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_70; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_70; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 | _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 | _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 | _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire _GEN_71 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41] wire cmd_put_partial; // @[TLB.scala:573:41] assign cmd_put_partial = _GEN_71; // @[TLB.scala:573:41] wire _cmd_write_T_1; // @[Consts.scala:90:49] assign _cmd_write_T_1 = _GEN_71; // @[TLB.scala:573:41] wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _GEN_72 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_1; // @[package.scala:16:47] assign _cmd_read_T_1 = _GEN_72; // @[package.scala:16:47] wire _cmd_readx_T; // @[TLB.scala:575:56] assign _cmd_readx_T = _GEN_72; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T | _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 | _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 | _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 | _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 | _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 | _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 | _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 | _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 | _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 | _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 | _cmd_read_T_22; // @[package.scala:81:59] wire cmd_read = _cmd_read_T_6 | _cmd_read_T_23; // @[package.scala:81:59] wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7] wire _cmd_write_T_2 = _cmd_write_T | _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 | _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 | _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 | _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 | _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 | _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 | _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 | _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 | _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 | _cmd_write_T_20; // @[package.scala:81:59] wire cmd_write = _cmd_write_T_4 | _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = _cmd_write_perms_T | _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire cmd_write_perms = cmd_write | _cmd_write_perms_T_2; // @[package.scala:81:59] wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] ae_array = _ae_array_T; // @[TLB.scala:582:{8,37}] wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}] wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [13:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [13:0] _ae_st_array_T_8 = _ae_st_array_T_5; // @[TLB.scala:588:53, :589:53] wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] ae_st_array = _ae_st_array_T_8; // @[TLB.scala:589:53, :590:53] wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [13:0] _must_alloc_array_T_4 = _must_alloc_array_T_1; // @[TLB.scala:593:{8,43}] wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] _must_alloc_array_T_7 = _must_alloc_array_T_4; // @[TLB.scala:593:43, :594:43] wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] must_alloc_array = _must_alloc_array_T_7; // @[TLB.scala:594:43, :595:46] wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}] wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27] wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [6:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_reg_1; // @[Replacement.scala:168:70] wire [1:0] _GEN_73 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_lo; // @[OneHot.scala:21:45] assign lo_lo = _GEN_73; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_lo = _GEN_73; // @[OneHot.scala:21:45] wire [1:0] _GEN_74 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] lo_hi; // @[OneHot.scala:21:45] assign lo_hi = _GEN_74; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_hi = _GEN_74; // @[OneHot.scala:21:45] wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45] wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_75 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45] wire [1:0] hi_lo; // @[OneHot.scala:21:45] assign hi_lo = _GEN_75; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_lo = _GEN_75; // @[OneHot.scala:21:45] wire [1:0] _GEN_76 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45] wire [1:0] hi_hi; // @[OneHot.scala:21:45] assign hi_hi = _GEN_76; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_hi = _GEN_76; // @[OneHot.scala:21:45] wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45] wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_vec_0_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13] wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17] wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17] wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13] wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13] wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13] wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13] wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38] wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13] wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13] wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16] wire [1:0] _GEN_77 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_3; // @[OneHot.scala:21:45] assign lo_3 = _GEN_77; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_lo = _GEN_77; // @[OneHot.scala:21:45] wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_78 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi_3; // @[OneHot.scala:21:45] assign hi_3 = _GEN_78; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_hi = _GEN_78; // @[OneHot.scala:21:45] wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_reg_touch_way_sized = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38] wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13] wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16] wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37] wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_8 | _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_17 | _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}] wire multipleHits_leftOne_5 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits_leftTwo_1 = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_6 = multipleHits_leftOne_7 | multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_8 = multipleHits_leftOne_6 | multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo_2 = _multipleHits_T_29 | _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}] wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39] wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39] wire multipleHits_leftOne_10 = multipleHits_leftOne_9 | multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61] wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}] wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39] wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_9 = multipleHits_leftOne_11 | multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}] wire multipleHits_rightOne_10 = multipleHits_leftOne_10 | multipleHits_rightOne_9; // @[Misc.scala:183:16] wire _multipleHits_T_42 = multipleHits_leftTwo_3 | multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_5 = _multipleHits_T_42 | _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}] wire multipleHits_rightOne_11 = multipleHits_leftOne_8 | multipleHits_rightOne_10; // @[Misc.scala:183:16] wire _multipleHits_T_44 = multipleHits_leftTwo_2 | multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_6 = _multipleHits_T_44 | _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_46 = multipleHits_leftOne_5 | multipleHits_rightOne_11; // @[Misc.scala:183:16] wire _multipleHits_T_47 = multipleHits_leftTwo_1 | multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_47 | _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28] wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28] wire [13:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64] wire _io_resp_pf_st_T_2 = |_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T | _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}] assign io_resp_pf_st_0 = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48] wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [13:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33] assign _io_resp_ae_st_T_1 = |_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign io_resp_ae_st_0 = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41] wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31] assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31] assign io_resp_ma_st_0 = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31] wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [13:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43] assign _io_resp_must_alloc_T_1 = |_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign io_resp_must_alloc_0 = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51] wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38] wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27] wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27] wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70] wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17] wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38] wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38] wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16] wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 | sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 | sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 | sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 | sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 | sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 | sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 | sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 | sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 | sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 | sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 | sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 | sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 | sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 | sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27] wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27] wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 | sector_hits_4; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 | sector_hits_5; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 | sector_hits_6; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 | sector_hits_7; // @[package.scala:81:59] wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45] wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18] wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sectored_hit_bits_T_3 = |r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 | r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}] wire _r_superpage_hit_valid_T = superpage_hits_0 | superpage_hits_1; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T | superpage_hits_2; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 | superpage_hits_3; // @[package.scala:81:59] wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_superpage_hit_bits_T_1 = |r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 | r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45]
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSink_TLBundleD_a29d64s7k1z3u : input clock : Clock input reset : Reset output io : { deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip async : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} wire source_ready : UInt<1> connect source_ready, UInt<1>(0h1) node _ridx_T = asAsyncReset(reset) node _ridx_T_1 = and(io.deq.ready, io.deq.valid) node _ridx_T_2 = eq(source_ready, UInt<1>(0h0)) wire ridx_incremented : UInt<4> regreset ridx_ridx_bin : UInt, clock, _ridx_T, UInt<1>(0h0) connect ridx_ridx_bin, ridx_incremented node _ridx_incremented_T = add(ridx_ridx_bin, _ridx_T_1) node _ridx_incremented_T_1 = tail(_ridx_incremented_T, 1) node _ridx_incremented_T_2 = mux(_ridx_T_2, UInt<1>(0h0), _ridx_incremented_T_1) connect ridx_incremented, _ridx_incremented_T_2 node _ridx_T_3 = shr(ridx_incremented, 1) node ridx = xor(ridx_incremented, _ridx_T_3) inst widx_widx_gray of AsyncResetSynchronizerShiftReg_w4_d3_i0_12 connect widx_widx_gray.clock, clock connect widx_widx_gray.reset, reset connect widx_widx_gray.io.d, io.async.widx wire widx : UInt<4> connect widx, widx_widx_gray.io.q node _valid_T = neq(ridx, widx) node valid = and(source_ready, _valid_T) node _index_T = bits(ridx, 2, 0) node _index_T_1 = bits(ridx, 3, 3) node _index_T_2 = shl(_index_T_1, 2) node index = xor(_index_T, _index_T_2) inst io_deq_bits_deq_bits_reg of ClockCrossingReg_w82 connect io_deq_bits_deq_bits_reg.clock, clock connect io_deq_bits_deq_bits_reg.reset, reset node io_deq_bits_deq_bits_reg_io_d_lo_lo = cat(io.async.mem[index].data, io.async.mem[index].corrupt) node io_deq_bits_deq_bits_reg_io_d_lo_hi_hi = cat(io.async.mem[index].denied, UInt<0>(0h0)) node io_deq_bits_deq_bits_reg_io_d_lo_hi = cat(io_deq_bits_deq_bits_reg_io_d_lo_hi_hi, UInt<0>(0h0)) node io_deq_bits_deq_bits_reg_io_d_lo = cat(io_deq_bits_deq_bits_reg_io_d_lo_hi, io_deq_bits_deq_bits_reg_io_d_lo_lo) node io_deq_bits_deq_bits_reg_io_d_hi_lo = cat(io.async.mem[index].source, io.async.mem[index].sink) node io_deq_bits_deq_bits_reg_io_d_hi_hi_hi = cat(io.async.mem[index].opcode, io.async.mem[index].param) node io_deq_bits_deq_bits_reg_io_d_hi_hi = cat(io_deq_bits_deq_bits_reg_io_d_hi_hi_hi, io.async.mem[index].size) node io_deq_bits_deq_bits_reg_io_d_hi = cat(io_deq_bits_deq_bits_reg_io_d_hi_hi, io_deq_bits_deq_bits_reg_io_d_hi_lo) node _io_deq_bits_deq_bits_reg_io_d_T = cat(io_deq_bits_deq_bits_reg_io_d_hi, io_deq_bits_deq_bits_reg_io_d_lo) connect io_deq_bits_deq_bits_reg.io.d, _io_deq_bits_deq_bits_reg_io_d_T connect io_deq_bits_deq_bits_reg.io.en, valid wire _io_deq_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} wire _io_deq_bits_WIRE_1 : UInt<82> connect _io_deq_bits_WIRE_1, io_deq_bits_deq_bits_reg.io.q node _io_deq_bits_T = bits(_io_deq_bits_WIRE_1, 0, 0) connect _io_deq_bits_WIRE.corrupt, _io_deq_bits_T node _io_deq_bits_T_1 = bits(_io_deq_bits_WIRE_1, 64, 1) connect _io_deq_bits_WIRE.data, _io_deq_bits_T_1 node _io_deq_bits_T_2 = bits(_io_deq_bits_WIRE_1, 65, 65) connect _io_deq_bits_WIRE.denied, _io_deq_bits_T_2 node _io_deq_bits_T_3 = bits(_io_deq_bits_WIRE_1, 66, 66) connect _io_deq_bits_WIRE.sink, _io_deq_bits_T_3 node _io_deq_bits_T_4 = bits(_io_deq_bits_WIRE_1, 73, 67) connect _io_deq_bits_WIRE.source, _io_deq_bits_T_4 node _io_deq_bits_T_5 = bits(_io_deq_bits_WIRE_1, 76, 74) connect _io_deq_bits_WIRE.size, _io_deq_bits_T_5 node _io_deq_bits_T_6 = bits(_io_deq_bits_WIRE_1, 78, 77) connect _io_deq_bits_WIRE.param, _io_deq_bits_T_6 node _io_deq_bits_T_7 = bits(_io_deq_bits_WIRE_1, 81, 79) connect _io_deq_bits_WIRE.opcode, _io_deq_bits_T_7 connect io.deq.bits, _io_deq_bits_WIRE node _valid_reg_T = asAsyncReset(reset) regreset valid_reg : UInt<1>, clock, _valid_reg_T, UInt<1>(0h0) connect valid_reg, valid node _io_deq_valid_T = and(valid_reg, source_ready) connect io.deq.valid, _io_deq_valid_T node _ridx_reg_T = asAsyncReset(reset) regreset ridx_gray : UInt, clock, _ridx_reg_T, UInt<1>(0h0) connect ridx_gray, ridx connect io.async.ridx, ridx_gray inst sink_valid_0 of AsyncValidSync_48 inst sink_valid_1 of AsyncValidSync_49 inst source_extend of AsyncValidSync_50 inst source_valid of AsyncValidSync_51 node _sink_valid_0_reset_T = asUInt(reset) node _sink_valid_0_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_0_reset_T_2 = or(_sink_valid_0_reset_T, _sink_valid_0_reset_T_1) node _sink_valid_0_reset_T_3 = asAsyncReset(_sink_valid_0_reset_T_2) connect sink_valid_0.reset, _sink_valid_0_reset_T_3 node _sink_valid_1_reset_T = asUInt(reset) node _sink_valid_1_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_1_reset_T_2 = or(_sink_valid_1_reset_T, _sink_valid_1_reset_T_1) node _sink_valid_1_reset_T_3 = asAsyncReset(_sink_valid_1_reset_T_2) connect sink_valid_1.reset, _sink_valid_1_reset_T_3 node _source_extend_reset_T = asUInt(reset) node _source_extend_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _source_extend_reset_T_2 = or(_source_extend_reset_T, _source_extend_reset_T_1) node _source_extend_reset_T_3 = asAsyncReset(_source_extend_reset_T_2) connect source_extend.reset, _source_extend_reset_T_3 node _source_valid_reset_T = asAsyncReset(reset) connect source_valid.reset, _source_valid_reset_T connect sink_valid_0.clock, clock connect sink_valid_1.clock, clock connect source_extend.clock, clock connect source_valid.clock, clock connect sink_valid_0.io.in, UInt<1>(0h1) connect sink_valid_1.io.in, sink_valid_0.io.out connect io.async.safe.ridx_valid, sink_valid_1.io.out connect source_extend.io.in, io.async.safe.widx_valid connect source_valid.io.in, source_extend.io.out connect source_ready, source_valid.io.out node _io_async_safe_sink_reset_n_T = asUInt(reset) node _io_async_safe_sink_reset_n_T_1 = eq(_io_async_safe_sink_reset_n_T, UInt<1>(0h0)) connect io.async.safe.sink_reset_n, _io_async_safe_sink_reset_n_T_1
module AsyncQueueSink_TLBundleD_a29d64s7k1z3u( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] input io_deq_ready, // @[AsyncQueue.scala:139:14] output io_deq_valid, // @[AsyncQueue.scala:139:14] output [2:0] io_deq_bits_opcode, // @[AsyncQueue.scala:139:14] output [1:0] io_deq_bits_param, // @[AsyncQueue.scala:139:14] output [2:0] io_deq_bits_size, // @[AsyncQueue.scala:139:14] output [6:0] io_deq_bits_source, // @[AsyncQueue.scala:139:14] output io_deq_bits_sink, // @[AsyncQueue.scala:139:14] output io_deq_bits_denied, // @[AsyncQueue.scala:139:14] output [63:0] io_deq_bits_data, // @[AsyncQueue.scala:139:14] output io_deq_bits_corrupt, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_0_opcode, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_0_param, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_0_size, // @[AsyncQueue.scala:139:14] input [6:0] io_async_mem_0_source, // @[AsyncQueue.scala:139:14] input io_async_mem_0_sink, // @[AsyncQueue.scala:139:14] input io_async_mem_0_denied, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_0_data, // @[AsyncQueue.scala:139:14] input io_async_mem_0_corrupt, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_1_opcode, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_1_param, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_1_size, // @[AsyncQueue.scala:139:14] input [6:0] io_async_mem_1_source, // @[AsyncQueue.scala:139:14] input io_async_mem_1_sink, // @[AsyncQueue.scala:139:14] input io_async_mem_1_denied, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_1_data, // @[AsyncQueue.scala:139:14] input io_async_mem_1_corrupt, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_2_opcode, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_2_param, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_2_size, // @[AsyncQueue.scala:139:14] input [6:0] io_async_mem_2_source, // @[AsyncQueue.scala:139:14] input io_async_mem_2_sink, // @[AsyncQueue.scala:139:14] input io_async_mem_2_denied, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_2_data, // @[AsyncQueue.scala:139:14] input io_async_mem_2_corrupt, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_3_opcode, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_3_param, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_3_size, // @[AsyncQueue.scala:139:14] input [6:0] io_async_mem_3_source, // @[AsyncQueue.scala:139:14] input io_async_mem_3_sink, // @[AsyncQueue.scala:139:14] input io_async_mem_3_denied, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_3_data, // @[AsyncQueue.scala:139:14] input io_async_mem_3_corrupt, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_4_opcode, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_4_param, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_4_size, // @[AsyncQueue.scala:139:14] input [6:0] io_async_mem_4_source, // @[AsyncQueue.scala:139:14] input io_async_mem_4_sink, // @[AsyncQueue.scala:139:14] input io_async_mem_4_denied, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_4_data, // @[AsyncQueue.scala:139:14] input io_async_mem_4_corrupt, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_5_opcode, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_5_param, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_5_size, // @[AsyncQueue.scala:139:14] input [6:0] io_async_mem_5_source, // @[AsyncQueue.scala:139:14] input io_async_mem_5_sink, // @[AsyncQueue.scala:139:14] input io_async_mem_5_denied, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_5_data, // @[AsyncQueue.scala:139:14] input io_async_mem_5_corrupt, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_6_opcode, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_6_param, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_6_size, // @[AsyncQueue.scala:139:14] input [6:0] io_async_mem_6_source, // @[AsyncQueue.scala:139:14] input io_async_mem_6_sink, // @[AsyncQueue.scala:139:14] input io_async_mem_6_denied, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_6_data, // @[AsyncQueue.scala:139:14] input io_async_mem_6_corrupt, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_7_opcode, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_7_param, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_7_size, // @[AsyncQueue.scala:139:14] input [6:0] io_async_mem_7_source, // @[AsyncQueue.scala:139:14] input io_async_mem_7_sink, // @[AsyncQueue.scala:139:14] input io_async_mem_7_denied, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_7_data, // @[AsyncQueue.scala:139:14] input io_async_mem_7_corrupt, // @[AsyncQueue.scala:139:14] output [3:0] io_async_ridx, // @[AsyncQueue.scala:139:14] input [3:0] io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_0_opcode_0 = io_async_mem_0_opcode; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_0_param_0 = io_async_mem_0_param; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_0_size_0 = io_async_mem_0_size; // @[AsyncQueue.scala:136:7] wire [6:0] io_async_mem_0_source_0 = io_async_mem_0_source; // @[AsyncQueue.scala:136:7] wire io_async_mem_0_sink_0 = io_async_mem_0_sink; // @[AsyncQueue.scala:136:7] wire io_async_mem_0_denied_0 = io_async_mem_0_denied; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_0_data_0 = io_async_mem_0_data; // @[AsyncQueue.scala:136:7] wire io_async_mem_0_corrupt_0 = io_async_mem_0_corrupt; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_1_opcode_0 = io_async_mem_1_opcode; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_1_param_0 = io_async_mem_1_param; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_1_size_0 = io_async_mem_1_size; // @[AsyncQueue.scala:136:7] wire [6:0] io_async_mem_1_source_0 = io_async_mem_1_source; // @[AsyncQueue.scala:136:7] wire io_async_mem_1_sink_0 = io_async_mem_1_sink; // @[AsyncQueue.scala:136:7] wire io_async_mem_1_denied_0 = io_async_mem_1_denied; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_1_data_0 = io_async_mem_1_data; // @[AsyncQueue.scala:136:7] wire io_async_mem_1_corrupt_0 = io_async_mem_1_corrupt; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_2_opcode_0 = io_async_mem_2_opcode; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_2_param_0 = io_async_mem_2_param; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_2_size_0 = io_async_mem_2_size; // @[AsyncQueue.scala:136:7] wire [6:0] io_async_mem_2_source_0 = io_async_mem_2_source; // @[AsyncQueue.scala:136:7] wire io_async_mem_2_sink_0 = io_async_mem_2_sink; // @[AsyncQueue.scala:136:7] wire io_async_mem_2_denied_0 = io_async_mem_2_denied; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_2_data_0 = io_async_mem_2_data; // @[AsyncQueue.scala:136:7] wire io_async_mem_2_corrupt_0 = io_async_mem_2_corrupt; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_3_opcode_0 = io_async_mem_3_opcode; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_3_param_0 = io_async_mem_3_param; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_3_size_0 = io_async_mem_3_size; // @[AsyncQueue.scala:136:7] wire [6:0] io_async_mem_3_source_0 = io_async_mem_3_source; // @[AsyncQueue.scala:136:7] wire io_async_mem_3_sink_0 = io_async_mem_3_sink; // @[AsyncQueue.scala:136:7] wire io_async_mem_3_denied_0 = io_async_mem_3_denied; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_3_data_0 = io_async_mem_3_data; // @[AsyncQueue.scala:136:7] wire io_async_mem_3_corrupt_0 = io_async_mem_3_corrupt; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_4_opcode_0 = io_async_mem_4_opcode; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_4_param_0 = io_async_mem_4_param; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_4_size_0 = io_async_mem_4_size; // @[AsyncQueue.scala:136:7] wire [6:0] io_async_mem_4_source_0 = io_async_mem_4_source; // @[AsyncQueue.scala:136:7] wire io_async_mem_4_sink_0 = io_async_mem_4_sink; // @[AsyncQueue.scala:136:7] wire io_async_mem_4_denied_0 = io_async_mem_4_denied; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_4_data_0 = io_async_mem_4_data; // @[AsyncQueue.scala:136:7] wire io_async_mem_4_corrupt_0 = io_async_mem_4_corrupt; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_5_opcode_0 = io_async_mem_5_opcode; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_5_param_0 = io_async_mem_5_param; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_5_size_0 = io_async_mem_5_size; // @[AsyncQueue.scala:136:7] wire [6:0] io_async_mem_5_source_0 = io_async_mem_5_source; // @[AsyncQueue.scala:136:7] wire io_async_mem_5_sink_0 = io_async_mem_5_sink; // @[AsyncQueue.scala:136:7] wire io_async_mem_5_denied_0 = io_async_mem_5_denied; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_5_data_0 = io_async_mem_5_data; // @[AsyncQueue.scala:136:7] wire io_async_mem_5_corrupt_0 = io_async_mem_5_corrupt; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_6_opcode_0 = io_async_mem_6_opcode; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_6_param_0 = io_async_mem_6_param; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_6_size_0 = io_async_mem_6_size; // @[AsyncQueue.scala:136:7] wire [6:0] io_async_mem_6_source_0 = io_async_mem_6_source; // @[AsyncQueue.scala:136:7] wire io_async_mem_6_sink_0 = io_async_mem_6_sink; // @[AsyncQueue.scala:136:7] wire io_async_mem_6_denied_0 = io_async_mem_6_denied; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_6_data_0 = io_async_mem_6_data; // @[AsyncQueue.scala:136:7] wire io_async_mem_6_corrupt_0 = io_async_mem_6_corrupt; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_7_opcode_0 = io_async_mem_7_opcode; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_7_param_0 = io_async_mem_7_param; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_7_size_0 = io_async_mem_7_size; // @[AsyncQueue.scala:136:7] wire [6:0] io_async_mem_7_source_0 = io_async_mem_7_source; // @[AsyncQueue.scala:136:7] wire io_async_mem_7_sink_0 = io_async_mem_7_sink; // @[AsyncQueue.scala:136:7] wire io_async_mem_7_denied_0 = io_async_mem_7_denied; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_7_data_0 = io_async_mem_7_data; // @[AsyncQueue.scala:136:7] wire io_async_mem_7_corrupt_0 = io_async_mem_7_corrupt; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_widx_0 = io_async_widx; // @[AsyncQueue.scala:136:7] wire io_async_safe_widx_valid_0 = io_async_safe_widx_valid; // @[AsyncQueue.scala:136:7] wire io_async_safe_source_reset_n_0 = io_async_safe_source_reset_n; // @[AsyncQueue.scala:136:7] wire _ridx_T = reset; // @[AsyncQueue.scala:148:30] wire _valid_reg_T = reset; // @[AsyncQueue.scala:165:35] wire _ridx_reg_T = reset; // @[AsyncQueue.scala:168:34] wire _sink_valid_0_reset_T = reset; // @[AsyncQueue.scala:177:35] wire _sink_valid_1_reset_T = reset; // @[AsyncQueue.scala:178:35] wire _source_extend_reset_T = reset; // @[AsyncQueue.scala:179:35] wire _source_valid_reset_T = reset; // @[AsyncQueue.scala:180:34] wire _io_async_safe_sink_reset_n_T = reset; // @[AsyncQueue.scala:193:32] wire _io_deq_valid_T; // @[AsyncQueue.scala:166:29] wire [2:0] _io_deq_bits_WIRE_opcode; // @[SynchronizerReg.scala:211:26] wire [1:0] _io_deq_bits_WIRE_param; // @[SynchronizerReg.scala:211:26] wire [2:0] _io_deq_bits_WIRE_size; // @[SynchronizerReg.scala:211:26] wire [6:0] _io_deq_bits_WIRE_source; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_WIRE_sink; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_WIRE_denied; // @[SynchronizerReg.scala:211:26] wire [63:0] _io_deq_bits_WIRE_data; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_WIRE_corrupt; // @[SynchronizerReg.scala:211:26] wire _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:193:25] wire [2:0] io_deq_bits_opcode_0; // @[AsyncQueue.scala:136:7] wire [1:0] io_deq_bits_param_0; // @[AsyncQueue.scala:136:7] wire [2:0] io_deq_bits_size_0; // @[AsyncQueue.scala:136:7] wire [6:0] io_deq_bits_source_0; // @[AsyncQueue.scala:136:7] wire io_deq_bits_sink_0; // @[AsyncQueue.scala:136:7] wire io_deq_bits_denied_0; // @[AsyncQueue.scala:136:7] wire [63:0] io_deq_bits_data_0; // @[AsyncQueue.scala:136:7] wire io_deq_bits_corrupt_0; // @[AsyncQueue.scala:136:7] wire io_deq_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_ridx_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_ridx_0; // @[AsyncQueue.scala:136:7] wire source_ready; // @[AsyncQueue.scala:147:30] wire _ridx_T_1 = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35] wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala:147:30, :148:77] wire [3:0] _ridx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] ridx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _ridx_incremented_T = {1'h0, ridx_ridx_bin} + {4'h0, _ridx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _ridx_incremented_T_1 = _ridx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _ridx_incremented_T_2 = _ridx_T_2 ? 4'h0 : _ridx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :148:77] assign ridx_incremented = _ridx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _ridx_T_3 = ridx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] ridx = {ridx_incremented[3], ridx_incremented[2:0] ^ _ridx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] widx; // @[ShiftReg.scala:48:24] wire _valid_T = ridx != widx; // @[ShiftReg.scala:48:24] wire valid = source_ready & _valid_T; // @[AsyncQueue.scala:147:30, :150:{28,36}] wire [2:0] _index_T = ridx[2:0]; // @[AsyncQueue.scala:54:17, :156:43] wire _index_T_1 = ridx[3]; // @[AsyncQueue.scala:54:17, :156:62] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:156:{62,75}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:156:{43,55,75}] wire [7:0][2:0] _GEN = {{io_async_mem_7_opcode_0}, {io_async_mem_6_opcode_0}, {io_async_mem_5_opcode_0}, {io_async_mem_4_opcode_0}, {io_async_mem_3_opcode_0}, {io_async_mem_2_opcode_0}, {io_async_mem_1_opcode_0}, {io_async_mem_0_opcode_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0][1:0] _GEN_0 = {{io_async_mem_7_param_0}, {io_async_mem_6_param_0}, {io_async_mem_5_param_0}, {io_async_mem_4_param_0}, {io_async_mem_3_param_0}, {io_async_mem_2_param_0}, {io_async_mem_1_param_0}, {io_async_mem_0_param_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0][2:0] _GEN_1 = {{io_async_mem_7_size_0}, {io_async_mem_6_size_0}, {io_async_mem_5_size_0}, {io_async_mem_4_size_0}, {io_async_mem_3_size_0}, {io_async_mem_2_size_0}, {io_async_mem_1_size_0}, {io_async_mem_0_size_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0][6:0] _GEN_2 = {{io_async_mem_7_source_0}, {io_async_mem_6_source_0}, {io_async_mem_5_source_0}, {io_async_mem_4_source_0}, {io_async_mem_3_source_0}, {io_async_mem_2_source_0}, {io_async_mem_1_source_0}, {io_async_mem_0_source_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0] _GEN_3 = {{io_async_mem_7_sink_0}, {io_async_mem_6_sink_0}, {io_async_mem_5_sink_0}, {io_async_mem_4_sink_0}, {io_async_mem_3_sink_0}, {io_async_mem_2_sink_0}, {io_async_mem_1_sink_0}, {io_async_mem_0_sink_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0] _GEN_4 = {{io_async_mem_7_denied_0}, {io_async_mem_6_denied_0}, {io_async_mem_5_denied_0}, {io_async_mem_4_denied_0}, {io_async_mem_3_denied_0}, {io_async_mem_2_denied_0}, {io_async_mem_1_denied_0}, {io_async_mem_0_denied_0}}; // @[SynchronizerReg.scala:209:24] wire io_deq_bits_deq_bits_reg_io_d_lo_hi_hi = _GEN_4[index]; // @[SynchronizerReg.scala:209:24] wire [7:0][63:0] _GEN_5 = {{io_async_mem_7_data_0}, {io_async_mem_6_data_0}, {io_async_mem_5_data_0}, {io_async_mem_4_data_0}, {io_async_mem_3_data_0}, {io_async_mem_2_data_0}, {io_async_mem_1_data_0}, {io_async_mem_0_data_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0] _GEN_6 = {{io_async_mem_7_corrupt_0}, {io_async_mem_6_corrupt_0}, {io_async_mem_5_corrupt_0}, {io_async_mem_4_corrupt_0}, {io_async_mem_3_corrupt_0}, {io_async_mem_2_corrupt_0}, {io_async_mem_1_corrupt_0}, {io_async_mem_0_corrupt_0}}; // @[SynchronizerReg.scala:209:24] wire [64:0] io_deq_bits_deq_bits_reg_io_d_lo_lo = {_GEN_5[index], _GEN_6[index]}; // @[SynchronizerReg.scala:209:24] wire io_deq_bits_deq_bits_reg_io_d_lo_hi = io_deq_bits_deq_bits_reg_io_d_lo_hi_hi; // @[SynchronizerReg.scala:209:24] wire [65:0] io_deq_bits_deq_bits_reg_io_d_lo = {io_deq_bits_deq_bits_reg_io_d_lo_hi, io_deq_bits_deq_bits_reg_io_d_lo_lo}; // @[SynchronizerReg.scala:209:24] wire [7:0] io_deq_bits_deq_bits_reg_io_d_hi_lo = {_GEN_2[index], _GEN_3[index]}; // @[SynchronizerReg.scala:209:24] wire [4:0] io_deq_bits_deq_bits_reg_io_d_hi_hi_hi = {_GEN[index], _GEN_0[index]}; // @[SynchronizerReg.scala:209:24] wire [7:0] io_deq_bits_deq_bits_reg_io_d_hi_hi = {io_deq_bits_deq_bits_reg_io_d_hi_hi_hi, _GEN_1[index]}; // @[SynchronizerReg.scala:209:24] wire [15:0] io_deq_bits_deq_bits_reg_io_d_hi = {io_deq_bits_deq_bits_reg_io_d_hi_hi, io_deq_bits_deq_bits_reg_io_d_hi_lo}; // @[SynchronizerReg.scala:209:24] wire [81:0] _io_deq_bits_deq_bits_reg_io_d_T = {io_deq_bits_deq_bits_reg_io_d_hi, io_deq_bits_deq_bits_reg_io_d_lo}; // @[SynchronizerReg.scala:209:24] wire [2:0] _io_deq_bits_T_7; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_opcode_0 = _io_deq_bits_WIRE_opcode; // @[SynchronizerReg.scala:211:26] wire [1:0] _io_deq_bits_T_6; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_param_0 = _io_deq_bits_WIRE_param; // @[SynchronizerReg.scala:211:26] wire [2:0] _io_deq_bits_T_5; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_size_0 = _io_deq_bits_WIRE_size; // @[SynchronizerReg.scala:211:26] wire [6:0] _io_deq_bits_T_4; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_source_0 = _io_deq_bits_WIRE_source; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_T_3; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_sink_0 = _io_deq_bits_WIRE_sink; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_T_2; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_denied_0 = _io_deq_bits_WIRE_denied; // @[SynchronizerReg.scala:211:26] wire [63:0] _io_deq_bits_T_1; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_data_0 = _io_deq_bits_WIRE_data; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_corrupt_0 = _io_deq_bits_WIRE_corrupt; // @[SynchronizerReg.scala:211:26] wire [81:0] _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T = _io_deq_bits_WIRE_1[0]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_corrupt = _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_1 = _io_deq_bits_WIRE_1[64:1]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_data = _io_deq_bits_T_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_2 = _io_deq_bits_WIRE_1[65]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_denied = _io_deq_bits_T_2; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_3 = _io_deq_bits_WIRE_1[66]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_sink = _io_deq_bits_T_3; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_4 = _io_deq_bits_WIRE_1[73:67]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_source = _io_deq_bits_T_4; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_5 = _io_deq_bits_WIRE_1[76:74]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_size = _io_deq_bits_T_5; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_6 = _io_deq_bits_WIRE_1[78:77]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_param = _io_deq_bits_T_6; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_7 = _io_deq_bits_WIRE_1[81:79]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_opcode = _io_deq_bits_T_7; // @[SynchronizerReg.scala:211:26] reg valid_reg; // @[AsyncQueue.scala:165:56] assign _io_deq_valid_T = valid_reg & source_ready; // @[AsyncQueue.scala:147:30, :165:56, :166:29] assign io_deq_valid_0 = _io_deq_valid_T; // @[AsyncQueue.scala:136:7, :166:29] reg [3:0] ridx_gray; // @[AsyncQueue.scala:168:55] assign io_async_ridx_0 = ridx_gray; // @[AsyncQueue.scala:136:7, :168:55] wire _sink_valid_0_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45] wire _sink_valid_0_reset_T_2 = _sink_valid_0_reset_T | _sink_valid_0_reset_T_1; // @[AsyncQueue.scala:177:{35,42,45}] wire _sink_valid_0_reset_T_3 = _sink_valid_0_reset_T_2; // @[AsyncQueue.scala:177:{42,66}] wire _sink_valid_1_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :178:45] wire _sink_valid_1_reset_T_2 = _sink_valid_1_reset_T | _sink_valid_1_reset_T_1; // @[AsyncQueue.scala:178:{35,42,45}] wire _sink_valid_1_reset_T_3 = _sink_valid_1_reset_T_2; // @[AsyncQueue.scala:178:{42,66}] wire _source_extend_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :179:45] wire _source_extend_reset_T_2 = _source_extend_reset_T | _source_extend_reset_T_1; // @[AsyncQueue.scala:179:{35,42,45}] wire _source_extend_reset_T_3 = _source_extend_reset_T_2; // @[AsyncQueue.scala:179:{42,66}] assign _io_async_safe_sink_reset_n_T_1 = ~_io_async_safe_sink_reset_n_T; // @[AsyncQueue.scala:193:{25,32}] assign io_async_safe_sink_reset_n_0 = _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:136:7, :193:25] always @(posedge clock or posedge _ridx_T) begin // @[AsyncQueue.scala:136:7, :148:30] if (_ridx_T) // @[AsyncQueue.scala:136:7, :148:30] ridx_ridx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _valid_reg_T) begin // @[AsyncQueue.scala:136:7, :165:35] if (_valid_reg_T) // @[AsyncQueue.scala:136:7, :165:35] valid_reg <= 1'h0; // @[AsyncQueue.scala:165:56] else // @[AsyncQueue.scala:136:7] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] always @(posedge, posedge) always @(posedge clock or posedge _ridx_reg_T) begin // @[AsyncQueue.scala:136:7, :168:34] if (_ridx_reg_T) // @[AsyncQueue.scala:136:7, :168:34] ridx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :168:55] else // @[AsyncQueue.scala:136:7] ridx_gray <= ridx; // @[AsyncQueue.scala:54:17, :168:55] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_115 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_195 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_115( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_195 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_53 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[2]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], debug : { va_stall : UInt<1>, sa_stall : UInt<1>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}} inst input_buffer of InputBuffer_53 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) inst route_arbiter of Arbiter2_RouteComputerReq_7 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<2>}[2], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_10 : connect states[1].g, UInt<3>(0h2) node _T_11 = and(io.router_req.ready, io.router_req.valid) when _T_11 : node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_12, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_16 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_17 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` regreset mask : UInt<2>, clock, reset, UInt<2>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}}[2] wire vcalloc_vals : UInt<1>[2] node _vcalloc_filter_T = cat(vcalloc_vals[1], vcalloc_vals[0]) node _vcalloc_filter_T_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = mux(_vcalloc_filter_T_8, UInt<4>(0h8), UInt<4>(0h0)) node _vcalloc_filter_T_10 = mux(_vcalloc_filter_T_7, UInt<4>(0h4), _vcalloc_filter_T_9) node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_6, UInt<4>(0h2), _vcalloc_filter_T_10) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<4>(0h1), _vcalloc_filter_T_11) node _vcalloc_sel_T = bits(vcalloc_filter, 1, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 2) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_18 = and(io.router_req.ready, io.router_req.valid) when _T_18 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_19 = or(vcalloc_vals[0], vcalloc_vals[1]) when _T_19 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = bits(vcalloc_sel, 0, 0) node _mask_T_6 = bits(vcalloc_sel, 1, 1) node _mask_T_7 = mux(_mask_T_5, _mask_T_3, UInt<1>(0h0)) node _mask_T_8 = mux(_mask_T_6, _mask_T_4, UInt<1>(0h0)) node _mask_T_9 = or(_mask_T_7, _mask_T_8) wire _mask_WIRE : UInt<2> connect _mask_WIRE, _mask_T_9 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}} wire _io_vcalloc_req_bits_WIRE_1 : { `1` : UInt<1>[1], `0` : UInt<1>[2]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[2] node _io_vcalloc_req_bits_T_2 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_4 = or(_io_vcalloc_req_bits_T_2, _io_vcalloc_req_bits_T_3) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_4 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_7 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>[1] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_10 connect _io_vcalloc_req_bits_WIRE_5[0], _io_vcalloc_req_bits_WIRE_6 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_5 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_12) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_13 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_7 wire _io_vcalloc_req_bits_WIRE_8 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_9 : UInt<2> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_16 connect _io_vcalloc_req_bits_WIRE_8.egress_node_id, _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18) wire _io_vcalloc_req_bits_WIRE_10 : UInt<4> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_19 connect _io_vcalloc_req_bits_WIRE_8.egress_node, _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_21) wire _io_vcalloc_req_bits_WIRE_11 : UInt<2> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_8.ingress_node_id, _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) wire _io_vcalloc_req_bits_WIRE_12 : UInt<4> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_25 connect _io_vcalloc_req_bits_WIRE_8.ingress_node, _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_27) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_28 connect _io_vcalloc_req_bits_WIRE_8.vnet_id, _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_8 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].flow, states[1].flow node _T_20 = bits(vcalloc_sel, 1, 1) node _T_21 = and(vcalloc_vals[1], _T_20) node _T_22 = and(_T_21, io.vcalloc_req.ready) when _T_22 : connect states[1].g, UInt<3>(0h3) node _T_23 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_23 : connect vcalloc_vals[1], UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, io.router_resp.vc_sel.`1` node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = sub(_io_debug_va_stall_T_1, io.vcalloc_req.ready) node _io_debug_va_stall_T_3 = tail(_io_debug_va_stall_T_2, 1) connect io.debug.va_stall, _io_debug_va_stall_T_3 node _T_24 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_24 : node _T_25 = bits(vcalloc_sel, 0, 0) when _T_25 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].g, UInt<3>(0h3) node _T_26 = bits(vcalloc_sel, 1, 1) when _T_26 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].g, UInt<3>(0h3) inst salloc_arb of SwitchArbiter_132 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] node _credit_available_T = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node _credit_available_T_1 = cat(states[1].vc_sel.`1`[0], _credit_available_T) node _credit_available_T_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node _credit_available_T_3 = cat(io.out_credit_available.`1`[0], _credit_available_T_2) node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3) node credit_available = neq(_credit_available_T_4, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_27 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_28 = and(_T_27, input_buffer.io.deq[1].bits.tail) when _T_28 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_5 = bits(_io_debug_sa_stall_T_4, 1, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_5 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) wire salloc_outs : { valid : UInt<1>, vid : UInt<1>, out_vid : UInt<1>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1] node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_5 = or(_io_in_vc_free_T_3, _io_in_vc_free_T_4) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_5 node _io_in_vc_free_T_6 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_6, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_7 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node _salloc_outs_0_vid_T = bits(salloc_arb.io.chosen_oh[0], 1, 1) connect salloc_outs[0].vid, _salloc_outs_0_vid_T node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) wire vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]} wire _vc_sel_WIRE : UInt<1>[2] node _vc_sel_T_2 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_3 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_4 = or(_vc_sel_T_2, _vc_sel_T_3) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_4 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_7 = or(_vc_sel_T_5, _vc_sel_T_6) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_7 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_3 : UInt<1>[1] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_10 = or(_vc_sel_T_8, _vc_sel_T_9) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_10 connect _vc_sel_WIRE_3[0], _vc_sel_WIRE_4 connect vc_sel.`1`, _vc_sel_WIRE_3 node channel_oh_0 = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _virt_channel_T = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node _virt_channel_T_1 = bits(_virt_channel_T, 1, 1) node _virt_channel_T_2 = mux(channel_oh_0, _virt_channel_T_1, UInt<1>(0h0)) node _virt_channel_T_3 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_4 = or(_virt_channel_T_2, _virt_channel_T_3) wire virt_channel : UInt<1> connect virt_channel, _virt_channel_T_4 node _T_29 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_29 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_4 = or(_salloc_outs_0_flit_payload_T_2, _salloc_outs_0_flit_payload_T_3) wire _salloc_outs_0_flit_payload_WIRE : UInt<37> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_4 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_4 = or(_salloc_outs_0_flit_head_T_2, _salloc_outs_0_flit_head_T_3) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_4 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_4 = or(_salloc_outs_0_flit_tail_T_2, _salloc_outs_0_flit_tail_T_3) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_4 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_2 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_4 = or(_salloc_outs_0_flit_flow_T_2, _salloc_outs_0_flit_flow_T_3) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_4 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_7 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_10 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_12) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_13 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<1> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_16 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`1`[0] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`0`[1], UInt<1>(0h0) node _T_30 = asUInt(reset) when _T_30 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0)
module InputUnit_53( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output io_debug_va_stall, // @[InputUnit.scala:170:14] output io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [1:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [1:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [1:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire _GEN_1 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_58 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_58( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMasterBEToNoC_1 : input clock : Clock input reset : Reset output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flits : { flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}} invalidate io.tilelink.e.bits.sink invalidate io.tilelink.e.valid invalidate io.tilelink.e.ready invalidate io.tilelink.d.bits.corrupt invalidate io.tilelink.d.bits.data invalidate io.tilelink.d.bits.denied invalidate io.tilelink.d.bits.sink invalidate io.tilelink.d.bits.source invalidate io.tilelink.d.bits.size invalidate io.tilelink.d.bits.param invalidate io.tilelink.d.bits.opcode invalidate io.tilelink.d.valid invalidate io.tilelink.d.ready invalidate io.tilelink.c.bits.corrupt invalidate io.tilelink.c.bits.data invalidate io.tilelink.c.bits.address invalidate io.tilelink.c.bits.source invalidate io.tilelink.c.bits.size invalidate io.tilelink.c.bits.param invalidate io.tilelink.c.bits.opcode invalidate io.tilelink.c.valid invalidate io.tilelink.c.ready invalidate io.tilelink.b.bits.corrupt invalidate io.tilelink.b.bits.data invalidate io.tilelink.b.bits.mask invalidate io.tilelink.b.bits.address invalidate io.tilelink.b.bits.source invalidate io.tilelink.b.bits.size invalidate io.tilelink.b.bits.param invalidate io.tilelink.b.bits.opcode invalidate io.tilelink.b.valid invalidate io.tilelink.b.ready invalidate io.tilelink.a.bits.corrupt invalidate io.tilelink.a.bits.data invalidate io.tilelink.a.bits.mask invalidate io.tilelink.a.bits.address invalidate io.tilelink.a.bits.source invalidate io.tilelink.a.bits.size invalidate io.tilelink.a.bits.param invalidate io.tilelink.a.bits.opcode invalidate io.tilelink.a.valid invalidate io.tilelink.a.ready inst b of TLBFromNoC_1 connect b.clock, clock connect b.reset, reset inst e of TLEToNoC_1 connect e.clock, clock connect e.reset, reset connect io.tilelink.b.bits, b.io.protocol.bits connect io.tilelink.b.valid, b.io.protocol.valid connect b.io.protocol.ready, io.tilelink.b.ready connect e.io.protocol, io.tilelink.e connect b.io.flit, io.flits.b connect io.flits.e.bits, e.io.flit.bits connect io.flits.e.valid, e.io.flit.valid connect e.io.flit.ready, io.flits.e.ready
module TLMasterBEToNoC_1( // @[Tilelink.scala:100:7] input clock, // @[Tilelink.scala:100:7] input reset, // @[Tilelink.scala:100:7] input io_tilelink_b_ready, // @[Tilelink.scala:107:14] output io_tilelink_b_valid, // @[Tilelink.scala:107:14] output [2:0] io_tilelink_b_bits_opcode, // @[Tilelink.scala:107:14] output [1:0] io_tilelink_b_bits_param, // @[Tilelink.scala:107:14] output [3:0] io_tilelink_b_bits_size, // @[Tilelink.scala:107:14] output [5:0] io_tilelink_b_bits_source, // @[Tilelink.scala:107:14] output [31:0] io_tilelink_b_bits_address, // @[Tilelink.scala:107:14] output [7:0] io_tilelink_b_bits_mask, // @[Tilelink.scala:107:14] output [63:0] io_tilelink_b_bits_data, // @[Tilelink.scala:107:14] output io_tilelink_b_bits_corrupt, // @[Tilelink.scala:107:14] output io_tilelink_e_ready, // @[Tilelink.scala:107:14] input io_tilelink_e_valid, // @[Tilelink.scala:107:14] input [4:0] io_tilelink_e_bits_sink, // @[Tilelink.scala:107:14] output io_flits_b_ready, // @[Tilelink.scala:107:14] input io_flits_b_valid, // @[Tilelink.scala:107:14] input io_flits_b_bits_head, // @[Tilelink.scala:107:14] input io_flits_b_bits_tail, // @[Tilelink.scala:107:14] input [72:0] io_flits_b_bits_payload, // @[Tilelink.scala:107:14] input io_flits_e_ready, // @[Tilelink.scala:107:14] output io_flits_e_valid, // @[Tilelink.scala:107:14] output io_flits_e_bits_head, // @[Tilelink.scala:107:14] output [72:0] io_flits_e_bits_payload, // @[Tilelink.scala:107:14] output [3:0] io_flits_e_bits_egress_id // @[Tilelink.scala:107:14] ); wire [4:0] _e_io_flit_bits_payload; // @[Tilelink.scala:116:17] TLBFromNoC_1 b ( // @[Tilelink.scala:115:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_b_ready), .io_protocol_valid (io_tilelink_b_valid), .io_protocol_bits_opcode (io_tilelink_b_bits_opcode), .io_protocol_bits_param (io_tilelink_b_bits_param), .io_protocol_bits_size (io_tilelink_b_bits_size), .io_protocol_bits_source (io_tilelink_b_bits_source), .io_protocol_bits_address (io_tilelink_b_bits_address), .io_protocol_bits_mask (io_tilelink_b_bits_mask), .io_protocol_bits_data (io_tilelink_b_bits_data), .io_protocol_bits_corrupt (io_tilelink_b_bits_corrupt), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail), .io_flit_bits_payload (io_flits_b_bits_payload) ); // @[Tilelink.scala:115:17] TLEToNoC e ( // @[Tilelink.scala:116:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_e_ready), .io_protocol_valid (io_tilelink_e_valid), .io_protocol_bits_sink (io_tilelink_e_bits_sink), .io_flit_ready (io_flits_e_ready), .io_flit_valid (io_flits_e_valid), .io_flit_bits_head (io_flits_e_bits_head), .io_flit_bits_payload (_e_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_e_bits_egress_id) ); // @[Tilelink.scala:116:17] assign io_flits_e_bits_payload = {68'h0, _e_io_flit_bits_payload}; // @[Tilelink.scala:100:7, :116:17, :121:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLPLIC : input clock : Clock input reset : Reset output auto : { flip int_in : UInt<1>[1], int_out_1 : UInt<1>[1], int_out_0 : UInt<1>[1], flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_50 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire intnodeIn : UInt<1>[1] invalidate intnodeIn[0] wire intnodeOut : UInt<1>[1] invalidate intnodeOut[0] wire x1_intnodeOut : UInt<1>[1] invalidate x1_intnodeOut[0] connect nodeIn, auto.in connect auto.int_out_0, intnodeOut connect auto.int_out_1, x1_intnodeOut connect intnodeIn, auto.int_in inst gateways_gateway of LevelGateway connect gateways_gateway.clock, clock connect gateways_gateway.reset, reset connect gateways_gateway.io.interrupt, intnodeIn[0] reg priority : UInt<1>[1], clock reg threshold : UInt<1>[2], clock wire _pending_WIRE : UInt<1>[1] connect _pending_WIRE[0], UInt<1>(0h0) regreset pending : UInt<1>[1], clock, reset, _pending_WIRE reg enables_0_0 : UInt<1>, clock reg enables_1_0 : UInt<1>, clock wire enableVec : UInt<1>[2] connect enableVec[0], enables_0_0 connect enableVec[1], enables_1_0 node _enableVec0_T = cat(enableVec[0], UInt<1>(0h0)) node _enableVec0_T_1 = cat(enableVec[1], UInt<1>(0h0)) wire enableVec0 : UInt<2>[2] connect enableVec0[0], _enableVec0_T connect enableVec0[1], _enableVec0_T_1 reg maxDevs : UInt<1>[2], clock inst fanin of PLICFanIn connect fanin.clock, clock connect fanin.reset, reset connect fanin.io.prio[0], priority[0] node _fanin_io_ip_T = and(enableVec[0], pending[0]) connect fanin.io.ip, _fanin_io_ip_T connect maxDevs[0], fanin.io.dev reg intnodeOut_0_REG : UInt, clock connect intnodeOut_0_REG, fanin.io.max node _intnodeOut_0_T = gt(intnodeOut_0_REG, threshold[0]) connect intnodeOut[0], _intnodeOut_0_T inst fanin_1 of PLICFanIn_1 connect fanin_1.clock, clock connect fanin_1.reset, reset connect fanin_1.io.prio[0], priority[0] node _fanin_io_ip_T_1 = and(enableVec[1], pending[0]) connect fanin_1.io.ip, _fanin_io_ip_T_1 connect maxDevs[1], fanin_1.io.dev reg intnodeOut_0_REG_1 : UInt, clock connect intnodeOut_0_REG_1, fanin_1.io.max node _intnodeOut_0_T_1 = gt(intnodeOut_0_REG_1, threshold[1]) connect x1_intnodeOut[0], _intnodeOut_0_T_1 wire claimer : UInt<1>[2] node _T = cat(claimer[1], claimer[0]) node _T_1 = cat(claimer[1], claimer[0]) node _T_2 = sub(_T_1, UInt<1>(0h1)) node _T_3 = tail(_T_2, 1) node _T_4 = and(_T, _T_3) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Plic.scala:251 assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot\n") : printf assert(clock, _T_5, UInt<1>(0h1), "") : assert node _claiming_T = mux(claimer[0], maxDevs[0], UInt<1>(0h0)) node _claiming_T_1 = mux(claimer[1], maxDevs[1], UInt<1>(0h0)) node claiming = or(_claiming_T, _claiming_T_1) node claimedDevs_shiftAmount = bits(claiming, 0, 0) node _claimedDevs_T = dshl(UInt<1>(0h1), claimedDevs_shiftAmount) node _claimedDevs_T_1 = bits(_claimedDevs_T, 1, 0) node _claimedDevs_T_2 = bits(_claimedDevs_T_1, 0, 0) node _claimedDevs_T_3 = bits(_claimedDevs_T_1, 1, 1) wire claimedDevs : UInt<1>[2] connect claimedDevs[0], _claimedDevs_T_2 connect claimedDevs[1], _claimedDevs_T_3 node _gateway_io_plic_ready_T = eq(pending[0], UInt<1>(0h0)) connect gateways_gateway.io.plic.ready, _gateway_io_plic_ready_T node _T_9 = or(claimedDevs[1], gateways_gateway.io.plic.valid) when _T_9 : node _pending_0_T = eq(claimedDevs[1], UInt<1>(0h0)) connect pending[0], _pending_0_T wire completer : UInt<1>[2] node _T_10 = cat(completer[1], completer[0]) node _T_11 = cat(completer[1], completer[0]) node _T_12 = sub(_T_11, UInt<1>(0h1)) node _T_13 = tail(_T_12, 1) node _T_14 = and(_T_10, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Plic.scala:268 assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot\n") : printf_1 assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 wire completerDev : UInt<1> node _completedDevs_T = or(completer[0], completer[1]) node completedDevs_shiftAmount = bits(completerDev, 0, 0) node _completedDevs_T_1 = dshl(UInt<1>(0h1), completedDevs_shiftAmount) node _completedDevs_T_2 = bits(_completedDevs_T_1, 1, 0) node completedDevs = mux(_completedDevs_T, _completedDevs_T_2, UInt<1>(0h0)) node _T_19 = bits(completedDevs, 0, 0) node _T_20 = bits(completedDevs, 1, 1) connect gateways_gateway.io.plic.complete, _T_20 wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits inst out_back_front_q of Queue1_RegMapperInput_i23_m8 connect out_back_front_q.clock, clock connect out_back_front_q.reset, reset connect out_back_front_q.io.enq, out_front node out_maskMatch = not(UInt<23>(0h40610)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<23>(0h0)) node _out_T_1 = eq(out_bindex, UInt<23>(0h0)) node _out_T_2 = eq(out_findex, UInt<23>(0h0)) node _out_T_3 = eq(out_bindex, UInt<23>(0h0)) node _out_T_4 = eq(out_findex, UInt<23>(0h0)) node _out_T_5 = eq(out_bindex, UInt<23>(0h0)) node _out_T_6 = eq(out_findex, UInt<23>(0h0)) node _out_T_7 = eq(out_bindex, UInt<23>(0h0)) node _out_T_8 = eq(out_findex, UInt<23>(0h0)) node _out_T_9 = eq(out_bindex, UInt<23>(0h0)) node _out_T_10 = eq(out_findex, UInt<23>(0h0)) node _out_T_11 = eq(out_bindex, UInt<23>(0h0)) wire out_rivalid : UInt<1>[13] wire out_wivalid : UInt<1>[13] wire out_roready : UInt<1>[13] wire out_woready : UInt<1>[13] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_12 = bits(out_back_front_q.io.deq.bits.data, 0, 0) node _out_T_13 = and(out_f_rivalid, UInt<1>(0h1)) node _out_T_14 = and(UInt<1>(0h1), out_f_roready) node _out_T_15 = eq(out_rimask, UInt<1>(0h0)) node _out_T_16 = eq(out_wimask, UInt<1>(0h0)) node _out_T_17 = eq(out_romask, UInt<1>(0h0)) node _out_T_18 = eq(out_womask, UInt<1>(0h0)) node _out_T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _out_T_20 = bits(_out_T_19, 0, 0) node _out_rimask_T_1 = bits(out_frontMask, 1, 1) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 1, 1) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 1, 1) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 1, 1) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_21 = bits(out_back_front_q.io.deq.bits.data, 1, 1) when out_f_woready_1 : connect enables_1_0, _out_T_21 node _out_T_22 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_23 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_24 = and(out_f_wivalid_1, UInt<1>(0h1)) node _out_T_25 = and(UInt<1>(0h1), out_f_woready_1) node _out_T_26 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_27 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_28 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_29 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_20, UInt<1>(0h0)) node out_prepend = cat(enables_1_0, _out_prepend_T) node _out_T_30 = or(out_prepend, UInt<2>(0h0)) node _out_T_31 = bits(_out_T_30, 1, 0) node _out_rimask_T_2 = bits(out_frontMask, 0, 0) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 0, 0) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 0, 0) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 0, 0) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_32 = bits(out_back_front_q.io.deq.bits.data, 0, 0) node _out_T_33 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_34 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_35 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_36 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_37 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_38 = eq(out_womask_2, UInt<1>(0h0)) node _out_T_39 = or(UInt<1>(0h0), UInt<1>(0h0)) node _out_T_40 = bits(_out_T_39, 0, 0) node _out_rimask_T_3 = bits(out_frontMask, 1, 1) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 1, 1) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 1, 1) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 1, 1) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_41 = bits(out_back_front_q.io.deq.bits.data, 1, 1) node _out_T_42 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_43 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_44 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_45 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_46 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_47 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_40, UInt<1>(0h0)) node out_prepend_1 = cat(pending[0], _out_prepend_T_1) node _out_T_48 = or(out_prepend_1, UInt<2>(0h0)) node _out_T_49 = bits(_out_T_48, 1, 0) node _out_rimask_T_4 = bits(out_frontMask, 0, 0) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 0, 0) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 0, 0) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 0, 0) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_50 = bits(out_back_front_q.io.deq.bits.data, 0, 0) when out_f_woready_4 : connect threshold[1], _out_T_50 node _out_T_51 = and(out_f_rivalid_4, UInt<1>(0h1)) node _out_T_52 = and(UInt<1>(0h1), out_f_roready_4) node _out_T_53 = and(out_f_wivalid_4, UInt<1>(0h1)) node _out_T_54 = and(UInt<1>(0h1), out_f_woready_4) node _out_T_55 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_56 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_57 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_58 = eq(out_womask_4, UInt<1>(0h0)) node _out_T_59 = or(threshold[1], UInt<1>(0h0)) node _out_T_60 = bits(_out_T_59, 0, 0) node _out_rimask_T_5 = bits(out_frontMask, 31, 1) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 31, 1) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 31, 1) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 31, 1) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_61 = bits(out_back_front_q.io.deq.bits.data, 31, 1) node _out_T_62 = and(out_f_rivalid_5, UInt<1>(0h1)) node _out_T_63 = and(UInt<1>(0h1), out_f_roready_5) node _out_T_64 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_65 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_66 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_67 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_60, UInt<1>(0h0)) node out_prepend_2 = cat(UInt<1>(0h0), _out_prepend_T_2) node _out_T_68 = or(out_prepend_2, UInt<32>(0h0)) node _out_T_69 = bits(_out_T_68, 31, 0) node _out_rimask_T_6 = bits(out_frontMask, 63, 32) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 63, 32) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 63, 32) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 63, 32) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) connect claimer[1], out_f_roready_6 node _out_T_70 = bits(out_back_front_q.io.deq.bits.data, 63, 32) node _out_T_71 = bits(_out_T_70, 0, 0) node _out_T_72 = eq(completerDev, _out_T_71) node _out_T_73 = asUInt(reset) node _out_T_74 = eq(_out_T_73, UInt<1>(0h0)) when _out_T_74 : node _out_T_75 = eq(_out_T_72, UInt<1>(0h0)) when _out_T_75 : printf(clock, UInt<1>(0h1), "Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:298 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n") : out_printf assert(clock, _out_T_72, UInt<1>(0h1), "") : out_assert node _out_completerDev_T = bits(_out_T_70, 0, 0) connect completerDev, _out_completerDev_T node _out_completer_1_T = dshr(enableVec0[1], completerDev) node _out_completer_1_T_1 = bits(_out_completer_1_T, 0, 0) node _out_completer_1_T_2 = and(out_f_woready_6, _out_completer_1_T_1) connect completer[1], _out_completer_1_T_2 node _out_T_76 = and(out_f_rivalid_6, UInt<1>(0h1)) node _out_T_77 = and(UInt<1>(0h1), out_f_roready_6) node _out_T_78 = and(out_f_wivalid_6, UInt<1>(0h1)) node _out_T_79 = and(UInt<1>(0h1), out_f_woready_6) node _out_T_80 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_81 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_82 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_83 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_69, UInt<32>(0h0)) node out_prepend_3 = cat(maxDevs[1], _out_prepend_T_3) node _out_T_84 = or(out_prepend_3, UInt<64>(0h0)) node _out_T_85 = bits(_out_T_84, 63, 0) node _out_rimask_T_7 = bits(out_frontMask, 0, 0) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 0, 0) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 0, 0) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 0, 0) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_86 = bits(out_back_front_q.io.deq.bits.data, 0, 0) when out_f_woready_7 : connect threshold[0], _out_T_86 node _out_T_87 = and(out_f_rivalid_7, UInt<1>(0h1)) node _out_T_88 = and(UInt<1>(0h1), out_f_roready_7) node _out_T_89 = and(out_f_wivalid_7, UInt<1>(0h1)) node _out_T_90 = and(UInt<1>(0h1), out_f_woready_7) node _out_T_91 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_92 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_93 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_94 = eq(out_womask_7, UInt<1>(0h0)) node _out_T_95 = or(threshold[0], UInt<1>(0h0)) node _out_T_96 = bits(_out_T_95, 0, 0) node _out_rimask_T_8 = bits(out_frontMask, 31, 1) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 31, 1) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 31, 1) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 31, 1) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) node _out_T_97 = bits(out_back_front_q.io.deq.bits.data, 31, 1) node _out_T_98 = and(out_f_rivalid_8, UInt<1>(0h1)) node _out_T_99 = and(UInt<1>(0h1), out_f_roready_8) node _out_T_100 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_101 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_102 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_103 = eq(out_womask_8, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_96, UInt<1>(0h0)) node out_prepend_4 = cat(UInt<1>(0h0), _out_prepend_T_4) node _out_T_104 = or(out_prepend_4, UInt<32>(0h0)) node _out_T_105 = bits(_out_T_104, 31, 0) node _out_rimask_T_9 = bits(out_frontMask, 63, 32) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 63, 32) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 63, 32) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 63, 32) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) connect claimer[0], out_f_roready_9 node _out_T_106 = bits(out_back_front_q.io.deq.bits.data, 63, 32) node _out_T_107 = bits(_out_T_106, 0, 0) node _out_T_108 = eq(completerDev, _out_T_107) node _out_T_109 = asUInt(reset) node _out_T_110 = eq(_out_T_109, UInt<1>(0h0)) when _out_T_110 : node _out_T_111 = eq(_out_T_108, UInt<1>(0h0)) when _out_T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:298 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n") : out_printf_1 assert(clock, _out_T_108, UInt<1>(0h1), "") : out_assert_1 node _out_completerDev_T_1 = bits(_out_T_106, 0, 0) connect completerDev, _out_completerDev_T_1 node _out_completer_0_T = dshr(enableVec0[0], completerDev) node _out_completer_0_T_1 = bits(_out_completer_0_T, 0, 0) node _out_completer_0_T_2 = and(out_f_woready_9, _out_completer_0_T_1) connect completer[0], _out_completer_0_T_2 node _out_T_112 = and(out_f_rivalid_9, UInt<1>(0h1)) node _out_T_113 = and(UInt<1>(0h1), out_f_roready_9) node _out_T_114 = and(out_f_wivalid_9, UInt<1>(0h1)) node _out_T_115 = and(UInt<1>(0h1), out_f_woready_9) node _out_T_116 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_117 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_118 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_119 = eq(out_womask_9, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_105, UInt<32>(0h0)) node out_prepend_5 = cat(maxDevs[0], _out_prepend_T_5) node _out_T_120 = or(out_prepend_5, UInt<64>(0h0)) node _out_T_121 = bits(_out_T_120, 63, 0) node _out_rimask_T_10 = bits(out_frontMask, 0, 0) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 0, 0) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 0, 0) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 0, 0) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) node _out_T_122 = bits(out_back_front_q.io.deq.bits.data, 0, 0) node _out_T_123 = and(out_f_rivalid_10, UInt<1>(0h1)) node _out_T_124 = and(UInt<1>(0h1), out_f_roready_10) node _out_T_125 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_126 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_127 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_128 = eq(out_womask_10, UInt<1>(0h0)) node _out_T_129 = or(UInt<1>(0h0), UInt<1>(0h0)) node _out_T_130 = bits(_out_T_129, 0, 0) node _out_rimask_T_11 = bits(out_frontMask, 1, 1) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 1, 1) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 1, 1) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 1, 1) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) node _out_T_131 = bits(out_back_front_q.io.deq.bits.data, 1, 1) when out_f_woready_11 : connect enables_0_0, _out_T_131 node _out_T_132 = and(out_f_rivalid_11, UInt<1>(0h1)) node _out_T_133 = and(UInt<1>(0h1), out_f_roready_11) node _out_T_134 = and(out_f_wivalid_11, UInt<1>(0h1)) node _out_T_135 = and(UInt<1>(0h1), out_f_woready_11) node _out_T_136 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_137 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_138 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_139 = eq(out_womask_11, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_130, UInt<1>(0h0)) node out_prepend_6 = cat(enables_0_0, _out_prepend_T_6) node _out_T_140 = or(out_prepend_6, UInt<2>(0h0)) node _out_T_141 = bits(_out_T_140, 1, 0) node _out_rimask_T_12 = bits(out_frontMask, 32, 32) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 32, 32) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 32, 32) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 32, 32) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_142 = bits(out_back_front_q.io.deq.bits.data, 32, 32) when out_f_woready_12 : connect priority[0], _out_T_142 node _out_T_143 = and(out_f_rivalid_12, UInt<1>(0h1)) node _out_T_144 = and(UInt<1>(0h1), out_f_roready_12) node _out_T_145 = and(out_f_wivalid_12, UInt<1>(0h1)) node _out_T_146 = and(UInt<1>(0h1), out_f_woready_12) node _out_T_147 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_148 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_149 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_150 = eq(out_womask_12, UInt<1>(0h0)) node _out_prepend_T_7 = or(UInt<1>(0h0), UInt<32>(0h0)) node out_prepend_7 = cat(priority[0], _out_prepend_T_7) node _out_T_151 = or(out_prepend_7, UInt<33>(0h0)) node _out_T_152 = bits(_out_T_151, 32, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node _out_iindex_T_9 = bits(out_front.bits.index, 9, 9) node _out_iindex_T_10 = bits(out_front.bits.index, 10, 10) node _out_iindex_T_11 = bits(out_front.bits.index, 11, 11) node _out_iindex_T_12 = bits(out_front.bits.index, 12, 12) node _out_iindex_T_13 = bits(out_front.bits.index, 13, 13) node _out_iindex_T_14 = bits(out_front.bits.index, 14, 14) node _out_iindex_T_15 = bits(out_front.bits.index, 15, 15) node _out_iindex_T_16 = bits(out_front.bits.index, 16, 16) node _out_iindex_T_17 = bits(out_front.bits.index, 17, 17) node _out_iindex_T_18 = bits(out_front.bits.index, 18, 18) node _out_iindex_T_19 = bits(out_front.bits.index, 19, 19) node _out_iindex_T_20 = bits(out_front.bits.index, 20, 20) node _out_iindex_T_21 = bits(out_front.bits.index, 21, 21) node _out_iindex_T_22 = bits(out_front.bits.index, 22, 22) node out_iindex_lo = cat(_out_iindex_T_9, _out_iindex_T_4) node out_iindex_hi = cat(_out_iindex_T_18, _out_iindex_T_10) node out_iindex = cat(out_iindex_hi, out_iindex_lo) node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_back_front_q.io.deq.bits.index, 8, 8) node _out_oindex_T_9 = bits(out_back_front_q.io.deq.bits.index, 9, 9) node _out_oindex_T_10 = bits(out_back_front_q.io.deq.bits.index, 10, 10) node _out_oindex_T_11 = bits(out_back_front_q.io.deq.bits.index, 11, 11) node _out_oindex_T_12 = bits(out_back_front_q.io.deq.bits.index, 12, 12) node _out_oindex_T_13 = bits(out_back_front_q.io.deq.bits.index, 13, 13) node _out_oindex_T_14 = bits(out_back_front_q.io.deq.bits.index, 14, 14) node _out_oindex_T_15 = bits(out_back_front_q.io.deq.bits.index, 15, 15) node _out_oindex_T_16 = bits(out_back_front_q.io.deq.bits.index, 16, 16) node _out_oindex_T_17 = bits(out_back_front_q.io.deq.bits.index, 17, 17) node _out_oindex_T_18 = bits(out_back_front_q.io.deq.bits.index, 18, 18) node _out_oindex_T_19 = bits(out_back_front_q.io.deq.bits.index, 19, 19) node _out_oindex_T_20 = bits(out_back_front_q.io.deq.bits.index, 20, 20) node _out_oindex_T_21 = bits(out_back_front_q.io.deq.bits.index, 21, 21) node _out_oindex_T_22 = bits(out_back_front_q.io.deq.bits.index, 22, 22) node out_oindex_lo = cat(_out_oindex_T_9, _out_oindex_T_4) node out_oindex_hi = cat(_out_oindex_T_18, _out_oindex_T_10) node out_oindex = cat(out_oindex_hi, out_oindex_lo) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node out_frontSel_4 = bits(_out_frontSel_T, 4, 4) node out_frontSel_5 = bits(_out_frontSel_T, 5, 5) node out_frontSel_6 = bits(_out_frontSel_T, 6, 6) node out_frontSel_7 = bits(_out_frontSel_T, 7, 7) node out_frontSel_8 = bits(_out_frontSel_T, 8, 8) node out_frontSel_9 = bits(_out_frontSel_T, 9, 9) node out_frontSel_10 = bits(_out_frontSel_T, 10, 10) node out_frontSel_11 = bits(_out_frontSel_T, 11, 11) node out_frontSel_12 = bits(_out_frontSel_T, 12, 12) node out_frontSel_13 = bits(_out_frontSel_T, 13, 13) node out_frontSel_14 = bits(_out_frontSel_T, 14, 14) node out_frontSel_15 = bits(_out_frontSel_T, 15, 15) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node out_backSel_4 = bits(_out_backSel_T, 4, 4) node out_backSel_5 = bits(_out_backSel_T, 5, 5) node out_backSel_6 = bits(_out_backSel_T, 6, 6) node out_backSel_7 = bits(_out_backSel_T, 7, 7) node out_backSel_8 = bits(_out_backSel_T, 8, 8) node out_backSel_9 = bits(_out_backSel_T, 9, 9) node out_backSel_10 = bits(_out_backSel_T, 10, 10) node out_backSel_11 = bits(_out_backSel_T, 11, 11) node out_backSel_12 = bits(_out_backSel_T, 12, 12) node out_backSel_13 = bits(_out_backSel_T, 13, 13) node out_backSel_14 = bits(_out_backSel_T, 14, 14) node out_backSel_15 = bits(_out_backSel_T, 15, 15) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T_10) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[12], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T_10, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, UInt<1>(0h1)) connect out_rifireMux_out_1, UInt<1>(0h1) node _out_rifireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_2) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[3], _out_rifireMux_T_11 connect out_rivalid[2], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, UInt<1>(0h1)) connect out_rifireMux_out_3, UInt<1>(0h1) node _out_rifireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) wire out_rifireMux_out_4 : UInt<1> node _out_rifireMux_T_18 = and(_out_rifireMux_T_1, out_frontSel_4) node _out_rifireMux_T_19 = and(_out_rifireMux_T_18, _out_T_8) connect out_rifireMux_out_4, UInt<1>(0h1) connect out_rivalid[11], _out_rifireMux_T_19 connect out_rivalid[10], _out_rifireMux_T_19 node _out_rifireMux_T_20 = eq(_out_T_8, UInt<1>(0h0)) node _out_rifireMux_T_21 = or(out_rifireMux_out_4, _out_rifireMux_T_20) wire out_rifireMux_out_5 : UInt<1> node _out_rifireMux_T_22 = and(_out_rifireMux_T_1, out_frontSel_5) node _out_rifireMux_T_23 = and(_out_rifireMux_T_22, _out_T) connect out_rifireMux_out_5, UInt<1>(0h1) connect out_rivalid[1], _out_rifireMux_T_23 connect out_rivalid[0], _out_rifireMux_T_23 node _out_rifireMux_T_24 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_25 = or(out_rifireMux_out_5, _out_rifireMux_T_24) wire out_rifireMux_out_6 : UInt<1> node _out_rifireMux_T_26 = and(_out_rifireMux_T_1, out_frontSel_6) node _out_rifireMux_T_27 = and(_out_rifireMux_T_26, UInt<1>(0h1)) connect out_rifireMux_out_6, UInt<1>(0h1) node _out_rifireMux_T_28 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_29 = or(out_rifireMux_out_6, _out_rifireMux_T_28) wire out_rifireMux_out_7 : UInt<1> node _out_rifireMux_T_30 = and(_out_rifireMux_T_1, out_frontSel_7) node _out_rifireMux_T_31 = and(_out_rifireMux_T_30, UInt<1>(0h1)) connect out_rifireMux_out_7, UInt<1>(0h1) node _out_rifireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_33 = or(out_rifireMux_out_7, _out_rifireMux_T_32) wire out_rifireMux_out_8 : UInt<1> node _out_rifireMux_T_34 = and(_out_rifireMux_T_1, out_frontSel_8) node _out_rifireMux_T_35 = and(_out_rifireMux_T_34, _out_T_6) connect out_rifireMux_out_8, UInt<1>(0h1) connect out_rivalid[9], _out_rifireMux_T_35 connect out_rivalid[8], _out_rifireMux_T_35 connect out_rivalid[7], _out_rifireMux_T_35 node _out_rifireMux_T_36 = eq(_out_T_6, UInt<1>(0h0)) node _out_rifireMux_T_37 = or(out_rifireMux_out_8, _out_rifireMux_T_36) wire out_rifireMux_out_9 : UInt<1> node _out_rifireMux_T_38 = and(_out_rifireMux_T_1, out_frontSel_9) node _out_rifireMux_T_39 = and(_out_rifireMux_T_38, UInt<1>(0h1)) connect out_rifireMux_out_9, UInt<1>(0h1) node _out_rifireMux_T_40 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_41 = or(out_rifireMux_out_9, _out_rifireMux_T_40) wire out_rifireMux_out_10 : UInt<1> node _out_rifireMux_T_42 = and(_out_rifireMux_T_1, out_frontSel_10) node _out_rifireMux_T_43 = and(_out_rifireMux_T_42, _out_T_4) connect out_rifireMux_out_10, UInt<1>(0h1) connect out_rivalid[6], _out_rifireMux_T_43 connect out_rivalid[5], _out_rifireMux_T_43 connect out_rivalid[4], _out_rifireMux_T_43 node _out_rifireMux_T_44 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_45 = or(out_rifireMux_out_10, _out_rifireMux_T_44) wire out_rifireMux_out_11 : UInt<1> node _out_rifireMux_T_46 = and(_out_rifireMux_T_1, out_frontSel_11) node _out_rifireMux_T_47 = and(_out_rifireMux_T_46, UInt<1>(0h1)) connect out_rifireMux_out_11, UInt<1>(0h1) node _out_rifireMux_T_48 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_49 = or(out_rifireMux_out_11, _out_rifireMux_T_48) wire out_rifireMux_out_12 : UInt<1> node _out_rifireMux_T_50 = and(_out_rifireMux_T_1, out_frontSel_12) node _out_rifireMux_T_51 = and(_out_rifireMux_T_50, UInt<1>(0h1)) connect out_rifireMux_out_12, UInt<1>(0h1) node _out_rifireMux_T_52 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_53 = or(out_rifireMux_out_12, _out_rifireMux_T_52) wire out_rifireMux_out_13 : UInt<1> node _out_rifireMux_T_54 = and(_out_rifireMux_T_1, out_frontSel_13) node _out_rifireMux_T_55 = and(_out_rifireMux_T_54, UInt<1>(0h1)) connect out_rifireMux_out_13, UInt<1>(0h1) node _out_rifireMux_T_56 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_57 = or(out_rifireMux_out_13, _out_rifireMux_T_56) wire out_rifireMux_out_14 : UInt<1> node _out_rifireMux_T_58 = and(_out_rifireMux_T_1, out_frontSel_14) node _out_rifireMux_T_59 = and(_out_rifireMux_T_58, UInt<1>(0h1)) connect out_rifireMux_out_14, UInt<1>(0h1) node _out_rifireMux_T_60 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_61 = or(out_rifireMux_out_14, _out_rifireMux_T_60) wire out_rifireMux_out_15 : UInt<1> node _out_rifireMux_T_62 = and(_out_rifireMux_T_1, out_frontSel_15) node _out_rifireMux_T_63 = and(_out_rifireMux_T_62, UInt<1>(0h1)) connect out_rifireMux_out_15, UInt<1>(0h1) node _out_rifireMux_T_64 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_65 = or(out_rifireMux_out_15, _out_rifireMux_T_64) node _out_rifireMux_T_66 = geq(out_iindex, UInt<5>(0h10)) wire _out_rifireMux_WIRE : UInt<1>[16] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 connect _out_rifireMux_WIRE[4], _out_rifireMux_T_21 connect _out_rifireMux_WIRE[5], _out_rifireMux_T_25 connect _out_rifireMux_WIRE[6], _out_rifireMux_T_29 connect _out_rifireMux_WIRE[7], _out_rifireMux_T_33 connect _out_rifireMux_WIRE[8], _out_rifireMux_T_37 connect _out_rifireMux_WIRE[9], _out_rifireMux_T_41 connect _out_rifireMux_WIRE[10], _out_rifireMux_T_45 connect _out_rifireMux_WIRE[11], _out_rifireMux_T_49 connect _out_rifireMux_WIRE[12], _out_rifireMux_T_53 connect _out_rifireMux_WIRE[13], _out_rifireMux_T_57 connect _out_rifireMux_WIRE[14], _out_rifireMux_T_61 connect _out_rifireMux_WIRE[15], _out_rifireMux_T_65 node out_rifireMux = mux(_out_rifireMux_T_66, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T_10) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[12], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T_10, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, UInt<1>(0h1)) connect out_wifireMux_out_1, UInt<1>(0h1) node _out_wifireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_2) connect out_wifireMux_out_2, UInt<1>(0h1) connect out_wivalid[3], _out_wifireMux_T_12 connect out_wivalid[2], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, UInt<1>(0h1)) connect out_wifireMux_out_3, UInt<1>(0h1) node _out_wifireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) wire out_wifireMux_out_4 : UInt<1> node _out_wifireMux_T_19 = and(_out_wifireMux_T_2, out_frontSel_4) node _out_wifireMux_T_20 = and(_out_wifireMux_T_19, _out_T_8) connect out_wifireMux_out_4, UInt<1>(0h1) connect out_wivalid[11], _out_wifireMux_T_20 connect out_wivalid[10], _out_wifireMux_T_20 node _out_wifireMux_T_21 = eq(_out_T_8, UInt<1>(0h0)) node _out_wifireMux_T_22 = or(out_wifireMux_out_4, _out_wifireMux_T_21) wire out_wifireMux_out_5 : UInt<1> node _out_wifireMux_T_23 = and(_out_wifireMux_T_2, out_frontSel_5) node _out_wifireMux_T_24 = and(_out_wifireMux_T_23, _out_T) connect out_wifireMux_out_5, UInt<1>(0h1) connect out_wivalid[1], _out_wifireMux_T_24 connect out_wivalid[0], _out_wifireMux_T_24 node _out_wifireMux_T_25 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_26 = or(out_wifireMux_out_5, _out_wifireMux_T_25) wire out_wifireMux_out_6 : UInt<1> node _out_wifireMux_T_27 = and(_out_wifireMux_T_2, out_frontSel_6) node _out_wifireMux_T_28 = and(_out_wifireMux_T_27, UInt<1>(0h1)) connect out_wifireMux_out_6, UInt<1>(0h1) node _out_wifireMux_T_29 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_30 = or(out_wifireMux_out_6, _out_wifireMux_T_29) wire out_wifireMux_out_7 : UInt<1> node _out_wifireMux_T_31 = and(_out_wifireMux_T_2, out_frontSel_7) node _out_wifireMux_T_32 = and(_out_wifireMux_T_31, UInt<1>(0h1)) connect out_wifireMux_out_7, UInt<1>(0h1) node _out_wifireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_34 = or(out_wifireMux_out_7, _out_wifireMux_T_33) wire out_wifireMux_out_8 : UInt<1> node _out_wifireMux_T_35 = and(_out_wifireMux_T_2, out_frontSel_8) node _out_wifireMux_T_36 = and(_out_wifireMux_T_35, _out_T_6) connect out_wifireMux_out_8, UInt<1>(0h1) connect out_wivalid[9], _out_wifireMux_T_36 connect out_wivalid[8], _out_wifireMux_T_36 connect out_wivalid[7], _out_wifireMux_T_36 node _out_wifireMux_T_37 = eq(_out_T_6, UInt<1>(0h0)) node _out_wifireMux_T_38 = or(out_wifireMux_out_8, _out_wifireMux_T_37) wire out_wifireMux_out_9 : UInt<1> node _out_wifireMux_T_39 = and(_out_wifireMux_T_2, out_frontSel_9) node _out_wifireMux_T_40 = and(_out_wifireMux_T_39, UInt<1>(0h1)) connect out_wifireMux_out_9, UInt<1>(0h1) node _out_wifireMux_T_41 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_42 = or(out_wifireMux_out_9, _out_wifireMux_T_41) wire out_wifireMux_out_10 : UInt<1> node _out_wifireMux_T_43 = and(_out_wifireMux_T_2, out_frontSel_10) node _out_wifireMux_T_44 = and(_out_wifireMux_T_43, _out_T_4) connect out_wifireMux_out_10, UInt<1>(0h1) connect out_wivalid[6], _out_wifireMux_T_44 connect out_wivalid[5], _out_wifireMux_T_44 connect out_wivalid[4], _out_wifireMux_T_44 node _out_wifireMux_T_45 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_46 = or(out_wifireMux_out_10, _out_wifireMux_T_45) wire out_wifireMux_out_11 : UInt<1> node _out_wifireMux_T_47 = and(_out_wifireMux_T_2, out_frontSel_11) node _out_wifireMux_T_48 = and(_out_wifireMux_T_47, UInt<1>(0h1)) connect out_wifireMux_out_11, UInt<1>(0h1) node _out_wifireMux_T_49 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_50 = or(out_wifireMux_out_11, _out_wifireMux_T_49) wire out_wifireMux_out_12 : UInt<1> node _out_wifireMux_T_51 = and(_out_wifireMux_T_2, out_frontSel_12) node _out_wifireMux_T_52 = and(_out_wifireMux_T_51, UInt<1>(0h1)) connect out_wifireMux_out_12, UInt<1>(0h1) node _out_wifireMux_T_53 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_54 = or(out_wifireMux_out_12, _out_wifireMux_T_53) wire out_wifireMux_out_13 : UInt<1> node _out_wifireMux_T_55 = and(_out_wifireMux_T_2, out_frontSel_13) node _out_wifireMux_T_56 = and(_out_wifireMux_T_55, UInt<1>(0h1)) connect out_wifireMux_out_13, UInt<1>(0h1) node _out_wifireMux_T_57 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_58 = or(out_wifireMux_out_13, _out_wifireMux_T_57) wire out_wifireMux_out_14 : UInt<1> node _out_wifireMux_T_59 = and(_out_wifireMux_T_2, out_frontSel_14) node _out_wifireMux_T_60 = and(_out_wifireMux_T_59, UInt<1>(0h1)) connect out_wifireMux_out_14, UInt<1>(0h1) node _out_wifireMux_T_61 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_62 = or(out_wifireMux_out_14, _out_wifireMux_T_61) wire out_wifireMux_out_15 : UInt<1> node _out_wifireMux_T_63 = and(_out_wifireMux_T_2, out_frontSel_15) node _out_wifireMux_T_64 = and(_out_wifireMux_T_63, UInt<1>(0h1)) connect out_wifireMux_out_15, UInt<1>(0h1) node _out_wifireMux_T_65 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_66 = or(out_wifireMux_out_15, _out_wifireMux_T_65) node _out_wifireMux_T_67 = geq(out_iindex, UInt<5>(0h10)) wire _out_wifireMux_WIRE : UInt<1>[16] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 connect _out_wifireMux_WIRE[4], _out_wifireMux_T_22 connect _out_wifireMux_WIRE[5], _out_wifireMux_T_26 connect _out_wifireMux_WIRE[6], _out_wifireMux_T_30 connect _out_wifireMux_WIRE[7], _out_wifireMux_T_34 connect _out_wifireMux_WIRE[8], _out_wifireMux_T_38 connect _out_wifireMux_WIRE[9], _out_wifireMux_T_42 connect _out_wifireMux_WIRE[10], _out_wifireMux_T_46 connect _out_wifireMux_WIRE[11], _out_wifireMux_T_50 connect _out_wifireMux_WIRE[12], _out_wifireMux_T_54 connect _out_wifireMux_WIRE[13], _out_wifireMux_T_58 connect _out_wifireMux_WIRE[14], _out_wifireMux_T_62 connect _out_wifireMux_WIRE[15], _out_wifireMux_T_66 node out_wifireMux = mux(_out_wifireMux_T_67, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_11) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[12], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_11, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, UInt<1>(0h1)) connect out_rofireMux_out_1, UInt<1>(0h1) node _out_rofireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_3) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[3], _out_rofireMux_T_11 connect out_roready[2], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, UInt<1>(0h1)) connect out_rofireMux_out_3, UInt<1>(0h1) node _out_rofireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) wire out_rofireMux_out_4 : UInt<1> node _out_rofireMux_T_18 = and(_out_rofireMux_T_1, out_backSel_4) node _out_rofireMux_T_19 = and(_out_rofireMux_T_18, _out_T_9) connect out_rofireMux_out_4, UInt<1>(0h1) connect out_roready[11], _out_rofireMux_T_19 connect out_roready[10], _out_rofireMux_T_19 node _out_rofireMux_T_20 = eq(_out_T_9, UInt<1>(0h0)) node _out_rofireMux_T_21 = or(out_rofireMux_out_4, _out_rofireMux_T_20) wire out_rofireMux_out_5 : UInt<1> node _out_rofireMux_T_22 = and(_out_rofireMux_T_1, out_backSel_5) node _out_rofireMux_T_23 = and(_out_rofireMux_T_22, _out_T_1) connect out_rofireMux_out_5, UInt<1>(0h1) connect out_roready[1], _out_rofireMux_T_23 connect out_roready[0], _out_rofireMux_T_23 node _out_rofireMux_T_24 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_25 = or(out_rofireMux_out_5, _out_rofireMux_T_24) wire out_rofireMux_out_6 : UInt<1> node _out_rofireMux_T_26 = and(_out_rofireMux_T_1, out_backSel_6) node _out_rofireMux_T_27 = and(_out_rofireMux_T_26, UInt<1>(0h1)) connect out_rofireMux_out_6, UInt<1>(0h1) node _out_rofireMux_T_28 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_29 = or(out_rofireMux_out_6, _out_rofireMux_T_28) wire out_rofireMux_out_7 : UInt<1> node _out_rofireMux_T_30 = and(_out_rofireMux_T_1, out_backSel_7) node _out_rofireMux_T_31 = and(_out_rofireMux_T_30, UInt<1>(0h1)) connect out_rofireMux_out_7, UInt<1>(0h1) node _out_rofireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_33 = or(out_rofireMux_out_7, _out_rofireMux_T_32) wire out_rofireMux_out_8 : UInt<1> node _out_rofireMux_T_34 = and(_out_rofireMux_T_1, out_backSel_8) node _out_rofireMux_T_35 = and(_out_rofireMux_T_34, _out_T_7) connect out_rofireMux_out_8, UInt<1>(0h1) connect out_roready[9], _out_rofireMux_T_35 connect out_roready[8], _out_rofireMux_T_35 connect out_roready[7], _out_rofireMux_T_35 node _out_rofireMux_T_36 = eq(_out_T_7, UInt<1>(0h0)) node _out_rofireMux_T_37 = or(out_rofireMux_out_8, _out_rofireMux_T_36) wire out_rofireMux_out_9 : UInt<1> node _out_rofireMux_T_38 = and(_out_rofireMux_T_1, out_backSel_9) node _out_rofireMux_T_39 = and(_out_rofireMux_T_38, UInt<1>(0h1)) connect out_rofireMux_out_9, UInt<1>(0h1) node _out_rofireMux_T_40 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_41 = or(out_rofireMux_out_9, _out_rofireMux_T_40) wire out_rofireMux_out_10 : UInt<1> node _out_rofireMux_T_42 = and(_out_rofireMux_T_1, out_backSel_10) node _out_rofireMux_T_43 = and(_out_rofireMux_T_42, _out_T_5) connect out_rofireMux_out_10, UInt<1>(0h1) connect out_roready[6], _out_rofireMux_T_43 connect out_roready[5], _out_rofireMux_T_43 connect out_roready[4], _out_rofireMux_T_43 node _out_rofireMux_T_44 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_45 = or(out_rofireMux_out_10, _out_rofireMux_T_44) wire out_rofireMux_out_11 : UInt<1> node _out_rofireMux_T_46 = and(_out_rofireMux_T_1, out_backSel_11) node _out_rofireMux_T_47 = and(_out_rofireMux_T_46, UInt<1>(0h1)) connect out_rofireMux_out_11, UInt<1>(0h1) node _out_rofireMux_T_48 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_49 = or(out_rofireMux_out_11, _out_rofireMux_T_48) wire out_rofireMux_out_12 : UInt<1> node _out_rofireMux_T_50 = and(_out_rofireMux_T_1, out_backSel_12) node _out_rofireMux_T_51 = and(_out_rofireMux_T_50, UInt<1>(0h1)) connect out_rofireMux_out_12, UInt<1>(0h1) node _out_rofireMux_T_52 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_53 = or(out_rofireMux_out_12, _out_rofireMux_T_52) wire out_rofireMux_out_13 : UInt<1> node _out_rofireMux_T_54 = and(_out_rofireMux_T_1, out_backSel_13) node _out_rofireMux_T_55 = and(_out_rofireMux_T_54, UInt<1>(0h1)) connect out_rofireMux_out_13, UInt<1>(0h1) node _out_rofireMux_T_56 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_57 = or(out_rofireMux_out_13, _out_rofireMux_T_56) wire out_rofireMux_out_14 : UInt<1> node _out_rofireMux_T_58 = and(_out_rofireMux_T_1, out_backSel_14) node _out_rofireMux_T_59 = and(_out_rofireMux_T_58, UInt<1>(0h1)) connect out_rofireMux_out_14, UInt<1>(0h1) node _out_rofireMux_T_60 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_61 = or(out_rofireMux_out_14, _out_rofireMux_T_60) wire out_rofireMux_out_15 : UInt<1> node _out_rofireMux_T_62 = and(_out_rofireMux_T_1, out_backSel_15) node _out_rofireMux_T_63 = and(_out_rofireMux_T_62, UInt<1>(0h1)) connect out_rofireMux_out_15, UInt<1>(0h1) node _out_rofireMux_T_64 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_65 = or(out_rofireMux_out_15, _out_rofireMux_T_64) node _out_rofireMux_T_66 = geq(out_oindex, UInt<5>(0h10)) wire _out_rofireMux_WIRE : UInt<1>[16] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 connect _out_rofireMux_WIRE[4], _out_rofireMux_T_21 connect _out_rofireMux_WIRE[5], _out_rofireMux_T_25 connect _out_rofireMux_WIRE[6], _out_rofireMux_T_29 connect _out_rofireMux_WIRE[7], _out_rofireMux_T_33 connect _out_rofireMux_WIRE[8], _out_rofireMux_T_37 connect _out_rofireMux_WIRE[9], _out_rofireMux_T_41 connect _out_rofireMux_WIRE[10], _out_rofireMux_T_45 connect _out_rofireMux_WIRE[11], _out_rofireMux_T_49 connect _out_rofireMux_WIRE[12], _out_rofireMux_T_53 connect _out_rofireMux_WIRE[13], _out_rofireMux_T_57 connect _out_rofireMux_WIRE[14], _out_rofireMux_T_61 connect _out_rofireMux_WIRE[15], _out_rofireMux_T_65 node out_rofireMux = mux(_out_rofireMux_T_66, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_11) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[12], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_11, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, UInt<1>(0h1)) connect out_wofireMux_out_1, UInt<1>(0h1) node _out_wofireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_3) connect out_wofireMux_out_2, UInt<1>(0h1) connect out_woready[3], _out_wofireMux_T_12 connect out_woready[2], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, UInt<1>(0h1)) connect out_wofireMux_out_3, UInt<1>(0h1) node _out_wofireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) wire out_wofireMux_out_4 : UInt<1> node _out_wofireMux_T_19 = and(_out_wofireMux_T_2, out_backSel_4) node _out_wofireMux_T_20 = and(_out_wofireMux_T_19, _out_T_9) connect out_wofireMux_out_4, UInt<1>(0h1) connect out_woready[11], _out_wofireMux_T_20 connect out_woready[10], _out_wofireMux_T_20 node _out_wofireMux_T_21 = eq(_out_T_9, UInt<1>(0h0)) node _out_wofireMux_T_22 = or(out_wofireMux_out_4, _out_wofireMux_T_21) wire out_wofireMux_out_5 : UInt<1> node _out_wofireMux_T_23 = and(_out_wofireMux_T_2, out_backSel_5) node _out_wofireMux_T_24 = and(_out_wofireMux_T_23, _out_T_1) connect out_wofireMux_out_5, UInt<1>(0h1) connect out_woready[1], _out_wofireMux_T_24 connect out_woready[0], _out_wofireMux_T_24 node _out_wofireMux_T_25 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_26 = or(out_wofireMux_out_5, _out_wofireMux_T_25) wire out_wofireMux_out_6 : UInt<1> node _out_wofireMux_T_27 = and(_out_wofireMux_T_2, out_backSel_6) node _out_wofireMux_T_28 = and(_out_wofireMux_T_27, UInt<1>(0h1)) connect out_wofireMux_out_6, UInt<1>(0h1) node _out_wofireMux_T_29 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_30 = or(out_wofireMux_out_6, _out_wofireMux_T_29) wire out_wofireMux_out_7 : UInt<1> node _out_wofireMux_T_31 = and(_out_wofireMux_T_2, out_backSel_7) node _out_wofireMux_T_32 = and(_out_wofireMux_T_31, UInt<1>(0h1)) connect out_wofireMux_out_7, UInt<1>(0h1) node _out_wofireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_34 = or(out_wofireMux_out_7, _out_wofireMux_T_33) wire out_wofireMux_out_8 : UInt<1> node _out_wofireMux_T_35 = and(_out_wofireMux_T_2, out_backSel_8) node _out_wofireMux_T_36 = and(_out_wofireMux_T_35, _out_T_7) connect out_wofireMux_out_8, UInt<1>(0h1) connect out_woready[9], _out_wofireMux_T_36 connect out_woready[8], _out_wofireMux_T_36 connect out_woready[7], _out_wofireMux_T_36 node _out_wofireMux_T_37 = eq(_out_T_7, UInt<1>(0h0)) node _out_wofireMux_T_38 = or(out_wofireMux_out_8, _out_wofireMux_T_37) wire out_wofireMux_out_9 : UInt<1> node _out_wofireMux_T_39 = and(_out_wofireMux_T_2, out_backSel_9) node _out_wofireMux_T_40 = and(_out_wofireMux_T_39, UInt<1>(0h1)) connect out_wofireMux_out_9, UInt<1>(0h1) node _out_wofireMux_T_41 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_42 = or(out_wofireMux_out_9, _out_wofireMux_T_41) wire out_wofireMux_out_10 : UInt<1> node _out_wofireMux_T_43 = and(_out_wofireMux_T_2, out_backSel_10) node _out_wofireMux_T_44 = and(_out_wofireMux_T_43, _out_T_5) connect out_wofireMux_out_10, UInt<1>(0h1) connect out_woready[6], _out_wofireMux_T_44 connect out_woready[5], _out_wofireMux_T_44 connect out_woready[4], _out_wofireMux_T_44 node _out_wofireMux_T_45 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_46 = or(out_wofireMux_out_10, _out_wofireMux_T_45) wire out_wofireMux_out_11 : UInt<1> node _out_wofireMux_T_47 = and(_out_wofireMux_T_2, out_backSel_11) node _out_wofireMux_T_48 = and(_out_wofireMux_T_47, UInt<1>(0h1)) connect out_wofireMux_out_11, UInt<1>(0h1) node _out_wofireMux_T_49 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_50 = or(out_wofireMux_out_11, _out_wofireMux_T_49) wire out_wofireMux_out_12 : UInt<1> node _out_wofireMux_T_51 = and(_out_wofireMux_T_2, out_backSel_12) node _out_wofireMux_T_52 = and(_out_wofireMux_T_51, UInt<1>(0h1)) connect out_wofireMux_out_12, UInt<1>(0h1) node _out_wofireMux_T_53 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_54 = or(out_wofireMux_out_12, _out_wofireMux_T_53) wire out_wofireMux_out_13 : UInt<1> node _out_wofireMux_T_55 = and(_out_wofireMux_T_2, out_backSel_13) node _out_wofireMux_T_56 = and(_out_wofireMux_T_55, UInt<1>(0h1)) connect out_wofireMux_out_13, UInt<1>(0h1) node _out_wofireMux_T_57 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_58 = or(out_wofireMux_out_13, _out_wofireMux_T_57) wire out_wofireMux_out_14 : UInt<1> node _out_wofireMux_T_59 = and(_out_wofireMux_T_2, out_backSel_14) node _out_wofireMux_T_60 = and(_out_wofireMux_T_59, UInt<1>(0h1)) connect out_wofireMux_out_14, UInt<1>(0h1) node _out_wofireMux_T_61 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_62 = or(out_wofireMux_out_14, _out_wofireMux_T_61) wire out_wofireMux_out_15 : UInt<1> node _out_wofireMux_T_63 = and(_out_wofireMux_T_2, out_backSel_15) node _out_wofireMux_T_64 = and(_out_wofireMux_T_63, UInt<1>(0h1)) connect out_wofireMux_out_15, UInt<1>(0h1) node _out_wofireMux_T_65 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_66 = or(out_wofireMux_out_15, _out_wofireMux_T_65) node _out_wofireMux_T_67 = geq(out_oindex, UInt<5>(0h10)) wire _out_wofireMux_WIRE : UInt<1>[16] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 connect _out_wofireMux_WIRE[4], _out_wofireMux_T_22 connect _out_wofireMux_WIRE[5], _out_wofireMux_T_26 connect _out_wofireMux_WIRE[6], _out_wofireMux_T_30 connect _out_wofireMux_WIRE[7], _out_wofireMux_T_34 connect _out_wofireMux_WIRE[8], _out_wofireMux_T_38 connect _out_wofireMux_WIRE[9], _out_wofireMux_T_42 connect _out_wofireMux_WIRE[10], _out_wofireMux_T_46 connect _out_wofireMux_WIRE[11], _out_wofireMux_T_50 connect _out_wofireMux_WIRE[12], _out_wofireMux_T_54 connect _out_wofireMux_WIRE[13], _out_wofireMux_T_58 connect _out_wofireMux_WIRE[14], _out_wofireMux_T_62 connect _out_wofireMux_WIRE[15], _out_wofireMux_T_66 node out_wofireMux = mux(_out_wofireMux_T_67, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_q_io_deq_ready_T = and(out.ready, out_oready) connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_back_front_q.io.deq.bits.read wire out_out_bits_data_out : UInt<1> connect out_out_bits_data_out, UInt<1>(0h1) node _out_out_bits_data_T = eq(UInt<1>(0h0), out_oindex) when _out_out_bits_data_T : connect out_out_bits_data_out, _out_T_11 else : node _out_out_bits_data_T_1 = eq(UInt<2>(0h2), out_oindex) when _out_out_bits_data_T_1 : connect out_out_bits_data_out, _out_T_3 else : node _out_out_bits_data_T_2 = eq(UInt<3>(0h4), out_oindex) when _out_out_bits_data_T_2 : connect out_out_bits_data_out, _out_T_9 else : node _out_out_bits_data_T_3 = eq(UInt<3>(0h5), out_oindex) when _out_out_bits_data_T_3 : connect out_out_bits_data_out, _out_T_1 else : node _out_out_bits_data_T_4 = eq(UInt<4>(0h8), out_oindex) when _out_out_bits_data_T_4 : connect out_out_bits_data_out, _out_T_7 else : node _out_out_bits_data_T_5 = eq(UInt<4>(0ha), out_oindex) when _out_out_bits_data_T_5 : connect out_out_bits_data_out, _out_T_5 wire out_out_bits_data_out_1 : UInt connect out_out_bits_data_out_1, UInt<1>(0h0) node _out_out_bits_data_T_6 = eq(UInt<1>(0h0), out_oindex) when _out_out_bits_data_T_6 : connect out_out_bits_data_out_1, _out_T_152 else : node _out_out_bits_data_T_7 = eq(UInt<2>(0h2), out_oindex) when _out_out_bits_data_T_7 : connect out_out_bits_data_out_1, _out_T_49 else : node _out_out_bits_data_T_8 = eq(UInt<3>(0h4), out_oindex) when _out_out_bits_data_T_8 : connect out_out_bits_data_out_1, _out_T_141 else : node _out_out_bits_data_T_9 = eq(UInt<3>(0h5), out_oindex) when _out_out_bits_data_T_9 : connect out_out_bits_data_out_1, _out_T_31 else : node _out_out_bits_data_T_10 = eq(UInt<4>(0h8), out_oindex) when _out_out_bits_data_T_10 : connect out_out_bits_data_out_1, _out_T_121 else : node _out_out_bits_data_T_11 = eq(UInt<4>(0ha), out_oindex) when _out_out_bits_data_T_11 : connect out_out_bits_data_out_1, _out_T_85 node _out_out_bits_data_T_12 = mux(out_out_bits_data_out, out_out_bits_data_out_1, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_12 connect out.bits.extra, out_back_front_q.io.deq.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)
module TLPLIC( // @[Plic.scala:132:9] input clock, // @[Plic.scala:132:9] input reset, // @[Plic.scala:132:9] input auto_int_in_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_0_0, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [22:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [22:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire _fanin_1_io_dev; // @[Plic.scala:189:27] wire _fanin_1_io_max; // @[Plic.scala:189:27] wire _fanin_io_dev; // @[Plic.scala:189:27] wire _fanin_io_max; // @[Plic.scala:189:27] wire _gateways_gateway_io_plic_valid; // @[Plic.scala:160:27] wire auto_int_in_0_0 = auto_int_in_0; // @[Plic.scala:132:9] wire auto_in_a_valid_0 = auto_in_a_valid; // @[Plic.scala:132:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Plic.scala:132:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Plic.scala:132:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Plic.scala:132:9] wire [11:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Plic.scala:132:9] wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Plic.scala:132:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Plic.scala:132:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Plic.scala:132:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Plic.scala:132:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Plic.scala:132:9] wire _out_T_73 = reset; // @[Plic.scala:298:19] wire _out_T_109 = reset; // @[Plic.scala:298:19] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Plic.scala:132:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[Plic.scala:132:9] wire auto_in_d_bits_denied = 1'h0; // @[Plic.scala:132:9] wire auto_in_d_bits_corrupt = 1'h0; // @[Plic.scala:132:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _pending_WIRE_0 = 1'h0; // @[Plic.scala:172:55] wire _out_T_19 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_20 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_39 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_40 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_130 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_6 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_40 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_48 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_66 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_41 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_49 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_67 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_40 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_48 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_66 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_41 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_49 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_67 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [31:0] _out_prepend_T_7 = 32'h0; // @[RegisterRouter.scala:87:24] wire [22:0] out_maskMatch = 23'h7BF9EF; // @[RegisterRouter.scala:87:24] wire intnodeIn_0 = auto_int_in_0_0; // @[Plic.scala:132:9] wire x1_intnodeOut_0; // @[MixedNode.scala:542:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Plic.scala:132:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Plic.scala:132:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Plic.scala:132:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Plic.scala:132:9] wire [11:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Plic.scala:132:9] wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Plic.scala:132:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Plic.scala:132:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Plic.scala:132:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Plic.scala:132:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Plic.scala:132:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_1_0_0; // @[Plic.scala:132:9] wire auto_int_out_0_0_0; // @[Plic.scala:132:9] wire auto_in_a_ready_0; // @[Plic.scala:132:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Plic.scala:132:9] wire [1:0] auto_in_d_bits_size_0; // @[Plic.scala:132:9] wire [11:0] auto_in_d_bits_source_0; // @[Plic.scala:132:9] wire [63:0] auto_in_d_bits_data_0; // @[Plic.scala:132:9] wire auto_in_d_valid_0; // @[Plic.scala:132:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Plic.scala:132:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Plic.scala:132:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Plic.scala:132:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Plic.scala:132:9] wire [11:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Plic.scala:132:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Plic.scala:132:9] wire _intnodeOut_0_T; // @[Plic.scala:193:60] assign auto_int_out_0_0_0 = intnodeOut_0; // @[Plic.scala:132:9] wire _intnodeOut_0_T_1; // @[Plic.scala:193:60] assign auto_int_out_1_0_0 = x1_intnodeOut_0; // @[Plic.scala:132:9] reg priority_0; // @[Plic.scala:167:31] reg threshold_0; // @[Plic.scala:170:31] wire _out_T_95 = threshold_0; // @[RegisterRouter.scala:87:24] reg threshold_1; // @[Plic.scala:170:31] wire _out_T_59 = threshold_1; // @[RegisterRouter.scala:87:24] reg pending_0; // @[Plic.scala:172:26] reg enables_0_0; // @[Plic.scala:178:26] wire enableVec_0 = enables_0_0; // @[Plic.scala:178:26, :182:28] reg enables_1_0; // @[Plic.scala:178:26] wire enableVec_1 = enables_1_0; // @[Plic.scala:178:26, :182:28] wire [1:0] _enableVec0_T = {enableVec_0, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [1:0] enableVec0_0 = _enableVec0_T; // @[Plic.scala:183:{29,52}] wire [1:0] _enableVec0_T_1 = {enableVec_1, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [1:0] enableVec0_1 = _enableVec0_T_1; // @[Plic.scala:183:{29,52}] reg maxDevs_0; // @[Plic.scala:185:22] reg maxDevs_1; // @[Plic.scala:185:22] wire _fanin_io_ip_T = enableVec_0 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40] reg intnodeOut_0_REG; // @[Plic.scala:193:45] assign _intnodeOut_0_T = intnodeOut_0_REG > threshold_0; // @[Plic.scala:170:31, :193:{45,60}] assign intnodeOut_0 = _intnodeOut_0_T; // @[Plic.scala:193:60] wire _fanin_io_ip_T_1 = enableVec_1 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40] reg intnodeOut_0_REG_1; // @[Plic.scala:193:45] assign _intnodeOut_0_T_1 = intnodeOut_0_REG_1 > threshold_1; // @[Plic.scala:170:31, :193:{45,60}] assign x1_intnodeOut_0 = _intnodeOut_0_T_1; // @[Plic.scala:193:60] wire out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_6; // @[RegisterRouter.scala:87:24] wire claimer_0; // @[Plic.scala:250:23] wire claimer_1; // @[Plic.scala:250:23] wire _claiming_T = claimer_0 & maxDevs_0; // @[Plic.scala:185:22, :250:23, :252:49] wire _claiming_T_1 = claimer_1 & maxDevs_1; // @[Plic.scala:185:22, :250:23, :252:49] wire claiming = _claiming_T | _claiming_T_1; // @[Plic.scala:252:{49,92}] wire claimedDevs_shiftAmount = claiming; // @[OneHot.scala:64:49] wire [1:0] _claimedDevs_T = 2'h1 << claimedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _claimedDevs_T_1 = _claimedDevs_T; // @[OneHot.scala:65:{12,27}] wire _claimedDevs_T_2 = _claimedDevs_T_1[0]; // @[OneHot.scala:65:27] wire claimedDevs_0 = _claimedDevs_T_2; // @[Plic.scala:253:{30,62}] wire _claimedDevs_T_3 = _claimedDevs_T_1[1]; // @[OneHot.scala:65:27] wire claimedDevs_1 = _claimedDevs_T_3; // @[Plic.scala:253:{30,62}] wire _gateway_io_plic_ready_T = ~pending_0; // @[Plic.scala:172:26, :256:18] wire _pending_0_T = ~claimedDevs_1; // @[Plic.scala:253:30, :257:34] wire _out_completer_0_T_2; // @[Plic.scala:301:35] wire _out_completer_1_T_2; // @[Plic.scala:301:35] wire completer_0; // @[Plic.scala:267:25] wire completer_1; // @[Plic.scala:267:25] wire _out_completerDev_T_1; // @[package.scala:163:13] wire completerDev; // @[Plic.scala:269:28] wire completedDevs_shiftAmount = completerDev; // @[OneHot.scala:64:49] wire _completedDevs_T = completer_0 | completer_1; // @[Plic.scala:267:25, :270:48] wire [1:0] _completedDevs_T_1 = 2'h1 << completedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _completedDevs_T_2 = _completedDevs_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] completedDevs = _completedDevs_T ? _completedDevs_T_2 : 2'h0; // @[OneHot.scala:65:27] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [22:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [24:0] _in_bits_index_T = nodeIn_a_bits_address[27:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[22:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_q_io_deq_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_12; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [22:0] out_findex = out_front_bits_index & 23'h7BF9EF; // @[RegisterRouter.scala:87:24] wire [22:0] out_bindex = _out_back_front_q_io_deq_bits_index & 23'h7BF9EF; // @[RegisterRouter.scala:87:24] wire _GEN = out_findex == 23'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_8; // @[RegisterRouter.scala:87:24] assign _out_T_8 = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_10; // @[RegisterRouter.scala:87:24] assign _out_T_10 = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_bindex == 23'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_9; // @[RegisterRouter.scala:87:24] assign _out_T_9 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_11; // @[RegisterRouter.scala:87:24] assign _out_T_11 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_2 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_2 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_4 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_4 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_7 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_7 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_10 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_10 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_2 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_2 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_4 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_4 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_7 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_7 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_10 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_10 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_32 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_50 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_86 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_122 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_15 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_1 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_1 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_3 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_3 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_11 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_11 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = _out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = _out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire _out_romask_T_1 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_1 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_3 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_3 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_11 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_11 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = _out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = _out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_24 = out_f_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_T_25 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_41 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_131 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_26 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_28 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_29 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend = {enables_1_0, 1'h0}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_30 = out_prepend; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_31 = _out_T_30; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_33 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_35 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_36 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_37 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = _out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = _out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire out_romask_3 = _out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = _out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_42 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_43 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire _out_T_44 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_46 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_1 = {pending_0, 1'h0}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_48 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_49 = _out_T_48; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = _out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = _out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = _out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = _out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_53 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_54 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_57 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_58 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_60 = _out_T_59; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_2 = _out_T_60; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_5 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_5 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_8 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_8 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_5 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_5 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_8 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_8 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_61 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_97 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_2 = {1'h0, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_68 = {30'h0, out_prepend_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_69 = _out_T_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_3 = _out_T_69; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_6 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_6 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_9 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_9 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_6 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_6 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_9 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_9 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_76 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] assign claimer_1 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire _out_T_77 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_79 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_70 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_106 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire _out_T_71 = _out_T_70[0]; // @[package.scala:163:13] wire _out_completerDev_T = _out_T_70[0]; // @[package.scala:163:13] wire _out_T_72 = completerDev == _out_T_71; // @[package.scala:163:13] wire _out_T_74 = ~_out_T_73; // @[Plic.scala:298:19] wire _out_T_75 = ~_out_T_72; // @[Plic.scala:298:{19,33}] wire [1:0] _GEN_1 = {1'h0, completerDev}; // @[Plic.scala:269:28, :301:51] wire [1:0] _out_completer_1_T = enableVec0_1 >> _GEN_1; // @[Plic.scala:183:29, :301:51] wire _out_completer_1_T_1 = _out_completer_1_T[0]; // @[Plic.scala:301:51] assign _out_completer_1_T_2 = out_f_woready_6 & _out_completer_1_T_1; // @[RegisterRouter.scala:87:24] assign completer_1 = _out_completer_1_T_2; // @[Plic.scala:267:25, :301:35] wire _out_T_80 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_81 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_82 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_83 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_3 = {maxDevs_1, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_84 = {31'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_85 = _out_T_84; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_87 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] wire _out_T_90 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_91 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_92 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_93 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_94 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire _out_T_96 = _out_T_95; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_4 = _out_T_96; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_98 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_101 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_102 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_103 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_4 = {1'h0, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_104 = {30'h0, out_prepend_4}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_105 = _out_T_104; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_5 = _out_T_105; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = |_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire out_romask_9 = |_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_112 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] assign claimer_0 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire _out_T_113 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_114 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_107 = _out_T_106[0]; // @[package.scala:163:13] assign _out_completerDev_T_1 = _out_T_106[0]; // @[package.scala:163:13] wire _out_T_108 = completerDev == _out_T_107; // @[package.scala:163:13] wire _out_T_110 = ~_out_T_109; // @[Plic.scala:298:19] wire _out_T_111 = ~_out_T_108; // @[Plic.scala:298:{19,33}]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_18 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_25 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_18( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_25 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_155 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_155( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule